drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_58802 0xd802
  74 #define BROADCOM_DEV_ID_58804 0xd804
  75 #define BROADCOM_DEV_ID_58808 0x16f0
  76
  77 static const struct rte_pci_id bnxt_pci_id_map[] = {
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  79                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 119         { .vendor_id = 0, /* sentinel */ },
 120 };
 121
 122 #define BNXT_ETH_RSS_SUPPORT (  \
 123         ETH_RSS_IPV4 |          \
 124         ETH_RSS_NONFRAG_IPV4_TCP |      \
 125         ETH_RSS_NONFRAG_IPV4_UDP |      \
 126         ETH_RSS_IPV6 |          \
 127         ETH_RSS_NONFRAG_IPV6_TCP |      \
 128         ETH_RSS_NONFRAG_IPV6_UDP)
 129
 130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 131                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 132                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 133                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 134                                      DEV_TX_OFFLOAD_TCP_TSO | \
 135                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 136                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 137                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 138                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 139                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 141
 142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 143                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 144                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 146                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 149                                      DEV_RX_OFFLOAD_CRC_STRIP | \
 150                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 151                                      DEV_RX_OFFLOAD_TCP_LRO)
 152
 153 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 154 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 155 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 156 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 157
 158 /***********************/
 159
 160 /*
 161  * High level utility functions
 162  */
 163
 164 static void bnxt_free_mem(struct bnxt *bp)
 165 {
 166         bnxt_free_filter_mem(bp);
 167         bnxt_free_vnic_attributes(bp);
 168         bnxt_free_vnic_mem(bp);
 169
 170         bnxt_free_stats(bp);
 171         bnxt_free_tx_rings(bp);
 172         bnxt_free_rx_rings(bp);
 173 }
 174
 175 static int bnxt_alloc_mem(struct bnxt *bp)
 176 {
 177         int rc;
 178
 179         rc = bnxt_alloc_vnic_mem(bp);
 180         if (rc)
 181                 goto alloc_mem_err;
 182
 183         rc = bnxt_alloc_vnic_attributes(bp);
 184         if (rc)
 185                 goto alloc_mem_err;
 186
 187         rc = bnxt_alloc_filter_mem(bp);
 188         if (rc)
 189                 goto alloc_mem_err;
 190
 191         return 0;
 192
 193 alloc_mem_err:
 194         bnxt_free_mem(bp);
 195         return rc;
 196 }
 197
 198 static int bnxt_init_chip(struct bnxt *bp)
 199 {
 200         unsigned int i;
 201         struct rte_eth_link new;
 202         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 203         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 204         uint32_t intr_vector = 0;
 205         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 206         uint32_t vec = BNXT_MISC_VEC_ID;
 207         int rc;
 208
 209         /* disable uio/vfio intr/eventfd mapping */
 210         rte_intr_disable(intr_handle);
 211
 212         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 213                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 214                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 215                 bp->flags |= BNXT_FLAG_JUMBO;
 216         } else {
 217                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 218                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 219                 bp->flags &= ~BNXT_FLAG_JUMBO;
 220         }
 221
 222         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 223         if (rc) {
 224                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 225                 goto err_out;
 226         }
 227
 228         rc = bnxt_alloc_hwrm_rings(bp);
 229         if (rc) {
 230                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 231                 goto err_out;
 232         }
 233
 234         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 235         if (rc) {
 236                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 237                 goto err_out;
 238         }
 239
 240         rc = bnxt_mq_rx_configure(bp);
 241         if (rc) {
 242                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 243                 goto err_out;
 244         }
 245
 246         /* VNIC configuration */
 247         for (i = 0; i < bp->nr_vnics; i++) {
 248                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 249
 250                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 251                 if (rc) {
 252                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 253                                 i, rc);
 254                         goto err_out;
 255                 }
 256
 257                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 258                 if (rc) {
 259                         PMD_DRV_LOG(ERR,
 260                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 261                                 i, rc);
 262                         goto err_out;
 263                 }
 264
 265                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 266                 if (rc) {
 267                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 268                                 i, rc);
 269                         goto err_out;
 270                 }
 271
 272                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 273                 if (rc) {
 274                         PMD_DRV_LOG(ERR,
 275                                 "HWRM vnic %d filter failure rc: %x\n",
 276                                 i, rc);
 277                         goto err_out;
 278                 }
 279
 280                 rc = bnxt_vnic_rss_configure(bp, vnic);
 281                 if (rc) {
 282                         PMD_DRV_LOG(ERR,
 283                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 284                         goto err_out;
 285                 }
 286
 287                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 288
 289                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 290                     DEV_RX_OFFLOAD_TCP_LRO)
 291                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 292                 else
 293                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 294         }
 295         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 296         if (rc) {
 297                 PMD_DRV_LOG(ERR,
 298                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 299                 goto err_out;
 300         }
 301
 302         /* check and configure queue intr-vector mapping */
 303         if ((rte_intr_cap_multiple(intr_handle) ||
 304              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 305             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 306                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 307                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 308                 if (intr_vector > bp->rx_cp_nr_rings) {
 309                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 310                                         bp->rx_cp_nr_rings);
 311                         return -ENOTSUP;
 312                 }
 313                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 314                         return -1;
 315         }
 316
 317         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 318                 intr_handle->intr_vec =
 319                         rte_zmalloc("intr_vec",
 320                                     bp->eth_dev->data->nb_rx_queues *
 321                                     sizeof(int), 0);
 322                 if (intr_handle->intr_vec == NULL) {
 323                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 324                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 325                         return -ENOMEM;
 326                 }
 327                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 328                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 329                          intr_handle->intr_vec, intr_handle->nb_efd,
 330                         intr_handle->max_intr);
 331         }
 332
 333         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 334              queue_id++) {
 335                 intr_handle->intr_vec[queue_id] = vec;
 336                 if (vec < base + intr_handle->nb_efd - 1)
 337                         vec++;
 338         }
 339
 340         /* enable uio/vfio intr/eventfd mapping */
 341         rte_intr_enable(intr_handle);
 342
 343         rc = bnxt_get_hwrm_link_config(bp, &new);
 344         if (rc) {
 345                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 346                 goto err_out;
 347         }
 348
 349         if (!bp->link_info.link_up) {
 350                 rc = bnxt_set_hwrm_link_config(bp, true);
 351                 if (rc) {
 352                         PMD_DRV_LOG(ERR,
 353                                 "HWRM link config failure rc: %x\n", rc);
 354                         goto err_out;
 355                 }
 356         }
 357         bnxt_print_link_info(bp->eth_dev);
 358
 359         return 0;
 360
 361 err_out:
 362         bnxt_free_all_hwrm_resources(bp);
 363
 364         /* Some of the error status returned by FW may not be from errno.h */
 365         if (rc > 0)
 366                 rc = -EIO;
 367
 368         return rc;
 369 }
 370
 371 static int bnxt_shutdown_nic(struct bnxt *bp)
 372 {
 373         bnxt_free_all_hwrm_resources(bp);
 374         bnxt_free_all_filters(bp);
 375         bnxt_free_all_vnics(bp);
 376         return 0;
 377 }
 378
 379 static int bnxt_init_nic(struct bnxt *bp)
 380 {
 381         int rc;
 382
 383         rc = bnxt_init_ring_grps(bp);
 384         if (rc)
 385                 return rc;
 386
 387         bnxt_init_vnics(bp);
 388         bnxt_init_filters(bp);
 389
 390         return 0;
 391 }
 392
 393 /*
 394  * Device configuration and status function
 395  */
 396
 397 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 398                                   struct rte_eth_dev_info *dev_info)
 399 {
 400         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 401         uint16_t max_vnics, i, j, vpool, vrxq;
 402         unsigned int max_rx_rings;
 403
 404         /* MAC Specifics */
 405         dev_info->max_mac_addrs = bp->max_l2_ctx;
 406         dev_info->max_hash_mac_addrs = 0;
 407
 408         /* PF/VF specifics */
 409         if (BNXT_PF(bp))
 410                 dev_info->max_vfs = bp->pdev->max_vfs;
 411         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 412         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 413         dev_info->max_rx_queues = max_rx_rings;
 414         dev_info->max_tx_queues = max_rx_rings;
 415         dev_info->reta_size = bp->max_rsscos_ctx;
 416         dev_info->hash_key_size = 40;
 417         max_vnics = bp->max_vnics;
 418
 419         /* Fast path specifics */
 420         dev_info->min_rx_bufsize = 1;
 421         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 422                                   + VLAN_TAG_SIZE;
 423
 424         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 425         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 426                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 427         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 428         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 429
 430         /* *INDENT-OFF* */
 431         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 432                 .rx_thresh = {
 433                         .pthresh = 8,
 434                         .hthresh = 8,
 435                         .wthresh = 0,
 436                 },
 437                 .rx_free_thresh = 32,
 438                 /* If no descriptors available, pkts are dropped by default */
 439                 .rx_drop_en = 1,
 440         };
 441
 442         dev_info->default_txconf = (struct rte_eth_txconf) {
 443                 .tx_thresh = {
 444                         .pthresh = 32,
 445                         .hthresh = 0,
 446                         .wthresh = 0,
 447                 },
 448                 .tx_free_thresh = 32,
 449                 .tx_rs_thresh = 32,
 450         };
 451         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 452
 453         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 454         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 455         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 456         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 457         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 458
 459         /* *INDENT-ON* */
 460
 461         /*
 462          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 463          *       need further investigation.
 464          */
 465
 466         /* VMDq resources */
 467         vpool = 64; /* ETH_64_POOLS */
 468         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 469         for (i = 0; i < 4; vpool >>= 1, i++) {
 470                 if (max_vnics > vpool) {
 471                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 472                                 if (dev_info->max_rx_queues > vrxq) {
 473                                         if (vpool > vrxq)
 474                                                 vpool = vrxq;
 475                                         goto found;
 476                                 }
 477                         }
 478                         /* Not enough resources to support VMDq */
 479                         break;
 480                 }
 481         }
 482         /* Not enough resources to support VMDq */
 483         vpool = 0;
 484         vrxq = 0;
 485 found:
 486         dev_info->max_vmdq_pools = vpool;
 487         dev_info->vmdq_queue_num = vrxq;
 488
 489         dev_info->vmdq_pool_base = 0;
 490         dev_info->vmdq_queue_base = 0;
 491 }
 492
 493 /* Configure the device based on the configuration provided */
 494 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 495 {
 496         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 497         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 498
 499         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 500         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 501         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 502         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 503
 504         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 505                 int rc;
 506
 507                 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
 508                 if (rc) {
 509                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 510                         return -ENOSPC;
 511                 }
 512
 513                 /* legacy driver needs to get updated values */
 514                 rc = bnxt_hwrm_func_qcaps(bp);
 515                 if (rc) {
 516                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 517                         return -ENOSPC;
 518                 }
 519         }
 520
 521         /* Inherit new configurations */
 522         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 523             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 524             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 525             bp->max_cp_rings ||
 526             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 527             bp->max_stat_ctx ||
 528             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
 529                 PMD_DRV_LOG(ERR,
 530                         "Insufficient resources to support requested config\n");
 531                 PMD_DRV_LOG(ERR,
 532                         "Num Queues Requested: Tx %d, Rx %d\n",
 533                         eth_dev->data->nb_tx_queues,
 534                         eth_dev->data->nb_rx_queues);
 535                 PMD_DRV_LOG(ERR,
 536                         "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
 537                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 538                         bp->max_stat_ctx, bp->max_ring_grps);
 539                 return -ENOSPC;
 540         }
 541
 542         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 543         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 544
 545         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 546                 eth_dev->data->mtu =
 547                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 548                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
 549                                 BNXT_NUM_VLANS;
 550                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 551         }
 552         return 0;
 553 }
 554
 555 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 556 {
 557         struct rte_eth_link *link = &eth_dev->data->dev_link;
 558
 559         if (link->link_status)
 560                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 561                         eth_dev->data->port_id,
 562                         (uint32_t)link->link_speed,
 563                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 564                         ("full-duplex") : ("half-duplex\n"));
 565         else
 566                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 567                         eth_dev->data->port_id);
 568 }
 569
 570 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 571 {
 572         bnxt_print_link_info(eth_dev);
 573         return 0;
 574 }
 575
 576 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 577 {
 578         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 579         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 580         int vlan_mask = 0;
 581         int rc;
 582
 583         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 584                 PMD_DRV_LOG(ERR,
 585                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 586                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 587         }
 588         bp->dev_stopped = 0;
 589
 590         rc = bnxt_init_chip(bp);
 591         if (rc)
 592                 goto error;
 593
 594         bnxt_link_update_op(eth_dev, 1);
 595
 596         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 597                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 598         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 599                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 600         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 601         if (rc)
 602                 goto error;
 603
 604         bp->flags |= BNXT_FLAG_INIT_DONE;
 605         return 0;
 606
 607 error:
 608         bnxt_shutdown_nic(bp);
 609         bnxt_free_tx_mbufs(bp);
 610         bnxt_free_rx_mbufs(bp);
 611         return rc;
 612 }
 613
 614 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 615 {
 616         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 617         int rc = 0;
 618
 619         if (!bp->link_info.link_up)
 620                 rc = bnxt_set_hwrm_link_config(bp, true);
 621         if (!rc)
 622                 eth_dev->data->dev_link.link_status = 1;
 623
 624         bnxt_print_link_info(eth_dev);
 625         return 0;
 626 }
 627
 628 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 629 {
 630         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 631
 632         eth_dev->data->dev_link.link_status = 0;
 633         bnxt_set_hwrm_link_config(bp, false);
 634         bp->link_info.link_up = 0;
 635
 636         return 0;
 637 }
 638
 639 /* Unload the driver, release resources */
 640 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 641 {
 642         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 643
 644         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 645         if (bp->eth_dev->data->dev_started) {
 646                 /* TBD: STOP HW queues DMA */
 647                 eth_dev->data->dev_link.link_status = 0;
 648         }
 649         bnxt_set_hwrm_link_config(bp, false);
 650         bnxt_hwrm_port_clr_stats(bp);
 651         bnxt_free_tx_mbufs(bp);
 652         bnxt_free_rx_mbufs(bp);
 653         bnxt_shutdown_nic(bp);
 654         bp->dev_stopped = 1;
 655 }
 656
 657 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 658 {
 659         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 660
 661         if (bp->dev_stopped == 0)
 662                 bnxt_dev_stop_op(eth_dev);
 663
 664         bnxt_free_mem(bp);
 665         if (eth_dev->data->mac_addrs != NULL) {
 666                 rte_free(eth_dev->data->mac_addrs);
 667                 eth_dev->data->mac_addrs = NULL;
 668         }
 669         if (bp->grp_info != NULL) {
 670                 rte_free(bp->grp_info);
 671                 bp->grp_info = NULL;
 672         }
 673
 674         bnxt_dev_uninit(eth_dev);
 675 }
 676
 677 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 678                                     uint32_t index)
 679 {
 680         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 681         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 682         struct bnxt_vnic_info *vnic;
 683         struct bnxt_filter_info *filter, *temp_filter;
 684         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 685         uint32_t i;
 686
 687         /*
 688          * Loop through all VNICs from the specified filter flow pools to
 689          * remove the corresponding MAC addr filter
 690          */
 691         for (i = 0; i < pool; i++) {
 692                 if (!(pool_mask & (1ULL << i)))
 693                         continue;
 694
 695                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 696                         filter = STAILQ_FIRST(&vnic->filter);
 697                         while (filter) {
 698                                 temp_filter = STAILQ_NEXT(filter, next);
 699                                 if (filter->mac_index == index) {
 700                                         STAILQ_REMOVE(&vnic->filter, filter,
 701                                                       bnxt_filter_info, next);
 702                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 703                                         filter->mac_index = INVALID_MAC_INDEX;
 704                                         memset(&filter->l2_addr, 0,
 705                                                ETHER_ADDR_LEN);
 706                                         STAILQ_INSERT_TAIL(
 707                                                         &bp->free_filter_list,
 708                                                         filter, next);
 709                                 }
 710                                 filter = temp_filter;
 711                         }
 712                 }
 713         }
 714 }
 715
 716 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 717                                 struct ether_addr *mac_addr,
 718                                 uint32_t index, uint32_t pool)
 719 {
 720         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 721         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 722         struct bnxt_filter_info *filter;
 723
 724         if (BNXT_VF(bp)) {
 725                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 726                 return -ENOTSUP;
 727         }
 728
 729         if (!vnic) {
 730                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 731                 return -EINVAL;
 732         }
 733         /* Attach requested MAC address to the new l2_filter */
 734         STAILQ_FOREACH(filter, &vnic->filter, next) {
 735                 if (filter->mac_index == index) {
 736                         PMD_DRV_LOG(ERR,
 737                                 "MAC addr already existed for pool %d\n", pool);
 738                         return 0;
 739                 }
 740         }
 741         filter = bnxt_alloc_filter(bp);
 742         if (!filter) {
 743                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 744                 return -ENODEV;
 745         }
 746         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 747         filter->mac_index = index;
 748         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 749         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 750 }
 751
 752 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 753 {
 754         int rc = 0;
 755         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 756         struct rte_eth_link new;
 757         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 758
 759         memset(&new, 0, sizeof(new));
 760         do {
 761                 /* Retrieve link info from hardware */
 762                 rc = bnxt_get_hwrm_link_config(bp, &new);
 763                 if (rc) {
 764                         new.link_speed = ETH_LINK_SPEED_100M;
 765                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 766                         PMD_DRV_LOG(ERR,
 767                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 768                         goto out;
 769                 }
 770                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 771
 772                 if (!wait_to_complete)
 773                         break;
 774         } while (!new.link_status && cnt--);
 775
 776 out:
 777         /* Timed out or success */
 778         if (new.link_status != eth_dev->data->dev_link.link_status ||
 779         new.link_speed != eth_dev->data->dev_link.link_speed) {
 780                 memcpy(&eth_dev->data->dev_link, &new,
 781                         sizeof(struct rte_eth_link));
 782
 783                 _rte_eth_dev_callback_process(eth_dev,
 784                                               RTE_ETH_EVENT_INTR_LSC,
 785                                               NULL);
 786
 787                 bnxt_print_link_info(eth_dev);
 788         }
 789
 790         return rc;
 791 }
 792
 793 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 794 {
 795         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 796         struct bnxt_vnic_info *vnic;
 797
 798         if (bp->vnic_info == NULL)
 799                 return;
 800
 801         vnic = &bp->vnic_info[0];
 802
 803         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 804         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 805 }
 806
 807 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 808 {
 809         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 810         struct bnxt_vnic_info *vnic;
 811
 812         if (bp->vnic_info == NULL)
 813                 return;
 814
 815         vnic = &bp->vnic_info[0];
 816
 817         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 818         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 819 }
 820
 821 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 822 {
 823         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 824         struct bnxt_vnic_info *vnic;
 825
 826         if (bp->vnic_info == NULL)
 827                 return;
 828
 829         vnic = &bp->vnic_info[0];
 830
 831         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 832         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 833 }
 834
 835 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 836 {
 837         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 838         struct bnxt_vnic_info *vnic;
 839
 840         if (bp->vnic_info == NULL)
 841                 return;
 842
 843         vnic = &bp->vnic_info[0];
 844
 845         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 846         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 847 }
 848
 849 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 850                             struct rte_eth_rss_reta_entry64 *reta_conf,
 851                             uint16_t reta_size)
 852 {
 853         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 854         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 855         struct bnxt_vnic_info *vnic;
 856         int i;
 857
 858         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 859                 return -EINVAL;
 860
 861         if (reta_size != HW_HASH_INDEX_SIZE) {
 862                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 863                         "(%d) must equal the size supported by the hardware "
 864                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 865                 return -EINVAL;
 866         }
 867         /* Update the RSS VNIC(s) */
 868         for (i = 0; i < MAX_FF_POOLS; i++) {
 869                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 870                         memcpy(vnic->rss_table, reta_conf, reta_size);
 871
 872                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 873                 }
 874         }
 875         return 0;
 876 }
 877
 878 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 879                               struct rte_eth_rss_reta_entry64 *reta_conf,
 880                               uint16_t reta_size)
 881 {
 882         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 883         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 884         struct rte_intr_handle *intr_handle
 885                 = &bp->pdev->intr_handle;
 886
 887         /* Retrieve from the default VNIC */
 888         if (!vnic)
 889                 return -EINVAL;
 890         if (!vnic->rss_table)
 891                 return -EINVAL;
 892
 893         if (reta_size != HW_HASH_INDEX_SIZE) {
 894                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 895                         "(%d) must equal the size supported by the hardware "
 896                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 897                 return -EINVAL;
 898         }
 899         /* EW - need to revisit here copying from uint64_t to uint16_t */
 900         memcpy(reta_conf, vnic->rss_table, reta_size);
 901
 902         if (rte_intr_allow_others(intr_handle)) {
 903                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 904                         bnxt_dev_lsc_intr_setup(eth_dev);
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 911                                    struct rte_eth_rss_conf *rss_conf)
 912 {
 913         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 914         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 915         struct bnxt_vnic_info *vnic;
 916         uint16_t hash_type = 0;
 917         int i;
 918
 919         /*
 920          * If RSS enablement were different than dev_configure,
 921          * then return -EINVAL
 922          */
 923         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 924                 if (!rss_conf->rss_hf)
 925                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 926         } else {
 927                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 928                         return -EINVAL;
 929         }
 930
 931         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 932         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 933
 934         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 935                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 936         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 937                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 938         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 939                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 940         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 941                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 942         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 943                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 944         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 945                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 946
 947         /* Update the RSS VNIC(s) */
 948         for (i = 0; i < MAX_FF_POOLS; i++) {
 949                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 950                         vnic->hash_type = hash_type;
 951
 952                         /*
 953                          * Use the supplied key if the key length is
 954                          * acceptable and the rss_key is not NULL
 955                          */
 956                         if (rss_conf->rss_key &&
 957                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 958                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 959                                        rss_conf->rss_key_len);
 960
 961                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 962                 }
 963         }
 964         return 0;
 965 }
 966
 967 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 968                                      struct rte_eth_rss_conf *rss_conf)
 969 {
 970         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 971         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 972         int len;
 973         uint32_t hash_types;
 974
 975         /* RSS configuration is the same for all VNICs */
 976         if (vnic && vnic->rss_hash_key) {
 977                 if (rss_conf->rss_key) {
 978                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 979                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 980                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 981                 }
 982
 983                 hash_types = vnic->hash_type;
 984                 rss_conf->rss_hf = 0;
 985                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 986                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 987                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 988                 }
 989                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 990                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 991                         hash_types &=
 992                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 993                 }
 994                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 995                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 996                         hash_types &=
 997                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 998                 }
 999                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1000                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1001                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1002                 }
1003                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1004                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1005                         hash_types &=
1006                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1007                 }
1008                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1009                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1010                         hash_types &=
1011                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1012                 }
1013                 if (hash_types) {
1014                         PMD_DRV_LOG(ERR,
1015                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1016                                 vnic->hash_type);
1017                         return -ENOTSUP;
1018                 }
1019         } else {
1020                 rss_conf->rss_hf = 0;
1021         }
1022         return 0;
1023 }
1024
1025 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1026                                struct rte_eth_fc_conf *fc_conf)
1027 {
1028         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1029         struct rte_eth_link link_info;
1030         int rc;
1031
1032         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1033         if (rc)
1034                 return rc;
1035
1036         memset(fc_conf, 0, sizeof(*fc_conf));
1037         if (bp->link_info.auto_pause)
1038                 fc_conf->autoneg = 1;
1039         switch (bp->link_info.pause) {
1040         case 0:
1041                 fc_conf->mode = RTE_FC_NONE;
1042                 break;
1043         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1044                 fc_conf->mode = RTE_FC_TX_PAUSE;
1045                 break;
1046         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1047                 fc_conf->mode = RTE_FC_RX_PAUSE;
1048                 break;
1049         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1050                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1051                 fc_conf->mode = RTE_FC_FULL;
1052                 break;
1053         }
1054         return 0;
1055 }
1056
1057 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1058                                struct rte_eth_fc_conf *fc_conf)
1059 {
1060         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1061
1062         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1063                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1064                 return -ENOTSUP;
1065         }
1066
1067         switch (fc_conf->mode) {
1068         case RTE_FC_NONE:
1069                 bp->link_info.auto_pause = 0;
1070                 bp->link_info.force_pause = 0;
1071                 break;
1072         case RTE_FC_RX_PAUSE:
1073                 if (fc_conf->autoneg) {
1074                         bp->link_info.auto_pause =
1075                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1076                         bp->link_info.force_pause = 0;
1077                 } else {
1078                         bp->link_info.auto_pause = 0;
1079                         bp->link_info.force_pause =
1080                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1081                 }
1082                 break;
1083         case RTE_FC_TX_PAUSE:
1084                 if (fc_conf->autoneg) {
1085                         bp->link_info.auto_pause =
1086                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1087                         bp->link_info.force_pause = 0;
1088                 } else {
1089                         bp->link_info.auto_pause = 0;
1090                         bp->link_info.force_pause =
1091                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1092                 }
1093                 break;
1094         case RTE_FC_FULL:
1095                 if (fc_conf->autoneg) {
1096                         bp->link_info.auto_pause =
1097                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1098                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1099                         bp->link_info.force_pause = 0;
1100                 } else {
1101                         bp->link_info.auto_pause = 0;
1102                         bp->link_info.force_pause =
1103                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1104                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1105                 }
1106                 break;
1107         }
1108         return bnxt_set_hwrm_link_config(bp, true);
1109 }
1110
1111 /* Add UDP tunneling port */
1112 static int
1113 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1114                          struct rte_eth_udp_tunnel *udp_tunnel)
1115 {
1116         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1117         uint16_t tunnel_type = 0;
1118         int rc = 0;
1119
1120         switch (udp_tunnel->prot_type) {
1121         case RTE_TUNNEL_TYPE_VXLAN:
1122                 if (bp->vxlan_port_cnt) {
1123                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1124                                 udp_tunnel->udp_port);
1125                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1126                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1127                                 return -ENOSPC;
1128                         }
1129                         bp->vxlan_port_cnt++;
1130                         return 0;
1131                 }
1132                 tunnel_type =
1133                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1134                 bp->vxlan_port_cnt++;
1135                 break;
1136         case RTE_TUNNEL_TYPE_GENEVE:
1137                 if (bp->geneve_port_cnt) {
1138                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1139                                 udp_tunnel->udp_port);
1140                         if (bp->geneve_port != udp_tunnel->udp_port) {
1141                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1142                                 return -ENOSPC;
1143                         }
1144                         bp->geneve_port_cnt++;
1145                         return 0;
1146                 }
1147                 tunnel_type =
1148                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1149                 bp->geneve_port_cnt++;
1150                 break;
1151         default:
1152                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1153                 return -ENOTSUP;
1154         }
1155         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1156                                              tunnel_type);
1157         return rc;
1158 }
1159
1160 static int
1161 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1162                          struct rte_eth_udp_tunnel *udp_tunnel)
1163 {
1164         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1165         uint16_t tunnel_type = 0;
1166         uint16_t port = 0;
1167         int rc = 0;
1168
1169         switch (udp_tunnel->prot_type) {
1170         case RTE_TUNNEL_TYPE_VXLAN:
1171                 if (!bp->vxlan_port_cnt) {
1172                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1173                         return -EINVAL;
1174                 }
1175                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1176                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1177                                 udp_tunnel->udp_port, bp->vxlan_port);
1178                         return -EINVAL;
1179                 }
1180                 if (--bp->vxlan_port_cnt)
1181                         return 0;
1182
1183                 tunnel_type =
1184                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1185                 port = bp->vxlan_fw_dst_port_id;
1186                 break;
1187         case RTE_TUNNEL_TYPE_GENEVE:
1188                 if (!bp->geneve_port_cnt) {
1189                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1190                         return -EINVAL;
1191                 }
1192                 if (bp->geneve_port != udp_tunnel->udp_port) {
1193                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1194                                 udp_tunnel->udp_port, bp->geneve_port);
1195                         return -EINVAL;
1196                 }
1197                 if (--bp->geneve_port_cnt)
1198                         return 0;
1199
1200                 tunnel_type =
1201                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1202                 port = bp->geneve_fw_dst_port_id;
1203                 break;
1204         default:
1205                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1206                 return -ENOTSUP;
1207         }
1208
1209         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1210         if (!rc) {
1211                 if (tunnel_type ==
1212                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1213                         bp->vxlan_port = 0;
1214                 if (tunnel_type ==
1215                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1216                         bp->geneve_port = 0;
1217         }
1218         return rc;
1219 }
1220
1221 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1222 {
1223         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1224         struct bnxt_vnic_info *vnic;
1225         unsigned int i;
1226         int rc = 0;
1227         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1228
1229         /* Cycle through all VNICs */
1230         for (i = 0; i < bp->nr_vnics; i++) {
1231                 /*
1232                  * For each VNIC and each associated filter(s)
1233                  * if VLAN exists && VLAN matches vlan_id
1234                  *      remove the MAC+VLAN filter
1235                  *      add a new MAC only filter
1236                  * else
1237                  *      VLAN filter doesn't exist, just skip and continue
1238                  */
1239                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1240                         filter = STAILQ_FIRST(&vnic->filter);
1241                         while (filter) {
1242                                 temp_filter = STAILQ_NEXT(filter, next);
1243
1244                                 if (filter->enables & chk &&
1245                                     filter->l2_ovlan == vlan_id) {
1246                                         /* Must delete the filter */
1247                                         STAILQ_REMOVE(&vnic->filter, filter,
1248                                                       bnxt_filter_info, next);
1249                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1250                                         STAILQ_INSERT_TAIL(
1251                                                         &bp->free_filter_list,
1252                                                         filter, next);
1253
1254                                         /*
1255                                          * Need to examine to see if the MAC
1256                                          * filter already existed or not before
1257                                          * allocating a new one
1258                                          */
1259
1260                                         new_filter = bnxt_alloc_filter(bp);
1261                                         if (!new_filter) {
1262                                                 PMD_DRV_LOG(ERR,
1263                                                         "MAC/VLAN filter alloc failed\n");
1264                                                 rc = -ENOMEM;
1265                                                 goto exit;
1266                                         }
1267                                         STAILQ_INSERT_TAIL(&vnic->filter,
1268                                                            new_filter, next);
1269                                         /* Inherit MAC from previous filter */
1270                                         new_filter->mac_index =
1271                                                         filter->mac_index;
1272                                         memcpy(new_filter->l2_addr,
1273                                                filter->l2_addr, ETHER_ADDR_LEN);
1274                                         /* MAC only filter */
1275                                         rc = bnxt_hwrm_set_l2_filter(bp,
1276                                                         vnic->fw_vnic_id,
1277                                                         new_filter);
1278                                         if (rc)
1279                                                 goto exit;
1280                                         PMD_DRV_LOG(INFO,
1281                                                 "Del Vlan filter for %d\n",
1282                                                 vlan_id);
1283                                 }
1284                                 filter = temp_filter;
1285                         }
1286                 }
1287         }
1288 exit:
1289         return rc;
1290 }
1291
1292 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1293 {
1294         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1295         struct bnxt_vnic_info *vnic;
1296         unsigned int i;
1297         int rc = 0;
1298         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1299                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1300         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1301
1302         /* Cycle through all VNICs */
1303         for (i = 0; i < bp->nr_vnics; i++) {
1304                 /*
1305                  * For each VNIC and each associated filter(s)
1306                  * if VLAN exists:
1307                  *   if VLAN matches vlan_id
1308                  *      VLAN filter already exists, just skip and continue
1309                  *   else
1310                  *      add a new MAC+VLAN filter
1311                  * else
1312                  *   Remove the old MAC only filter
1313                  *    Add a new MAC+VLAN filter
1314                  */
1315                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1316                         filter = STAILQ_FIRST(&vnic->filter);
1317                         while (filter) {
1318                                 temp_filter = STAILQ_NEXT(filter, next);
1319
1320                                 if (filter->enables & chk) {
1321                                         if (filter->l2_ovlan == vlan_id)
1322                                                 goto cont;
1323                                 } else {
1324                                         /* Must delete the MAC filter */
1325                                         STAILQ_REMOVE(&vnic->filter, filter,
1326                                                       bnxt_filter_info, next);
1327                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1328                                         filter->l2_ovlan = 0;
1329                                         STAILQ_INSERT_TAIL(
1330                                                         &bp->free_filter_list,
1331                                                         filter, next);
1332                                 }
1333                                 new_filter = bnxt_alloc_filter(bp);
1334                                 if (!new_filter) {
1335                                         PMD_DRV_LOG(ERR,
1336                                                 "MAC/VLAN filter alloc failed\n");
1337                                         rc = -ENOMEM;
1338                                         goto exit;
1339                                 }
1340                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1341                                                    next);
1342                                 /* Inherit MAC from the previous filter */
1343                                 new_filter->mac_index = filter->mac_index;
1344                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1345                                        ETHER_ADDR_LEN);
1346                                 /* MAC + VLAN ID filter */
1347                                 new_filter->l2_ovlan = vlan_id;
1348                                 new_filter->l2_ovlan_mask = 0xF000;
1349                                 new_filter->enables |= en;
1350                                 rc = bnxt_hwrm_set_l2_filter(bp,
1351                                                              vnic->fw_vnic_id,
1352                                                              new_filter);
1353                                 if (rc)
1354                                         goto exit;
1355                                 PMD_DRV_LOG(INFO,
1356                                         "Added Vlan filter for %d\n", vlan_id);
1357 cont:
1358                                 filter = temp_filter;
1359                         }
1360                 }
1361         }
1362 exit:
1363         return rc;
1364 }
1365
1366 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1367                                    uint16_t vlan_id, int on)
1368 {
1369         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1370
1371         /* These operations apply to ALL existing MAC/VLAN filters */
1372         if (on)
1373                 return bnxt_add_vlan_filter(bp, vlan_id);
1374         else
1375                 return bnxt_del_vlan_filter(bp, vlan_id);
1376 }
1377
1378 static int
1379 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1380 {
1381         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1382         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1383         unsigned int i;
1384
1385         if (mask & ETH_VLAN_FILTER_MASK) {
1386                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1387                         /* Remove any VLAN filters programmed */
1388                         for (i = 0; i < 4095; i++)
1389                                 bnxt_del_vlan_filter(bp, i);
1390                 }
1391                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1392                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1393         }
1394
1395         if (mask & ETH_VLAN_STRIP_MASK) {
1396                 /* Enable or disable VLAN stripping */
1397                 for (i = 0; i < bp->nr_vnics; i++) {
1398                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1399                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1400                                 vnic->vlan_strip = true;
1401                         else
1402                                 vnic->vlan_strip = false;
1403                         bnxt_hwrm_vnic_cfg(bp, vnic);
1404                 }
1405                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1406                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1407         }
1408
1409         if (mask & ETH_VLAN_EXTEND_MASK)
1410                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1411
1412         return 0;
1413 }
1414
1415 static int
1416 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1417 {
1418         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1419         /* Default Filter is tied to VNIC 0 */
1420         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1421         struct bnxt_filter_info *filter;
1422         int rc;
1423
1424         if (BNXT_VF(bp))
1425                 return -EPERM;
1426
1427         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1428
1429         STAILQ_FOREACH(filter, &vnic->filter, next) {
1430                 /* Default Filter is at Index 0 */
1431                 if (filter->mac_index != 0)
1432                         continue;
1433                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1434                 if (rc)
1435                         return rc;
1436                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1437                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1438                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1439                 filter->enables |=
1440                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1441                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1442                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1443                 if (rc)
1444                         return rc;
1445                 filter->mac_index = 0;
1446                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1447         }
1448
1449         return 0;
1450 }
1451
1452 static int
1453 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1454                           struct ether_addr *mc_addr_set,
1455                           uint32_t nb_mc_addr)
1456 {
1457         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1458         char *mc_addr_list = (char *)mc_addr_set;
1459         struct bnxt_vnic_info *vnic;
1460         uint32_t off = 0, i = 0;
1461
1462         vnic = &bp->vnic_info[0];
1463
1464         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1465                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1466                 goto allmulti;
1467         }
1468
1469         /* TODO Check for Duplicate mcast addresses */
1470         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1471         for (i = 0; i < nb_mc_addr; i++) {
1472                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1473                 off += ETHER_ADDR_LEN;
1474         }
1475
1476         vnic->mc_addr_cnt = i;
1477
1478 allmulti:
1479         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1480 }
1481
1482 static int
1483 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1484 {
1485         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1486         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1487         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1488         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1489         int ret;
1490
1491         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1492                         fw_major, fw_minor, fw_updt);
1493
1494         ret += 1; /* add the size of '\0' */
1495         if (fw_size < (uint32_t)ret)
1496                 return ret;
1497         else
1498                 return 0;
1499 }
1500
1501 static void
1502 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1503         struct rte_eth_rxq_info *qinfo)
1504 {
1505         struct bnxt_rx_queue *rxq;
1506
1507         rxq = dev->data->rx_queues[queue_id];
1508
1509         qinfo->mp = rxq->mb_pool;
1510         qinfo->scattered_rx = dev->data->scattered_rx;
1511         qinfo->nb_desc = rxq->nb_rx_desc;
1512
1513         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1514         qinfo->conf.rx_drop_en = 0;
1515         qinfo->conf.rx_deferred_start = 0;
1516 }
1517
1518 static void
1519 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1520         struct rte_eth_txq_info *qinfo)
1521 {
1522         struct bnxt_tx_queue *txq;
1523
1524         txq = dev->data->tx_queues[queue_id];
1525
1526         qinfo->nb_desc = txq->nb_tx_desc;
1527
1528         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1529         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1530         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1531
1532         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1533         qinfo->conf.tx_rs_thresh = 0;
1534         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1535 }
1536
1537 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1538 {
1539         struct bnxt *bp = eth_dev->data->dev_private;
1540         struct rte_eth_dev_info dev_info;
1541         uint32_t max_dev_mtu;
1542         uint32_t rc = 0;
1543         uint32_t i;
1544
1545         bnxt_dev_info_get_op(eth_dev, &dev_info);
1546         max_dev_mtu = dev_info.max_rx_pktlen -
1547                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1548
1549         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1550                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1551                         ETHER_MIN_MTU, max_dev_mtu);
1552                 return -EINVAL;
1553         }
1554
1555
1556         if (new_mtu > ETHER_MTU) {
1557                 bp->flags |= BNXT_FLAG_JUMBO;
1558                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1559                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1560         } else {
1561                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1562                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1563                 bp->flags &= ~BNXT_FLAG_JUMBO;
1564         }
1565
1566         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1567                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1568
1569         eth_dev->data->mtu = new_mtu;
1570         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1571
1572         for (i = 0; i < bp->nr_vnics; i++) {
1573                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1574
1575                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1576                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1577                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1578                 if (rc)
1579                         break;
1580
1581                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1582                 if (rc)
1583                         return rc;
1584         }
1585
1586         return rc;
1587 }
1588
1589 static int
1590 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1591 {
1592         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1593         uint16_t vlan = bp->vlan;
1594         int rc;
1595
1596         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1597                 PMD_DRV_LOG(ERR,
1598                         "PVID cannot be modified for this function\n");
1599                 return -ENOTSUP;
1600         }
1601         bp->vlan = on ? pvid : 0;
1602
1603         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1604         if (rc)
1605                 bp->vlan = vlan;
1606         return rc;
1607 }
1608
1609 static int
1610 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1611 {
1612         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1613
1614         return bnxt_hwrm_port_led_cfg(bp, true);
1615 }
1616
1617 static int
1618 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1619 {
1620         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1621
1622         return bnxt_hwrm_port_led_cfg(bp, false);
1623 }
1624
1625 static uint32_t
1626 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1627 {
1628         uint32_t desc = 0, raw_cons = 0, cons;
1629         struct bnxt_cp_ring_info *cpr;
1630         struct bnxt_rx_queue *rxq;
1631         struct rx_pkt_cmpl *rxcmp;
1632         uint16_t cmp_type;
1633         uint8_t cmp = 1;
1634         bool valid;
1635
1636         rxq = dev->data->rx_queues[rx_queue_id];
1637         cpr = rxq->cp_ring;
1638         valid = cpr->valid;
1639
1640         while (raw_cons < rxq->nb_rx_desc) {
1641                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1642                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1643
1644                 if (!CMPL_VALID(rxcmp, valid))
1645                         goto nothing_to_do;
1646                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1647                 cmp_type = CMP_TYPE(rxcmp);
1648                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1649                         cmp = (rte_le_to_cpu_32(
1650                                         ((struct rx_tpa_end_cmpl *)
1651                                          (rxcmp))->agg_bufs_v1) &
1652                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1653                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1654                         desc++;
1655                 } else if (cmp_type == 0x11) {
1656                         desc++;
1657                         cmp = (rxcmp->agg_bufs_v1 &
1658                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1659                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1660                 } else {
1661                         cmp = 1;
1662                 }
1663 nothing_to_do:
1664                 raw_cons += cmp ? cmp : 2;
1665         }
1666
1667         return desc;
1668 }
1669
1670 static int
1671 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1672 {
1673         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1674         struct bnxt_rx_ring_info *rxr;
1675         struct bnxt_cp_ring_info *cpr;
1676         struct bnxt_sw_rx_bd *rx_buf;
1677         struct rx_pkt_cmpl *rxcmp;
1678         uint32_t cons, cp_cons;
1679
1680         if (!rxq)
1681                 return -EINVAL;
1682
1683         cpr = rxq->cp_ring;
1684         rxr = rxq->rx_ring;
1685
1686         if (offset >= rxq->nb_rx_desc)
1687                 return -EINVAL;
1688
1689         cons = RING_CMP(cpr->cp_ring_struct, offset);
1690         cp_cons = cpr->cp_raw_cons;
1691         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1692
1693         if (cons > cp_cons) {
1694                 if (CMPL_VALID(rxcmp, cpr->valid))
1695                         return RTE_ETH_RX_DESC_DONE;
1696         } else {
1697                 if (CMPL_VALID(rxcmp, !cpr->valid))
1698                         return RTE_ETH_RX_DESC_DONE;
1699         }
1700         rx_buf = &rxr->rx_buf_ring[cons];
1701         if (rx_buf->mbuf == NULL)
1702                 return RTE_ETH_RX_DESC_UNAVAIL;
1703
1704
1705         return RTE_ETH_RX_DESC_AVAIL;
1706 }
1707
1708 static int
1709 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1710 {
1711         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1712         struct bnxt_tx_ring_info *txr;
1713         struct bnxt_cp_ring_info *cpr;
1714         struct bnxt_sw_tx_bd *tx_buf;
1715         struct tx_pkt_cmpl *txcmp;
1716         uint32_t cons, cp_cons;
1717
1718         if (!txq)
1719                 return -EINVAL;
1720
1721         cpr = txq->cp_ring;
1722         txr = txq->tx_ring;
1723
1724         if (offset >= txq->nb_tx_desc)
1725                 return -EINVAL;
1726
1727         cons = RING_CMP(cpr->cp_ring_struct, offset);
1728         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1729         cp_cons = cpr->cp_raw_cons;
1730
1731         if (cons > cp_cons) {
1732                 if (CMPL_VALID(txcmp, cpr->valid))
1733                         return RTE_ETH_TX_DESC_UNAVAIL;
1734         } else {
1735                 if (CMPL_VALID(txcmp, !cpr->valid))
1736                         return RTE_ETH_TX_DESC_UNAVAIL;
1737         }
1738         tx_buf = &txr->tx_buf_ring[cons];
1739         if (tx_buf->mbuf == NULL)
1740                 return RTE_ETH_TX_DESC_DONE;
1741
1742         return RTE_ETH_TX_DESC_FULL;
1743 }
1744
1745 static struct bnxt_filter_info *
1746 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1747                                 struct rte_eth_ethertype_filter *efilter,
1748                                 struct bnxt_vnic_info *vnic0,
1749                                 struct bnxt_vnic_info *vnic,
1750                                 int *ret)
1751 {
1752         struct bnxt_filter_info *mfilter = NULL;
1753         int match = 0;
1754         *ret = 0;
1755
1756         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1757                 efilter->ether_type == ETHER_TYPE_IPv6) {
1758                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1759                         " ethertype filter.", efilter->ether_type);
1760                 *ret = -EINVAL;
1761                 goto exit;
1762         }
1763         if (efilter->queue >= bp->rx_nr_rings) {
1764                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1765                 *ret = -EINVAL;
1766                 goto exit;
1767         }
1768
1769         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1770         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1771         if (vnic == NULL) {
1772                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1773                 *ret = -EINVAL;
1774                 goto exit;
1775         }
1776
1777         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1778                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1779                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1780                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1781                              mfilter->flags ==
1782                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1783                              mfilter->ethertype == efilter->ether_type)) {
1784                                 match = 1;
1785                                 break;
1786                         }
1787                 }
1788         } else {
1789                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1790                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1791                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1792                              mfilter->ethertype == efilter->ether_type &&
1793                              mfilter->flags ==
1794                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1795                                 match = 1;
1796                                 break;
1797                         }
1798         }
1799
1800         if (match)
1801                 *ret = -EEXIST;
1802
1803 exit:
1804         return mfilter;
1805 }
1806
1807 static int
1808 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1809                         enum rte_filter_op filter_op,
1810                         void *arg)
1811 {
1812         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1813         struct rte_eth_ethertype_filter *efilter =
1814                         (struct rte_eth_ethertype_filter *)arg;
1815         struct bnxt_filter_info *bfilter, *filter1;
1816         struct bnxt_vnic_info *vnic, *vnic0;
1817         int ret;
1818
1819         if (filter_op == RTE_ETH_FILTER_NOP)
1820                 return 0;
1821
1822         if (arg == NULL) {
1823                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1824                             filter_op);
1825                 return -EINVAL;
1826         }
1827
1828         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1829         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1830
1831         switch (filter_op) {
1832         case RTE_ETH_FILTER_ADD:
1833                 bnxt_match_and_validate_ether_filter(bp, efilter,
1834                                                         vnic0, vnic, &ret);
1835                 if (ret < 0)
1836                         return ret;
1837
1838                 bfilter = bnxt_get_unused_filter(bp);
1839                 if (bfilter == NULL) {
1840                         PMD_DRV_LOG(ERR,
1841                                 "Not enough resources for a new filter.\n");
1842                         return -ENOMEM;
1843                 }
1844                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1845                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1846                        ETHER_ADDR_LEN);
1847                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1848                        ETHER_ADDR_LEN);
1849                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1850                 bfilter->ethertype = efilter->ether_type;
1851                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1852
1853                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1854                 if (filter1 == NULL) {
1855                         ret = -1;
1856                         goto cleanup;
1857                 }
1858                 bfilter->enables |=
1859                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1860                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1861
1862                 bfilter->dst_id = vnic->fw_vnic_id;
1863
1864                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1865                         bfilter->flags =
1866                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1867                 }
1868
1869                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1870                 if (ret)
1871                         goto cleanup;
1872                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1873                 break;
1874         case RTE_ETH_FILTER_DELETE:
1875                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1876                                                         vnic0, vnic, &ret);
1877                 if (ret == -EEXIST) {
1878                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1879
1880                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1881                                       next);
1882                         bnxt_free_filter(bp, filter1);
1883                 } else if (ret == 0) {
1884                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1885                 }
1886                 break;
1887         default:
1888                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1889                 ret = -EINVAL;
1890                 goto error;
1891         }
1892         return ret;
1893 cleanup:
1894         bnxt_free_filter(bp, bfilter);
1895 error:
1896         return ret;
1897 }
1898
1899 static inline int
1900 parse_ntuple_filter(struct bnxt *bp,
1901                     struct rte_eth_ntuple_filter *nfilter,
1902                     struct bnxt_filter_info *bfilter)
1903 {
1904         uint32_t en = 0;
1905
1906         if (nfilter->queue >= bp->rx_nr_rings) {
1907                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1908                 return -EINVAL;
1909         }
1910
1911         switch (nfilter->dst_port_mask) {
1912         case UINT16_MAX:
1913                 bfilter->dst_port_mask = -1;
1914                 bfilter->dst_port = nfilter->dst_port;
1915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1916                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1917                 break;
1918         default:
1919                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1920                 return -EINVAL;
1921         }
1922
1923         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1924         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1925
1926         switch (nfilter->proto_mask) {
1927         case UINT8_MAX:
1928                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1929                         bfilter->ip_protocol = 17;
1930                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1931                         bfilter->ip_protocol = 6;
1932                 else
1933                         return -EINVAL;
1934                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1935                 break;
1936         default:
1937                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1938                 return -EINVAL;
1939         }
1940
1941         switch (nfilter->dst_ip_mask) {
1942         case UINT32_MAX:
1943                 bfilter->dst_ipaddr_mask[0] = -1;
1944                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1945                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1946                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1947                 break;
1948         default:
1949                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1950                 return -EINVAL;
1951         }
1952
1953         switch (nfilter->src_ip_mask) {
1954         case UINT32_MAX:
1955                 bfilter->src_ipaddr_mask[0] = -1;
1956                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1957                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1958                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1959                 break;
1960         default:
1961                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1962                 return -EINVAL;
1963         }
1964
1965         switch (nfilter->src_port_mask) {
1966         case UINT16_MAX:
1967                 bfilter->src_port_mask = -1;
1968                 bfilter->src_port = nfilter->src_port;
1969                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1970                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1971                 break;
1972         default:
1973                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1974                 return -EINVAL;
1975         }
1976
1977         //TODO Priority
1978         //nfilter->priority = (uint8_t)filter->priority;
1979
1980         bfilter->enables = en;
1981         return 0;
1982 }
1983
1984 static struct bnxt_filter_info*
1985 bnxt_match_ntuple_filter(struct bnxt *bp,
1986                          struct bnxt_filter_info *bfilter,
1987                          struct bnxt_vnic_info **mvnic)
1988 {
1989         struct bnxt_filter_info *mfilter = NULL;
1990         int i;
1991
1992         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1993                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1994                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1995                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1996                             bfilter->src_ipaddr_mask[0] ==
1997                             mfilter->src_ipaddr_mask[0] &&
1998                             bfilter->src_port == mfilter->src_port &&
1999                             bfilter->src_port_mask == mfilter->src_port_mask &&
2000                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2001                             bfilter->dst_ipaddr_mask[0] ==
2002                             mfilter->dst_ipaddr_mask[0] &&
2003                             bfilter->dst_port == mfilter->dst_port &&
2004                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2005                             bfilter->flags == mfilter->flags &&
2006                             bfilter->enables == mfilter->enables) {
2007                                 if (mvnic)
2008                                         *mvnic = vnic;
2009                                 return mfilter;
2010                         }
2011                 }
2012         }
2013         return NULL;
2014 }
2015
2016 static int
2017 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2018                        struct rte_eth_ntuple_filter *nfilter,
2019                        enum rte_filter_op filter_op)
2020 {
2021         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2022         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2023         int ret;
2024
2025         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2026                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2027                 return -EINVAL;
2028         }
2029
2030         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2031                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2032                 return -EINVAL;
2033         }
2034
2035         bfilter = bnxt_get_unused_filter(bp);
2036         if (bfilter == NULL) {
2037                 PMD_DRV_LOG(ERR,
2038                         "Not enough resources for a new filter.\n");
2039                 return -ENOMEM;
2040         }
2041         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2042         if (ret < 0)
2043                 goto free_filter;
2044
2045         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2046         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2047         filter1 = STAILQ_FIRST(&vnic0->filter);
2048         if (filter1 == NULL) {
2049                 ret = -1;
2050                 goto free_filter;
2051         }
2052
2053         bfilter->dst_id = vnic->fw_vnic_id;
2054         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2055         bfilter->enables |=
2056                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2057         bfilter->ethertype = 0x800;
2058         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2059
2060         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2061
2062         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2063             bfilter->dst_id == mfilter->dst_id) {
2064                 PMD_DRV_LOG(ERR, "filter exists.\n");
2065                 ret = -EEXIST;
2066                 goto free_filter;
2067         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2068                    bfilter->dst_id != mfilter->dst_id) {
2069                 mfilter->dst_id = vnic->fw_vnic_id;
2070                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2071                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2072                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2073                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2074                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2075                 goto free_filter;
2076         }
2077         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2078                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2079                 ret = -ENOENT;
2080                 goto free_filter;
2081         }
2082
2083         if (filter_op == RTE_ETH_FILTER_ADD) {
2084                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2085                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2086                 if (ret)
2087                         goto free_filter;
2088                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2089         } else {
2090                 if (mfilter == NULL) {
2091                         /* This should not happen. But for Coverity! */
2092                         ret = -ENOENT;
2093                         goto free_filter;
2094                 }
2095                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2096
2097                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2098                 bnxt_free_filter(bp, mfilter);
2099                 mfilter->fw_l2_filter_id = -1;
2100                 bnxt_free_filter(bp, bfilter);
2101                 bfilter->fw_l2_filter_id = -1;
2102         }
2103
2104         return 0;
2105 free_filter:
2106         bfilter->fw_l2_filter_id = -1;
2107         bnxt_free_filter(bp, bfilter);
2108         return ret;
2109 }
2110
2111 static int
2112 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2113                         enum rte_filter_op filter_op,
2114                         void *arg)
2115 {
2116         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2117         int ret;
2118
2119         if (filter_op == RTE_ETH_FILTER_NOP)
2120                 return 0;
2121
2122         if (arg == NULL) {
2123                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2124                             filter_op);
2125                 return -EINVAL;
2126         }
2127
2128         switch (filter_op) {
2129         case RTE_ETH_FILTER_ADD:
2130                 ret = bnxt_cfg_ntuple_filter(bp,
2131                         (struct rte_eth_ntuple_filter *)arg,
2132                         filter_op);
2133                 break;
2134         case RTE_ETH_FILTER_DELETE:
2135                 ret = bnxt_cfg_ntuple_filter(bp,
2136                         (struct rte_eth_ntuple_filter *)arg,
2137                         filter_op);
2138                 break;
2139         default:
2140                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2141                 ret = -EINVAL;
2142                 break;
2143         }
2144         return ret;
2145 }
2146
2147 static int
2148 bnxt_parse_fdir_filter(struct bnxt *bp,
2149                        struct rte_eth_fdir_filter *fdir,
2150                        struct bnxt_filter_info *filter)
2151 {
2152         enum rte_fdir_mode fdir_mode =
2153                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2154         struct bnxt_vnic_info *vnic0, *vnic;
2155         struct bnxt_filter_info *filter1;
2156         uint32_t en = 0;
2157         int i;
2158
2159         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2160                 return -EINVAL;
2161
2162         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2163         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2164
2165         switch (fdir->input.flow_type) {
2166         case RTE_ETH_FLOW_IPV4:
2167         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2168                 /* FALLTHROUGH */
2169                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2170                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2171                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2172                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2173                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2174                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2175                 filter->ip_addr_type =
2176                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2177                 filter->src_ipaddr_mask[0] = 0xffffffff;
2178                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2179                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2180                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2181                 filter->ethertype = 0x800;
2182                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2183                 break;
2184         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2185                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2186                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2187                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2189                 filter->dst_port_mask = 0xffff;
2190                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2191                 filter->src_port_mask = 0xffff;
2192                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2193                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2194                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2195                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2197                 filter->ip_protocol = 6;
2198                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2199                 filter->ip_addr_type =
2200                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2201                 filter->src_ipaddr_mask[0] = 0xffffffff;
2202                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2203                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2204                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2205                 filter->ethertype = 0x800;
2206                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2207                 break;
2208         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2209                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2210                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2211                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2212                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2213                 filter->dst_port_mask = 0xffff;
2214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2215                 filter->src_port_mask = 0xffff;
2216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2217                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2218                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2219                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2221                 filter->ip_protocol = 17;
2222                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2223                 filter->ip_addr_type =
2224                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2225                 filter->src_ipaddr_mask[0] = 0xffffffff;
2226                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2227                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2228                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2229                 filter->ethertype = 0x800;
2230                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2231                 break;
2232         case RTE_ETH_FLOW_IPV6:
2233         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2234                 /* FALLTHROUGH */
2235                 filter->ip_addr_type =
2236                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2237                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2238                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2239                 rte_memcpy(filter->src_ipaddr,
2240                            fdir->input.flow.ipv6_flow.src_ip, 16);
2241                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2242                 rte_memcpy(filter->dst_ipaddr,
2243                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2244                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2245                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2247                 memset(filter->src_ipaddr_mask, 0xff, 16);
2248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2249                 filter->ethertype = 0x86dd;
2250                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2251                 break;
2252         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2253                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2254                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2255                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2257                 filter->dst_port_mask = 0xffff;
2258                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2259                 filter->src_port_mask = 0xffff;
2260                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2261                 filter->ip_addr_type =
2262                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2263                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2264                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2265                 rte_memcpy(filter->src_ipaddr,
2266                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2267                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2268                 rte_memcpy(filter->dst_ipaddr,
2269                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2270                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2271                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2273                 memset(filter->src_ipaddr_mask, 0xff, 16);
2274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2275                 filter->ethertype = 0x86dd;
2276                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2277                 break;
2278         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2279                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2280                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2281                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2283                 filter->dst_port_mask = 0xffff;
2284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2285                 filter->src_port_mask = 0xffff;
2286                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2287                 filter->ip_addr_type =
2288                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2289                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2290                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2291                 rte_memcpy(filter->src_ipaddr,
2292                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2293                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2294                 rte_memcpy(filter->dst_ipaddr,
2295                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2296                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2297                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2298                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2299                 memset(filter->src_ipaddr_mask, 0xff, 16);
2300                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2301                 filter->ethertype = 0x86dd;
2302                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2303                 break;
2304         case RTE_ETH_FLOW_L2_PAYLOAD:
2305                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2306                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2307                 break;
2308         case RTE_ETH_FLOW_VXLAN:
2309                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2310                         return -EINVAL;
2311                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2312                 filter->tunnel_type =
2313                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2314                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2315                 break;
2316         case RTE_ETH_FLOW_NVGRE:
2317                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2318                         return -EINVAL;
2319                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2320                 filter->tunnel_type =
2321                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2322                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2323                 break;
2324         case RTE_ETH_FLOW_UNKNOWN:
2325         case RTE_ETH_FLOW_RAW:
2326         case RTE_ETH_FLOW_FRAG_IPV4:
2327         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2328         case RTE_ETH_FLOW_FRAG_IPV6:
2329         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2330         case RTE_ETH_FLOW_IPV6_EX:
2331         case RTE_ETH_FLOW_IPV6_TCP_EX:
2332         case RTE_ETH_FLOW_IPV6_UDP_EX:
2333         case RTE_ETH_FLOW_GENEVE:
2334                 /* FALLTHROUGH */
2335         default:
2336                 return -EINVAL;
2337         }
2338
2339         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2340         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2341         if (vnic == NULL) {
2342                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2343                 return -EINVAL;
2344         }
2345
2346
2347         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2348                 rte_memcpy(filter->dst_macaddr,
2349                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2350                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2351         }
2352
2353         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2354                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2355                 filter1 = STAILQ_FIRST(&vnic0->filter);
2356                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2357         } else {
2358                 filter->dst_id = vnic->fw_vnic_id;
2359                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2360                         if (filter->dst_macaddr[i] == 0x00)
2361                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2362                         else
2363                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2364         }
2365
2366         if (filter1 == NULL)
2367                 return -EINVAL;
2368
2369         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2370         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2371
2372         filter->enables = en;
2373
2374         return 0;
2375 }
2376
2377 static struct bnxt_filter_info *
2378 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2379                 struct bnxt_vnic_info **mvnic)
2380 {
2381         struct bnxt_filter_info *mf = NULL;
2382         int i;
2383
2384         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2385                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2386
2387                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2388                         if (mf->filter_type == nf->filter_type &&
2389                             mf->flags == nf->flags &&
2390                             mf->src_port == nf->src_port &&
2391                             mf->src_port_mask == nf->src_port_mask &&
2392                             mf->dst_port == nf->dst_port &&
2393                             mf->dst_port_mask == nf->dst_port_mask &&
2394                             mf->ip_protocol == nf->ip_protocol &&
2395                             mf->ip_addr_type == nf->ip_addr_type &&
2396                             mf->ethertype == nf->ethertype &&
2397                             mf->vni == nf->vni &&
2398                             mf->tunnel_type == nf->tunnel_type &&
2399                             mf->l2_ovlan == nf->l2_ovlan &&
2400                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2401                             mf->l2_ivlan == nf->l2_ivlan &&
2402                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2403                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2404                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2405                                     ETHER_ADDR_LEN) &&
2406                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2407                                     ETHER_ADDR_LEN) &&
2408                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2409                                     ETHER_ADDR_LEN) &&
2410                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2411                                     sizeof(nf->src_ipaddr)) &&
2412                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2413                                     sizeof(nf->src_ipaddr_mask)) &&
2414                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2415                                     sizeof(nf->dst_ipaddr)) &&
2416                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2417                                     sizeof(nf->dst_ipaddr_mask))) {
2418                                 if (mvnic)
2419                                         *mvnic = vnic;
2420                                 return mf;
2421                         }
2422                 }
2423         }
2424         return NULL;
2425 }
2426
2427 static int
2428 bnxt_fdir_filter(struct rte_eth_dev *dev,
2429                  enum rte_filter_op filter_op,
2430                  void *arg)
2431 {
2432         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2433         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2434         struct bnxt_filter_info *filter, *match;
2435         struct bnxt_vnic_info *vnic, *mvnic;
2436         int ret = 0, i;
2437
2438         if (filter_op == RTE_ETH_FILTER_NOP)
2439                 return 0;
2440
2441         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2442                 return -EINVAL;
2443
2444         switch (filter_op) {
2445         case RTE_ETH_FILTER_ADD:
2446         case RTE_ETH_FILTER_DELETE:
2447                 /* FALLTHROUGH */
2448                 filter = bnxt_get_unused_filter(bp);
2449                 if (filter == NULL) {
2450                         PMD_DRV_LOG(ERR,
2451                                 "Not enough resources for a new flow.\n");
2452                         return -ENOMEM;
2453                 }
2454
2455                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2456                 if (ret != 0)
2457                         goto free_filter;
2458                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2459
2460                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2461                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2462                 else
2463                         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2464
2465                 match = bnxt_match_fdir(bp, filter, &mvnic);
2466                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2467                         if (match->dst_id == vnic->fw_vnic_id) {
2468                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2469                                 ret = -EEXIST;
2470                                 goto free_filter;
2471                         } else {
2472                                 match->dst_id = vnic->fw_vnic_id;
2473                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2474                                                                   match->dst_id,
2475                                                                   match);
2476                                 STAILQ_REMOVE(&mvnic->filter, match,
2477                                               bnxt_filter_info, next);
2478                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2479                                 PMD_DRV_LOG(ERR,
2480                                         "Filter with matching pattern exist\n");
2481                                 PMD_DRV_LOG(ERR,
2482                                         "Updated it to new destination q\n");
2483                                 goto free_filter;
2484                         }
2485                 }
2486                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2487                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2488                         ret = -ENOENT;
2489                         goto free_filter;
2490                 }
2491
2492                 if (filter_op == RTE_ETH_FILTER_ADD) {
2493                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2494                                                           filter->dst_id,
2495                                                           filter);
2496                         if (ret)
2497                                 goto free_filter;
2498                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2499                 } else {
2500                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2501                         STAILQ_REMOVE(&vnic->filter, match,
2502                                       bnxt_filter_info, next);
2503                         bnxt_free_filter(bp, match);
2504                         filter->fw_l2_filter_id = -1;
2505                         bnxt_free_filter(bp, filter);
2506                 }
2507                 break;
2508         case RTE_ETH_FILTER_FLUSH:
2509                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2510                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2511
2512                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2513                                 if (filter->filter_type ==
2514                                     HWRM_CFA_NTUPLE_FILTER) {
2515                                         ret =
2516                                         bnxt_hwrm_clear_ntuple_filter(bp,
2517                                                                       filter);
2518                                         STAILQ_REMOVE(&vnic->filter, filter,
2519                                                       bnxt_filter_info, next);
2520                                 }
2521                         }
2522                 }
2523                 return ret;
2524         case RTE_ETH_FILTER_UPDATE:
2525         case RTE_ETH_FILTER_STATS:
2526         case RTE_ETH_FILTER_INFO:
2527                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2528                 break;
2529         default:
2530                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2531                 ret = -EINVAL;
2532                 break;
2533         }
2534         return ret;
2535
2536 free_filter:
2537         filter->fw_l2_filter_id = -1;
2538         bnxt_free_filter(bp, filter);
2539         return ret;
2540 }
2541
2542 static int
2543 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2544                     enum rte_filter_type filter_type,
2545                     enum rte_filter_op filter_op, void *arg)
2546 {
2547         int ret = 0;
2548
2549         switch (filter_type) {
2550         case RTE_ETH_FILTER_TUNNEL:
2551                 PMD_DRV_LOG(ERR,
2552                         "filter type: %d: To be implemented\n", filter_type);
2553                 break;
2554         case RTE_ETH_FILTER_FDIR:
2555                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2556                 break;
2557         case RTE_ETH_FILTER_NTUPLE:
2558                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2559                 break;
2560         case RTE_ETH_FILTER_ETHERTYPE:
2561                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2562                 break;
2563         case RTE_ETH_FILTER_GENERIC:
2564                 if (filter_op != RTE_ETH_FILTER_GET)
2565                         return -EINVAL;
2566                 *(const void **)arg = &bnxt_flow_ops;
2567                 break;
2568         default:
2569                 PMD_DRV_LOG(ERR,
2570                         "Filter type (%d) not supported", filter_type);
2571                 ret = -EINVAL;
2572                 break;
2573         }
2574         return ret;
2575 }
2576
2577 static const uint32_t *
2578 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2579 {
2580         static const uint32_t ptypes[] = {
2581                 RTE_PTYPE_L2_ETHER_VLAN,
2582                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2583                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2584                 RTE_PTYPE_L4_ICMP,
2585                 RTE_PTYPE_L4_TCP,
2586                 RTE_PTYPE_L4_UDP,
2587                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2588                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2589                 RTE_PTYPE_INNER_L4_ICMP,
2590                 RTE_PTYPE_INNER_L4_TCP,
2591                 RTE_PTYPE_INNER_L4_UDP,
2592                 RTE_PTYPE_UNKNOWN
2593         };
2594
2595         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2596                 return ptypes;
2597         return NULL;
2598 }
2599
2600 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2601                          int reg_win)
2602 {
2603         uint32_t reg_base = *reg_arr & 0xfffff000;
2604         uint32_t win_off;
2605         int i;
2606
2607         for (i = 0; i < count; i++) {
2608                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2609                         return -ERANGE;
2610         }
2611         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2612         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2613         return 0;
2614 }
2615
2616 static int bnxt_map_ptp_regs(struct bnxt *bp)
2617 {
2618         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2619         uint32_t *reg_arr;
2620         int rc, i;
2621
2622         reg_arr = ptp->rx_regs;
2623         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2624         if (rc)
2625                 return rc;
2626
2627         reg_arr = ptp->tx_regs;
2628         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2629         if (rc)
2630                 return rc;
2631
2632         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2633                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2634
2635         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2636                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2637
2638         return 0;
2639 }
2640
2641 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2642 {
2643         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2644                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2645         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2646                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2647 }
2648
2649 static uint64_t bnxt_cc_read(struct bnxt *bp)
2650 {
2651         uint64_t ns;
2652
2653         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2654                               BNXT_GRCPF_REG_SYNC_TIME));
2655         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2656                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2657         return ns;
2658 }
2659
2660 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2661 {
2662         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2663         uint32_t fifo;
2664
2665         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2666                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2667         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2668                 return -EAGAIN;
2669
2670         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2671                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2672         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2673                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2674         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2675                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2676
2677         return 0;
2678 }
2679
2680 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2681 {
2682         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2683         struct bnxt_pf_info *pf = &bp->pf;
2684         uint16_t port_id;
2685         uint32_t fifo;
2686
2687         if (!ptp)
2688                 return -ENODEV;
2689
2690         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2691                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2692         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2693                 return -EAGAIN;
2694
2695         port_id = pf->port_id;
2696         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2697                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2698
2699         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2700                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2701         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2702 /*              bnxt_clr_rx_ts(bp);       TBD  */
2703                 return -EBUSY;
2704         }
2705
2706         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2707                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2708         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2709                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2710
2711         return 0;
2712 }
2713
2714 static int
2715 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2716 {
2717         uint64_t ns;
2718         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2719         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2720
2721         if (!ptp)
2722                 return 0;
2723
2724         ns = rte_timespec_to_ns(ts);
2725         /* Set the timecounters to a new value. */
2726         ptp->tc.nsec = ns;
2727
2728         return 0;
2729 }
2730
2731 static int
2732 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2733 {
2734         uint64_t ns, systime_cycles;
2735         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2736         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2737
2738         if (!ptp)
2739                 return 0;
2740
2741         systime_cycles = bnxt_cc_read(bp);
2742         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2743         *ts = rte_ns_to_timespec(ns);
2744
2745         return 0;
2746 }
2747 static int
2748 bnxt_timesync_enable(struct rte_eth_dev *dev)
2749 {
2750         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2751         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2752         uint32_t shift = 0;
2753
2754         if (!ptp)
2755                 return 0;
2756
2757         ptp->rx_filter = 1;
2758         ptp->tx_tstamp_en = 1;
2759         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2760
2761         if (!bnxt_hwrm_ptp_cfg(bp))
2762                 bnxt_map_ptp_regs(bp);
2763
2764         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2765         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2766         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2767
2768         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2769         ptp->tc.cc_shift = shift;
2770         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2771
2772         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2773         ptp->rx_tstamp_tc.cc_shift = shift;
2774         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2775
2776         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2777         ptp->tx_tstamp_tc.cc_shift = shift;
2778         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2779
2780         return 0;
2781 }
2782
2783 static int
2784 bnxt_timesync_disable(struct rte_eth_dev *dev)
2785 {
2786         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2787         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2788
2789         if (!ptp)
2790                 return 0;
2791
2792         ptp->rx_filter = 0;
2793         ptp->tx_tstamp_en = 0;
2794         ptp->rxctl = 0;
2795
2796         bnxt_hwrm_ptp_cfg(bp);
2797
2798         bnxt_unmap_ptp_regs(bp);
2799
2800         return 0;
2801 }
2802
2803 static int
2804 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2805                                  struct timespec *timestamp,
2806                                  uint32_t flags __rte_unused)
2807 {
2808         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2809         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2810         uint64_t rx_tstamp_cycles = 0;
2811         uint64_t ns;
2812
2813         if (!ptp)
2814                 return 0;
2815
2816         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2817         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2818         *timestamp = rte_ns_to_timespec(ns);
2819         return  0;
2820 }
2821
2822 static int
2823 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2824                                  struct timespec *timestamp)
2825 {
2826         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2827         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2828         uint64_t tx_tstamp_cycles = 0;
2829         uint64_t ns;
2830
2831         if (!ptp)
2832                 return 0;
2833
2834         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2835         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2836         *timestamp = rte_ns_to_timespec(ns);
2837
2838         return 0;
2839 }
2840
2841 static int
2842 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2843 {
2844         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2845         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2846
2847         if (!ptp)
2848                 return 0;
2849
2850         ptp->tc.nsec += delta;
2851
2852         return 0;
2853 }
2854
2855 static int
2856 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2857 {
2858         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2859         int rc;
2860         uint32_t dir_entries;
2861         uint32_t entry_length;
2862
2863         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2864                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2865                 bp->pdev->addr.devid, bp->pdev->addr.function);
2866
2867         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2868         if (rc != 0)
2869                 return rc;
2870
2871         return dir_entries * entry_length;
2872 }
2873
2874 static int
2875 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2876                 struct rte_dev_eeprom_info *in_eeprom)
2877 {
2878         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2879         uint32_t index;
2880         uint32_t offset;
2881
2882         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2883                 "len = %d\n", bp->pdev->addr.domain,
2884                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2885                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2886
2887         if (in_eeprom->offset == 0) /* special offset value to get directory */
2888                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2889                                                 in_eeprom->data);
2890
2891         index = in_eeprom->offset >> 24;
2892         offset = in_eeprom->offset & 0xffffff;
2893
2894         if (index != 0)
2895                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2896                                            in_eeprom->length, in_eeprom->data);
2897
2898         return 0;
2899 }
2900
2901 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2902 {
2903         switch (dir_type) {
2904         case BNX_DIR_TYPE_CHIMP_PATCH:
2905         case BNX_DIR_TYPE_BOOTCODE:
2906         case BNX_DIR_TYPE_BOOTCODE_2:
2907         case BNX_DIR_TYPE_APE_FW:
2908         case BNX_DIR_TYPE_APE_PATCH:
2909         case BNX_DIR_TYPE_KONG_FW:
2910         case BNX_DIR_TYPE_KONG_PATCH:
2911         case BNX_DIR_TYPE_BONO_FW:
2912         case BNX_DIR_TYPE_BONO_PATCH:
2913                 /* FALLTHROUGH */
2914                 return true;
2915         }
2916
2917         return false;
2918 }
2919
2920 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2921 {
2922         switch (dir_type) {
2923         case BNX_DIR_TYPE_AVS:
2924         case BNX_DIR_TYPE_EXP_ROM_MBA:
2925         case BNX_DIR_TYPE_PCIE:
2926         case BNX_DIR_TYPE_TSCF_UCODE:
2927         case BNX_DIR_TYPE_EXT_PHY:
2928         case BNX_DIR_TYPE_CCM:
2929         case BNX_DIR_TYPE_ISCSI_BOOT:
2930         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2931         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2932                 /* FALLTHROUGH */
2933                 return true;
2934         }
2935
2936         return false;
2937 }
2938
2939 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2940 {
2941         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2942                 bnxt_dir_type_is_other_exec_format(dir_type);
2943 }
2944
2945 static int
2946 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2947                 struct rte_dev_eeprom_info *in_eeprom)
2948 {
2949         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2950         uint8_t index, dir_op;
2951         uint16_t type, ext, ordinal, attr;
2952
2953         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2954                 "len = %d\n", bp->pdev->addr.domain,
2955                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2956                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2957
2958         if (!BNXT_PF(bp)) {
2959                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2960                 return -EINVAL;
2961         }
2962
2963         type = in_eeprom->magic >> 16;
2964
2965         if (type == 0xffff) { /* special value for directory operations */
2966                 index = in_eeprom->magic & 0xff;
2967                 dir_op = in_eeprom->magic >> 8;
2968                 if (index == 0)
2969                         return -EINVAL;
2970                 switch (dir_op) {
2971                 case 0x0e: /* erase */
2972                         if (in_eeprom->offset != ~in_eeprom->magic)
2973                                 return -EINVAL;
2974                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2975                 default:
2976                         return -EINVAL;
2977                 }
2978         }
2979
2980         /* Create or re-write an NVM item: */
2981         if (bnxt_dir_type_is_executable(type) == true)
2982                 return -EOPNOTSUPP;
2983         ext = in_eeprom->magic & 0xffff;
2984         ordinal = in_eeprom->offset >> 16;
2985         attr = in_eeprom->offset & 0xffff;
2986
2987         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2988                                      in_eeprom->data, in_eeprom->length);
2989         return 0;
2990 }
2991
2992 /*
2993  * Initialization
2994  */
2995
2996 static const struct eth_dev_ops bnxt_dev_ops = {
2997         .dev_infos_get = bnxt_dev_info_get_op,
2998         .dev_close = bnxt_dev_close_op,
2999         .dev_configure = bnxt_dev_configure_op,
3000         .dev_start = bnxt_dev_start_op,
3001         .dev_stop = bnxt_dev_stop_op,
3002         .dev_set_link_up = bnxt_dev_set_link_up_op,
3003         .dev_set_link_down = bnxt_dev_set_link_down_op,
3004         .stats_get = bnxt_stats_get_op,
3005         .stats_reset = bnxt_stats_reset_op,
3006         .rx_queue_setup = bnxt_rx_queue_setup_op,
3007         .rx_queue_release = bnxt_rx_queue_release_op,
3008         .tx_queue_setup = bnxt_tx_queue_setup_op,
3009         .tx_queue_release = bnxt_tx_queue_release_op,
3010         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3011         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3012         .reta_update = bnxt_reta_update_op,
3013         .reta_query = bnxt_reta_query_op,
3014         .rss_hash_update = bnxt_rss_hash_update_op,
3015         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3016         .link_update = bnxt_link_update_op,
3017         .promiscuous_enable = bnxt_promiscuous_enable_op,
3018         .promiscuous_disable = bnxt_promiscuous_disable_op,
3019         .allmulticast_enable = bnxt_allmulticast_enable_op,
3020         .allmulticast_disable = bnxt_allmulticast_disable_op,
3021         .mac_addr_add = bnxt_mac_addr_add_op,
3022         .mac_addr_remove = bnxt_mac_addr_remove_op,
3023         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3024         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3025         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3026         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3027         .vlan_filter_set = bnxt_vlan_filter_set_op,
3028         .vlan_offload_set = bnxt_vlan_offload_set_op,
3029         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3030         .mtu_set = bnxt_mtu_set_op,
3031         .mac_addr_set = bnxt_set_default_mac_addr_op,
3032         .xstats_get = bnxt_dev_xstats_get_op,
3033         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3034         .xstats_reset = bnxt_dev_xstats_reset_op,
3035         .fw_version_get = bnxt_fw_version_get,
3036         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3037         .rxq_info_get = bnxt_rxq_info_get_op,
3038         .txq_info_get = bnxt_txq_info_get_op,
3039         .dev_led_on = bnxt_dev_led_on_op,
3040         .dev_led_off = bnxt_dev_led_off_op,
3041         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3042         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3043         .rx_queue_count = bnxt_rx_queue_count_op,
3044         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3045         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3046         .rx_queue_start = bnxt_rx_queue_start,
3047         .rx_queue_stop = bnxt_rx_queue_stop,
3048         .tx_queue_start = bnxt_tx_queue_start,
3049         .tx_queue_stop = bnxt_tx_queue_stop,
3050         .filter_ctrl = bnxt_filter_ctrl_op,
3051         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3052         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3053         .get_eeprom           = bnxt_get_eeprom_op,
3054         .set_eeprom           = bnxt_set_eeprom_op,
3055         .timesync_enable      = bnxt_timesync_enable,
3056         .timesync_disable     = bnxt_timesync_disable,
3057         .timesync_read_time   = bnxt_timesync_read_time,
3058         .timesync_write_time   = bnxt_timesync_write_time,
3059         .timesync_adjust_time = bnxt_timesync_adjust_time,
3060         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3061         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3062 };
3063
3064 static bool bnxt_vf_pciid(uint16_t id)
3065 {
3066         if (id == BROADCOM_DEV_ID_57304_VF ||
3067             id == BROADCOM_DEV_ID_57406_VF ||
3068             id == BROADCOM_DEV_ID_5731X_VF ||
3069             id == BROADCOM_DEV_ID_5741X_VF ||
3070             id == BROADCOM_DEV_ID_57414_VF ||
3071             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3072             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3073                 return true;
3074         return false;
3075 }
3076
3077 bool bnxt_stratus_device(struct bnxt *bp)
3078 {
3079         uint16_t id = bp->pdev->id.device_id;
3080
3081         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3082             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3083             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3084                 return true;
3085         return false;
3086 }
3087
3088 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3089 {
3090         struct bnxt *bp = eth_dev->data->dev_private;
3091         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3092         int rc;
3093
3094         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3095         if (!pci_dev->mem_resource[0].addr) {
3096                 PMD_DRV_LOG(ERR,
3097                         "Cannot find PCI device base address, aborting\n");
3098                 rc = -ENODEV;
3099                 goto init_err_disable;
3100         }
3101
3102         bp->eth_dev = eth_dev;
3103         bp->pdev = pci_dev;
3104
3105         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3106         if (!bp->bar0) {
3107                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3108                 rc = -ENOMEM;
3109                 goto init_err_release;
3110         }
3111
3112         if (!pci_dev->mem_resource[2].addr) {
3113                 PMD_DRV_LOG(ERR,
3114                             "Cannot find PCI device BAR 2 address, aborting\n");
3115                 rc = -ENODEV;
3116                 goto init_err_release;
3117         } else {
3118                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3119         }
3120
3121         return 0;
3122
3123 init_err_release:
3124         if (bp->bar0)
3125                 bp->bar0 = NULL;
3126         if (bp->doorbell_base)
3127                 bp->doorbell_base = NULL;
3128
3129 init_err_disable:
3130
3131         return rc;
3132 }
3133
3134
3135 #define ALLOW_FUNC(x)   \
3136         { \
3137                 typeof(x) arg = (x); \
3138                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3139                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3140         }
3141 static int
3142 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3143 {
3144         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3145         char mz_name[RTE_MEMZONE_NAMESIZE];
3146         const struct rte_memzone *mz = NULL;
3147         static int version_printed;
3148         uint32_t total_alloc_len;
3149         rte_iova_t mz_phys_addr;
3150         struct bnxt *bp;
3151         int rc;
3152
3153         if (version_printed++ == 0)
3154                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3155
3156         rte_eth_copy_pci_info(eth_dev, pci_dev);
3157
3158         bp = eth_dev->data->dev_private;
3159
3160         bp->dev_stopped = 1;
3161
3162         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3163                 goto skip_init;
3164
3165         if (bnxt_vf_pciid(pci_dev->id.device_id))
3166                 bp->flags |= BNXT_FLAG_VF;
3167
3168         rc = bnxt_init_board(eth_dev);
3169         if (rc) {
3170                 PMD_DRV_LOG(ERR,
3171                         "Board initialization failed rc: %x\n", rc);
3172                 goto error;
3173         }
3174 skip_init:
3175         eth_dev->dev_ops = &bnxt_dev_ops;
3176         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3177         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3178         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3179                 return 0;
3180
3181         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3182                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3183                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3184                          pci_dev->addr.bus, pci_dev->addr.devid,
3185                          pci_dev->addr.function, "rx_port_stats");
3186                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3187                 mz = rte_memzone_lookup(mz_name);
3188                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3189                                 sizeof(struct rx_port_stats) + 512);
3190                 if (!mz) {
3191                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3192                                         SOCKET_ID_ANY,
3193                                         RTE_MEMZONE_2MB |
3194                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3195                                         RTE_MEMZONE_IOVA_CONTIG);
3196                         if (mz == NULL)
3197                                 return -ENOMEM;
3198                 }
3199                 memset(mz->addr, 0, mz->len);
3200                 mz_phys_addr = mz->iova;
3201                 if ((unsigned long)mz->addr == mz_phys_addr) {
3202                         PMD_DRV_LOG(WARNING,
3203                                 "Memzone physical address same as virtual.\n");
3204                         PMD_DRV_LOG(WARNING,
3205                                 "Using rte_mem_virt2iova()\n");
3206                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3207                         if (mz_phys_addr == 0) {
3208                                 PMD_DRV_LOG(ERR,
3209                                 "unable to map address to physical memory\n");
3210                                 return -ENOMEM;
3211                         }
3212                 }
3213
3214                 bp->rx_mem_zone = (const void *)mz;
3215                 bp->hw_rx_port_stats = mz->addr;
3216                 bp->hw_rx_port_stats_map = mz_phys_addr;
3217
3218                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3219                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3220                          pci_dev->addr.bus, pci_dev->addr.devid,
3221                          pci_dev->addr.function, "tx_port_stats");
3222                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3223                 mz = rte_memzone_lookup(mz_name);
3224                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3225                                 sizeof(struct tx_port_stats) + 512);
3226                 if (!mz) {
3227                         mz = rte_memzone_reserve(mz_name,
3228                                         total_alloc_len,
3229                                         SOCKET_ID_ANY,
3230                                         RTE_MEMZONE_2MB |
3231                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3232                                         RTE_MEMZONE_IOVA_CONTIG);
3233                         if (mz == NULL)
3234                                 return -ENOMEM;
3235                 }
3236                 memset(mz->addr, 0, mz->len);
3237                 mz_phys_addr = mz->iova;
3238                 if ((unsigned long)mz->addr == mz_phys_addr) {
3239                         PMD_DRV_LOG(WARNING,
3240                                 "Memzone physical address same as virtual.\n");
3241                         PMD_DRV_LOG(WARNING,
3242                                 "Using rte_mem_virt2iova()\n");
3243                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3244                         if (mz_phys_addr == 0) {
3245                                 PMD_DRV_LOG(ERR,
3246                                 "unable to map address to physical memory\n");
3247                                 return -ENOMEM;
3248                         }
3249                 }
3250
3251                 bp->tx_mem_zone = (const void *)mz;
3252                 bp->hw_tx_port_stats = mz->addr;
3253                 bp->hw_tx_port_stats_map = mz_phys_addr;
3254
3255                 bp->flags |= BNXT_FLAG_PORT_STATS;
3256         }
3257
3258         rc = bnxt_alloc_hwrm_resources(bp);
3259         if (rc) {
3260                 PMD_DRV_LOG(ERR,
3261                         "hwrm resource allocation failure rc: %x\n", rc);
3262                 goto error_free;
3263         }
3264         rc = bnxt_hwrm_ver_get(bp);
3265         if (rc)
3266                 goto error_free;
3267         rc = bnxt_hwrm_queue_qportcfg(bp);
3268         if (rc) {
3269                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3270                 goto error_free;
3271         }
3272
3273         rc = bnxt_hwrm_func_qcfg(bp);
3274         if (rc) {
3275                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3276                 goto error_free;
3277         }
3278
3279         /* Get the MAX capabilities for this function */
3280         rc = bnxt_hwrm_func_qcaps(bp);
3281         if (rc) {
3282                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3283                 goto error_free;
3284         }
3285         if (bp->max_tx_rings == 0) {
3286                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3287                 rc = -EBUSY;
3288                 goto error_free;
3289         }
3290         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3291                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3292         if (eth_dev->data->mac_addrs == NULL) {
3293                 PMD_DRV_LOG(ERR,
3294                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3295                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3296                 rc = -ENOMEM;
3297                 goto error_free;
3298         }
3299
3300         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3301                 PMD_DRV_LOG(ERR,
3302                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3303                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3304                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3305                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3306                 rc = -EINVAL;
3307                 goto error_free;
3308         }
3309         /* Copy the permanent MAC from the qcap response address now. */
3310         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3311         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3312
3313         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3314                 /* 1 ring is for default completion ring */
3315                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3316                 rc = -ENOSPC;
3317                 goto error_free;
3318         }
3319
3320         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3321                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3322         if (!bp->grp_info) {
3323                 PMD_DRV_LOG(ERR,
3324                         "Failed to alloc %zu bytes to store group info table\n",
3325                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3326                 rc = -ENOMEM;
3327                 goto error_free;
3328         }
3329
3330         /* Forward all requests if firmware is new enough */
3331         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3332             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3333             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3334                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3335         } else {
3336                 PMD_DRV_LOG(WARNING,
3337                         "Firmware too old for VF mailbox functionality\n");
3338                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3339         }
3340
3341         /*
3342          * The following are used for driver cleanup.  If we disallow these,
3343          * VF drivers can't clean up cleanly.
3344          */
3345         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3346         ALLOW_FUNC(HWRM_VNIC_FREE);
3347         ALLOW_FUNC(HWRM_RING_FREE);
3348         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3349         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3350         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3351         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3352         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3353         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3354         rc = bnxt_hwrm_func_driver_register(bp);
3355         if (rc) {
3356                 PMD_DRV_LOG(ERR,
3357                         "Failed to register driver");
3358                 rc = -EBUSY;
3359                 goto error_free;
3360         }
3361
3362         PMD_DRV_LOG(INFO,
3363                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3364                 pci_dev->mem_resource[0].phys_addr,
3365                 pci_dev->mem_resource[0].addr);
3366
3367         rc = bnxt_hwrm_func_reset(bp);
3368         if (rc) {
3369                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3370                 rc = -EIO;
3371                 goto error_free;
3372         }
3373
3374         if (BNXT_PF(bp)) {
3375                 //if (bp->pf.active_vfs) {
3376                         // TODO: Deallocate VF resources?
3377                 //}
3378                 if (bp->pdev->max_vfs) {
3379                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3380                         if (rc) {
3381                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3382                                 goto error_free;
3383                         }
3384                 } else {
3385                         rc = bnxt_hwrm_allocate_pf_only(bp);
3386                         if (rc) {
3387                                 PMD_DRV_LOG(ERR,
3388                                         "Failed to allocate PF resources\n");
3389                                 goto error_free;
3390                         }
3391                 }
3392         }
3393
3394         bnxt_hwrm_port_led_qcaps(bp);
3395
3396         rc = bnxt_setup_int(bp);
3397         if (rc)
3398                 goto error_free;
3399
3400         rc = bnxt_alloc_mem(bp);
3401         if (rc)
3402                 goto error_free_int;
3403
3404         rc = bnxt_request_int(bp);
3405         if (rc)
3406                 goto error_free_int;
3407
3408         bnxt_enable_int(bp);
3409         bnxt_init_nic(bp);
3410
3411         return 0;
3412
3413 error_free_int:
3414         bnxt_disable_int(bp);
3415         bnxt_hwrm_func_buf_unrgtr(bp);
3416         bnxt_free_int(bp);
3417         bnxt_free_mem(bp);
3418 error_free:
3419         bnxt_dev_uninit(eth_dev);
3420 error:
3421         return rc;
3422 }
3423
3424 static int
3425 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3426 {
3427         struct bnxt *bp = eth_dev->data->dev_private;
3428         int rc;
3429
3430         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3431                 return -EPERM;
3432
3433         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3434         bnxt_disable_int(bp);
3435         bnxt_free_int(bp);
3436         bnxt_free_mem(bp);
3437         if (eth_dev->data->mac_addrs != NULL) {
3438                 rte_free(eth_dev->data->mac_addrs);
3439                 eth_dev->data->mac_addrs = NULL;
3440         }
3441         if (bp->grp_info != NULL) {
3442                 rte_free(bp->grp_info);
3443                 bp->grp_info = NULL;
3444         }
3445         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3446         bnxt_free_hwrm_resources(bp);
3447
3448         if (bp->tx_mem_zone) {
3449                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3450                 bp->tx_mem_zone = NULL;
3451         }
3452
3453         if (bp->rx_mem_zone) {
3454                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3455                 bp->rx_mem_zone = NULL;
3456         }
3457
3458         if (bp->dev_stopped == 0)
3459                 bnxt_dev_close_op(eth_dev);
3460         if (bp->pf.vf_info)
3461                 rte_free(bp->pf.vf_info);
3462         eth_dev->dev_ops = NULL;
3463         eth_dev->rx_pkt_burst = NULL;
3464         eth_dev->tx_pkt_burst = NULL;
3465
3466         return rc;
3467 }
3468
3469 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3470         struct rte_pci_device *pci_dev)
3471 {
3472         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3473                 bnxt_dev_init);
3474 }
3475
3476 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3477 {
3478         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3479 }
3480
3481 static struct rte_pci_driver bnxt_rte_pmd = {
3482         .id_table = bnxt_pci_id_map,
3483         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3484                 RTE_PCI_DRV_INTR_LSC,
3485         .probe = bnxt_pci_probe,
3486         .remove = bnxt_pci_remove,
3487 };
3488
3489 static bool
3490 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3491 {
3492         if (strcmp(dev->device->driver->name, drv->driver.name))
3493                 return false;
3494
3495         return true;
3496 }
3497
3498 bool is_bnxt_supported(struct rte_eth_dev *dev)
3499 {
3500         return is_device_supported(dev, &bnxt_rte_pmd);
3501 }
3502
3503 RTE_INIT(bnxt_init_log);
3504 static void
3505 bnxt_init_log(void)
3506 {
3507         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3508         if (bnxt_logtype_driver >= 0)
3509                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3510 }
3511
3512 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3513 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3514 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");