drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
 130         { .vendor_id = 0, /* sentinel */ },
 131 };
 132
 133 #define BNXT_ETH_RSS_SUPPORT (  \
 134         ETH_RSS_IPV4 |          \
 135         ETH_RSS_NONFRAG_IPV4_TCP |      \
 136         ETH_RSS_NONFRAG_IPV4_UDP |      \
 137         ETH_RSS_IPV6 |          \
 138         ETH_RSS_NONFRAG_IPV6_TCP |      \
 139         ETH_RSS_NONFRAG_IPV6_UDP)
 140
 141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 142                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 143                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 144                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_TSO | \
 146                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 147                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 148                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 152
 153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 154                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 155                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 156                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 157                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 158                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 160                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 161                                      DEV_RX_OFFLOAD_TCP_LRO)
 162
 163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 167
 168 /***********************/
 169
 170 /*
 171  * High level utility functions
 172  */
 173
 174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 175 {
 176         if (!BNXT_CHIP_THOR(bp))
 177                 return 1;
 178
 179         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 180                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 181                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 182 }
 183
 184 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 185 {
 186         if (!BNXT_CHIP_THOR(bp))
 187                 return HW_HASH_INDEX_SIZE;
 188
 189         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 190 }
 191
 192 static void bnxt_free_mem(struct bnxt *bp)
 193 {
 194         bnxt_free_filter_mem(bp);
 195         bnxt_free_vnic_attributes(bp);
 196         bnxt_free_vnic_mem(bp);
 197
 198         bnxt_free_stats(bp);
 199         bnxt_free_tx_rings(bp);
 200         bnxt_free_rx_rings(bp);
 201 }
 202
 203 static int bnxt_alloc_mem(struct bnxt *bp)
 204 {
 205         int rc;
 206
 207         rc = bnxt_alloc_vnic_mem(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_vnic_attributes(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_filter_mem(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         return 0;
 220
 221 alloc_mem_err:
 222         bnxt_free_mem(bp);
 223         return rc;
 224 }
 225
 226 static int bnxt_init_chip(struct bnxt *bp)
 227 {
 228         struct bnxt_rx_queue *rxq;
 229         struct rte_eth_link new;
 230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 231         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 233         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 234         uint32_t intr_vector = 0;
 235         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 236         uint32_t vec = BNXT_MISC_VEC_ID;
 237         unsigned int i, j;
 238         int rc;
 239
 240         /* disable uio/vfio intr/eventfd mapping */
 241         rte_intr_disable(intr_handle);
 242
 243         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 244                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 245                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 246                 bp->flags |= BNXT_FLAG_JUMBO;
 247         } else {
 248                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 249                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 250                 bp->flags &= ~BNXT_FLAG_JUMBO;
 251         }
 252
 253         /* THOR does not support ring groups.
 254          * But we will use the array to save RSS context IDs.
 255          */
 256         if (BNXT_CHIP_THOR(bp))
 257                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 258
 259         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 260         if (rc) {
 261                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 262                 goto err_out;
 263         }
 264
 265         rc = bnxt_alloc_hwrm_rings(bp);
 266         if (rc) {
 267                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 268                 goto err_out;
 269         }
 270
 271         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 272         if (rc) {
 273                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 274                 goto err_out;
 275         }
 276
 277         rc = bnxt_mq_rx_configure(bp);
 278         if (rc) {
 279                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 280                 goto err_out;
 281         }
 282
 283         /* VNIC configuration */
 284         for (i = 0; i < bp->nr_vnics; i++) {
 285                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 286                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 287                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 288
 289                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 290                 if (!vnic->fw_grp_ids) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "Failed to alloc %d bytes for group ids\n",
 293                                     size);
 294                         rc = -ENOMEM;
 295                         goto err_out;
 296                 }
 297                 memset(vnic->fw_grp_ids, -1, size);
 298
 299                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 300                             i, vnic, vnic->fw_grp_ids);
 301
 302                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 303                 if (rc) {
 304                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 305                                 i, rc);
 306                         goto err_out;
 307                 }
 308
 309                 /* Alloc RSS context only if RSS mode is enabled */
 310                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 311                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 312
 313                         rc = 0;
 314                         for (j = 0; j < nr_ctxs; j++) {
 315                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 316                                 if (rc)
 317                                         break;
 318                         }
 319                         if (rc) {
 320                                 PMD_DRV_LOG(ERR,
 321                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 322                                   i, j, rc);
 323                                 goto err_out;
 324                         }
 325                         vnic->num_lb_ctxts = nr_ctxs;
 326                 }
 327
 328                 /*
 329                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 330                  * setting is not available at this time, it will not be
 331                  * configured correctly in the CFA.
 332                  */
 333                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 334                         vnic->vlan_strip = true;
 335                 else
 336                         vnic->vlan_strip = false;
 337
 338                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 339                 if (rc) {
 340                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                                 i, rc);
 342                         goto err_out;
 343                 }
 344
 345                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 346                 if (rc) {
 347                         PMD_DRV_LOG(ERR,
 348                                 "HWRM vnic %d filter failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 for (j = 0; j < bp->rx_nr_rings; j++) {
 354                         rxq = bp->eth_dev->data->rx_queues[j];
 355
 356                         PMD_DRV_LOG(DEBUG,
 357                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 358                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 359
 360                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 361                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 362                 }
 363
 364                 rc = bnxt_vnic_rss_configure(bp, vnic);
 365                 if (rc) {
 366                         PMD_DRV_LOG(ERR,
 367                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 368                         goto err_out;
 369                 }
 370
 371                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 372
 373                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 374                     DEV_RX_OFFLOAD_TCP_LRO)
 375                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 376                 else
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 378         }
 379         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 380         if (rc) {
 381                 PMD_DRV_LOG(ERR,
 382                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 383                 goto err_out;
 384         }
 385
 386         /* check and configure queue intr-vector mapping */
 387         if ((rte_intr_cap_multiple(intr_handle) ||
 388              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 389             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 390                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 391                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 392                 if (intr_vector > bp->rx_cp_nr_rings) {
 393                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 394                                         bp->rx_cp_nr_rings);
 395                         return -ENOTSUP;
 396                 }
 397                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 398                 if (rc)
 399                         return rc;
 400         }
 401
 402         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 403                 intr_handle->intr_vec =
 404                         rte_zmalloc("intr_vec",
 405                                     bp->eth_dev->data->nb_rx_queues *
 406                                     sizeof(int), 0);
 407                 if (intr_handle->intr_vec == NULL) {
 408                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 409                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 410                         rc = -ENOMEM;
 411                         goto err_disable;
 412                 }
 413                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 414                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 415                          intr_handle->intr_vec, intr_handle->nb_efd,
 416                         intr_handle->max_intr);
 417                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 418                      queue_id++) {
 419                         intr_handle->intr_vec[queue_id] = vec;
 420                         if (vec < base + intr_handle->nb_efd - 1)
 421                                 vec++;
 422                 }
 423         }
 424
 425         /* enable uio/vfio intr/eventfd mapping */
 426         rc = rte_intr_enable(intr_handle);
 427         if (rc)
 428                 goto err_free;
 429
 430         rc = bnxt_get_hwrm_link_config(bp, &new);
 431         if (rc) {
 432                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 433                 goto err_free;
 434         }
 435
 436         if (!bp->link_info.link_up) {
 437                 rc = bnxt_set_hwrm_link_config(bp, true);
 438                 if (rc) {
 439                         PMD_DRV_LOG(ERR,
 440                                 "HWRM link config failure rc: %x\n", rc);
 441                         goto err_free;
 442                 }
 443         }
 444         bnxt_print_link_info(bp->eth_dev);
 445
 446         return 0;
 447
 448 err_free:
 449         rte_free(intr_handle->intr_vec);
 450 err_disable:
 451         rte_intr_efd_disable(intr_handle);
 452 err_out:
 453         /* Some of the error status returned by FW may not be from errno.h */
 454         if (rc > 0)
 455                 rc = -EIO;
 456
 457         return rc;
 458 }
 459
 460 static int bnxt_shutdown_nic(struct bnxt *bp)
 461 {
 462         bnxt_free_all_hwrm_resources(bp);
 463         bnxt_free_all_filters(bp);
 464         bnxt_free_all_vnics(bp);
 465         return 0;
 466 }
 467
 468 static int bnxt_init_nic(struct bnxt *bp)
 469 {
 470         int rc;
 471
 472         if (BNXT_HAS_RING_GRPS(bp)) {
 473                 rc = bnxt_init_ring_grps(bp);
 474                 if (rc)
 475                         return rc;
 476         }
 477
 478         bnxt_init_vnics(bp);
 479         bnxt_init_filters(bp);
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Device configuration and status function
 486  */
 487
 488 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 489                                   struct rte_eth_dev_info *dev_info)
 490 {
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494
 495         /* MAC Specifics */
 496         dev_info->max_mac_addrs = bp->max_l2_ctx;
 497         dev_info->max_hash_mac_addrs = 0;
 498
 499         /* PF/VF specifics */
 500         if (BNXT_PF(bp))
 501                 dev_info->max_vfs = bp->pdev->max_vfs;
 502         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 503         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 504         dev_info->max_rx_queues = max_rx_rings;
 505         dev_info->max_tx_queues = max_rx_rings;
 506         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 507         dev_info->hash_key_size = 40;
 508         max_vnics = bp->max_vnics;
 509
 510         /* Fast path specifics */
 511         dev_info->min_rx_bufsize = 1;
 512         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 513                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 514
 515         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 516         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 517                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 518         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 519         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 520
 521         /* *INDENT-OFF* */
 522         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 523                 .rx_thresh = {
 524                         .pthresh = 8,
 525                         .hthresh = 8,
 526                         .wthresh = 0,
 527                 },
 528                 .rx_free_thresh = 32,
 529                 /* If no descriptors available, pkts are dropped by default */
 530                 .rx_drop_en = 1,
 531         };
 532
 533         dev_info->default_txconf = (struct rte_eth_txconf) {
 534                 .tx_thresh = {
 535                         .pthresh = 32,
 536                         .hthresh = 0,
 537                         .wthresh = 0,
 538                 },
 539                 .tx_free_thresh = 32,
 540                 .tx_rs_thresh = 32,
 541         };
 542         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 543
 544         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 545         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 546         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 547         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 548         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 549
 550         /* *INDENT-ON* */
 551
 552         /*
 553          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 554          *       need further investigation.
 555          */
 556
 557         /* VMDq resources */
 558         vpool = 64; /* ETH_64_POOLS */
 559         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 560         for (i = 0; i < 4; vpool >>= 1, i++) {
 561                 if (max_vnics > vpool) {
 562                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 563                                 if (dev_info->max_rx_queues > vrxq) {
 564                                         if (vpool > vrxq)
 565                                                 vpool = vrxq;
 566                                         goto found;
 567                                 }
 568                         }
 569                         /* Not enough resources to support VMDq */
 570                         break;
 571                 }
 572         }
 573         /* Not enough resources to support VMDq */
 574         vpool = 0;
 575         vrxq = 0;
 576 found:
 577         dev_info->max_vmdq_pools = vpool;
 578         dev_info->vmdq_queue_num = vrxq;
 579
 580         dev_info->vmdq_pool_base = 0;
 581         dev_info->vmdq_queue_base = 0;
 582 }
 583
 584 /* Configure the device based on the configuration provided */
 585 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 586 {
 587         struct bnxt *bp = eth_dev->data->dev_private;
 588         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 589         int rc;
 590
 591         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 592         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 593         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 594         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 595
 596         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 597                 rc = bnxt_hwrm_check_vf_rings(bp);
 598                 if (rc) {
 599                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 600                         return -ENOSPC;
 601                 }
 602
 603                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 604                 if (rc) {
 605                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 606                         return -ENOSPC;
 607                 }
 608         } else {
 609                 /* legacy driver needs to get updated values */
 610                 rc = bnxt_hwrm_func_qcaps(bp);
 611                 if (rc) {
 612                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 613                         return rc;
 614                 }
 615         }
 616
 617         /* Inherit new configurations */
 618         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 619             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 620             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 621             bp->max_cp_rings ||
 622             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 623             bp->max_stat_ctx)
 624                 goto resource_error;
 625
 626         if (BNXT_HAS_RING_GRPS(bp) &&
 627             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 628                 goto resource_error;
 629
 630         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 631             bp->max_vnics < eth_dev->data->nb_rx_queues)
 632                 goto resource_error;
 633
 634         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 635         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 636
 637         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 638                 eth_dev->data->mtu =
 639                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 640                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 641                         BNXT_NUM_VLANS;
 642                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 643         }
 644         return 0;
 645
 646 resource_error:
 647         PMD_DRV_LOG(ERR,
 648                     "Insufficient resources to support requested config\n");
 649         PMD_DRV_LOG(ERR,
 650                     "Num Queues Requested: Tx %d, Rx %d\n",
 651                     eth_dev->data->nb_tx_queues,
 652                     eth_dev->data->nb_rx_queues);
 653         PMD_DRV_LOG(ERR,
 654                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 655                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 656                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 657         return -ENOSPC;
 658 }
 659
 660 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 661 {
 662         struct rte_eth_link *link = &eth_dev->data->dev_link;
 663
 664         if (link->link_status)
 665                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 666                         eth_dev->data->port_id,
 667                         (uint32_t)link->link_speed,
 668                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 669                         ("full-duplex") : ("half-duplex\n"));
 670         else
 671                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 672                         eth_dev->data->port_id);
 673 }
 674
 675 /*
 676  * Determine whether the current configuration requires support for scattered
 677  * receive; return 1 if scattered receive is required and 0 if not.
 678  */
 679 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 680 {
 681         uint16_t buf_size;
 682         int i;
 683
 684         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 685                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 686
 687                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 688                                       RTE_PKTMBUF_HEADROOM);
 689                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 690                         return 1;
 691         }
 692         return 0;
 693 }
 694
 695 static eth_rx_burst_t
 696 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 697 {
 698 #ifdef RTE_ARCH_X86
 699         /*
 700          * Vector mode receive can be enabled only if scatter rx is not
 701          * in use and rx offloads are limited to VLAN stripping and
 702          * CRC stripping.
 703          */
 704         if (!eth_dev->data->scattered_rx &&
 705             !(eth_dev->data->dev_conf.rxmode.offloads &
 706               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 707                 DEV_RX_OFFLOAD_KEEP_CRC |
 708                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 709                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 710                 DEV_RX_OFFLOAD_UDP_CKSUM |
 711                 DEV_RX_OFFLOAD_TCP_CKSUM |
 712                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 713                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 714                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 715                             eth_dev->data->port_id);
 716                 return bnxt_recv_pkts_vec;
 717         }
 718         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 719                     eth_dev->data->port_id);
 720         PMD_DRV_LOG(INFO,
 721                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 722                     eth_dev->data->port_id,
 723                     eth_dev->data->scattered_rx,
 724                     eth_dev->data->dev_conf.rxmode.offloads);
 725 #endif
 726         return bnxt_recv_pkts;
 727 }
 728
 729 static eth_tx_burst_t
 730 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 731 {
 732 #ifdef RTE_ARCH_X86
 733         /*
 734          * Vector mode receive can be enabled only if scatter tx is not
 735          * in use and tx offloads other than VLAN insertion are not
 736          * in use.
 737          */
 738         if (!eth_dev->data->scattered_rx &&
 739             !(eth_dev->data->dev_conf.txmode.offloads &
 740               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 741                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 742                             eth_dev->data->port_id);
 743                 return bnxt_xmit_pkts_vec;
 744         }
 745         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 746                     eth_dev->data->port_id);
 747         PMD_DRV_LOG(INFO,
 748                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 749                     eth_dev->data->port_id,
 750                     eth_dev->data->scattered_rx,
 751                     eth_dev->data->dev_conf.txmode.offloads);
 752 #endif
 753         return bnxt_xmit_pkts;
 754 }
 755
 756 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 757 {
 758         struct bnxt *bp = eth_dev->data->dev_private;
 759         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 760         int vlan_mask = 0;
 761         int rc;
 762
 763         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 764                 PMD_DRV_LOG(ERR,
 765                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 766                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 767         }
 768
 769         rc = bnxt_init_chip(bp);
 770         if (rc)
 771                 goto error;
 772
 773         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 774
 775         bnxt_link_update_op(eth_dev, 1);
 776
 777         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 778                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 779         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 780                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 781         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 782         if (rc)
 783                 goto error;
 784
 785         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 786         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 787         bnxt_enable_int(bp);
 788         bp->flags |= BNXT_FLAG_INIT_DONE;
 789         bp->dev_stopped = 0;
 790         return 0;
 791
 792 error:
 793         bnxt_shutdown_nic(bp);
 794         bnxt_free_tx_mbufs(bp);
 795         bnxt_free_rx_mbufs(bp);
 796         return rc;
 797 }
 798
 799 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 800 {
 801         struct bnxt *bp = eth_dev->data->dev_private;
 802         int rc = 0;
 803
 804         if (!bp->link_info.link_up)
 805                 rc = bnxt_set_hwrm_link_config(bp, true);
 806         if (!rc)
 807                 eth_dev->data->dev_link.link_status = 1;
 808
 809         bnxt_print_link_info(eth_dev);
 810         return 0;
 811 }
 812
 813 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 814 {
 815         struct bnxt *bp = eth_dev->data->dev_private;
 816
 817         eth_dev->data->dev_link.link_status = 0;
 818         bnxt_set_hwrm_link_config(bp, false);
 819         bp->link_info.link_up = 0;
 820
 821         return 0;
 822 }
 823
 824 /* Unload the driver, release resources */
 825 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 826 {
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 829         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 830
 831         bnxt_disable_int(bp);
 832
 833         /* disable uio/vfio intr/eventfd mapping */
 834         rte_intr_disable(intr_handle);
 835
 836         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 837         if (bp->eth_dev->data->dev_started) {
 838                 /* TBD: STOP HW queues DMA */
 839                 eth_dev->data->dev_link.link_status = 0;
 840         }
 841         bnxt_set_hwrm_link_config(bp, false);
 842
 843         /* Clean queue intr-vector mapping */
 844         rte_intr_efd_disable(intr_handle);
 845         if (intr_handle->intr_vec != NULL) {
 846                 rte_free(intr_handle->intr_vec);
 847                 intr_handle->intr_vec = NULL;
 848         }
 849
 850         bnxt_hwrm_port_clr_stats(bp);
 851         bnxt_free_tx_mbufs(bp);
 852         bnxt_free_rx_mbufs(bp);
 853         bnxt_shutdown_nic(bp);
 854         bp->dev_stopped = 1;
 855 }
 856
 857 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 858 {
 859         struct bnxt *bp = eth_dev->data->dev_private;
 860
 861         if (bp->dev_stopped == 0)
 862                 bnxt_dev_stop_op(eth_dev);
 863
 864         if (eth_dev->data->mac_addrs != NULL) {
 865                 rte_free(eth_dev->data->mac_addrs);
 866                 eth_dev->data->mac_addrs = NULL;
 867         }
 868         if (bp->grp_info != NULL) {
 869                 rte_free(bp->grp_info);
 870                 bp->grp_info = NULL;
 871         }
 872
 873         bnxt_dev_uninit(eth_dev);
 874 }
 875
 876 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 877                                     uint32_t index)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 881         struct bnxt_vnic_info *vnic;
 882         struct bnxt_filter_info *filter, *temp_filter;
 883         uint32_t i;
 884
 885         /*
 886          * Loop through all VNICs from the specified filter flow pools to
 887          * remove the corresponding MAC addr filter
 888          */
 889         for (i = 0; i < bp->nr_vnics; i++) {
 890                 if (!(pool_mask & (1ULL << i)))
 891                         continue;
 892
 893                 vnic = &bp->vnic_info[i];
 894                 filter = STAILQ_FIRST(&vnic->filter);
 895                 while (filter) {
 896                         temp_filter = STAILQ_NEXT(filter, next);
 897                         if (filter->mac_index == index) {
 898                                 STAILQ_REMOVE(&vnic->filter, filter,
 899                                                 bnxt_filter_info, next);
 900                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 901                                 filter->mac_index = INVALID_MAC_INDEX;
 902                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 903                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 904                                                    filter, next);
 905                         }
 906                         filter = temp_filter;
 907                 }
 908         }
 909 }
 910
 911 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 912                                 struct rte_ether_addr *mac_addr,
 913                                 uint32_t index, uint32_t pool)
 914 {
 915         struct bnxt *bp = eth_dev->data->dev_private;
 916         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 917         struct bnxt_filter_info *filter;
 918
 919         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 920                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 921                 return -ENOTSUP;
 922         }
 923
 924         if (!vnic) {
 925                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 926                 return -EINVAL;
 927         }
 928         /* Attach requested MAC address to the new l2_filter */
 929         STAILQ_FOREACH(filter, &vnic->filter, next) {
 930                 if (filter->mac_index == index) {
 931                         PMD_DRV_LOG(ERR,
 932                                 "MAC addr already existed for pool %d\n", pool);
 933                         return 0;
 934                 }
 935         }
 936         filter = bnxt_alloc_filter(bp);
 937         if (!filter) {
 938                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 939                 return -ENODEV;
 940         }
 941         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 942         filter->mac_index = index;
 943         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 944         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 945 }
 946
 947 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 948 {
 949         int rc = 0;
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         struct rte_eth_link new;
 952         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 953
 954         memset(&new, 0, sizeof(new));
 955         do {
 956                 /* Retrieve link info from hardware */
 957                 rc = bnxt_get_hwrm_link_config(bp, &new);
 958                 if (rc) {
 959                         new.link_speed = ETH_LINK_SPEED_100M;
 960                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 961                         PMD_DRV_LOG(ERR,
 962                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 963                         goto out;
 964                 }
 965                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 966
 967                 if (!wait_to_complete)
 968                         break;
 969         } while (!new.link_status && cnt--);
 970
 971 out:
 972         /* Timed out or success */
 973         if (new.link_status != eth_dev->data->dev_link.link_status ||
 974         new.link_speed != eth_dev->data->dev_link.link_speed) {
 975                 memcpy(&eth_dev->data->dev_link, &new,
 976                         sizeof(struct rte_eth_link));
 977
 978                 _rte_eth_dev_callback_process(eth_dev,
 979                                               RTE_ETH_EVENT_INTR_LSC,
 980                                               NULL);
 981
 982                 bnxt_print_link_info(eth_dev);
 983         }
 984
 985         return rc;
 986 }
 987
 988 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 989 {
 990         struct bnxt *bp = eth_dev->data->dev_private;
 991         struct bnxt_vnic_info *vnic;
 992
 993         if (bp->vnic_info == NULL)
 994                 return;
 995
 996         vnic = &bp->vnic_info[0];
 997
 998         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 999         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1000 }
1001
1002 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1003 {
1004         struct bnxt *bp = eth_dev->data->dev_private;
1005         struct bnxt_vnic_info *vnic;
1006
1007         if (bp->vnic_info == NULL)
1008                 return;
1009
1010         vnic = &bp->vnic_info[0];
1011
1012         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1013         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1014 }
1015
1016 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1017 {
1018         struct bnxt *bp = eth_dev->data->dev_private;
1019         struct bnxt_vnic_info *vnic;
1020
1021         if (bp->vnic_info == NULL)
1022                 return;
1023
1024         vnic = &bp->vnic_info[0];
1025
1026         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1027         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1028 }
1029
1030 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1031 {
1032         struct bnxt *bp = eth_dev->data->dev_private;
1033         struct bnxt_vnic_info *vnic;
1034
1035         if (bp->vnic_info == NULL)
1036                 return;
1037
1038         vnic = &bp->vnic_info[0];
1039
1040         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1041         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1042 }
1043
1044 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1045 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1046 {
1047         if (qid >= bp->rx_nr_rings)
1048                 return NULL;
1049
1050         return bp->eth_dev->data->rx_queues[qid];
1051 }
1052
1053 /* Return rxq corresponding to a given rss table ring/group ID. */
1054 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1055 {
1056         struct bnxt_rx_queue *rxq;
1057         unsigned int i;
1058
1059         if (!BNXT_HAS_RING_GRPS(bp)) {
1060                 for (i = 0; i < bp->rx_nr_rings; i++) {
1061                         rxq = bp->eth_dev->data->rx_queues[i];
1062                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1063                                 return rxq->index;
1064                 }
1065         } else {
1066                 for (i = 0; i < bp->rx_nr_rings; i++) {
1067                         if (bp->grp_info[i].fw_grp_id == fwr)
1068                                 return i;
1069                 }
1070         }
1071
1072         return INVALID_HW_RING_ID;
1073 }
1074
1075 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1076                             struct rte_eth_rss_reta_entry64 *reta_conf,
1077                             uint16_t reta_size)
1078 {
1079         struct bnxt *bp = eth_dev->data->dev_private;
1080         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1081         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1082         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1083         uint16_t idx, sft;
1084         int i;
1085
1086         if (!vnic->rss_table)
1087                 return -EINVAL;
1088
1089         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1090                 return -EINVAL;
1091
1092         if (reta_size != tbl_size) {
1093                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1094                         "(%d) must equal the size supported by the hardware "
1095                         "(%d)\n", reta_size, tbl_size);
1096                 return -EINVAL;
1097         }
1098
1099         for (i = 0; i < reta_size; i++) {
1100                 struct bnxt_rx_queue *rxq;
1101
1102                 idx = i / RTE_RETA_GROUP_SIZE;
1103                 sft = i % RTE_RETA_GROUP_SIZE;
1104
1105                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1106                         continue;
1107
1108                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1109                 if (!rxq) {
1110                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1111                         return -EINVAL;
1112                 }
1113
1114                 if (BNXT_CHIP_THOR(bp)) {
1115                         vnic->rss_table[i * 2] =
1116                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1117                         vnic->rss_table[i * 2 + 1] =
1118                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1119                 } else {
1120                         vnic->rss_table[i] =
1121                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1122                 }
1123
1124                 vnic->rss_table[i] =
1125                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1126         }
1127
1128         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1129         return 0;
1130 }
1131
1132 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1133                               struct rte_eth_rss_reta_entry64 *reta_conf,
1134                               uint16_t reta_size)
1135 {
1136         struct bnxt *bp = eth_dev->data->dev_private;
1137         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1138         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1139         uint16_t idx, sft, i;
1140
1141         /* Retrieve from the default VNIC */
1142         if (!vnic)
1143                 return -EINVAL;
1144         if (!vnic->rss_table)
1145                 return -EINVAL;
1146
1147         if (reta_size != tbl_size) {
1148                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1149                         "(%d) must equal the size supported by the hardware "
1150                         "(%d)\n", reta_size, tbl_size);
1151                 return -EINVAL;
1152         }
1153
1154         for (idx = 0, i = 0; i < reta_size; i++) {
1155                 idx = i / RTE_RETA_GROUP_SIZE;
1156                 sft = i % RTE_RETA_GROUP_SIZE;
1157
1158                 if (reta_conf[idx].mask & (1ULL << sft)) {
1159                         uint16_t qid;
1160
1161                         if (BNXT_CHIP_THOR(bp))
1162                                 qid = bnxt_rss_to_qid(bp,
1163                                                       vnic->rss_table[i * 2]);
1164                         else
1165                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1166
1167                         if (qid == INVALID_HW_RING_ID) {
1168                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1169                                 return -EINVAL;
1170                         }
1171                         reta_conf[idx].reta[sft] = qid;
1172                 }
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1179                                    struct rte_eth_rss_conf *rss_conf)
1180 {
1181         struct bnxt *bp = eth_dev->data->dev_private;
1182         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1183         struct bnxt_vnic_info *vnic;
1184         uint16_t hash_type = 0;
1185         unsigned int i;
1186
1187         /*
1188          * If RSS enablement were different than dev_configure,
1189          * then return -EINVAL
1190          */
1191         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1192                 if (!rss_conf->rss_hf)
1193                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1194         } else {
1195                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1196                         return -EINVAL;
1197         }
1198
1199         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1200         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1201
1202         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1203                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1204         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1205                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1206         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1207                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1208         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1209                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1210         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1211                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1212         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1213                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1214
1215         /* Update the RSS VNIC(s) */
1216         for (i = 0; i < bp->nr_vnics; i++) {
1217                 vnic = &bp->vnic_info[i];
1218                 vnic->hash_type = hash_type;
1219
1220                 /*
1221                  * Use the supplied key if the key length is
1222                  * acceptable and the rss_key is not NULL
1223                  */
1224                 if (rss_conf->rss_key &&
1225                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1226                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1227                                rss_conf->rss_key_len);
1228
1229                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1230         }
1231         return 0;
1232 }
1233
1234 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1235                                      struct rte_eth_rss_conf *rss_conf)
1236 {
1237         struct bnxt *bp = eth_dev->data->dev_private;
1238         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1239         int len;
1240         uint32_t hash_types;
1241
1242         /* RSS configuration is the same for all VNICs */
1243         if (vnic && vnic->rss_hash_key) {
1244                 if (rss_conf->rss_key) {
1245                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1246                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1247                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1248                 }
1249
1250                 hash_types = vnic->hash_type;
1251                 rss_conf->rss_hf = 0;
1252                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1253                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1254                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1255                 }
1256                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1257                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1258                         hash_types &=
1259                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1260                 }
1261                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1262                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1263                         hash_types &=
1264                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1265                 }
1266                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1267                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1268                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1269                 }
1270                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1271                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1272                         hash_types &=
1273                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1274                 }
1275                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1276                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1277                         hash_types &=
1278                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1279                 }
1280                 if (hash_types) {
1281                         PMD_DRV_LOG(ERR,
1282                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1283                                 vnic->hash_type);
1284                         return -ENOTSUP;
1285                 }
1286         } else {
1287                 rss_conf->rss_hf = 0;
1288         }
1289         return 0;
1290 }
1291
1292 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1293                                struct rte_eth_fc_conf *fc_conf)
1294 {
1295         struct bnxt *bp = dev->data->dev_private;
1296         struct rte_eth_link link_info;
1297         int rc;
1298
1299         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1300         if (rc)
1301                 return rc;
1302
1303         memset(fc_conf, 0, sizeof(*fc_conf));
1304         if (bp->link_info.auto_pause)
1305                 fc_conf->autoneg = 1;
1306         switch (bp->link_info.pause) {
1307         case 0:
1308                 fc_conf->mode = RTE_FC_NONE;
1309                 break;
1310         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1311                 fc_conf->mode = RTE_FC_TX_PAUSE;
1312                 break;
1313         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1314                 fc_conf->mode = RTE_FC_RX_PAUSE;
1315                 break;
1316         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1317                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1318                 fc_conf->mode = RTE_FC_FULL;
1319                 break;
1320         }
1321         return 0;
1322 }
1323
1324 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1325                                struct rte_eth_fc_conf *fc_conf)
1326 {
1327         struct bnxt *bp = dev->data->dev_private;
1328
1329         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1330                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1331                 return -ENOTSUP;
1332         }
1333
1334         switch (fc_conf->mode) {
1335         case RTE_FC_NONE:
1336                 bp->link_info.auto_pause = 0;
1337                 bp->link_info.force_pause = 0;
1338                 break;
1339         case RTE_FC_RX_PAUSE:
1340                 if (fc_conf->autoneg) {
1341                         bp->link_info.auto_pause =
1342                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1343                         bp->link_info.force_pause = 0;
1344                 } else {
1345                         bp->link_info.auto_pause = 0;
1346                         bp->link_info.force_pause =
1347                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1348                 }
1349                 break;
1350         case RTE_FC_TX_PAUSE:
1351                 if (fc_conf->autoneg) {
1352                         bp->link_info.auto_pause =
1353                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1354                         bp->link_info.force_pause = 0;
1355                 } else {
1356                         bp->link_info.auto_pause = 0;
1357                         bp->link_info.force_pause =
1358                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1359                 }
1360                 break;
1361         case RTE_FC_FULL:
1362                 if (fc_conf->autoneg) {
1363                         bp->link_info.auto_pause =
1364                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1365                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1366                         bp->link_info.force_pause = 0;
1367                 } else {
1368                         bp->link_info.auto_pause = 0;
1369                         bp->link_info.force_pause =
1370                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1371                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1372                 }
1373                 break;
1374         }
1375         return bnxt_set_hwrm_link_config(bp, true);
1376 }
1377
1378 /* Add UDP tunneling port */
1379 static int
1380 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1381                          struct rte_eth_udp_tunnel *udp_tunnel)
1382 {
1383         struct bnxt *bp = eth_dev->data->dev_private;
1384         uint16_t tunnel_type = 0;
1385         int rc = 0;
1386
1387         switch (udp_tunnel->prot_type) {
1388         case RTE_TUNNEL_TYPE_VXLAN:
1389                 if (bp->vxlan_port_cnt) {
1390                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1391                                 udp_tunnel->udp_port);
1392                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1393                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1394                                 return -ENOSPC;
1395                         }
1396                         bp->vxlan_port_cnt++;
1397                         return 0;
1398                 }
1399                 tunnel_type =
1400                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1401                 bp->vxlan_port_cnt++;
1402                 break;
1403         case RTE_TUNNEL_TYPE_GENEVE:
1404                 if (bp->geneve_port_cnt) {
1405                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1406                                 udp_tunnel->udp_port);
1407                         if (bp->geneve_port != udp_tunnel->udp_port) {
1408                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1409                                 return -ENOSPC;
1410                         }
1411                         bp->geneve_port_cnt++;
1412                         return 0;
1413                 }
1414                 tunnel_type =
1415                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1416                 bp->geneve_port_cnt++;
1417                 break;
1418         default:
1419                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1420                 return -ENOTSUP;
1421         }
1422         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1423                                              tunnel_type);
1424         return rc;
1425 }
1426
1427 static int
1428 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1429                          struct rte_eth_udp_tunnel *udp_tunnel)
1430 {
1431         struct bnxt *bp = eth_dev->data->dev_private;
1432         uint16_t tunnel_type = 0;
1433         uint16_t port = 0;
1434         int rc = 0;
1435
1436         switch (udp_tunnel->prot_type) {
1437         case RTE_TUNNEL_TYPE_VXLAN:
1438                 if (!bp->vxlan_port_cnt) {
1439                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1440                         return -EINVAL;
1441                 }
1442                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1443                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1444                                 udp_tunnel->udp_port, bp->vxlan_port);
1445                         return -EINVAL;
1446                 }
1447                 if (--bp->vxlan_port_cnt)
1448                         return 0;
1449
1450                 tunnel_type =
1451                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1452                 port = bp->vxlan_fw_dst_port_id;
1453                 break;
1454         case RTE_TUNNEL_TYPE_GENEVE:
1455                 if (!bp->geneve_port_cnt) {
1456                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1457                         return -EINVAL;
1458                 }
1459                 if (bp->geneve_port != udp_tunnel->udp_port) {
1460                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1461                                 udp_tunnel->udp_port, bp->geneve_port);
1462                         return -EINVAL;
1463                 }
1464                 if (--bp->geneve_port_cnt)
1465                         return 0;
1466
1467                 tunnel_type =
1468                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1469                 port = bp->geneve_fw_dst_port_id;
1470                 break;
1471         default:
1472                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1473                 return -ENOTSUP;
1474         }
1475
1476         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1477         if (!rc) {
1478                 if (tunnel_type ==
1479                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1480                         bp->vxlan_port = 0;
1481                 if (tunnel_type ==
1482                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1483                         bp->geneve_port = 0;
1484         }
1485         return rc;
1486 }
1487
1488 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1489 {
1490         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1491         struct bnxt_vnic_info *vnic;
1492         unsigned int i;
1493         int rc = 0;
1494         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1495
1496         /* Cycle through all VNICs */
1497         for (i = 0; i < bp->nr_vnics; i++) {
1498                 /*
1499                  * For each VNIC and each associated filter(s)
1500                  * if VLAN exists && VLAN matches vlan_id
1501                  *      remove the MAC+VLAN filter
1502                  *      add a new MAC only filter
1503                  * else
1504                  *      VLAN filter doesn't exist, just skip and continue
1505                  */
1506                 vnic = &bp->vnic_info[i];
1507                 filter = STAILQ_FIRST(&vnic->filter);
1508                 while (filter) {
1509                         temp_filter = STAILQ_NEXT(filter, next);
1510
1511                         if (filter->enables & chk &&
1512                             filter->l2_ovlan == vlan_id) {
1513                                 /* Must delete the filter */
1514                                 STAILQ_REMOVE(&vnic->filter, filter,
1515                                               bnxt_filter_info, next);
1516                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1517                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1518                                                    filter, next);
1519
1520                                 /*
1521                                  * Need to examine to see if the MAC
1522                                  * filter already existed or not before
1523                                  * allocating a new one
1524                                  */
1525
1526                                 new_filter = bnxt_alloc_filter(bp);
1527                                 if (!new_filter) {
1528                                         PMD_DRV_LOG(ERR,
1529                                                         "MAC/VLAN filter alloc failed\n");
1530                                         rc = -ENOMEM;
1531                                         goto exit;
1532                                 }
1533                                 STAILQ_INSERT_TAIL(&vnic->filter,
1534                                                 new_filter, next);
1535                                 /* Inherit MAC from previous filter */
1536                                 new_filter->mac_index =
1537                                         filter->mac_index;
1538                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1539                                        RTE_ETHER_ADDR_LEN);
1540                                 /* MAC only filter */
1541                                 rc = bnxt_hwrm_set_l2_filter(bp,
1542                                                              vnic->fw_vnic_id,
1543                                                              new_filter);
1544                                 if (rc)
1545                                         goto exit;
1546                                 PMD_DRV_LOG(INFO,
1547                                             "Del Vlan filter for %d\n",
1548                                             vlan_id);
1549                         }
1550                         filter = temp_filter;
1551                 }
1552         }
1553 exit:
1554         return rc;
1555 }
1556
1557 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1558 {
1559         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1560         struct bnxt_vnic_info *vnic;
1561         unsigned int i;
1562         int rc = 0;
1563         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1564                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1565         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1566
1567         /* Cycle through all VNICs */
1568         for (i = 0; i < bp->nr_vnics; i++) {
1569                 /*
1570                  * For each VNIC and each associated filter(s)
1571                  * if VLAN exists:
1572                  *   if VLAN matches vlan_id
1573                  *      VLAN filter already exists, just skip and continue
1574                  *   else
1575                  *      add a new MAC+VLAN filter
1576                  * else
1577                  *   Remove the old MAC only filter
1578                  *    Add a new MAC+VLAN filter
1579                  */
1580                 vnic = &bp->vnic_info[i];
1581                 filter = STAILQ_FIRST(&vnic->filter);
1582                 while (filter) {
1583                         temp_filter = STAILQ_NEXT(filter, next);
1584
1585                         if (filter->enables & chk) {
1586                                 if (filter->l2_ivlan == vlan_id)
1587                                         goto cont;
1588                         } else {
1589                                 /* Must delete the MAC filter */
1590                                 STAILQ_REMOVE(&vnic->filter, filter,
1591                                                 bnxt_filter_info, next);
1592                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1593                                 filter->l2_ovlan = 0;
1594                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1595                                                    filter, next);
1596                         }
1597                         new_filter = bnxt_alloc_filter(bp);
1598                         if (!new_filter) {
1599                                 PMD_DRV_LOG(ERR,
1600                                                 "MAC/VLAN filter alloc failed\n");
1601                                 rc = -ENOMEM;
1602                                 goto exit;
1603                         }
1604                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1605                         /* Inherit MAC from the previous filter */
1606                         new_filter->mac_index = filter->mac_index;
1607                         memcpy(new_filter->l2_addr, filter->l2_addr,
1608                                RTE_ETHER_ADDR_LEN);
1609                         /* MAC + VLAN ID filter */
1610                         new_filter->l2_ivlan = vlan_id;
1611                         new_filter->l2_ivlan_mask = 0xF000;
1612                         new_filter->enables |= en;
1613                         rc = bnxt_hwrm_set_l2_filter(bp,
1614                                         vnic->fw_vnic_id,
1615                                         new_filter);
1616                         if (rc)
1617                                 goto exit;
1618                         PMD_DRV_LOG(INFO,
1619                                     "Added Vlan filter for %d\n", vlan_id);
1620 cont:
1621                         filter = temp_filter;
1622                 }
1623         }
1624 exit:
1625         return rc;
1626 }
1627
1628 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1629                 uint16_t vlan_id, int on)
1630 {
1631         struct bnxt *bp = eth_dev->data->dev_private;
1632
1633         /* These operations apply to ALL existing MAC/VLAN filters */
1634         if (on)
1635                 return bnxt_add_vlan_filter(bp, vlan_id);
1636         else
1637                 return bnxt_del_vlan_filter(bp, vlan_id);
1638 }
1639
1640 static int
1641 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1642 {
1643         struct bnxt *bp = dev->data->dev_private;
1644         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1645         unsigned int i;
1646
1647         if (mask & ETH_VLAN_FILTER_MASK) {
1648                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1649                         /* Remove any VLAN filters programmed */
1650                         for (i = 0; i < 4095; i++)
1651                                 bnxt_del_vlan_filter(bp, i);
1652                 }
1653                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1654                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1655         }
1656
1657         if (mask & ETH_VLAN_STRIP_MASK) {
1658                 /* Enable or disable VLAN stripping */
1659                 for (i = 0; i < bp->nr_vnics; i++) {
1660                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1661                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1662                                 vnic->vlan_strip = true;
1663                         else
1664                                 vnic->vlan_strip = false;
1665                         bnxt_hwrm_vnic_cfg(bp, vnic);
1666                 }
1667                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1668                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1669         }
1670
1671         if (mask & ETH_VLAN_EXTEND_MASK)
1672                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1673
1674         return 0;
1675 }
1676
1677 static int
1678 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1679                         struct rte_ether_addr *addr)
1680 {
1681         struct bnxt *bp = dev->data->dev_private;
1682         /* Default Filter is tied to VNIC 0 */
1683         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1684         struct bnxt_filter_info *filter;
1685         int rc;
1686
1687         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1688                 return -EPERM;
1689
1690         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1691
1692         STAILQ_FOREACH(filter, &vnic->filter, next) {
1693                 /* Default Filter is at Index 0 */
1694                 if (filter->mac_index != 0)
1695                         continue;
1696                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1697                 if (rc)
1698                         return rc;
1699                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1700                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1701                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1702                 filter->enables |=
1703                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1704                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1705                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1706                 if (rc)
1707                         return rc;
1708                 filter->mac_index = 0;
1709                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1710         }
1711
1712         return 0;
1713 }
1714
1715 static int
1716 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1717                           struct rte_ether_addr *mc_addr_set,
1718                           uint32_t nb_mc_addr)
1719 {
1720         struct bnxt *bp = eth_dev->data->dev_private;
1721         char *mc_addr_list = (char *)mc_addr_set;
1722         struct bnxt_vnic_info *vnic;
1723         uint32_t off = 0, i = 0;
1724
1725         vnic = &bp->vnic_info[0];
1726
1727         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1728                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1729                 goto allmulti;
1730         }
1731
1732         /* TODO Check for Duplicate mcast addresses */
1733         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1734         for (i = 0; i < nb_mc_addr; i++) {
1735                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1736                         RTE_ETHER_ADDR_LEN);
1737                 off += RTE_ETHER_ADDR_LEN;
1738         }
1739
1740         vnic->mc_addr_cnt = i;
1741
1742 allmulti:
1743         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1744 }
1745
1746 static int
1747 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1748 {
1749         struct bnxt *bp = dev->data->dev_private;
1750         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1751         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1752         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1753         int ret;
1754
1755         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1756                         fw_major, fw_minor, fw_updt);
1757
1758         ret += 1; /* add the size of '\0' */
1759         if (fw_size < (uint32_t)ret)
1760                 return ret;
1761         else
1762                 return 0;
1763 }
1764
1765 static void
1766 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1767         struct rte_eth_rxq_info *qinfo)
1768 {
1769         struct bnxt_rx_queue *rxq;
1770
1771         rxq = dev->data->rx_queues[queue_id];
1772
1773         qinfo->mp = rxq->mb_pool;
1774         qinfo->scattered_rx = dev->data->scattered_rx;
1775         qinfo->nb_desc = rxq->nb_rx_desc;
1776
1777         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1778         qinfo->conf.rx_drop_en = 0;
1779         qinfo->conf.rx_deferred_start = 0;
1780 }
1781
1782 static void
1783 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1784         struct rte_eth_txq_info *qinfo)
1785 {
1786         struct bnxt_tx_queue *txq;
1787
1788         txq = dev->data->tx_queues[queue_id];
1789
1790         qinfo->nb_desc = txq->nb_tx_desc;
1791
1792         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1793         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1794         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1795
1796         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1797         qinfo->conf.tx_rs_thresh = 0;
1798         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1799 }
1800
1801 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1802 {
1803         struct bnxt *bp = eth_dev->data->dev_private;
1804         struct rte_eth_dev_info dev_info;
1805         uint32_t new_pkt_size;
1806         uint32_t rc = 0;
1807         uint32_t i;
1808
1809         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1810                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1811
1812         bnxt_dev_info_get_op(eth_dev, &dev_info);
1813
1814         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1815                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1816                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1817                 return -EINVAL;
1818         }
1819
1820 #ifdef RTE_ARCH_X86
1821         /*
1822          * If vector-mode tx/rx is active, disallow any MTU change that would
1823          * require scattered receive support.
1824          */
1825         if (eth_dev->data->dev_started &&
1826             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1827              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1828             (new_pkt_size >
1829              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1830                 PMD_DRV_LOG(ERR,
1831                             "MTU change would require scattered rx support. ");
1832                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1833                 return -EINVAL;
1834         }
1835 #endif
1836
1837         if (new_mtu > RTE_ETHER_MTU) {
1838                 bp->flags |= BNXT_FLAG_JUMBO;
1839                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1840                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1841         } else {
1842                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1843                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1844                 bp->flags &= ~BNXT_FLAG_JUMBO;
1845         }
1846
1847         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1848
1849         eth_dev->data->mtu = new_mtu;
1850         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1851
1852         for (i = 0; i < bp->nr_vnics; i++) {
1853                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1854                 uint16_t size = 0;
1855
1856                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1857                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1858                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1859                 if (rc)
1860                         break;
1861
1862                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1863                 size -= RTE_PKTMBUF_HEADROOM;
1864
1865                 if (size < new_mtu) {
1866                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1867                         if (rc)
1868                                 return rc;
1869                 }
1870         }
1871
1872         return rc;
1873 }
1874
1875 static int
1876 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1877 {
1878         struct bnxt *bp = dev->data->dev_private;
1879         uint16_t vlan = bp->vlan;
1880         int rc;
1881
1882         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1883                 PMD_DRV_LOG(ERR,
1884                         "PVID cannot be modified for this function\n");
1885                 return -ENOTSUP;
1886         }
1887         bp->vlan = on ? pvid : 0;
1888
1889         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1890         if (rc)
1891                 bp->vlan = vlan;
1892         return rc;
1893 }
1894
1895 static int
1896 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1897 {
1898         struct bnxt *bp = dev->data->dev_private;
1899
1900         return bnxt_hwrm_port_led_cfg(bp, true);
1901 }
1902
1903 static int
1904 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1905 {
1906         struct bnxt *bp = dev->data->dev_private;
1907
1908         return bnxt_hwrm_port_led_cfg(bp, false);
1909 }
1910
1911 static uint32_t
1912 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1913 {
1914         uint32_t desc = 0, raw_cons = 0, cons;
1915         struct bnxt_cp_ring_info *cpr;
1916         struct bnxt_rx_queue *rxq;
1917         struct rx_pkt_cmpl *rxcmp;
1918         uint16_t cmp_type;
1919         uint8_t cmp = 1;
1920         bool valid;
1921
1922         rxq = dev->data->rx_queues[rx_queue_id];
1923         cpr = rxq->cp_ring;
1924         valid = cpr->valid;
1925
1926         while (raw_cons < rxq->nb_rx_desc) {
1927                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1928                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1929
1930                 if (!CMPL_VALID(rxcmp, valid))
1931                         goto nothing_to_do;
1932                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1933                 cmp_type = CMP_TYPE(rxcmp);
1934                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1935                         cmp = (rte_le_to_cpu_32(
1936                                         ((struct rx_tpa_end_cmpl *)
1937                                          (rxcmp))->agg_bufs_v1) &
1938                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1939                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1940                         desc++;
1941                 } else if (cmp_type == 0x11) {
1942                         desc++;
1943                         cmp = (rxcmp->agg_bufs_v1 &
1944                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1945                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1946                 } else {
1947                         cmp = 1;
1948                 }
1949 nothing_to_do:
1950                 raw_cons += cmp ? cmp : 2;
1951         }
1952
1953         return desc;
1954 }
1955
1956 static int
1957 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1958 {
1959         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1960         struct bnxt_rx_ring_info *rxr;
1961         struct bnxt_cp_ring_info *cpr;
1962         struct bnxt_sw_rx_bd *rx_buf;
1963         struct rx_pkt_cmpl *rxcmp;
1964         uint32_t cons, cp_cons;
1965
1966         if (!rxq)
1967                 return -EINVAL;
1968
1969         cpr = rxq->cp_ring;
1970         rxr = rxq->rx_ring;
1971
1972         if (offset >= rxq->nb_rx_desc)
1973                 return -EINVAL;
1974
1975         cons = RING_CMP(cpr->cp_ring_struct, offset);
1976         cp_cons = cpr->cp_raw_cons;
1977         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1978
1979         if (cons > cp_cons) {
1980                 if (CMPL_VALID(rxcmp, cpr->valid))
1981                         return RTE_ETH_RX_DESC_DONE;
1982         } else {
1983                 if (CMPL_VALID(rxcmp, !cpr->valid))
1984                         return RTE_ETH_RX_DESC_DONE;
1985         }
1986         rx_buf = &rxr->rx_buf_ring[cons];
1987         if (rx_buf->mbuf == NULL)
1988                 return RTE_ETH_RX_DESC_UNAVAIL;
1989
1990
1991         return RTE_ETH_RX_DESC_AVAIL;
1992 }
1993
1994 static int
1995 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1996 {
1997         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1998         struct bnxt_tx_ring_info *txr;
1999         struct bnxt_cp_ring_info *cpr;
2000         struct bnxt_sw_tx_bd *tx_buf;
2001         struct tx_pkt_cmpl *txcmp;
2002         uint32_t cons, cp_cons;
2003
2004         if (!txq)
2005                 return -EINVAL;
2006
2007         cpr = txq->cp_ring;
2008         txr = txq->tx_ring;
2009
2010         if (offset >= txq->nb_tx_desc)
2011                 return -EINVAL;
2012
2013         cons = RING_CMP(cpr->cp_ring_struct, offset);
2014         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2015         cp_cons = cpr->cp_raw_cons;
2016
2017         if (cons > cp_cons) {
2018                 if (CMPL_VALID(txcmp, cpr->valid))
2019                         return RTE_ETH_TX_DESC_UNAVAIL;
2020         } else {
2021                 if (CMPL_VALID(txcmp, !cpr->valid))
2022                         return RTE_ETH_TX_DESC_UNAVAIL;
2023         }
2024         tx_buf = &txr->tx_buf_ring[cons];
2025         if (tx_buf->mbuf == NULL)
2026                 return RTE_ETH_TX_DESC_DONE;
2027
2028         return RTE_ETH_TX_DESC_FULL;
2029 }
2030
2031 static struct bnxt_filter_info *
2032 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2033                                 struct rte_eth_ethertype_filter *efilter,
2034                                 struct bnxt_vnic_info *vnic0,
2035                                 struct bnxt_vnic_info *vnic,
2036                                 int *ret)
2037 {
2038         struct bnxt_filter_info *mfilter = NULL;
2039         int match = 0;
2040         *ret = 0;
2041
2042         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2043                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2044                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2045                         " ethertype filter.", efilter->ether_type);
2046                 *ret = -EINVAL;
2047                 goto exit;
2048         }
2049         if (efilter->queue >= bp->rx_nr_rings) {
2050                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2051                 *ret = -EINVAL;
2052                 goto exit;
2053         }
2054
2055         vnic0 = &bp->vnic_info[0];
2056         vnic = &bp->vnic_info[efilter->queue];
2057         if (vnic == NULL) {
2058                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2059                 *ret = -EINVAL;
2060                 goto exit;
2061         }
2062
2063         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2064                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2065                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2066                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2067                              mfilter->flags ==
2068                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2069                              mfilter->ethertype == efilter->ether_type)) {
2070                                 match = 1;
2071                                 break;
2072                         }
2073                 }
2074         } else {
2075                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2076                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2077                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2078                              mfilter->ethertype == efilter->ether_type &&
2079                              mfilter->flags ==
2080                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2081                                 match = 1;
2082                                 break;
2083                         }
2084         }
2085
2086         if (match)
2087                 *ret = -EEXIST;
2088
2089 exit:
2090         return mfilter;
2091 }
2092
2093 static int
2094 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2095                         enum rte_filter_op filter_op,
2096                         void *arg)
2097 {
2098         struct bnxt *bp = dev->data->dev_private;
2099         struct rte_eth_ethertype_filter *efilter =
2100                         (struct rte_eth_ethertype_filter *)arg;
2101         struct bnxt_filter_info *bfilter, *filter1;
2102         struct bnxt_vnic_info *vnic, *vnic0;
2103         int ret;
2104
2105         if (filter_op == RTE_ETH_FILTER_NOP)
2106                 return 0;
2107
2108         if (arg == NULL) {
2109                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2110                             filter_op);
2111                 return -EINVAL;
2112         }
2113
2114         vnic0 = &bp->vnic_info[0];
2115         vnic = &bp->vnic_info[efilter->queue];
2116
2117         switch (filter_op) {
2118         case RTE_ETH_FILTER_ADD:
2119                 bnxt_match_and_validate_ether_filter(bp, efilter,
2120                                                         vnic0, vnic, &ret);
2121                 if (ret < 0)
2122                         return ret;
2123
2124                 bfilter = bnxt_get_unused_filter(bp);
2125                 if (bfilter == NULL) {
2126                         PMD_DRV_LOG(ERR,
2127                                 "Not enough resources for a new filter.\n");
2128                         return -ENOMEM;
2129                 }
2130                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2131                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2132                        RTE_ETHER_ADDR_LEN);
2133                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2134                        RTE_ETHER_ADDR_LEN);
2135                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2136                 bfilter->ethertype = efilter->ether_type;
2137                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2138
2139                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2140                 if (filter1 == NULL) {
2141                         ret = -1;
2142                         goto cleanup;
2143                 }
2144                 bfilter->enables |=
2145                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2146                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2147
2148                 bfilter->dst_id = vnic->fw_vnic_id;
2149
2150                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2151                         bfilter->flags =
2152                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2153                 }
2154
2155                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2156                 if (ret)
2157                         goto cleanup;
2158                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2159                 break;
2160         case RTE_ETH_FILTER_DELETE:
2161                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2162                                                         vnic0, vnic, &ret);
2163                 if (ret == -EEXIST) {
2164                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2165
2166                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2167                                       next);
2168                         bnxt_free_filter(bp, filter1);
2169                 } else if (ret == 0) {
2170                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2171                 }
2172                 break;
2173         default:
2174                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2175                 ret = -EINVAL;
2176                 goto error;
2177         }
2178         return ret;
2179 cleanup:
2180         bnxt_free_filter(bp, bfilter);
2181 error:
2182         return ret;
2183 }
2184
2185 static inline int
2186 parse_ntuple_filter(struct bnxt *bp,
2187                     struct rte_eth_ntuple_filter *nfilter,
2188                     struct bnxt_filter_info *bfilter)
2189 {
2190         uint32_t en = 0;
2191
2192         if (nfilter->queue >= bp->rx_nr_rings) {
2193                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2194                 return -EINVAL;
2195         }
2196
2197         switch (nfilter->dst_port_mask) {
2198         case UINT16_MAX:
2199                 bfilter->dst_port_mask = -1;
2200                 bfilter->dst_port = nfilter->dst_port;
2201                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2202                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2203                 break;
2204         default:
2205                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2206                 return -EINVAL;
2207         }
2208
2209         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2210         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2211
2212         switch (nfilter->proto_mask) {
2213         case UINT8_MAX:
2214                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2215                         bfilter->ip_protocol = 17;
2216                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2217                         bfilter->ip_protocol = 6;
2218                 else
2219                         return -EINVAL;
2220                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2221                 break;
2222         default:
2223                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2224                 return -EINVAL;
2225         }
2226
2227         switch (nfilter->dst_ip_mask) {
2228         case UINT32_MAX:
2229                 bfilter->dst_ipaddr_mask[0] = -1;
2230                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2231                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2232                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2233                 break;
2234         default:
2235                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2236                 return -EINVAL;
2237         }
2238
2239         switch (nfilter->src_ip_mask) {
2240         case UINT32_MAX:
2241                 bfilter->src_ipaddr_mask[0] = -1;
2242                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2243                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2244                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2245                 break;
2246         default:
2247                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2248                 return -EINVAL;
2249         }
2250
2251         switch (nfilter->src_port_mask) {
2252         case UINT16_MAX:
2253                 bfilter->src_port_mask = -1;
2254                 bfilter->src_port = nfilter->src_port;
2255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2256                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2257                 break;
2258         default:
2259                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2260                 return -EINVAL;
2261         }
2262
2263         //TODO Priority
2264         //nfilter->priority = (uint8_t)filter->priority;
2265
2266         bfilter->enables = en;
2267         return 0;
2268 }
2269
2270 static struct bnxt_filter_info*
2271 bnxt_match_ntuple_filter(struct bnxt *bp,
2272                          struct bnxt_filter_info *bfilter,
2273                          struct bnxt_vnic_info **mvnic)
2274 {
2275         struct bnxt_filter_info *mfilter = NULL;
2276         int i;
2277
2278         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2279                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2280                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2281                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2282                             bfilter->src_ipaddr_mask[0] ==
2283                             mfilter->src_ipaddr_mask[0] &&
2284                             bfilter->src_port == mfilter->src_port &&
2285                             bfilter->src_port_mask == mfilter->src_port_mask &&
2286                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2287                             bfilter->dst_ipaddr_mask[0] ==
2288                             mfilter->dst_ipaddr_mask[0] &&
2289                             bfilter->dst_port == mfilter->dst_port &&
2290                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2291                             bfilter->flags == mfilter->flags &&
2292                             bfilter->enables == mfilter->enables) {
2293                                 if (mvnic)
2294                                         *mvnic = vnic;
2295                                 return mfilter;
2296                         }
2297                 }
2298         }
2299         return NULL;
2300 }
2301
2302 static int
2303 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2304                        struct rte_eth_ntuple_filter *nfilter,
2305                        enum rte_filter_op filter_op)
2306 {
2307         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2308         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2309         int ret;
2310
2311         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2312                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2313                 return -EINVAL;
2314         }
2315
2316         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2317                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2318                 return -EINVAL;
2319         }
2320
2321         bfilter = bnxt_get_unused_filter(bp);
2322         if (bfilter == NULL) {
2323                 PMD_DRV_LOG(ERR,
2324                         "Not enough resources for a new filter.\n");
2325                 return -ENOMEM;
2326         }
2327         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2328         if (ret < 0)
2329                 goto free_filter;
2330
2331         vnic = &bp->vnic_info[nfilter->queue];
2332         vnic0 = &bp->vnic_info[0];
2333         filter1 = STAILQ_FIRST(&vnic0->filter);
2334         if (filter1 == NULL) {
2335                 ret = -1;
2336                 goto free_filter;
2337         }
2338
2339         bfilter->dst_id = vnic->fw_vnic_id;
2340         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2341         bfilter->enables |=
2342                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2343         bfilter->ethertype = 0x800;
2344         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2345
2346         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2347
2348         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2349             bfilter->dst_id == mfilter->dst_id) {
2350                 PMD_DRV_LOG(ERR, "filter exists.\n");
2351                 ret = -EEXIST;
2352                 goto free_filter;
2353         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2354                    bfilter->dst_id != mfilter->dst_id) {
2355                 mfilter->dst_id = vnic->fw_vnic_id;
2356                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2357                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2358                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2359                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2360                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2361                 goto free_filter;
2362         }
2363         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2364                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2365                 ret = -ENOENT;
2366                 goto free_filter;
2367         }
2368
2369         if (filter_op == RTE_ETH_FILTER_ADD) {
2370                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2371                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2372                 if (ret)
2373                         goto free_filter;
2374                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2375         } else {
2376                 if (mfilter == NULL) {
2377                         /* This should not happen. But for Coverity! */
2378                         ret = -ENOENT;
2379                         goto free_filter;
2380                 }
2381                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2382
2383                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2384                 bnxt_free_filter(bp, mfilter);
2385                 mfilter->fw_l2_filter_id = -1;
2386                 bnxt_free_filter(bp, bfilter);
2387                 bfilter->fw_l2_filter_id = -1;
2388         }
2389
2390         return 0;
2391 free_filter:
2392         bfilter->fw_l2_filter_id = -1;
2393         bnxt_free_filter(bp, bfilter);
2394         return ret;
2395 }
2396
2397 static int
2398 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2399                         enum rte_filter_op filter_op,
2400                         void *arg)
2401 {
2402         struct bnxt *bp = dev->data->dev_private;
2403         int ret;
2404
2405         if (filter_op == RTE_ETH_FILTER_NOP)
2406                 return 0;
2407
2408         if (arg == NULL) {
2409                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2410                             filter_op);
2411                 return -EINVAL;
2412         }
2413
2414         switch (filter_op) {
2415         case RTE_ETH_FILTER_ADD:
2416                 ret = bnxt_cfg_ntuple_filter(bp,
2417                         (struct rte_eth_ntuple_filter *)arg,
2418                         filter_op);
2419                 break;
2420         case RTE_ETH_FILTER_DELETE:
2421                 ret = bnxt_cfg_ntuple_filter(bp,
2422                         (struct rte_eth_ntuple_filter *)arg,
2423                         filter_op);
2424                 break;
2425         default:
2426                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2427                 ret = -EINVAL;
2428                 break;
2429         }
2430         return ret;
2431 }
2432
2433 static int
2434 bnxt_parse_fdir_filter(struct bnxt *bp,
2435                        struct rte_eth_fdir_filter *fdir,
2436                        struct bnxt_filter_info *filter)
2437 {
2438         enum rte_fdir_mode fdir_mode =
2439                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2440         struct bnxt_vnic_info *vnic0, *vnic;
2441         struct bnxt_filter_info *filter1;
2442         uint32_t en = 0;
2443         int i;
2444
2445         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2446                 return -EINVAL;
2447
2448         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2449         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2450
2451         switch (fdir->input.flow_type) {
2452         case RTE_ETH_FLOW_IPV4:
2453         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2454                 /* FALLTHROUGH */
2455                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2457                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2459                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2460                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2461                 filter->ip_addr_type =
2462                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2463                 filter->src_ipaddr_mask[0] = 0xffffffff;
2464                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2465                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2466                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2467                 filter->ethertype = 0x800;
2468                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2469                 break;
2470         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2471                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2473                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2475                 filter->dst_port_mask = 0xffff;
2476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2477                 filter->src_port_mask = 0xffff;
2478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2479                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2481                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2482                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2483                 filter->ip_protocol = 6;
2484                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2485                 filter->ip_addr_type =
2486                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2487                 filter->src_ipaddr_mask[0] = 0xffffffff;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2489                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2491                 filter->ethertype = 0x800;
2492                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2493                 break;
2494         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2495                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2497                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2499                 filter->dst_port_mask = 0xffff;
2500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2501                 filter->src_port_mask = 0xffff;
2502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2503                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2505                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2506                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2507                 filter->ip_protocol = 17;
2508                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2509                 filter->ip_addr_type =
2510                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2511                 filter->src_ipaddr_mask[0] = 0xffffffff;
2512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2513                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2515                 filter->ethertype = 0x800;
2516                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2517                 break;
2518         case RTE_ETH_FLOW_IPV6:
2519         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2520                 /* FALLTHROUGH */
2521                 filter->ip_addr_type =
2522                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2523                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2524                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2525                 rte_memcpy(filter->src_ipaddr,
2526                            fdir->input.flow.ipv6_flow.src_ip, 16);
2527                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2528                 rte_memcpy(filter->dst_ipaddr,
2529                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2531                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2532                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2533                 memset(filter->src_ipaddr_mask, 0xff, 16);
2534                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2535                 filter->ethertype = 0x86dd;
2536                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2537                 break;
2538         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2539                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2540                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2541                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2543                 filter->dst_port_mask = 0xffff;
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2545                 filter->src_port_mask = 0xffff;
2546                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2547                 filter->ip_addr_type =
2548                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2549                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2550                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2551                 rte_memcpy(filter->src_ipaddr,
2552                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2553                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2554                 rte_memcpy(filter->dst_ipaddr,
2555                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2557                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2559                 memset(filter->src_ipaddr_mask, 0xff, 16);
2560                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2561                 filter->ethertype = 0x86dd;
2562                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2563                 break;
2564         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2565                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2566                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2567                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2568                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2569                 filter->dst_port_mask = 0xffff;
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2571                 filter->src_port_mask = 0xffff;
2572                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2573                 filter->ip_addr_type =
2574                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2575                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2576                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2577                 rte_memcpy(filter->src_ipaddr,
2578                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2579                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2580                 rte_memcpy(filter->dst_ipaddr,
2581                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2582                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2583                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2584                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2585                 memset(filter->src_ipaddr_mask, 0xff, 16);
2586                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2587                 filter->ethertype = 0x86dd;
2588                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2589                 break;
2590         case RTE_ETH_FLOW_L2_PAYLOAD:
2591                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2592                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2593                 break;
2594         case RTE_ETH_FLOW_VXLAN:
2595                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2596                         return -EINVAL;
2597                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2598                 filter->tunnel_type =
2599                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2600                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2601                 break;
2602         case RTE_ETH_FLOW_NVGRE:
2603                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2604                         return -EINVAL;
2605                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2606                 filter->tunnel_type =
2607                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2608                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2609                 break;
2610         case RTE_ETH_FLOW_UNKNOWN:
2611         case RTE_ETH_FLOW_RAW:
2612         case RTE_ETH_FLOW_FRAG_IPV4:
2613         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2614         case RTE_ETH_FLOW_FRAG_IPV6:
2615         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2616         case RTE_ETH_FLOW_IPV6_EX:
2617         case RTE_ETH_FLOW_IPV6_TCP_EX:
2618         case RTE_ETH_FLOW_IPV6_UDP_EX:
2619         case RTE_ETH_FLOW_GENEVE:
2620                 /* FALLTHROUGH */
2621         default:
2622                 return -EINVAL;
2623         }
2624
2625         vnic0 = &bp->vnic_info[0];
2626         vnic = &bp->vnic_info[fdir->action.rx_queue];
2627         if (vnic == NULL) {
2628                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2629                 return -EINVAL;
2630         }
2631
2632
2633         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2634                 rte_memcpy(filter->dst_macaddr,
2635                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2636                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2637         }
2638
2639         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2640                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2641                 filter1 = STAILQ_FIRST(&vnic0->filter);
2642                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2643         } else {
2644                 filter->dst_id = vnic->fw_vnic_id;
2645                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2646                         if (filter->dst_macaddr[i] == 0x00)
2647                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2648                         else
2649                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2650         }
2651
2652         if (filter1 == NULL)
2653                 return -EINVAL;
2654
2655         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2656         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2657
2658         filter->enables = en;
2659
2660         return 0;
2661 }
2662
2663 static struct bnxt_filter_info *
2664 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2665                 struct bnxt_vnic_info **mvnic)
2666 {
2667         struct bnxt_filter_info *mf = NULL;
2668         int i;
2669
2670         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2671                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2672
2673                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2674                         if (mf->filter_type == nf->filter_type &&
2675                             mf->flags == nf->flags &&
2676                             mf->src_port == nf->src_port &&
2677                             mf->src_port_mask == nf->src_port_mask &&
2678                             mf->dst_port == nf->dst_port &&
2679                             mf->dst_port_mask == nf->dst_port_mask &&
2680                             mf->ip_protocol == nf->ip_protocol &&
2681                             mf->ip_addr_type == nf->ip_addr_type &&
2682                             mf->ethertype == nf->ethertype &&
2683                             mf->vni == nf->vni &&
2684                             mf->tunnel_type == nf->tunnel_type &&
2685                             mf->l2_ovlan == nf->l2_ovlan &&
2686                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2687                             mf->l2_ivlan == nf->l2_ivlan &&
2688                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2689                             !memcmp(mf->l2_addr, nf->l2_addr,
2690                                     RTE_ETHER_ADDR_LEN) &&
2691                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2692                                     RTE_ETHER_ADDR_LEN) &&
2693                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2694                                     RTE_ETHER_ADDR_LEN) &&
2695                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2696                                     RTE_ETHER_ADDR_LEN) &&
2697                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2698                                     sizeof(nf->src_ipaddr)) &&
2699                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2700                                     sizeof(nf->src_ipaddr_mask)) &&
2701                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2702                                     sizeof(nf->dst_ipaddr)) &&
2703                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2704                                     sizeof(nf->dst_ipaddr_mask))) {
2705                                 if (mvnic)
2706                                         *mvnic = vnic;
2707                                 return mf;
2708                         }
2709                 }
2710         }
2711         return NULL;
2712 }
2713
2714 static int
2715 bnxt_fdir_filter(struct rte_eth_dev *dev,
2716                  enum rte_filter_op filter_op,
2717                  void *arg)
2718 {
2719         struct bnxt *bp = dev->data->dev_private;
2720         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2721         struct bnxt_filter_info *filter, *match;
2722         struct bnxt_vnic_info *vnic, *mvnic;
2723         int ret = 0, i;
2724
2725         if (filter_op == RTE_ETH_FILTER_NOP)
2726                 return 0;
2727
2728         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2729                 return -EINVAL;
2730
2731         switch (filter_op) {
2732         case RTE_ETH_FILTER_ADD:
2733         case RTE_ETH_FILTER_DELETE:
2734                 /* FALLTHROUGH */
2735                 filter = bnxt_get_unused_filter(bp);
2736                 if (filter == NULL) {
2737                         PMD_DRV_LOG(ERR,
2738                                 "Not enough resources for a new flow.\n");
2739                         return -ENOMEM;
2740                 }
2741
2742                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2743                 if (ret != 0)
2744                         goto free_filter;
2745                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2746
2747                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2748                         vnic = &bp->vnic_info[0];
2749                 else
2750                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2751
2752                 match = bnxt_match_fdir(bp, filter, &mvnic);
2753                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2754                         if (match->dst_id == vnic->fw_vnic_id) {
2755                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2756                                 ret = -EEXIST;
2757                                 goto free_filter;
2758                         } else {
2759                                 match->dst_id = vnic->fw_vnic_id;
2760                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2761                                                                   match->dst_id,
2762                                                                   match);
2763                                 STAILQ_REMOVE(&mvnic->filter, match,
2764                                               bnxt_filter_info, next);
2765                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2766                                 PMD_DRV_LOG(ERR,
2767                                         "Filter with matching pattern exist\n");
2768                                 PMD_DRV_LOG(ERR,
2769                                         "Updated it to new destination q\n");
2770                                 goto free_filter;
2771                         }
2772                 }
2773                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2774                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2775                         ret = -ENOENT;
2776                         goto free_filter;
2777                 }
2778
2779                 if (filter_op == RTE_ETH_FILTER_ADD) {
2780                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2781                                                           filter->dst_id,
2782                                                           filter);
2783                         if (ret)
2784                                 goto free_filter;
2785                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2786                 } else {
2787                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2788                         STAILQ_REMOVE(&vnic->filter, match,
2789                                       bnxt_filter_info, next);
2790                         bnxt_free_filter(bp, match);
2791                         filter->fw_l2_filter_id = -1;
2792                         bnxt_free_filter(bp, filter);
2793                 }
2794                 break;
2795         case RTE_ETH_FILTER_FLUSH:
2796                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2797                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2798
2799                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2800                                 if (filter->filter_type ==
2801                                     HWRM_CFA_NTUPLE_FILTER) {
2802                                         ret =
2803                                         bnxt_hwrm_clear_ntuple_filter(bp,
2804                                                                       filter);
2805                                         STAILQ_REMOVE(&vnic->filter, filter,
2806                                                       bnxt_filter_info, next);
2807                                 }
2808                         }
2809                 }
2810                 return ret;
2811         case RTE_ETH_FILTER_UPDATE:
2812         case RTE_ETH_FILTER_STATS:
2813         case RTE_ETH_FILTER_INFO:
2814                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2815                 break;
2816         default:
2817                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2818                 ret = -EINVAL;
2819                 break;
2820         }
2821         return ret;
2822
2823 free_filter:
2824         filter->fw_l2_filter_id = -1;
2825         bnxt_free_filter(bp, filter);
2826         return ret;
2827 }
2828
2829 static int
2830 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2831                     enum rte_filter_type filter_type,
2832                     enum rte_filter_op filter_op, void *arg)
2833 {
2834         int ret = 0;
2835
2836         switch (filter_type) {
2837         case RTE_ETH_FILTER_TUNNEL:
2838                 PMD_DRV_LOG(ERR,
2839                         "filter type: %d: To be implemented\n", filter_type);
2840                 break;
2841         case RTE_ETH_FILTER_FDIR:
2842                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2843                 break;
2844         case RTE_ETH_FILTER_NTUPLE:
2845                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2846                 break;
2847         case RTE_ETH_FILTER_ETHERTYPE:
2848                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2849                 break;
2850         case RTE_ETH_FILTER_GENERIC:
2851                 if (filter_op != RTE_ETH_FILTER_GET)
2852                         return -EINVAL;
2853                 *(const void **)arg = &bnxt_flow_ops;
2854                 break;
2855         default:
2856                 PMD_DRV_LOG(ERR,
2857                         "Filter type (%d) not supported", filter_type);
2858                 ret = -EINVAL;
2859                 break;
2860         }
2861         return ret;
2862 }
2863
2864 static const uint32_t *
2865 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2866 {
2867         static const uint32_t ptypes[] = {
2868                 RTE_PTYPE_L2_ETHER_VLAN,
2869                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2870                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2871                 RTE_PTYPE_L4_ICMP,
2872                 RTE_PTYPE_L4_TCP,
2873                 RTE_PTYPE_L4_UDP,
2874                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2875                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2876                 RTE_PTYPE_INNER_L4_ICMP,
2877                 RTE_PTYPE_INNER_L4_TCP,
2878                 RTE_PTYPE_INNER_L4_UDP,
2879                 RTE_PTYPE_UNKNOWN
2880         };
2881
2882         if (!dev->rx_pkt_burst)
2883                 return NULL;
2884
2885         return ptypes;
2886 }
2887
2888 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2889                          int reg_win)
2890 {
2891         uint32_t reg_base = *reg_arr & 0xfffff000;
2892         uint32_t win_off;
2893         int i;
2894
2895         for (i = 0; i < count; i++) {
2896                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2897                         return -ERANGE;
2898         }
2899         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2900         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2901         return 0;
2902 }
2903
2904 static int bnxt_map_ptp_regs(struct bnxt *bp)
2905 {
2906         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2907         uint32_t *reg_arr;
2908         int rc, i;
2909
2910         reg_arr = ptp->rx_regs;
2911         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2912         if (rc)
2913                 return rc;
2914
2915         reg_arr = ptp->tx_regs;
2916         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2917         if (rc)
2918                 return rc;
2919
2920         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2921                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2922
2923         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2924                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2925
2926         return 0;
2927 }
2928
2929 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2930 {
2931         rte_write32(0, (uint8_t *)bp->bar0 +
2932                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2933         rte_write32(0, (uint8_t *)bp->bar0 +
2934                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2935 }
2936
2937 static uint64_t bnxt_cc_read(struct bnxt *bp)
2938 {
2939         uint64_t ns;
2940
2941         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2942                               BNXT_GRCPF_REG_SYNC_TIME));
2943         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2944                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2945         return ns;
2946 }
2947
2948 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2949 {
2950         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2951         uint32_t fifo;
2952
2953         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2954                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2955         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2956                 return -EAGAIN;
2957
2958         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2959                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2960         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2961                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2962         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2963                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2964
2965         return 0;
2966 }
2967
2968 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2969 {
2970         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2971         struct bnxt_pf_info *pf = &bp->pf;
2972         uint16_t port_id;
2973         uint32_t fifo;
2974
2975         if (!ptp)
2976                 return -ENODEV;
2977
2978         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2979                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2980         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2981                 return -EAGAIN;
2982
2983         port_id = pf->port_id;
2984         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2985                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2986
2987         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2988                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2989         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2990 /*              bnxt_clr_rx_ts(bp);       TBD  */
2991                 return -EBUSY;
2992         }
2993
2994         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2995                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2996         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2997                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2998
2999         return 0;
3000 }
3001
3002 static int
3003 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3004 {
3005         uint64_t ns;
3006         struct bnxt *bp = dev->data->dev_private;
3007         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3008
3009         if (!ptp)
3010                 return 0;
3011
3012         ns = rte_timespec_to_ns(ts);
3013         /* Set the timecounters to a new value. */
3014         ptp->tc.nsec = ns;
3015
3016         return 0;
3017 }
3018
3019 static int
3020 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3021 {
3022         uint64_t ns, systime_cycles;
3023         struct bnxt *bp = dev->data->dev_private;
3024         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3025
3026         if (!ptp)
3027                 return 0;
3028
3029         systime_cycles = bnxt_cc_read(bp);
3030         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3031         *ts = rte_ns_to_timespec(ns);
3032
3033         return 0;
3034 }
3035 static int
3036 bnxt_timesync_enable(struct rte_eth_dev *dev)
3037 {
3038         struct bnxt *bp = dev->data->dev_private;
3039         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3040         uint32_t shift = 0;
3041
3042         if (!ptp)
3043                 return 0;
3044
3045         ptp->rx_filter = 1;
3046         ptp->tx_tstamp_en = 1;
3047         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3048
3049         if (!bnxt_hwrm_ptp_cfg(bp))
3050                 bnxt_map_ptp_regs(bp);
3051
3052         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3053         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3054         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3055
3056         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3057         ptp->tc.cc_shift = shift;
3058         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3059
3060         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3061         ptp->rx_tstamp_tc.cc_shift = shift;
3062         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3063
3064         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3065         ptp->tx_tstamp_tc.cc_shift = shift;
3066         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3067
3068         return 0;
3069 }
3070
3071 static int
3072 bnxt_timesync_disable(struct rte_eth_dev *dev)
3073 {
3074         struct bnxt *bp = dev->data->dev_private;
3075         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3076
3077         if (!ptp)
3078                 return 0;
3079
3080         ptp->rx_filter = 0;
3081         ptp->tx_tstamp_en = 0;
3082         ptp->rxctl = 0;
3083
3084         bnxt_hwrm_ptp_cfg(bp);
3085
3086         bnxt_unmap_ptp_regs(bp);
3087
3088         return 0;
3089 }
3090
3091 static int
3092 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3093                                  struct timespec *timestamp,
3094                                  uint32_t flags __rte_unused)
3095 {
3096         struct bnxt *bp = dev->data->dev_private;
3097         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3098         uint64_t rx_tstamp_cycles = 0;
3099         uint64_t ns;
3100
3101         if (!ptp)
3102                 return 0;
3103
3104         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3105         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3106         *timestamp = rte_ns_to_timespec(ns);
3107         return  0;
3108 }
3109
3110 static int
3111 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3112                                  struct timespec *timestamp)
3113 {
3114         struct bnxt *bp = dev->data->dev_private;
3115         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3116         uint64_t tx_tstamp_cycles = 0;
3117         uint64_t ns;
3118
3119         if (!ptp)
3120                 return 0;
3121
3122         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3123         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3124         *timestamp = rte_ns_to_timespec(ns);
3125
3126         return 0;
3127 }
3128
3129 static int
3130 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3131 {
3132         struct bnxt *bp = dev->data->dev_private;
3133         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3134
3135         if (!ptp)
3136                 return 0;
3137
3138         ptp->tc.nsec += delta;
3139
3140         return 0;
3141 }
3142
3143 static int
3144 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3145 {
3146         struct bnxt *bp = dev->data->dev_private;
3147         int rc;
3148         uint32_t dir_entries;
3149         uint32_t entry_length;
3150
3151         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3152                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3153                 bp->pdev->addr.devid, bp->pdev->addr.function);
3154
3155         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3156         if (rc != 0)
3157                 return rc;
3158
3159         return dir_entries * entry_length;
3160 }
3161
3162 static int
3163 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3164                 struct rte_dev_eeprom_info *in_eeprom)
3165 {
3166         struct bnxt *bp = dev->data->dev_private;
3167         uint32_t index;
3168         uint32_t offset;
3169
3170         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3171                 "len = %d\n", bp->pdev->addr.domain,
3172                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3173                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3174
3175         if (in_eeprom->offset == 0) /* special offset value to get directory */
3176                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3177                                                 in_eeprom->data);
3178
3179         index = in_eeprom->offset >> 24;
3180         offset = in_eeprom->offset & 0xffffff;
3181
3182         if (index != 0)
3183                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3184                                            in_eeprom->length, in_eeprom->data);
3185
3186         return 0;
3187 }
3188
3189 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3190 {
3191         switch (dir_type) {
3192         case BNX_DIR_TYPE_CHIMP_PATCH:
3193         case BNX_DIR_TYPE_BOOTCODE:
3194         case BNX_DIR_TYPE_BOOTCODE_2:
3195         case BNX_DIR_TYPE_APE_FW:
3196         case BNX_DIR_TYPE_APE_PATCH:
3197         case BNX_DIR_TYPE_KONG_FW:
3198         case BNX_DIR_TYPE_KONG_PATCH:
3199         case BNX_DIR_TYPE_BONO_FW:
3200         case BNX_DIR_TYPE_BONO_PATCH:
3201                 /* FALLTHROUGH */
3202                 return true;
3203         }
3204
3205         return false;
3206 }
3207
3208 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3209 {
3210         switch (dir_type) {
3211         case BNX_DIR_TYPE_AVS:
3212         case BNX_DIR_TYPE_EXP_ROM_MBA:
3213         case BNX_DIR_TYPE_PCIE:
3214         case BNX_DIR_TYPE_TSCF_UCODE:
3215         case BNX_DIR_TYPE_EXT_PHY:
3216         case BNX_DIR_TYPE_CCM:
3217         case BNX_DIR_TYPE_ISCSI_BOOT:
3218         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3219         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3220                 /* FALLTHROUGH */
3221                 return true;
3222         }
3223
3224         return false;
3225 }
3226
3227 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3228 {
3229         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3230                 bnxt_dir_type_is_other_exec_format(dir_type);
3231 }
3232
3233 static int
3234 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3235                 struct rte_dev_eeprom_info *in_eeprom)
3236 {
3237         struct bnxt *bp = dev->data->dev_private;
3238         uint8_t index, dir_op;
3239         uint16_t type, ext, ordinal, attr;
3240
3241         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3242                 "len = %d\n", bp->pdev->addr.domain,
3243                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3244                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3245
3246         if (!BNXT_PF(bp)) {
3247                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3248                 return -EINVAL;
3249         }
3250
3251         type = in_eeprom->magic >> 16;
3252
3253         if (type == 0xffff) { /* special value for directory operations */
3254                 index = in_eeprom->magic & 0xff;
3255                 dir_op = in_eeprom->magic >> 8;
3256                 if (index == 0)
3257                         return -EINVAL;
3258                 switch (dir_op) {
3259                 case 0x0e: /* erase */
3260                         if (in_eeprom->offset != ~in_eeprom->magic)
3261                                 return -EINVAL;
3262                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3263                 default:
3264                         return -EINVAL;
3265                 }
3266         }
3267
3268         /* Create or re-write an NVM item: */
3269         if (bnxt_dir_type_is_executable(type) == true)
3270                 return -EOPNOTSUPP;
3271         ext = in_eeprom->magic & 0xffff;
3272         ordinal = in_eeprom->offset >> 16;
3273         attr = in_eeprom->offset & 0xffff;
3274
3275         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3276                                      in_eeprom->data, in_eeprom->length);
3277         return 0;
3278 }
3279
3280 /*
3281  * Initialization
3282  */
3283
3284 static const struct eth_dev_ops bnxt_dev_ops = {
3285         .dev_infos_get = bnxt_dev_info_get_op,
3286         .dev_close = bnxt_dev_close_op,
3287         .dev_configure = bnxt_dev_configure_op,
3288         .dev_start = bnxt_dev_start_op,
3289         .dev_stop = bnxt_dev_stop_op,
3290         .dev_set_link_up = bnxt_dev_set_link_up_op,
3291         .dev_set_link_down = bnxt_dev_set_link_down_op,
3292         .stats_get = bnxt_stats_get_op,
3293         .stats_reset = bnxt_stats_reset_op,
3294         .rx_queue_setup = bnxt_rx_queue_setup_op,
3295         .rx_queue_release = bnxt_rx_queue_release_op,
3296         .tx_queue_setup = bnxt_tx_queue_setup_op,
3297         .tx_queue_release = bnxt_tx_queue_release_op,
3298         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3299         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3300         .reta_update = bnxt_reta_update_op,
3301         .reta_query = bnxt_reta_query_op,
3302         .rss_hash_update = bnxt_rss_hash_update_op,
3303         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3304         .link_update = bnxt_link_update_op,
3305         .promiscuous_enable = bnxt_promiscuous_enable_op,
3306         .promiscuous_disable = bnxt_promiscuous_disable_op,
3307         .allmulticast_enable = bnxt_allmulticast_enable_op,
3308         .allmulticast_disable = bnxt_allmulticast_disable_op,
3309         .mac_addr_add = bnxt_mac_addr_add_op,
3310         .mac_addr_remove = bnxt_mac_addr_remove_op,
3311         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3312         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3313         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3314         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3315         .vlan_filter_set = bnxt_vlan_filter_set_op,
3316         .vlan_offload_set = bnxt_vlan_offload_set_op,
3317         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3318         .mtu_set = bnxt_mtu_set_op,
3319         .mac_addr_set = bnxt_set_default_mac_addr_op,
3320         .xstats_get = bnxt_dev_xstats_get_op,
3321         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3322         .xstats_reset = bnxt_dev_xstats_reset_op,
3323         .fw_version_get = bnxt_fw_version_get,
3324         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3325         .rxq_info_get = bnxt_rxq_info_get_op,
3326         .txq_info_get = bnxt_txq_info_get_op,
3327         .dev_led_on = bnxt_dev_led_on_op,
3328         .dev_led_off = bnxt_dev_led_off_op,
3329         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3330         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3331         .rx_queue_count = bnxt_rx_queue_count_op,
3332         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3333         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3334         .rx_queue_start = bnxt_rx_queue_start,
3335         .rx_queue_stop = bnxt_rx_queue_stop,
3336         .tx_queue_start = bnxt_tx_queue_start,
3337         .tx_queue_stop = bnxt_tx_queue_stop,
3338         .filter_ctrl = bnxt_filter_ctrl_op,
3339         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3340         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3341         .get_eeprom           = bnxt_get_eeprom_op,
3342         .set_eeprom           = bnxt_set_eeprom_op,
3343         .timesync_enable      = bnxt_timesync_enable,
3344         .timesync_disable     = bnxt_timesync_disable,
3345         .timesync_read_time   = bnxt_timesync_read_time,
3346         .timesync_write_time   = bnxt_timesync_write_time,
3347         .timesync_adjust_time = bnxt_timesync_adjust_time,
3348         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3349         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3350 };
3351
3352 static bool bnxt_vf_pciid(uint16_t id)
3353 {
3354         if (id == BROADCOM_DEV_ID_57304_VF ||
3355             id == BROADCOM_DEV_ID_57406_VF ||
3356             id == BROADCOM_DEV_ID_5731X_VF ||
3357             id == BROADCOM_DEV_ID_5741X_VF ||
3358             id == BROADCOM_DEV_ID_57414_VF ||
3359             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3360             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3361             id == BROADCOM_DEV_ID_58802_VF ||
3362             id == BROADCOM_DEV_ID_57500_VF)
3363                 return true;
3364         return false;
3365 }
3366
3367 bool bnxt_stratus_device(struct bnxt *bp)
3368 {
3369         uint16_t id = bp->pdev->id.device_id;
3370
3371         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3372             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3373             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3374                 return true;
3375         return false;
3376 }
3377
3378 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3379 {
3380         struct bnxt *bp = eth_dev->data->dev_private;
3381         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3382         int rc;
3383
3384         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3385         if (!pci_dev->mem_resource[0].addr) {
3386                 PMD_DRV_LOG(ERR,
3387                         "Cannot find PCI device base address, aborting\n");
3388                 rc = -ENODEV;
3389                 goto init_err_disable;
3390         }
3391
3392         bp->eth_dev = eth_dev;
3393         bp->pdev = pci_dev;
3394
3395         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3396         if (!bp->bar0) {
3397                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3398                 rc = -ENOMEM;
3399                 goto init_err_release;
3400         }
3401
3402         if (!pci_dev->mem_resource[2].addr) {
3403                 PMD_DRV_LOG(ERR,
3404                             "Cannot find PCI device BAR 2 address, aborting\n");
3405                 rc = -ENODEV;
3406                 goto init_err_release;
3407         } else {
3408                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3409         }
3410
3411         return 0;
3412
3413 init_err_release:
3414         if (bp->bar0)
3415                 bp->bar0 = NULL;
3416         if (bp->doorbell_base)
3417                 bp->doorbell_base = NULL;
3418
3419 init_err_disable:
3420
3421         return rc;
3422 }
3423
3424 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3425                                   struct bnxt_ctx_pg_info *ctx_pg,
3426                                   uint32_t mem_size,
3427                                   const char *suffix,
3428                                   uint16_t idx)
3429 {
3430         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3431         const struct rte_memzone *mz = NULL;
3432         char mz_name[RTE_MEMZONE_NAMESIZE];
3433         rte_iova_t mz_phys_addr;
3434         uint64_t valid_bits = 0;
3435         uint32_t sz;
3436         int i;
3437
3438         if (!mem_size)
3439                 return 0;
3440
3441         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3442                          BNXT_PAGE_SIZE;
3443         rmem->page_size = BNXT_PAGE_SIZE;
3444         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3445         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3446         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3447
3448         valid_bits = PTU_PTE_VALID;
3449
3450         if (rmem->nr_pages > 1) {
3451                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3452                          suffix, idx);
3453                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3454                 mz = rte_memzone_lookup(mz_name);
3455                 if (!mz) {
3456                         mz = rte_memzone_reserve_aligned(mz_name,
3457                                                 rmem->nr_pages * 8,
3458                                                 SOCKET_ID_ANY,
3459                                                 RTE_MEMZONE_2MB |
3460                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3461                                                 RTE_MEMZONE_IOVA_CONTIG,
3462                                                 BNXT_PAGE_SIZE);
3463                         if (mz == NULL)
3464                                 return -ENOMEM;
3465                 }
3466
3467                 memset(mz->addr, 0, mz->len);
3468                 mz_phys_addr = mz->iova;
3469                 if ((unsigned long)mz->addr == mz_phys_addr) {
3470                         PMD_DRV_LOG(WARNING,
3471                                 "Memzone physical address same as virtual.\n");
3472                         PMD_DRV_LOG(WARNING,
3473                                     "Using rte_mem_virt2iova()\n");
3474                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3475                         if (mz_phys_addr == 0) {
3476                                 PMD_DRV_LOG(ERR,
3477                                         "unable to map addr to phys memory\n");
3478                                 return -ENOMEM;
3479                         }
3480                 }
3481                 rte_mem_lock_page(((char *)mz->addr));
3482
3483                 rmem->pg_tbl = mz->addr;
3484                 rmem->pg_tbl_map = mz_phys_addr;
3485                 rmem->pg_tbl_mz = mz;
3486         }
3487
3488         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3489         mz = rte_memzone_lookup(mz_name);
3490         if (!mz) {
3491                 mz = rte_memzone_reserve_aligned(mz_name,
3492                                                  mem_size,
3493                                                  SOCKET_ID_ANY,
3494                                                  RTE_MEMZONE_1GB |
3495                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3496                                                  RTE_MEMZONE_IOVA_CONTIG,
3497                                                  BNXT_PAGE_SIZE);
3498                 if (mz == NULL)
3499                         return -ENOMEM;
3500         }
3501
3502         memset(mz->addr, 0, mz->len);
3503         mz_phys_addr = mz->iova;
3504         if ((unsigned long)mz->addr == mz_phys_addr) {
3505                 PMD_DRV_LOG(WARNING,
3506                             "Memzone physical address same as virtual.\n");
3507                 PMD_DRV_LOG(WARNING,
3508                             "Using rte_mem_virt2iova()\n");
3509                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3510                         rte_mem_lock_page(((char *)mz->addr) + sz);
3511                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3512                 if (mz_phys_addr == RTE_BAD_IOVA) {
3513                         PMD_DRV_LOG(ERR,
3514                                     "unable to map addr to phys memory\n");
3515                         return -ENOMEM;
3516                 }
3517         }
3518
3519         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3520                 rte_mem_lock_page(((char *)mz->addr) + sz);
3521                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3522                 rmem->dma_arr[i] = mz_phys_addr + sz;
3523
3524                 if (rmem->nr_pages > 1) {
3525                         if (i == rmem->nr_pages - 2 &&
3526                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3527                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3528                         else if (i == rmem->nr_pages - 1 &&
3529                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3530                                 valid_bits |= PTU_PTE_LAST;
3531
3532                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3533                                                            valid_bits);
3534                 }
3535         }
3536
3537         rmem->mz = mz;
3538         if (rmem->vmem_size)
3539                 rmem->vmem = (void **)mz->addr;
3540         rmem->dma_arr[0] = mz_phys_addr;
3541         return 0;
3542 }
3543
3544 static void bnxt_free_ctx_mem(struct bnxt *bp)
3545 {
3546         int i;
3547
3548         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3549                 return;
3550
3551         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3552         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3553         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3554         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3555         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3556         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3557         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3558         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3559         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3560         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3561         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3562
3563         for (i = 0; i < BNXT_MAX_Q; i++) {
3564                 if (bp->ctx->tqm_mem[i])
3565                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3566         }
3567
3568         rte_free(bp->ctx);
3569         bp->ctx = NULL;
3570 }
3571
3572 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3573
3574 #define min_t(type, x, y) ({                    \
3575         type __min1 = (x);                      \
3576         type __min2 = (y);                      \
3577         __min1 < __min2 ? __min1 : __min2; })
3578
3579 #define max_t(type, x, y) ({                    \
3580         type __max1 = (x);                      \
3581         type __max2 = (y);                      \
3582         __max1 > __max2 ? __max1 : __max2; })
3583
3584 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3585
3586 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3587 {
3588         struct bnxt_ctx_pg_info *ctx_pg;
3589         struct bnxt_ctx_mem_info *ctx;
3590         uint32_t mem_size, ena, entries;
3591         int i, rc;
3592
3593         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3594         if (rc) {
3595                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3596                 return rc;
3597         }
3598         ctx = bp->ctx;
3599         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3600                 return 0;
3601
3602         ctx_pg = &ctx->qp_mem;
3603         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3604         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3605         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3606         if (rc)
3607                 return rc;
3608
3609         ctx_pg = &ctx->srq_mem;
3610         ctx_pg->entries = ctx->srq_max_l2_entries;
3611         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3612         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3613         if (rc)
3614                 return rc;
3615
3616         ctx_pg = &ctx->cq_mem;
3617         ctx_pg->entries = ctx->cq_max_l2_entries;
3618         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3619         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3620         if (rc)
3621                 return rc;
3622
3623         ctx_pg = &ctx->vnic_mem;
3624         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3625                 ctx->vnic_max_ring_table_entries;
3626         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3627         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3628         if (rc)
3629                 return rc;
3630
3631         ctx_pg = &ctx->stat_mem;
3632         ctx_pg->entries = ctx->stat_max_entries;
3633         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3634         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3635         if (rc)
3636                 return rc;
3637
3638         entries = ctx->qp_max_l2_entries;
3639         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3640         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3641                           ctx->tqm_max_entries_per_ring);
3642         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3643                 ctx_pg = ctx->tqm_mem[i];
3644                 /* use min tqm entries for now. */
3645                 ctx_pg->entries = entries;
3646                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3647                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3648                 if (rc)
3649                         return rc;
3650                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3651         }
3652
3653         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3654         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3655         if (rc)
3656                 PMD_DRV_LOG(ERR,
3657                             "Failed to configure context mem: rc = %d\n", rc);
3658         else
3659                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3660
3661         return 0;
3662 }
3663
3664 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3665 {
3666         struct rte_pci_device *pci_dev = bp->pdev;
3667         char mz_name[RTE_MEMZONE_NAMESIZE];
3668         const struct rte_memzone *mz = NULL;
3669         uint32_t total_alloc_len;
3670         rte_iova_t mz_phys_addr;
3671
3672         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3673                 return 0;
3674
3675         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3676                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3677                  pci_dev->addr.bus, pci_dev->addr.devid,
3678                  pci_dev->addr.function, "rx_port_stats");
3679         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3680         mz = rte_memzone_lookup(mz_name);
3681         total_alloc_len =
3682                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3683                                        sizeof(struct rx_port_stats_ext) + 512);
3684         if (!mz) {
3685                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3686                                          SOCKET_ID_ANY,
3687                                          RTE_MEMZONE_2MB |
3688                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3689                                          RTE_MEMZONE_IOVA_CONTIG);
3690                 if (mz == NULL)
3691                         return -ENOMEM;
3692         }
3693         memset(mz->addr, 0, mz->len);
3694         mz_phys_addr = mz->iova;
3695         if ((unsigned long)mz->addr == mz_phys_addr) {
3696                 PMD_DRV_LOG(WARNING,
3697                             "Memzone physical address same as virtual.\n");
3698                 PMD_DRV_LOG(WARNING,
3699                             "Using rte_mem_virt2iova()\n");
3700                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3701                 if (mz_phys_addr == 0) {
3702                         PMD_DRV_LOG(ERR,
3703                                     "Can't map address to physical memory\n");
3704                         return -ENOMEM;
3705                 }
3706         }
3707
3708         bp->rx_mem_zone = (const void *)mz;
3709         bp->hw_rx_port_stats = mz->addr;
3710         bp->hw_rx_port_stats_map = mz_phys_addr;
3711
3712         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3713                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3714                  pci_dev->addr.bus, pci_dev->addr.devid,
3715                  pci_dev->addr.function, "tx_port_stats");
3716         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3717         mz = rte_memzone_lookup(mz_name);
3718         total_alloc_len =
3719                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3720                                        sizeof(struct tx_port_stats_ext) + 512);
3721         if (!mz) {
3722                 mz = rte_memzone_reserve(mz_name,
3723                                          total_alloc_len,
3724                                          SOCKET_ID_ANY,
3725                                          RTE_MEMZONE_2MB |
3726                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3727                                          RTE_MEMZONE_IOVA_CONTIG);
3728                 if (mz == NULL)
3729                         return -ENOMEM;
3730         }
3731         memset(mz->addr, 0, mz->len);
3732         mz_phys_addr = mz->iova;
3733         if ((unsigned long)mz->addr == mz_phys_addr) {
3734                 PMD_DRV_LOG(WARNING,
3735                             "Memzone physical address same as virtual\n");
3736                 PMD_DRV_LOG(WARNING,
3737                             "Using rte_mem_virt2iova()\n");
3738                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3739                 if (mz_phys_addr == 0) {
3740                         PMD_DRV_LOG(ERR,
3741                                     "Can't map address to physical memory\n");
3742                         return -ENOMEM;
3743                 }
3744         }
3745
3746         bp->tx_mem_zone = (const void *)mz;
3747         bp->hw_tx_port_stats = mz->addr;
3748         bp->hw_tx_port_stats_map = mz_phys_addr;
3749         bp->flags |= BNXT_FLAG_PORT_STATS;
3750
3751         /* Display extended statistics if FW supports it */
3752         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3753             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3754             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3755                 return 0;
3756
3757         bp->hw_rx_port_stats_ext = (void *)
3758                 ((uint8_t *)bp->hw_rx_port_stats +
3759                  sizeof(struct rx_port_stats));
3760         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3761                 sizeof(struct rx_port_stats);
3762         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3763
3764         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3765             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3766                 bp->hw_tx_port_stats_ext = (void *)
3767                         ((uint8_t *)bp->hw_tx_port_stats +
3768                          sizeof(struct tx_port_stats));
3769                 bp->hw_tx_port_stats_ext_map =
3770                         bp->hw_tx_port_stats_map +
3771                         sizeof(struct tx_port_stats);
3772                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3773         }
3774
3775         return 0;
3776 }
3777
3778 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3779 {
3780         struct bnxt *bp = eth_dev->data->dev_private;
3781         int rc = 0;
3782
3783         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3784                                                RTE_ETHER_ADDR_LEN *
3785                                                bp->max_l2_ctx,
3786                                                0);
3787         if (eth_dev->data->mac_addrs == NULL) {
3788                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3789                 return -ENOMEM;
3790         }
3791
3792         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3793                 if (BNXT_PF(bp))
3794                         return -EINVAL;
3795
3796                 /* Generate a random MAC address, if none was assigned by PF */
3797                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3798                 bnxt_eth_hw_addr_random(bp->mac_addr);
3799                 PMD_DRV_LOG(INFO,
3800                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3801                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3802                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3803
3804                 rc = bnxt_hwrm_set_mac(bp);
3805                 if (!rc)
3806                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3807                                RTE_ETHER_ADDR_LEN);
3808                 return rc;
3809         }
3810
3811         /* Copy the permanent MAC from the FUNC_QCAPS response */
3812         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3813         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3814
3815         return rc;
3816 }
3817
3818 #define ALLOW_FUNC(x)   \
3819         { \
3820                 uint32_t arg = (x); \
3821                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3822                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3823         }
3824 static int
3825 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3826 {
3827         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3828         static int version_printed;
3829         struct bnxt *bp;
3830         uint16_t mtu;
3831         int rc;
3832
3833         if (version_printed++ == 0)
3834                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3835
3836         rte_eth_copy_pci_info(eth_dev, pci_dev);
3837
3838         bp = eth_dev->data->dev_private;
3839
3840         bp->dev_stopped = 1;
3841
3842         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3843                 goto skip_init;
3844
3845         if (bnxt_vf_pciid(pci_dev->id.device_id))
3846                 bp->flags |= BNXT_FLAG_VF;
3847
3848         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3849             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3850             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3851             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3852                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3853
3854         rc = bnxt_init_board(eth_dev);
3855         if (rc) {
3856                 PMD_DRV_LOG(ERR,
3857                         "Board initialization failed rc: %x\n", rc);
3858                 goto error;
3859         }
3860 skip_init:
3861         eth_dev->dev_ops = &bnxt_dev_ops;
3862         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3863         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3864         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3865                 return 0;
3866
3867         rc = bnxt_alloc_hwrm_resources(bp);
3868         if (rc) {
3869                 PMD_DRV_LOG(ERR,
3870                         "hwrm resource allocation failure rc: %x\n", rc);
3871                 goto error_free;
3872         }
3873         rc = bnxt_hwrm_ver_get(bp);
3874         if (rc)
3875                 goto error_free;
3876
3877         rc = bnxt_hwrm_func_reset(bp);
3878         if (rc) {
3879                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3880                 rc = -EIO;
3881                 goto error_free;
3882         }
3883
3884         rc = bnxt_hwrm_queue_qportcfg(bp);
3885         if (rc) {
3886                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3887                 goto error_free;
3888         }
3889         /* Get the MAX capabilities for this function */
3890         rc = bnxt_hwrm_func_qcaps(bp);
3891         if (rc) {
3892                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3893                 goto error_free;
3894         }
3895
3896         rc = bnxt_alloc_stats_mem(bp);
3897         if (rc)
3898                 goto error_free;
3899
3900         if (bp->max_tx_rings == 0) {
3901                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3902                 rc = -EBUSY;
3903                 goto error_free;
3904         }
3905
3906         rc = bnxt_setup_mac_addr(eth_dev);
3907         if (rc)
3908                 goto error_free;
3909
3910         /* THOR does not support ring groups.
3911          * But we will use the array to save RSS context IDs.
3912          */
3913         if (BNXT_CHIP_THOR(bp)) {
3914                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3915         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3916                 /* 1 ring is for default completion ring */
3917                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3918                 rc = -ENOSPC;
3919                 goto error_free;
3920         }
3921
3922         if (BNXT_HAS_RING_GRPS(bp)) {
3923                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3924                                         sizeof(*bp->grp_info) *
3925                                                 bp->max_ring_grps, 0);
3926                 if (!bp->grp_info) {
3927                         PMD_DRV_LOG(ERR,
3928                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3929                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3930                         rc = -ENOMEM;
3931                         goto error_free;
3932                 }
3933         }
3934
3935         /* Forward all requests if firmware is new enough */
3936         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3937             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3938             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3939                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3940         } else {
3941                 PMD_DRV_LOG(WARNING,
3942                         "Firmware too old for VF mailbox functionality\n");
3943                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3944         }
3945
3946         /*
3947          * The following are used for driver cleanup.  If we disallow these,
3948          * VF drivers can't clean up cleanly.
3949          */
3950         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3951         ALLOW_FUNC(HWRM_VNIC_FREE);
3952         ALLOW_FUNC(HWRM_RING_FREE);
3953         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3954         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3955         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3956         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3957         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3958         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3959         rc = bnxt_hwrm_func_driver_register(bp);
3960         if (rc) {
3961                 PMD_DRV_LOG(ERR,
3962                         "Failed to register driver");
3963                 rc = -EBUSY;
3964                 goto error_free;
3965         }
3966
3967         PMD_DRV_LOG(INFO,
3968                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3969                 pci_dev->mem_resource[0].phys_addr,
3970                 pci_dev->mem_resource[0].addr);
3971
3972         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3973         if (rc) {
3974                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3975                 goto error_free;
3976         }
3977
3978         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3979             mtu != eth_dev->data->mtu)
3980                 eth_dev->data->mtu = mtu;
3981
3982         if (BNXT_PF(bp)) {
3983                 //if (bp->pf.active_vfs) {
3984                         // TODO: Deallocate VF resources?
3985                 //}
3986                 if (bp->pdev->max_vfs) {
3987                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3988                         if (rc) {
3989                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3990                                 goto error_free;
3991                         }
3992                 } else {
3993                         rc = bnxt_hwrm_allocate_pf_only(bp);
3994                         if (rc) {
3995                                 PMD_DRV_LOG(ERR,
3996                                         "Failed to allocate PF resources\n");
3997                                 goto error_free;
3998                         }
3999                 }
4000         }
4001
4002         bnxt_hwrm_port_led_qcaps(bp);
4003
4004         rc = bnxt_setup_int(bp);
4005         if (rc)
4006                 goto error_free;
4007
4008         rc = bnxt_alloc_mem(bp);
4009         if (rc)
4010                 goto error_free_int;
4011
4012         rc = bnxt_request_int(bp);
4013         if (rc)
4014                 goto error_free_int;
4015
4016         bnxt_init_nic(bp);
4017
4018         return 0;
4019
4020 error_free_int:
4021         bnxt_disable_int(bp);
4022         bnxt_hwrm_func_buf_unrgtr(bp);
4023         bnxt_free_int(bp);
4024         bnxt_free_mem(bp);
4025 error_free:
4026         bnxt_dev_uninit(eth_dev);
4027 error:
4028         return rc;
4029 }
4030
4031 static int
4032 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4033 {
4034         struct bnxt *bp = eth_dev->data->dev_private;
4035         int rc;
4036
4037         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4038                 return -EPERM;
4039
4040         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4041         bnxt_disable_int(bp);
4042         bnxt_free_int(bp);
4043         bnxt_free_mem(bp);
4044         if (bp->grp_info != NULL) {
4045                 rte_free(bp->grp_info);
4046                 bp->grp_info = NULL;
4047         }
4048         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4049         bnxt_free_hwrm_resources(bp);
4050
4051         if (bp->tx_mem_zone) {
4052                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4053                 bp->tx_mem_zone = NULL;
4054         }
4055
4056         if (bp->rx_mem_zone) {
4057                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4058                 bp->rx_mem_zone = NULL;
4059         }
4060
4061         if (bp->dev_stopped == 0)
4062                 bnxt_dev_close_op(eth_dev);
4063         if (bp->pf.vf_info)
4064                 rte_free(bp->pf.vf_info);
4065         bnxt_free_ctx_mem(bp);
4066         eth_dev->dev_ops = NULL;
4067         eth_dev->rx_pkt_burst = NULL;
4068         eth_dev->tx_pkt_burst = NULL;
4069
4070         return rc;
4071 }
4072
4073 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4074         struct rte_pci_device *pci_dev)
4075 {
4076         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4077                 bnxt_dev_init);
4078 }
4079
4080 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4081 {
4082         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4083                 return rte_eth_dev_pci_generic_remove(pci_dev,
4084                                 bnxt_dev_uninit);
4085         else
4086                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4087 }
4088
4089 static struct rte_pci_driver bnxt_rte_pmd = {
4090         .id_table = bnxt_pci_id_map,
4091         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4092         .probe = bnxt_pci_probe,
4093         .remove = bnxt_pci_remove,
4094 };
4095
4096 static bool
4097 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4098 {
4099         if (strcmp(dev->device->driver->name, drv->driver.name))
4100                 return false;
4101
4102         return true;
4103 }
4104
4105 bool is_bnxt_supported(struct rte_eth_dev *dev)
4106 {
4107         return is_device_supported(dev, &bnxt_rte_pmd);
4108 }
4109
4110 RTE_INIT(bnxt_init_log)
4111 {
4112         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4113         if (bnxt_logtype_driver >= 0)
4114                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4115 }
4116
4117 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4118 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4119 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");