drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 static const char *const bnxt_dev_args[] = {
 132         BNXT_DEVARG_TRUFLOW,
 133         NULL
 134 };
 135
 136 /*
 137  * truflow == false to disable the feature
 138  * truflow == true to enable the feature
 139  */
 140 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 141
 142 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 143 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 144 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 145 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 146 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 147 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 148 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 149 static void bnxt_dev_recover(void *arg);
 150
 151 int is_bnxt_in_error(struct bnxt *bp)
 152 {
 153         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 154                 return -EIO;
 155         if (bp->flags & BNXT_FLAG_FW_RESET)
 156                 return -EBUSY;
 157
 158         return 0;
 159 }
 160
 161 /***********************/
 162
 163 /*
 164  * High level utility functions
 165  */
 166
 167 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 168 {
 169         if (!BNXT_CHIP_THOR(bp))
 170                 return 1;
 171
 172         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 173                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 174                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 175 }
 176
 177 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 178 {
 179         if (!BNXT_CHIP_THOR(bp))
 180                 return HW_HASH_INDEX_SIZE;
 181
 182         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 183 }
 184
 185 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 186 {
 187         bnxt_free_filter_mem(bp);
 188         bnxt_free_vnic_attributes(bp);
 189         bnxt_free_vnic_mem(bp);
 190
 191         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 192          * If the number of rings change across fw update,
 193          * we don't have much choice except to warn the user.
 194          */
 195         if (!reconfig) {
 196                 bnxt_free_stats(bp);
 197                 bnxt_free_tx_rings(bp);
 198                 bnxt_free_rx_rings(bp);
 199         }
 200         bnxt_free_async_cp_ring(bp);
 201         bnxt_free_rxtx_nq_ring(bp);
 202
 203         rte_free(bp->grp_info);
 204         bp->grp_info = NULL;
 205 }
 206
 207 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 208 {
 209         int rc;
 210
 211         rc = bnxt_alloc_ring_grps(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_async_ring_struct(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         rc = bnxt_alloc_vnic_mem(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         rc = bnxt_alloc_vnic_attributes(bp);
 224         if (rc)
 225                 goto alloc_mem_err;
 226
 227         rc = bnxt_alloc_filter_mem(bp);
 228         if (rc)
 229                 goto alloc_mem_err;
 230
 231         rc = bnxt_alloc_async_cp_ring(bp);
 232         if (rc)
 233                 goto alloc_mem_err;
 234
 235         rc = bnxt_alloc_rxtx_nq_ring(bp);
 236         if (rc)
 237                 goto alloc_mem_err;
 238
 239         return 0;
 240
 241 alloc_mem_err:
 242         bnxt_free_mem(bp, reconfig);
 243         return rc;
 244 }
 245
 246 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 247 {
 248         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 249         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 250         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 251         struct bnxt_rx_queue *rxq;
 252         unsigned int j;
 253         int rc;
 254
 255         rc = bnxt_vnic_grp_alloc(bp, vnic);
 256         if (rc)
 257                 goto err_out;
 258
 259         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 260                     vnic_id, vnic, vnic->fw_grp_ids);
 261
 262         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 263         if (rc)
 264                 goto err_out;
 265
 266         /* Alloc RSS context only if RSS mode is enabled */
 267         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 268                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 269
 270                 rc = 0;
 271                 for (j = 0; j < nr_ctxs; j++) {
 272                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 273                         if (rc)
 274                                 break;
 275                 }
 276                 if (rc) {
 277                         PMD_DRV_LOG(ERR,
 278                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 279                                     vnic_id, j, rc);
 280                         goto err_out;
 281                 }
 282                 vnic->num_lb_ctxts = nr_ctxs;
 283         }
 284
 285         /*
 286          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 287          * setting is not available at this time, it will not be
 288          * configured correctly in the CFA.
 289          */
 290         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 291                 vnic->vlan_strip = true;
 292         else
 293                 vnic->vlan_strip = false;
 294
 295         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 296         if (rc)
 297                 goto err_out;
 298
 299         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 300         if (rc)
 301                 goto err_out;
 302
 303         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 304                 rxq = bp->eth_dev->data->rx_queues[j];
 305
 306                 PMD_DRV_LOG(DEBUG,
 307                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 308                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 309
 310                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 311                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 312                 else
 313                         vnic->rx_queue_cnt++;
 314         }
 315
 316         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 317
 318         rc = bnxt_vnic_rss_configure(bp, vnic);
 319         if (rc)
 320                 goto err_out;
 321
 322         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 323
 324         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 325                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 326         else
 327                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 328
 329         return 0;
 330 err_out:
 331         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 332                     vnic_id, rc);
 333         return rc;
 334 }
 335
 336 static int bnxt_init_chip(struct bnxt *bp)
 337 {
 338         struct rte_eth_link new;
 339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 341         uint32_t intr_vector = 0;
 342         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 343         uint32_t vec = BNXT_MISC_VEC_ID;
 344         unsigned int i, j;
 345         int rc;
 346
 347         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 348                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 349                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 350                 bp->flags |= BNXT_FLAG_JUMBO;
 351         } else {
 352                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 353                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 354                 bp->flags &= ~BNXT_FLAG_JUMBO;
 355         }
 356
 357         /* THOR does not support ring groups.
 358          * But we will use the array to save RSS context IDs.
 359          */
 360         if (BNXT_CHIP_THOR(bp))
 361                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 362
 363         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 364         if (rc) {
 365                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 366                 goto err_out;
 367         }
 368
 369         rc = bnxt_alloc_hwrm_rings(bp);
 370         if (rc) {
 371                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 372                 goto err_out;
 373         }
 374
 375         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 376         if (rc) {
 377                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 378                 goto err_out;
 379         }
 380
 381         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 382                 goto skip_cosq_cfg;
 383
 384         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 385                 if (bp->rx_cos_queue[i].id != 0xff) {
 386                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 387
 388                         if (!vnic) {
 389                                 PMD_DRV_LOG(ERR,
 390                                             "Num pools more than FW profile\n");
 391                                 rc = -EINVAL;
 392                                 goto err_out;
 393                         }
 394                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 395                         bp->rx_cosq_cnt++;
 396                 }
 397         }
 398
 399 skip_cosq_cfg:
 400         rc = bnxt_mq_rx_configure(bp);
 401         if (rc) {
 402                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 403                 goto err_out;
 404         }
 405
 406         /* VNIC configuration */
 407         for (i = 0; i < bp->nr_vnics; i++) {
 408                 rc = bnxt_setup_one_vnic(bp, i);
 409                 if (rc)
 410                         goto err_out;
 411         }
 412
 413         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 414         if (rc) {
 415                 PMD_DRV_LOG(ERR,
 416                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 417                 goto err_out;
 418         }
 419
 420         /* check and configure queue intr-vector mapping */
 421         if ((rte_intr_cap_multiple(intr_handle) ||
 422              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 423             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 424                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 425                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 426                 if (intr_vector > bp->rx_cp_nr_rings) {
 427                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 428                                         bp->rx_cp_nr_rings);
 429                         return -ENOTSUP;
 430                 }
 431                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 432                 if (rc)
 433                         return rc;
 434         }
 435
 436         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 437                 intr_handle->intr_vec =
 438                         rte_zmalloc("intr_vec",
 439                                     bp->eth_dev->data->nb_rx_queues *
 440                                     sizeof(int), 0);
 441                 if (intr_handle->intr_vec == NULL) {
 442                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 443                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 444                         rc = -ENOMEM;
 445                         goto err_disable;
 446                 }
 447                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 448                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 449                          intr_handle->intr_vec, intr_handle->nb_efd,
 450                         intr_handle->max_intr);
 451                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 452                      queue_id++) {
 453                         intr_handle->intr_vec[queue_id] =
 454                                                         vec + BNXT_RX_VEC_START;
 455                         if (vec < base + intr_handle->nb_efd - 1)
 456                                 vec++;
 457                 }
 458         }
 459
 460         /* enable uio/vfio intr/eventfd mapping */
 461         rc = rte_intr_enable(intr_handle);
 462 #ifndef RTE_EXEC_ENV_FREEBSD
 463         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 464         if (rc)
 465                 goto err_free;
 466 #endif
 467
 468         rc = bnxt_get_hwrm_link_config(bp, &new);
 469         if (rc) {
 470                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 471                 goto err_free;
 472         }
 473
 474         if (!bp->link_info.link_up) {
 475                 rc = bnxt_set_hwrm_link_config(bp, true);
 476                 if (rc) {
 477                         PMD_DRV_LOG(ERR,
 478                                 "HWRM link config failure rc: %x\n", rc);
 479                         goto err_free;
 480                 }
 481         }
 482         bnxt_print_link_info(bp->eth_dev);
 483
 484         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 485         if (!bp->mark_table)
 486                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 487
 488         return 0;
 489
 490 err_free:
 491         rte_free(intr_handle->intr_vec);
 492 err_disable:
 493         rte_intr_efd_disable(intr_handle);
 494 err_out:
 495         /* Some of the error status returned by FW may not be from errno.h */
 496         if (rc > 0)
 497                 rc = -EIO;
 498
 499         return rc;
 500 }
 501
 502 static int bnxt_shutdown_nic(struct bnxt *bp)
 503 {
 504         bnxt_free_all_hwrm_resources(bp);
 505         bnxt_free_all_filters(bp);
 506         bnxt_free_all_vnics(bp);
 507         return 0;
 508 }
 509
 510 /*
 511  * Device configuration and status function
 512  */
 513
 514 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 515                                 struct rte_eth_dev_info *dev_info)
 516 {
 517         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 518         struct bnxt *bp = eth_dev->data->dev_private;
 519         uint16_t max_vnics, i, j, vpool, vrxq;
 520         unsigned int max_rx_rings;
 521         int rc;
 522
 523         rc = is_bnxt_in_error(bp);
 524         if (rc)
 525                 return rc;
 526
 527         /* MAC Specifics */
 528         dev_info->max_mac_addrs = bp->max_l2_ctx;
 529         dev_info->max_hash_mac_addrs = 0;
 530
 531         /* PF/VF specifics */
 532         if (BNXT_PF(bp))
 533                 dev_info->max_vfs = pdev->max_vfs;
 534
 535         max_rx_rings = BNXT_MAX_RINGS(bp);
 536         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 537         dev_info->max_rx_queues = max_rx_rings;
 538         dev_info->max_tx_queues = max_rx_rings;
 539         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 540         dev_info->hash_key_size = 40;
 541         max_vnics = bp->max_vnics;
 542
 543         /* MTU specifics */
 544         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 545         dev_info->max_mtu = BNXT_MAX_MTU;
 546
 547         /* Fast path specifics */
 548         dev_info->min_rx_bufsize = 1;
 549         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 550
 551         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 552         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 553                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 554         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 555         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 556
 557         /* *INDENT-OFF* */
 558         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 559                 .rx_thresh = {
 560                         .pthresh = 8,
 561                         .hthresh = 8,
 562                         .wthresh = 0,
 563                 },
 564                 .rx_free_thresh = 32,
 565                 /* If no descriptors available, pkts are dropped by default */
 566                 .rx_drop_en = 1,
 567         };
 568
 569         dev_info->default_txconf = (struct rte_eth_txconf) {
 570                 .tx_thresh = {
 571                         .pthresh = 32,
 572                         .hthresh = 0,
 573                         .wthresh = 0,
 574                 },
 575                 .tx_free_thresh = 32,
 576                 .tx_rs_thresh = 32,
 577         };
 578         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 579
 580         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 581         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 582         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 583         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 585
 586         /* *INDENT-ON* */
 587
 588         /*
 589          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 590          *       need further investigation.
 591          */
 592
 593         /* VMDq resources */
 594         vpool = 64; /* ETH_64_POOLS */
 595         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 596         for (i = 0; i < 4; vpool >>= 1, i++) {
 597                 if (max_vnics > vpool) {
 598                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 599                                 if (dev_info->max_rx_queues > vrxq) {
 600                                         if (vpool > vrxq)
 601                                                 vpool = vrxq;
 602                                         goto found;
 603                                 }
 604                         }
 605                         /* Not enough resources to support VMDq */
 606                         break;
 607                 }
 608         }
 609         /* Not enough resources to support VMDq */
 610         vpool = 0;
 611         vrxq = 0;
 612 found:
 613         dev_info->max_vmdq_pools = vpool;
 614         dev_info->vmdq_queue_num = vrxq;
 615
 616         dev_info->vmdq_pool_base = 0;
 617         dev_info->vmdq_queue_base = 0;
 618
 619         return 0;
 620 }
 621
 622 /* Configure the device based on the configuration provided */
 623 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 624 {
 625         struct bnxt *bp = eth_dev->data->dev_private;
 626         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 627         int rc;
 628
 629         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 630         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 631         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 632         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 633
 634         rc = is_bnxt_in_error(bp);
 635         if (rc)
 636                 return rc;
 637
 638         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 639                 rc = bnxt_hwrm_check_vf_rings(bp);
 640                 if (rc) {
 641                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 642                         return -ENOSPC;
 643                 }
 644
 645                 /* If a resource has already been allocated - in this case
 646                  * it is the async completion ring, free it. Reallocate it after
 647                  * resource reservation. This will ensure the resource counts
 648                  * are calculated correctly.
 649                  */
 650
 651                 pthread_mutex_lock(&bp->def_cp_lock);
 652
 653                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 654                         bnxt_disable_int(bp);
 655                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 656                 }
 657
 658                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 659                 if (rc) {
 660                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 661                         pthread_mutex_unlock(&bp->def_cp_lock);
 662                         return -ENOSPC;
 663                 }
 664
 665                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 666                         rc = bnxt_alloc_async_cp_ring(bp);
 667                         if (rc) {
 668                                 pthread_mutex_unlock(&bp->def_cp_lock);
 669                                 return rc;
 670                         }
 671                         bnxt_enable_int(bp);
 672                 }
 673
 674                 pthread_mutex_unlock(&bp->def_cp_lock);
 675         } else {
 676                 /* legacy driver needs to get updated values */
 677                 rc = bnxt_hwrm_func_qcaps(bp);
 678                 if (rc) {
 679                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 680                         return rc;
 681                 }
 682         }
 683
 684         /* Inherit new configurations */
 685         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 686             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 687             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 688                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 689             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 690             bp->max_stat_ctx)
 691                 goto resource_error;
 692
 693         if (BNXT_HAS_RING_GRPS(bp) &&
 694             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 695                 goto resource_error;
 696
 697         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 698             bp->max_vnics < eth_dev->data->nb_rx_queues)
 699                 goto resource_error;
 700
 701         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 702         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 703
 704         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 705                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 706         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 707
 708         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 709                 eth_dev->data->mtu =
 710                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 711                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 712                         BNXT_NUM_VLANS;
 713                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 714         }
 715         return 0;
 716
 717 resource_error:
 718         PMD_DRV_LOG(ERR,
 719                     "Insufficient resources to support requested config\n");
 720         PMD_DRV_LOG(ERR,
 721                     "Num Queues Requested: Tx %d, Rx %d\n",
 722                     eth_dev->data->nb_tx_queues,
 723                     eth_dev->data->nb_rx_queues);
 724         PMD_DRV_LOG(ERR,
 725                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 726                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 727                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 728         return -ENOSPC;
 729 }
 730
 731 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 732 {
 733         struct rte_eth_link *link = &eth_dev->data->dev_link;
 734
 735         if (link->link_status)
 736                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 737                         eth_dev->data->port_id,
 738                         (uint32_t)link->link_speed,
 739                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 740                         ("full-duplex") : ("half-duplex\n"));
 741         else
 742                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 743                         eth_dev->data->port_id);
 744 }
 745
 746 /*
 747  * Determine whether the current configuration requires support for scattered
 748  * receive; return 1 if scattered receive is required and 0 if not.
 749  */
 750 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 751 {
 752         uint16_t buf_size;
 753         int i;
 754
 755         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 756                 return 1;
 757
 758         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 759                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 760
 761                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 762                                       RTE_PKTMBUF_HEADROOM);
 763                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 764                         return 1;
 765         }
 766         return 0;
 767 }
 768
 769 static eth_rx_burst_t
 770 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 771 {
 772         struct bnxt *bp = eth_dev->data->dev_private;
 773
 774 #ifdef RTE_ARCH_X86
 775 #ifndef RTE_LIBRTE_IEEE1588
 776         /*
 777          * Vector mode receive can be enabled only if scatter rx is not
 778          * in use and rx offloads are limited to VLAN stripping and
 779          * CRC stripping.
 780          */
 781         if (!eth_dev->data->scattered_rx &&
 782             !(eth_dev->data->dev_conf.rxmode.offloads &
 783               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 784                 DEV_RX_OFFLOAD_KEEP_CRC |
 785                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 786                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 787                 DEV_RX_OFFLOAD_UDP_CKSUM |
 788                 DEV_RX_OFFLOAD_TCP_CKSUM |
 789                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 790                 DEV_RX_OFFLOAD_RSS_HASH |
 791                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 792                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 793                             eth_dev->data->port_id);
 794                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 795                 return bnxt_recv_pkts_vec;
 796         }
 797         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 798                     eth_dev->data->port_id);
 799         PMD_DRV_LOG(INFO,
 800                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 801                     eth_dev->data->port_id,
 802                     eth_dev->data->scattered_rx,
 803                     eth_dev->data->dev_conf.rxmode.offloads);
 804 #endif
 805 #endif
 806         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 807         return bnxt_recv_pkts;
 808 }
 809
 810 static eth_tx_burst_t
 811 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 812 {
 813 #ifdef RTE_ARCH_X86
 814 #ifndef RTE_LIBRTE_IEEE1588
 815         /*
 816          * Vector mode transmit can be enabled only if not using scatter rx
 817          * or tx offloads.
 818          */
 819         if (!eth_dev->data->scattered_rx &&
 820             !eth_dev->data->dev_conf.txmode.offloads) {
 821                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 822                             eth_dev->data->port_id);
 823                 return bnxt_xmit_pkts_vec;
 824         }
 825         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 826                     eth_dev->data->port_id);
 827         PMD_DRV_LOG(INFO,
 828                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 829                     eth_dev->data->port_id,
 830                     eth_dev->data->scattered_rx,
 831                     eth_dev->data->dev_conf.txmode.offloads);
 832 #endif
 833 #endif
 834         return bnxt_xmit_pkts;
 835 }
 836
 837 static int bnxt_handle_if_change_status(struct bnxt *bp)
 838 {
 839         int rc;
 840
 841         /* Since fw has undergone a reset and lost all contexts,
 842          * set fatal flag to not issue hwrm during cleanup
 843          */
 844         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 845         bnxt_uninit_resources(bp, true);
 846
 847         /* clear fatal flag so that re-init happens */
 848         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 849         rc = bnxt_init_resources(bp, true);
 850
 851         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 852
 853         return rc;
 854 }
 855
 856 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 857 {
 858         struct bnxt *bp = eth_dev->data->dev_private;
 859         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 860         int vlan_mask = 0;
 861         int rc;
 862
 863         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 864                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 865                 return -EINVAL;
 866         }
 867
 868         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 869                 PMD_DRV_LOG(ERR,
 870                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 871                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 872         }
 873
 874         rc = bnxt_hwrm_if_change(bp, 1);
 875         if (!rc) {
 876                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 877                         rc = bnxt_handle_if_change_status(bp);
 878                         if (rc)
 879                                 return rc;
 880                 }
 881         }
 882         bnxt_enable_int(bp);
 883
 884         rc = bnxt_init_chip(bp);
 885         if (rc)
 886                 goto error;
 887
 888         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 889         eth_dev->data->dev_started = 1;
 890
 891         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 892
 893         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 894                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 895         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 896                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 897         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 898         if (rc)
 899                 goto error;
 900
 901         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 902         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 903
 904         pthread_mutex_lock(&bp->def_cp_lock);
 905         bnxt_schedule_fw_health_check(bp);
 906         pthread_mutex_unlock(&bp->def_cp_lock);
 907
 908         if (bp->truflow)
 909                 bnxt_ulp_init(bp);
 910
 911         return 0;
 912
 913 error:
 914         bnxt_hwrm_if_change(bp, 0);
 915         bnxt_shutdown_nic(bp);
 916         bnxt_free_tx_mbufs(bp);
 917         bnxt_free_rx_mbufs(bp);
 918         eth_dev->data->dev_started = 0;
 919         return rc;
 920 }
 921
 922 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 923 {
 924         struct bnxt *bp = eth_dev->data->dev_private;
 925         int rc = 0;
 926
 927         if (!bp->link_info.link_up)
 928                 rc = bnxt_set_hwrm_link_config(bp, true);
 929         if (!rc)
 930                 eth_dev->data->dev_link.link_status = 1;
 931
 932         bnxt_print_link_info(eth_dev);
 933         return rc;
 934 }
 935
 936 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 937 {
 938         struct bnxt *bp = eth_dev->data->dev_private;
 939
 940         eth_dev->data->dev_link.link_status = 0;
 941         bnxt_set_hwrm_link_config(bp, false);
 942         bp->link_info.link_up = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Unload the driver, release resources */
 948 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 953
 954         if (bp->truflow)
 955                 bnxt_ulp_deinit(bp);
 956
 957         eth_dev->data->dev_started = 0;
 958         /* Prevent crashes when queues are still in use */
 959         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 960         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 961
 962         bnxt_disable_int(bp);
 963
 964         /* disable uio/vfio intr/eventfd mapping */
 965         rte_intr_disable(intr_handle);
 966
 967         bnxt_cancel_fw_health_check(bp);
 968
 969         bnxt_dev_set_link_down_op(eth_dev);
 970
 971         /* Wait for link to be reset and the async notification to process.
 972          * During reset recovery, there is no need to wait and
 973          * VF/NPAR functions do not have privilege to change PHY config.
 974          */
 975         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
 976                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 977
 978         /* Clean queue intr-vector mapping */
 979         rte_intr_efd_disable(intr_handle);
 980         if (intr_handle->intr_vec != NULL) {
 981                 rte_free(intr_handle->intr_vec);
 982                 intr_handle->intr_vec = NULL;
 983         }
 984
 985         bnxt_hwrm_port_clr_stats(bp);
 986         bnxt_free_tx_mbufs(bp);
 987         bnxt_free_rx_mbufs(bp);
 988         /* Process any remaining notifications in default completion queue */
 989         bnxt_int_handler(eth_dev);
 990         bnxt_shutdown_nic(bp);
 991         bnxt_hwrm_if_change(bp, 0);
 992
 993         rte_free(bp->mark_table);
 994         bp->mark_table = NULL;
 995
 996         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 997         bp->rx_cosq_cnt = 0;
 998 }
 999
1000 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1001 {
1002         struct bnxt *bp = eth_dev->data->dev_private;
1003
1004         /* cancel the recovery handler before remove dev */
1005         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1006         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1007
1008         if (eth_dev->data->dev_started)
1009                 bnxt_dev_stop_op(eth_dev);
1010
1011         bnxt_uninit_resources(bp, false);
1012
1013         eth_dev->dev_ops = NULL;
1014         eth_dev->rx_pkt_burst = NULL;
1015         eth_dev->tx_pkt_burst = NULL;
1016
1017         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1018         bp->tx_mem_zone = NULL;
1019         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1020         bp->rx_mem_zone = NULL;
1021
1022         rte_free(bp->pf.vf_info);
1023         bp->pf.vf_info = NULL;
1024
1025         rte_free(bp->grp_info);
1026         bp->grp_info = NULL;
1027 }
1028
1029 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1030                                     uint32_t index)
1031 {
1032         struct bnxt *bp = eth_dev->data->dev_private;
1033         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1034         struct bnxt_vnic_info *vnic;
1035         struct bnxt_filter_info *filter, *temp_filter;
1036         uint32_t i;
1037
1038         if (is_bnxt_in_error(bp))
1039                 return;
1040
1041         /*
1042          * Loop through all VNICs from the specified filter flow pools to
1043          * remove the corresponding MAC addr filter
1044          */
1045         for (i = 0; i < bp->nr_vnics; i++) {
1046                 if (!(pool_mask & (1ULL << i)))
1047                         continue;
1048
1049                 vnic = &bp->vnic_info[i];
1050                 filter = STAILQ_FIRST(&vnic->filter);
1051                 while (filter) {
1052                         temp_filter = STAILQ_NEXT(filter, next);
1053                         if (filter->mac_index == index) {
1054                                 STAILQ_REMOVE(&vnic->filter, filter,
1055                                                 bnxt_filter_info, next);
1056                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1057                                 bnxt_free_filter(bp, filter);
1058                         }
1059                         filter = temp_filter;
1060                 }
1061         }
1062 }
1063
1064 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1065                                struct rte_ether_addr *mac_addr, uint32_t index,
1066                                uint32_t pool)
1067 {
1068         struct bnxt_filter_info *filter;
1069         int rc = 0;
1070
1071         /* Attach requested MAC address to the new l2_filter */
1072         STAILQ_FOREACH(filter, &vnic->filter, next) {
1073                 if (filter->mac_index == index) {
1074                         PMD_DRV_LOG(DEBUG,
1075                                     "MAC addr already existed for pool %d\n",
1076                                     pool);
1077                         return 0;
1078                 }
1079         }
1080
1081         filter = bnxt_alloc_filter(bp);
1082         if (!filter) {
1083                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1084                 return -ENODEV;
1085         }
1086
1087         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1088          * if the MAC that's been programmed now is a different one, then,
1089          * copy that addr to filter->l2_addr
1090          */
1091         if (mac_addr)
1092                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1093         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1094
1095         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1096         if (!rc) {
1097                 filter->mac_index = index;
1098                 if (filter->mac_index == 0)
1099                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1100                 else
1101                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1102         } else {
1103                 bnxt_free_filter(bp, filter);
1104         }
1105
1106         return rc;
1107 }
1108
1109 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1110                                 struct rte_ether_addr *mac_addr,
1111                                 uint32_t index, uint32_t pool)
1112 {
1113         struct bnxt *bp = eth_dev->data->dev_private;
1114         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1115         int rc = 0;
1116
1117         rc = is_bnxt_in_error(bp);
1118         if (rc)
1119                 return rc;
1120
1121         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1122                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1123                 return -ENOTSUP;
1124         }
1125
1126         if (!vnic) {
1127                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1128                 return -EINVAL;
1129         }
1130
1131         /* Filter settings will get applied when port is started */
1132         if (!eth_dev->data->dev_started)
1133                 return 0;
1134
1135         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1136
1137         return rc;
1138 }
1139
1140 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1141                      bool exp_link_status)
1142 {
1143         int rc = 0;
1144         struct bnxt *bp = eth_dev->data->dev_private;
1145         struct rte_eth_link new;
1146         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1147                   BNXT_LINK_DOWN_WAIT_CNT;
1148
1149         rc = is_bnxt_in_error(bp);
1150         if (rc)
1151                 return rc;
1152
1153         memset(&new, 0, sizeof(new));
1154         do {
1155                 /* Retrieve link info from hardware */
1156                 rc = bnxt_get_hwrm_link_config(bp, &new);
1157                 if (rc) {
1158                         new.link_speed = ETH_LINK_SPEED_100M;
1159                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1160                         PMD_DRV_LOG(ERR,
1161                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1162                         goto out;
1163                 }
1164
1165                 if (!wait_to_complete || new.link_status == exp_link_status)
1166                         break;
1167
1168                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1169         } while (cnt--);
1170
1171 out:
1172         /* Timed out or success */
1173         if (new.link_status != eth_dev->data->dev_link.link_status ||
1174         new.link_speed != eth_dev->data->dev_link.link_speed) {
1175                 rte_eth_linkstatus_set(eth_dev, &new);
1176
1177                 _rte_eth_dev_callback_process(eth_dev,
1178                                               RTE_ETH_EVENT_INTR_LSC,
1179                                               NULL);
1180
1181                 bnxt_print_link_info(eth_dev);
1182         }
1183
1184         return rc;
1185 }
1186
1187 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1188                                int wait_to_complete)
1189 {
1190         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1191 }
1192
1193 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1194 {
1195         struct bnxt *bp = eth_dev->data->dev_private;
1196         struct bnxt_vnic_info *vnic;
1197         uint32_t old_flags;
1198         int rc;
1199
1200         rc = is_bnxt_in_error(bp);
1201         if (rc)
1202                 return rc;
1203
1204         /* Filter settings will get applied when port is started */
1205         if (!eth_dev->data->dev_started)
1206                 return 0;
1207
1208         if (bp->vnic_info == NULL)
1209                 return 0;
1210
1211         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1212
1213         old_flags = vnic->flags;
1214         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1215         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1216         if (rc != 0)
1217                 vnic->flags = old_flags;
1218
1219         return rc;
1220 }
1221
1222 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1223 {
1224         struct bnxt *bp = eth_dev->data->dev_private;
1225         struct bnxt_vnic_info *vnic;
1226         uint32_t old_flags;
1227         int rc;
1228
1229         rc = is_bnxt_in_error(bp);
1230         if (rc)
1231                 return rc;
1232
1233         /* Filter settings will get applied when port is started */
1234         if (!eth_dev->data->dev_started)
1235                 return 0;
1236
1237         if (bp->vnic_info == NULL)
1238                 return 0;
1239
1240         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1241
1242         old_flags = vnic->flags;
1243         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1244         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1245         if (rc != 0)
1246                 vnic->flags = old_flags;
1247
1248         return rc;
1249 }
1250
1251 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1252 {
1253         struct bnxt *bp = eth_dev->data->dev_private;
1254         struct bnxt_vnic_info *vnic;
1255         uint32_t old_flags;
1256         int rc;
1257
1258         rc = is_bnxt_in_error(bp);
1259         if (rc)
1260                 return rc;
1261
1262         /* Filter settings will get applied when port is started */
1263         if (!eth_dev->data->dev_started)
1264                 return 0;
1265
1266         if (bp->vnic_info == NULL)
1267                 return 0;
1268
1269         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1270
1271         old_flags = vnic->flags;
1272         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1273         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1274         if (rc != 0)
1275                 vnic->flags = old_flags;
1276
1277         return rc;
1278 }
1279
1280 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1281 {
1282         struct bnxt *bp = eth_dev->data->dev_private;
1283         struct bnxt_vnic_info *vnic;
1284         uint32_t old_flags;
1285         int rc;
1286
1287         rc = is_bnxt_in_error(bp);
1288         if (rc)
1289                 return rc;
1290
1291         /* Filter settings will get applied when port is started */
1292         if (!eth_dev->data->dev_started)
1293                 return 0;
1294
1295         if (bp->vnic_info == NULL)
1296                 return 0;
1297
1298         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1299
1300         old_flags = vnic->flags;
1301         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1302         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1303         if (rc != 0)
1304                 vnic->flags = old_flags;
1305
1306         return rc;
1307 }
1308
1309 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1310 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1311 {
1312         if (qid >= bp->rx_nr_rings)
1313                 return NULL;
1314
1315         return bp->eth_dev->data->rx_queues[qid];
1316 }
1317
1318 /* Return rxq corresponding to a given rss table ring/group ID. */
1319 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1320 {
1321         struct bnxt_rx_queue *rxq;
1322         unsigned int i;
1323
1324         if (!BNXT_HAS_RING_GRPS(bp)) {
1325                 for (i = 0; i < bp->rx_nr_rings; i++) {
1326                         rxq = bp->eth_dev->data->rx_queues[i];
1327                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1328                                 return rxq->index;
1329                 }
1330         } else {
1331                 for (i = 0; i < bp->rx_nr_rings; i++) {
1332                         if (bp->grp_info[i].fw_grp_id == fwr)
1333                                 return i;
1334                 }
1335         }
1336
1337         return INVALID_HW_RING_ID;
1338 }
1339
1340 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1341                             struct rte_eth_rss_reta_entry64 *reta_conf,
1342                             uint16_t reta_size)
1343 {
1344         struct bnxt *bp = eth_dev->data->dev_private;
1345         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1346         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1347         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1348         uint16_t idx, sft;
1349         int i, rc;
1350
1351         rc = is_bnxt_in_error(bp);
1352         if (rc)
1353                 return rc;
1354
1355         if (!vnic->rss_table)
1356                 return -EINVAL;
1357
1358         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1359                 return -EINVAL;
1360
1361         if (reta_size != tbl_size) {
1362                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1363                         "(%d) must equal the size supported by the hardware "
1364                         "(%d)\n", reta_size, tbl_size);
1365                 return -EINVAL;
1366         }
1367
1368         for (i = 0; i < reta_size; i++) {
1369                 struct bnxt_rx_queue *rxq;
1370
1371                 idx = i / RTE_RETA_GROUP_SIZE;
1372                 sft = i % RTE_RETA_GROUP_SIZE;
1373
1374                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1375                         continue;
1376
1377                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1378                 if (!rxq) {
1379                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1380                         return -EINVAL;
1381                 }
1382
1383                 if (BNXT_CHIP_THOR(bp)) {
1384                         vnic->rss_table[i * 2] =
1385                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1386                         vnic->rss_table[i * 2 + 1] =
1387                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1388                 } else {
1389                         vnic->rss_table[i] =
1390                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1391                 }
1392         }
1393
1394         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1395         return 0;
1396 }
1397
1398 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1399                               struct rte_eth_rss_reta_entry64 *reta_conf,
1400                               uint16_t reta_size)
1401 {
1402         struct bnxt *bp = eth_dev->data->dev_private;
1403         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1404         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1405         uint16_t idx, sft, i;
1406         int rc;
1407
1408         rc = is_bnxt_in_error(bp);
1409         if (rc)
1410                 return rc;
1411
1412         /* Retrieve from the default VNIC */
1413         if (!vnic)
1414                 return -EINVAL;
1415         if (!vnic->rss_table)
1416                 return -EINVAL;
1417
1418         if (reta_size != tbl_size) {
1419                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1420                         "(%d) must equal the size supported by the hardware "
1421                         "(%d)\n", reta_size, tbl_size);
1422                 return -EINVAL;
1423         }
1424
1425         for (idx = 0, i = 0; i < reta_size; i++) {
1426                 idx = i / RTE_RETA_GROUP_SIZE;
1427                 sft = i % RTE_RETA_GROUP_SIZE;
1428
1429                 if (reta_conf[idx].mask & (1ULL << sft)) {
1430                         uint16_t qid;
1431
1432                         if (BNXT_CHIP_THOR(bp))
1433                                 qid = bnxt_rss_to_qid(bp,
1434                                                       vnic->rss_table[i * 2]);
1435                         else
1436                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1437
1438                         if (qid == INVALID_HW_RING_ID) {
1439                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1440                                 return -EINVAL;
1441                         }
1442                         reta_conf[idx].reta[sft] = qid;
1443                 }
1444         }
1445
1446         return 0;
1447 }
1448
1449 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1450                                    struct rte_eth_rss_conf *rss_conf)
1451 {
1452         struct bnxt *bp = eth_dev->data->dev_private;
1453         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1454         struct bnxt_vnic_info *vnic;
1455         int rc;
1456
1457         rc = is_bnxt_in_error(bp);
1458         if (rc)
1459                 return rc;
1460
1461         /*
1462          * If RSS enablement were different than dev_configure,
1463          * then return -EINVAL
1464          */
1465         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1466                 if (!rss_conf->rss_hf)
1467                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1468         } else {
1469                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1470                         return -EINVAL;
1471         }
1472
1473         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1474         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1475
1476         /* Update the default RSS VNIC(s) */
1477         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1478         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1479
1480         /*
1481          * If hashkey is not specified, use the previously configured
1482          * hashkey
1483          */
1484         if (!rss_conf->rss_key)
1485                 goto rss_config;
1486
1487         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1488                 PMD_DRV_LOG(ERR,
1489                             "Invalid hashkey length, should be 16 bytes\n");
1490                 return -EINVAL;
1491         }
1492         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1493
1494 rss_config:
1495         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1496         return 0;
1497 }
1498
1499 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1500                                      struct rte_eth_rss_conf *rss_conf)
1501 {
1502         struct bnxt *bp = eth_dev->data->dev_private;
1503         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1504         int len, rc;
1505         uint32_t hash_types;
1506
1507         rc = is_bnxt_in_error(bp);
1508         if (rc)
1509                 return rc;
1510
1511         /* RSS configuration is the same for all VNICs */
1512         if (vnic && vnic->rss_hash_key) {
1513                 if (rss_conf->rss_key) {
1514                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1515                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1516                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1517                 }
1518
1519                 hash_types = vnic->hash_type;
1520                 rss_conf->rss_hf = 0;
1521                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1522                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1523                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1524                 }
1525                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1526                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1527                         hash_types &=
1528                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1529                 }
1530                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1531                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1532                         hash_types &=
1533                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1534                 }
1535                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1536                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1537                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1538                 }
1539                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1540                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1541                         hash_types &=
1542                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1543                 }
1544                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1545                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1546                         hash_types &=
1547                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1548                 }
1549                 if (hash_types) {
1550                         PMD_DRV_LOG(ERR,
1551                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1552                                 vnic->hash_type);
1553                         return -ENOTSUP;
1554                 }
1555         } else {
1556                 rss_conf->rss_hf = 0;
1557         }
1558         return 0;
1559 }
1560
1561 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1562                                struct rte_eth_fc_conf *fc_conf)
1563 {
1564         struct bnxt *bp = dev->data->dev_private;
1565         struct rte_eth_link link_info;
1566         int rc;
1567
1568         rc = is_bnxt_in_error(bp);
1569         if (rc)
1570                 return rc;
1571
1572         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1573         if (rc)
1574                 return rc;
1575
1576         memset(fc_conf, 0, sizeof(*fc_conf));
1577         if (bp->link_info.auto_pause)
1578                 fc_conf->autoneg = 1;
1579         switch (bp->link_info.pause) {
1580         case 0:
1581                 fc_conf->mode = RTE_FC_NONE;
1582                 break;
1583         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1584                 fc_conf->mode = RTE_FC_TX_PAUSE;
1585                 break;
1586         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1587                 fc_conf->mode = RTE_FC_RX_PAUSE;
1588                 break;
1589         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1590                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1591                 fc_conf->mode = RTE_FC_FULL;
1592                 break;
1593         }
1594         return 0;
1595 }
1596
1597 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1598                                struct rte_eth_fc_conf *fc_conf)
1599 {
1600         struct bnxt *bp = dev->data->dev_private;
1601         int rc;
1602
1603         rc = is_bnxt_in_error(bp);
1604         if (rc)
1605                 return rc;
1606
1607         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1608                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1609                 return -ENOTSUP;
1610         }
1611
1612         switch (fc_conf->mode) {
1613         case RTE_FC_NONE:
1614                 bp->link_info.auto_pause = 0;
1615                 bp->link_info.force_pause = 0;
1616                 break;
1617         case RTE_FC_RX_PAUSE:
1618                 if (fc_conf->autoneg) {
1619                         bp->link_info.auto_pause =
1620                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1621                         bp->link_info.force_pause = 0;
1622                 } else {
1623                         bp->link_info.auto_pause = 0;
1624                         bp->link_info.force_pause =
1625                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1626                 }
1627                 break;
1628         case RTE_FC_TX_PAUSE:
1629                 if (fc_conf->autoneg) {
1630                         bp->link_info.auto_pause =
1631                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1632                         bp->link_info.force_pause = 0;
1633                 } else {
1634                         bp->link_info.auto_pause = 0;
1635                         bp->link_info.force_pause =
1636                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1637                 }
1638                 break;
1639         case RTE_FC_FULL:
1640                 if (fc_conf->autoneg) {
1641                         bp->link_info.auto_pause =
1642                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1643                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1644                         bp->link_info.force_pause = 0;
1645                 } else {
1646                         bp->link_info.auto_pause = 0;
1647                         bp->link_info.force_pause =
1648                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1649                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1650                 }
1651                 break;
1652         }
1653         return bnxt_set_hwrm_link_config(bp, true);
1654 }
1655
1656 /* Add UDP tunneling port */
1657 static int
1658 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1659                          struct rte_eth_udp_tunnel *udp_tunnel)
1660 {
1661         struct bnxt *bp = eth_dev->data->dev_private;
1662         uint16_t tunnel_type = 0;
1663         int rc = 0;
1664
1665         rc = is_bnxt_in_error(bp);
1666         if (rc)
1667                 return rc;
1668
1669         switch (udp_tunnel->prot_type) {
1670         case RTE_TUNNEL_TYPE_VXLAN:
1671                 if (bp->vxlan_port_cnt) {
1672                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1673                                 udp_tunnel->udp_port);
1674                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1675                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1676                                 return -ENOSPC;
1677                         }
1678                         bp->vxlan_port_cnt++;
1679                         return 0;
1680                 }
1681                 tunnel_type =
1682                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1683                 bp->vxlan_port_cnt++;
1684                 break;
1685         case RTE_TUNNEL_TYPE_GENEVE:
1686                 if (bp->geneve_port_cnt) {
1687                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1688                                 udp_tunnel->udp_port);
1689                         if (bp->geneve_port != udp_tunnel->udp_port) {
1690                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1691                                 return -ENOSPC;
1692                         }
1693                         bp->geneve_port_cnt++;
1694                         return 0;
1695                 }
1696                 tunnel_type =
1697                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1698                 bp->geneve_port_cnt++;
1699                 break;
1700         default:
1701                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1702                 return -ENOTSUP;
1703         }
1704         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1705                                              tunnel_type);
1706         return rc;
1707 }
1708
1709 static int
1710 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1711                          struct rte_eth_udp_tunnel *udp_tunnel)
1712 {
1713         struct bnxt *bp = eth_dev->data->dev_private;
1714         uint16_t tunnel_type = 0;
1715         uint16_t port = 0;
1716         int rc = 0;
1717
1718         rc = is_bnxt_in_error(bp);
1719         if (rc)
1720                 return rc;
1721
1722         switch (udp_tunnel->prot_type) {
1723         case RTE_TUNNEL_TYPE_VXLAN:
1724                 if (!bp->vxlan_port_cnt) {
1725                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1726                         return -EINVAL;
1727                 }
1728                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1729                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1730                                 udp_tunnel->udp_port, bp->vxlan_port);
1731                         return -EINVAL;
1732                 }
1733                 if (--bp->vxlan_port_cnt)
1734                         return 0;
1735
1736                 tunnel_type =
1737                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1738                 port = bp->vxlan_fw_dst_port_id;
1739                 break;
1740         case RTE_TUNNEL_TYPE_GENEVE:
1741                 if (!bp->geneve_port_cnt) {
1742                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1743                         return -EINVAL;
1744                 }
1745                 if (bp->geneve_port != udp_tunnel->udp_port) {
1746                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1747                                 udp_tunnel->udp_port, bp->geneve_port);
1748                         return -EINVAL;
1749                 }
1750                 if (--bp->geneve_port_cnt)
1751                         return 0;
1752
1753                 tunnel_type =
1754                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1755                 port = bp->geneve_fw_dst_port_id;
1756                 break;
1757         default:
1758                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1759                 return -ENOTSUP;
1760         }
1761
1762         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1763         if (!rc) {
1764                 if (tunnel_type ==
1765                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1766                         bp->vxlan_port = 0;
1767                 if (tunnel_type ==
1768                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1769                         bp->geneve_port = 0;
1770         }
1771         return rc;
1772 }
1773
1774 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1775 {
1776         struct bnxt_filter_info *filter;
1777         struct bnxt_vnic_info *vnic;
1778         int rc = 0;
1779         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1780
1781         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1782         filter = STAILQ_FIRST(&vnic->filter);
1783         while (filter) {
1784                 /* Search for this matching MAC+VLAN filter */
1785                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1786                         /* Delete the filter */
1787                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1788                         if (rc)
1789                                 return rc;
1790                         STAILQ_REMOVE(&vnic->filter, filter,
1791                                       bnxt_filter_info, next);
1792                         bnxt_free_filter(bp, filter);
1793                         PMD_DRV_LOG(INFO,
1794                                     "Deleted vlan filter for %d\n",
1795                                     vlan_id);
1796                         return 0;
1797                 }
1798                 filter = STAILQ_NEXT(filter, next);
1799         }
1800         return -ENOENT;
1801 }
1802
1803 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1804 {
1805         struct bnxt_filter_info *filter;
1806         struct bnxt_vnic_info *vnic;
1807         int rc = 0;
1808         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1809                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1810         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1811
1812         /* Implementation notes on the use of VNIC in this command:
1813          *
1814          * By default, these filters belong to default vnic for the function.
1815          * Once these filters are set up, only destination VNIC can be modified.
1816          * If the destination VNIC is not specified in this command,
1817          * then the HWRM shall only create an l2 context id.
1818          */
1819
1820         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1821         filter = STAILQ_FIRST(&vnic->filter);
1822         /* Check if the VLAN has already been added */
1823         while (filter) {
1824                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1825                         return -EEXIST;
1826
1827                 filter = STAILQ_NEXT(filter, next);
1828         }
1829
1830         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1831          * command to create MAC+VLAN filter with the right flags, enables set.
1832          */
1833         filter = bnxt_alloc_filter(bp);
1834         if (!filter) {
1835                 PMD_DRV_LOG(ERR,
1836                             "MAC/VLAN filter alloc failed\n");
1837                 return -ENOMEM;
1838         }
1839         /* MAC + VLAN ID filter */
1840         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1841          * untagged packets are received
1842          *
1843          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1844          * packets and only the programmed vlan's packets are received
1845          */
1846         filter->l2_ivlan = vlan_id;
1847         filter->l2_ivlan_mask = 0x0FFF;
1848         filter->enables |= en;
1849         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1850
1851         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1852         if (rc) {
1853                 /* Free the newly allocated filter as we were
1854                  * not able to create the filter in hardware.
1855                  */
1856                 bnxt_free_filter(bp, filter);
1857                 return rc;
1858         }
1859
1860         filter->mac_index = 0;
1861         /* Add this new filter to the list */
1862         if (vlan_id == 0)
1863                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1864         else
1865                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1866
1867         PMD_DRV_LOG(INFO,
1868                     "Added Vlan filter for %d\n", vlan_id);
1869         return rc;
1870 }
1871
1872 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1873                 uint16_t vlan_id, int on)
1874 {
1875         struct bnxt *bp = eth_dev->data->dev_private;
1876         int rc;
1877
1878         rc = is_bnxt_in_error(bp);
1879         if (rc)
1880                 return rc;
1881
1882         /* These operations apply to ALL existing MAC/VLAN filters */
1883         if (on)
1884                 return bnxt_add_vlan_filter(bp, vlan_id);
1885         else
1886                 return bnxt_del_vlan_filter(bp, vlan_id);
1887 }
1888
1889 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1890                                     struct bnxt_vnic_info *vnic)
1891 {
1892         struct bnxt_filter_info *filter;
1893         int rc;
1894
1895         filter = STAILQ_FIRST(&vnic->filter);
1896         while (filter) {
1897                 if (filter->mac_index == 0 &&
1898                     !memcmp(filter->l2_addr, bp->mac_addr,
1899                             RTE_ETHER_ADDR_LEN)) {
1900                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1901                         if (!rc) {
1902                                 STAILQ_REMOVE(&vnic->filter, filter,
1903                                               bnxt_filter_info, next);
1904                                 bnxt_free_filter(bp, filter);
1905                         }
1906                         return rc;
1907                 }
1908                 filter = STAILQ_NEXT(filter, next);
1909         }
1910         return 0;
1911 }
1912
1913 static int
1914 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1915 {
1916         struct bnxt_vnic_info *vnic;
1917         unsigned int i;
1918         int rc;
1919
1920         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1921         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1922                 /* Remove any VLAN filters programmed */
1923                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1924                         bnxt_del_vlan_filter(bp, i);
1925
1926                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1927                 if (rc)
1928                         return rc;
1929         } else {
1930                 /* Default filter will allow packets that match the
1931                  * dest mac. So, it has to be deleted, otherwise, we
1932                  * will endup receiving vlan packets for which the
1933                  * filter is not programmed, when hw-vlan-filter
1934                  * configuration is ON
1935                  */
1936                 bnxt_del_dflt_mac_filter(bp, vnic);
1937                 /* This filter will allow only untagged packets */
1938                 bnxt_add_vlan_filter(bp, 0);
1939         }
1940         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1941                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1942
1943         return 0;
1944 }
1945
1946 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1947 {
1948         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1949         unsigned int i;
1950         int rc;
1951
1952         /* Destroy vnic filters and vnic */
1953         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1954             DEV_RX_OFFLOAD_VLAN_FILTER) {
1955                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1956                         bnxt_del_vlan_filter(bp, i);
1957         }
1958         bnxt_del_dflt_mac_filter(bp, vnic);
1959
1960         rc = bnxt_hwrm_vnic_free(bp, vnic);
1961         if (rc)
1962                 return rc;
1963
1964         rte_free(vnic->fw_grp_ids);
1965         vnic->fw_grp_ids = NULL;
1966
1967         return 0;
1968 }
1969
1970 static int
1971 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1972 {
1973         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1974         int rc;
1975
1976         /* Destroy, recreate and reconfigure the default vnic */
1977         rc = bnxt_free_one_vnic(bp, 0);
1978         if (rc)
1979                 return rc;
1980
1981         /* default vnic 0 */
1982         rc = bnxt_setup_one_vnic(bp, 0);
1983         if (rc)
1984                 return rc;
1985
1986         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1987             DEV_RX_OFFLOAD_VLAN_FILTER) {
1988                 rc = bnxt_add_vlan_filter(bp, 0);
1989                 if (rc)
1990                         return rc;
1991                 rc = bnxt_restore_vlan_filters(bp);
1992                 if (rc)
1993                         return rc;
1994         } else {
1995                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1996                 if (rc)
1997                         return rc;
1998         }
1999
2000         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2001         if (rc)
2002                 return rc;
2003
2004         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2005                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2006
2007         return rc;
2008 }
2009
2010 static int
2011 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2012 {
2013         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2014         struct bnxt *bp = dev->data->dev_private;
2015         int rc;
2016
2017         rc = is_bnxt_in_error(bp);
2018         if (rc)
2019                 return rc;
2020
2021         /* Filter settings will get applied when port is started */
2022         if (!dev->data->dev_started)
2023                 return 0;
2024
2025         if (mask & ETH_VLAN_FILTER_MASK) {
2026                 /* Enable or disable VLAN filtering */
2027                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2028                 if (rc)
2029                         return rc;
2030         }
2031
2032         if (mask & ETH_VLAN_STRIP_MASK) {
2033                 /* Enable or disable VLAN stripping */
2034                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2035                 if (rc)
2036                         return rc;
2037         }
2038
2039         if (mask & ETH_VLAN_EXTEND_MASK) {
2040                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2041                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2042                 else
2043                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2044         }
2045
2046         return 0;
2047 }
2048
2049 static int
2050 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2051                       uint16_t tpid)
2052 {
2053         struct bnxt *bp = dev->data->dev_private;
2054         int qinq = dev->data->dev_conf.rxmode.offloads &
2055                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2056
2057         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2058             vlan_type != ETH_VLAN_TYPE_OUTER) {
2059                 PMD_DRV_LOG(ERR,
2060                             "Unsupported vlan type.");
2061                 return -EINVAL;
2062         }
2063         if (!qinq) {
2064                 PMD_DRV_LOG(ERR,
2065                             "QinQ not enabled. Needs to be ON as we can "
2066                             "accelerate only outer vlan\n");
2067                 return -EINVAL;
2068         }
2069
2070         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2071                 switch (tpid) {
2072                 case RTE_ETHER_TYPE_QINQ:
2073                         bp->outer_tpid_bd =
2074                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2075                                 break;
2076                 case RTE_ETHER_TYPE_VLAN:
2077                         bp->outer_tpid_bd =
2078                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2079                                 break;
2080                 case 0x9100:
2081                         bp->outer_tpid_bd =
2082                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2083                                 break;
2084                 case 0x9200:
2085                         bp->outer_tpid_bd =
2086                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2087                                 break;
2088                 case 0x9300:
2089                         bp->outer_tpid_bd =
2090                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2091                                 break;
2092                 default:
2093                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2094                         return -EINVAL;
2095                 }
2096                 bp->outer_tpid_bd |= tpid;
2097                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2098         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2099                 PMD_DRV_LOG(ERR,
2100                             "Can accelerate only outer vlan in QinQ\n");
2101                 return -EINVAL;
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int
2108 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2109                              struct rte_ether_addr *addr)
2110 {
2111         struct bnxt *bp = dev->data->dev_private;
2112         /* Default Filter is tied to VNIC 0 */
2113         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2114         int rc;
2115
2116         rc = is_bnxt_in_error(bp);
2117         if (rc)
2118                 return rc;
2119
2120         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2121                 return -EPERM;
2122
2123         if (rte_is_zero_ether_addr(addr))
2124                 return -EINVAL;
2125
2126         /* Filter settings will get applied when port is started */
2127         if (!dev->data->dev_started)
2128                 return 0;
2129
2130         /* Check if the requested MAC is already added */
2131         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2132                 return 0;
2133
2134         /* Destroy filter and re-create it */
2135         bnxt_del_dflt_mac_filter(bp, vnic);
2136
2137         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2138         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2139                 /* This filter will allow only untagged packets */
2140                 rc = bnxt_add_vlan_filter(bp, 0);
2141         } else {
2142                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2143         }
2144
2145         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2146         return rc;
2147 }
2148
2149 static int
2150 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2151                           struct rte_ether_addr *mc_addr_set,
2152                           uint32_t nb_mc_addr)
2153 {
2154         struct bnxt *bp = eth_dev->data->dev_private;
2155         char *mc_addr_list = (char *)mc_addr_set;
2156         struct bnxt_vnic_info *vnic;
2157         uint32_t off = 0, i = 0;
2158         int rc;
2159
2160         rc = is_bnxt_in_error(bp);
2161         if (rc)
2162                 return rc;
2163
2164         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2165
2166         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2167                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2168                 goto allmulti;
2169         }
2170
2171         /* TODO Check for Duplicate mcast addresses */
2172         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2173         for (i = 0; i < nb_mc_addr; i++) {
2174                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2175                         RTE_ETHER_ADDR_LEN);
2176                 off += RTE_ETHER_ADDR_LEN;
2177         }
2178
2179         vnic->mc_addr_cnt = i;
2180         if (vnic->mc_addr_cnt)
2181                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2182         else
2183                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2184
2185 allmulti:
2186         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2187 }
2188
2189 static int
2190 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2191 {
2192         struct bnxt *bp = dev->data->dev_private;
2193         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2194         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2195         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2196         int ret;
2197
2198         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2199                         fw_major, fw_minor, fw_updt);
2200
2201         ret += 1; /* add the size of '\0' */
2202         if (fw_size < (uint32_t)ret)
2203                 return ret;
2204         else
2205                 return 0;
2206 }
2207
2208 static void
2209 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2210         struct rte_eth_rxq_info *qinfo)
2211 {
2212         struct bnxt *bp = dev->data->dev_private;
2213         struct bnxt_rx_queue *rxq;
2214
2215         if (is_bnxt_in_error(bp))
2216                 return;
2217
2218         rxq = dev->data->rx_queues[queue_id];
2219
2220         qinfo->mp = rxq->mb_pool;
2221         qinfo->scattered_rx = dev->data->scattered_rx;
2222         qinfo->nb_desc = rxq->nb_rx_desc;
2223
2224         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2225         qinfo->conf.rx_drop_en = 0;
2226         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2227 }
2228
2229 static void
2230 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2231         struct rte_eth_txq_info *qinfo)
2232 {
2233         struct bnxt *bp = dev->data->dev_private;
2234         struct bnxt_tx_queue *txq;
2235
2236         if (is_bnxt_in_error(bp))
2237                 return;
2238
2239         txq = dev->data->tx_queues[queue_id];
2240
2241         qinfo->nb_desc = txq->nb_tx_desc;
2242
2243         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2244         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2245         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2246
2247         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2248         qinfo->conf.tx_rs_thresh = 0;
2249         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2250 }
2251
2252 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2253 {
2254         struct bnxt *bp = eth_dev->data->dev_private;
2255         uint32_t new_pkt_size;
2256         uint32_t rc = 0;
2257         uint32_t i;
2258
2259         rc = is_bnxt_in_error(bp);
2260         if (rc)
2261                 return rc;
2262
2263         /* Exit if receive queues are not configured yet */
2264         if (!eth_dev->data->nb_rx_queues)
2265                 return rc;
2266
2267         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2268                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2269
2270 #ifdef RTE_ARCH_X86
2271         /*
2272          * If vector-mode tx/rx is active, disallow any MTU change that would
2273          * require scattered receive support.
2274          */
2275         if (eth_dev->data->dev_started &&
2276             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2277              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2278             (new_pkt_size >
2279              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2280                 PMD_DRV_LOG(ERR,
2281                             "MTU change would require scattered rx support. ");
2282                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2283                 return -EINVAL;
2284         }
2285 #endif
2286
2287         if (new_mtu > RTE_ETHER_MTU) {
2288                 bp->flags |= BNXT_FLAG_JUMBO;
2289                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2290                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2291         } else {
2292                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2293                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2294                 bp->flags &= ~BNXT_FLAG_JUMBO;
2295         }
2296
2297         /* Is there a change in mtu setting? */
2298         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2299                 return rc;
2300
2301         for (i = 0; i < bp->nr_vnics; i++) {
2302                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2303                 uint16_t size = 0;
2304
2305                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2306                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2307                 if (rc)
2308                         break;
2309
2310                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2311                 size -= RTE_PKTMBUF_HEADROOM;
2312
2313                 if (size < new_mtu) {
2314                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2315                         if (rc)
2316                                 return rc;
2317                 }
2318         }
2319
2320         if (!rc)
2321                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2322
2323         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2324
2325         return rc;
2326 }
2327
2328 static int
2329 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2330 {
2331         struct bnxt *bp = dev->data->dev_private;
2332         uint16_t vlan = bp->vlan;
2333         int rc;
2334
2335         rc = is_bnxt_in_error(bp);
2336         if (rc)
2337                 return rc;
2338
2339         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2340                 PMD_DRV_LOG(ERR,
2341                         "PVID cannot be modified for this function\n");
2342                 return -ENOTSUP;
2343         }
2344         bp->vlan = on ? pvid : 0;
2345
2346         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2347         if (rc)
2348                 bp->vlan = vlan;
2349         return rc;
2350 }
2351
2352 static int
2353 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2354 {
2355         struct bnxt *bp = dev->data->dev_private;
2356         int rc;
2357
2358         rc = is_bnxt_in_error(bp);
2359         if (rc)
2360                 return rc;
2361
2362         return bnxt_hwrm_port_led_cfg(bp, true);
2363 }
2364
2365 static int
2366 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2367 {
2368         struct bnxt *bp = dev->data->dev_private;
2369         int rc;
2370
2371         rc = is_bnxt_in_error(bp);
2372         if (rc)
2373                 return rc;
2374
2375         return bnxt_hwrm_port_led_cfg(bp, false);
2376 }
2377
2378 static uint32_t
2379 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2380 {
2381         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2382         uint32_t desc = 0, raw_cons = 0, cons;
2383         struct bnxt_cp_ring_info *cpr;
2384         struct bnxt_rx_queue *rxq;
2385         struct rx_pkt_cmpl *rxcmp;
2386         int rc;
2387
2388         rc = is_bnxt_in_error(bp);
2389         if (rc)
2390                 return rc;
2391
2392         rxq = dev->data->rx_queues[rx_queue_id];
2393         cpr = rxq->cp_ring;
2394         raw_cons = cpr->cp_raw_cons;
2395
2396         while (1) {
2397                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2398                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2399                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2400
2401                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2402                         break;
2403                 } else {
2404                         raw_cons++;
2405                         desc++;
2406                 }
2407         }
2408
2409         return desc;
2410 }
2411
2412 static int
2413 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2414 {
2415         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2416         struct bnxt_rx_ring_info *rxr;
2417         struct bnxt_cp_ring_info *cpr;
2418         struct bnxt_sw_rx_bd *rx_buf;
2419         struct rx_pkt_cmpl *rxcmp;
2420         uint32_t cons, cp_cons;
2421         int rc;
2422
2423         if (!rxq)
2424                 return -EINVAL;
2425
2426         rc = is_bnxt_in_error(rxq->bp);
2427         if (rc)
2428                 return rc;
2429
2430         cpr = rxq->cp_ring;
2431         rxr = rxq->rx_ring;
2432
2433         if (offset >= rxq->nb_rx_desc)
2434                 return -EINVAL;
2435
2436         cons = RING_CMP(cpr->cp_ring_struct, offset);
2437         cp_cons = cpr->cp_raw_cons;
2438         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2439
2440         if (cons > cp_cons) {
2441                 if (CMPL_VALID(rxcmp, cpr->valid))
2442                         return RTE_ETH_RX_DESC_DONE;
2443         } else {
2444                 if (CMPL_VALID(rxcmp, !cpr->valid))
2445                         return RTE_ETH_RX_DESC_DONE;
2446         }
2447         rx_buf = &rxr->rx_buf_ring[cons];
2448         if (rx_buf->mbuf == NULL)
2449                 return RTE_ETH_RX_DESC_UNAVAIL;
2450
2451
2452         return RTE_ETH_RX_DESC_AVAIL;
2453 }
2454
2455 static int
2456 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2457 {
2458         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2459         struct bnxt_tx_ring_info *txr;
2460         struct bnxt_cp_ring_info *cpr;
2461         struct bnxt_sw_tx_bd *tx_buf;
2462         struct tx_pkt_cmpl *txcmp;
2463         uint32_t cons, cp_cons;
2464         int rc;
2465
2466         if (!txq)
2467                 return -EINVAL;
2468
2469         rc = is_bnxt_in_error(txq->bp);
2470         if (rc)
2471                 return rc;
2472
2473         cpr = txq->cp_ring;
2474         txr = txq->tx_ring;
2475
2476         if (offset >= txq->nb_tx_desc)
2477                 return -EINVAL;
2478
2479         cons = RING_CMP(cpr->cp_ring_struct, offset);
2480         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2481         cp_cons = cpr->cp_raw_cons;
2482
2483         if (cons > cp_cons) {
2484                 if (CMPL_VALID(txcmp, cpr->valid))
2485                         return RTE_ETH_TX_DESC_UNAVAIL;
2486         } else {
2487                 if (CMPL_VALID(txcmp, !cpr->valid))
2488                         return RTE_ETH_TX_DESC_UNAVAIL;
2489         }
2490         tx_buf = &txr->tx_buf_ring[cons];
2491         if (tx_buf->mbuf == NULL)
2492                 return RTE_ETH_TX_DESC_DONE;
2493
2494         return RTE_ETH_TX_DESC_FULL;
2495 }
2496
2497 static struct bnxt_filter_info *
2498 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2499                                 struct rte_eth_ethertype_filter *efilter,
2500                                 struct bnxt_vnic_info *vnic0,
2501                                 struct bnxt_vnic_info *vnic,
2502                                 int *ret)
2503 {
2504         struct bnxt_filter_info *mfilter = NULL;
2505         int match = 0;
2506         *ret = 0;
2507
2508         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2509                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2510                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2511                         " ethertype filter.", efilter->ether_type);
2512                 *ret = -EINVAL;
2513                 goto exit;
2514         }
2515         if (efilter->queue >= bp->rx_nr_rings) {
2516                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2517                 *ret = -EINVAL;
2518                 goto exit;
2519         }
2520
2521         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2522         vnic = &bp->vnic_info[efilter->queue];
2523         if (vnic == NULL) {
2524                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2525                 *ret = -EINVAL;
2526                 goto exit;
2527         }
2528
2529         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2530                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2531                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2532                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2533                              mfilter->flags ==
2534                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2535                              mfilter->ethertype == efilter->ether_type)) {
2536                                 match = 1;
2537                                 break;
2538                         }
2539                 }
2540         } else {
2541                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2542                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2543                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2544                              mfilter->ethertype == efilter->ether_type &&
2545                              mfilter->flags ==
2546                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2547                                 match = 1;
2548                                 break;
2549                         }
2550         }
2551
2552         if (match)
2553                 *ret = -EEXIST;
2554
2555 exit:
2556         return mfilter;
2557 }
2558
2559 static int
2560 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2561                         enum rte_filter_op filter_op,
2562                         void *arg)
2563 {
2564         struct bnxt *bp = dev->data->dev_private;
2565         struct rte_eth_ethertype_filter *efilter =
2566                         (struct rte_eth_ethertype_filter *)arg;
2567         struct bnxt_filter_info *bfilter, *filter1;
2568         struct bnxt_vnic_info *vnic, *vnic0;
2569         int ret;
2570
2571         if (filter_op == RTE_ETH_FILTER_NOP)
2572                 return 0;
2573
2574         if (arg == NULL) {
2575                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2576                             filter_op);
2577                 return -EINVAL;
2578         }
2579
2580         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2581         vnic = &bp->vnic_info[efilter->queue];
2582
2583         switch (filter_op) {
2584         case RTE_ETH_FILTER_ADD:
2585                 bnxt_match_and_validate_ether_filter(bp, efilter,
2586                                                         vnic0, vnic, &ret);
2587                 if (ret < 0)
2588                         return ret;
2589
2590                 bfilter = bnxt_get_unused_filter(bp);
2591                 if (bfilter == NULL) {
2592                         PMD_DRV_LOG(ERR,
2593                                 "Not enough resources for a new filter.\n");
2594                         return -ENOMEM;
2595                 }
2596                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2597                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2598                        RTE_ETHER_ADDR_LEN);
2599                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2600                        RTE_ETHER_ADDR_LEN);
2601                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2602                 bfilter->ethertype = efilter->ether_type;
2603                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2604
2605                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2606                 if (filter1 == NULL) {
2607                         ret = -EINVAL;
2608                         goto cleanup;
2609                 }
2610                 bfilter->enables |=
2611                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2612                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2613
2614                 bfilter->dst_id = vnic->fw_vnic_id;
2615
2616                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2617                         bfilter->flags =
2618                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2619                 }
2620
2621                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2622                 if (ret)
2623                         goto cleanup;
2624                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2625                 break;
2626         case RTE_ETH_FILTER_DELETE:
2627                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2628                                                         vnic0, vnic, &ret);
2629                 if (ret == -EEXIST) {
2630                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2631
2632                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2633                                       next);
2634                         bnxt_free_filter(bp, filter1);
2635                 } else if (ret == 0) {
2636                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2637                 }
2638                 break;
2639         default:
2640                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2641                 ret = -EINVAL;
2642                 goto error;
2643         }
2644         return ret;
2645 cleanup:
2646         bnxt_free_filter(bp, bfilter);
2647 error:
2648         return ret;
2649 }
2650
2651 static inline int
2652 parse_ntuple_filter(struct bnxt *bp,
2653                     struct rte_eth_ntuple_filter *nfilter,
2654                     struct bnxt_filter_info *bfilter)
2655 {
2656         uint32_t en = 0;
2657
2658         if (nfilter->queue >= bp->rx_nr_rings) {
2659                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2660                 return -EINVAL;
2661         }
2662
2663         switch (nfilter->dst_port_mask) {
2664         case UINT16_MAX:
2665                 bfilter->dst_port_mask = -1;
2666                 bfilter->dst_port = nfilter->dst_port;
2667                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2668                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2669                 break;
2670         default:
2671                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2672                 return -EINVAL;
2673         }
2674
2675         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2676         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2677
2678         switch (nfilter->proto_mask) {
2679         case UINT8_MAX:
2680                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2681                         bfilter->ip_protocol = 17;
2682                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2683                         bfilter->ip_protocol = 6;
2684                 else
2685                         return -EINVAL;
2686                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2687                 break;
2688         default:
2689                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2690                 return -EINVAL;
2691         }
2692
2693         switch (nfilter->dst_ip_mask) {
2694         case UINT32_MAX:
2695                 bfilter->dst_ipaddr_mask[0] = -1;
2696                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2697                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2698                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2699                 break;
2700         default:
2701                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2702                 return -EINVAL;
2703         }
2704
2705         switch (nfilter->src_ip_mask) {
2706         case UINT32_MAX:
2707                 bfilter->src_ipaddr_mask[0] = -1;
2708                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2709                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2710                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2711                 break;
2712         default:
2713                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2714                 return -EINVAL;
2715         }
2716
2717         switch (nfilter->src_port_mask) {
2718         case UINT16_MAX:
2719                 bfilter->src_port_mask = -1;
2720                 bfilter->src_port = nfilter->src_port;
2721                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2722                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2723                 break;
2724         default:
2725                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2726                 return -EINVAL;
2727         }
2728
2729         bfilter->enables = en;
2730         return 0;
2731 }
2732
2733 static struct bnxt_filter_info*
2734 bnxt_match_ntuple_filter(struct bnxt *bp,
2735                          struct bnxt_filter_info *bfilter,
2736                          struct bnxt_vnic_info **mvnic)
2737 {
2738         struct bnxt_filter_info *mfilter = NULL;
2739         int i;
2740
2741         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2742                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2743                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2744                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2745                             bfilter->src_ipaddr_mask[0] ==
2746                             mfilter->src_ipaddr_mask[0] &&
2747                             bfilter->src_port == mfilter->src_port &&
2748                             bfilter->src_port_mask == mfilter->src_port_mask &&
2749                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2750                             bfilter->dst_ipaddr_mask[0] ==
2751                             mfilter->dst_ipaddr_mask[0] &&
2752                             bfilter->dst_port == mfilter->dst_port &&
2753                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2754                             bfilter->flags == mfilter->flags &&
2755                             bfilter->enables == mfilter->enables) {
2756                                 if (mvnic)
2757                                         *mvnic = vnic;
2758                                 return mfilter;
2759                         }
2760                 }
2761         }
2762         return NULL;
2763 }
2764
2765 static int
2766 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2767                        struct rte_eth_ntuple_filter *nfilter,
2768                        enum rte_filter_op filter_op)
2769 {
2770         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2771         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2772         int ret;
2773
2774         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2775                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2776                 return -EINVAL;
2777         }
2778
2779         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2780                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2781                 return -EINVAL;
2782         }
2783
2784         bfilter = bnxt_get_unused_filter(bp);
2785         if (bfilter == NULL) {
2786                 PMD_DRV_LOG(ERR,
2787                         "Not enough resources for a new filter.\n");
2788                 return -ENOMEM;
2789         }
2790         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2791         if (ret < 0)
2792                 goto free_filter;
2793
2794         vnic = &bp->vnic_info[nfilter->queue];
2795         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2796         filter1 = STAILQ_FIRST(&vnic0->filter);
2797         if (filter1 == NULL) {
2798                 ret = -EINVAL;
2799                 goto free_filter;
2800         }
2801
2802         bfilter->dst_id = vnic->fw_vnic_id;
2803         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2804         bfilter->enables |=
2805                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2806         bfilter->ethertype = 0x800;
2807         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2808
2809         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2810
2811         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2812             bfilter->dst_id == mfilter->dst_id) {
2813                 PMD_DRV_LOG(ERR, "filter exists.\n");
2814                 ret = -EEXIST;
2815                 goto free_filter;
2816         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2817                    bfilter->dst_id != mfilter->dst_id) {
2818                 mfilter->dst_id = vnic->fw_vnic_id;
2819                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2820                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2821                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2822                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2823                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2824                 goto free_filter;
2825         }
2826         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2827                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2828                 ret = -ENOENT;
2829                 goto free_filter;
2830         }
2831
2832         if (filter_op == RTE_ETH_FILTER_ADD) {
2833                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2834                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2835                 if (ret)
2836                         goto free_filter;
2837                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2838         } else {
2839                 if (mfilter == NULL) {
2840                         /* This should not happen. But for Coverity! */
2841                         ret = -ENOENT;
2842                         goto free_filter;
2843                 }
2844                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2845
2846                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2847                 bnxt_free_filter(bp, mfilter);
2848                 bnxt_free_filter(bp, bfilter);
2849         }
2850
2851         return 0;
2852 free_filter:
2853         bnxt_free_filter(bp, bfilter);
2854         return ret;
2855 }
2856
2857 static int
2858 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2859                         enum rte_filter_op filter_op,
2860                         void *arg)
2861 {
2862         struct bnxt *bp = dev->data->dev_private;
2863         int ret;
2864
2865         if (filter_op == RTE_ETH_FILTER_NOP)
2866                 return 0;
2867
2868         if (arg == NULL) {
2869                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2870                             filter_op);
2871                 return -EINVAL;
2872         }
2873
2874         switch (filter_op) {
2875         case RTE_ETH_FILTER_ADD:
2876                 ret = bnxt_cfg_ntuple_filter(bp,
2877                         (struct rte_eth_ntuple_filter *)arg,
2878                         filter_op);
2879                 break;
2880         case RTE_ETH_FILTER_DELETE:
2881                 ret = bnxt_cfg_ntuple_filter(bp,
2882                         (struct rte_eth_ntuple_filter *)arg,
2883                         filter_op);
2884                 break;
2885         default:
2886                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2887                 ret = -EINVAL;
2888                 break;
2889         }
2890         return ret;
2891 }
2892
2893 static int
2894 bnxt_parse_fdir_filter(struct bnxt *bp,
2895                        struct rte_eth_fdir_filter *fdir,
2896                        struct bnxt_filter_info *filter)
2897 {
2898         enum rte_fdir_mode fdir_mode =
2899                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2900         struct bnxt_vnic_info *vnic0, *vnic;
2901         struct bnxt_filter_info *filter1;
2902         uint32_t en = 0;
2903         int i;
2904
2905         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2906                 return -EINVAL;
2907
2908         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2909         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2910
2911         switch (fdir->input.flow_type) {
2912         case RTE_ETH_FLOW_IPV4:
2913         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2914                 /* FALLTHROUGH */
2915                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2917                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2919                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2920                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2921                 filter->ip_addr_type =
2922                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2923                 filter->src_ipaddr_mask[0] = 0xffffffff;
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2925                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2926                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2927                 filter->ethertype = 0x800;
2928                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2929                 break;
2930         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2931                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2932                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2933                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2934                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2935                 filter->dst_port_mask = 0xffff;
2936                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2937                 filter->src_port_mask = 0xffff;
2938                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2939                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2940                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2941                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2942                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2943                 filter->ip_protocol = 6;
2944                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2945                 filter->ip_addr_type =
2946                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2947                 filter->src_ipaddr_mask[0] = 0xffffffff;
2948                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2949                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2950                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2951                 filter->ethertype = 0x800;
2952                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2953                 break;
2954         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2955                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2956                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2957                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2958                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2959                 filter->dst_port_mask = 0xffff;
2960                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2961                 filter->src_port_mask = 0xffff;
2962                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2963                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2964                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2965                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2966                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2967                 filter->ip_protocol = 17;
2968                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2969                 filter->ip_addr_type =
2970                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2971                 filter->src_ipaddr_mask[0] = 0xffffffff;
2972                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2973                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2974                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2975                 filter->ethertype = 0x800;
2976                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2977                 break;
2978         case RTE_ETH_FLOW_IPV6:
2979         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2980                 /* FALLTHROUGH */
2981                 filter->ip_addr_type =
2982                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2983                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2984                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2985                 rte_memcpy(filter->src_ipaddr,
2986                            fdir->input.flow.ipv6_flow.src_ip, 16);
2987                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2988                 rte_memcpy(filter->dst_ipaddr,
2989                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2990                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2991                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2992                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2993                 memset(filter->src_ipaddr_mask, 0xff, 16);
2994                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2995                 filter->ethertype = 0x86dd;
2996                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2997                 break;
2998         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2999                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3000                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3001                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3002                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3003                 filter->dst_port_mask = 0xffff;
3004                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3005                 filter->src_port_mask = 0xffff;
3006                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3007                 filter->ip_addr_type =
3008                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3009                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3010                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3011                 rte_memcpy(filter->src_ipaddr,
3012                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3013                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3014                 rte_memcpy(filter->dst_ipaddr,
3015                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3016                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3017                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3018                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3019                 memset(filter->src_ipaddr_mask, 0xff, 16);
3020                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3021                 filter->ethertype = 0x86dd;
3022                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3023                 break;
3024         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3025                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3026                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3027                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3028                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3029                 filter->dst_port_mask = 0xffff;
3030                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3031                 filter->src_port_mask = 0xffff;
3032                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3033                 filter->ip_addr_type =
3034                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3035                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3036                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3037                 rte_memcpy(filter->src_ipaddr,
3038                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3039                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3040                 rte_memcpy(filter->dst_ipaddr,
3041                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3042                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3043                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3044                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3045                 memset(filter->src_ipaddr_mask, 0xff, 16);
3046                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3047                 filter->ethertype = 0x86dd;
3048                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3049                 break;
3050         case RTE_ETH_FLOW_L2_PAYLOAD:
3051                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3052                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3053                 break;
3054         case RTE_ETH_FLOW_VXLAN:
3055                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3056                         return -EINVAL;
3057                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3058                 filter->tunnel_type =
3059                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3060                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3061                 break;
3062         case RTE_ETH_FLOW_NVGRE:
3063                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3064                         return -EINVAL;
3065                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3066                 filter->tunnel_type =
3067                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3068                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3069                 break;
3070         case RTE_ETH_FLOW_UNKNOWN:
3071         case RTE_ETH_FLOW_RAW:
3072         case RTE_ETH_FLOW_FRAG_IPV4:
3073         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3074         case RTE_ETH_FLOW_FRAG_IPV6:
3075         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3076         case RTE_ETH_FLOW_IPV6_EX:
3077         case RTE_ETH_FLOW_IPV6_TCP_EX:
3078         case RTE_ETH_FLOW_IPV6_UDP_EX:
3079         case RTE_ETH_FLOW_GENEVE:
3080                 /* FALLTHROUGH */
3081         default:
3082                 return -EINVAL;
3083         }
3084
3085         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3086         vnic = &bp->vnic_info[fdir->action.rx_queue];
3087         if (vnic == NULL) {
3088                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3089                 return -EINVAL;
3090         }
3091
3092         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3093                 rte_memcpy(filter->dst_macaddr,
3094                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3095                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3096         }
3097
3098         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3099                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3100                 filter1 = STAILQ_FIRST(&vnic0->filter);
3101                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3102         } else {
3103                 filter->dst_id = vnic->fw_vnic_id;
3104                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3105                         if (filter->dst_macaddr[i] == 0x00)
3106                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3107                         else
3108                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3109         }
3110
3111         if (filter1 == NULL)
3112                 return -EINVAL;
3113
3114         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3115         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3116
3117         filter->enables = en;
3118
3119         return 0;
3120 }
3121
3122 static struct bnxt_filter_info *
3123 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3124                 struct bnxt_vnic_info **mvnic)
3125 {
3126         struct bnxt_filter_info *mf = NULL;
3127         int i;
3128
3129         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3130                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3131
3132                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3133                         if (mf->filter_type == nf->filter_type &&
3134                             mf->flags == nf->flags &&
3135                             mf->src_port == nf->src_port &&
3136                             mf->src_port_mask == nf->src_port_mask &&
3137                             mf->dst_port == nf->dst_port &&
3138                             mf->dst_port_mask == nf->dst_port_mask &&
3139                             mf->ip_protocol == nf->ip_protocol &&
3140                             mf->ip_addr_type == nf->ip_addr_type &&
3141                             mf->ethertype == nf->ethertype &&
3142                             mf->vni == nf->vni &&
3143                             mf->tunnel_type == nf->tunnel_type &&
3144                             mf->l2_ovlan == nf->l2_ovlan &&
3145                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3146                             mf->l2_ivlan == nf->l2_ivlan &&
3147                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3148                             !memcmp(mf->l2_addr, nf->l2_addr,
3149                                     RTE_ETHER_ADDR_LEN) &&
3150                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3151                                     RTE_ETHER_ADDR_LEN) &&
3152                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3153                                     RTE_ETHER_ADDR_LEN) &&
3154                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3155                                     RTE_ETHER_ADDR_LEN) &&
3156                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3157                                     sizeof(nf->src_ipaddr)) &&
3158                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3159                                     sizeof(nf->src_ipaddr_mask)) &&
3160                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3161                                     sizeof(nf->dst_ipaddr)) &&
3162                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3163                                     sizeof(nf->dst_ipaddr_mask))) {
3164                                 if (mvnic)
3165                                         *mvnic = vnic;
3166                                 return mf;
3167                         }
3168                 }
3169         }
3170         return NULL;
3171 }
3172
3173 static int
3174 bnxt_fdir_filter(struct rte_eth_dev *dev,
3175                  enum rte_filter_op filter_op,
3176                  void *arg)
3177 {
3178         struct bnxt *bp = dev->data->dev_private;
3179         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3180         struct bnxt_filter_info *filter, *match;
3181         struct bnxt_vnic_info *vnic, *mvnic;
3182         int ret = 0, i;
3183
3184         if (filter_op == RTE_ETH_FILTER_NOP)
3185                 return 0;
3186
3187         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3188                 return -EINVAL;
3189
3190         switch (filter_op) {
3191         case RTE_ETH_FILTER_ADD:
3192         case RTE_ETH_FILTER_DELETE:
3193                 /* FALLTHROUGH */
3194                 filter = bnxt_get_unused_filter(bp);
3195                 if (filter == NULL) {
3196                         PMD_DRV_LOG(ERR,
3197                                 "Not enough resources for a new flow.\n");
3198                         return -ENOMEM;
3199                 }
3200
3201                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3202                 if (ret != 0)
3203                         goto free_filter;
3204                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3205
3206                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3207                         vnic = &bp->vnic_info[0];
3208                 else
3209                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3210
3211                 match = bnxt_match_fdir(bp, filter, &mvnic);
3212                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3213                         if (match->dst_id == vnic->fw_vnic_id) {
3214                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3215                                 ret = -EEXIST;
3216                                 goto free_filter;
3217                         } else {
3218                                 match->dst_id = vnic->fw_vnic_id;
3219                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3220                                                                   match->dst_id,
3221                                                                   match);
3222                                 STAILQ_REMOVE(&mvnic->filter, match,
3223                                               bnxt_filter_info, next);
3224                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3225                                 PMD_DRV_LOG(ERR,
3226                                         "Filter with matching pattern exist\n");
3227                                 PMD_DRV_LOG(ERR,
3228                                         "Updated it to new destination q\n");
3229                                 goto free_filter;
3230                         }
3231                 }
3232                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3233                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3234                         ret = -ENOENT;
3235                         goto free_filter;
3236                 }
3237
3238                 if (filter_op == RTE_ETH_FILTER_ADD) {
3239                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3240                                                           filter->dst_id,
3241                                                           filter);
3242                         if (ret)
3243                                 goto free_filter;
3244                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3245                 } else {
3246                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3247                         STAILQ_REMOVE(&vnic->filter, match,
3248                                       bnxt_filter_info, next);
3249                         bnxt_free_filter(bp, match);
3250                         bnxt_free_filter(bp, filter);
3251                 }
3252                 break;
3253         case RTE_ETH_FILTER_FLUSH:
3254                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3255                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3256
3257                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3258                                 if (filter->filter_type ==
3259                                     HWRM_CFA_NTUPLE_FILTER) {
3260                                         ret =
3261                                         bnxt_hwrm_clear_ntuple_filter(bp,
3262                                                                       filter);
3263                                         STAILQ_REMOVE(&vnic->filter, filter,
3264                                                       bnxt_filter_info, next);
3265                                 }
3266                         }
3267                 }
3268                 return ret;
3269         case RTE_ETH_FILTER_UPDATE:
3270         case RTE_ETH_FILTER_STATS:
3271         case RTE_ETH_FILTER_INFO:
3272                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3273                 break;
3274         default:
3275                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3276                 ret = -EINVAL;
3277                 break;
3278         }
3279         return ret;
3280
3281 free_filter:
3282         bnxt_free_filter(bp, filter);
3283         return ret;
3284 }
3285
3286 static int
3287 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3288                     enum rte_filter_type filter_type,
3289                     enum rte_filter_op filter_op, void *arg)
3290 {
3291         int ret = 0;
3292
3293         ret = is_bnxt_in_error(dev->data->dev_private);
3294         if (ret)
3295                 return ret;
3296
3297         switch (filter_type) {
3298         case RTE_ETH_FILTER_TUNNEL:
3299                 PMD_DRV_LOG(ERR,
3300                         "filter type: %d: To be implemented\n", filter_type);
3301                 break;
3302         case RTE_ETH_FILTER_FDIR:
3303                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3304                 break;
3305         case RTE_ETH_FILTER_NTUPLE:
3306                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3307                 break;
3308         case RTE_ETH_FILTER_ETHERTYPE:
3309                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3310                 break;
3311         case RTE_ETH_FILTER_GENERIC:
3312                 if (filter_op != RTE_ETH_FILTER_GET)
3313                         return -EINVAL;
3314                 *(const void **)arg = &bnxt_flow_ops;
3315                 break;
3316         default:
3317                 PMD_DRV_LOG(ERR,
3318                         "Filter type (%d) not supported", filter_type);
3319                 ret = -EINVAL;
3320                 break;
3321         }
3322         return ret;
3323 }
3324
3325 static const uint32_t *
3326 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3327 {
3328         static const uint32_t ptypes[] = {
3329                 RTE_PTYPE_L2_ETHER_VLAN,
3330                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3331                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3332                 RTE_PTYPE_L4_ICMP,
3333                 RTE_PTYPE_L4_TCP,
3334                 RTE_PTYPE_L4_UDP,
3335                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3336                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3337                 RTE_PTYPE_INNER_L4_ICMP,
3338                 RTE_PTYPE_INNER_L4_TCP,
3339                 RTE_PTYPE_INNER_L4_UDP,
3340                 RTE_PTYPE_UNKNOWN
3341         };
3342
3343         if (!dev->rx_pkt_burst)
3344                 return NULL;
3345
3346         return ptypes;
3347 }
3348
3349 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3350                          int reg_win)
3351 {
3352         uint32_t reg_base = *reg_arr & 0xfffff000;
3353         uint32_t win_off;
3354         int i;
3355
3356         for (i = 0; i < count; i++) {
3357                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3358                         return -ERANGE;
3359         }
3360         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3361         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3362         return 0;
3363 }
3364
3365 static int bnxt_map_ptp_regs(struct bnxt *bp)
3366 {
3367         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3368         uint32_t *reg_arr;
3369         int rc, i;
3370
3371         reg_arr = ptp->rx_regs;
3372         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3373         if (rc)
3374                 return rc;
3375
3376         reg_arr = ptp->tx_regs;
3377         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3378         if (rc)
3379                 return rc;
3380
3381         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3382                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3383
3384         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3385                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3386
3387         return 0;
3388 }
3389
3390 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3391 {
3392         rte_write32(0, (uint8_t *)bp->bar0 +
3393                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3394         rte_write32(0, (uint8_t *)bp->bar0 +
3395                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3396 }
3397
3398 static uint64_t bnxt_cc_read(struct bnxt *bp)
3399 {
3400         uint64_t ns;
3401
3402         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3403                               BNXT_GRCPF_REG_SYNC_TIME));
3404         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3405                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3406         return ns;
3407 }
3408
3409 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3410 {
3411         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3412         uint32_t fifo;
3413
3414         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3415                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3416         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3417                 return -EAGAIN;
3418
3419         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3421         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3422                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3423         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3424                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3425
3426         return 0;
3427 }
3428
3429 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3430 {
3431         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3432         struct bnxt_pf_info *pf = &bp->pf;
3433         uint16_t port_id;
3434         uint32_t fifo;
3435
3436         if (!ptp)
3437                 return -ENODEV;
3438
3439         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3440                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3441         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3442                 return -EAGAIN;
3443
3444         port_id = pf->port_id;
3445         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3446                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3447
3448         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3449                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3450         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3451 /*              bnxt_clr_rx_ts(bp);       TBD  */
3452                 return -EBUSY;
3453         }
3454
3455         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3456                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3457         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3458                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3459
3460         return 0;
3461 }
3462
3463 static int
3464 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3465 {
3466         uint64_t ns;
3467         struct bnxt *bp = dev->data->dev_private;
3468         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3469
3470         if (!ptp)
3471                 return 0;
3472
3473         ns = rte_timespec_to_ns(ts);
3474         /* Set the timecounters to a new value. */
3475         ptp->tc.nsec = ns;
3476
3477         return 0;
3478 }
3479
3480 static int
3481 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3482 {
3483         struct bnxt *bp = dev->data->dev_private;
3484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3485         uint64_t ns, systime_cycles = 0;
3486         int rc = 0;
3487
3488         if (!ptp)
3489                 return 0;
3490
3491         if (BNXT_CHIP_THOR(bp))
3492                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3493                                              &systime_cycles);
3494         else
3495                 systime_cycles = bnxt_cc_read(bp);
3496
3497         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3498         *ts = rte_ns_to_timespec(ns);
3499
3500         return rc;
3501 }
3502 static int
3503 bnxt_timesync_enable(struct rte_eth_dev *dev)
3504 {
3505         struct bnxt *bp = dev->data->dev_private;
3506         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3507         uint32_t shift = 0;
3508         int rc;
3509
3510         if (!ptp)
3511                 return 0;
3512
3513         ptp->rx_filter = 1;
3514         ptp->tx_tstamp_en = 1;
3515         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3516
3517         rc = bnxt_hwrm_ptp_cfg(bp);
3518         if (rc)
3519                 return rc;
3520
3521         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3522         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3523         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3524
3525         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3526         ptp->tc.cc_shift = shift;
3527         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3528
3529         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3530         ptp->rx_tstamp_tc.cc_shift = shift;
3531         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3532
3533         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3534         ptp->tx_tstamp_tc.cc_shift = shift;
3535         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3536
3537         if (!BNXT_CHIP_THOR(bp))
3538                 bnxt_map_ptp_regs(bp);
3539
3540         return 0;
3541 }
3542
3543 static int
3544 bnxt_timesync_disable(struct rte_eth_dev *dev)
3545 {
3546         struct bnxt *bp = dev->data->dev_private;
3547         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3548
3549         if (!ptp)
3550                 return 0;
3551
3552         ptp->rx_filter = 0;
3553         ptp->tx_tstamp_en = 0;
3554         ptp->rxctl = 0;
3555
3556         bnxt_hwrm_ptp_cfg(bp);
3557
3558         if (!BNXT_CHIP_THOR(bp))
3559                 bnxt_unmap_ptp_regs(bp);
3560
3561         return 0;
3562 }
3563
3564 static int
3565 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3566                                  struct timespec *timestamp,
3567                                  uint32_t flags __rte_unused)
3568 {
3569         struct bnxt *bp = dev->data->dev_private;
3570         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3571         uint64_t rx_tstamp_cycles = 0;
3572         uint64_t ns;
3573
3574         if (!ptp)
3575                 return 0;
3576
3577         if (BNXT_CHIP_THOR(bp))
3578                 rx_tstamp_cycles = ptp->rx_timestamp;
3579         else
3580                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3581
3582         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3583         *timestamp = rte_ns_to_timespec(ns);
3584         return  0;
3585 }
3586
3587 static int
3588 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3589                                  struct timespec *timestamp)
3590 {
3591         struct bnxt *bp = dev->data->dev_private;
3592         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3593         uint64_t tx_tstamp_cycles = 0;
3594         uint64_t ns;
3595         int rc = 0;
3596
3597         if (!ptp)
3598                 return 0;
3599
3600         if (BNXT_CHIP_THOR(bp))
3601                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3602                                              &tx_tstamp_cycles);
3603         else
3604                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3605
3606         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3607         *timestamp = rte_ns_to_timespec(ns);
3608
3609         return rc;
3610 }
3611
3612 static int
3613 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3614 {
3615         struct bnxt *bp = dev->data->dev_private;
3616         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3617
3618         if (!ptp)
3619                 return 0;
3620
3621         ptp->tc.nsec += delta;
3622
3623         return 0;
3624 }
3625
3626 static int
3627 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3628 {
3629         struct bnxt *bp = dev->data->dev_private;
3630         int rc;
3631         uint32_t dir_entries;
3632         uint32_t entry_length;
3633
3634         rc = is_bnxt_in_error(bp);
3635         if (rc)
3636                 return rc;
3637
3638         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3639                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3640                     bp->pdev->addr.devid, bp->pdev->addr.function);
3641
3642         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3643         if (rc != 0)
3644                 return rc;
3645
3646         return dir_entries * entry_length;
3647 }
3648
3649 static int
3650 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3651                 struct rte_dev_eeprom_info *in_eeprom)
3652 {
3653         struct bnxt *bp = dev->data->dev_private;
3654         uint32_t index;
3655         uint32_t offset;
3656         int rc;
3657
3658         rc = is_bnxt_in_error(bp);
3659         if (rc)
3660                 return rc;
3661
3662         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3663                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3664                     bp->pdev->addr.devid, bp->pdev->addr.function,
3665                     in_eeprom->offset, in_eeprom->length);
3666
3667         if (in_eeprom->offset == 0) /* special offset value to get directory */
3668                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3669                                                 in_eeprom->data);
3670
3671         index = in_eeprom->offset >> 24;
3672         offset = in_eeprom->offset & 0xffffff;
3673
3674         if (index != 0)
3675                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3676                                            in_eeprom->length, in_eeprom->data);
3677
3678         return 0;
3679 }
3680
3681 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3682 {
3683         switch (dir_type) {
3684         case BNX_DIR_TYPE_CHIMP_PATCH:
3685         case BNX_DIR_TYPE_BOOTCODE:
3686         case BNX_DIR_TYPE_BOOTCODE_2:
3687         case BNX_DIR_TYPE_APE_FW:
3688         case BNX_DIR_TYPE_APE_PATCH:
3689         case BNX_DIR_TYPE_KONG_FW:
3690         case BNX_DIR_TYPE_KONG_PATCH:
3691         case BNX_DIR_TYPE_BONO_FW:
3692         case BNX_DIR_TYPE_BONO_PATCH:
3693                 /* FALLTHROUGH */
3694                 return true;
3695         }
3696
3697         return false;
3698 }
3699
3700 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3701 {
3702         switch (dir_type) {
3703         case BNX_DIR_TYPE_AVS:
3704         case BNX_DIR_TYPE_EXP_ROM_MBA:
3705         case BNX_DIR_TYPE_PCIE:
3706         case BNX_DIR_TYPE_TSCF_UCODE:
3707         case BNX_DIR_TYPE_EXT_PHY:
3708         case BNX_DIR_TYPE_CCM:
3709         case BNX_DIR_TYPE_ISCSI_BOOT:
3710         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3711         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3712                 /* FALLTHROUGH */
3713                 return true;
3714         }
3715
3716         return false;
3717 }
3718
3719 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3720 {
3721         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3722                 bnxt_dir_type_is_other_exec_format(dir_type);
3723 }
3724
3725 static int
3726 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3727                 struct rte_dev_eeprom_info *in_eeprom)
3728 {
3729         struct bnxt *bp = dev->data->dev_private;
3730         uint8_t index, dir_op;
3731         uint16_t type, ext, ordinal, attr;
3732         int rc;
3733
3734         rc = is_bnxt_in_error(bp);
3735         if (rc)
3736                 return rc;
3737
3738         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3739                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3740                     bp->pdev->addr.devid, bp->pdev->addr.function,
3741                     in_eeprom->offset, in_eeprom->length);
3742
3743         if (!BNXT_PF(bp)) {
3744                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3745                 return -EINVAL;
3746         }
3747
3748         type = in_eeprom->magic >> 16;
3749
3750         if (type == 0xffff) { /* special value for directory operations */
3751                 index = in_eeprom->magic & 0xff;
3752                 dir_op = in_eeprom->magic >> 8;
3753                 if (index == 0)
3754                         return -EINVAL;
3755                 switch (dir_op) {
3756                 case 0x0e: /* erase */
3757                         if (in_eeprom->offset != ~in_eeprom->magic)
3758                                 return -EINVAL;
3759                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3760                 default:
3761                         return -EINVAL;
3762                 }
3763         }
3764
3765         /* Create or re-write an NVM item: */
3766         if (bnxt_dir_type_is_executable(type) == true)
3767                 return -EOPNOTSUPP;
3768         ext = in_eeprom->magic & 0xffff;
3769         ordinal = in_eeprom->offset >> 16;
3770         attr = in_eeprom->offset & 0xffff;
3771
3772         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3773                                      in_eeprom->data, in_eeprom->length);
3774 }
3775
3776 /*
3777  * Initialization
3778  */
3779
3780 static const struct eth_dev_ops bnxt_dev_ops = {
3781         .dev_infos_get = bnxt_dev_info_get_op,
3782         .dev_close = bnxt_dev_close_op,
3783         .dev_configure = bnxt_dev_configure_op,
3784         .dev_start = bnxt_dev_start_op,
3785         .dev_stop = bnxt_dev_stop_op,
3786         .dev_set_link_up = bnxt_dev_set_link_up_op,
3787         .dev_set_link_down = bnxt_dev_set_link_down_op,
3788         .stats_get = bnxt_stats_get_op,
3789         .stats_reset = bnxt_stats_reset_op,
3790         .rx_queue_setup = bnxt_rx_queue_setup_op,
3791         .rx_queue_release = bnxt_rx_queue_release_op,
3792         .tx_queue_setup = bnxt_tx_queue_setup_op,
3793         .tx_queue_release = bnxt_tx_queue_release_op,
3794         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3795         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3796         .reta_update = bnxt_reta_update_op,
3797         .reta_query = bnxt_reta_query_op,
3798         .rss_hash_update = bnxt_rss_hash_update_op,
3799         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3800         .link_update = bnxt_link_update_op,
3801         .promiscuous_enable = bnxt_promiscuous_enable_op,
3802         .promiscuous_disable = bnxt_promiscuous_disable_op,
3803         .allmulticast_enable = bnxt_allmulticast_enable_op,
3804         .allmulticast_disable = bnxt_allmulticast_disable_op,
3805         .mac_addr_add = bnxt_mac_addr_add_op,
3806         .mac_addr_remove = bnxt_mac_addr_remove_op,
3807         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3808         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3809         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3810         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3811         .vlan_filter_set = bnxt_vlan_filter_set_op,
3812         .vlan_offload_set = bnxt_vlan_offload_set_op,
3813         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3814         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3815         .mtu_set = bnxt_mtu_set_op,
3816         .mac_addr_set = bnxt_set_default_mac_addr_op,
3817         .xstats_get = bnxt_dev_xstats_get_op,
3818         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3819         .xstats_reset = bnxt_dev_xstats_reset_op,
3820         .fw_version_get = bnxt_fw_version_get,
3821         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3822         .rxq_info_get = bnxt_rxq_info_get_op,
3823         .txq_info_get = bnxt_txq_info_get_op,
3824         .dev_led_on = bnxt_dev_led_on_op,
3825         .dev_led_off = bnxt_dev_led_off_op,
3826         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3827         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3828         .rx_queue_count = bnxt_rx_queue_count_op,
3829         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3830         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3831         .rx_queue_start = bnxt_rx_queue_start,
3832         .rx_queue_stop = bnxt_rx_queue_stop,
3833         .tx_queue_start = bnxt_tx_queue_start,
3834         .tx_queue_stop = bnxt_tx_queue_stop,
3835         .filter_ctrl = bnxt_filter_ctrl_op,
3836         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3837         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3838         .get_eeprom           = bnxt_get_eeprom_op,
3839         .set_eeprom           = bnxt_set_eeprom_op,
3840         .timesync_enable      = bnxt_timesync_enable,
3841         .timesync_disable     = bnxt_timesync_disable,
3842         .timesync_read_time   = bnxt_timesync_read_time,
3843         .timesync_write_time   = bnxt_timesync_write_time,
3844         .timesync_adjust_time = bnxt_timesync_adjust_time,
3845         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3846         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3847 };
3848
3849 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3850 {
3851         uint32_t offset;
3852
3853         /* Only pre-map the reset GRC registers using window 3 */
3854         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3855                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3856
3857         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3858
3859         return offset;
3860 }
3861
3862 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3863 {
3864         struct bnxt_error_recovery_info *info = bp->recovery_info;
3865         uint32_t reg_base = 0xffffffff;
3866         int i;
3867
3868         /* Only pre-map the monitoring GRC registers using window 2 */
3869         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3870                 uint32_t reg = info->status_regs[i];
3871
3872                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3873                         continue;
3874
3875                 if (reg_base == 0xffffffff)
3876                         reg_base = reg & 0xfffff000;
3877                 if ((reg & 0xfffff000) != reg_base)
3878                         return -ERANGE;
3879
3880                 /* Use mask 0xffc as the Lower 2 bits indicates
3881                  * address space location
3882                  */
3883                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3884                                                 (reg & 0xffc);
3885         }
3886
3887         if (reg_base == 0xffffffff)
3888                 return 0;
3889
3890         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3891                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3892
3893         return 0;
3894 }
3895
3896 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3897 {
3898         struct bnxt_error_recovery_info *info = bp->recovery_info;
3899         uint32_t delay = info->delay_after_reset[index];
3900         uint32_t val = info->reset_reg_val[index];
3901         uint32_t reg = info->reset_reg[index];
3902         uint32_t type, offset;
3903
3904         type = BNXT_FW_STATUS_REG_TYPE(reg);
3905         offset = BNXT_FW_STATUS_REG_OFF(reg);
3906
3907         switch (type) {
3908         case BNXT_FW_STATUS_REG_TYPE_CFG:
3909                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3910                 break;
3911         case BNXT_FW_STATUS_REG_TYPE_GRC:
3912                 offset = bnxt_map_reset_regs(bp, offset);
3913                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3914                 break;
3915         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3916                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3917                 break;
3918         }
3919         /* wait on a specific interval of time until core reset is complete */
3920         if (delay)
3921                 rte_delay_ms(delay);
3922 }
3923
3924 static void bnxt_dev_cleanup(struct bnxt *bp)
3925 {
3926         bnxt_set_hwrm_link_config(bp, false);
3927         bp->link_info.link_up = 0;
3928         if (bp->eth_dev->data->dev_started)
3929                 bnxt_dev_stop_op(bp->eth_dev);
3930
3931         bnxt_uninit_resources(bp, true);
3932 }
3933
3934 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3935 {
3936         struct rte_eth_dev *dev = bp->eth_dev;
3937         struct rte_vlan_filter_conf *vfc;
3938         int vidx, vbit, rc;
3939         uint16_t vlan_id;
3940
3941         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3942                 vfc = &dev->data->vlan_filter_conf;
3943                 vidx = vlan_id / 64;
3944                 vbit = vlan_id % 64;
3945
3946                 /* Each bit corresponds to a VLAN id */
3947                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3948                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3949                         if (rc)
3950                                 return rc;
3951                 }
3952         }
3953
3954         return 0;
3955 }
3956
3957 static int bnxt_restore_mac_filters(struct bnxt *bp)
3958 {
3959         struct rte_eth_dev *dev = bp->eth_dev;
3960         struct rte_eth_dev_info dev_info;
3961         struct rte_ether_addr *addr;
3962         uint64_t pool_mask;
3963         uint32_t pool = 0;
3964         uint16_t i;
3965         int rc;
3966
3967         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3968                 return 0;
3969
3970         rc = bnxt_dev_info_get_op(dev, &dev_info);
3971         if (rc)
3972                 return rc;
3973
3974         /* replay MAC address configuration */
3975         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3976                 addr = &dev->data->mac_addrs[i];
3977
3978                 /* skip zero address */
3979                 if (rte_is_zero_ether_addr(addr))
3980                         continue;
3981
3982                 pool = 0;
3983                 pool_mask = dev->data->mac_pool_sel[i];
3984
3985                 do {
3986                         if (pool_mask & 1ULL) {
3987                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3988                                 if (rc)
3989                                         return rc;
3990                         }
3991                         pool_mask >>= 1;
3992                         pool++;
3993                 } while (pool_mask);
3994         }
3995
3996         return 0;
3997 }
3998
3999 static int bnxt_restore_filters(struct bnxt *bp)
4000 {
4001         struct rte_eth_dev *dev = bp->eth_dev;
4002         int ret = 0;
4003
4004         if (dev->data->all_multicast) {
4005                 ret = bnxt_allmulticast_enable_op(dev);
4006                 if (ret)
4007                         return ret;
4008         }
4009         if (dev->data->promiscuous) {
4010                 ret = bnxt_promiscuous_enable_op(dev);
4011                 if (ret)
4012                         return ret;
4013         }
4014
4015         ret = bnxt_restore_mac_filters(bp);
4016         if (ret)
4017                 return ret;
4018
4019         ret = bnxt_restore_vlan_filters(bp);
4020         /* TODO restore other filters as well */
4021         return ret;
4022 }
4023
4024 static void bnxt_dev_recover(void *arg)
4025 {
4026         struct bnxt *bp = arg;
4027         int timeout = bp->fw_reset_max_msecs;
4028         int rc = 0;
4029
4030         /* Clear Error flag so that device re-init should happen */
4031         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4032
4033         do {
4034                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4035                 if (rc == 0)
4036                         break;
4037                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4038                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4039         } while (rc && timeout);
4040
4041         if (rc) {
4042                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4043                 goto err;
4044         }
4045
4046         rc = bnxt_init_resources(bp, true);
4047         if (rc) {
4048                 PMD_DRV_LOG(ERR,
4049                             "Failed to initialize resources after reset\n");
4050                 goto err;
4051         }
4052         /* clear reset flag as the device is initialized now */
4053         bp->flags &= ~BNXT_FLAG_FW_RESET;
4054
4055         rc = bnxt_dev_start_op(bp->eth_dev);
4056         if (rc) {
4057                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4058                 goto err_start;
4059         }
4060
4061         rc = bnxt_restore_filters(bp);
4062         if (rc)
4063                 goto err_start;
4064
4065         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4066         return;
4067 err_start:
4068         bnxt_dev_stop_op(bp->eth_dev);
4069 err:
4070         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4071         bnxt_uninit_resources(bp, false);
4072         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4073 }
4074
4075 void bnxt_dev_reset_and_resume(void *arg)
4076 {
4077         struct bnxt *bp = arg;
4078         int rc;
4079
4080         bnxt_dev_cleanup(bp);
4081
4082         bnxt_wait_for_device_shutdown(bp);
4083
4084         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4085                                bnxt_dev_recover, (void *)bp);
4086         if (rc)
4087                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4088 }
4089
4090 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4091 {
4092         struct bnxt_error_recovery_info *info = bp->recovery_info;
4093         uint32_t reg = info->status_regs[index];
4094         uint32_t type, offset, val = 0;
4095
4096         type = BNXT_FW_STATUS_REG_TYPE(reg);
4097         offset = BNXT_FW_STATUS_REG_OFF(reg);
4098
4099         switch (type) {
4100         case BNXT_FW_STATUS_REG_TYPE_CFG:
4101                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4102                 break;
4103         case BNXT_FW_STATUS_REG_TYPE_GRC:
4104                 offset = info->mapped_status_regs[index];
4105                 /* FALLTHROUGH */
4106         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4107                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4108                                        offset));
4109                 break;
4110         }
4111
4112         return val;
4113 }
4114
4115 static int bnxt_fw_reset_all(struct bnxt *bp)
4116 {
4117         struct bnxt_error_recovery_info *info = bp->recovery_info;
4118         uint32_t i;
4119         int rc = 0;
4120
4121         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4122                 /* Reset through master function driver */
4123                 for (i = 0; i < info->reg_array_cnt; i++)
4124                         bnxt_write_fw_reset_reg(bp, i);
4125                 /* Wait for time specified by FW after triggering reset */
4126                 rte_delay_ms(info->master_func_wait_period_after_reset);
4127         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4128                 /* Reset with the help of Kong processor */
4129                 rc = bnxt_hwrm_fw_reset(bp);
4130                 if (rc)
4131                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4132         }
4133
4134         return rc;
4135 }
4136
4137 static void bnxt_fw_reset_cb(void *arg)
4138 {
4139         struct bnxt *bp = arg;
4140         struct bnxt_error_recovery_info *info = bp->recovery_info;
4141         int rc = 0;
4142
4143         /* Only Master function can do FW reset */
4144         if (bnxt_is_master_func(bp) &&
4145             bnxt_is_recovery_enabled(bp)) {
4146                 rc = bnxt_fw_reset_all(bp);
4147                 if (rc) {
4148                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4149                         return;
4150                 }
4151         }
4152
4153         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4154          * EXCEPTION_FATAL_ASYNC event to all the functions
4155          * (including MASTER FUNC). After receiving this Async, all the active
4156          * drivers should treat this case as FW initiated recovery
4157          */
4158         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4159                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4160                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4161
4162                 /* To recover from error */
4163                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4164                                   (void *)bp);
4165         }
4166 }
4167
4168 /* Driver should poll FW heartbeat, reset_counter with the frequency
4169  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4170  * When the driver detects heartbeat stop or change in reset_counter,
4171  * it has to trigger a reset to recover from the error condition.
4172  * A “master PF” is the function who will have the privilege to
4173  * initiate the chimp reset. The master PF will be elected by the
4174  * firmware and will be notified through async message.
4175  */
4176 static void bnxt_check_fw_health(void *arg)
4177 {
4178         struct bnxt *bp = arg;
4179         struct bnxt_error_recovery_info *info = bp->recovery_info;
4180         uint32_t val = 0, wait_msec;
4181
4182         if (!info || !bnxt_is_recovery_enabled(bp) ||
4183             is_bnxt_in_error(bp))
4184                 return;
4185
4186         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4187         if (val == info->last_heart_beat)
4188                 goto reset;
4189
4190         info->last_heart_beat = val;
4191
4192         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4193         if (val != info->last_reset_counter)
4194                 goto reset;
4195
4196         info->last_reset_counter = val;
4197
4198         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4199                           bnxt_check_fw_health, (void *)bp);
4200
4201         return;
4202 reset:
4203         /* Stop DMA to/from device */
4204         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4205         bp->flags |= BNXT_FLAG_FW_RESET;
4206
4207         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4208
4209         if (bnxt_is_master_func(bp))
4210                 wait_msec = info->master_func_wait_period;
4211         else
4212                 wait_msec = info->normal_func_wait_period;
4213
4214         rte_eal_alarm_set(US_PER_MS * wait_msec,
4215                           bnxt_fw_reset_cb, (void *)bp);
4216 }
4217
4218 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4219 {
4220         uint32_t polling_freq;
4221
4222         if (!bnxt_is_recovery_enabled(bp))
4223                 return;
4224
4225         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4226                 return;
4227
4228         polling_freq = bp->recovery_info->driver_polling_freq;
4229
4230         rte_eal_alarm_set(US_PER_MS * polling_freq,
4231                           bnxt_check_fw_health, (void *)bp);
4232         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4233 }
4234
4235 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4236 {
4237         if (!bnxt_is_recovery_enabled(bp))
4238                 return;
4239
4240         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4241         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4242 }
4243
4244 static bool bnxt_vf_pciid(uint16_t device_id)
4245 {
4246         switch (device_id) {
4247         case BROADCOM_DEV_ID_57304_VF:
4248         case BROADCOM_DEV_ID_57406_VF:
4249         case BROADCOM_DEV_ID_5731X_VF:
4250         case BROADCOM_DEV_ID_5741X_VF:
4251         case BROADCOM_DEV_ID_57414_VF:
4252         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4253         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4254         case BROADCOM_DEV_ID_58802_VF:
4255         case BROADCOM_DEV_ID_57500_VF1:
4256         case BROADCOM_DEV_ID_57500_VF2:
4257                 /* FALLTHROUGH */
4258                 return true;
4259         default:
4260                 return false;
4261         }
4262 }
4263
4264 static bool bnxt_thor_device(uint16_t device_id)
4265 {
4266         switch (device_id) {
4267         case BROADCOM_DEV_ID_57508:
4268         case BROADCOM_DEV_ID_57504:
4269         case BROADCOM_DEV_ID_57502:
4270         case BROADCOM_DEV_ID_57508_MF1:
4271         case BROADCOM_DEV_ID_57504_MF1:
4272         case BROADCOM_DEV_ID_57502_MF1:
4273         case BROADCOM_DEV_ID_57508_MF2:
4274         case BROADCOM_DEV_ID_57504_MF2:
4275         case BROADCOM_DEV_ID_57502_MF2:
4276         case BROADCOM_DEV_ID_57500_VF1:
4277         case BROADCOM_DEV_ID_57500_VF2:
4278                 /* FALLTHROUGH */
4279                 return true;
4280         default:
4281                 return false;
4282         }
4283 }
4284
4285 bool bnxt_stratus_device(struct bnxt *bp)
4286 {
4287         uint16_t device_id = bp->pdev->id.device_id;
4288
4289         switch (device_id) {
4290         case BROADCOM_DEV_ID_STRATUS_NIC:
4291         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4292         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4293                 /* FALLTHROUGH */
4294                 return true;
4295         default:
4296                 return false;
4297         }
4298 }
4299
4300 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4301 {
4302         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4303         struct bnxt *bp = eth_dev->data->dev_private;
4304
4305         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4306         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4307         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4308         if (!bp->bar0 || !bp->doorbell_base) {
4309                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4310                 return -ENODEV;
4311         }
4312
4313         bp->eth_dev = eth_dev;
4314         bp->pdev = pci_dev;
4315
4316         return 0;
4317 }
4318
4319 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4320                                   struct bnxt_ctx_pg_info *ctx_pg,
4321                                   uint32_t mem_size,
4322                                   const char *suffix,
4323                                   uint16_t idx)
4324 {
4325         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4326         const struct rte_memzone *mz = NULL;
4327         char mz_name[RTE_MEMZONE_NAMESIZE];
4328         rte_iova_t mz_phys_addr;
4329         uint64_t valid_bits = 0;
4330         uint32_t sz;
4331         int i;
4332
4333         if (!mem_size)
4334                 return 0;
4335
4336         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4337                          BNXT_PAGE_SIZE;
4338         rmem->page_size = BNXT_PAGE_SIZE;
4339         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4340         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4341         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4342
4343         valid_bits = PTU_PTE_VALID;
4344
4345         if (rmem->nr_pages > 1) {
4346                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4347                          "bnxt_ctx_pg_tbl%s_%x_%d",
4348                          suffix, idx, bp->eth_dev->data->port_id);
4349                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4350                 mz = rte_memzone_lookup(mz_name);
4351                 if (!mz) {
4352                         mz = rte_memzone_reserve_aligned(mz_name,
4353                                                 rmem->nr_pages * 8,
4354                                                 SOCKET_ID_ANY,
4355                                                 RTE_MEMZONE_2MB |
4356                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4357                                                 RTE_MEMZONE_IOVA_CONTIG,
4358                                                 BNXT_PAGE_SIZE);
4359                         if (mz == NULL)
4360                                 return -ENOMEM;
4361                 }
4362
4363                 memset(mz->addr, 0, mz->len);
4364                 mz_phys_addr = mz->iova;
4365
4366                 rmem->pg_tbl = mz->addr;
4367                 rmem->pg_tbl_map = mz_phys_addr;
4368                 rmem->pg_tbl_mz = mz;
4369         }
4370
4371         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4372                  suffix, idx, bp->eth_dev->data->port_id);
4373         mz = rte_memzone_lookup(mz_name);
4374         if (!mz) {
4375                 mz = rte_memzone_reserve_aligned(mz_name,
4376                                                  mem_size,
4377                                                  SOCKET_ID_ANY,
4378                                                  RTE_MEMZONE_1GB |
4379                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4380                                                  RTE_MEMZONE_IOVA_CONTIG,
4381                                                  BNXT_PAGE_SIZE);
4382                 if (mz == NULL)
4383                         return -ENOMEM;
4384         }
4385
4386         memset(mz->addr, 0, mz->len);
4387         mz_phys_addr = mz->iova;
4388
4389         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4390                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4391                 rmem->dma_arr[i] = mz_phys_addr + sz;
4392
4393                 if (rmem->nr_pages > 1) {
4394                         if (i == rmem->nr_pages - 2 &&
4395                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4396                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4397                         else if (i == rmem->nr_pages - 1 &&
4398                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4399                                 valid_bits |= PTU_PTE_LAST;
4400
4401                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4402                                                            valid_bits);
4403                 }
4404         }
4405
4406         rmem->mz = mz;
4407         if (rmem->vmem_size)
4408                 rmem->vmem = (void **)mz->addr;
4409         rmem->dma_arr[0] = mz_phys_addr;
4410         return 0;
4411 }
4412
4413 static void bnxt_free_ctx_mem(struct bnxt *bp)
4414 {
4415         int i;
4416
4417         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4418                 return;
4419
4420         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4421         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4422         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4423         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4424         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4425         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4426         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4427         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4428         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4429         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4430         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4431
4432         for (i = 0; i < BNXT_MAX_Q; i++) {
4433                 if (bp->ctx->tqm_mem[i])
4434                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4435         }
4436
4437         rte_free(bp->ctx);
4438         bp->ctx = NULL;
4439 }
4440
4441 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4442
4443 #define min_t(type, x, y) ({                    \
4444         type __min1 = (x);                      \
4445         type __min2 = (y);                      \
4446         __min1 < __min2 ? __min1 : __min2; })
4447
4448 #define max_t(type, x, y) ({                    \
4449         type __max1 = (x);                      \
4450         type __max2 = (y);                      \
4451         __max1 > __max2 ? __max1 : __max2; })
4452
4453 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4454
4455 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4456 {
4457         struct bnxt_ctx_pg_info *ctx_pg;
4458         struct bnxt_ctx_mem_info *ctx;
4459         uint32_t mem_size, ena, entries;
4460         int i, rc;
4461
4462         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4463         if (rc) {
4464                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4465                 return rc;
4466         }
4467         ctx = bp->ctx;
4468         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4469                 return 0;
4470
4471         ctx_pg = &ctx->qp_mem;
4472         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4473         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4474         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4475         if (rc)
4476                 return rc;
4477
4478         ctx_pg = &ctx->srq_mem;
4479         ctx_pg->entries = ctx->srq_max_l2_entries;
4480         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4481         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4482         if (rc)
4483                 return rc;
4484
4485         ctx_pg = &ctx->cq_mem;
4486         ctx_pg->entries = ctx->cq_max_l2_entries;
4487         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4488         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4489         if (rc)
4490                 return rc;
4491
4492         ctx_pg = &ctx->vnic_mem;
4493         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4494                 ctx->vnic_max_ring_table_entries;
4495         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4496         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4497         if (rc)
4498                 return rc;
4499
4500         ctx_pg = &ctx->stat_mem;
4501         ctx_pg->entries = ctx->stat_max_entries;
4502         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4503         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4504         if (rc)
4505                 return rc;
4506
4507         entries = ctx->qp_max_l2_entries +
4508                   ctx->vnic_max_vnic_entries +
4509                   ctx->tqm_min_entries_per_ring;
4510         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4511         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4512                           ctx->tqm_max_entries_per_ring);
4513         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4514                 ctx_pg = ctx->tqm_mem[i];
4515                 /* use min tqm entries for now. */
4516                 ctx_pg->entries = entries;
4517                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4518                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4519                 if (rc)
4520                         return rc;
4521                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4522         }
4523
4524         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4525         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4526         if (rc)
4527                 PMD_DRV_LOG(ERR,
4528                             "Failed to configure context mem: rc = %d\n", rc);
4529         else
4530                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4531
4532         return rc;
4533 }
4534
4535 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4536 {
4537         struct rte_pci_device *pci_dev = bp->pdev;
4538         char mz_name[RTE_MEMZONE_NAMESIZE];
4539         const struct rte_memzone *mz = NULL;
4540         uint32_t total_alloc_len;
4541         rte_iova_t mz_phys_addr;
4542
4543         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4544                 return 0;
4545
4546         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4547                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4548                  pci_dev->addr.bus, pci_dev->addr.devid,
4549                  pci_dev->addr.function, "rx_port_stats");
4550         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4551         mz = rte_memzone_lookup(mz_name);
4552         total_alloc_len =
4553                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4554                                        sizeof(struct rx_port_stats_ext) + 512);
4555         if (!mz) {
4556                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4557                                          SOCKET_ID_ANY,
4558                                          RTE_MEMZONE_2MB |
4559                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4560                                          RTE_MEMZONE_IOVA_CONTIG);
4561                 if (mz == NULL)
4562                         return -ENOMEM;
4563         }
4564         memset(mz->addr, 0, mz->len);
4565         mz_phys_addr = mz->iova;
4566
4567         bp->rx_mem_zone = (const void *)mz;
4568         bp->hw_rx_port_stats = mz->addr;
4569         bp->hw_rx_port_stats_map = mz_phys_addr;
4570
4571         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4572                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4573                  pci_dev->addr.bus, pci_dev->addr.devid,
4574                  pci_dev->addr.function, "tx_port_stats");
4575         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4576         mz = rte_memzone_lookup(mz_name);
4577         total_alloc_len =
4578                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4579                                        sizeof(struct tx_port_stats_ext) + 512);
4580         if (!mz) {
4581                 mz = rte_memzone_reserve(mz_name,
4582                                          total_alloc_len,
4583                                          SOCKET_ID_ANY,
4584                                          RTE_MEMZONE_2MB |
4585                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4586                                          RTE_MEMZONE_IOVA_CONTIG);
4587                 if (mz == NULL)
4588                         return -ENOMEM;
4589         }
4590         memset(mz->addr, 0, mz->len);
4591         mz_phys_addr = mz->iova;
4592
4593         bp->tx_mem_zone = (const void *)mz;
4594         bp->hw_tx_port_stats = mz->addr;
4595         bp->hw_tx_port_stats_map = mz_phys_addr;
4596         bp->flags |= BNXT_FLAG_PORT_STATS;
4597
4598         /* Display extended statistics if FW supports it */
4599         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4600             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4601             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4602                 return 0;
4603
4604         bp->hw_rx_port_stats_ext = (void *)
4605                 ((uint8_t *)bp->hw_rx_port_stats +
4606                  sizeof(struct rx_port_stats));
4607         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4608                 sizeof(struct rx_port_stats);
4609         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4610
4611         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4612             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4613                 bp->hw_tx_port_stats_ext = (void *)
4614                         ((uint8_t *)bp->hw_tx_port_stats +
4615                          sizeof(struct tx_port_stats));
4616                 bp->hw_tx_port_stats_ext_map =
4617                         bp->hw_tx_port_stats_map +
4618                         sizeof(struct tx_port_stats);
4619                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4620         }
4621
4622         return 0;
4623 }
4624
4625 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4626 {
4627         struct bnxt *bp = eth_dev->data->dev_private;
4628         int rc = 0;
4629
4630         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4631                                                RTE_ETHER_ADDR_LEN *
4632                                                bp->max_l2_ctx,
4633                                                0);
4634         if (eth_dev->data->mac_addrs == NULL) {
4635                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4636                 return -ENOMEM;
4637         }
4638
4639         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4640                 if (BNXT_PF(bp))
4641                         return -EINVAL;
4642
4643                 /* Generate a random MAC address, if none was assigned by PF */
4644                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4645                 bnxt_eth_hw_addr_random(bp->mac_addr);
4646                 PMD_DRV_LOG(INFO,
4647                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4648                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4649                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4650
4651                 rc = bnxt_hwrm_set_mac(bp);
4652                 if (!rc)
4653                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4654                                RTE_ETHER_ADDR_LEN);
4655                 return rc;
4656         }
4657
4658         /* Copy the permanent MAC from the FUNC_QCAPS response */
4659         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4660         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4661
4662         return rc;
4663 }
4664
4665 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4666 {
4667         int rc = 0;
4668
4669         /* MAC is already configured in FW */
4670         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4671                 return 0;
4672
4673         /* Restore the old MAC configured */
4674         rc = bnxt_hwrm_set_mac(bp);
4675         if (rc)
4676                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4677
4678         return rc;
4679 }
4680
4681 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4682 {
4683         if (!BNXT_PF(bp))
4684                 return;
4685
4686 #define ALLOW_FUNC(x)   \
4687         { \
4688                 uint32_t arg = (x); \
4689                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4690                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4691         }
4692
4693         /* Forward all requests if firmware is new enough */
4694         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4695              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4696             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4697                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4698         } else {
4699                 PMD_DRV_LOG(WARNING,
4700                             "Firmware too old for VF mailbox functionality\n");
4701                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4702         }
4703
4704         /*
4705          * The following are used for driver cleanup. If we disallow these,
4706          * VF drivers can't clean up cleanly.
4707          */
4708         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4709         ALLOW_FUNC(HWRM_VNIC_FREE);
4710         ALLOW_FUNC(HWRM_RING_FREE);
4711         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4712         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4713         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4714         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4715         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4716         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4717 }
4718
4719 uint16_t
4720 bnxt_get_svif(uint16_t port_id, bool func_svif)
4721 {
4722         struct rte_eth_dev *eth_dev;
4723         struct bnxt *bp;
4724
4725         eth_dev = &rte_eth_devices[port_id];
4726         bp = eth_dev->data->dev_private;
4727
4728         return func_svif ? bp->func_svif : bp->port_svif;
4729 }
4730
4731 uint16_t
4732 bnxt_get_vnic_id(uint16_t port)
4733 {
4734         struct rte_eth_dev *eth_dev;
4735         struct bnxt_vnic_info *vnic;
4736         struct bnxt *bp;
4737
4738         eth_dev = &rte_eth_devices[port];
4739         bp = eth_dev->data->dev_private;
4740
4741         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4742
4743         return vnic->fw_vnic_id;
4744 }
4745
4746 static int bnxt_init_fw(struct bnxt *bp)
4747 {
4748         uint16_t mtu;
4749         int rc = 0;
4750
4751         bp->fw_cap = 0;
4752
4753         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4754         if (rc)
4755                 return rc;
4756
4757         rc = bnxt_hwrm_func_reset(bp);
4758         if (rc)
4759                 return -EIO;
4760
4761         rc = bnxt_hwrm_vnic_qcaps(bp);
4762         if (rc)
4763                 return rc;
4764
4765         rc = bnxt_hwrm_queue_qportcfg(bp);
4766         if (rc)
4767                 return rc;
4768
4769         /* Get the MAX capabilities for this function.
4770          * This function also allocates context memory for TQM rings and
4771          * informs the firmware about this allocated backing store memory.
4772          */
4773         rc = bnxt_hwrm_func_qcaps(bp);
4774         if (rc)
4775                 return rc;
4776
4777         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4778         if (rc)
4779                 return rc;
4780
4781         bnxt_hwrm_port_mac_qcfg(bp);
4782
4783         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4784         if (rc)
4785                 return rc;
4786
4787         /* Get the adapter error recovery support info */
4788         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4789         if (rc)
4790                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4791
4792         bnxt_hwrm_port_led_qcaps(bp);
4793
4794         return 0;
4795 }
4796
4797 static int
4798 bnxt_init_locks(struct bnxt *bp)
4799 {
4800         int err;
4801
4802         err = pthread_mutex_init(&bp->flow_lock, NULL);
4803         if (err) {
4804                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4805                 return err;
4806         }
4807
4808         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4809         if (err)
4810                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4811         return err;
4812 }
4813
4814 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4815 {
4816         int rc;
4817
4818         rc = bnxt_init_fw(bp);
4819         if (rc)
4820                 return rc;
4821
4822         if (!reconfig_dev) {
4823                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4824                 if (rc)
4825                         return rc;
4826         } else {
4827                 rc = bnxt_restore_dflt_mac(bp);
4828                 if (rc)
4829                         return rc;
4830         }
4831
4832         bnxt_config_vf_req_fwd(bp);
4833
4834         rc = bnxt_hwrm_func_driver_register(bp);
4835         if (rc) {
4836                 PMD_DRV_LOG(ERR, "Failed to register driver");
4837                 return -EBUSY;
4838         }
4839
4840         if (BNXT_PF(bp)) {
4841                 if (bp->pdev->max_vfs) {
4842                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4843                         if (rc) {
4844                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4845                                 return rc;
4846                         }
4847                 } else {
4848                         rc = bnxt_hwrm_allocate_pf_only(bp);
4849                         if (rc) {
4850                                 PMD_DRV_LOG(ERR,
4851                                             "Failed to allocate PF resources");
4852                                 return rc;
4853                         }
4854                 }
4855         }
4856
4857         rc = bnxt_alloc_mem(bp, reconfig_dev);
4858         if (rc)
4859                 return rc;
4860
4861         rc = bnxt_setup_int(bp);
4862         if (rc)
4863                 return rc;
4864
4865         rc = bnxt_request_int(bp);
4866         if (rc)
4867                 return rc;
4868
4869         rc = bnxt_init_locks(bp);
4870         if (rc)
4871                 return rc;
4872
4873         return 0;
4874 }
4875
4876 static int
4877 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4878                           const char *value, void *opaque_arg)
4879 {
4880         struct bnxt *bp = opaque_arg;
4881         unsigned long truflow;
4882         char *end = NULL;
4883
4884         if (!value || !opaque_arg) {
4885                 PMD_DRV_LOG(ERR,
4886                             "Invalid parameter passed to truflow devargs.\n");
4887                 return -EINVAL;
4888         }
4889
4890         truflow = strtoul(value, &end, 10);
4891         if (end == NULL || *end != '\0' ||
4892             (truflow == ULONG_MAX && errno == ERANGE)) {
4893                 PMD_DRV_LOG(ERR,
4894                             "Invalid parameter passed to truflow devargs.\n");
4895                 return -EINVAL;
4896         }
4897
4898         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4899                 PMD_DRV_LOG(ERR,
4900                             "Invalid value passed to truflow devargs.\n");
4901                 return -EINVAL;
4902         }
4903
4904         bp->truflow = truflow;
4905         if (bp->truflow)
4906                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4907
4908         return 0;
4909 }
4910
4911 static void
4912 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
4913 {
4914         struct rte_kvargs *kvlist;
4915
4916         if (devargs == NULL)
4917                 return;
4918
4919         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
4920         if (kvlist == NULL)
4921                 return;
4922
4923         /*
4924          * Handler for "truflow" devarg.
4925          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
4926          */
4927         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
4928                            bnxt_parse_devarg_truflow, bp);
4929
4930         rte_kvargs_free(kvlist);
4931 }
4932
4933 static int
4934 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4935 {
4936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4937         static int version_printed;
4938         struct bnxt *bp;
4939         int rc;
4940
4941         if (version_printed++ == 0)
4942                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4943
4944         eth_dev->dev_ops = &bnxt_dev_ops;
4945         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4946         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4947
4948         /*
4949          * For secondary processes, we don't initialise any further
4950          * as primary has already done this work.
4951          */
4952         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4953                 return 0;
4954
4955         rte_eth_copy_pci_info(eth_dev, pci_dev);
4956
4957         bp = eth_dev->data->dev_private;
4958
4959         /* Parse dev arguments passed on when starting the DPDK application. */
4960         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
4961
4962         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4963
4964         if (bnxt_vf_pciid(pci_dev->id.device_id))
4965                 bp->flags |= BNXT_FLAG_VF;
4966
4967         if (bnxt_thor_device(pci_dev->id.device_id))
4968                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4969
4970         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4971             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4972             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4973             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4974                 bp->flags |= BNXT_FLAG_STINGRAY;
4975
4976         rc = bnxt_init_board(eth_dev);
4977         if (rc) {
4978                 PMD_DRV_LOG(ERR,
4979                             "Failed to initialize board rc: %x\n", rc);
4980                 return rc;
4981         }
4982
4983         rc = bnxt_alloc_hwrm_resources(bp);
4984         if (rc) {
4985                 PMD_DRV_LOG(ERR,
4986                             "Failed to allocate hwrm resource rc: %x\n", rc);
4987                 goto error_free;
4988         }
4989         rc = bnxt_init_resources(bp, false);
4990         if (rc)
4991                 goto error_free;
4992
4993         rc = bnxt_alloc_stats_mem(bp);
4994         if (rc)
4995                 goto error_free;
4996
4997         /* Pass the information to the rte_eth_dev_close() that it should also
4998          * release the private port resources.
4999          */
5000         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5001
5002         PMD_DRV_LOG(INFO,
5003                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5004                     pci_dev->mem_resource[0].phys_addr,
5005                     pci_dev->mem_resource[0].addr);
5006
5007         return 0;
5008
5009 error_free:
5010         bnxt_dev_uninit(eth_dev);
5011         return rc;
5012 }
5013
5014 static void
5015 bnxt_uninit_locks(struct bnxt *bp)
5016 {
5017         pthread_mutex_destroy(&bp->flow_lock);
5018         pthread_mutex_destroy(&bp->def_cp_lock);
5019 }
5020
5021 static int
5022 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5023 {
5024         int rc;
5025
5026         bnxt_free_int(bp);
5027         bnxt_free_mem(bp, reconfig_dev);
5028         bnxt_hwrm_func_buf_unrgtr(bp);
5029         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5030         bp->flags &= ~BNXT_FLAG_REGISTERED;
5031         bnxt_free_ctx_mem(bp);
5032         if (!reconfig_dev) {
5033                 bnxt_free_hwrm_resources(bp);
5034
5035                 if (bp->recovery_info != NULL) {
5036                         rte_free(bp->recovery_info);
5037                         bp->recovery_info = NULL;
5038                 }
5039         }
5040
5041         bnxt_uninit_locks(bp);
5042         rte_free(bp->ptp_cfg);
5043         bp->ptp_cfg = NULL;
5044         return rc;
5045 }
5046
5047 static int
5048 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5049 {
5050         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5051                 return -EPERM;
5052
5053         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5054
5055         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5056                 bnxt_dev_close_op(eth_dev);
5057
5058         return 0;
5059 }
5060
5061 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5062         struct rte_pci_device *pci_dev)
5063 {
5064         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5065                 bnxt_dev_init);
5066 }
5067
5068 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5069 {
5070         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5071                 return rte_eth_dev_pci_generic_remove(pci_dev,
5072                                 bnxt_dev_uninit);
5073         else
5074                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5075 }
5076
5077 static struct rte_pci_driver bnxt_rte_pmd = {
5078         .id_table = bnxt_pci_id_map,
5079         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5080         .probe = bnxt_pci_probe,
5081         .remove = bnxt_pci_remove,
5082 };
5083
5084 static bool
5085 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5086 {
5087         if (strcmp(dev->device->driver->name, drv->driver.name))
5088                 return false;
5089
5090         return true;
5091 }
5092
5093 bool is_bnxt_supported(struct rte_eth_dev *dev)
5094 {
5095         return is_device_supported(dev, &bnxt_rte_pmd);
5096 }
5097
5098 RTE_INIT(bnxt_init_log)
5099 {
5100         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5101         if (bnxt_logtype_driver >= 0)
5102                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5103 }
5104
5105 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5106 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5107 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");