drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { .vendor_id = 0, /* sentinel */ },
  87 };
  88
  89 #define BNXT_ETH_RSS_SUPPORT (  \
  90         ETH_RSS_IPV4 |          \
  91         ETH_RSS_NONFRAG_IPV4_TCP |      \
  92         ETH_RSS_NONFRAG_IPV4_UDP |      \
  93         ETH_RSS_IPV6 |          \
  94         ETH_RSS_NONFRAG_IPV6_TCP |      \
  95         ETH_RSS_NONFRAG_IPV6_UDP)
  96
  97 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
  98                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
  99                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 100                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 101                                      DEV_TX_OFFLOAD_TCP_TSO | \
 102                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 103                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 104                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 105                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 106                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 107                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 108                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 109
 110 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 111                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 112                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 113                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 114                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 115                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 116                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 117                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 118                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 119                                      DEV_RX_OFFLOAD_TCP_LRO | \
 120                                      DEV_RX_OFFLOAD_SCATTER)
 121
 122 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 123 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 124 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 125 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 126 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 127 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 128 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 129
 130 int is_bnxt_in_error(struct bnxt *bp)
 131 {
 132         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 133                 return -EIO;
 134         if (bp->flags & BNXT_FLAG_FW_RESET)
 135                 return -EBUSY;
 136
 137         return 0;
 138 }
 139
 140 /***********************/
 141
 142 /*
 143  * High level utility functions
 144  */
 145
 146 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 147 {
 148         if (!BNXT_CHIP_THOR(bp))
 149                 return 1;
 150
 151         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 152                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 153                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 154 }
 155
 156 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 157 {
 158         if (!BNXT_CHIP_THOR(bp))
 159                 return HW_HASH_INDEX_SIZE;
 160
 161         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 162 }
 163
 164 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 165 {
 166         bnxt_free_filter_mem(bp);
 167         bnxt_free_vnic_attributes(bp);
 168         bnxt_free_vnic_mem(bp);
 169
 170         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 171          * If the number of rings change across fw update,
 172          * we don't have much choice except to warn the user.
 173          */
 174         if (!reconfig) {
 175                 bnxt_free_stats(bp);
 176                 bnxt_free_tx_rings(bp);
 177                 bnxt_free_rx_rings(bp);
 178         }
 179         bnxt_free_async_cp_ring(bp);
 180         bnxt_free_rxtx_nq_ring(bp);
 181 }
 182
 183 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 184 {
 185         int rc;
 186
 187         rc = bnxt_alloc_ring_grps(bp);
 188         if (rc)
 189                 goto alloc_mem_err;
 190
 191         rc = bnxt_alloc_async_ring_struct(bp);
 192         if (rc)
 193                 goto alloc_mem_err;
 194
 195         rc = bnxt_alloc_vnic_mem(bp);
 196         if (rc)
 197                 goto alloc_mem_err;
 198
 199         rc = bnxt_alloc_vnic_attributes(bp);
 200         if (rc)
 201                 goto alloc_mem_err;
 202
 203         rc = bnxt_alloc_filter_mem(bp);
 204         if (rc)
 205                 goto alloc_mem_err;
 206
 207         rc = bnxt_alloc_async_cp_ring(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_rxtx_nq_ring(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         return 0;
 216
 217 alloc_mem_err:
 218         bnxt_free_mem(bp, reconfig);
 219         return rc;
 220 }
 221
 222 static int bnxt_init_chip(struct bnxt *bp)
 223 {
 224         struct bnxt_rx_queue *rxq;
 225         struct rte_eth_link new;
 226         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 227         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 229         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 230         uint32_t intr_vector = 0;
 231         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 232         uint32_t vec = BNXT_MISC_VEC_ID;
 233         unsigned int i, j;
 234         int rc;
 235
 236         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 237                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 238                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 239                 bp->flags |= BNXT_FLAG_JUMBO;
 240         } else {
 241                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 243                 bp->flags &= ~BNXT_FLAG_JUMBO;
 244         }
 245
 246         /* THOR does not support ring groups.
 247          * But we will use the array to save RSS context IDs.
 248          */
 249         if (BNXT_CHIP_THOR(bp))
 250                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 251
 252         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 253         if (rc) {
 254                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 255                 goto err_out;
 256         }
 257
 258         rc = bnxt_alloc_hwrm_rings(bp);
 259         if (rc) {
 260                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 261                 goto err_out;
 262         }
 263
 264         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 265         if (rc) {
 266                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 267                 goto err_out;
 268         }
 269
 270         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 271                 goto skip_cosq_cfg;
 272
 273         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 274                 if (bp->rx_cos_queue[i].id != 0xff) {
 275                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 276
 277                         if (!vnic) {
 278                                 PMD_DRV_LOG(ERR,
 279                                             "Num pools more than FW profile\n");
 280                                 rc = -EINVAL;
 281                                 goto err_out;
 282                         }
 283                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 284                         bp->rx_cosq_cnt++;
 285                 }
 286         }
 287
 288 skip_cosq_cfg:
 289         rc = bnxt_mq_rx_configure(bp);
 290         if (rc) {
 291                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 292                 goto err_out;
 293         }
 294
 295         /* VNIC configuration */
 296         for (i = 0; i < bp->nr_vnics; i++) {
 297                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 298                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 299
 300                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 301                 if (rc)
 302                         goto err_out;
 303
 304                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 305                             i, vnic, vnic->fw_grp_ids);
 306
 307                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 308                 if (rc) {
 309                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 310                                 i, rc);
 311                         goto err_out;
 312                 }
 313
 314                 /* Alloc RSS context only if RSS mode is enabled */
 315                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 316                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 317
 318                         rc = 0;
 319                         for (j = 0; j < nr_ctxs; j++) {
 320                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 321                                 if (rc)
 322                                         break;
 323                         }
 324                         if (rc) {
 325                                 PMD_DRV_LOG(ERR,
 326                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 327                                   i, j, rc);
 328                                 goto err_out;
 329                         }
 330                         vnic->num_lb_ctxts = nr_ctxs;
 331                 }
 332
 333                 /*
 334                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 335                  * setting is not available at this time, it will not be
 336                  * configured correctly in the CFA.
 337                  */
 338                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 339                         vnic->vlan_strip = true;
 340                 else
 341                         vnic->vlan_strip = false;
 342
 343                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 344                 if (rc) {
 345                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 346                                 i, rc);
 347                         goto err_out;
 348                 }
 349
 350                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 351                 if (rc) {
 352                         PMD_DRV_LOG(ERR,
 353                                 "HWRM vnic %d filter failure rc: %x\n",
 354                                 i, rc);
 355                         goto err_out;
 356                 }
 357
 358                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 359                         rxq = bp->eth_dev->data->rx_queues[j];
 360
 361                         PMD_DRV_LOG(DEBUG,
 362                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 363                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 364
 365                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 366                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 367                 }
 368
 369                 rc = bnxt_vnic_rss_configure(bp, vnic);
 370                 if (rc) {
 371                         PMD_DRV_LOG(ERR,
 372                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 373                         goto err_out;
 374                 }
 375
 376                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 377
 378                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 379                     DEV_RX_OFFLOAD_TCP_LRO)
 380                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 381                 else
 382                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 383         }
 384         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 385         if (rc) {
 386                 PMD_DRV_LOG(ERR,
 387                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 388                 goto err_out;
 389         }
 390
 391         /* check and configure queue intr-vector mapping */
 392         if ((rte_intr_cap_multiple(intr_handle) ||
 393              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 394             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 395                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 396                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 397                 if (intr_vector > bp->rx_cp_nr_rings) {
 398                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 399                                         bp->rx_cp_nr_rings);
 400                         return -ENOTSUP;
 401                 }
 402                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 403                 if (rc)
 404                         return rc;
 405         }
 406
 407         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 408                 intr_handle->intr_vec =
 409                         rte_zmalloc("intr_vec",
 410                                     bp->eth_dev->data->nb_rx_queues *
 411                                     sizeof(int), 0);
 412                 if (intr_handle->intr_vec == NULL) {
 413                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 414                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 415                         rc = -ENOMEM;
 416                         goto err_disable;
 417                 }
 418                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 419                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 420                          intr_handle->intr_vec, intr_handle->nb_efd,
 421                         intr_handle->max_intr);
 422                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 423                      queue_id++) {
 424                         intr_handle->intr_vec[queue_id] =
 425                                                         vec + BNXT_RX_VEC_START;
 426                         if (vec < base + intr_handle->nb_efd - 1)
 427                                 vec++;
 428                 }
 429         }
 430
 431         /* enable uio/vfio intr/eventfd mapping */
 432         rc = rte_intr_enable(intr_handle);
 433         if (rc)
 434                 goto err_free;
 435
 436         rc = bnxt_get_hwrm_link_config(bp, &new);
 437         if (rc) {
 438                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 439                 goto err_free;
 440         }
 441
 442         if (!bp->link_info.link_up) {
 443                 rc = bnxt_set_hwrm_link_config(bp, true);
 444                 if (rc) {
 445                         PMD_DRV_LOG(ERR,
 446                                 "HWRM link config failure rc: %x\n", rc);
 447                         goto err_free;
 448                 }
 449         }
 450         bnxt_print_link_info(bp->eth_dev);
 451
 452         return 0;
 453
 454 err_free:
 455         rte_free(intr_handle->intr_vec);
 456 err_disable:
 457         rte_intr_efd_disable(intr_handle);
 458 err_out:
 459         /* Some of the error status returned by FW may not be from errno.h */
 460         if (rc > 0)
 461                 rc = -EIO;
 462
 463         return rc;
 464 }
 465
 466 static int bnxt_shutdown_nic(struct bnxt *bp)
 467 {
 468         bnxt_free_all_hwrm_resources(bp);
 469         bnxt_free_all_filters(bp);
 470         bnxt_free_all_vnics(bp);
 471         return 0;
 472 }
 473
 474 static int bnxt_init_nic(struct bnxt *bp)
 475 {
 476         int rc;
 477
 478         if (BNXT_HAS_RING_GRPS(bp)) {
 479                 rc = bnxt_init_ring_grps(bp);
 480                 if (rc)
 481                         return rc;
 482         }
 483
 484         bnxt_init_vnics(bp);
 485         bnxt_init_filters(bp);
 486
 487         return 0;
 488 }
 489
 490 /*
 491  * Device configuration and status function
 492  */
 493
 494 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 495                                 struct rte_eth_dev_info *dev_info)
 496 {
 497         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 498         struct bnxt *bp = eth_dev->data->dev_private;
 499         uint16_t max_vnics, i, j, vpool, vrxq;
 500         unsigned int max_rx_rings;
 501         int rc;
 502
 503         rc = is_bnxt_in_error(bp);
 504         if (rc)
 505                 return rc;
 506
 507         /* MAC Specifics */
 508         dev_info->max_mac_addrs = bp->max_l2_ctx;
 509         dev_info->max_hash_mac_addrs = 0;
 510
 511         /* PF/VF specifics */
 512         if (BNXT_PF(bp))
 513                 dev_info->max_vfs = pdev->max_vfs;
 514
 515         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 516         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 517         dev_info->max_rx_queues = max_rx_rings;
 518         dev_info->max_tx_queues = max_rx_rings;
 519         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 520         dev_info->hash_key_size = 40;
 521         max_vnics = bp->max_vnics;
 522
 523         /* MTU specifics */
 524         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 525         dev_info->max_mtu = BNXT_MAX_MTU;
 526
 527         /* Fast path specifics */
 528         dev_info->min_rx_bufsize = 1;
 529         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 530
 531         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 532         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 533                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 534         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 535         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 536
 537         /* *INDENT-OFF* */
 538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 539                 .rx_thresh = {
 540                         .pthresh = 8,
 541                         .hthresh = 8,
 542                         .wthresh = 0,
 543                 },
 544                 .rx_free_thresh = 32,
 545                 /* If no descriptors available, pkts are dropped by default */
 546                 .rx_drop_en = 1,
 547         };
 548
 549         dev_info->default_txconf = (struct rte_eth_txconf) {
 550                 .tx_thresh = {
 551                         .pthresh = 32,
 552                         .hthresh = 0,
 553                         .wthresh = 0,
 554                 },
 555                 .tx_free_thresh = 32,
 556                 .tx_rs_thresh = 32,
 557         };
 558         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 559
 560         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 561         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 562         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 563         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 564         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 565
 566         /* *INDENT-ON* */
 567
 568         /*
 569          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 570          *       need further investigation.
 571          */
 572
 573         /* VMDq resources */
 574         vpool = 64; /* ETH_64_POOLS */
 575         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 576         for (i = 0; i < 4; vpool >>= 1, i++) {
 577                 if (max_vnics > vpool) {
 578                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 579                                 if (dev_info->max_rx_queues > vrxq) {
 580                                         if (vpool > vrxq)
 581                                                 vpool = vrxq;
 582                                         goto found;
 583                                 }
 584                         }
 585                         /* Not enough resources to support VMDq */
 586                         break;
 587                 }
 588         }
 589         /* Not enough resources to support VMDq */
 590         vpool = 0;
 591         vrxq = 0;
 592 found:
 593         dev_info->max_vmdq_pools = vpool;
 594         dev_info->vmdq_queue_num = vrxq;
 595
 596         dev_info->vmdq_pool_base = 0;
 597         dev_info->vmdq_queue_base = 0;
 598
 599         return 0;
 600 }
 601
 602 /* Configure the device based on the configuration provided */
 603 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 604 {
 605         struct bnxt *bp = eth_dev->data->dev_private;
 606         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 607         int rc;
 608
 609         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 610         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 611         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 612         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 613
 614         rc = is_bnxt_in_error(bp);
 615         if (rc)
 616                 return rc;
 617
 618         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 619                 rc = bnxt_hwrm_check_vf_rings(bp);
 620                 if (rc) {
 621                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 622                         return -ENOSPC;
 623                 }
 624
 625                 /* If a resource has already been allocated - in this case
 626                  * it is the async completion ring, free it. Reallocate it after
 627                  * resource reservation. This will ensure the resource counts
 628                  * are calculated correctly.
 629                  */
 630
 631                 pthread_mutex_lock(&bp->def_cp_lock);
 632
 633                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 634                         bnxt_disable_int(bp);
 635                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 636                 }
 637
 638                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 639                 if (rc) {
 640                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 641                         pthread_mutex_unlock(&bp->def_cp_lock);
 642                         return -ENOSPC;
 643                 }
 644
 645                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 646                         rc = bnxt_alloc_async_cp_ring(bp);
 647                         if (rc) {
 648                                 pthread_mutex_unlock(&bp->def_cp_lock);
 649                                 return rc;
 650                         }
 651                         bnxt_enable_int(bp);
 652                 }
 653
 654                 pthread_mutex_unlock(&bp->def_cp_lock);
 655         } else {
 656                 /* legacy driver needs to get updated values */
 657                 rc = bnxt_hwrm_func_qcaps(bp);
 658                 if (rc) {
 659                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 660                         return rc;
 661                 }
 662         }
 663
 664         /* Inherit new configurations */
 665         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 666             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 667             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 668                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 669             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 670             bp->max_stat_ctx)
 671                 goto resource_error;
 672
 673         if (BNXT_HAS_RING_GRPS(bp) &&
 674             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 675                 goto resource_error;
 676
 677         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 678             bp->max_vnics < eth_dev->data->nb_rx_queues)
 679                 goto resource_error;
 680
 681         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 682         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 683
 684         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 685                 eth_dev->data->mtu =
 686                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 687                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 688                         BNXT_NUM_VLANS;
 689                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 690         }
 691         return 0;
 692
 693 resource_error:
 694         PMD_DRV_LOG(ERR,
 695                     "Insufficient resources to support requested config\n");
 696         PMD_DRV_LOG(ERR,
 697                     "Num Queues Requested: Tx %d, Rx %d\n",
 698                     eth_dev->data->nb_tx_queues,
 699                     eth_dev->data->nb_rx_queues);
 700         PMD_DRV_LOG(ERR,
 701                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 702                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 703                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 704         return -ENOSPC;
 705 }
 706
 707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 708 {
 709         struct rte_eth_link *link = &eth_dev->data->dev_link;
 710
 711         if (link->link_status)
 712                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 713                         eth_dev->data->port_id,
 714                         (uint32_t)link->link_speed,
 715                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 716                         ("full-duplex") : ("half-duplex\n"));
 717         else
 718                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 719                         eth_dev->data->port_id);
 720 }
 721
 722 /*
 723  * Determine whether the current configuration requires support for scattered
 724  * receive; return 1 if scattered receive is required and 0 if not.
 725  */
 726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 727 {
 728         uint16_t buf_size;
 729         int i;
 730
 731         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 732                 return 1;
 733
 734         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 735                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 736
 737                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 738                                       RTE_PKTMBUF_HEADROOM);
 739                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 740                         return 1;
 741         }
 742         return 0;
 743 }
 744
 745 static eth_rx_burst_t
 746 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 747 {
 748 #ifdef RTE_ARCH_X86
 749 #ifndef RTE_LIBRTE_IEEE1588
 750         /*
 751          * Vector mode receive can be enabled only if scatter rx is not
 752          * in use and rx offloads are limited to VLAN stripping and
 753          * CRC stripping.
 754          */
 755         if (!eth_dev->data->scattered_rx &&
 756             !(eth_dev->data->dev_conf.rxmode.offloads &
 757               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 758                 DEV_RX_OFFLOAD_KEEP_CRC |
 759                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 760                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_UDP_CKSUM |
 762                 DEV_RX_OFFLOAD_TCP_CKSUM |
 763                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 764                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 765                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 766                             eth_dev->data->port_id);
 767                 return bnxt_recv_pkts_vec;
 768         }
 769         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 770                     eth_dev->data->port_id);
 771         PMD_DRV_LOG(INFO,
 772                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 773                     eth_dev->data->port_id,
 774                     eth_dev->data->scattered_rx,
 775                     eth_dev->data->dev_conf.rxmode.offloads);
 776 #endif
 777 #endif
 778         return bnxt_recv_pkts;
 779 }
 780
 781 static eth_tx_burst_t
 782 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 783 {
 784 #ifdef RTE_ARCH_X86
 785 #ifndef RTE_LIBRTE_IEEE1588
 786         /*
 787          * Vector mode transmit can be enabled only if not using scatter rx
 788          * or tx offloads.
 789          */
 790         if (!eth_dev->data->scattered_rx &&
 791             !eth_dev->data->dev_conf.txmode.offloads) {
 792                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 793                             eth_dev->data->port_id);
 794                 return bnxt_xmit_pkts_vec;
 795         }
 796         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 797                     eth_dev->data->port_id);
 798         PMD_DRV_LOG(INFO,
 799                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 800                     eth_dev->data->port_id,
 801                     eth_dev->data->scattered_rx,
 802                     eth_dev->data->dev_conf.txmode.offloads);
 803 #endif
 804 #endif
 805         return bnxt_xmit_pkts;
 806 }
 807
 808 static int bnxt_handle_if_change_status(struct bnxt *bp)
 809 {
 810         int rc;
 811
 812         /* Since fw has undergone a reset and lost all contexts,
 813          * set fatal flag to not issue hwrm during cleanup
 814          */
 815         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 816         bnxt_uninit_resources(bp, true);
 817
 818         /* clear fatal flag so that re-init happens */
 819         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 820         rc = bnxt_init_resources(bp, true);
 821
 822         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 823
 824         return rc;
 825 }
 826
 827 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 828 {
 829         struct bnxt *bp = eth_dev->data->dev_private;
 830         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 831         int vlan_mask = 0;
 832         int rc;
 833
 834         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 835                 PMD_DRV_LOG(ERR,
 836                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 837                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 838         }
 839
 840         rc = bnxt_hwrm_if_change(bp, 1);
 841         if (!rc) {
 842                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 843                         rc = bnxt_handle_if_change_status(bp);
 844                         if (rc)
 845                                 return rc;
 846                 }
 847         }
 848         bnxt_enable_int(bp);
 849
 850         rc = bnxt_init_chip(bp);
 851         if (rc)
 852                 goto error;
 853
 854         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 855
 856         bnxt_link_update_op(eth_dev, 1);
 857
 858         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 859                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 860         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 861                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 862         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 863         if (rc)
 864                 goto error;
 865
 866         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 867         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 868
 869         bp->flags |= BNXT_FLAG_INIT_DONE;
 870         eth_dev->data->dev_started = 1;
 871         bp->dev_stopped = 0;
 872         bnxt_schedule_fw_health_check(bp);
 873         return 0;
 874
 875 error:
 876         bnxt_hwrm_if_change(bp, 0);
 877         bnxt_shutdown_nic(bp);
 878         bnxt_free_tx_mbufs(bp);
 879         bnxt_free_rx_mbufs(bp);
 880         return rc;
 881 }
 882
 883 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 884 {
 885         struct bnxt *bp = eth_dev->data->dev_private;
 886         int rc = 0;
 887
 888         if (!bp->link_info.link_up)
 889                 rc = bnxt_set_hwrm_link_config(bp, true);
 890         if (!rc)
 891                 eth_dev->data->dev_link.link_status = 1;
 892
 893         bnxt_print_link_info(eth_dev);
 894         return rc;
 895 }
 896
 897 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 898 {
 899         struct bnxt *bp = eth_dev->data->dev_private;
 900
 901         eth_dev->data->dev_link.link_status = 0;
 902         bnxt_set_hwrm_link_config(bp, false);
 903         bp->link_info.link_up = 0;
 904
 905         return 0;
 906 }
 907
 908 /* Unload the driver, release resources */
 909 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 910 {
 911         struct bnxt *bp = eth_dev->data->dev_private;
 912         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 913         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 914
 915         eth_dev->data->dev_started = 0;
 916         /* Prevent crashes when queues are still in use */
 917         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 918         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 919
 920         bnxt_disable_int(bp);
 921
 922         /* disable uio/vfio intr/eventfd mapping */
 923         rte_intr_disable(intr_handle);
 924
 925         bnxt_cancel_fw_health_check(bp);
 926
 927         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 928         if (bp->eth_dev->data->dev_started) {
 929                 /* TBD: STOP HW queues DMA */
 930                 eth_dev->data->dev_link.link_status = 0;
 931         }
 932         bnxt_dev_set_link_down_op(eth_dev);
 933
 934         /* Wait for link to be reset and the async notification to process.
 935          * During reset recovery, there is no need to wait
 936          */
 937         if (!is_bnxt_in_error(bp))
 938                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 939
 940         /* Clean queue intr-vector mapping */
 941         rte_intr_efd_disable(intr_handle);
 942         if (intr_handle->intr_vec != NULL) {
 943                 rte_free(intr_handle->intr_vec);
 944                 intr_handle->intr_vec = NULL;
 945         }
 946
 947         bnxt_hwrm_port_clr_stats(bp);
 948         bnxt_free_tx_mbufs(bp);
 949         bnxt_free_rx_mbufs(bp);
 950         /* Process any remaining notifications in default completion queue */
 951         bnxt_int_handler(eth_dev);
 952         bnxt_shutdown_nic(bp);
 953         bnxt_hwrm_if_change(bp, 0);
 954         bp->dev_stopped = 1;
 955 }
 956
 957 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 958 {
 959         struct bnxt *bp = eth_dev->data->dev_private;
 960
 961         if (bp->dev_stopped == 0)
 962                 bnxt_dev_stop_op(eth_dev);
 963
 964         if (eth_dev->data->mac_addrs != NULL) {
 965                 rte_free(eth_dev->data->mac_addrs);
 966                 eth_dev->data->mac_addrs = NULL;
 967         }
 968         if (bp->grp_info != NULL) {
 969                 rte_free(bp->grp_info);
 970                 bp->grp_info = NULL;
 971         }
 972
 973         bnxt_dev_uninit(eth_dev);
 974 }
 975
 976 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 977                                     uint32_t index)
 978 {
 979         struct bnxt *bp = eth_dev->data->dev_private;
 980         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 981         struct bnxt_vnic_info *vnic;
 982         struct bnxt_filter_info *filter, *temp_filter;
 983         uint32_t i;
 984
 985         if (is_bnxt_in_error(bp))
 986                 return;
 987
 988         /*
 989          * Loop through all VNICs from the specified filter flow pools to
 990          * remove the corresponding MAC addr filter
 991          */
 992         for (i = 0; i < bp->nr_vnics; i++) {
 993                 if (!(pool_mask & (1ULL << i)))
 994                         continue;
 995
 996                 vnic = &bp->vnic_info[i];
 997                 filter = STAILQ_FIRST(&vnic->filter);
 998                 while (filter) {
 999                         temp_filter = STAILQ_NEXT(filter, next);
1000                         if (filter->mac_index == index) {
1001                                 STAILQ_REMOVE(&vnic->filter, filter,
1002                                                 bnxt_filter_info, next);
1003                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1004                                 filter->mac_index = INVALID_MAC_INDEX;
1005                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1006                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1007                                                    filter, next);
1008                         }
1009                         filter = temp_filter;
1010                 }
1011         }
1012 }
1013
1014 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1015                                struct rte_ether_addr *mac_addr, uint32_t index)
1016 {
1017         struct bnxt_filter_info *filter;
1018         int rc = 0;
1019
1020         filter = STAILQ_FIRST(&vnic->filter);
1021         /* During bnxt_mac_addr_add_op, default MAC is
1022          * already programmed, so skip it. But, when
1023          * hw-vlan-filter is turned OFF from ON, default
1024          * MAC filter should be restored
1025          */
1026         if (filter->dflt)
1027                 return 0;
1028
1029         filter = bnxt_alloc_filter(bp);
1030         if (!filter) {
1031                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1032                 return -ENODEV;
1033         }
1034
1035         filter->mac_index = index;
1036         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1037          * if the MAC that's been programmed now is a different one, then,
1038          * copy that addr to filter->l2_addr
1039          */
1040         if (mac_addr)
1041                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1043
1044         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1045         if (!rc) {
1046                 if (filter->mac_index == 0) {
1047                         filter->dflt = true;
1048                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1049                 } else {
1050                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1051                 }
1052         } else {
1053                 filter->mac_index = INVALID_MAC_INDEX;
1054                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1055                 bnxt_free_filter(bp, filter);
1056         }
1057
1058         return rc;
1059 }
1060
1061 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1062                                 struct rte_ether_addr *mac_addr,
1063                                 uint32_t index, uint32_t pool)
1064 {
1065         struct bnxt *bp = eth_dev->data->dev_private;
1066         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1067         struct bnxt_filter_info *filter;
1068         int rc = 0;
1069
1070         rc = is_bnxt_in_error(bp);
1071         if (rc)
1072                 return rc;
1073
1074         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1075                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1076                 return -ENOTSUP;
1077         }
1078
1079         if (!vnic) {
1080                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1081                 return -EINVAL;
1082         }
1083         /* Attach requested MAC address to the new l2_filter */
1084         STAILQ_FOREACH(filter, &vnic->filter, next) {
1085                 if (filter->mac_index == index) {
1086                         PMD_DRV_LOG(ERR,
1087                                 "MAC addr already existed for pool %d\n", pool);
1088                         return 0;
1089                 }
1090         }
1091
1092         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1093
1094         return rc;
1095 }
1096
1097 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1098 {
1099         int rc = 0;
1100         struct bnxt *bp = eth_dev->data->dev_private;
1101         struct rte_eth_link new;
1102         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1103
1104         rc = is_bnxt_in_error(bp);
1105         if (rc)
1106                 return rc;
1107
1108         memset(&new, 0, sizeof(new));
1109         do {
1110                 /* Retrieve link info from hardware */
1111                 rc = bnxt_get_hwrm_link_config(bp, &new);
1112                 if (rc) {
1113                         new.link_speed = ETH_LINK_SPEED_100M;
1114                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1115                         PMD_DRV_LOG(ERR,
1116                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1117                         goto out;
1118                 }
1119
1120                 if (!wait_to_complete || new.link_status)
1121                         break;
1122
1123                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1124         } while (cnt--);
1125
1126 out:
1127         /* Timed out or success */
1128         if (new.link_status != eth_dev->data->dev_link.link_status ||
1129         new.link_speed != eth_dev->data->dev_link.link_speed) {
1130                 rte_eth_linkstatus_set(eth_dev, &new);
1131
1132                 _rte_eth_dev_callback_process(eth_dev,
1133                                               RTE_ETH_EVENT_INTR_LSC,
1134                                               NULL);
1135
1136                 bnxt_print_link_info(eth_dev);
1137         }
1138
1139         return rc;
1140 }
1141
1142 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1143 {
1144         struct bnxt *bp = eth_dev->data->dev_private;
1145         struct bnxt_vnic_info *vnic;
1146         uint32_t old_flags;
1147         int rc;
1148
1149         rc = is_bnxt_in_error(bp);
1150         if (rc)
1151                 return rc;
1152
1153         if (bp->vnic_info == NULL)
1154                 return 0;
1155
1156         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1157
1158         old_flags = vnic->flags;
1159         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1160         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1161         if (rc != 0)
1162                 vnic->flags = old_flags;
1163
1164         return rc;
1165 }
1166
1167 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1168 {
1169         struct bnxt *bp = eth_dev->data->dev_private;
1170         struct bnxt_vnic_info *vnic;
1171         uint32_t old_flags;
1172         int rc;
1173
1174         rc = is_bnxt_in_error(bp);
1175         if (rc)
1176                 return rc;
1177
1178         if (bp->vnic_info == NULL)
1179                 return 0;
1180
1181         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1182
1183         old_flags = vnic->flags;
1184         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1185         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1186         if (rc != 0)
1187                 vnic->flags = old_flags;
1188
1189         return rc;
1190 }
1191
1192 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1193 {
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195         struct bnxt_vnic_info *vnic;
1196         uint32_t old_flags;
1197         int rc;
1198
1199         rc = is_bnxt_in_error(bp);
1200         if (rc)
1201                 return rc;
1202
1203         if (bp->vnic_info == NULL)
1204                 return 0;
1205
1206         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1207
1208         old_flags = vnic->flags;
1209         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1210         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1211         if (rc != 0)
1212                 vnic->flags = old_flags;
1213
1214         return rc;
1215 }
1216
1217 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1218 {
1219         struct bnxt *bp = eth_dev->data->dev_private;
1220         struct bnxt_vnic_info *vnic;
1221         uint32_t old_flags;
1222         int rc;
1223
1224         rc = is_bnxt_in_error(bp);
1225         if (rc)
1226                 return rc;
1227
1228         if (bp->vnic_info == NULL)
1229                 return 0;
1230
1231         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1232
1233         old_flags = vnic->flags;
1234         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1235         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1236         if (rc != 0)
1237                 vnic->flags = old_flags;
1238
1239         return rc;
1240 }
1241
1242 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1243 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1244 {
1245         if (qid >= bp->rx_nr_rings)
1246                 return NULL;
1247
1248         return bp->eth_dev->data->rx_queues[qid];
1249 }
1250
1251 /* Return rxq corresponding to a given rss table ring/group ID. */
1252 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1253 {
1254         struct bnxt_rx_queue *rxq;
1255         unsigned int i;
1256
1257         if (!BNXT_HAS_RING_GRPS(bp)) {
1258                 for (i = 0; i < bp->rx_nr_rings; i++) {
1259                         rxq = bp->eth_dev->data->rx_queues[i];
1260                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1261                                 return rxq->index;
1262                 }
1263         } else {
1264                 for (i = 0; i < bp->rx_nr_rings; i++) {
1265                         if (bp->grp_info[i].fw_grp_id == fwr)
1266                                 return i;
1267                 }
1268         }
1269
1270         return INVALID_HW_RING_ID;
1271 }
1272
1273 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1274                             struct rte_eth_rss_reta_entry64 *reta_conf,
1275                             uint16_t reta_size)
1276 {
1277         struct bnxt *bp = eth_dev->data->dev_private;
1278         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1279         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1280         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1281         uint16_t idx, sft;
1282         int i, rc;
1283
1284         rc = is_bnxt_in_error(bp);
1285         if (rc)
1286                 return rc;
1287
1288         if (!vnic->rss_table)
1289                 return -EINVAL;
1290
1291         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1292                 return -EINVAL;
1293
1294         if (reta_size != tbl_size) {
1295                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1296                         "(%d) must equal the size supported by the hardware "
1297                         "(%d)\n", reta_size, tbl_size);
1298                 return -EINVAL;
1299         }
1300
1301         for (i = 0; i < reta_size; i++) {
1302                 struct bnxt_rx_queue *rxq;
1303
1304                 idx = i / RTE_RETA_GROUP_SIZE;
1305                 sft = i % RTE_RETA_GROUP_SIZE;
1306
1307                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1308                         continue;
1309
1310                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1311                 if (!rxq) {
1312                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1313                         return -EINVAL;
1314                 }
1315
1316                 if (BNXT_CHIP_THOR(bp)) {
1317                         vnic->rss_table[i * 2] =
1318                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1319                         vnic->rss_table[i * 2 + 1] =
1320                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1321                 } else {
1322                         vnic->rss_table[i] =
1323                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1324                 }
1325
1326                 vnic->rss_table[i] =
1327                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1328         }
1329
1330         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1331         return 0;
1332 }
1333
1334 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1335                               struct rte_eth_rss_reta_entry64 *reta_conf,
1336                               uint16_t reta_size)
1337 {
1338         struct bnxt *bp = eth_dev->data->dev_private;
1339         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1340         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1341         uint16_t idx, sft, i;
1342         int rc;
1343
1344         rc = is_bnxt_in_error(bp);
1345         if (rc)
1346                 return rc;
1347
1348         /* Retrieve from the default VNIC */
1349         if (!vnic)
1350                 return -EINVAL;
1351         if (!vnic->rss_table)
1352                 return -EINVAL;
1353
1354         if (reta_size != tbl_size) {
1355                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1356                         "(%d) must equal the size supported by the hardware "
1357                         "(%d)\n", reta_size, tbl_size);
1358                 return -EINVAL;
1359         }
1360
1361         for (idx = 0, i = 0; i < reta_size; i++) {
1362                 idx = i / RTE_RETA_GROUP_SIZE;
1363                 sft = i % RTE_RETA_GROUP_SIZE;
1364
1365                 if (reta_conf[idx].mask & (1ULL << sft)) {
1366                         uint16_t qid;
1367
1368                         if (BNXT_CHIP_THOR(bp))
1369                                 qid = bnxt_rss_to_qid(bp,
1370                                                       vnic->rss_table[i * 2]);
1371                         else
1372                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1373
1374                         if (qid == INVALID_HW_RING_ID) {
1375                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1376                                 return -EINVAL;
1377                         }
1378                         reta_conf[idx].reta[sft] = qid;
1379                 }
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1386                                    struct rte_eth_rss_conf *rss_conf)
1387 {
1388         struct bnxt *bp = eth_dev->data->dev_private;
1389         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1390         struct bnxt_vnic_info *vnic;
1391         int rc;
1392
1393         rc = is_bnxt_in_error(bp);
1394         if (rc)
1395                 return rc;
1396
1397         /*
1398          * If RSS enablement were different than dev_configure,
1399          * then return -EINVAL
1400          */
1401         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1402                 if (!rss_conf->rss_hf)
1403                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1404         } else {
1405                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1406                         return -EINVAL;
1407         }
1408
1409         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1410         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1411
1412         /* Update the default RSS VNIC(s) */
1413         vnic = &bp->vnic_info[0];
1414         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1415
1416         /*
1417          * If hashkey is not specified, use the previously configured
1418          * hashkey
1419          */
1420         if (!rss_conf->rss_key)
1421                 goto rss_config;
1422
1423         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1424                 PMD_DRV_LOG(ERR,
1425                             "Invalid hashkey length, should be 16 bytes\n");
1426                 return -EINVAL;
1427         }
1428         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1429
1430 rss_config:
1431         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1432         return 0;
1433 }
1434
1435 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1436                                      struct rte_eth_rss_conf *rss_conf)
1437 {
1438         struct bnxt *bp = eth_dev->data->dev_private;
1439         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1440         int len, rc;
1441         uint32_t hash_types;
1442
1443         rc = is_bnxt_in_error(bp);
1444         if (rc)
1445                 return rc;
1446
1447         /* RSS configuration is the same for all VNICs */
1448         if (vnic && vnic->rss_hash_key) {
1449                 if (rss_conf->rss_key) {
1450                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1451                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1452                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1453                 }
1454
1455                 hash_types = vnic->hash_type;
1456                 rss_conf->rss_hf = 0;
1457                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1458                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1459                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1460                 }
1461                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1462                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1463                         hash_types &=
1464                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1465                 }
1466                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1467                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1468                         hash_types &=
1469                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1470                 }
1471                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1472                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1473                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1474                 }
1475                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1476                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1477                         hash_types &=
1478                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1479                 }
1480                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1481                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1482                         hash_types &=
1483                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1484                 }
1485                 if (hash_types) {
1486                         PMD_DRV_LOG(ERR,
1487                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1488                                 vnic->hash_type);
1489                         return -ENOTSUP;
1490                 }
1491         } else {
1492                 rss_conf->rss_hf = 0;
1493         }
1494         return 0;
1495 }
1496
1497 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1498                                struct rte_eth_fc_conf *fc_conf)
1499 {
1500         struct bnxt *bp = dev->data->dev_private;
1501         struct rte_eth_link link_info;
1502         int rc;
1503
1504         rc = is_bnxt_in_error(bp);
1505         if (rc)
1506                 return rc;
1507
1508         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1509         if (rc)
1510                 return rc;
1511
1512         memset(fc_conf, 0, sizeof(*fc_conf));
1513         if (bp->link_info.auto_pause)
1514                 fc_conf->autoneg = 1;
1515         switch (bp->link_info.pause) {
1516         case 0:
1517                 fc_conf->mode = RTE_FC_NONE;
1518                 break;
1519         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1520                 fc_conf->mode = RTE_FC_TX_PAUSE;
1521                 break;
1522         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1523                 fc_conf->mode = RTE_FC_RX_PAUSE;
1524                 break;
1525         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1526                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1527                 fc_conf->mode = RTE_FC_FULL;
1528                 break;
1529         }
1530         return 0;
1531 }
1532
1533 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1534                                struct rte_eth_fc_conf *fc_conf)
1535 {
1536         struct bnxt *bp = dev->data->dev_private;
1537         int rc;
1538
1539         rc = is_bnxt_in_error(bp);
1540         if (rc)
1541                 return rc;
1542
1543         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1544                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1545                 return -ENOTSUP;
1546         }
1547
1548         switch (fc_conf->mode) {
1549         case RTE_FC_NONE:
1550                 bp->link_info.auto_pause = 0;
1551                 bp->link_info.force_pause = 0;
1552                 break;
1553         case RTE_FC_RX_PAUSE:
1554                 if (fc_conf->autoneg) {
1555                         bp->link_info.auto_pause =
1556                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1557                         bp->link_info.force_pause = 0;
1558                 } else {
1559                         bp->link_info.auto_pause = 0;
1560                         bp->link_info.force_pause =
1561                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1562                 }
1563                 break;
1564         case RTE_FC_TX_PAUSE:
1565                 if (fc_conf->autoneg) {
1566                         bp->link_info.auto_pause =
1567                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1568                         bp->link_info.force_pause = 0;
1569                 } else {
1570                         bp->link_info.auto_pause = 0;
1571                         bp->link_info.force_pause =
1572                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1573                 }
1574                 break;
1575         case RTE_FC_FULL:
1576                 if (fc_conf->autoneg) {
1577                         bp->link_info.auto_pause =
1578                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1579                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1580                         bp->link_info.force_pause = 0;
1581                 } else {
1582                         bp->link_info.auto_pause = 0;
1583                         bp->link_info.force_pause =
1584                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1585                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1586                 }
1587                 break;
1588         }
1589         return bnxt_set_hwrm_link_config(bp, true);
1590 }
1591
1592 /* Add UDP tunneling port */
1593 static int
1594 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1595                          struct rte_eth_udp_tunnel *udp_tunnel)
1596 {
1597         struct bnxt *bp = eth_dev->data->dev_private;
1598         uint16_t tunnel_type = 0;
1599         int rc = 0;
1600
1601         rc = is_bnxt_in_error(bp);
1602         if (rc)
1603                 return rc;
1604
1605         switch (udp_tunnel->prot_type) {
1606         case RTE_TUNNEL_TYPE_VXLAN:
1607                 if (bp->vxlan_port_cnt) {
1608                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1609                                 udp_tunnel->udp_port);
1610                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1611                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1612                                 return -ENOSPC;
1613                         }
1614                         bp->vxlan_port_cnt++;
1615                         return 0;
1616                 }
1617                 tunnel_type =
1618                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1619                 bp->vxlan_port_cnt++;
1620                 break;
1621         case RTE_TUNNEL_TYPE_GENEVE:
1622                 if (bp->geneve_port_cnt) {
1623                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1624                                 udp_tunnel->udp_port);
1625                         if (bp->geneve_port != udp_tunnel->udp_port) {
1626                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1627                                 return -ENOSPC;
1628                         }
1629                         bp->geneve_port_cnt++;
1630                         return 0;
1631                 }
1632                 tunnel_type =
1633                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1634                 bp->geneve_port_cnt++;
1635                 break;
1636         default:
1637                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1638                 return -ENOTSUP;
1639         }
1640         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1641                                              tunnel_type);
1642         return rc;
1643 }
1644
1645 static int
1646 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1647                          struct rte_eth_udp_tunnel *udp_tunnel)
1648 {
1649         struct bnxt *bp = eth_dev->data->dev_private;
1650         uint16_t tunnel_type = 0;
1651         uint16_t port = 0;
1652         int rc = 0;
1653
1654         rc = is_bnxt_in_error(bp);
1655         if (rc)
1656                 return rc;
1657
1658         switch (udp_tunnel->prot_type) {
1659         case RTE_TUNNEL_TYPE_VXLAN:
1660                 if (!bp->vxlan_port_cnt) {
1661                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1662                         return -EINVAL;
1663                 }
1664                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1665                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1666                                 udp_tunnel->udp_port, bp->vxlan_port);
1667                         return -EINVAL;
1668                 }
1669                 if (--bp->vxlan_port_cnt)
1670                         return 0;
1671
1672                 tunnel_type =
1673                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1674                 port = bp->vxlan_fw_dst_port_id;
1675                 break;
1676         case RTE_TUNNEL_TYPE_GENEVE:
1677                 if (!bp->geneve_port_cnt) {
1678                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1679                         return -EINVAL;
1680                 }
1681                 if (bp->geneve_port != udp_tunnel->udp_port) {
1682                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1683                                 udp_tunnel->udp_port, bp->geneve_port);
1684                         return -EINVAL;
1685                 }
1686                 if (--bp->geneve_port_cnt)
1687                         return 0;
1688
1689                 tunnel_type =
1690                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1691                 port = bp->geneve_fw_dst_port_id;
1692                 break;
1693         default:
1694                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1695                 return -ENOTSUP;
1696         }
1697
1698         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1699         if (!rc) {
1700                 if (tunnel_type ==
1701                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1702                         bp->vxlan_port = 0;
1703                 if (tunnel_type ==
1704                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1705                         bp->geneve_port = 0;
1706         }
1707         return rc;
1708 }
1709
1710 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1711 {
1712         struct bnxt_filter_info *filter;
1713         struct bnxt_vnic_info *vnic;
1714         int rc = 0;
1715         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1716
1717         /* if VLAN exists && VLAN matches vlan_id
1718          *      remove the MAC+VLAN filter
1719          *      add a new MAC only filter
1720          * else
1721          *      VLAN filter doesn't exist, just skip and continue
1722          */
1723         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1724         filter = STAILQ_FIRST(&vnic->filter);
1725         while (filter) {
1726                 /* Search for this matching MAC+VLAN filter */
1727                 if ((filter->enables & chk) &&
1728                     (filter->l2_ivlan == vlan_id &&
1729                      filter->l2_ivlan_mask != 0) &&
1730                     !memcmp(filter->l2_addr, bp->mac_addr,
1731                             RTE_ETHER_ADDR_LEN)) {
1732                         /* Delete the filter */
1733                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1734                         if (rc)
1735                                 return rc;
1736                         STAILQ_REMOVE(&vnic->filter, filter,
1737                                       bnxt_filter_info, next);
1738                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1739
1740                         PMD_DRV_LOG(INFO,
1741                                     "Del Vlan filter for %d\n",
1742                                     vlan_id);
1743                         return rc;
1744                 }
1745                 filter = STAILQ_NEXT(filter, next);
1746         }
1747         return -ENOENT;
1748 }
1749
1750 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1751 {
1752         struct bnxt_filter_info *filter;
1753         struct bnxt_vnic_info *vnic;
1754         int rc = 0;
1755         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1756                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1757         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1758
1759         /* Implementation notes on the use of VNIC in this command:
1760          *
1761          * By default, these filters belong to default vnic for the function.
1762          * Once these filters are set up, only destination VNIC can be modified.
1763          * If the destination VNIC is not specified in this command,
1764          * then the HWRM shall only create an l2 context id.
1765          */
1766
1767         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1768         filter = STAILQ_FIRST(&vnic->filter);
1769         /* Check if the VLAN has already been added */
1770         while (filter) {
1771                 if ((filter->enables & chk) &&
1772                     (filter->l2_ivlan == vlan_id &&
1773                      filter->l2_ivlan_mask == 0x0FFF) &&
1774                      !memcmp(filter->l2_addr, bp->mac_addr,
1775                              RTE_ETHER_ADDR_LEN))
1776                         return -EEXIST;
1777
1778                 filter = STAILQ_NEXT(filter, next);
1779         }
1780
1781         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1782          * command to create MAC+VLAN filter with the right flags, enables set.
1783          */
1784         filter = bnxt_alloc_filter(bp);
1785         if (!filter) {
1786                 PMD_DRV_LOG(ERR,
1787                             "MAC/VLAN filter alloc failed\n");
1788                 return -ENOMEM;
1789         }
1790         /* MAC + VLAN ID filter */
1791         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1792          * untagged packets are received
1793          *
1794          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1795          * packets and only the programmed vlan's packets are received
1796          */
1797         filter->l2_ivlan = vlan_id;
1798         filter->l2_ivlan_mask = 0x0FFF;
1799         filter->enables |= en;
1800         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1801
1802         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1803         if (rc) {
1804                 /* Free the newly allocated filter as we were
1805                  * not able to create the filter in hardware.
1806                  */
1807                 filter->fw_l2_filter_id = UINT64_MAX;
1808                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1809                 return rc;
1810         } else {
1811                 /* Add this new filter to the list */
1812                 if (vlan_id == 0) {
1813                         filter->dflt = true;
1814                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1815                 } else {
1816                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1817                 }
1818         }
1819
1820         PMD_DRV_LOG(INFO,
1821                     "Added Vlan filter for %d\n", vlan_id);
1822         return rc;
1823 }
1824
1825 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1826                 uint16_t vlan_id, int on)
1827 {
1828         struct bnxt *bp = eth_dev->data->dev_private;
1829         int rc;
1830
1831         rc = is_bnxt_in_error(bp);
1832         if (rc)
1833                 return rc;
1834
1835         /* These operations apply to ALL existing MAC/VLAN filters */
1836         if (on)
1837                 return bnxt_add_vlan_filter(bp, vlan_id);
1838         else
1839                 return bnxt_del_vlan_filter(bp, vlan_id);
1840 }
1841
1842 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1843                                     struct bnxt_vnic_info *vnic)
1844 {
1845         struct bnxt_filter_info *filter;
1846         int rc;
1847
1848         filter = STAILQ_FIRST(&vnic->filter);
1849         while (filter) {
1850                 if (filter->dflt &&
1851                     !memcmp(filter->l2_addr, bp->mac_addr,
1852                             RTE_ETHER_ADDR_LEN)) {
1853                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1854                         if (rc)
1855                                 return rc;
1856                         filter->dflt = false;
1857                         STAILQ_REMOVE(&vnic->filter, filter,
1858                                       bnxt_filter_info, next);
1859                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1860                                            filter, next);
1861                         filter->fw_l2_filter_id = -1;
1862                         break;
1863                 }
1864                 filter = STAILQ_NEXT(filter, next);
1865         }
1866         return 0;
1867 }
1868
1869 static int
1870 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1871 {
1872         struct bnxt *bp = dev->data->dev_private;
1873         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1874         struct bnxt_vnic_info *vnic;
1875         unsigned int i;
1876         int rc;
1877
1878         rc = is_bnxt_in_error(bp);
1879         if (rc)
1880                 return rc;
1881
1882         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1883         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1884                 /* Remove any VLAN filters programmed */
1885                 for (i = 0; i < 4095; i++)
1886                         bnxt_del_vlan_filter(bp, i);
1887
1888                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1889                 if (rc)
1890                         return rc;
1891         } else {
1892                 /* Default filter will allow packets that match the
1893                  * dest mac. So, it has to be deleted, otherwise, we
1894                  * will endup receiving vlan packets for which the
1895                  * filter is not programmed, when hw-vlan-filter
1896                  * configuration is ON
1897                  */
1898                 bnxt_del_dflt_mac_filter(bp, vnic);
1899                 /* This filter will allow only untagged packets */
1900                 bnxt_add_vlan_filter(bp, 0);
1901         }
1902         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1903                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1904
1905         if (mask & ETH_VLAN_STRIP_MASK) {
1906                 /* Enable or disable VLAN stripping */
1907                 for (i = 0; i < bp->nr_vnics; i++) {
1908                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1909                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1910                                 vnic->vlan_strip = true;
1911                         else
1912                                 vnic->vlan_strip = false;
1913                         bnxt_hwrm_vnic_cfg(bp, vnic);
1914                 }
1915                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1916                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1917         }
1918
1919         if (mask & ETH_VLAN_EXTEND_MASK) {
1920                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1921                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1922                 else
1923                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1924         }
1925
1926         return 0;
1927 }
1928
1929 static int
1930 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1931                       uint16_t tpid)
1932 {
1933         struct bnxt *bp = dev->data->dev_private;
1934         int qinq = dev->data->dev_conf.rxmode.offloads &
1935                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1936
1937         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1938             vlan_type != ETH_VLAN_TYPE_OUTER) {
1939                 PMD_DRV_LOG(ERR,
1940                             "Unsupported vlan type.");
1941                 return -EINVAL;
1942         }
1943         if (!qinq) {
1944                 PMD_DRV_LOG(ERR,
1945                             "QinQ not enabled. Needs to be ON as we can "
1946                             "accelerate only outer vlan\n");
1947                 return -EINVAL;
1948         }
1949
1950         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1951                 switch (tpid) {
1952                 case RTE_ETHER_TYPE_QINQ:
1953                         bp->outer_tpid_bd =
1954                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1955                                 break;
1956                 case RTE_ETHER_TYPE_VLAN:
1957                         bp->outer_tpid_bd =
1958                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1959                                 break;
1960                 case 0x9100:
1961                         bp->outer_tpid_bd =
1962                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1963                                 break;
1964                 case 0x9200:
1965                         bp->outer_tpid_bd =
1966                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1967                                 break;
1968                 case 0x9300:
1969                         bp->outer_tpid_bd =
1970                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1971                                 break;
1972                 default:
1973                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1974                         return -EINVAL;
1975                 }
1976                 bp->outer_tpid_bd |= tpid;
1977                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1978         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1979                 PMD_DRV_LOG(ERR,
1980                             "Can accelerate only outer vlan in QinQ\n");
1981                 return -EINVAL;
1982         }
1983
1984         return 0;
1985 }
1986
1987 static int
1988 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1989                              struct rte_ether_addr *addr)
1990 {
1991         struct bnxt *bp = dev->data->dev_private;
1992         /* Default Filter is tied to VNIC 0 */
1993         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1994         struct bnxt_filter_info *filter;
1995         int rc;
1996
1997         rc = is_bnxt_in_error(bp);
1998         if (rc)
1999                 return rc;
2000
2001         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2002                 return -EPERM;
2003
2004         if (rte_is_zero_ether_addr(addr))
2005                 return -EINVAL;
2006
2007         STAILQ_FOREACH(filter, &vnic->filter, next) {
2008                 /* Default Filter is at Index 0 */
2009                 if (filter->mac_index != 0)
2010                         continue;
2011
2012                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2013                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2014                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2015                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2016                 filter->enables |=
2017                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2018                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2019
2020                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2021                 if (rc) {
2022                         memcpy(filter->l2_addr, bp->mac_addr,
2023                                RTE_ETHER_ADDR_LEN);
2024                         return rc;
2025                 }
2026
2027                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2028                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2029                 return 0;
2030         }
2031
2032         return 0;
2033 }
2034
2035 static int
2036 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2037                           struct rte_ether_addr *mc_addr_set,
2038                           uint32_t nb_mc_addr)
2039 {
2040         struct bnxt *bp = eth_dev->data->dev_private;
2041         char *mc_addr_list = (char *)mc_addr_set;
2042         struct bnxt_vnic_info *vnic;
2043         uint32_t off = 0, i = 0;
2044         int rc;
2045
2046         rc = is_bnxt_in_error(bp);
2047         if (rc)
2048                 return rc;
2049
2050         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2051
2052         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2053                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2054                 goto allmulti;
2055         }
2056
2057         /* TODO Check for Duplicate mcast addresses */
2058         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2059         for (i = 0; i < nb_mc_addr; i++) {
2060                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2061                         RTE_ETHER_ADDR_LEN);
2062                 off += RTE_ETHER_ADDR_LEN;
2063         }
2064
2065         vnic->mc_addr_cnt = i;
2066         if (vnic->mc_addr_cnt)
2067                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2068         else
2069                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2070
2071 allmulti:
2072         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2073 }
2074
2075 static int
2076 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2077 {
2078         struct bnxt *bp = dev->data->dev_private;
2079         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2080         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2081         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2082         int ret;
2083
2084         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2085                         fw_major, fw_minor, fw_updt);
2086
2087         ret += 1; /* add the size of '\0' */
2088         if (fw_size < (uint32_t)ret)
2089                 return ret;
2090         else
2091                 return 0;
2092 }
2093
2094 static void
2095 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2096         struct rte_eth_rxq_info *qinfo)
2097 {
2098         struct bnxt_rx_queue *rxq;
2099
2100         rxq = dev->data->rx_queues[queue_id];
2101
2102         qinfo->mp = rxq->mb_pool;
2103         qinfo->scattered_rx = dev->data->scattered_rx;
2104         qinfo->nb_desc = rxq->nb_rx_desc;
2105
2106         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2107         qinfo->conf.rx_drop_en = 0;
2108         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2109 }
2110
2111 static void
2112 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2113         struct rte_eth_txq_info *qinfo)
2114 {
2115         struct bnxt_tx_queue *txq;
2116
2117         txq = dev->data->tx_queues[queue_id];
2118
2119         qinfo->nb_desc = txq->nb_tx_desc;
2120
2121         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2122         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2123         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2124
2125         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2126         qinfo->conf.tx_rs_thresh = 0;
2127         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2128 }
2129
2130 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2131 {
2132         struct bnxt *bp = eth_dev->data->dev_private;
2133         uint32_t new_pkt_size;
2134         uint32_t rc = 0;
2135         uint32_t i;
2136
2137         rc = is_bnxt_in_error(bp);
2138         if (rc)
2139                 return rc;
2140
2141         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2142                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2143
2144 #ifdef RTE_ARCH_X86
2145         /*
2146          * If vector-mode tx/rx is active, disallow any MTU change that would
2147          * require scattered receive support.
2148          */
2149         if (eth_dev->data->dev_started &&
2150             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2151              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2152             (new_pkt_size >
2153              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2154                 PMD_DRV_LOG(ERR,
2155                             "MTU change would require scattered rx support. ");
2156                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2157                 return -EINVAL;
2158         }
2159 #endif
2160
2161         if (new_mtu > RTE_ETHER_MTU) {
2162                 bp->flags |= BNXT_FLAG_JUMBO;
2163                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2164                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2165         } else {
2166                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2167                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2168                 bp->flags &= ~BNXT_FLAG_JUMBO;
2169         }
2170
2171         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2172
2173         for (i = 0; i < bp->nr_vnics; i++) {
2174                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2175                 uint16_t size = 0;
2176
2177                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2178                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2179                 if (rc)
2180                         break;
2181
2182                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2183                 size -= RTE_PKTMBUF_HEADROOM;
2184
2185                 if (size < new_mtu) {
2186                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2187                         if (rc)
2188                                 return rc;
2189                 }
2190         }
2191
2192         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2193
2194         return rc;
2195 }
2196
2197 static int
2198 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2199 {
2200         struct bnxt *bp = dev->data->dev_private;
2201         uint16_t vlan = bp->vlan;
2202         int rc;
2203
2204         rc = is_bnxt_in_error(bp);
2205         if (rc)
2206                 return rc;
2207
2208         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2209                 PMD_DRV_LOG(ERR,
2210                         "PVID cannot be modified for this function\n");
2211                 return -ENOTSUP;
2212         }
2213         bp->vlan = on ? pvid : 0;
2214
2215         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2216         if (rc)
2217                 bp->vlan = vlan;
2218         return rc;
2219 }
2220
2221 static int
2222 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2223 {
2224         struct bnxt *bp = dev->data->dev_private;
2225         int rc;
2226
2227         rc = is_bnxt_in_error(bp);
2228         if (rc)
2229                 return rc;
2230
2231         return bnxt_hwrm_port_led_cfg(bp, true);
2232 }
2233
2234 static int
2235 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2236 {
2237         struct bnxt *bp = dev->data->dev_private;
2238         int rc;
2239
2240         rc = is_bnxt_in_error(bp);
2241         if (rc)
2242                 return rc;
2243
2244         return bnxt_hwrm_port_led_cfg(bp, false);
2245 }
2246
2247 static uint32_t
2248 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2249 {
2250         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2251         uint32_t desc = 0, raw_cons = 0, cons;
2252         struct bnxt_cp_ring_info *cpr;
2253         struct bnxt_rx_queue *rxq;
2254         struct rx_pkt_cmpl *rxcmp;
2255         int rc;
2256
2257         rc = is_bnxt_in_error(bp);
2258         if (rc)
2259                 return rc;
2260
2261         rxq = dev->data->rx_queues[rx_queue_id];
2262         cpr = rxq->cp_ring;
2263         raw_cons = cpr->cp_raw_cons;
2264
2265         while (1) {
2266                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2267                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2268                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2269
2270                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2271                         break;
2272                 } else {
2273                         raw_cons++;
2274                         desc++;
2275                 }
2276         }
2277
2278         return desc;
2279 }
2280
2281 static int
2282 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2283 {
2284         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2285         struct bnxt_rx_ring_info *rxr;
2286         struct bnxt_cp_ring_info *cpr;
2287         struct bnxt_sw_rx_bd *rx_buf;
2288         struct rx_pkt_cmpl *rxcmp;
2289         uint32_t cons, cp_cons;
2290         int rc;
2291
2292         if (!rxq)
2293                 return -EINVAL;
2294
2295         rc = is_bnxt_in_error(rxq->bp);
2296         if (rc)
2297                 return rc;
2298
2299         cpr = rxq->cp_ring;
2300         rxr = rxq->rx_ring;
2301
2302         if (offset >= rxq->nb_rx_desc)
2303                 return -EINVAL;
2304
2305         cons = RING_CMP(cpr->cp_ring_struct, offset);
2306         cp_cons = cpr->cp_raw_cons;
2307         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2308
2309         if (cons > cp_cons) {
2310                 if (CMPL_VALID(rxcmp, cpr->valid))
2311                         return RTE_ETH_RX_DESC_DONE;
2312         } else {
2313                 if (CMPL_VALID(rxcmp, !cpr->valid))
2314                         return RTE_ETH_RX_DESC_DONE;
2315         }
2316         rx_buf = &rxr->rx_buf_ring[cons];
2317         if (rx_buf->mbuf == NULL)
2318                 return RTE_ETH_RX_DESC_UNAVAIL;
2319
2320
2321         return RTE_ETH_RX_DESC_AVAIL;
2322 }
2323
2324 static int
2325 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2326 {
2327         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2328         struct bnxt_tx_ring_info *txr;
2329         struct bnxt_cp_ring_info *cpr;
2330         struct bnxt_sw_tx_bd *tx_buf;
2331         struct tx_pkt_cmpl *txcmp;
2332         uint32_t cons, cp_cons;
2333         int rc;
2334
2335         if (!txq)
2336                 return -EINVAL;
2337
2338         rc = is_bnxt_in_error(txq->bp);
2339         if (rc)
2340                 return rc;
2341
2342         cpr = txq->cp_ring;
2343         txr = txq->tx_ring;
2344
2345         if (offset >= txq->nb_tx_desc)
2346                 return -EINVAL;
2347
2348         cons = RING_CMP(cpr->cp_ring_struct, offset);
2349         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2350         cp_cons = cpr->cp_raw_cons;
2351
2352         if (cons > cp_cons) {
2353                 if (CMPL_VALID(txcmp, cpr->valid))
2354                         return RTE_ETH_TX_DESC_UNAVAIL;
2355         } else {
2356                 if (CMPL_VALID(txcmp, !cpr->valid))
2357                         return RTE_ETH_TX_DESC_UNAVAIL;
2358         }
2359         tx_buf = &txr->tx_buf_ring[cons];
2360         if (tx_buf->mbuf == NULL)
2361                 return RTE_ETH_TX_DESC_DONE;
2362
2363         return RTE_ETH_TX_DESC_FULL;
2364 }
2365
2366 static struct bnxt_filter_info *
2367 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2368                                 struct rte_eth_ethertype_filter *efilter,
2369                                 struct bnxt_vnic_info *vnic0,
2370                                 struct bnxt_vnic_info *vnic,
2371                                 int *ret)
2372 {
2373         struct bnxt_filter_info *mfilter = NULL;
2374         int match = 0;
2375         *ret = 0;
2376
2377         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2378                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2379                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2380                         " ethertype filter.", efilter->ether_type);
2381                 *ret = -EINVAL;
2382                 goto exit;
2383         }
2384         if (efilter->queue >= bp->rx_nr_rings) {
2385                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2386                 *ret = -EINVAL;
2387                 goto exit;
2388         }
2389
2390         vnic0 = &bp->vnic_info[0];
2391         vnic = &bp->vnic_info[efilter->queue];
2392         if (vnic == NULL) {
2393                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2394                 *ret = -EINVAL;
2395                 goto exit;
2396         }
2397
2398         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2399                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2400                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2401                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2402                              mfilter->flags ==
2403                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2404                              mfilter->ethertype == efilter->ether_type)) {
2405                                 match = 1;
2406                                 break;
2407                         }
2408                 }
2409         } else {
2410                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2411                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2412                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2413                              mfilter->ethertype == efilter->ether_type &&
2414                              mfilter->flags ==
2415                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2416                                 match = 1;
2417                                 break;
2418                         }
2419         }
2420
2421         if (match)
2422                 *ret = -EEXIST;
2423
2424 exit:
2425         return mfilter;
2426 }
2427
2428 static int
2429 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2430                         enum rte_filter_op filter_op,
2431                         void *arg)
2432 {
2433         struct bnxt *bp = dev->data->dev_private;
2434         struct rte_eth_ethertype_filter *efilter =
2435                         (struct rte_eth_ethertype_filter *)arg;
2436         struct bnxt_filter_info *bfilter, *filter1;
2437         struct bnxt_vnic_info *vnic, *vnic0;
2438         int ret;
2439
2440         if (filter_op == RTE_ETH_FILTER_NOP)
2441                 return 0;
2442
2443         if (arg == NULL) {
2444                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2445                             filter_op);
2446                 return -EINVAL;
2447         }
2448
2449         vnic0 = &bp->vnic_info[0];
2450         vnic = &bp->vnic_info[efilter->queue];
2451
2452         switch (filter_op) {
2453         case RTE_ETH_FILTER_ADD:
2454                 bnxt_match_and_validate_ether_filter(bp, efilter,
2455                                                         vnic0, vnic, &ret);
2456                 if (ret < 0)
2457                         return ret;
2458
2459                 bfilter = bnxt_get_unused_filter(bp);
2460                 if (bfilter == NULL) {
2461                         PMD_DRV_LOG(ERR,
2462                                 "Not enough resources for a new filter.\n");
2463                         return -ENOMEM;
2464                 }
2465                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2466                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2467                        RTE_ETHER_ADDR_LEN);
2468                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2469                        RTE_ETHER_ADDR_LEN);
2470                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2471                 bfilter->ethertype = efilter->ether_type;
2472                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2473
2474                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2475                 if (filter1 == NULL) {
2476                         ret = -EINVAL;
2477                         goto cleanup;
2478                 }
2479                 bfilter->enables |=
2480                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2481                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2482
2483                 bfilter->dst_id = vnic->fw_vnic_id;
2484
2485                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2486                         bfilter->flags =
2487                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2488                 }
2489
2490                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2491                 if (ret)
2492                         goto cleanup;
2493                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2494                 break;
2495         case RTE_ETH_FILTER_DELETE:
2496                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2497                                                         vnic0, vnic, &ret);
2498                 if (ret == -EEXIST) {
2499                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2500
2501                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2502                                       next);
2503                         bnxt_free_filter(bp, filter1);
2504                 } else if (ret == 0) {
2505                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2506                 }
2507                 break;
2508         default:
2509                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2510                 ret = -EINVAL;
2511                 goto error;
2512         }
2513         return ret;
2514 cleanup:
2515         bnxt_free_filter(bp, bfilter);
2516 error:
2517         return ret;
2518 }
2519
2520 static inline int
2521 parse_ntuple_filter(struct bnxt *bp,
2522                     struct rte_eth_ntuple_filter *nfilter,
2523                     struct bnxt_filter_info *bfilter)
2524 {
2525         uint32_t en = 0;
2526
2527         if (nfilter->queue >= bp->rx_nr_rings) {
2528                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2529                 return -EINVAL;
2530         }
2531
2532         switch (nfilter->dst_port_mask) {
2533         case UINT16_MAX:
2534                 bfilter->dst_port_mask = -1;
2535                 bfilter->dst_port = nfilter->dst_port;
2536                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2537                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2538                 break;
2539         default:
2540                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2541                 return -EINVAL;
2542         }
2543
2544         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2545         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2546
2547         switch (nfilter->proto_mask) {
2548         case UINT8_MAX:
2549                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2550                         bfilter->ip_protocol = 17;
2551                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2552                         bfilter->ip_protocol = 6;
2553                 else
2554                         return -EINVAL;
2555                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2556                 break;
2557         default:
2558                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2559                 return -EINVAL;
2560         }
2561
2562         switch (nfilter->dst_ip_mask) {
2563         case UINT32_MAX:
2564                 bfilter->dst_ipaddr_mask[0] = -1;
2565                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2566                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2567                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2568                 break;
2569         default:
2570                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2571                 return -EINVAL;
2572         }
2573
2574         switch (nfilter->src_ip_mask) {
2575         case UINT32_MAX:
2576                 bfilter->src_ipaddr_mask[0] = -1;
2577                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2578                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2579                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2580                 break;
2581         default:
2582                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2583                 return -EINVAL;
2584         }
2585
2586         switch (nfilter->src_port_mask) {
2587         case UINT16_MAX:
2588                 bfilter->src_port_mask = -1;
2589                 bfilter->src_port = nfilter->src_port;
2590                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2591                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2592                 break;
2593         default:
2594                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2595                 return -EINVAL;
2596         }
2597
2598         //TODO Priority
2599         //nfilter->priority = (uint8_t)filter->priority;
2600
2601         bfilter->enables = en;
2602         return 0;
2603 }
2604
2605 static struct bnxt_filter_info*
2606 bnxt_match_ntuple_filter(struct bnxt *bp,
2607                          struct bnxt_filter_info *bfilter,
2608                          struct bnxt_vnic_info **mvnic)
2609 {
2610         struct bnxt_filter_info *mfilter = NULL;
2611         int i;
2612
2613         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2614                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2615                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2616                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2617                             bfilter->src_ipaddr_mask[0] ==
2618                             mfilter->src_ipaddr_mask[0] &&
2619                             bfilter->src_port == mfilter->src_port &&
2620                             bfilter->src_port_mask == mfilter->src_port_mask &&
2621                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2622                             bfilter->dst_ipaddr_mask[0] ==
2623                             mfilter->dst_ipaddr_mask[0] &&
2624                             bfilter->dst_port == mfilter->dst_port &&
2625                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2626                             bfilter->flags == mfilter->flags &&
2627                             bfilter->enables == mfilter->enables) {
2628                                 if (mvnic)
2629                                         *mvnic = vnic;
2630                                 return mfilter;
2631                         }
2632                 }
2633         }
2634         return NULL;
2635 }
2636
2637 static int
2638 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2639                        struct rte_eth_ntuple_filter *nfilter,
2640                        enum rte_filter_op filter_op)
2641 {
2642         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2643         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2644         int ret;
2645
2646         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2647                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2648                 return -EINVAL;
2649         }
2650
2651         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2652                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2653                 return -EINVAL;
2654         }
2655
2656         bfilter = bnxt_get_unused_filter(bp);
2657         if (bfilter == NULL) {
2658                 PMD_DRV_LOG(ERR,
2659                         "Not enough resources for a new filter.\n");
2660                 return -ENOMEM;
2661         }
2662         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2663         if (ret < 0)
2664                 goto free_filter;
2665
2666         vnic = &bp->vnic_info[nfilter->queue];
2667         vnic0 = &bp->vnic_info[0];
2668         filter1 = STAILQ_FIRST(&vnic0->filter);
2669         if (filter1 == NULL) {
2670                 ret = -EINVAL;
2671                 goto free_filter;
2672         }
2673
2674         bfilter->dst_id = vnic->fw_vnic_id;
2675         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2676         bfilter->enables |=
2677                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2678         bfilter->ethertype = 0x800;
2679         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2680
2681         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2682
2683         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2684             bfilter->dst_id == mfilter->dst_id) {
2685                 PMD_DRV_LOG(ERR, "filter exists.\n");
2686                 ret = -EEXIST;
2687                 goto free_filter;
2688         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2689                    bfilter->dst_id != mfilter->dst_id) {
2690                 mfilter->dst_id = vnic->fw_vnic_id;
2691                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2692                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2693                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2694                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2695                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2696                 goto free_filter;
2697         }
2698         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2699                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2700                 ret = -ENOENT;
2701                 goto free_filter;
2702         }
2703
2704         if (filter_op == RTE_ETH_FILTER_ADD) {
2705                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2706                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2707                 if (ret)
2708                         goto free_filter;
2709                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2710         } else {
2711                 if (mfilter == NULL) {
2712                         /* This should not happen. But for Coverity! */
2713                         ret = -ENOENT;
2714                         goto free_filter;
2715                 }
2716                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2717
2718                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2719                 bnxt_free_filter(bp, mfilter);
2720                 mfilter->fw_l2_filter_id = -1;
2721                 bnxt_free_filter(bp, bfilter);
2722                 bfilter->fw_l2_filter_id = -1;
2723         }
2724
2725         return 0;
2726 free_filter:
2727         bfilter->fw_l2_filter_id = -1;
2728         bnxt_free_filter(bp, bfilter);
2729         return ret;
2730 }
2731
2732 static int
2733 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2734                         enum rte_filter_op filter_op,
2735                         void *arg)
2736 {
2737         struct bnxt *bp = dev->data->dev_private;
2738         int ret;
2739
2740         if (filter_op == RTE_ETH_FILTER_NOP)
2741                 return 0;
2742
2743         if (arg == NULL) {
2744                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2745                             filter_op);
2746                 return -EINVAL;
2747         }
2748
2749         switch (filter_op) {
2750         case RTE_ETH_FILTER_ADD:
2751                 ret = bnxt_cfg_ntuple_filter(bp,
2752                         (struct rte_eth_ntuple_filter *)arg,
2753                         filter_op);
2754                 break;
2755         case RTE_ETH_FILTER_DELETE:
2756                 ret = bnxt_cfg_ntuple_filter(bp,
2757                         (struct rte_eth_ntuple_filter *)arg,
2758                         filter_op);
2759                 break;
2760         default:
2761                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2762                 ret = -EINVAL;
2763                 break;
2764         }
2765         return ret;
2766 }
2767
2768 static int
2769 bnxt_parse_fdir_filter(struct bnxt *bp,
2770                        struct rte_eth_fdir_filter *fdir,
2771                        struct bnxt_filter_info *filter)
2772 {
2773         enum rte_fdir_mode fdir_mode =
2774                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2775         struct bnxt_vnic_info *vnic0, *vnic;
2776         struct bnxt_filter_info *filter1;
2777         uint32_t en = 0;
2778         int i;
2779
2780         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2781                 return -EINVAL;
2782
2783         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2784         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2785
2786         switch (fdir->input.flow_type) {
2787         case RTE_ETH_FLOW_IPV4:
2788         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2789                 /* FALLTHROUGH */
2790                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2791                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2792                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2793                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2794                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2795                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2796                 filter->ip_addr_type =
2797                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2798                 filter->src_ipaddr_mask[0] = 0xffffffff;
2799                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2800                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2801                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2802                 filter->ethertype = 0x800;
2803                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2804                 break;
2805         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2806                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2807                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2808                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2809                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2810                 filter->dst_port_mask = 0xffff;
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2812                 filter->src_port_mask = 0xffff;
2813                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2814                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2815                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2816                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2817                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2818                 filter->ip_protocol = 6;
2819                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2820                 filter->ip_addr_type =
2821                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2822                 filter->src_ipaddr_mask[0] = 0xffffffff;
2823                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2824                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2825                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2826                 filter->ethertype = 0x800;
2827                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2828                 break;
2829         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2830                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2831                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2832                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2833                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2834                 filter->dst_port_mask = 0xffff;
2835                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2836                 filter->src_port_mask = 0xffff;
2837                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2838                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2839                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2840                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2841                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2842                 filter->ip_protocol = 17;
2843                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2844                 filter->ip_addr_type =
2845                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2846                 filter->src_ipaddr_mask[0] = 0xffffffff;
2847                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2848                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2850                 filter->ethertype = 0x800;
2851                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2852                 break;
2853         case RTE_ETH_FLOW_IPV6:
2854         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2855                 /* FALLTHROUGH */
2856                 filter->ip_addr_type =
2857                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2858                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2859                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2860                 rte_memcpy(filter->src_ipaddr,
2861                            fdir->input.flow.ipv6_flow.src_ip, 16);
2862                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2863                 rte_memcpy(filter->dst_ipaddr,
2864                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2865                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2866                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2867                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2868                 memset(filter->src_ipaddr_mask, 0xff, 16);
2869                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2870                 filter->ethertype = 0x86dd;
2871                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2872                 break;
2873         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2874                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2876                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2877                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2878                 filter->dst_port_mask = 0xffff;
2879                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2880                 filter->src_port_mask = 0xffff;
2881                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2882                 filter->ip_addr_type =
2883                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2884                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2885                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2886                 rte_memcpy(filter->src_ipaddr,
2887                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2888                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2889                 rte_memcpy(filter->dst_ipaddr,
2890                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2891                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2892                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2893                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2894                 memset(filter->src_ipaddr_mask, 0xff, 16);
2895                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2896                 filter->ethertype = 0x86dd;
2897                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2898                 break;
2899         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2900                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2902                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2904                 filter->dst_port_mask = 0xffff;
2905                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2906                 filter->src_port_mask = 0xffff;
2907                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2908                 filter->ip_addr_type =
2909                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2910                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2911                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2912                 rte_memcpy(filter->src_ipaddr,
2913                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2914                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2915                 rte_memcpy(filter->dst_ipaddr,
2916                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2918                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2919                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2920                 memset(filter->src_ipaddr_mask, 0xff, 16);
2921                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2922                 filter->ethertype = 0x86dd;
2923                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2924                 break;
2925         case RTE_ETH_FLOW_L2_PAYLOAD:
2926                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2927                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2928                 break;
2929         case RTE_ETH_FLOW_VXLAN:
2930                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2931                         return -EINVAL;
2932                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2933                 filter->tunnel_type =
2934                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2935                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2936                 break;
2937         case RTE_ETH_FLOW_NVGRE:
2938                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2939                         return -EINVAL;
2940                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2941                 filter->tunnel_type =
2942                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2943                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2944                 break;
2945         case RTE_ETH_FLOW_UNKNOWN:
2946         case RTE_ETH_FLOW_RAW:
2947         case RTE_ETH_FLOW_FRAG_IPV4:
2948         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2949         case RTE_ETH_FLOW_FRAG_IPV6:
2950         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2951         case RTE_ETH_FLOW_IPV6_EX:
2952         case RTE_ETH_FLOW_IPV6_TCP_EX:
2953         case RTE_ETH_FLOW_IPV6_UDP_EX:
2954         case RTE_ETH_FLOW_GENEVE:
2955                 /* FALLTHROUGH */
2956         default:
2957                 return -EINVAL;
2958         }
2959
2960         vnic0 = &bp->vnic_info[0];
2961         vnic = &bp->vnic_info[fdir->action.rx_queue];
2962         if (vnic == NULL) {
2963                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2964                 return -EINVAL;
2965         }
2966
2967         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2968                 rte_memcpy(filter->dst_macaddr,
2969                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2970                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2971         }
2972
2973         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2974                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2975                 filter1 = STAILQ_FIRST(&vnic0->filter);
2976                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2977         } else {
2978                 filter->dst_id = vnic->fw_vnic_id;
2979                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2980                         if (filter->dst_macaddr[i] == 0x00)
2981                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2982                         else
2983                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2984         }
2985
2986         if (filter1 == NULL)
2987                 return -EINVAL;
2988
2989         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2990         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2991
2992         filter->enables = en;
2993
2994         return 0;
2995 }
2996
2997 static struct bnxt_filter_info *
2998 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2999                 struct bnxt_vnic_info **mvnic)
3000 {
3001         struct bnxt_filter_info *mf = NULL;
3002         int i;
3003
3004         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3005                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3006
3007                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3008                         if (mf->filter_type == nf->filter_type &&
3009                             mf->flags == nf->flags &&
3010                             mf->src_port == nf->src_port &&
3011                             mf->src_port_mask == nf->src_port_mask &&
3012                             mf->dst_port == nf->dst_port &&
3013                             mf->dst_port_mask == nf->dst_port_mask &&
3014                             mf->ip_protocol == nf->ip_protocol &&
3015                             mf->ip_addr_type == nf->ip_addr_type &&
3016                             mf->ethertype == nf->ethertype &&
3017                             mf->vni == nf->vni &&
3018                             mf->tunnel_type == nf->tunnel_type &&
3019                             mf->l2_ovlan == nf->l2_ovlan &&
3020                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3021                             mf->l2_ivlan == nf->l2_ivlan &&
3022                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3023                             !memcmp(mf->l2_addr, nf->l2_addr,
3024                                     RTE_ETHER_ADDR_LEN) &&
3025                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3026                                     RTE_ETHER_ADDR_LEN) &&
3027                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3028                                     RTE_ETHER_ADDR_LEN) &&
3029                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3030                                     RTE_ETHER_ADDR_LEN) &&
3031                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3032                                     sizeof(nf->src_ipaddr)) &&
3033                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3034                                     sizeof(nf->src_ipaddr_mask)) &&
3035                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3036                                     sizeof(nf->dst_ipaddr)) &&
3037                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3038                                     sizeof(nf->dst_ipaddr_mask))) {
3039                                 if (mvnic)
3040                                         *mvnic = vnic;
3041                                 return mf;
3042                         }
3043                 }
3044         }
3045         return NULL;
3046 }
3047
3048 static int
3049 bnxt_fdir_filter(struct rte_eth_dev *dev,
3050                  enum rte_filter_op filter_op,
3051                  void *arg)
3052 {
3053         struct bnxt *bp = dev->data->dev_private;
3054         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3055         struct bnxt_filter_info *filter, *match;
3056         struct bnxt_vnic_info *vnic, *mvnic;
3057         int ret = 0, i;
3058
3059         if (filter_op == RTE_ETH_FILTER_NOP)
3060                 return 0;
3061
3062         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3063                 return -EINVAL;
3064
3065         switch (filter_op) {
3066         case RTE_ETH_FILTER_ADD:
3067         case RTE_ETH_FILTER_DELETE:
3068                 /* FALLTHROUGH */
3069                 filter = bnxt_get_unused_filter(bp);
3070                 if (filter == NULL) {
3071                         PMD_DRV_LOG(ERR,
3072                                 "Not enough resources for a new flow.\n");
3073                         return -ENOMEM;
3074                 }
3075
3076                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3077                 if (ret != 0)
3078                         goto free_filter;
3079                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3080
3081                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3082                         vnic = &bp->vnic_info[0];
3083                 else
3084                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3085
3086                 match = bnxt_match_fdir(bp, filter, &mvnic);
3087                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3088                         if (match->dst_id == vnic->fw_vnic_id) {
3089                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3090                                 ret = -EEXIST;
3091                                 goto free_filter;
3092                         } else {
3093                                 match->dst_id = vnic->fw_vnic_id;
3094                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3095                                                                   match->dst_id,
3096                                                                   match);
3097                                 STAILQ_REMOVE(&mvnic->filter, match,
3098                                               bnxt_filter_info, next);
3099                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3100                                 PMD_DRV_LOG(ERR,
3101                                         "Filter with matching pattern exist\n");
3102                                 PMD_DRV_LOG(ERR,
3103                                         "Updated it to new destination q\n");
3104                                 goto free_filter;
3105                         }
3106                 }
3107                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3108                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3109                         ret = -ENOENT;
3110                         goto free_filter;
3111                 }
3112
3113                 if (filter_op == RTE_ETH_FILTER_ADD) {
3114                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3115                                                           filter->dst_id,
3116                                                           filter);
3117                         if (ret)
3118                                 goto free_filter;
3119                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3120                 } else {
3121                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3122                         STAILQ_REMOVE(&vnic->filter, match,
3123                                       bnxt_filter_info, next);
3124                         bnxt_free_filter(bp, match);
3125                         filter->fw_l2_filter_id = -1;
3126                         bnxt_free_filter(bp, filter);
3127                 }
3128                 break;
3129         case RTE_ETH_FILTER_FLUSH:
3130                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3131                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3132
3133                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3134                                 if (filter->filter_type ==
3135                                     HWRM_CFA_NTUPLE_FILTER) {
3136                                         ret =
3137                                         bnxt_hwrm_clear_ntuple_filter(bp,
3138                                                                       filter);
3139                                         STAILQ_REMOVE(&vnic->filter, filter,
3140                                                       bnxt_filter_info, next);
3141                                 }
3142                         }
3143                 }
3144                 return ret;
3145         case RTE_ETH_FILTER_UPDATE:
3146         case RTE_ETH_FILTER_STATS:
3147         case RTE_ETH_FILTER_INFO:
3148                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3149                 break;
3150         default:
3151                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3152                 ret = -EINVAL;
3153                 break;
3154         }
3155         return ret;
3156
3157 free_filter:
3158         filter->fw_l2_filter_id = -1;
3159         bnxt_free_filter(bp, filter);
3160         return ret;
3161 }
3162
3163 static int
3164 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3165                     enum rte_filter_type filter_type,
3166                     enum rte_filter_op filter_op, void *arg)
3167 {
3168         int ret = 0;
3169
3170         ret = is_bnxt_in_error(dev->data->dev_private);
3171         if (ret)
3172                 return ret;
3173
3174         switch (filter_type) {
3175         case RTE_ETH_FILTER_TUNNEL:
3176                 PMD_DRV_LOG(ERR,
3177                         "filter type: %d: To be implemented\n", filter_type);
3178                 break;
3179         case RTE_ETH_FILTER_FDIR:
3180                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3181                 break;
3182         case RTE_ETH_FILTER_NTUPLE:
3183                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3184                 break;
3185         case RTE_ETH_FILTER_ETHERTYPE:
3186                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3187                 break;
3188         case RTE_ETH_FILTER_GENERIC:
3189                 if (filter_op != RTE_ETH_FILTER_GET)
3190                         return -EINVAL;
3191                 *(const void **)arg = &bnxt_flow_ops;
3192                 break;
3193         default:
3194                 PMD_DRV_LOG(ERR,
3195                         "Filter type (%d) not supported", filter_type);
3196                 ret = -EINVAL;
3197                 break;
3198         }
3199         return ret;
3200 }
3201
3202 static const uint32_t *
3203 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3204 {
3205         static const uint32_t ptypes[] = {
3206                 RTE_PTYPE_L2_ETHER_VLAN,
3207                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3208                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3209                 RTE_PTYPE_L4_ICMP,
3210                 RTE_PTYPE_L4_TCP,
3211                 RTE_PTYPE_L4_UDP,
3212                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3213                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3214                 RTE_PTYPE_INNER_L4_ICMP,
3215                 RTE_PTYPE_INNER_L4_TCP,
3216                 RTE_PTYPE_INNER_L4_UDP,
3217                 RTE_PTYPE_UNKNOWN
3218         };
3219
3220         if (!dev->rx_pkt_burst)
3221                 return NULL;
3222
3223         return ptypes;
3224 }
3225
3226 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3227                          int reg_win)
3228 {
3229         uint32_t reg_base = *reg_arr & 0xfffff000;
3230         uint32_t win_off;
3231         int i;
3232
3233         for (i = 0; i < count; i++) {
3234                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3235                         return -ERANGE;
3236         }
3237         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3238         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3239         return 0;
3240 }
3241
3242 static int bnxt_map_ptp_regs(struct bnxt *bp)
3243 {
3244         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3245         uint32_t *reg_arr;
3246         int rc, i;
3247
3248         reg_arr = ptp->rx_regs;
3249         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3250         if (rc)
3251                 return rc;
3252
3253         reg_arr = ptp->tx_regs;
3254         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3255         if (rc)
3256                 return rc;
3257
3258         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3259                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3260
3261         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3262                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3263
3264         return 0;
3265 }
3266
3267 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3268 {
3269         rte_write32(0, (uint8_t *)bp->bar0 +
3270                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3271         rte_write32(0, (uint8_t *)bp->bar0 +
3272                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3273 }
3274
3275 static uint64_t bnxt_cc_read(struct bnxt *bp)
3276 {
3277         uint64_t ns;
3278
3279         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3280                               BNXT_GRCPF_REG_SYNC_TIME));
3281         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3282                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3283         return ns;
3284 }
3285
3286 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3287 {
3288         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3289         uint32_t fifo;
3290
3291         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3292                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3293         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3294                 return -EAGAIN;
3295
3296         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3297                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3298         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3299                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3300         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3301                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3302
3303         return 0;
3304 }
3305
3306 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3307 {
3308         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3309         struct bnxt_pf_info *pf = &bp->pf;
3310         uint16_t port_id;
3311         uint32_t fifo;
3312
3313         if (!ptp)
3314                 return -ENODEV;
3315
3316         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3317                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3318         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3319                 return -EAGAIN;
3320
3321         port_id = pf->port_id;
3322         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3323                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3324
3325         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3326                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3327         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3328 /*              bnxt_clr_rx_ts(bp);       TBD  */
3329                 return -EBUSY;
3330         }
3331
3332         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3333                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3334         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3335                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3336
3337         return 0;
3338 }
3339
3340 static int
3341 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3342 {
3343         uint64_t ns;
3344         struct bnxt *bp = dev->data->dev_private;
3345         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3346
3347         if (!ptp)
3348                 return 0;
3349
3350         ns = rte_timespec_to_ns(ts);
3351         /* Set the timecounters to a new value. */
3352         ptp->tc.nsec = ns;
3353
3354         return 0;
3355 }
3356
3357 static int
3358 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3359 {
3360         struct bnxt *bp = dev->data->dev_private;
3361         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3362         uint64_t ns, systime_cycles = 0;
3363         int rc = 0;
3364
3365         if (!ptp)
3366                 return 0;
3367
3368         if (BNXT_CHIP_THOR(bp))
3369                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3370                                              &systime_cycles);
3371         else
3372                 systime_cycles = bnxt_cc_read(bp);
3373
3374         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3375         *ts = rte_ns_to_timespec(ns);
3376
3377         return rc;
3378 }
3379 static int
3380 bnxt_timesync_enable(struct rte_eth_dev *dev)
3381 {
3382         struct bnxt *bp = dev->data->dev_private;
3383         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3384         uint32_t shift = 0;
3385         int rc;
3386
3387         if (!ptp)
3388                 return 0;
3389
3390         ptp->rx_filter = 1;
3391         ptp->tx_tstamp_en = 1;
3392         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3393
3394         rc = bnxt_hwrm_ptp_cfg(bp);
3395         if (rc)
3396                 return rc;
3397
3398         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3399         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3400         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3401
3402         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3403         ptp->tc.cc_shift = shift;
3404         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3405
3406         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3407         ptp->rx_tstamp_tc.cc_shift = shift;
3408         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3409
3410         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3411         ptp->tx_tstamp_tc.cc_shift = shift;
3412         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3413
3414         if (!BNXT_CHIP_THOR(bp))
3415                 bnxt_map_ptp_regs(bp);
3416
3417         return 0;
3418 }
3419
3420 static int
3421 bnxt_timesync_disable(struct rte_eth_dev *dev)
3422 {
3423         struct bnxt *bp = dev->data->dev_private;
3424         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3425
3426         if (!ptp)
3427                 return 0;
3428
3429         ptp->rx_filter = 0;
3430         ptp->tx_tstamp_en = 0;
3431         ptp->rxctl = 0;
3432
3433         bnxt_hwrm_ptp_cfg(bp);
3434
3435         if (!BNXT_CHIP_THOR(bp))
3436                 bnxt_unmap_ptp_regs(bp);
3437
3438         return 0;
3439 }
3440
3441 static int
3442 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3443                                  struct timespec *timestamp,
3444                                  uint32_t flags __rte_unused)
3445 {
3446         struct bnxt *bp = dev->data->dev_private;
3447         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3448         uint64_t rx_tstamp_cycles = 0;
3449         uint64_t ns;
3450
3451         if (!ptp)
3452                 return 0;
3453
3454         if (BNXT_CHIP_THOR(bp))
3455                 rx_tstamp_cycles = ptp->rx_timestamp;
3456         else
3457                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3458
3459         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3460         *timestamp = rte_ns_to_timespec(ns);
3461         return  0;
3462 }
3463
3464 static int
3465 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3466                                  struct timespec *timestamp)
3467 {
3468         struct bnxt *bp = dev->data->dev_private;
3469         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3470         uint64_t tx_tstamp_cycles = 0;
3471         uint64_t ns;
3472         int rc = 0;
3473
3474         if (!ptp)
3475                 return 0;
3476
3477         if (BNXT_CHIP_THOR(bp))
3478                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3479                                              &tx_tstamp_cycles);
3480         else
3481                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3482
3483         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3484         *timestamp = rte_ns_to_timespec(ns);
3485
3486         return rc;
3487 }
3488
3489 static int
3490 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3491 {
3492         struct bnxt *bp = dev->data->dev_private;
3493         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3494
3495         if (!ptp)
3496                 return 0;
3497
3498         ptp->tc.nsec += delta;
3499
3500         return 0;
3501 }
3502
3503 static int
3504 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3505 {
3506         struct bnxt *bp = dev->data->dev_private;
3507         int rc;
3508         uint32_t dir_entries;
3509         uint32_t entry_length;
3510
3511         rc = is_bnxt_in_error(bp);
3512         if (rc)
3513                 return rc;
3514
3515         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3516                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3517                 bp->pdev->addr.devid, bp->pdev->addr.function);
3518
3519         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3520         if (rc != 0)
3521                 return rc;
3522
3523         return dir_entries * entry_length;
3524 }
3525
3526 static int
3527 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3528                 struct rte_dev_eeprom_info *in_eeprom)
3529 {
3530         struct bnxt *bp = dev->data->dev_private;
3531         uint32_t index;
3532         uint32_t offset;
3533         int rc;
3534
3535         rc = is_bnxt_in_error(bp);
3536         if (rc)
3537                 return rc;
3538
3539         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3540                 "len = %d\n", bp->pdev->addr.domain,
3541                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3542                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3543
3544         if (in_eeprom->offset == 0) /* special offset value to get directory */
3545                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3546                                                 in_eeprom->data);
3547
3548         index = in_eeprom->offset >> 24;
3549         offset = in_eeprom->offset & 0xffffff;
3550
3551         if (index != 0)
3552                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3553                                            in_eeprom->length, in_eeprom->data);
3554
3555         return 0;
3556 }
3557
3558 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3559 {
3560         switch (dir_type) {
3561         case BNX_DIR_TYPE_CHIMP_PATCH:
3562         case BNX_DIR_TYPE_BOOTCODE:
3563         case BNX_DIR_TYPE_BOOTCODE_2:
3564         case BNX_DIR_TYPE_APE_FW:
3565         case BNX_DIR_TYPE_APE_PATCH:
3566         case BNX_DIR_TYPE_KONG_FW:
3567         case BNX_DIR_TYPE_KONG_PATCH:
3568         case BNX_DIR_TYPE_BONO_FW:
3569         case BNX_DIR_TYPE_BONO_PATCH:
3570                 /* FALLTHROUGH */
3571                 return true;
3572         }
3573
3574         return false;
3575 }
3576
3577 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3578 {
3579         switch (dir_type) {
3580         case BNX_DIR_TYPE_AVS:
3581         case BNX_DIR_TYPE_EXP_ROM_MBA:
3582         case BNX_DIR_TYPE_PCIE:
3583         case BNX_DIR_TYPE_TSCF_UCODE:
3584         case BNX_DIR_TYPE_EXT_PHY:
3585         case BNX_DIR_TYPE_CCM:
3586         case BNX_DIR_TYPE_ISCSI_BOOT:
3587         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3588         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3589                 /* FALLTHROUGH */
3590                 return true;
3591         }
3592
3593         return false;
3594 }
3595
3596 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3597 {
3598         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3599                 bnxt_dir_type_is_other_exec_format(dir_type);
3600 }
3601
3602 static int
3603 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3604                 struct rte_dev_eeprom_info *in_eeprom)
3605 {
3606         struct bnxt *bp = dev->data->dev_private;
3607         uint8_t index, dir_op;
3608         uint16_t type, ext, ordinal, attr;
3609         int rc;
3610
3611         rc = is_bnxt_in_error(bp);
3612         if (rc)
3613                 return rc;
3614
3615         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3616                 "len = %d\n", bp->pdev->addr.domain,
3617                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3618                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3619
3620         if (!BNXT_PF(bp)) {
3621                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3622                 return -EINVAL;
3623         }
3624
3625         type = in_eeprom->magic >> 16;
3626
3627         if (type == 0xffff) { /* special value for directory operations */
3628                 index = in_eeprom->magic & 0xff;
3629                 dir_op = in_eeprom->magic >> 8;
3630                 if (index == 0)
3631                         return -EINVAL;
3632                 switch (dir_op) {
3633                 case 0x0e: /* erase */
3634                         if (in_eeprom->offset != ~in_eeprom->magic)
3635                                 return -EINVAL;
3636                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3637                 default:
3638                         return -EINVAL;
3639                 }
3640         }
3641
3642         /* Create or re-write an NVM item: */
3643         if (bnxt_dir_type_is_executable(type) == true)
3644                 return -EOPNOTSUPP;
3645         ext = in_eeprom->magic & 0xffff;
3646         ordinal = in_eeprom->offset >> 16;
3647         attr = in_eeprom->offset & 0xffff;
3648
3649         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3650                                      in_eeprom->data, in_eeprom->length);
3651 }
3652
3653 /*
3654  * Initialization
3655  */
3656
3657 static const struct eth_dev_ops bnxt_dev_ops = {
3658         .dev_infos_get = bnxt_dev_info_get_op,
3659         .dev_close = bnxt_dev_close_op,
3660         .dev_configure = bnxt_dev_configure_op,
3661         .dev_start = bnxt_dev_start_op,
3662         .dev_stop = bnxt_dev_stop_op,
3663         .dev_set_link_up = bnxt_dev_set_link_up_op,
3664         .dev_set_link_down = bnxt_dev_set_link_down_op,
3665         .stats_get = bnxt_stats_get_op,
3666         .stats_reset = bnxt_stats_reset_op,
3667         .rx_queue_setup = bnxt_rx_queue_setup_op,
3668         .rx_queue_release = bnxt_rx_queue_release_op,
3669         .tx_queue_setup = bnxt_tx_queue_setup_op,
3670         .tx_queue_release = bnxt_tx_queue_release_op,
3671         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3672         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3673         .reta_update = bnxt_reta_update_op,
3674         .reta_query = bnxt_reta_query_op,
3675         .rss_hash_update = bnxt_rss_hash_update_op,
3676         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3677         .link_update = bnxt_link_update_op,
3678         .promiscuous_enable = bnxt_promiscuous_enable_op,
3679         .promiscuous_disable = bnxt_promiscuous_disable_op,
3680         .allmulticast_enable = bnxt_allmulticast_enable_op,
3681         .allmulticast_disable = bnxt_allmulticast_disable_op,
3682         .mac_addr_add = bnxt_mac_addr_add_op,
3683         .mac_addr_remove = bnxt_mac_addr_remove_op,
3684         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3685         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3686         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3687         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3688         .vlan_filter_set = bnxt_vlan_filter_set_op,
3689         .vlan_offload_set = bnxt_vlan_offload_set_op,
3690         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3691         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3692         .mtu_set = bnxt_mtu_set_op,
3693         .mac_addr_set = bnxt_set_default_mac_addr_op,
3694         .xstats_get = bnxt_dev_xstats_get_op,
3695         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3696         .xstats_reset = bnxt_dev_xstats_reset_op,
3697         .fw_version_get = bnxt_fw_version_get,
3698         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3699         .rxq_info_get = bnxt_rxq_info_get_op,
3700         .txq_info_get = bnxt_txq_info_get_op,
3701         .dev_led_on = bnxt_dev_led_on_op,
3702         .dev_led_off = bnxt_dev_led_off_op,
3703         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3704         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3705         .rx_queue_count = bnxt_rx_queue_count_op,
3706         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3707         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3708         .rx_queue_start = bnxt_rx_queue_start,
3709         .rx_queue_stop = bnxt_rx_queue_stop,
3710         .tx_queue_start = bnxt_tx_queue_start,
3711         .tx_queue_stop = bnxt_tx_queue_stop,
3712         .filter_ctrl = bnxt_filter_ctrl_op,
3713         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3714         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3715         .get_eeprom           = bnxt_get_eeprom_op,
3716         .set_eeprom           = bnxt_set_eeprom_op,
3717         .timesync_enable      = bnxt_timesync_enable,
3718         .timesync_disable     = bnxt_timesync_disable,
3719         .timesync_read_time   = bnxt_timesync_read_time,
3720         .timesync_write_time   = bnxt_timesync_write_time,
3721         .timesync_adjust_time = bnxt_timesync_adjust_time,
3722         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3723         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3724 };
3725
3726 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3727 {
3728         uint32_t offset;
3729
3730         /* Only pre-map the reset GRC registers using window 3 */
3731         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3732                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3733
3734         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3735
3736         return offset;
3737 }
3738
3739 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3740 {
3741         struct bnxt_error_recovery_info *info = bp->recovery_info;
3742         uint32_t reg_base = 0xffffffff;
3743         int i;
3744
3745         /* Only pre-map the monitoring GRC registers using window 2 */
3746         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3747                 uint32_t reg = info->status_regs[i];
3748
3749                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3750                         continue;
3751
3752                 if (reg_base == 0xffffffff)
3753                         reg_base = reg & 0xfffff000;
3754                 if ((reg & 0xfffff000) != reg_base)
3755                         return -ERANGE;
3756
3757                 /* Use mask 0xffc as the Lower 2 bits indicates
3758                  * address space location
3759                  */
3760                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3761                                                 (reg & 0xffc);
3762         }
3763
3764         if (reg_base == 0xffffffff)
3765                 return 0;
3766
3767         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3768                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3769
3770         return 0;
3771 }
3772
3773 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3774 {
3775         struct bnxt_error_recovery_info *info = bp->recovery_info;
3776         uint32_t delay = info->delay_after_reset[index];
3777         uint32_t val = info->reset_reg_val[index];
3778         uint32_t reg = info->reset_reg[index];
3779         uint32_t type, offset;
3780
3781         type = BNXT_FW_STATUS_REG_TYPE(reg);
3782         offset = BNXT_FW_STATUS_REG_OFF(reg);
3783
3784         switch (type) {
3785         case BNXT_FW_STATUS_REG_TYPE_CFG:
3786                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3787                 break;
3788         case BNXT_FW_STATUS_REG_TYPE_GRC:
3789                 offset = bnxt_map_reset_regs(bp, offset);
3790                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3791                 break;
3792         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3793                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3794                 break;
3795         }
3796         /* wait on a specific interval of time until core reset is complete */
3797         if (delay)
3798                 rte_delay_ms(delay);
3799 }
3800
3801 static void bnxt_dev_cleanup(struct bnxt *bp)
3802 {
3803         bnxt_set_hwrm_link_config(bp, false);
3804         bp->link_info.link_up = 0;
3805         if (bp->dev_stopped == 0)
3806                 bnxt_dev_stop_op(bp->eth_dev);
3807
3808         bnxt_uninit_resources(bp, true);
3809 }
3810
3811 static int bnxt_restore_filters(struct bnxt *bp)
3812 {
3813         struct rte_eth_dev *dev = bp->eth_dev;
3814         int ret = 0;
3815
3816         if (dev->data->all_multicast)
3817                 ret = bnxt_allmulticast_enable_op(dev);
3818         if (dev->data->promiscuous)
3819                 ret = bnxt_promiscuous_enable_op(dev);
3820
3821         /* TODO restore other filters as well */
3822         return ret;
3823 }
3824
3825 static void bnxt_dev_recover(void *arg)
3826 {
3827         struct bnxt *bp = arg;
3828         int timeout = bp->fw_reset_max_msecs;
3829         int rc = 0;
3830
3831         /* Clear Error flag so that device re-init should happen */
3832         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3833
3834         do {
3835                 rc = bnxt_hwrm_ver_get(bp);
3836                 if (rc == 0)
3837                         break;
3838                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3839                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3840         } while (rc && timeout);
3841
3842         if (rc) {
3843                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3844                 goto err;
3845         }
3846
3847         rc = bnxt_init_resources(bp, true);
3848         if (rc) {
3849                 PMD_DRV_LOG(ERR,
3850                             "Failed to initialize resources after reset\n");
3851                 goto err;
3852         }
3853         /* clear reset flag as the device is initialized now */
3854         bp->flags &= ~BNXT_FLAG_FW_RESET;
3855
3856         rc = bnxt_dev_start_op(bp->eth_dev);
3857         if (rc) {
3858                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3859                 goto err;
3860         }
3861
3862         rc = bnxt_restore_filters(bp);
3863         if (rc)
3864                 goto err;
3865
3866         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3867         return;
3868 err:
3869         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3870         bnxt_uninit_resources(bp, false);
3871         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3872 }
3873
3874 void bnxt_dev_reset_and_resume(void *arg)
3875 {
3876         struct bnxt *bp = arg;
3877         int rc;
3878
3879         bnxt_dev_cleanup(bp);
3880
3881         bnxt_wait_for_device_shutdown(bp);
3882
3883         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3884                                bnxt_dev_recover, (void *)bp);
3885         if (rc)
3886                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3887 }
3888
3889 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3890 {
3891         struct bnxt_error_recovery_info *info = bp->recovery_info;
3892         uint32_t reg = info->status_regs[index];
3893         uint32_t type, offset, val = 0;
3894
3895         type = BNXT_FW_STATUS_REG_TYPE(reg);
3896         offset = BNXT_FW_STATUS_REG_OFF(reg);
3897
3898         switch (type) {
3899         case BNXT_FW_STATUS_REG_TYPE_CFG:
3900                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3901                 break;
3902         case BNXT_FW_STATUS_REG_TYPE_GRC:
3903                 offset = info->mapped_status_regs[index];
3904                 /* FALLTHROUGH */
3905         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3906                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3907                                        offset));
3908                 break;
3909         }
3910
3911         return val;
3912 }
3913
3914 static int bnxt_fw_reset_all(struct bnxt *bp)
3915 {
3916         struct bnxt_error_recovery_info *info = bp->recovery_info;
3917         uint32_t i;
3918         int rc = 0;
3919
3920         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3921                 /* Reset through master function driver */
3922                 for (i = 0; i < info->reg_array_cnt; i++)
3923                         bnxt_write_fw_reset_reg(bp, i);
3924                 /* Wait for time specified by FW after triggering reset */
3925                 rte_delay_ms(info->master_func_wait_period_after_reset);
3926         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3927                 /* Reset with the help of Kong processor */
3928                 rc = bnxt_hwrm_fw_reset(bp);
3929                 if (rc)
3930                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3931         }
3932
3933         return rc;
3934 }
3935
3936 static void bnxt_fw_reset_cb(void *arg)
3937 {
3938         struct bnxt *bp = arg;
3939         struct bnxt_error_recovery_info *info = bp->recovery_info;
3940         int rc = 0;
3941
3942         /* Only Master function can do FW reset */
3943         if (bnxt_is_master_func(bp) &&
3944             bnxt_is_recovery_enabled(bp)) {
3945                 rc = bnxt_fw_reset_all(bp);
3946                 if (rc) {
3947                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3948                         return;
3949                 }
3950         }
3951
3952         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3953          * EXCEPTION_FATAL_ASYNC event to all the functions
3954          * (including MASTER FUNC). After receiving this Async, all the active
3955          * drivers should treat this case as FW initiated recovery
3956          */
3957         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3958                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3959                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3960
3961                 /* To recover from error */
3962                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3963                                   (void *)bp);
3964         }
3965 }
3966
3967 /* Driver should poll FW heartbeat, reset_counter with the frequency
3968  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3969  * When the driver detects heartbeat stop or change in reset_counter,
3970  * it has to trigger a reset to recover from the error condition.
3971  * A “master PF” is the function who will have the privilege to
3972  * initiate the chimp reset. The master PF will be elected by the
3973  * firmware and will be notified through async message.
3974  */
3975 static void bnxt_check_fw_health(void *arg)
3976 {
3977         struct bnxt *bp = arg;
3978         struct bnxt_error_recovery_info *info = bp->recovery_info;
3979         uint32_t val = 0, wait_msec;
3980
3981         if (!info || !bnxt_is_recovery_enabled(bp) ||
3982             is_bnxt_in_error(bp))
3983                 return;
3984
3985         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3986         if (val == info->last_heart_beat)
3987                 goto reset;
3988
3989         info->last_heart_beat = val;
3990
3991         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3992         if (val != info->last_reset_counter)
3993                 goto reset;
3994
3995         info->last_reset_counter = val;
3996
3997         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3998                           bnxt_check_fw_health, (void *)bp);
3999
4000         return;
4001 reset:
4002         /* Stop DMA to/from device */
4003         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4004         bp->flags |= BNXT_FLAG_FW_RESET;
4005
4006         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4007
4008         if (bnxt_is_master_func(bp))
4009                 wait_msec = info->master_func_wait_period;
4010         else
4011                 wait_msec = info->normal_func_wait_period;
4012
4013         rte_eal_alarm_set(US_PER_MS * wait_msec,
4014                           bnxt_fw_reset_cb, (void *)bp);
4015 }
4016
4017 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4018 {
4019         uint32_t polling_freq;
4020
4021         if (!bnxt_is_recovery_enabled(bp))
4022                 return;
4023
4024         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4025                 return;
4026
4027         polling_freq = bp->recovery_info->driver_polling_freq;
4028
4029         rte_eal_alarm_set(US_PER_MS * polling_freq,
4030                           bnxt_check_fw_health, (void *)bp);
4031         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4032 }
4033
4034 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4035 {
4036         if (!bnxt_is_recovery_enabled(bp))
4037                 return;
4038
4039         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4040         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4041 }
4042
4043 static bool bnxt_vf_pciid(uint16_t id)
4044 {
4045         if (id == BROADCOM_DEV_ID_57304_VF ||
4046             id == BROADCOM_DEV_ID_57406_VF ||
4047             id == BROADCOM_DEV_ID_5731X_VF ||
4048             id == BROADCOM_DEV_ID_5741X_VF ||
4049             id == BROADCOM_DEV_ID_57414_VF ||
4050             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4051             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4052             id == BROADCOM_DEV_ID_58802_VF ||
4053             id == BROADCOM_DEV_ID_57500_VF1 ||
4054             id == BROADCOM_DEV_ID_57500_VF2)
4055                 return true;
4056         return false;
4057 }
4058
4059 bool bnxt_stratus_device(struct bnxt *bp)
4060 {
4061         uint16_t id = bp->pdev->id.device_id;
4062
4063         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4064             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4065             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4066                 return true;
4067         return false;
4068 }
4069
4070 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4071 {
4072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4073         struct bnxt *bp = eth_dev->data->dev_private;
4074
4075         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4076         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4077         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4078         if (!bp->bar0 || !bp->doorbell_base) {
4079                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4080                 return -ENODEV;
4081         }
4082
4083         bp->eth_dev = eth_dev;
4084         bp->pdev = pci_dev;
4085
4086         return 0;
4087 }
4088
4089 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4090                                   struct bnxt_ctx_pg_info *ctx_pg,
4091                                   uint32_t mem_size,
4092                                   const char *suffix,
4093                                   uint16_t idx)
4094 {
4095         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4096         const struct rte_memzone *mz = NULL;
4097         char mz_name[RTE_MEMZONE_NAMESIZE];
4098         rte_iova_t mz_phys_addr;
4099         uint64_t valid_bits = 0;
4100         uint32_t sz;
4101         int i;
4102
4103         if (!mem_size)
4104                 return 0;
4105
4106         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4107                          BNXT_PAGE_SIZE;
4108         rmem->page_size = BNXT_PAGE_SIZE;
4109         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4110         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4111         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4112
4113         valid_bits = PTU_PTE_VALID;
4114
4115         if (rmem->nr_pages > 1) {
4116                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4117                          "bnxt_ctx_pg_tbl%s_%x_%d",
4118                          suffix, idx, bp->eth_dev->data->port_id);
4119                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4120                 mz = rte_memzone_lookup(mz_name);
4121                 if (!mz) {
4122                         mz = rte_memzone_reserve_aligned(mz_name,
4123                                                 rmem->nr_pages * 8,
4124                                                 SOCKET_ID_ANY,
4125                                                 RTE_MEMZONE_2MB |
4126                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4127                                                 RTE_MEMZONE_IOVA_CONTIG,
4128                                                 BNXT_PAGE_SIZE);
4129                         if (mz == NULL)
4130                                 return -ENOMEM;
4131                 }
4132
4133                 memset(mz->addr, 0, mz->len);
4134                 mz_phys_addr = mz->iova;
4135                 if ((unsigned long)mz->addr == mz_phys_addr) {
4136                         PMD_DRV_LOG(DEBUG,
4137                                     "physical address same as virtual\n");
4138                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4139                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4140                         if (mz_phys_addr == RTE_BAD_IOVA) {
4141                                 PMD_DRV_LOG(ERR,
4142                                         "unable to map addr to phys memory\n");
4143                                 return -ENOMEM;
4144                         }
4145                 }
4146                 rte_mem_lock_page(((char *)mz->addr));
4147
4148                 rmem->pg_tbl = mz->addr;
4149                 rmem->pg_tbl_map = mz_phys_addr;
4150                 rmem->pg_tbl_mz = mz;
4151         }
4152
4153         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4154                  suffix, idx, bp->eth_dev->data->port_id);
4155         mz = rte_memzone_lookup(mz_name);
4156         if (!mz) {
4157                 mz = rte_memzone_reserve_aligned(mz_name,
4158                                                  mem_size,
4159                                                  SOCKET_ID_ANY,
4160                                                  RTE_MEMZONE_1GB |
4161                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4162                                                  RTE_MEMZONE_IOVA_CONTIG,
4163                                                  BNXT_PAGE_SIZE);
4164                 if (mz == NULL)
4165                         return -ENOMEM;
4166         }
4167
4168         memset(mz->addr, 0, mz->len);
4169         mz_phys_addr = mz->iova;
4170         if ((unsigned long)mz->addr == mz_phys_addr) {
4171                 PMD_DRV_LOG(DEBUG,
4172                             "Memzone physical address same as virtual.\n");
4173                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4174                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4175                         rte_mem_lock_page(((char *)mz->addr) + sz);
4176                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4177                 if (mz_phys_addr == RTE_BAD_IOVA) {
4178                         PMD_DRV_LOG(ERR,
4179                                     "unable to map addr to phys memory\n");
4180                         return -ENOMEM;
4181                 }
4182         }
4183
4184         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4185                 rte_mem_lock_page(((char *)mz->addr) + sz);
4186                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4187                 rmem->dma_arr[i] = mz_phys_addr + sz;
4188
4189                 if (rmem->nr_pages > 1) {
4190                         if (i == rmem->nr_pages - 2 &&
4191                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4192                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4193                         else if (i == rmem->nr_pages - 1 &&
4194                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4195                                 valid_bits |= PTU_PTE_LAST;
4196
4197                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4198                                                            valid_bits);
4199                 }
4200         }
4201
4202         rmem->mz = mz;
4203         if (rmem->vmem_size)
4204                 rmem->vmem = (void **)mz->addr;
4205         rmem->dma_arr[0] = mz_phys_addr;
4206         return 0;
4207 }
4208
4209 static void bnxt_free_ctx_mem(struct bnxt *bp)
4210 {
4211         int i;
4212
4213         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4214                 return;
4215
4216         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4217         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4218         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4219         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4220         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4221         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4222         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4223         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4224         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4225         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4226         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4227
4228         for (i = 0; i < BNXT_MAX_Q; i++) {
4229                 if (bp->ctx->tqm_mem[i])
4230                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4231         }
4232
4233         rte_free(bp->ctx);
4234         bp->ctx = NULL;
4235 }
4236
4237 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4238
4239 #define min_t(type, x, y) ({                    \
4240         type __min1 = (x);                      \
4241         type __min2 = (y);                      \
4242         __min1 < __min2 ? __min1 : __min2; })
4243
4244 #define max_t(type, x, y) ({                    \
4245         type __max1 = (x);                      \
4246         type __max2 = (y);                      \
4247         __max1 > __max2 ? __max1 : __max2; })
4248
4249 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4250
4251 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4252 {
4253         struct bnxt_ctx_pg_info *ctx_pg;
4254         struct bnxt_ctx_mem_info *ctx;
4255         uint32_t mem_size, ena, entries;
4256         int i, rc;
4257
4258         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4259         if (rc) {
4260                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4261                 return rc;
4262         }
4263         ctx = bp->ctx;
4264         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4265                 return 0;
4266
4267         ctx_pg = &ctx->qp_mem;
4268         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4269         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4270         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4271         if (rc)
4272                 return rc;
4273
4274         ctx_pg = &ctx->srq_mem;
4275         ctx_pg->entries = ctx->srq_max_l2_entries;
4276         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4277         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4278         if (rc)
4279                 return rc;
4280
4281         ctx_pg = &ctx->cq_mem;
4282         ctx_pg->entries = ctx->cq_max_l2_entries;
4283         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4284         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4285         if (rc)
4286                 return rc;
4287
4288         ctx_pg = &ctx->vnic_mem;
4289         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4290                 ctx->vnic_max_ring_table_entries;
4291         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4292         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4293         if (rc)
4294                 return rc;
4295
4296         ctx_pg = &ctx->stat_mem;
4297         ctx_pg->entries = ctx->stat_max_entries;
4298         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4299         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4300         if (rc)
4301                 return rc;
4302
4303         entries = ctx->qp_max_l2_entries +
4304                   ctx->vnic_max_vnic_entries +
4305                   ctx->tqm_min_entries_per_ring;
4306         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4307         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4308                           ctx->tqm_max_entries_per_ring);
4309         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4310                 ctx_pg = ctx->tqm_mem[i];
4311                 /* use min tqm entries for now. */
4312                 ctx_pg->entries = entries;
4313                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4314                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4315                 if (rc)
4316                         return rc;
4317                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4318         }
4319
4320         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4321         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4322         if (rc)
4323                 PMD_DRV_LOG(ERR,
4324                             "Failed to configure context mem: rc = %d\n", rc);
4325         else
4326                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4327
4328         return rc;
4329 }
4330
4331 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4332 {
4333         struct rte_pci_device *pci_dev = bp->pdev;
4334         char mz_name[RTE_MEMZONE_NAMESIZE];
4335         const struct rte_memzone *mz = NULL;
4336         uint32_t total_alloc_len;
4337         rte_iova_t mz_phys_addr;
4338
4339         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4340                 return 0;
4341
4342         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4343                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4344                  pci_dev->addr.bus, pci_dev->addr.devid,
4345                  pci_dev->addr.function, "rx_port_stats");
4346         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4347         mz = rte_memzone_lookup(mz_name);
4348         total_alloc_len =
4349                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4350                                        sizeof(struct rx_port_stats_ext) + 512);
4351         if (!mz) {
4352                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4353                                          SOCKET_ID_ANY,
4354                                          RTE_MEMZONE_2MB |
4355                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4356                                          RTE_MEMZONE_IOVA_CONTIG);
4357                 if (mz == NULL)
4358                         return -ENOMEM;
4359         }
4360         memset(mz->addr, 0, mz->len);
4361         mz_phys_addr = mz->iova;
4362         if ((unsigned long)mz->addr == mz_phys_addr) {
4363                 PMD_DRV_LOG(DEBUG,
4364                             "Memzone physical address same as virtual.\n");
4365                 PMD_DRV_LOG(DEBUG,
4366                             "Using rte_mem_virt2iova()\n");
4367                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4368                 if (mz_phys_addr == RTE_BAD_IOVA) {
4369                         PMD_DRV_LOG(ERR,
4370                                     "Can't map address to physical memory\n");
4371                         return -ENOMEM;
4372                 }
4373         }
4374
4375         bp->rx_mem_zone = (const void *)mz;
4376         bp->hw_rx_port_stats = mz->addr;
4377         bp->hw_rx_port_stats_map = mz_phys_addr;
4378
4379         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4380                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4381                  pci_dev->addr.bus, pci_dev->addr.devid,
4382                  pci_dev->addr.function, "tx_port_stats");
4383         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4384         mz = rte_memzone_lookup(mz_name);
4385         total_alloc_len =
4386                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4387                                        sizeof(struct tx_port_stats_ext) + 512);
4388         if (!mz) {
4389                 mz = rte_memzone_reserve(mz_name,
4390                                          total_alloc_len,
4391                                          SOCKET_ID_ANY,
4392                                          RTE_MEMZONE_2MB |
4393                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4394                                          RTE_MEMZONE_IOVA_CONTIG);
4395                 if (mz == NULL)
4396                         return -ENOMEM;
4397         }
4398         memset(mz->addr, 0, mz->len);
4399         mz_phys_addr = mz->iova;
4400         if ((unsigned long)mz->addr == mz_phys_addr) {
4401                 PMD_DRV_LOG(DEBUG,
4402                             "Memzone physical address same as virtual\n");
4403                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4404                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4405                 if (mz_phys_addr == RTE_BAD_IOVA) {
4406                         PMD_DRV_LOG(ERR,
4407                                     "Can't map address to physical memory\n");
4408                         return -ENOMEM;
4409                 }
4410         }
4411
4412         bp->tx_mem_zone = (const void *)mz;
4413         bp->hw_tx_port_stats = mz->addr;
4414         bp->hw_tx_port_stats_map = mz_phys_addr;
4415         bp->flags |= BNXT_FLAG_PORT_STATS;
4416
4417         /* Display extended statistics if FW supports it */
4418         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4419             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4420             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4421                 return 0;
4422
4423         bp->hw_rx_port_stats_ext = (void *)
4424                 ((uint8_t *)bp->hw_rx_port_stats +
4425                  sizeof(struct rx_port_stats));
4426         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4427                 sizeof(struct rx_port_stats);
4428         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4429
4430         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4431             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4432                 bp->hw_tx_port_stats_ext = (void *)
4433                         ((uint8_t *)bp->hw_tx_port_stats +
4434                          sizeof(struct tx_port_stats));
4435                 bp->hw_tx_port_stats_ext_map =
4436                         bp->hw_tx_port_stats_map +
4437                         sizeof(struct tx_port_stats);
4438                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4439         }
4440
4441         return 0;
4442 }
4443
4444 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4445 {
4446         struct bnxt *bp = eth_dev->data->dev_private;
4447         int rc = 0;
4448
4449         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4450                                                RTE_ETHER_ADDR_LEN *
4451                                                bp->max_l2_ctx,
4452                                                0);
4453         if (eth_dev->data->mac_addrs == NULL) {
4454                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4455                 return -ENOMEM;
4456         }
4457
4458         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4459                 if (BNXT_PF(bp))
4460                         return -EINVAL;
4461
4462                 /* Generate a random MAC address, if none was assigned by PF */
4463                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4464                 bnxt_eth_hw_addr_random(bp->mac_addr);
4465                 PMD_DRV_LOG(INFO,
4466                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4467                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4468                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4469
4470                 rc = bnxt_hwrm_set_mac(bp);
4471                 if (!rc)
4472                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4473                                RTE_ETHER_ADDR_LEN);
4474                 return rc;
4475         }
4476
4477         /* Copy the permanent MAC from the FUNC_QCAPS response */
4478         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4479         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4480
4481         return rc;
4482 }
4483
4484 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4485 {
4486         int rc = 0;
4487
4488         /* MAC is already configured in FW */
4489         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4490                 return 0;
4491
4492         /* Restore the old MAC configured */
4493         rc = bnxt_hwrm_set_mac(bp);
4494         if (rc)
4495                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4496
4497         return rc;
4498 }
4499
4500 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4501 {
4502         if (!BNXT_PF(bp))
4503                 return;
4504
4505 #define ALLOW_FUNC(x)   \
4506         { \
4507                 uint32_t arg = (x); \
4508                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4509                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4510         }
4511
4512         /* Forward all requests if firmware is new enough */
4513         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4514              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4515             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4516                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4517         } else {
4518                 PMD_DRV_LOG(WARNING,
4519                             "Firmware too old for VF mailbox functionality\n");
4520                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4521         }
4522
4523         /*
4524          * The following are used for driver cleanup. If we disallow these,
4525          * VF drivers can't clean up cleanly.
4526          */
4527         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4528         ALLOW_FUNC(HWRM_VNIC_FREE);
4529         ALLOW_FUNC(HWRM_RING_FREE);
4530         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4531         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4532         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4533         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4534         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4535         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4536 }
4537
4538 static int bnxt_init_fw(struct bnxt *bp)
4539 {
4540         uint16_t mtu;
4541         int rc = 0;
4542
4543         rc = bnxt_hwrm_ver_get(bp);
4544         if (rc)
4545                 return rc;
4546
4547         rc = bnxt_hwrm_func_reset(bp);
4548         if (rc)
4549                 return -EIO;
4550
4551         rc = bnxt_hwrm_vnic_qcaps(bp);
4552         if (rc)
4553                 return rc;
4554
4555         rc = bnxt_hwrm_queue_qportcfg(bp);
4556         if (rc)
4557                 return rc;
4558
4559         /* Get the MAX capabilities for this function.
4560          * This function also allocates context memory for TQM rings and
4561          * informs the firmware about this allocated backing store memory.
4562          */
4563         rc = bnxt_hwrm_func_qcaps(bp);
4564         if (rc)
4565                 return rc;
4566
4567         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4568         if (rc)
4569                 return rc;
4570
4571         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4572         if (rc)
4573                 return rc;
4574
4575         /* Get the adapter error recovery support info */
4576         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4577         if (rc)
4578                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4579
4580         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4581             mtu != bp->eth_dev->data->mtu)
4582                 bp->eth_dev->data->mtu = mtu;
4583
4584         bnxt_hwrm_port_led_qcaps(bp);
4585
4586         return 0;
4587 }
4588
4589 static int
4590 bnxt_init_locks(struct bnxt *bp)
4591 {
4592         int err;
4593
4594         err = pthread_mutex_init(&bp->flow_lock, NULL);
4595         if (err) {
4596                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4597                 return err;
4598         }
4599
4600         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4601         if (err)
4602                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4603         return err;
4604 }
4605
4606 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4607 {
4608         int rc;
4609
4610         rc = bnxt_init_fw(bp);
4611         if (rc)
4612                 return rc;
4613
4614         if (!reconfig_dev) {
4615                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4616                 if (rc)
4617                         return rc;
4618         } else {
4619                 rc = bnxt_restore_dflt_mac(bp);
4620                 if (rc)
4621                         return rc;
4622         }
4623
4624         bnxt_config_vf_req_fwd(bp);
4625
4626         rc = bnxt_hwrm_func_driver_register(bp);
4627         if (rc) {
4628                 PMD_DRV_LOG(ERR, "Failed to register driver");
4629                 return -EBUSY;
4630         }
4631
4632         if (BNXT_PF(bp)) {
4633                 if (bp->pdev->max_vfs) {
4634                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4635                         if (rc) {
4636                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4637                                 return rc;
4638                         }
4639                 } else {
4640                         rc = bnxt_hwrm_allocate_pf_only(bp);
4641                         if (rc) {
4642                                 PMD_DRV_LOG(ERR,
4643                                             "Failed to allocate PF resources");
4644                                 return rc;
4645                         }
4646                 }
4647         }
4648
4649         rc = bnxt_alloc_mem(bp, reconfig_dev);
4650         if (rc)
4651                 return rc;
4652
4653         rc = bnxt_setup_int(bp);
4654         if (rc)
4655                 return rc;
4656
4657         bnxt_init_nic(bp);
4658
4659         rc = bnxt_request_int(bp);
4660         if (rc)
4661                 return rc;
4662
4663         rc = bnxt_init_locks(bp);
4664         if (rc)
4665                 return rc;
4666
4667         return 0;
4668 }
4669
4670 static int
4671 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4672 {
4673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4674         static int version_printed;
4675         struct bnxt *bp;
4676         int rc;
4677
4678         if (version_printed++ == 0)
4679                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4680
4681         eth_dev->dev_ops = &bnxt_dev_ops;
4682         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4683         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4684
4685         /*
4686          * For secondary processes, we don't initialise any further
4687          * as primary has already done this work.
4688          */
4689         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4690                 return 0;
4691
4692         rte_eth_copy_pci_info(eth_dev, pci_dev);
4693
4694         bp = eth_dev->data->dev_private;
4695
4696         bp->dev_stopped = 1;
4697
4698         if (bnxt_vf_pciid(pci_dev->id.device_id))
4699                 bp->flags |= BNXT_FLAG_VF;
4700
4701         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4702             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4703             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4704             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4705             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4706                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4707
4708         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4709             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4710             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4711             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4712                 bp->flags |= BNXT_FLAG_STINGRAY;
4713
4714         rc = bnxt_init_board(eth_dev);
4715         if (rc) {
4716                 PMD_DRV_LOG(ERR,
4717                             "Failed to initialize board rc: %x\n", rc);
4718                 return rc;
4719         }
4720
4721         rc = bnxt_alloc_hwrm_resources(bp);
4722         if (rc) {
4723                 PMD_DRV_LOG(ERR,
4724                             "Failed to allocate hwrm resource rc: %x\n", rc);
4725                 goto error_free;
4726         }
4727         rc = bnxt_init_resources(bp, false);
4728         if (rc)
4729                 goto error_free;
4730
4731         rc = bnxt_alloc_stats_mem(bp);
4732         if (rc)
4733                 goto error_free;
4734
4735         PMD_DRV_LOG(INFO,
4736                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4737                     pci_dev->mem_resource[0].phys_addr,
4738                     pci_dev->mem_resource[0].addr);
4739
4740         return 0;
4741
4742 error_free:
4743         bnxt_dev_uninit(eth_dev);
4744         return rc;
4745 }
4746
4747 static void
4748 bnxt_uninit_locks(struct bnxt *bp)
4749 {
4750         pthread_mutex_destroy(&bp->flow_lock);
4751         pthread_mutex_destroy(&bp->def_cp_lock);
4752 }
4753
4754 static int
4755 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4756 {
4757         int rc;
4758
4759         bnxt_free_int(bp);
4760         bnxt_free_mem(bp, reconfig_dev);
4761         bnxt_hwrm_func_buf_unrgtr(bp);
4762         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4763         bp->flags &= ~BNXT_FLAG_REGISTERED;
4764         bnxt_free_ctx_mem(bp);
4765         if (!reconfig_dev) {
4766                 bnxt_free_hwrm_resources(bp);
4767
4768                 if (bp->recovery_info != NULL) {
4769                         rte_free(bp->recovery_info);
4770                         bp->recovery_info = NULL;
4771                 }
4772         }
4773
4774         rte_free(bp->ptp_cfg);
4775         bp->ptp_cfg = NULL;
4776         return rc;
4777 }
4778
4779 static int
4780 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4781 {
4782         struct bnxt *bp = eth_dev->data->dev_private;
4783         int rc;
4784
4785         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4786                 return -EPERM;
4787
4788         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4789
4790         rc = bnxt_uninit_resources(bp, false);
4791
4792         if (bp->grp_info != NULL) {
4793                 rte_free(bp->grp_info);
4794                 bp->grp_info = NULL;
4795         }
4796
4797         if (bp->tx_mem_zone) {
4798                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4799                 bp->tx_mem_zone = NULL;
4800         }
4801
4802         if (bp->rx_mem_zone) {
4803                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4804                 bp->rx_mem_zone = NULL;
4805         }
4806
4807         if (bp->dev_stopped == 0)
4808                 bnxt_dev_close_op(eth_dev);
4809         if (bp->pf.vf_info)
4810                 rte_free(bp->pf.vf_info);
4811         eth_dev->dev_ops = NULL;
4812         eth_dev->rx_pkt_burst = NULL;
4813         eth_dev->tx_pkt_burst = NULL;
4814
4815         bnxt_uninit_locks(bp);
4816
4817         return rc;
4818 }
4819
4820 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4821         struct rte_pci_device *pci_dev)
4822 {
4823         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4824                 bnxt_dev_init);
4825 }
4826
4827 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4828 {
4829         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4830                 return rte_eth_dev_pci_generic_remove(pci_dev,
4831                                 bnxt_dev_uninit);
4832         else
4833                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4834 }
4835
4836 static struct rte_pci_driver bnxt_rte_pmd = {
4837         .id_table = bnxt_pci_id_map,
4838         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4839         .probe = bnxt_pci_probe,
4840         .remove = bnxt_pci_remove,
4841 };
4842
4843 static bool
4844 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4845 {
4846         if (strcmp(dev->device->driver->name, drv->driver.name))
4847                 return false;
4848
4849         return true;
4850 }
4851
4852 bool is_bnxt_supported(struct rte_eth_dev *dev)
4853 {
4854         return is_device_supported(dev, &bnxt_rte_pmd);
4855 }
4856
4857 RTE_INIT(bnxt_init_log)
4858 {
4859         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4860         if (bnxt_logtype_driver >= 0)
4861                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4862 }
4863
4864 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4865 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4866 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");