drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135
 136 int is_bnxt_in_error(struct bnxt *bp)
 137 {
 138         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 139                 return -EIO;
 140         if (bp->flags & BNXT_FLAG_FW_RESET)
 141                 return -EBUSY;
 142
 143         return 0;
 144 }
 145
 146 /***********************/
 147
 148 /*
 149  * High level utility functions
 150  */
 151
 152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 153 {
 154         if (!BNXT_CHIP_THOR(bp))
 155                 return 1;
 156
 157         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 158                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 159                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 160 }
 161
 162 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return HW_HASH_INDEX_SIZE;
 166
 167         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 168 }
 169
 170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 171 {
 172         bnxt_free_filter_mem(bp);
 173         bnxt_free_vnic_attributes(bp);
 174         bnxt_free_vnic_mem(bp);
 175
 176         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 177          * If the number of rings change across fw update,
 178          * we don't have much choice except to warn the user.
 179          */
 180         if (!reconfig) {
 181                 bnxt_free_stats(bp);
 182                 bnxt_free_tx_rings(bp);
 183                 bnxt_free_rx_rings(bp);
 184         }
 185         bnxt_free_async_cp_ring(bp);
 186         bnxt_free_rxtx_nq_ring(bp);
 187
 188         rte_free(bp->grp_info);
 189         bp->grp_info = NULL;
 190 }
 191
 192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 193 {
 194         int rc;
 195
 196         rc = bnxt_alloc_ring_grps(bp);
 197         if (rc)
 198                 goto alloc_mem_err;
 199
 200         rc = bnxt_alloc_async_ring_struct(bp);
 201         if (rc)
 202                 goto alloc_mem_err;
 203
 204         rc = bnxt_alloc_vnic_mem(bp);
 205         if (rc)
 206                 goto alloc_mem_err;
 207
 208         rc = bnxt_alloc_vnic_attributes(bp);
 209         if (rc)
 210                 goto alloc_mem_err;
 211
 212         rc = bnxt_alloc_filter_mem(bp);
 213         if (rc)
 214                 goto alloc_mem_err;
 215
 216         rc = bnxt_alloc_async_cp_ring(bp);
 217         if (rc)
 218                 goto alloc_mem_err;
 219
 220         rc = bnxt_alloc_rxtx_nq_ring(bp);
 221         if (rc)
 222                 goto alloc_mem_err;
 223
 224         return 0;
 225
 226 alloc_mem_err:
 227         bnxt_free_mem(bp, reconfig);
 228         return rc;
 229 }
 230
 231 static int bnxt_init_chip(struct bnxt *bp)
 232 {
 233         struct bnxt_rx_queue *rxq;
 234         struct rte_eth_link new;
 235         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 236         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 237         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 238         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 239         uint32_t intr_vector = 0;
 240         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 241         uint32_t vec = BNXT_MISC_VEC_ID;
 242         unsigned int i, j;
 243         int rc;
 244
 245         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 246                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 247                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 248                 bp->flags |= BNXT_FLAG_JUMBO;
 249         } else {
 250                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 251                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 252                 bp->flags &= ~BNXT_FLAG_JUMBO;
 253         }
 254
 255         /* THOR does not support ring groups.
 256          * But we will use the array to save RSS context IDs.
 257          */
 258         if (BNXT_CHIP_THOR(bp))
 259                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 260
 261         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 262         if (rc) {
 263                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 264                 goto err_out;
 265         }
 266
 267         rc = bnxt_alloc_hwrm_rings(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 280                 goto skip_cosq_cfg;
 281
 282         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 283                 if (bp->rx_cos_queue[i].id != 0xff) {
 284                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 285
 286                         if (!vnic) {
 287                                 PMD_DRV_LOG(ERR,
 288                                             "Num pools more than FW profile\n");
 289                                 rc = -EINVAL;
 290                                 goto err_out;
 291                         }
 292                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 293                         bp->rx_cosq_cnt++;
 294                 }
 295         }
 296
 297 skip_cosq_cfg:
 298         rc = bnxt_mq_rx_configure(bp);
 299         if (rc) {
 300                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 301                 goto err_out;
 302         }
 303
 304         /* VNIC configuration */
 305         for (i = 0; i < bp->nr_vnics; i++) {
 306                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 307                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 308
 309                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 310                 if (rc)
 311                         goto err_out;
 312
 313                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 314                             i, vnic, vnic->fw_grp_ids);
 315
 316                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 317                 if (rc) {
 318                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 319                                 i, rc);
 320                         goto err_out;
 321                 }
 322
 323                 /* Alloc RSS context only if RSS mode is enabled */
 324                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 325                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 326
 327                         rc = 0;
 328                         for (j = 0; j < nr_ctxs; j++) {
 329                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 330                                 if (rc)
 331                                         break;
 332                         }
 333                         if (rc) {
 334                                 PMD_DRV_LOG(ERR,
 335                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 336                                   i, j, rc);
 337                                 goto err_out;
 338                         }
 339                         vnic->num_lb_ctxts = nr_ctxs;
 340                 }
 341
 342                 /*
 343                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 344                  * setting is not available at this time, it will not be
 345                  * configured correctly in the CFA.
 346                  */
 347                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 348                         vnic->vlan_strip = true;
 349                 else
 350                         vnic->vlan_strip = false;
 351
 352                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 353                 if (rc) {
 354                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 355                                 i, rc);
 356                         goto err_out;
 357                 }
 358
 359                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 360                 if (rc) {
 361                         PMD_DRV_LOG(ERR,
 362                                 "HWRM vnic %d filter failure rc: %x\n",
 363                                 i, rc);
 364                         goto err_out;
 365                 }
 366
 367                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 368                         rxq = bp->eth_dev->data->rx_queues[j];
 369
 370                         PMD_DRV_LOG(DEBUG,
 371                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 372                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 373
 374                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 375                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 376                 }
 377
 378                 rc = bnxt_vnic_rss_configure(bp, vnic);
 379                 if (rc) {
 380                         PMD_DRV_LOG(ERR,
 381                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 382                         goto err_out;
 383                 }
 384
 385                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 386
 387                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 388                     DEV_RX_OFFLOAD_TCP_LRO)
 389                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 390                 else
 391                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 392         }
 393         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 394         if (rc) {
 395                 PMD_DRV_LOG(ERR,
 396                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 397                 goto err_out;
 398         }
 399
 400         /* check and configure queue intr-vector mapping */
 401         if ((rte_intr_cap_multiple(intr_handle) ||
 402              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 403             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 404                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 405                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 406                 if (intr_vector > bp->rx_cp_nr_rings) {
 407                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 408                                         bp->rx_cp_nr_rings);
 409                         return -ENOTSUP;
 410                 }
 411                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 412                 if (rc)
 413                         return rc;
 414         }
 415
 416         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 417                 intr_handle->intr_vec =
 418                         rte_zmalloc("intr_vec",
 419                                     bp->eth_dev->data->nb_rx_queues *
 420                                     sizeof(int), 0);
 421                 if (intr_handle->intr_vec == NULL) {
 422                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 423                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 424                         rc = -ENOMEM;
 425                         goto err_disable;
 426                 }
 427                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 428                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 429                          intr_handle->intr_vec, intr_handle->nb_efd,
 430                         intr_handle->max_intr);
 431                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 432                      queue_id++) {
 433                         intr_handle->intr_vec[queue_id] =
 434                                                         vec + BNXT_RX_VEC_START;
 435                         if (vec < base + intr_handle->nb_efd - 1)
 436                                 vec++;
 437                 }
 438         }
 439
 440         /* enable uio/vfio intr/eventfd mapping */
 441         rc = rte_intr_enable(intr_handle);
 442         if (rc)
 443                 goto err_free;
 444
 445         rc = bnxt_get_hwrm_link_config(bp, &new);
 446         if (rc) {
 447                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 448                 goto err_free;
 449         }
 450
 451         if (!bp->link_info.link_up) {
 452                 rc = bnxt_set_hwrm_link_config(bp, true);
 453                 if (rc) {
 454                         PMD_DRV_LOG(ERR,
 455                                 "HWRM link config failure rc: %x\n", rc);
 456                         goto err_free;
 457                 }
 458         }
 459         bnxt_print_link_info(bp->eth_dev);
 460
 461         return 0;
 462
 463 err_free:
 464         rte_free(intr_handle->intr_vec);
 465 err_disable:
 466         rte_intr_efd_disable(intr_handle);
 467 err_out:
 468         /* Some of the error status returned by FW may not be from errno.h */
 469         if (rc > 0)
 470                 rc = -EIO;
 471
 472         return rc;
 473 }
 474
 475 static int bnxt_shutdown_nic(struct bnxt *bp)
 476 {
 477         bnxt_free_all_hwrm_resources(bp);
 478         bnxt_free_all_filters(bp);
 479         bnxt_free_all_vnics(bp);
 480         return 0;
 481 }
 482
 483 /*
 484  * Device configuration and status function
 485  */
 486
 487 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 488                                 struct rte_eth_dev_info *dev_info)
 489 {
 490         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 491         struct bnxt *bp = eth_dev->data->dev_private;
 492         uint16_t max_vnics, i, j, vpool, vrxq;
 493         unsigned int max_rx_rings;
 494         int rc;
 495
 496         rc = is_bnxt_in_error(bp);
 497         if (rc)
 498                 return rc;
 499
 500         /* MAC Specifics */
 501         dev_info->max_mac_addrs = bp->max_l2_ctx;
 502         dev_info->max_hash_mac_addrs = 0;
 503
 504         /* PF/VF specifics */
 505         if (BNXT_PF(bp))
 506                 dev_info->max_vfs = pdev->max_vfs;
 507
 508         max_rx_rings = BNXT_MAX_RINGS(bp);
 509         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 510         dev_info->max_rx_queues = max_rx_rings;
 511         dev_info->max_tx_queues = max_rx_rings;
 512         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 513         dev_info->hash_key_size = 40;
 514         max_vnics = bp->max_vnics;
 515
 516         /* MTU specifics */
 517         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 518         dev_info->max_mtu = BNXT_MAX_MTU;
 519
 520         /* Fast path specifics */
 521         dev_info->min_rx_bufsize = 1;
 522         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 523
 524         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 525         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 526                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 527         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 528         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 529
 530         /* *INDENT-OFF* */
 531         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 532                 .rx_thresh = {
 533                         .pthresh = 8,
 534                         .hthresh = 8,
 535                         .wthresh = 0,
 536                 },
 537                 .rx_free_thresh = 32,
 538                 /* If no descriptors available, pkts are dropped by default */
 539                 .rx_drop_en = 1,
 540         };
 541
 542         dev_info->default_txconf = (struct rte_eth_txconf) {
 543                 .tx_thresh = {
 544                         .pthresh = 32,
 545                         .hthresh = 0,
 546                         .wthresh = 0,
 547                 },
 548                 .tx_free_thresh = 32,
 549                 .tx_rs_thresh = 32,
 550         };
 551         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 552
 553         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 554         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 555         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 556         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 557         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 558
 559         /* *INDENT-ON* */
 560
 561         /*
 562          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 563          *       need further investigation.
 564          */
 565
 566         /* VMDq resources */
 567         vpool = 64; /* ETH_64_POOLS */
 568         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 569         for (i = 0; i < 4; vpool >>= 1, i++) {
 570                 if (max_vnics > vpool) {
 571                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 572                                 if (dev_info->max_rx_queues > vrxq) {
 573                                         if (vpool > vrxq)
 574                                                 vpool = vrxq;
 575                                         goto found;
 576                                 }
 577                         }
 578                         /* Not enough resources to support VMDq */
 579                         break;
 580                 }
 581         }
 582         /* Not enough resources to support VMDq */
 583         vpool = 0;
 584         vrxq = 0;
 585 found:
 586         dev_info->max_vmdq_pools = vpool;
 587         dev_info->vmdq_queue_num = vrxq;
 588
 589         dev_info->vmdq_pool_base = 0;
 590         dev_info->vmdq_queue_base = 0;
 591
 592         return 0;
 593 }
 594
 595 /* Configure the device based on the configuration provided */
 596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 597 {
 598         struct bnxt *bp = eth_dev->data->dev_private;
 599         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 600         int rc;
 601
 602         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 603         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 604         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 605         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 606
 607         rc = is_bnxt_in_error(bp);
 608         if (rc)
 609                 return rc;
 610
 611         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 612                 rc = bnxt_hwrm_check_vf_rings(bp);
 613                 if (rc) {
 614                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 615                         return -ENOSPC;
 616                 }
 617
 618                 /* If a resource has already been allocated - in this case
 619                  * it is the async completion ring, free it. Reallocate it after
 620                  * resource reservation. This will ensure the resource counts
 621                  * are calculated correctly.
 622                  */
 623
 624                 pthread_mutex_lock(&bp->def_cp_lock);
 625
 626                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 627                         bnxt_disable_int(bp);
 628                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 629                 }
 630
 631                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 632                 if (rc) {
 633                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 634                         pthread_mutex_unlock(&bp->def_cp_lock);
 635                         return -ENOSPC;
 636                 }
 637
 638                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 639                         rc = bnxt_alloc_async_cp_ring(bp);
 640                         if (rc) {
 641                                 pthread_mutex_unlock(&bp->def_cp_lock);
 642                                 return rc;
 643                         }
 644                         bnxt_enable_int(bp);
 645                 }
 646
 647                 pthread_mutex_unlock(&bp->def_cp_lock);
 648         } else {
 649                 /* legacy driver needs to get updated values */
 650                 rc = bnxt_hwrm_func_qcaps(bp);
 651                 if (rc) {
 652                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 653                         return rc;
 654                 }
 655         }
 656
 657         /* Inherit new configurations */
 658         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 659             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 660             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 661                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 662             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 663             bp->max_stat_ctx)
 664                 goto resource_error;
 665
 666         if (BNXT_HAS_RING_GRPS(bp) &&
 667             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 668                 goto resource_error;
 669
 670         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 671             bp->max_vnics < eth_dev->data->nb_rx_queues)
 672                 goto resource_error;
 673
 674         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 675         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 676
 677         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 678                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 679         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 729                 return 1;
 730
 731         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 732                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 733
 734                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 735                                       RTE_PKTMBUF_HEADROOM);
 736                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 737                         return 1;
 738         }
 739         return 0;
 740 }
 741
 742 static eth_rx_burst_t
 743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 744 {
 745 #ifdef RTE_ARCH_X86
 746 #ifndef RTE_LIBRTE_IEEE1588
 747         /*
 748          * Vector mode receive can be enabled only if scatter rx is not
 749          * in use and rx offloads are limited to VLAN stripping and
 750          * CRC stripping.
 751          */
 752         if (!eth_dev->data->scattered_rx &&
 753             !(eth_dev->data->dev_conf.rxmode.offloads &
 754               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 755                 DEV_RX_OFFLOAD_KEEP_CRC |
 756                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 757                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_UDP_CKSUM |
 759                 DEV_RX_OFFLOAD_TCP_CKSUM |
 760                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_RSS_HASH |
 762                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 763                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 764                             eth_dev->data->port_id);
 765                 return bnxt_recv_pkts_vec;
 766         }
 767         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 768                     eth_dev->data->port_id);
 769         PMD_DRV_LOG(INFO,
 770                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 771                     eth_dev->data->port_id,
 772                     eth_dev->data->scattered_rx,
 773                     eth_dev->data->dev_conf.rxmode.offloads);
 774 #endif
 775 #endif
 776         return bnxt_recv_pkts;
 777 }
 778
 779 static eth_tx_burst_t
 780 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 781 {
 782 #ifdef RTE_ARCH_X86
 783 #ifndef RTE_LIBRTE_IEEE1588
 784         /*
 785          * Vector mode transmit can be enabled only if not using scatter rx
 786          * or tx offloads.
 787          */
 788         if (!eth_dev->data->scattered_rx &&
 789             !eth_dev->data->dev_conf.txmode.offloads) {
 790                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 791                             eth_dev->data->port_id);
 792                 return bnxt_xmit_pkts_vec;
 793         }
 794         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 795                     eth_dev->data->port_id);
 796         PMD_DRV_LOG(INFO,
 797                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 798                     eth_dev->data->port_id,
 799                     eth_dev->data->scattered_rx,
 800                     eth_dev->data->dev_conf.txmode.offloads);
 801 #endif
 802 #endif
 803         return bnxt_xmit_pkts;
 804 }
 805
 806 static int bnxt_handle_if_change_status(struct bnxt *bp)
 807 {
 808         int rc;
 809
 810         /* Since fw has undergone a reset and lost all contexts,
 811          * set fatal flag to not issue hwrm during cleanup
 812          */
 813         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 814         bnxt_uninit_resources(bp, true);
 815
 816         /* clear fatal flag so that re-init happens */
 817         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 818         rc = bnxt_init_resources(bp, true);
 819
 820         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 821
 822         return rc;
 823 }
 824
 825 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 826 {
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 829         int vlan_mask = 0;
 830         int rc;
 831
 832         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 833                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 834                 return -EINVAL;
 835         }
 836
 837         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 838                 PMD_DRV_LOG(ERR,
 839                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 840                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 841         }
 842
 843         rc = bnxt_hwrm_if_change(bp, 1);
 844         if (!rc) {
 845                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 846                         rc = bnxt_handle_if_change_status(bp);
 847                         if (rc)
 848                                 return rc;
 849                 }
 850         }
 851         bnxt_enable_int(bp);
 852
 853         rc = bnxt_init_chip(bp);
 854         if (rc)
 855                 goto error;
 856
 857         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 858
 859         bnxt_link_update_op(eth_dev, 1);
 860
 861         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 862                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 863         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 864                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 865         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 866         if (rc)
 867                 goto error;
 868
 869         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 870         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 871
 872         bp->flags |= BNXT_FLAG_INIT_DONE;
 873         eth_dev->data->dev_started = 1;
 874         bp->dev_stopped = 0;
 875         pthread_mutex_lock(&bp->def_cp_lock);
 876         bnxt_schedule_fw_health_check(bp);
 877         pthread_mutex_unlock(&bp->def_cp_lock);
 878         return 0;
 879
 880 error:
 881         bnxt_hwrm_if_change(bp, 0);
 882         bnxt_shutdown_nic(bp);
 883         bnxt_free_tx_mbufs(bp);
 884         bnxt_free_rx_mbufs(bp);
 885         return rc;
 886 }
 887
 888 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 889 {
 890         struct bnxt *bp = eth_dev->data->dev_private;
 891         int rc = 0;
 892
 893         if (!bp->link_info.link_up)
 894                 rc = bnxt_set_hwrm_link_config(bp, true);
 895         if (!rc)
 896                 eth_dev->data->dev_link.link_status = 1;
 897
 898         bnxt_print_link_info(eth_dev);
 899         return rc;
 900 }
 901
 902 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 903 {
 904         struct bnxt *bp = eth_dev->data->dev_private;
 905
 906         eth_dev->data->dev_link.link_status = 0;
 907         bnxt_set_hwrm_link_config(bp, false);
 908         bp->link_info.link_up = 0;
 909
 910         return 0;
 911 }
 912
 913 /* Unload the driver, release resources */
 914 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 915 {
 916         struct bnxt *bp = eth_dev->data->dev_private;
 917         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 918         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 919
 920         eth_dev->data->dev_started = 0;
 921         /* Prevent crashes when queues are still in use */
 922         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 923         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 924
 925         bnxt_disable_int(bp);
 926
 927         /* disable uio/vfio intr/eventfd mapping */
 928         rte_intr_disable(intr_handle);
 929
 930         bnxt_cancel_fw_health_check(bp);
 931
 932         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 933         if (bp->eth_dev->data->dev_started) {
 934                 /* TBD: STOP HW queues DMA */
 935                 eth_dev->data->dev_link.link_status = 0;
 936         }
 937         bnxt_dev_set_link_down_op(eth_dev);
 938
 939         /* Wait for link to be reset and the async notification to process.
 940          * During reset recovery, there is no need to wait
 941          */
 942         if (!is_bnxt_in_error(bp))
 943                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 944
 945         /* Clean queue intr-vector mapping */
 946         rte_intr_efd_disable(intr_handle);
 947         if (intr_handle->intr_vec != NULL) {
 948                 rte_free(intr_handle->intr_vec);
 949                 intr_handle->intr_vec = NULL;
 950         }
 951
 952         bnxt_hwrm_port_clr_stats(bp);
 953         bnxt_free_tx_mbufs(bp);
 954         bnxt_free_rx_mbufs(bp);
 955         /* Process any remaining notifications in default completion queue */
 956         bnxt_int_handler(eth_dev);
 957         bnxt_shutdown_nic(bp);
 958         bnxt_hwrm_if_change(bp, 0);
 959         bp->dev_stopped = 1;
 960         bp->rx_cosq_cnt = 0;
 961 }
 962
 963 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 964 {
 965         struct bnxt *bp = eth_dev->data->dev_private;
 966
 967         if (bp->dev_stopped == 0)
 968                 bnxt_dev_stop_op(eth_dev);
 969
 970         if (eth_dev->data->mac_addrs != NULL) {
 971                 rte_free(eth_dev->data->mac_addrs);
 972                 eth_dev->data->mac_addrs = NULL;
 973         }
 974         if (bp->grp_info != NULL) {
 975                 rte_free(bp->grp_info);
 976                 bp->grp_info = NULL;
 977         }
 978
 979         bnxt_dev_uninit(eth_dev);
 980 }
 981
 982 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 983                                     uint32_t index)
 984 {
 985         struct bnxt *bp = eth_dev->data->dev_private;
 986         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 987         struct bnxt_vnic_info *vnic;
 988         struct bnxt_filter_info *filter, *temp_filter;
 989         uint32_t i;
 990
 991         if (is_bnxt_in_error(bp))
 992                 return;
 993
 994         /*
 995          * Loop through all VNICs from the specified filter flow pools to
 996          * remove the corresponding MAC addr filter
 997          */
 998         for (i = 0; i < bp->nr_vnics; i++) {
 999                 if (!(pool_mask & (1ULL << i)))
1000                         continue;
1001
1002                 vnic = &bp->vnic_info[i];
1003                 filter = STAILQ_FIRST(&vnic->filter);
1004                 while (filter) {
1005                         temp_filter = STAILQ_NEXT(filter, next);
1006                         if (filter->mac_index == index) {
1007                                 STAILQ_REMOVE(&vnic->filter, filter,
1008                                                 bnxt_filter_info, next);
1009                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1010                                 bnxt_free_filter(bp, filter);
1011                         }
1012                         filter = temp_filter;
1013                 }
1014         }
1015 }
1016
1017 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1018                                struct rte_ether_addr *mac_addr, uint32_t index,
1019                                uint32_t pool)
1020 {
1021         struct bnxt_filter_info *filter;
1022         int rc = 0;
1023
1024         /* Attach requested MAC address to the new l2_filter */
1025         STAILQ_FOREACH(filter, &vnic->filter, next) {
1026                 if (filter->mac_index == index) {
1027                         PMD_DRV_LOG(DEBUG,
1028                                     "MAC addr already existed for pool %d\n",
1029                                     pool);
1030                         return 0;
1031                 }
1032         }
1033
1034         filter = bnxt_alloc_filter(bp);
1035         if (!filter) {
1036                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1037                 return -ENODEV;
1038         }
1039
1040         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1041          * if the MAC that's been programmed now is a different one, then,
1042          * copy that addr to filter->l2_addr
1043          */
1044         if (mac_addr)
1045                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1046         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1047
1048         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1049         if (!rc) {
1050                 filter->mac_index = index;
1051                 if (filter->mac_index == 0)
1052                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1053                 else
1054                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1055         } else {
1056                 bnxt_free_filter(bp, filter);
1057         }
1058
1059         return rc;
1060 }
1061
1062 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1063                                 struct rte_ether_addr *mac_addr,
1064                                 uint32_t index, uint32_t pool)
1065 {
1066         struct bnxt *bp = eth_dev->data->dev_private;
1067         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1068         int rc = 0;
1069
1070         rc = is_bnxt_in_error(bp);
1071         if (rc)
1072                 return rc;
1073
1074         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1075                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1076                 return -ENOTSUP;
1077         }
1078
1079         if (!vnic) {
1080                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1081                 return -EINVAL;
1082         }
1083
1084         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1085
1086         return rc;
1087 }
1088
1089 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1090 {
1091         int rc = 0;
1092         struct bnxt *bp = eth_dev->data->dev_private;
1093         struct rte_eth_link new;
1094         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1095
1096         rc = is_bnxt_in_error(bp);
1097         if (rc)
1098                 return rc;
1099
1100         memset(&new, 0, sizeof(new));
1101         do {
1102                 /* Retrieve link info from hardware */
1103                 rc = bnxt_get_hwrm_link_config(bp, &new);
1104                 if (rc) {
1105                         new.link_speed = ETH_LINK_SPEED_100M;
1106                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1107                         PMD_DRV_LOG(ERR,
1108                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1109                         goto out;
1110                 }
1111
1112                 if (!wait_to_complete || new.link_status)
1113                         break;
1114
1115                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1116         } while (cnt--);
1117
1118 out:
1119         /* Timed out or success */
1120         if (new.link_status != eth_dev->data->dev_link.link_status ||
1121         new.link_speed != eth_dev->data->dev_link.link_speed) {
1122                 rte_eth_linkstatus_set(eth_dev, &new);
1123
1124                 _rte_eth_dev_callback_process(eth_dev,
1125                                               RTE_ETH_EVENT_INTR_LSC,
1126                                               NULL);
1127
1128                 bnxt_print_link_info(eth_dev);
1129         }
1130
1131         return rc;
1132 }
1133
1134 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1135 {
1136         struct bnxt *bp = eth_dev->data->dev_private;
1137         struct bnxt_vnic_info *vnic;
1138         uint32_t old_flags;
1139         int rc;
1140
1141         rc = is_bnxt_in_error(bp);
1142         if (rc)
1143                 return rc;
1144
1145         if (bp->vnic_info == NULL)
1146                 return 0;
1147
1148         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1149
1150         old_flags = vnic->flags;
1151         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1152         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1153         if (rc != 0)
1154                 vnic->flags = old_flags;
1155
1156         return rc;
1157 }
1158
1159 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1160 {
1161         struct bnxt *bp = eth_dev->data->dev_private;
1162         struct bnxt_vnic_info *vnic;
1163         uint32_t old_flags;
1164         int rc;
1165
1166         rc = is_bnxt_in_error(bp);
1167         if (rc)
1168                 return rc;
1169
1170         if (bp->vnic_info == NULL)
1171                 return 0;
1172
1173         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1174
1175         old_flags = vnic->flags;
1176         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1177         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1178         if (rc != 0)
1179                 vnic->flags = old_flags;
1180
1181         return rc;
1182 }
1183
1184 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1185 {
1186         struct bnxt *bp = eth_dev->data->dev_private;
1187         struct bnxt_vnic_info *vnic;
1188         uint32_t old_flags;
1189         int rc;
1190
1191         rc = is_bnxt_in_error(bp);
1192         if (rc)
1193                 return rc;
1194
1195         if (bp->vnic_info == NULL)
1196                 return 0;
1197
1198         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1199
1200         old_flags = vnic->flags;
1201         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1202         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1203         if (rc != 0)
1204                 vnic->flags = old_flags;
1205
1206         return rc;
1207 }
1208
1209 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1210 {
1211         struct bnxt *bp = eth_dev->data->dev_private;
1212         struct bnxt_vnic_info *vnic;
1213         uint32_t old_flags;
1214         int rc;
1215
1216         rc = is_bnxt_in_error(bp);
1217         if (rc)
1218                 return rc;
1219
1220         if (bp->vnic_info == NULL)
1221                 return 0;
1222
1223         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1224
1225         old_flags = vnic->flags;
1226         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1227         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1228         if (rc != 0)
1229                 vnic->flags = old_flags;
1230
1231         return rc;
1232 }
1233
1234 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1235 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1236 {
1237         if (qid >= bp->rx_nr_rings)
1238                 return NULL;
1239
1240         return bp->eth_dev->data->rx_queues[qid];
1241 }
1242
1243 /* Return rxq corresponding to a given rss table ring/group ID. */
1244 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1245 {
1246         struct bnxt_rx_queue *rxq;
1247         unsigned int i;
1248
1249         if (!BNXT_HAS_RING_GRPS(bp)) {
1250                 for (i = 0; i < bp->rx_nr_rings; i++) {
1251                         rxq = bp->eth_dev->data->rx_queues[i];
1252                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1253                                 return rxq->index;
1254                 }
1255         } else {
1256                 for (i = 0; i < bp->rx_nr_rings; i++) {
1257                         if (bp->grp_info[i].fw_grp_id == fwr)
1258                                 return i;
1259                 }
1260         }
1261
1262         return INVALID_HW_RING_ID;
1263 }
1264
1265 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1266                             struct rte_eth_rss_reta_entry64 *reta_conf,
1267                             uint16_t reta_size)
1268 {
1269         struct bnxt *bp = eth_dev->data->dev_private;
1270         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1271         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1272         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1273         uint16_t idx, sft;
1274         int i, rc;
1275
1276         rc = is_bnxt_in_error(bp);
1277         if (rc)
1278                 return rc;
1279
1280         if (!vnic->rss_table)
1281                 return -EINVAL;
1282
1283         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1284                 return -EINVAL;
1285
1286         if (reta_size != tbl_size) {
1287                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1288                         "(%d) must equal the size supported by the hardware "
1289                         "(%d)\n", reta_size, tbl_size);
1290                 return -EINVAL;
1291         }
1292
1293         for (i = 0; i < reta_size; i++) {
1294                 struct bnxt_rx_queue *rxq;
1295
1296                 idx = i / RTE_RETA_GROUP_SIZE;
1297                 sft = i % RTE_RETA_GROUP_SIZE;
1298
1299                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1300                         continue;
1301
1302                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1303                 if (!rxq) {
1304                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1305                         return -EINVAL;
1306                 }
1307
1308                 if (BNXT_CHIP_THOR(bp)) {
1309                         vnic->rss_table[i * 2] =
1310                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1311                         vnic->rss_table[i * 2 + 1] =
1312                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1313                 } else {
1314                         vnic->rss_table[i] =
1315                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1316                 }
1317         }
1318
1319         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1320         return 0;
1321 }
1322
1323 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1324                               struct rte_eth_rss_reta_entry64 *reta_conf,
1325                               uint16_t reta_size)
1326 {
1327         struct bnxt *bp = eth_dev->data->dev_private;
1328         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1329         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1330         uint16_t idx, sft, i;
1331         int rc;
1332
1333         rc = is_bnxt_in_error(bp);
1334         if (rc)
1335                 return rc;
1336
1337         /* Retrieve from the default VNIC */
1338         if (!vnic)
1339                 return -EINVAL;
1340         if (!vnic->rss_table)
1341                 return -EINVAL;
1342
1343         if (reta_size != tbl_size) {
1344                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1345                         "(%d) must equal the size supported by the hardware "
1346                         "(%d)\n", reta_size, tbl_size);
1347                 return -EINVAL;
1348         }
1349
1350         for (idx = 0, i = 0; i < reta_size; i++) {
1351                 idx = i / RTE_RETA_GROUP_SIZE;
1352                 sft = i % RTE_RETA_GROUP_SIZE;
1353
1354                 if (reta_conf[idx].mask & (1ULL << sft)) {
1355                         uint16_t qid;
1356
1357                         if (BNXT_CHIP_THOR(bp))
1358                                 qid = bnxt_rss_to_qid(bp,
1359                                                       vnic->rss_table[i * 2]);
1360                         else
1361                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1362
1363                         if (qid == INVALID_HW_RING_ID) {
1364                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1365                                 return -EINVAL;
1366                         }
1367                         reta_conf[idx].reta[sft] = qid;
1368                 }
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1375                                    struct rte_eth_rss_conf *rss_conf)
1376 {
1377         struct bnxt *bp = eth_dev->data->dev_private;
1378         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1379         struct bnxt_vnic_info *vnic;
1380         int rc;
1381
1382         rc = is_bnxt_in_error(bp);
1383         if (rc)
1384                 return rc;
1385
1386         /*
1387          * If RSS enablement were different than dev_configure,
1388          * then return -EINVAL
1389          */
1390         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1391                 if (!rss_conf->rss_hf)
1392                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1393         } else {
1394                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1395                         return -EINVAL;
1396         }
1397
1398         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1399         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1400
1401         /* Update the default RSS VNIC(s) */
1402         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1403         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1404
1405         /*
1406          * If hashkey is not specified, use the previously configured
1407          * hashkey
1408          */
1409         if (!rss_conf->rss_key)
1410                 goto rss_config;
1411
1412         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1413                 PMD_DRV_LOG(ERR,
1414                             "Invalid hashkey length, should be 16 bytes\n");
1415                 return -EINVAL;
1416         }
1417         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1418
1419 rss_config:
1420         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1421         return 0;
1422 }
1423
1424 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1425                                      struct rte_eth_rss_conf *rss_conf)
1426 {
1427         struct bnxt *bp = eth_dev->data->dev_private;
1428         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1429         int len, rc;
1430         uint32_t hash_types;
1431
1432         rc = is_bnxt_in_error(bp);
1433         if (rc)
1434                 return rc;
1435
1436         /* RSS configuration is the same for all VNICs */
1437         if (vnic && vnic->rss_hash_key) {
1438                 if (rss_conf->rss_key) {
1439                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1440                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1441                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1442                 }
1443
1444                 hash_types = vnic->hash_type;
1445                 rss_conf->rss_hf = 0;
1446                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1447                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1448                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1449                 }
1450                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1451                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1452                         hash_types &=
1453                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1454                 }
1455                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1456                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1457                         hash_types &=
1458                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1459                 }
1460                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1461                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1462                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1463                 }
1464                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1465                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1466                         hash_types &=
1467                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1468                 }
1469                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1470                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1471                         hash_types &=
1472                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1473                 }
1474                 if (hash_types) {
1475                         PMD_DRV_LOG(ERR,
1476                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1477                                 vnic->hash_type);
1478                         return -ENOTSUP;
1479                 }
1480         } else {
1481                 rss_conf->rss_hf = 0;
1482         }
1483         return 0;
1484 }
1485
1486 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1487                                struct rte_eth_fc_conf *fc_conf)
1488 {
1489         struct bnxt *bp = dev->data->dev_private;
1490         struct rte_eth_link link_info;
1491         int rc;
1492
1493         rc = is_bnxt_in_error(bp);
1494         if (rc)
1495                 return rc;
1496
1497         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1498         if (rc)
1499                 return rc;
1500
1501         memset(fc_conf, 0, sizeof(*fc_conf));
1502         if (bp->link_info.auto_pause)
1503                 fc_conf->autoneg = 1;
1504         switch (bp->link_info.pause) {
1505         case 0:
1506                 fc_conf->mode = RTE_FC_NONE;
1507                 break;
1508         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1509                 fc_conf->mode = RTE_FC_TX_PAUSE;
1510                 break;
1511         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1512                 fc_conf->mode = RTE_FC_RX_PAUSE;
1513                 break;
1514         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1515                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1516                 fc_conf->mode = RTE_FC_FULL;
1517                 break;
1518         }
1519         return 0;
1520 }
1521
1522 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1523                                struct rte_eth_fc_conf *fc_conf)
1524 {
1525         struct bnxt *bp = dev->data->dev_private;
1526         int rc;
1527
1528         rc = is_bnxt_in_error(bp);
1529         if (rc)
1530                 return rc;
1531
1532         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1533                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1534                 return -ENOTSUP;
1535         }
1536
1537         switch (fc_conf->mode) {
1538         case RTE_FC_NONE:
1539                 bp->link_info.auto_pause = 0;
1540                 bp->link_info.force_pause = 0;
1541                 break;
1542         case RTE_FC_RX_PAUSE:
1543                 if (fc_conf->autoneg) {
1544                         bp->link_info.auto_pause =
1545                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1546                         bp->link_info.force_pause = 0;
1547                 } else {
1548                         bp->link_info.auto_pause = 0;
1549                         bp->link_info.force_pause =
1550                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1551                 }
1552                 break;
1553         case RTE_FC_TX_PAUSE:
1554                 if (fc_conf->autoneg) {
1555                         bp->link_info.auto_pause =
1556                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1557                         bp->link_info.force_pause = 0;
1558                 } else {
1559                         bp->link_info.auto_pause = 0;
1560                         bp->link_info.force_pause =
1561                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1562                 }
1563                 break;
1564         case RTE_FC_FULL:
1565                 if (fc_conf->autoneg) {
1566                         bp->link_info.auto_pause =
1567                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1568                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1569                         bp->link_info.force_pause = 0;
1570                 } else {
1571                         bp->link_info.auto_pause = 0;
1572                         bp->link_info.force_pause =
1573                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1574                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1575                 }
1576                 break;
1577         }
1578         return bnxt_set_hwrm_link_config(bp, true);
1579 }
1580
1581 /* Add UDP tunneling port */
1582 static int
1583 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1584                          struct rte_eth_udp_tunnel *udp_tunnel)
1585 {
1586         struct bnxt *bp = eth_dev->data->dev_private;
1587         uint16_t tunnel_type = 0;
1588         int rc = 0;
1589
1590         rc = is_bnxt_in_error(bp);
1591         if (rc)
1592                 return rc;
1593
1594         switch (udp_tunnel->prot_type) {
1595         case RTE_TUNNEL_TYPE_VXLAN:
1596                 if (bp->vxlan_port_cnt) {
1597                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1598                                 udp_tunnel->udp_port);
1599                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1600                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1601                                 return -ENOSPC;
1602                         }
1603                         bp->vxlan_port_cnt++;
1604                         return 0;
1605                 }
1606                 tunnel_type =
1607                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1608                 bp->vxlan_port_cnt++;
1609                 break;
1610         case RTE_TUNNEL_TYPE_GENEVE:
1611                 if (bp->geneve_port_cnt) {
1612                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1613                                 udp_tunnel->udp_port);
1614                         if (bp->geneve_port != udp_tunnel->udp_port) {
1615                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1616                                 return -ENOSPC;
1617                         }
1618                         bp->geneve_port_cnt++;
1619                         return 0;
1620                 }
1621                 tunnel_type =
1622                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1623                 bp->geneve_port_cnt++;
1624                 break;
1625         default:
1626                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1627                 return -ENOTSUP;
1628         }
1629         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1630                                              tunnel_type);
1631         return rc;
1632 }
1633
1634 static int
1635 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1636                          struct rte_eth_udp_tunnel *udp_tunnel)
1637 {
1638         struct bnxt *bp = eth_dev->data->dev_private;
1639         uint16_t tunnel_type = 0;
1640         uint16_t port = 0;
1641         int rc = 0;
1642
1643         rc = is_bnxt_in_error(bp);
1644         if (rc)
1645                 return rc;
1646
1647         switch (udp_tunnel->prot_type) {
1648         case RTE_TUNNEL_TYPE_VXLAN:
1649                 if (!bp->vxlan_port_cnt) {
1650                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1651                         return -EINVAL;
1652                 }
1653                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1654                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1655                                 udp_tunnel->udp_port, bp->vxlan_port);
1656                         return -EINVAL;
1657                 }
1658                 if (--bp->vxlan_port_cnt)
1659                         return 0;
1660
1661                 tunnel_type =
1662                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1663                 port = bp->vxlan_fw_dst_port_id;
1664                 break;
1665         case RTE_TUNNEL_TYPE_GENEVE:
1666                 if (!bp->geneve_port_cnt) {
1667                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1668                         return -EINVAL;
1669                 }
1670                 if (bp->geneve_port != udp_tunnel->udp_port) {
1671                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1672                                 udp_tunnel->udp_port, bp->geneve_port);
1673                         return -EINVAL;
1674                 }
1675                 if (--bp->geneve_port_cnt)
1676                         return 0;
1677
1678                 tunnel_type =
1679                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1680                 port = bp->geneve_fw_dst_port_id;
1681                 break;
1682         default:
1683                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1684                 return -ENOTSUP;
1685         }
1686
1687         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1688         if (!rc) {
1689                 if (tunnel_type ==
1690                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1691                         bp->vxlan_port = 0;
1692                 if (tunnel_type ==
1693                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1694                         bp->geneve_port = 0;
1695         }
1696         return rc;
1697 }
1698
1699 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1700 {
1701         struct bnxt_filter_info *filter;
1702         struct bnxt_vnic_info *vnic;
1703         int rc = 0;
1704         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1705
1706         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1707         filter = STAILQ_FIRST(&vnic->filter);
1708         while (filter) {
1709                 /* Search for this matching MAC+VLAN filter */
1710                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1711                         /* Delete the filter */
1712                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1713                         if (rc)
1714                                 return rc;
1715                         STAILQ_REMOVE(&vnic->filter, filter,
1716                                       bnxt_filter_info, next);
1717                         bnxt_free_filter(bp, filter);
1718                         PMD_DRV_LOG(INFO,
1719                                     "Deleted vlan filter for %d\n",
1720                                     vlan_id);
1721                         return 0;
1722                 }
1723                 filter = STAILQ_NEXT(filter, next);
1724         }
1725         return -ENOENT;
1726 }
1727
1728 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1729 {
1730         struct bnxt_filter_info *filter;
1731         struct bnxt_vnic_info *vnic;
1732         int rc = 0;
1733         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1734                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1735         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1736
1737         /* Implementation notes on the use of VNIC in this command:
1738          *
1739          * By default, these filters belong to default vnic for the function.
1740          * Once these filters are set up, only destination VNIC can be modified.
1741          * If the destination VNIC is not specified in this command,
1742          * then the HWRM shall only create an l2 context id.
1743          */
1744
1745         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1746         filter = STAILQ_FIRST(&vnic->filter);
1747         /* Check if the VLAN has already been added */
1748         while (filter) {
1749                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1750                         return -EEXIST;
1751
1752                 filter = STAILQ_NEXT(filter, next);
1753         }
1754
1755         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1756          * command to create MAC+VLAN filter with the right flags, enables set.
1757          */
1758         filter = bnxt_alloc_filter(bp);
1759         if (!filter) {
1760                 PMD_DRV_LOG(ERR,
1761                             "MAC/VLAN filter alloc failed\n");
1762                 return -ENOMEM;
1763         }
1764         /* MAC + VLAN ID filter */
1765         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1766          * untagged packets are received
1767          *
1768          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1769          * packets and only the programmed vlan's packets are received
1770          */
1771         filter->l2_ivlan = vlan_id;
1772         filter->l2_ivlan_mask = 0x0FFF;
1773         filter->enables |= en;
1774         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1775
1776         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1777         if (rc) {
1778                 /* Free the newly allocated filter as we were
1779                  * not able to create the filter in hardware.
1780                  */
1781                 bnxt_free_filter(bp, filter);
1782                 return rc;
1783         }
1784
1785         filter->mac_index = 0;
1786         /* Add this new filter to the list */
1787         if (vlan_id == 0)
1788                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1789         else
1790                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1791
1792         PMD_DRV_LOG(INFO,
1793                     "Added Vlan filter for %d\n", vlan_id);
1794         return rc;
1795 }
1796
1797 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1798                 uint16_t vlan_id, int on)
1799 {
1800         struct bnxt *bp = eth_dev->data->dev_private;
1801         int rc;
1802
1803         rc = is_bnxt_in_error(bp);
1804         if (rc)
1805                 return rc;
1806
1807         /* These operations apply to ALL existing MAC/VLAN filters */
1808         if (on)
1809                 return bnxt_add_vlan_filter(bp, vlan_id);
1810         else
1811                 return bnxt_del_vlan_filter(bp, vlan_id);
1812 }
1813
1814 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1815                                     struct bnxt_vnic_info *vnic)
1816 {
1817         struct bnxt_filter_info *filter;
1818         int rc;
1819
1820         filter = STAILQ_FIRST(&vnic->filter);
1821         while (filter) {
1822                 if (filter->mac_index == 0 &&
1823                     !memcmp(filter->l2_addr, bp->mac_addr,
1824                             RTE_ETHER_ADDR_LEN)) {
1825                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1826                         if (!rc) {
1827                                 STAILQ_REMOVE(&vnic->filter, filter,
1828                                               bnxt_filter_info, next);
1829                                 bnxt_free_filter(bp, filter);
1830                         }
1831                         return rc;
1832                 }
1833                 filter = STAILQ_NEXT(filter, next);
1834         }
1835         return 0;
1836 }
1837
1838 static int
1839 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1840 {
1841         struct bnxt *bp = dev->data->dev_private;
1842         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1843         struct bnxt_vnic_info *vnic;
1844         unsigned int i;
1845         int rc;
1846
1847         rc = is_bnxt_in_error(bp);
1848         if (rc)
1849                 return rc;
1850
1851         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1852         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1853                 /* Remove any VLAN filters programmed */
1854                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1855                         bnxt_del_vlan_filter(bp, i);
1856
1857                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1858                 if (rc)
1859                         return rc;
1860         } else {
1861                 /* Default filter will allow packets that match the
1862                  * dest mac. So, it has to be deleted, otherwise, we
1863                  * will endup receiving vlan packets for which the
1864                  * filter is not programmed, when hw-vlan-filter
1865                  * configuration is ON
1866                  */
1867                 bnxt_del_dflt_mac_filter(bp, vnic);
1868                 /* This filter will allow only untagged packets */
1869                 bnxt_add_vlan_filter(bp, 0);
1870         }
1871         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1872                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1873
1874         if (mask & ETH_VLAN_STRIP_MASK) {
1875                 /* Enable or disable VLAN stripping */
1876                 for (i = 0; i < bp->nr_vnics; i++) {
1877                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1878                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1879                                 vnic->vlan_strip = true;
1880                         else
1881                                 vnic->vlan_strip = false;
1882                         bnxt_hwrm_vnic_cfg(bp, vnic);
1883                 }
1884                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1885                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1886         }
1887
1888         if (mask & ETH_VLAN_EXTEND_MASK) {
1889                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1890                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1891                 else
1892                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1893         }
1894
1895         return 0;
1896 }
1897
1898 static int
1899 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1900                       uint16_t tpid)
1901 {
1902         struct bnxt *bp = dev->data->dev_private;
1903         int qinq = dev->data->dev_conf.rxmode.offloads &
1904                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1905
1906         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1907             vlan_type != ETH_VLAN_TYPE_OUTER) {
1908                 PMD_DRV_LOG(ERR,
1909                             "Unsupported vlan type.");
1910                 return -EINVAL;
1911         }
1912         if (!qinq) {
1913                 PMD_DRV_LOG(ERR,
1914                             "QinQ not enabled. Needs to be ON as we can "
1915                             "accelerate only outer vlan\n");
1916                 return -EINVAL;
1917         }
1918
1919         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1920                 switch (tpid) {
1921                 case RTE_ETHER_TYPE_QINQ:
1922                         bp->outer_tpid_bd =
1923                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1924                                 break;
1925                 case RTE_ETHER_TYPE_VLAN:
1926                         bp->outer_tpid_bd =
1927                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1928                                 break;
1929                 case 0x9100:
1930                         bp->outer_tpid_bd =
1931                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1932                                 break;
1933                 case 0x9200:
1934                         bp->outer_tpid_bd =
1935                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1936                                 break;
1937                 case 0x9300:
1938                         bp->outer_tpid_bd =
1939                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1940                                 break;
1941                 default:
1942                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1943                         return -EINVAL;
1944                 }
1945                 bp->outer_tpid_bd |= tpid;
1946                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1947         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1948                 PMD_DRV_LOG(ERR,
1949                             "Can accelerate only outer vlan in QinQ\n");
1950                 return -EINVAL;
1951         }
1952
1953         return 0;
1954 }
1955
1956 static int
1957 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1958                              struct rte_ether_addr *addr)
1959 {
1960         struct bnxt *bp = dev->data->dev_private;
1961         /* Default Filter is tied to VNIC 0 */
1962         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1963         struct bnxt_filter_info *filter;
1964         int rc;
1965
1966         rc = is_bnxt_in_error(bp);
1967         if (rc)
1968                 return rc;
1969
1970         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1971                 return -EPERM;
1972
1973         if (rte_is_zero_ether_addr(addr))
1974                 return -EINVAL;
1975
1976         STAILQ_FOREACH(filter, &vnic->filter, next) {
1977                 /* Default Filter is at Index 0 */
1978                 if (filter->mac_index != 0)
1979                         continue;
1980
1981                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1982                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1983                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1984                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1985                 filter->enables |=
1986                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1987                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1988
1989                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1990                 if (rc) {
1991                         memcpy(filter->l2_addr, bp->mac_addr,
1992                                RTE_ETHER_ADDR_LEN);
1993                         return rc;
1994                 }
1995
1996                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1997                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1998                 return 0;
1999         }
2000
2001         return 0;
2002 }
2003
2004 static int
2005 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2006                           struct rte_ether_addr *mc_addr_set,
2007                           uint32_t nb_mc_addr)
2008 {
2009         struct bnxt *bp = eth_dev->data->dev_private;
2010         char *mc_addr_list = (char *)mc_addr_set;
2011         struct bnxt_vnic_info *vnic;
2012         uint32_t off = 0, i = 0;
2013         int rc;
2014
2015         rc = is_bnxt_in_error(bp);
2016         if (rc)
2017                 return rc;
2018
2019         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2020
2021         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2022                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2023                 goto allmulti;
2024         }
2025
2026         /* TODO Check for Duplicate mcast addresses */
2027         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2028         for (i = 0; i < nb_mc_addr; i++) {
2029                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2030                         RTE_ETHER_ADDR_LEN);
2031                 off += RTE_ETHER_ADDR_LEN;
2032         }
2033
2034         vnic->mc_addr_cnt = i;
2035         if (vnic->mc_addr_cnt)
2036                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2037         else
2038                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2039
2040 allmulti:
2041         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2042 }
2043
2044 static int
2045 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2046 {
2047         struct bnxt *bp = dev->data->dev_private;
2048         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2049         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2050         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2051         int ret;
2052
2053         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2054                         fw_major, fw_minor, fw_updt);
2055
2056         ret += 1; /* add the size of '\0' */
2057         if (fw_size < (uint32_t)ret)
2058                 return ret;
2059         else
2060                 return 0;
2061 }
2062
2063 static void
2064 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2065         struct rte_eth_rxq_info *qinfo)
2066 {
2067         struct bnxt *bp = dev->data->dev_private;
2068         struct bnxt_rx_queue *rxq;
2069
2070         if (is_bnxt_in_error(bp))
2071                 return;
2072
2073         rxq = dev->data->rx_queues[queue_id];
2074
2075         qinfo->mp = rxq->mb_pool;
2076         qinfo->scattered_rx = dev->data->scattered_rx;
2077         qinfo->nb_desc = rxq->nb_rx_desc;
2078
2079         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2080         qinfo->conf.rx_drop_en = 0;
2081         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2082 }
2083
2084 static void
2085 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2086         struct rte_eth_txq_info *qinfo)
2087 {
2088         struct bnxt *bp = dev->data->dev_private;
2089         struct bnxt_tx_queue *txq;
2090
2091         if (is_bnxt_in_error(bp))
2092                 return;
2093
2094         txq = dev->data->tx_queues[queue_id];
2095
2096         qinfo->nb_desc = txq->nb_tx_desc;
2097
2098         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2099         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2100         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2101
2102         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2103         qinfo->conf.tx_rs_thresh = 0;
2104         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2105 }
2106
2107 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2108 {
2109         struct bnxt *bp = eth_dev->data->dev_private;
2110         uint32_t new_pkt_size;
2111         uint32_t rc = 0;
2112         uint32_t i;
2113
2114         rc = is_bnxt_in_error(bp);
2115         if (rc)
2116                 return rc;
2117
2118         /* Exit if receive queues are not configured yet */
2119         if (!eth_dev->data->nb_rx_queues)
2120                 return rc;
2121
2122         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2123                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2124
2125 #ifdef RTE_ARCH_X86
2126         /*
2127          * If vector-mode tx/rx is active, disallow any MTU change that would
2128          * require scattered receive support.
2129          */
2130         if (eth_dev->data->dev_started &&
2131             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2132              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2133             (new_pkt_size >
2134              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2135                 PMD_DRV_LOG(ERR,
2136                             "MTU change would require scattered rx support. ");
2137                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2138                 return -EINVAL;
2139         }
2140 #endif
2141
2142         if (new_mtu > RTE_ETHER_MTU) {
2143                 bp->flags |= BNXT_FLAG_JUMBO;
2144                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2145                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2146         } else {
2147                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2148                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2149                 bp->flags &= ~BNXT_FLAG_JUMBO;
2150         }
2151
2152         /* Is there a change in mtu setting? */
2153         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2154                 return rc;
2155
2156         for (i = 0; i < bp->nr_vnics; i++) {
2157                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2158                 uint16_t size = 0;
2159
2160                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2161                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2162                 if (rc)
2163                         break;
2164
2165                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2166                 size -= RTE_PKTMBUF_HEADROOM;
2167
2168                 if (size < new_mtu) {
2169                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2170                         if (rc)
2171                                 return rc;
2172                 }
2173         }
2174
2175         if (!rc)
2176                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2177
2178         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2179
2180         return rc;
2181 }
2182
2183 static int
2184 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2185 {
2186         struct bnxt *bp = dev->data->dev_private;
2187         uint16_t vlan = bp->vlan;
2188         int rc;
2189
2190         rc = is_bnxt_in_error(bp);
2191         if (rc)
2192                 return rc;
2193
2194         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2195                 PMD_DRV_LOG(ERR,
2196                         "PVID cannot be modified for this function\n");
2197                 return -ENOTSUP;
2198         }
2199         bp->vlan = on ? pvid : 0;
2200
2201         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2202         if (rc)
2203                 bp->vlan = vlan;
2204         return rc;
2205 }
2206
2207 static int
2208 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2209 {
2210         struct bnxt *bp = dev->data->dev_private;
2211         int rc;
2212
2213         rc = is_bnxt_in_error(bp);
2214         if (rc)
2215                 return rc;
2216
2217         return bnxt_hwrm_port_led_cfg(bp, true);
2218 }
2219
2220 static int
2221 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2222 {
2223         struct bnxt *bp = dev->data->dev_private;
2224         int rc;
2225
2226         rc = is_bnxt_in_error(bp);
2227         if (rc)
2228                 return rc;
2229
2230         return bnxt_hwrm_port_led_cfg(bp, false);
2231 }
2232
2233 static uint32_t
2234 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2235 {
2236         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2237         uint32_t desc = 0, raw_cons = 0, cons;
2238         struct bnxt_cp_ring_info *cpr;
2239         struct bnxt_rx_queue *rxq;
2240         struct rx_pkt_cmpl *rxcmp;
2241         int rc;
2242
2243         rc = is_bnxt_in_error(bp);
2244         if (rc)
2245                 return rc;
2246
2247         rxq = dev->data->rx_queues[rx_queue_id];
2248         cpr = rxq->cp_ring;
2249         raw_cons = cpr->cp_raw_cons;
2250
2251         while (1) {
2252                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2253                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2254                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2255
2256                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2257                         break;
2258                 } else {
2259                         raw_cons++;
2260                         desc++;
2261                 }
2262         }
2263
2264         return desc;
2265 }
2266
2267 static int
2268 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2269 {
2270         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2271         struct bnxt_rx_ring_info *rxr;
2272         struct bnxt_cp_ring_info *cpr;
2273         struct bnxt_sw_rx_bd *rx_buf;
2274         struct rx_pkt_cmpl *rxcmp;
2275         uint32_t cons, cp_cons;
2276         int rc;
2277
2278         if (!rxq)
2279                 return -EINVAL;
2280
2281         rc = is_bnxt_in_error(rxq->bp);
2282         if (rc)
2283                 return rc;
2284
2285         cpr = rxq->cp_ring;
2286         rxr = rxq->rx_ring;
2287
2288         if (offset >= rxq->nb_rx_desc)
2289                 return -EINVAL;
2290
2291         cons = RING_CMP(cpr->cp_ring_struct, offset);
2292         cp_cons = cpr->cp_raw_cons;
2293         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2294
2295         if (cons > cp_cons) {
2296                 if (CMPL_VALID(rxcmp, cpr->valid))
2297                         return RTE_ETH_RX_DESC_DONE;
2298         } else {
2299                 if (CMPL_VALID(rxcmp, !cpr->valid))
2300                         return RTE_ETH_RX_DESC_DONE;
2301         }
2302         rx_buf = &rxr->rx_buf_ring[cons];
2303         if (rx_buf->mbuf == NULL)
2304                 return RTE_ETH_RX_DESC_UNAVAIL;
2305
2306
2307         return RTE_ETH_RX_DESC_AVAIL;
2308 }
2309
2310 static int
2311 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2312 {
2313         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2314         struct bnxt_tx_ring_info *txr;
2315         struct bnxt_cp_ring_info *cpr;
2316         struct bnxt_sw_tx_bd *tx_buf;
2317         struct tx_pkt_cmpl *txcmp;
2318         uint32_t cons, cp_cons;
2319         int rc;
2320
2321         if (!txq)
2322                 return -EINVAL;
2323
2324         rc = is_bnxt_in_error(txq->bp);
2325         if (rc)
2326                 return rc;
2327
2328         cpr = txq->cp_ring;
2329         txr = txq->tx_ring;
2330
2331         if (offset >= txq->nb_tx_desc)
2332                 return -EINVAL;
2333
2334         cons = RING_CMP(cpr->cp_ring_struct, offset);
2335         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2336         cp_cons = cpr->cp_raw_cons;
2337
2338         if (cons > cp_cons) {
2339                 if (CMPL_VALID(txcmp, cpr->valid))
2340                         return RTE_ETH_TX_DESC_UNAVAIL;
2341         } else {
2342                 if (CMPL_VALID(txcmp, !cpr->valid))
2343                         return RTE_ETH_TX_DESC_UNAVAIL;
2344         }
2345         tx_buf = &txr->tx_buf_ring[cons];
2346         if (tx_buf->mbuf == NULL)
2347                 return RTE_ETH_TX_DESC_DONE;
2348
2349         return RTE_ETH_TX_DESC_FULL;
2350 }
2351
2352 static struct bnxt_filter_info *
2353 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2354                                 struct rte_eth_ethertype_filter *efilter,
2355                                 struct bnxt_vnic_info *vnic0,
2356                                 struct bnxt_vnic_info *vnic,
2357                                 int *ret)
2358 {
2359         struct bnxt_filter_info *mfilter = NULL;
2360         int match = 0;
2361         *ret = 0;
2362
2363         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2364                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2365                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2366                         " ethertype filter.", efilter->ether_type);
2367                 *ret = -EINVAL;
2368                 goto exit;
2369         }
2370         if (efilter->queue >= bp->rx_nr_rings) {
2371                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2372                 *ret = -EINVAL;
2373                 goto exit;
2374         }
2375
2376         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2377         vnic = &bp->vnic_info[efilter->queue];
2378         if (vnic == NULL) {
2379                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2380                 *ret = -EINVAL;
2381                 goto exit;
2382         }
2383
2384         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2385                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2386                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2387                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2388                              mfilter->flags ==
2389                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2390                              mfilter->ethertype == efilter->ether_type)) {
2391                                 match = 1;
2392                                 break;
2393                         }
2394                 }
2395         } else {
2396                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2397                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2398                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2399                              mfilter->ethertype == efilter->ether_type &&
2400                              mfilter->flags ==
2401                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2402                                 match = 1;
2403                                 break;
2404                         }
2405         }
2406
2407         if (match)
2408                 *ret = -EEXIST;
2409
2410 exit:
2411         return mfilter;
2412 }
2413
2414 static int
2415 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2416                         enum rte_filter_op filter_op,
2417                         void *arg)
2418 {
2419         struct bnxt *bp = dev->data->dev_private;
2420         struct rte_eth_ethertype_filter *efilter =
2421                         (struct rte_eth_ethertype_filter *)arg;
2422         struct bnxt_filter_info *bfilter, *filter1;
2423         struct bnxt_vnic_info *vnic, *vnic0;
2424         int ret;
2425
2426         if (filter_op == RTE_ETH_FILTER_NOP)
2427                 return 0;
2428
2429         if (arg == NULL) {
2430                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2431                             filter_op);
2432                 return -EINVAL;
2433         }
2434
2435         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2436         vnic = &bp->vnic_info[efilter->queue];
2437
2438         switch (filter_op) {
2439         case RTE_ETH_FILTER_ADD:
2440                 bnxt_match_and_validate_ether_filter(bp, efilter,
2441                                                         vnic0, vnic, &ret);
2442                 if (ret < 0)
2443                         return ret;
2444
2445                 bfilter = bnxt_get_unused_filter(bp);
2446                 if (bfilter == NULL) {
2447                         PMD_DRV_LOG(ERR,
2448                                 "Not enough resources for a new filter.\n");
2449                         return -ENOMEM;
2450                 }
2451                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2452                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2453                        RTE_ETHER_ADDR_LEN);
2454                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2455                        RTE_ETHER_ADDR_LEN);
2456                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2457                 bfilter->ethertype = efilter->ether_type;
2458                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2459
2460                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2461                 if (filter1 == NULL) {
2462                         ret = -EINVAL;
2463                         goto cleanup;
2464                 }
2465                 bfilter->enables |=
2466                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2467                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2468
2469                 bfilter->dst_id = vnic->fw_vnic_id;
2470
2471                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2472                         bfilter->flags =
2473                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2474                 }
2475
2476                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2477                 if (ret)
2478                         goto cleanup;
2479                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2480                 break;
2481         case RTE_ETH_FILTER_DELETE:
2482                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2483                                                         vnic0, vnic, &ret);
2484                 if (ret == -EEXIST) {
2485                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2486
2487                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2488                                       next);
2489                         bnxt_free_filter(bp, filter1);
2490                 } else if (ret == 0) {
2491                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2492                 }
2493                 break;
2494         default:
2495                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2496                 ret = -EINVAL;
2497                 goto error;
2498         }
2499         return ret;
2500 cleanup:
2501         bnxt_free_filter(bp, bfilter);
2502 error:
2503         return ret;
2504 }
2505
2506 static inline int
2507 parse_ntuple_filter(struct bnxt *bp,
2508                     struct rte_eth_ntuple_filter *nfilter,
2509                     struct bnxt_filter_info *bfilter)
2510 {
2511         uint32_t en = 0;
2512
2513         if (nfilter->queue >= bp->rx_nr_rings) {
2514                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2515                 return -EINVAL;
2516         }
2517
2518         switch (nfilter->dst_port_mask) {
2519         case UINT16_MAX:
2520                 bfilter->dst_port_mask = -1;
2521                 bfilter->dst_port = nfilter->dst_port;
2522                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2523                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2524                 break;
2525         default:
2526                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2527                 return -EINVAL;
2528         }
2529
2530         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2531         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2532
2533         switch (nfilter->proto_mask) {
2534         case UINT8_MAX:
2535                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2536                         bfilter->ip_protocol = 17;
2537                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2538                         bfilter->ip_protocol = 6;
2539                 else
2540                         return -EINVAL;
2541                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2542                 break;
2543         default:
2544                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2545                 return -EINVAL;
2546         }
2547
2548         switch (nfilter->dst_ip_mask) {
2549         case UINT32_MAX:
2550                 bfilter->dst_ipaddr_mask[0] = -1;
2551                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2552                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2553                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2554                 break;
2555         default:
2556                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2557                 return -EINVAL;
2558         }
2559
2560         switch (nfilter->src_ip_mask) {
2561         case UINT32_MAX:
2562                 bfilter->src_ipaddr_mask[0] = -1;
2563                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2564                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2565                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2566                 break;
2567         default:
2568                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2569                 return -EINVAL;
2570         }
2571
2572         switch (nfilter->src_port_mask) {
2573         case UINT16_MAX:
2574                 bfilter->src_port_mask = -1;
2575                 bfilter->src_port = nfilter->src_port;
2576                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2577                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2578                 break;
2579         default:
2580                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2581                 return -EINVAL;
2582         }
2583
2584         bfilter->enables = en;
2585         return 0;
2586 }
2587
2588 static struct bnxt_filter_info*
2589 bnxt_match_ntuple_filter(struct bnxt *bp,
2590                          struct bnxt_filter_info *bfilter,
2591                          struct bnxt_vnic_info **mvnic)
2592 {
2593         struct bnxt_filter_info *mfilter = NULL;
2594         int i;
2595
2596         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2597                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2598                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2599                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2600                             bfilter->src_ipaddr_mask[0] ==
2601                             mfilter->src_ipaddr_mask[0] &&
2602                             bfilter->src_port == mfilter->src_port &&
2603                             bfilter->src_port_mask == mfilter->src_port_mask &&
2604                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2605                             bfilter->dst_ipaddr_mask[0] ==
2606                             mfilter->dst_ipaddr_mask[0] &&
2607                             bfilter->dst_port == mfilter->dst_port &&
2608                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2609                             bfilter->flags == mfilter->flags &&
2610                             bfilter->enables == mfilter->enables) {
2611                                 if (mvnic)
2612                                         *mvnic = vnic;
2613                                 return mfilter;
2614                         }
2615                 }
2616         }
2617         return NULL;
2618 }
2619
2620 static int
2621 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2622                        struct rte_eth_ntuple_filter *nfilter,
2623                        enum rte_filter_op filter_op)
2624 {
2625         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2626         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2627         int ret;
2628
2629         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2630                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2631                 return -EINVAL;
2632         }
2633
2634         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2635                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2636                 return -EINVAL;
2637         }
2638
2639         bfilter = bnxt_get_unused_filter(bp);
2640         if (bfilter == NULL) {
2641                 PMD_DRV_LOG(ERR,
2642                         "Not enough resources for a new filter.\n");
2643                 return -ENOMEM;
2644         }
2645         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2646         if (ret < 0)
2647                 goto free_filter;
2648
2649         vnic = &bp->vnic_info[nfilter->queue];
2650         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2651         filter1 = STAILQ_FIRST(&vnic0->filter);
2652         if (filter1 == NULL) {
2653                 ret = -EINVAL;
2654                 goto free_filter;
2655         }
2656
2657         bfilter->dst_id = vnic->fw_vnic_id;
2658         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2659         bfilter->enables |=
2660                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2661         bfilter->ethertype = 0x800;
2662         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2663
2664         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2665
2666         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2667             bfilter->dst_id == mfilter->dst_id) {
2668                 PMD_DRV_LOG(ERR, "filter exists.\n");
2669                 ret = -EEXIST;
2670                 goto free_filter;
2671         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2672                    bfilter->dst_id != mfilter->dst_id) {
2673                 mfilter->dst_id = vnic->fw_vnic_id;
2674                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2675                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2676                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2677                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2678                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2679                 goto free_filter;
2680         }
2681         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2682                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2683                 ret = -ENOENT;
2684                 goto free_filter;
2685         }
2686
2687         if (filter_op == RTE_ETH_FILTER_ADD) {
2688                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2689                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2690                 if (ret)
2691                         goto free_filter;
2692                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2693         } else {
2694                 if (mfilter == NULL) {
2695                         /* This should not happen. But for Coverity! */
2696                         ret = -ENOENT;
2697                         goto free_filter;
2698                 }
2699                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2700
2701                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2702                 bnxt_free_filter(bp, mfilter);
2703                 bnxt_free_filter(bp, bfilter);
2704         }
2705
2706         return 0;
2707 free_filter:
2708         bnxt_free_filter(bp, bfilter);
2709         return ret;
2710 }
2711
2712 static int
2713 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2714                         enum rte_filter_op filter_op,
2715                         void *arg)
2716 {
2717         struct bnxt *bp = dev->data->dev_private;
2718         int ret;
2719
2720         if (filter_op == RTE_ETH_FILTER_NOP)
2721                 return 0;
2722
2723         if (arg == NULL) {
2724                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2725                             filter_op);
2726                 return -EINVAL;
2727         }
2728
2729         switch (filter_op) {
2730         case RTE_ETH_FILTER_ADD:
2731                 ret = bnxt_cfg_ntuple_filter(bp,
2732                         (struct rte_eth_ntuple_filter *)arg,
2733                         filter_op);
2734                 break;
2735         case RTE_ETH_FILTER_DELETE:
2736                 ret = bnxt_cfg_ntuple_filter(bp,
2737                         (struct rte_eth_ntuple_filter *)arg,
2738                         filter_op);
2739                 break;
2740         default:
2741                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2742                 ret = -EINVAL;
2743                 break;
2744         }
2745         return ret;
2746 }
2747
2748 static int
2749 bnxt_parse_fdir_filter(struct bnxt *bp,
2750                        struct rte_eth_fdir_filter *fdir,
2751                        struct bnxt_filter_info *filter)
2752 {
2753         enum rte_fdir_mode fdir_mode =
2754                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2755         struct bnxt_vnic_info *vnic0, *vnic;
2756         struct bnxt_filter_info *filter1;
2757         uint32_t en = 0;
2758         int i;
2759
2760         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2761                 return -EINVAL;
2762
2763         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2764         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2765
2766         switch (fdir->input.flow_type) {
2767         case RTE_ETH_FLOW_IPV4:
2768         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2769                 /* FALLTHROUGH */
2770                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2771                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2772                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2773                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2774                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2775                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2776                 filter->ip_addr_type =
2777                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2778                 filter->src_ipaddr_mask[0] = 0xffffffff;
2779                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2780                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2781                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2782                 filter->ethertype = 0x800;
2783                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2784                 break;
2785         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2786                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2787                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2788                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2789                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2790                 filter->dst_port_mask = 0xffff;
2791                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2792                 filter->src_port_mask = 0xffff;
2793                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2794                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2795                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2796                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2797                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2798                 filter->ip_protocol = 6;
2799                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2800                 filter->ip_addr_type =
2801                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2802                 filter->src_ipaddr_mask[0] = 0xffffffff;
2803                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2804                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2805                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2806                 filter->ethertype = 0x800;
2807                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2808                 break;
2809         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2810                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2812                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2813                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2814                 filter->dst_port_mask = 0xffff;
2815                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2816                 filter->src_port_mask = 0xffff;
2817                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2818                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2819                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2820                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2821                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2822                 filter->ip_protocol = 17;
2823                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2824                 filter->ip_addr_type =
2825                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2826                 filter->src_ipaddr_mask[0] = 0xffffffff;
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2828                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2829                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2830                 filter->ethertype = 0x800;
2831                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2832                 break;
2833         case RTE_ETH_FLOW_IPV6:
2834         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2835                 /* FALLTHROUGH */
2836                 filter->ip_addr_type =
2837                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2838                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2839                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2840                 rte_memcpy(filter->src_ipaddr,
2841                            fdir->input.flow.ipv6_flow.src_ip, 16);
2842                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2843                 rte_memcpy(filter->dst_ipaddr,
2844                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2845                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2846                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2847                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2848                 memset(filter->src_ipaddr_mask, 0xff, 16);
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2850                 filter->ethertype = 0x86dd;
2851                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2852                 break;
2853         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2854                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2855                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2856                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2857                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2858                 filter->dst_port_mask = 0xffff;
2859                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2860                 filter->src_port_mask = 0xffff;
2861                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2862                 filter->ip_addr_type =
2863                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2864                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2865                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2866                 rte_memcpy(filter->src_ipaddr,
2867                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2868                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2869                 rte_memcpy(filter->dst_ipaddr,
2870                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2871                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2872                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2873                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2874                 memset(filter->src_ipaddr_mask, 0xff, 16);
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2876                 filter->ethertype = 0x86dd;
2877                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2878                 break;
2879         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2880                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2881                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2882                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2883                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2884                 filter->dst_port_mask = 0xffff;
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2886                 filter->src_port_mask = 0xffff;
2887                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2888                 filter->ip_addr_type =
2889                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2890                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2891                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2892                 rte_memcpy(filter->src_ipaddr,
2893                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2895                 rte_memcpy(filter->dst_ipaddr,
2896                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2897                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2898                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2899                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2900                 memset(filter->src_ipaddr_mask, 0xff, 16);
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2902                 filter->ethertype = 0x86dd;
2903                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2904                 break;
2905         case RTE_ETH_FLOW_L2_PAYLOAD:
2906                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2907                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2908                 break;
2909         case RTE_ETH_FLOW_VXLAN:
2910                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2911                         return -EINVAL;
2912                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2913                 filter->tunnel_type =
2914                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2915                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2916                 break;
2917         case RTE_ETH_FLOW_NVGRE:
2918                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2919                         return -EINVAL;
2920                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2921                 filter->tunnel_type =
2922                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2923                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2924                 break;
2925         case RTE_ETH_FLOW_UNKNOWN:
2926         case RTE_ETH_FLOW_RAW:
2927         case RTE_ETH_FLOW_FRAG_IPV4:
2928         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2929         case RTE_ETH_FLOW_FRAG_IPV6:
2930         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2931         case RTE_ETH_FLOW_IPV6_EX:
2932         case RTE_ETH_FLOW_IPV6_TCP_EX:
2933         case RTE_ETH_FLOW_IPV6_UDP_EX:
2934         case RTE_ETH_FLOW_GENEVE:
2935                 /* FALLTHROUGH */
2936         default:
2937                 return -EINVAL;
2938         }
2939
2940         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2941         vnic = &bp->vnic_info[fdir->action.rx_queue];
2942         if (vnic == NULL) {
2943                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2944                 return -EINVAL;
2945         }
2946
2947         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2948                 rte_memcpy(filter->dst_macaddr,
2949                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2950                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2951         }
2952
2953         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2954                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2955                 filter1 = STAILQ_FIRST(&vnic0->filter);
2956                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2957         } else {
2958                 filter->dst_id = vnic->fw_vnic_id;
2959                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2960                         if (filter->dst_macaddr[i] == 0x00)
2961                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2962                         else
2963                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2964         }
2965
2966         if (filter1 == NULL)
2967                 return -EINVAL;
2968
2969         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2970         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2971
2972         filter->enables = en;
2973
2974         return 0;
2975 }
2976
2977 static struct bnxt_filter_info *
2978 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2979                 struct bnxt_vnic_info **mvnic)
2980 {
2981         struct bnxt_filter_info *mf = NULL;
2982         int i;
2983
2984         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2985                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2986
2987                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2988                         if (mf->filter_type == nf->filter_type &&
2989                             mf->flags == nf->flags &&
2990                             mf->src_port == nf->src_port &&
2991                             mf->src_port_mask == nf->src_port_mask &&
2992                             mf->dst_port == nf->dst_port &&
2993                             mf->dst_port_mask == nf->dst_port_mask &&
2994                             mf->ip_protocol == nf->ip_protocol &&
2995                             mf->ip_addr_type == nf->ip_addr_type &&
2996                             mf->ethertype == nf->ethertype &&
2997                             mf->vni == nf->vni &&
2998                             mf->tunnel_type == nf->tunnel_type &&
2999                             mf->l2_ovlan == nf->l2_ovlan &&
3000                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3001                             mf->l2_ivlan == nf->l2_ivlan &&
3002                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3003                             !memcmp(mf->l2_addr, nf->l2_addr,
3004                                     RTE_ETHER_ADDR_LEN) &&
3005                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3006                                     RTE_ETHER_ADDR_LEN) &&
3007                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3008                                     RTE_ETHER_ADDR_LEN) &&
3009                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3010                                     RTE_ETHER_ADDR_LEN) &&
3011                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3012                                     sizeof(nf->src_ipaddr)) &&
3013                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3014                                     sizeof(nf->src_ipaddr_mask)) &&
3015                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3016                                     sizeof(nf->dst_ipaddr)) &&
3017                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3018                                     sizeof(nf->dst_ipaddr_mask))) {
3019                                 if (mvnic)
3020                                         *mvnic = vnic;
3021                                 return mf;
3022                         }
3023                 }
3024         }
3025         return NULL;
3026 }
3027
3028 static int
3029 bnxt_fdir_filter(struct rte_eth_dev *dev,
3030                  enum rte_filter_op filter_op,
3031                  void *arg)
3032 {
3033         struct bnxt *bp = dev->data->dev_private;
3034         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3035         struct bnxt_filter_info *filter, *match;
3036         struct bnxt_vnic_info *vnic, *mvnic;
3037         int ret = 0, i;
3038
3039         if (filter_op == RTE_ETH_FILTER_NOP)
3040                 return 0;
3041
3042         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3043                 return -EINVAL;
3044
3045         switch (filter_op) {
3046         case RTE_ETH_FILTER_ADD:
3047         case RTE_ETH_FILTER_DELETE:
3048                 /* FALLTHROUGH */
3049                 filter = bnxt_get_unused_filter(bp);
3050                 if (filter == NULL) {
3051                         PMD_DRV_LOG(ERR,
3052                                 "Not enough resources for a new flow.\n");
3053                         return -ENOMEM;
3054                 }
3055
3056                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3057                 if (ret != 0)
3058                         goto free_filter;
3059                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3060
3061                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3062                         vnic = &bp->vnic_info[0];
3063                 else
3064                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3065
3066                 match = bnxt_match_fdir(bp, filter, &mvnic);
3067                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3068                         if (match->dst_id == vnic->fw_vnic_id) {
3069                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3070                                 ret = -EEXIST;
3071                                 goto free_filter;
3072                         } else {
3073                                 match->dst_id = vnic->fw_vnic_id;
3074                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3075                                                                   match->dst_id,
3076                                                                   match);
3077                                 STAILQ_REMOVE(&mvnic->filter, match,
3078                                               bnxt_filter_info, next);
3079                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3080                                 PMD_DRV_LOG(ERR,
3081                                         "Filter with matching pattern exist\n");
3082                                 PMD_DRV_LOG(ERR,
3083                                         "Updated it to new destination q\n");
3084                                 goto free_filter;
3085                         }
3086                 }
3087                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3088                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3089                         ret = -ENOENT;
3090                         goto free_filter;
3091                 }
3092
3093                 if (filter_op == RTE_ETH_FILTER_ADD) {
3094                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3095                                                           filter->dst_id,
3096                                                           filter);
3097                         if (ret)
3098                                 goto free_filter;
3099                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3100                 } else {
3101                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3102                         STAILQ_REMOVE(&vnic->filter, match,
3103                                       bnxt_filter_info, next);
3104                         bnxt_free_filter(bp, match);
3105                         bnxt_free_filter(bp, filter);
3106                 }
3107                 break;
3108         case RTE_ETH_FILTER_FLUSH:
3109                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3110                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3111
3112                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3113                                 if (filter->filter_type ==
3114                                     HWRM_CFA_NTUPLE_FILTER) {
3115                                         ret =
3116                                         bnxt_hwrm_clear_ntuple_filter(bp,
3117                                                                       filter);
3118                                         STAILQ_REMOVE(&vnic->filter, filter,
3119                                                       bnxt_filter_info, next);
3120                                 }
3121                         }
3122                 }
3123                 return ret;
3124         case RTE_ETH_FILTER_UPDATE:
3125         case RTE_ETH_FILTER_STATS:
3126         case RTE_ETH_FILTER_INFO:
3127                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3128                 break;
3129         default:
3130                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3131                 ret = -EINVAL;
3132                 break;
3133         }
3134         return ret;
3135
3136 free_filter:
3137         bnxt_free_filter(bp, filter);
3138         return ret;
3139 }
3140
3141 static int
3142 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3143                     enum rte_filter_type filter_type,
3144                     enum rte_filter_op filter_op, void *arg)
3145 {
3146         int ret = 0;
3147
3148         ret = is_bnxt_in_error(dev->data->dev_private);
3149         if (ret)
3150                 return ret;
3151
3152         switch (filter_type) {
3153         case RTE_ETH_FILTER_TUNNEL:
3154                 PMD_DRV_LOG(ERR,
3155                         "filter type: %d: To be implemented\n", filter_type);
3156                 break;
3157         case RTE_ETH_FILTER_FDIR:
3158                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3159                 break;
3160         case RTE_ETH_FILTER_NTUPLE:
3161                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3162                 break;
3163         case RTE_ETH_FILTER_ETHERTYPE:
3164                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3165                 break;
3166         case RTE_ETH_FILTER_GENERIC:
3167                 if (filter_op != RTE_ETH_FILTER_GET)
3168                         return -EINVAL;
3169                 *(const void **)arg = &bnxt_flow_ops;
3170                 break;
3171         default:
3172                 PMD_DRV_LOG(ERR,
3173                         "Filter type (%d) not supported", filter_type);
3174                 ret = -EINVAL;
3175                 break;
3176         }
3177         return ret;
3178 }
3179
3180 static const uint32_t *
3181 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3182 {
3183         static const uint32_t ptypes[] = {
3184                 RTE_PTYPE_L2_ETHER_VLAN,
3185                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3186                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3187                 RTE_PTYPE_L4_ICMP,
3188                 RTE_PTYPE_L4_TCP,
3189                 RTE_PTYPE_L4_UDP,
3190                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3191                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3192                 RTE_PTYPE_INNER_L4_ICMP,
3193                 RTE_PTYPE_INNER_L4_TCP,
3194                 RTE_PTYPE_INNER_L4_UDP,
3195                 RTE_PTYPE_UNKNOWN
3196         };
3197
3198         if (!dev->rx_pkt_burst)
3199                 return NULL;
3200
3201         return ptypes;
3202 }
3203
3204 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3205                          int reg_win)
3206 {
3207         uint32_t reg_base = *reg_arr & 0xfffff000;
3208         uint32_t win_off;
3209         int i;
3210
3211         for (i = 0; i < count; i++) {
3212                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3213                         return -ERANGE;
3214         }
3215         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3216         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3217         return 0;
3218 }
3219
3220 static int bnxt_map_ptp_regs(struct bnxt *bp)
3221 {
3222         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3223         uint32_t *reg_arr;
3224         int rc, i;
3225
3226         reg_arr = ptp->rx_regs;
3227         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3228         if (rc)
3229                 return rc;
3230
3231         reg_arr = ptp->tx_regs;
3232         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3233         if (rc)
3234                 return rc;
3235
3236         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3237                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3238
3239         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3240                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3241
3242         return 0;
3243 }
3244
3245 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3246 {
3247         rte_write32(0, (uint8_t *)bp->bar0 +
3248                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3249         rte_write32(0, (uint8_t *)bp->bar0 +
3250                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3251 }
3252
3253 static uint64_t bnxt_cc_read(struct bnxt *bp)
3254 {
3255         uint64_t ns;
3256
3257         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3258                               BNXT_GRCPF_REG_SYNC_TIME));
3259         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3260                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3261         return ns;
3262 }
3263
3264 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3265 {
3266         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3267         uint32_t fifo;
3268
3269         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3270                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3271         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3272                 return -EAGAIN;
3273
3274         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3275                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3276         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3277                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3278         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3279                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3280
3281         return 0;
3282 }
3283
3284 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3285 {
3286         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3287         struct bnxt_pf_info *pf = &bp->pf;
3288         uint16_t port_id;
3289         uint32_t fifo;
3290
3291         if (!ptp)
3292                 return -ENODEV;
3293
3294         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3295                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3296         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3297                 return -EAGAIN;
3298
3299         port_id = pf->port_id;
3300         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3301                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3302
3303         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3304                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3305         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3306 /*              bnxt_clr_rx_ts(bp);       TBD  */
3307                 return -EBUSY;
3308         }
3309
3310         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3311                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3312         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3313                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3314
3315         return 0;
3316 }
3317
3318 static int
3319 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3320 {
3321         uint64_t ns;
3322         struct bnxt *bp = dev->data->dev_private;
3323         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3324
3325         if (!ptp)
3326                 return 0;
3327
3328         ns = rte_timespec_to_ns(ts);
3329         /* Set the timecounters to a new value. */
3330         ptp->tc.nsec = ns;
3331
3332         return 0;
3333 }
3334
3335 static int
3336 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3337 {
3338         struct bnxt *bp = dev->data->dev_private;
3339         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3340         uint64_t ns, systime_cycles = 0;
3341         int rc = 0;
3342
3343         if (!ptp)
3344                 return 0;
3345
3346         if (BNXT_CHIP_THOR(bp))
3347                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3348                                              &systime_cycles);
3349         else
3350                 systime_cycles = bnxt_cc_read(bp);
3351
3352         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3353         *ts = rte_ns_to_timespec(ns);
3354
3355         return rc;
3356 }
3357 static int
3358 bnxt_timesync_enable(struct rte_eth_dev *dev)
3359 {
3360         struct bnxt *bp = dev->data->dev_private;
3361         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3362         uint32_t shift = 0;
3363         int rc;
3364
3365         if (!ptp)
3366                 return 0;
3367
3368         ptp->rx_filter = 1;
3369         ptp->tx_tstamp_en = 1;
3370         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3371
3372         rc = bnxt_hwrm_ptp_cfg(bp);
3373         if (rc)
3374                 return rc;
3375
3376         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3377         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3378         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3379
3380         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3381         ptp->tc.cc_shift = shift;
3382         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3383
3384         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3385         ptp->rx_tstamp_tc.cc_shift = shift;
3386         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3387
3388         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3389         ptp->tx_tstamp_tc.cc_shift = shift;
3390         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3391
3392         if (!BNXT_CHIP_THOR(bp))
3393                 bnxt_map_ptp_regs(bp);
3394
3395         return 0;
3396 }
3397
3398 static int
3399 bnxt_timesync_disable(struct rte_eth_dev *dev)
3400 {
3401         struct bnxt *bp = dev->data->dev_private;
3402         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3403
3404         if (!ptp)
3405                 return 0;
3406
3407         ptp->rx_filter = 0;
3408         ptp->tx_tstamp_en = 0;
3409         ptp->rxctl = 0;
3410
3411         bnxt_hwrm_ptp_cfg(bp);
3412
3413         if (!BNXT_CHIP_THOR(bp))
3414                 bnxt_unmap_ptp_regs(bp);
3415
3416         return 0;
3417 }
3418
3419 static int
3420 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3421                                  struct timespec *timestamp,
3422                                  uint32_t flags __rte_unused)
3423 {
3424         struct bnxt *bp = dev->data->dev_private;
3425         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3426         uint64_t rx_tstamp_cycles = 0;
3427         uint64_t ns;
3428
3429         if (!ptp)
3430                 return 0;
3431
3432         if (BNXT_CHIP_THOR(bp))
3433                 rx_tstamp_cycles = ptp->rx_timestamp;
3434         else
3435                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3436
3437         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3438         *timestamp = rte_ns_to_timespec(ns);
3439         return  0;
3440 }
3441
3442 static int
3443 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3444                                  struct timespec *timestamp)
3445 {
3446         struct bnxt *bp = dev->data->dev_private;
3447         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3448         uint64_t tx_tstamp_cycles = 0;
3449         uint64_t ns;
3450         int rc = 0;
3451
3452         if (!ptp)
3453                 return 0;
3454
3455         if (BNXT_CHIP_THOR(bp))
3456                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3457                                              &tx_tstamp_cycles);
3458         else
3459                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3460
3461         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3462         *timestamp = rte_ns_to_timespec(ns);
3463
3464         return rc;
3465 }
3466
3467 static int
3468 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3469 {
3470         struct bnxt *bp = dev->data->dev_private;
3471         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3472
3473         if (!ptp)
3474                 return 0;
3475
3476         ptp->tc.nsec += delta;
3477
3478         return 0;
3479 }
3480
3481 static int
3482 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3483 {
3484         struct bnxt *bp = dev->data->dev_private;
3485         int rc;
3486         uint32_t dir_entries;
3487         uint32_t entry_length;
3488
3489         rc = is_bnxt_in_error(bp);
3490         if (rc)
3491                 return rc;
3492
3493         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3494                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3495                 bp->pdev->addr.devid, bp->pdev->addr.function);
3496
3497         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3498         if (rc != 0)
3499                 return rc;
3500
3501         return dir_entries * entry_length;
3502 }
3503
3504 static int
3505 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3506                 struct rte_dev_eeprom_info *in_eeprom)
3507 {
3508         struct bnxt *bp = dev->data->dev_private;
3509         uint32_t index;
3510         uint32_t offset;
3511         int rc;
3512
3513         rc = is_bnxt_in_error(bp);
3514         if (rc)
3515                 return rc;
3516
3517         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3518                 "len = %d\n", bp->pdev->addr.domain,
3519                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3520                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3521
3522         if (in_eeprom->offset == 0) /* special offset value to get directory */
3523                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3524                                                 in_eeprom->data);
3525
3526         index = in_eeprom->offset >> 24;
3527         offset = in_eeprom->offset & 0xffffff;
3528
3529         if (index != 0)
3530                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3531                                            in_eeprom->length, in_eeprom->data);
3532
3533         return 0;
3534 }
3535
3536 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3537 {
3538         switch (dir_type) {
3539         case BNX_DIR_TYPE_CHIMP_PATCH:
3540         case BNX_DIR_TYPE_BOOTCODE:
3541         case BNX_DIR_TYPE_BOOTCODE_2:
3542         case BNX_DIR_TYPE_APE_FW:
3543         case BNX_DIR_TYPE_APE_PATCH:
3544         case BNX_DIR_TYPE_KONG_FW:
3545         case BNX_DIR_TYPE_KONG_PATCH:
3546         case BNX_DIR_TYPE_BONO_FW:
3547         case BNX_DIR_TYPE_BONO_PATCH:
3548                 /* FALLTHROUGH */
3549                 return true;
3550         }
3551
3552         return false;
3553 }
3554
3555 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3556 {
3557         switch (dir_type) {
3558         case BNX_DIR_TYPE_AVS:
3559         case BNX_DIR_TYPE_EXP_ROM_MBA:
3560         case BNX_DIR_TYPE_PCIE:
3561         case BNX_DIR_TYPE_TSCF_UCODE:
3562         case BNX_DIR_TYPE_EXT_PHY:
3563         case BNX_DIR_TYPE_CCM:
3564         case BNX_DIR_TYPE_ISCSI_BOOT:
3565         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3566         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3567                 /* FALLTHROUGH */
3568                 return true;
3569         }
3570
3571         return false;
3572 }
3573
3574 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3575 {
3576         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3577                 bnxt_dir_type_is_other_exec_format(dir_type);
3578 }
3579
3580 static int
3581 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3582                 struct rte_dev_eeprom_info *in_eeprom)
3583 {
3584         struct bnxt *bp = dev->data->dev_private;
3585         uint8_t index, dir_op;
3586         uint16_t type, ext, ordinal, attr;
3587         int rc;
3588
3589         rc = is_bnxt_in_error(bp);
3590         if (rc)
3591                 return rc;
3592
3593         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3594                 "len = %d\n", bp->pdev->addr.domain,
3595                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3596                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3597
3598         if (!BNXT_PF(bp)) {
3599                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3600                 return -EINVAL;
3601         }
3602
3603         type = in_eeprom->magic >> 16;
3604
3605         if (type == 0xffff) { /* special value for directory operations */
3606                 index = in_eeprom->magic & 0xff;
3607                 dir_op = in_eeprom->magic >> 8;
3608                 if (index == 0)
3609                         return -EINVAL;
3610                 switch (dir_op) {
3611                 case 0x0e: /* erase */
3612                         if (in_eeprom->offset != ~in_eeprom->magic)
3613                                 return -EINVAL;
3614                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3615                 default:
3616                         return -EINVAL;
3617                 }
3618         }
3619
3620         /* Create or re-write an NVM item: */
3621         if (bnxt_dir_type_is_executable(type) == true)
3622                 return -EOPNOTSUPP;
3623         ext = in_eeprom->magic & 0xffff;
3624         ordinal = in_eeprom->offset >> 16;
3625         attr = in_eeprom->offset & 0xffff;
3626
3627         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3628                                      in_eeprom->data, in_eeprom->length);
3629 }
3630
3631 /*
3632  * Initialization
3633  */
3634
3635 static const struct eth_dev_ops bnxt_dev_ops = {
3636         .dev_infos_get = bnxt_dev_info_get_op,
3637         .dev_close = bnxt_dev_close_op,
3638         .dev_configure = bnxt_dev_configure_op,
3639         .dev_start = bnxt_dev_start_op,
3640         .dev_stop = bnxt_dev_stop_op,
3641         .dev_set_link_up = bnxt_dev_set_link_up_op,
3642         .dev_set_link_down = bnxt_dev_set_link_down_op,
3643         .stats_get = bnxt_stats_get_op,
3644         .stats_reset = bnxt_stats_reset_op,
3645         .rx_queue_setup = bnxt_rx_queue_setup_op,
3646         .rx_queue_release = bnxt_rx_queue_release_op,
3647         .tx_queue_setup = bnxt_tx_queue_setup_op,
3648         .tx_queue_release = bnxt_tx_queue_release_op,
3649         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3650         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3651         .reta_update = bnxt_reta_update_op,
3652         .reta_query = bnxt_reta_query_op,
3653         .rss_hash_update = bnxt_rss_hash_update_op,
3654         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3655         .link_update = bnxt_link_update_op,
3656         .promiscuous_enable = bnxt_promiscuous_enable_op,
3657         .promiscuous_disable = bnxt_promiscuous_disable_op,
3658         .allmulticast_enable = bnxt_allmulticast_enable_op,
3659         .allmulticast_disable = bnxt_allmulticast_disable_op,
3660         .mac_addr_add = bnxt_mac_addr_add_op,
3661         .mac_addr_remove = bnxt_mac_addr_remove_op,
3662         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3663         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3664         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3665         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3666         .vlan_filter_set = bnxt_vlan_filter_set_op,
3667         .vlan_offload_set = bnxt_vlan_offload_set_op,
3668         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3669         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3670         .mtu_set = bnxt_mtu_set_op,
3671         .mac_addr_set = bnxt_set_default_mac_addr_op,
3672         .xstats_get = bnxt_dev_xstats_get_op,
3673         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3674         .xstats_reset = bnxt_dev_xstats_reset_op,
3675         .fw_version_get = bnxt_fw_version_get,
3676         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3677         .rxq_info_get = bnxt_rxq_info_get_op,
3678         .txq_info_get = bnxt_txq_info_get_op,
3679         .dev_led_on = bnxt_dev_led_on_op,
3680         .dev_led_off = bnxt_dev_led_off_op,
3681         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3682         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3683         .rx_queue_count = bnxt_rx_queue_count_op,
3684         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3685         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3686         .rx_queue_start = bnxt_rx_queue_start,
3687         .rx_queue_stop = bnxt_rx_queue_stop,
3688         .tx_queue_start = bnxt_tx_queue_start,
3689         .tx_queue_stop = bnxt_tx_queue_stop,
3690         .filter_ctrl = bnxt_filter_ctrl_op,
3691         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3692         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3693         .get_eeprom           = bnxt_get_eeprom_op,
3694         .set_eeprom           = bnxt_set_eeprom_op,
3695         .timesync_enable      = bnxt_timesync_enable,
3696         .timesync_disable     = bnxt_timesync_disable,
3697         .timesync_read_time   = bnxt_timesync_read_time,
3698         .timesync_write_time   = bnxt_timesync_write_time,
3699         .timesync_adjust_time = bnxt_timesync_adjust_time,
3700         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3701         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3702 };
3703
3704 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3705 {
3706         uint32_t offset;
3707
3708         /* Only pre-map the reset GRC registers using window 3 */
3709         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3710                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3711
3712         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3713
3714         return offset;
3715 }
3716
3717 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3718 {
3719         struct bnxt_error_recovery_info *info = bp->recovery_info;
3720         uint32_t reg_base = 0xffffffff;
3721         int i;
3722
3723         /* Only pre-map the monitoring GRC registers using window 2 */
3724         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3725                 uint32_t reg = info->status_regs[i];
3726
3727                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3728                         continue;
3729
3730                 if (reg_base == 0xffffffff)
3731                         reg_base = reg & 0xfffff000;
3732                 if ((reg & 0xfffff000) != reg_base)
3733                         return -ERANGE;
3734
3735                 /* Use mask 0xffc as the Lower 2 bits indicates
3736                  * address space location
3737                  */
3738                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3739                                                 (reg & 0xffc);
3740         }
3741
3742         if (reg_base == 0xffffffff)
3743                 return 0;
3744
3745         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3746                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3747
3748         return 0;
3749 }
3750
3751 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3752 {
3753         struct bnxt_error_recovery_info *info = bp->recovery_info;
3754         uint32_t delay = info->delay_after_reset[index];
3755         uint32_t val = info->reset_reg_val[index];
3756         uint32_t reg = info->reset_reg[index];
3757         uint32_t type, offset;
3758
3759         type = BNXT_FW_STATUS_REG_TYPE(reg);
3760         offset = BNXT_FW_STATUS_REG_OFF(reg);
3761
3762         switch (type) {
3763         case BNXT_FW_STATUS_REG_TYPE_CFG:
3764                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3765                 break;
3766         case BNXT_FW_STATUS_REG_TYPE_GRC:
3767                 offset = bnxt_map_reset_regs(bp, offset);
3768                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3769                 break;
3770         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3771                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3772                 break;
3773         }
3774         /* wait on a specific interval of time until core reset is complete */
3775         if (delay)
3776                 rte_delay_ms(delay);
3777 }
3778
3779 static void bnxt_dev_cleanup(struct bnxt *bp)
3780 {
3781         bnxt_set_hwrm_link_config(bp, false);
3782         bp->link_info.link_up = 0;
3783         if (bp->dev_stopped == 0)
3784                 bnxt_dev_stop_op(bp->eth_dev);
3785
3786         bnxt_uninit_resources(bp, true);
3787 }
3788
3789 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3790 {
3791         struct rte_eth_dev *dev = bp->eth_dev;
3792         struct rte_vlan_filter_conf *vfc;
3793         int vidx, vbit, rc;
3794         uint16_t vlan_id;
3795
3796         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3797                 vfc = &dev->data->vlan_filter_conf;
3798                 vidx = vlan_id / 64;
3799                 vbit = vlan_id % 64;
3800
3801                 /* Each bit corresponds to a VLAN id */
3802                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3803                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3804                         if (rc)
3805                                 return rc;
3806                 }
3807         }
3808
3809         return 0;
3810 }
3811
3812 static int bnxt_restore_mac_filters(struct bnxt *bp)
3813 {
3814         struct rte_eth_dev *dev = bp->eth_dev;
3815         struct rte_eth_dev_info dev_info;
3816         struct rte_ether_addr *addr;
3817         uint64_t pool_mask;
3818         uint32_t pool = 0;
3819         uint16_t i;
3820         int rc;
3821
3822         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3823                 return 0;
3824
3825         rc = bnxt_dev_info_get_op(dev, &dev_info);
3826         if (rc)
3827                 return rc;
3828
3829         /* replay MAC address configuration */
3830         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3831                 addr = &dev->data->mac_addrs[i];
3832
3833                 /* skip zero address */
3834                 if (rte_is_zero_ether_addr(addr))
3835                         continue;
3836
3837                 pool = 0;
3838                 pool_mask = dev->data->mac_pool_sel[i];
3839
3840                 do {
3841                         if (pool_mask & 1ULL) {
3842                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3843                                 if (rc)
3844                                         return rc;
3845                         }
3846                         pool_mask >>= 1;
3847                         pool++;
3848                 } while (pool_mask);
3849         }
3850
3851         return 0;
3852 }
3853
3854 static int bnxt_restore_filters(struct bnxt *bp)
3855 {
3856         struct rte_eth_dev *dev = bp->eth_dev;
3857         int ret = 0;
3858
3859         if (dev->data->all_multicast)
3860                 ret = bnxt_allmulticast_enable_op(dev);
3861         if (dev->data->promiscuous)
3862                 ret = bnxt_promiscuous_enable_op(dev);
3863
3864         ret = bnxt_restore_mac_filters(bp);
3865         if (ret)
3866                 return ret;
3867
3868         ret = bnxt_restore_vlan_filters(bp);
3869         /* TODO restore other filters as well */
3870         return ret;
3871 }
3872
3873 static void bnxt_dev_recover(void *arg)
3874 {
3875         struct bnxt *bp = arg;
3876         int timeout = bp->fw_reset_max_msecs;
3877         int rc = 0;
3878
3879         /* Clear Error flag so that device re-init should happen */
3880         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3881
3882         do {
3883                 rc = bnxt_hwrm_ver_get(bp);
3884                 if (rc == 0)
3885                         break;
3886                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3887                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3888         } while (rc && timeout);
3889
3890         if (rc) {
3891                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3892                 goto err;
3893         }
3894
3895         rc = bnxt_init_resources(bp, true);
3896         if (rc) {
3897                 PMD_DRV_LOG(ERR,
3898                             "Failed to initialize resources after reset\n");
3899                 goto err;
3900         }
3901         /* clear reset flag as the device is initialized now */
3902         bp->flags &= ~BNXT_FLAG_FW_RESET;
3903
3904         rc = bnxt_dev_start_op(bp->eth_dev);
3905         if (rc) {
3906                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3907                 goto err;
3908         }
3909
3910         rc = bnxt_restore_filters(bp);
3911         if (rc)
3912                 goto err;
3913
3914         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3915         return;
3916 err:
3917         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3918         bnxt_uninit_resources(bp, false);
3919         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3920 }
3921
3922 void bnxt_dev_reset_and_resume(void *arg)
3923 {
3924         struct bnxt *bp = arg;
3925         int rc;
3926
3927         bnxt_dev_cleanup(bp);
3928
3929         bnxt_wait_for_device_shutdown(bp);
3930
3931         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3932                                bnxt_dev_recover, (void *)bp);
3933         if (rc)
3934                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3935 }
3936
3937 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3938 {
3939         struct bnxt_error_recovery_info *info = bp->recovery_info;
3940         uint32_t reg = info->status_regs[index];
3941         uint32_t type, offset, val = 0;
3942
3943         type = BNXT_FW_STATUS_REG_TYPE(reg);
3944         offset = BNXT_FW_STATUS_REG_OFF(reg);
3945
3946         switch (type) {
3947         case BNXT_FW_STATUS_REG_TYPE_CFG:
3948                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3949                 break;
3950         case BNXT_FW_STATUS_REG_TYPE_GRC:
3951                 offset = info->mapped_status_regs[index];
3952                 /* FALLTHROUGH */
3953         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3954                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3955                                        offset));
3956                 break;
3957         }
3958
3959         return val;
3960 }
3961
3962 static int bnxt_fw_reset_all(struct bnxt *bp)
3963 {
3964         struct bnxt_error_recovery_info *info = bp->recovery_info;
3965         uint32_t i;
3966         int rc = 0;
3967
3968         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3969                 /* Reset through master function driver */
3970                 for (i = 0; i < info->reg_array_cnt; i++)
3971                         bnxt_write_fw_reset_reg(bp, i);
3972                 /* Wait for time specified by FW after triggering reset */
3973                 rte_delay_ms(info->master_func_wait_period_after_reset);
3974         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3975                 /* Reset with the help of Kong processor */
3976                 rc = bnxt_hwrm_fw_reset(bp);
3977                 if (rc)
3978                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3979         }
3980
3981         return rc;
3982 }
3983
3984 static void bnxt_fw_reset_cb(void *arg)
3985 {
3986         struct bnxt *bp = arg;
3987         struct bnxt_error_recovery_info *info = bp->recovery_info;
3988         int rc = 0;
3989
3990         /* Only Master function can do FW reset */
3991         if (bnxt_is_master_func(bp) &&
3992             bnxt_is_recovery_enabled(bp)) {
3993                 rc = bnxt_fw_reset_all(bp);
3994                 if (rc) {
3995                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3996                         return;
3997                 }
3998         }
3999
4000         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4001          * EXCEPTION_FATAL_ASYNC event to all the functions
4002          * (including MASTER FUNC). After receiving this Async, all the active
4003          * drivers should treat this case as FW initiated recovery
4004          */
4005         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4006                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4007                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4008
4009                 /* To recover from error */
4010                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4011                                   (void *)bp);
4012         }
4013 }
4014
4015 /* Driver should poll FW heartbeat, reset_counter with the frequency
4016  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4017  * When the driver detects heartbeat stop or change in reset_counter,
4018  * it has to trigger a reset to recover from the error condition.
4019  * A “master PF” is the function who will have the privilege to
4020  * initiate the chimp reset. The master PF will be elected by the
4021  * firmware and will be notified through async message.
4022  */
4023 static void bnxt_check_fw_health(void *arg)
4024 {
4025         struct bnxt *bp = arg;
4026         struct bnxt_error_recovery_info *info = bp->recovery_info;
4027         uint32_t val = 0, wait_msec;
4028
4029         if (!info || !bnxt_is_recovery_enabled(bp) ||
4030             is_bnxt_in_error(bp))
4031                 return;
4032
4033         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4034         if (val == info->last_heart_beat)
4035                 goto reset;
4036
4037         info->last_heart_beat = val;
4038
4039         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4040         if (val != info->last_reset_counter)
4041                 goto reset;
4042
4043         info->last_reset_counter = val;
4044
4045         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4046                           bnxt_check_fw_health, (void *)bp);
4047
4048         return;
4049 reset:
4050         /* Stop DMA to/from device */
4051         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4052         bp->flags |= BNXT_FLAG_FW_RESET;
4053
4054         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4055
4056         if (bnxt_is_master_func(bp))
4057                 wait_msec = info->master_func_wait_period;
4058         else
4059                 wait_msec = info->normal_func_wait_period;
4060
4061         rte_eal_alarm_set(US_PER_MS * wait_msec,
4062                           bnxt_fw_reset_cb, (void *)bp);
4063 }
4064
4065 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4066 {
4067         uint32_t polling_freq;
4068
4069         if (!bnxt_is_recovery_enabled(bp))
4070                 return;
4071
4072         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4073                 return;
4074
4075         polling_freq = bp->recovery_info->driver_polling_freq;
4076
4077         rte_eal_alarm_set(US_PER_MS * polling_freq,
4078                           bnxt_check_fw_health, (void *)bp);
4079         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4080 }
4081
4082 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4083 {
4084         if (!bnxt_is_recovery_enabled(bp))
4085                 return;
4086
4087         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4088         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4089 }
4090
4091 static bool bnxt_vf_pciid(uint16_t device_id)
4092 {
4093         switch (device_id) {
4094         case BROADCOM_DEV_ID_57304_VF:
4095         case BROADCOM_DEV_ID_57406_VF:
4096         case BROADCOM_DEV_ID_5731X_VF:
4097         case BROADCOM_DEV_ID_5741X_VF:
4098         case BROADCOM_DEV_ID_57414_VF:
4099         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4100         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4101         case BROADCOM_DEV_ID_58802_VF:
4102         case BROADCOM_DEV_ID_57500_VF1:
4103         case BROADCOM_DEV_ID_57500_VF2:
4104                 /* FALLTHROUGH */
4105                 return true;
4106         default:
4107                 return false;
4108         }
4109 }
4110
4111 static bool bnxt_thor_device(uint16_t device_id)
4112 {
4113         switch (device_id) {
4114         case BROADCOM_DEV_ID_57508:
4115         case BROADCOM_DEV_ID_57504:
4116         case BROADCOM_DEV_ID_57502:
4117         case BROADCOM_DEV_ID_57508_MF1:
4118         case BROADCOM_DEV_ID_57504_MF1:
4119         case BROADCOM_DEV_ID_57502_MF1:
4120         case BROADCOM_DEV_ID_57508_MF2:
4121         case BROADCOM_DEV_ID_57504_MF2:
4122         case BROADCOM_DEV_ID_57502_MF2:
4123         case BROADCOM_DEV_ID_57500_VF1:
4124         case BROADCOM_DEV_ID_57500_VF2:
4125                 /* FALLTHROUGH */
4126                 return true;
4127         default:
4128                 return false;
4129         }
4130 }
4131
4132 bool bnxt_stratus_device(struct bnxt *bp)
4133 {
4134         uint16_t device_id = bp->pdev->id.device_id;
4135
4136         switch (device_id) {
4137         case BROADCOM_DEV_ID_STRATUS_NIC:
4138         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4139         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4140                 /* FALLTHROUGH */
4141                 return true;
4142         default:
4143                 return false;
4144         }
4145 }
4146
4147 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4148 {
4149         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4150         struct bnxt *bp = eth_dev->data->dev_private;
4151
4152         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4153         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4154         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4155         if (!bp->bar0 || !bp->doorbell_base) {
4156                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4157                 return -ENODEV;
4158         }
4159
4160         bp->eth_dev = eth_dev;
4161         bp->pdev = pci_dev;
4162
4163         return 0;
4164 }
4165
4166 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4167                                   struct bnxt_ctx_pg_info *ctx_pg,
4168                                   uint32_t mem_size,
4169                                   const char *suffix,
4170                                   uint16_t idx)
4171 {
4172         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4173         const struct rte_memzone *mz = NULL;
4174         char mz_name[RTE_MEMZONE_NAMESIZE];
4175         rte_iova_t mz_phys_addr;
4176         uint64_t valid_bits = 0;
4177         uint32_t sz;
4178         int i;
4179
4180         if (!mem_size)
4181                 return 0;
4182
4183         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4184                          BNXT_PAGE_SIZE;
4185         rmem->page_size = BNXT_PAGE_SIZE;
4186         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4187         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4188         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4189
4190         valid_bits = PTU_PTE_VALID;
4191
4192         if (rmem->nr_pages > 1) {
4193                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4194                          "bnxt_ctx_pg_tbl%s_%x_%d",
4195                          suffix, idx, bp->eth_dev->data->port_id);
4196                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4197                 mz = rte_memzone_lookup(mz_name);
4198                 if (!mz) {
4199                         mz = rte_memzone_reserve_aligned(mz_name,
4200                                                 rmem->nr_pages * 8,
4201                                                 SOCKET_ID_ANY,
4202                                                 RTE_MEMZONE_2MB |
4203                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4204                                                 RTE_MEMZONE_IOVA_CONTIG,
4205                                                 BNXT_PAGE_SIZE);
4206                         if (mz == NULL)
4207                                 return -ENOMEM;
4208                 }
4209
4210                 memset(mz->addr, 0, mz->len);
4211                 mz_phys_addr = mz->iova;
4212                 if ((unsigned long)mz->addr == mz_phys_addr) {
4213                         PMD_DRV_LOG(DEBUG,
4214                                     "physical address same as virtual\n");
4215                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4216                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4217                         if (mz_phys_addr == RTE_BAD_IOVA) {
4218                                 PMD_DRV_LOG(ERR,
4219                                         "unable to map addr to phys memory\n");
4220                                 return -ENOMEM;
4221                         }
4222                 }
4223                 rte_mem_lock_page(((char *)mz->addr));
4224
4225                 rmem->pg_tbl = mz->addr;
4226                 rmem->pg_tbl_map = mz_phys_addr;
4227                 rmem->pg_tbl_mz = mz;
4228         }
4229
4230         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4231                  suffix, idx, bp->eth_dev->data->port_id);
4232         mz = rte_memzone_lookup(mz_name);
4233         if (!mz) {
4234                 mz = rte_memzone_reserve_aligned(mz_name,
4235                                                  mem_size,
4236                                                  SOCKET_ID_ANY,
4237                                                  RTE_MEMZONE_1GB |
4238                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4239                                                  RTE_MEMZONE_IOVA_CONTIG,
4240                                                  BNXT_PAGE_SIZE);
4241                 if (mz == NULL)
4242                         return -ENOMEM;
4243         }
4244
4245         memset(mz->addr, 0, mz->len);
4246         mz_phys_addr = mz->iova;
4247         if ((unsigned long)mz->addr == mz_phys_addr) {
4248                 PMD_DRV_LOG(DEBUG,
4249                             "Memzone physical address same as virtual.\n");
4250                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4251                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4252                         rte_mem_lock_page(((char *)mz->addr) + sz);
4253                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4254                 if (mz_phys_addr == RTE_BAD_IOVA) {
4255                         PMD_DRV_LOG(ERR,
4256                                     "unable to map addr to phys memory\n");
4257                         return -ENOMEM;
4258                 }
4259         }
4260
4261         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4262                 rte_mem_lock_page(((char *)mz->addr) + sz);
4263                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4264                 rmem->dma_arr[i] = mz_phys_addr + sz;
4265
4266                 if (rmem->nr_pages > 1) {
4267                         if (i == rmem->nr_pages - 2 &&
4268                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4269                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4270                         else if (i == rmem->nr_pages - 1 &&
4271                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4272                                 valid_bits |= PTU_PTE_LAST;
4273
4274                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4275                                                            valid_bits);
4276                 }
4277         }
4278
4279         rmem->mz = mz;
4280         if (rmem->vmem_size)
4281                 rmem->vmem = (void **)mz->addr;
4282         rmem->dma_arr[0] = mz_phys_addr;
4283         return 0;
4284 }
4285
4286 static void bnxt_free_ctx_mem(struct bnxt *bp)
4287 {
4288         int i;
4289
4290         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4291                 return;
4292
4293         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4294         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4295         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4296         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4297         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4298         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4299         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4300         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4301         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4302         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4303         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4304
4305         for (i = 0; i < BNXT_MAX_Q; i++) {
4306                 if (bp->ctx->tqm_mem[i])
4307                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4308         }
4309
4310         rte_free(bp->ctx);
4311         bp->ctx = NULL;
4312 }
4313
4314 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4315
4316 #define min_t(type, x, y) ({                    \
4317         type __min1 = (x);                      \
4318         type __min2 = (y);                      \
4319         __min1 < __min2 ? __min1 : __min2; })
4320
4321 #define max_t(type, x, y) ({                    \
4322         type __max1 = (x);                      \
4323         type __max2 = (y);                      \
4324         __max1 > __max2 ? __max1 : __max2; })
4325
4326 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4327
4328 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4329 {
4330         struct bnxt_ctx_pg_info *ctx_pg;
4331         struct bnxt_ctx_mem_info *ctx;
4332         uint32_t mem_size, ena, entries;
4333         int i, rc;
4334
4335         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4336         if (rc) {
4337                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4338                 return rc;
4339         }
4340         ctx = bp->ctx;
4341         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4342                 return 0;
4343
4344         ctx_pg = &ctx->qp_mem;
4345         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4346         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4347         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4348         if (rc)
4349                 return rc;
4350
4351         ctx_pg = &ctx->srq_mem;
4352         ctx_pg->entries = ctx->srq_max_l2_entries;
4353         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4354         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4355         if (rc)
4356                 return rc;
4357
4358         ctx_pg = &ctx->cq_mem;
4359         ctx_pg->entries = ctx->cq_max_l2_entries;
4360         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4361         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4362         if (rc)
4363                 return rc;
4364
4365         ctx_pg = &ctx->vnic_mem;
4366         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4367                 ctx->vnic_max_ring_table_entries;
4368         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4369         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4370         if (rc)
4371                 return rc;
4372
4373         ctx_pg = &ctx->stat_mem;
4374         ctx_pg->entries = ctx->stat_max_entries;
4375         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4376         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4377         if (rc)
4378                 return rc;
4379
4380         entries = ctx->qp_max_l2_entries +
4381                   ctx->vnic_max_vnic_entries +
4382                   ctx->tqm_min_entries_per_ring;
4383         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4384         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4385                           ctx->tqm_max_entries_per_ring);
4386         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4387                 ctx_pg = ctx->tqm_mem[i];
4388                 /* use min tqm entries for now. */
4389                 ctx_pg->entries = entries;
4390                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4391                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4392                 if (rc)
4393                         return rc;
4394                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4395         }
4396
4397         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4398         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4399         if (rc)
4400                 PMD_DRV_LOG(ERR,
4401                             "Failed to configure context mem: rc = %d\n", rc);
4402         else
4403                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4404
4405         return rc;
4406 }
4407
4408 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4409 {
4410         struct rte_pci_device *pci_dev = bp->pdev;
4411         char mz_name[RTE_MEMZONE_NAMESIZE];
4412         const struct rte_memzone *mz = NULL;
4413         uint32_t total_alloc_len;
4414         rte_iova_t mz_phys_addr;
4415
4416         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4417                 return 0;
4418
4419         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4420                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4421                  pci_dev->addr.bus, pci_dev->addr.devid,
4422                  pci_dev->addr.function, "rx_port_stats");
4423         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4424         mz = rte_memzone_lookup(mz_name);
4425         total_alloc_len =
4426                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4427                                        sizeof(struct rx_port_stats_ext) + 512);
4428         if (!mz) {
4429                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4430                                          SOCKET_ID_ANY,
4431                                          RTE_MEMZONE_2MB |
4432                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4433                                          RTE_MEMZONE_IOVA_CONTIG);
4434                 if (mz == NULL)
4435                         return -ENOMEM;
4436         }
4437         memset(mz->addr, 0, mz->len);
4438         mz_phys_addr = mz->iova;
4439         if ((unsigned long)mz->addr == mz_phys_addr) {
4440                 PMD_DRV_LOG(DEBUG,
4441                             "Memzone physical address same as virtual.\n");
4442                 PMD_DRV_LOG(DEBUG,
4443                             "Using rte_mem_virt2iova()\n");
4444                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4445                 if (mz_phys_addr == RTE_BAD_IOVA) {
4446                         PMD_DRV_LOG(ERR,
4447                                     "Can't map address to physical memory\n");
4448                         return -ENOMEM;
4449                 }
4450         }
4451
4452         bp->rx_mem_zone = (const void *)mz;
4453         bp->hw_rx_port_stats = mz->addr;
4454         bp->hw_rx_port_stats_map = mz_phys_addr;
4455
4456         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4457                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4458                  pci_dev->addr.bus, pci_dev->addr.devid,
4459                  pci_dev->addr.function, "tx_port_stats");
4460         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4461         mz = rte_memzone_lookup(mz_name);
4462         total_alloc_len =
4463                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4464                                        sizeof(struct tx_port_stats_ext) + 512);
4465         if (!mz) {
4466                 mz = rte_memzone_reserve(mz_name,
4467                                          total_alloc_len,
4468                                          SOCKET_ID_ANY,
4469                                          RTE_MEMZONE_2MB |
4470                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4471                                          RTE_MEMZONE_IOVA_CONTIG);
4472                 if (mz == NULL)
4473                         return -ENOMEM;
4474         }
4475         memset(mz->addr, 0, mz->len);
4476         mz_phys_addr = mz->iova;
4477         if ((unsigned long)mz->addr == mz_phys_addr) {
4478                 PMD_DRV_LOG(DEBUG,
4479                             "Memzone physical address same as virtual\n");
4480                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4481                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4482                 if (mz_phys_addr == RTE_BAD_IOVA) {
4483                         PMD_DRV_LOG(ERR,
4484                                     "Can't map address to physical memory\n");
4485                         return -ENOMEM;
4486                 }
4487         }
4488
4489         bp->tx_mem_zone = (const void *)mz;
4490         bp->hw_tx_port_stats = mz->addr;
4491         bp->hw_tx_port_stats_map = mz_phys_addr;
4492         bp->flags |= BNXT_FLAG_PORT_STATS;
4493
4494         /* Display extended statistics if FW supports it */
4495         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4496             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4497             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4498                 return 0;
4499
4500         bp->hw_rx_port_stats_ext = (void *)
4501                 ((uint8_t *)bp->hw_rx_port_stats +
4502                  sizeof(struct rx_port_stats));
4503         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4504                 sizeof(struct rx_port_stats);
4505         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4506
4507         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4508             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4509                 bp->hw_tx_port_stats_ext = (void *)
4510                         ((uint8_t *)bp->hw_tx_port_stats +
4511                          sizeof(struct tx_port_stats));
4512                 bp->hw_tx_port_stats_ext_map =
4513                         bp->hw_tx_port_stats_map +
4514                         sizeof(struct tx_port_stats);
4515                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4516         }
4517
4518         return 0;
4519 }
4520
4521 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4522 {
4523         struct bnxt *bp = eth_dev->data->dev_private;
4524         int rc = 0;
4525
4526         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4527                                                RTE_ETHER_ADDR_LEN *
4528                                                bp->max_l2_ctx,
4529                                                0);
4530         if (eth_dev->data->mac_addrs == NULL) {
4531                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4532                 return -ENOMEM;
4533         }
4534
4535         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4536                 if (BNXT_PF(bp))
4537                         return -EINVAL;
4538
4539                 /* Generate a random MAC address, if none was assigned by PF */
4540                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4541                 bnxt_eth_hw_addr_random(bp->mac_addr);
4542                 PMD_DRV_LOG(INFO,
4543                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4544                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4545                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4546
4547                 rc = bnxt_hwrm_set_mac(bp);
4548                 if (!rc)
4549                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4550                                RTE_ETHER_ADDR_LEN);
4551                 return rc;
4552         }
4553
4554         /* Copy the permanent MAC from the FUNC_QCAPS response */
4555         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4556         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4557
4558         return rc;
4559 }
4560
4561 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4562 {
4563         int rc = 0;
4564
4565         /* MAC is already configured in FW */
4566         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4567                 return 0;
4568
4569         /* Restore the old MAC configured */
4570         rc = bnxt_hwrm_set_mac(bp);
4571         if (rc)
4572                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4573
4574         return rc;
4575 }
4576
4577 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4578 {
4579         if (!BNXT_PF(bp))
4580                 return;
4581
4582 #define ALLOW_FUNC(x)   \
4583         { \
4584                 uint32_t arg = (x); \
4585                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4586                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4587         }
4588
4589         /* Forward all requests if firmware is new enough */
4590         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4591              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4592             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4593                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4594         } else {
4595                 PMD_DRV_LOG(WARNING,
4596                             "Firmware too old for VF mailbox functionality\n");
4597                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4598         }
4599
4600         /*
4601          * The following are used for driver cleanup. If we disallow these,
4602          * VF drivers can't clean up cleanly.
4603          */
4604         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4605         ALLOW_FUNC(HWRM_VNIC_FREE);
4606         ALLOW_FUNC(HWRM_RING_FREE);
4607         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4608         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4609         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4610         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4611         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4612         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4613 }
4614
4615 static int bnxt_init_fw(struct bnxt *bp)
4616 {
4617         uint16_t mtu;
4618         int rc = 0;
4619
4620         bp->fw_cap = 0;
4621
4622         rc = bnxt_hwrm_ver_get(bp);
4623         if (rc)
4624                 return rc;
4625
4626         rc = bnxt_hwrm_func_reset(bp);
4627         if (rc)
4628                 return -EIO;
4629
4630         rc = bnxt_hwrm_vnic_qcaps(bp);
4631         if (rc)
4632                 return rc;
4633
4634         rc = bnxt_hwrm_queue_qportcfg(bp);
4635         if (rc)
4636                 return rc;
4637
4638         /* Get the MAX capabilities for this function.
4639          * This function also allocates context memory for TQM rings and
4640          * informs the firmware about this allocated backing store memory.
4641          */
4642         rc = bnxt_hwrm_func_qcaps(bp);
4643         if (rc)
4644                 return rc;
4645
4646         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4647         if (rc)
4648                 return rc;
4649
4650         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4651         if (rc)
4652                 return rc;
4653
4654         /* Get the adapter error recovery support info */
4655         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4656         if (rc)
4657                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4658
4659         bnxt_hwrm_port_led_qcaps(bp);
4660
4661         return 0;
4662 }
4663
4664 static int
4665 bnxt_init_locks(struct bnxt *bp)
4666 {
4667         int err;
4668
4669         err = pthread_mutex_init(&bp->flow_lock, NULL);
4670         if (err) {
4671                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4672                 return err;
4673         }
4674
4675         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4676         if (err)
4677                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4678         return err;
4679 }
4680
4681 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4682 {
4683         int rc;
4684
4685         rc = bnxt_init_fw(bp);
4686         if (rc)
4687                 return rc;
4688
4689         if (!reconfig_dev) {
4690                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4691                 if (rc)
4692                         return rc;
4693         } else {
4694                 rc = bnxt_restore_dflt_mac(bp);
4695                 if (rc)
4696                         return rc;
4697         }
4698
4699         bnxt_config_vf_req_fwd(bp);
4700
4701         rc = bnxt_hwrm_func_driver_register(bp);
4702         if (rc) {
4703                 PMD_DRV_LOG(ERR, "Failed to register driver");
4704                 return -EBUSY;
4705         }
4706
4707         if (BNXT_PF(bp)) {
4708                 if (bp->pdev->max_vfs) {
4709                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4710                         if (rc) {
4711                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4712                                 return rc;
4713                         }
4714                 } else {
4715                         rc = bnxt_hwrm_allocate_pf_only(bp);
4716                         if (rc) {
4717                                 PMD_DRV_LOG(ERR,
4718                                             "Failed to allocate PF resources");
4719                                 return rc;
4720                         }
4721                 }
4722         }
4723
4724         rc = bnxt_alloc_mem(bp, reconfig_dev);
4725         if (rc)
4726                 return rc;
4727
4728         rc = bnxt_setup_int(bp);
4729         if (rc)
4730                 return rc;
4731
4732         rc = bnxt_request_int(bp);
4733         if (rc)
4734                 return rc;
4735
4736         rc = bnxt_init_locks(bp);
4737         if (rc)
4738                 return rc;
4739
4740         return 0;
4741 }
4742
4743 static int
4744 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4745 {
4746         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4747         static int version_printed;
4748         struct bnxt *bp;
4749         int rc;
4750
4751         if (version_printed++ == 0)
4752                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4753
4754         eth_dev->dev_ops = &bnxt_dev_ops;
4755         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4756         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4757
4758         /*
4759          * For secondary processes, we don't initialise any further
4760          * as primary has already done this work.
4761          */
4762         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4763                 return 0;
4764
4765         rte_eth_copy_pci_info(eth_dev, pci_dev);
4766
4767         bp = eth_dev->data->dev_private;
4768
4769         bp->dev_stopped = 1;
4770
4771         if (bnxt_vf_pciid(pci_dev->id.device_id))
4772                 bp->flags |= BNXT_FLAG_VF;
4773
4774         if (bnxt_thor_device(pci_dev->id.device_id))
4775                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4776
4777         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4778             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4779             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4780             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4781                 bp->flags |= BNXT_FLAG_STINGRAY;
4782
4783         rc = bnxt_init_board(eth_dev);
4784         if (rc) {
4785                 PMD_DRV_LOG(ERR,
4786                             "Failed to initialize board rc: %x\n", rc);
4787                 return rc;
4788         }
4789
4790         rc = bnxt_alloc_hwrm_resources(bp);
4791         if (rc) {
4792                 PMD_DRV_LOG(ERR,
4793                             "Failed to allocate hwrm resource rc: %x\n", rc);
4794                 goto error_free;
4795         }
4796         rc = bnxt_init_resources(bp, false);
4797         if (rc)
4798                 goto error_free;
4799
4800         rc = bnxt_alloc_stats_mem(bp);
4801         if (rc)
4802                 goto error_free;
4803
4804         PMD_DRV_LOG(INFO,
4805                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4806                     pci_dev->mem_resource[0].phys_addr,
4807                     pci_dev->mem_resource[0].addr);
4808
4809         return 0;
4810
4811 error_free:
4812         bnxt_dev_uninit(eth_dev);
4813         return rc;
4814 }
4815
4816 static void
4817 bnxt_uninit_locks(struct bnxt *bp)
4818 {
4819         pthread_mutex_destroy(&bp->flow_lock);
4820         pthread_mutex_destroy(&bp->def_cp_lock);
4821 }
4822
4823 static int
4824 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4825 {
4826         int rc;
4827
4828         bnxt_free_int(bp);
4829         bnxt_free_mem(bp, reconfig_dev);
4830         bnxt_hwrm_func_buf_unrgtr(bp);
4831         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4832         bp->flags &= ~BNXT_FLAG_REGISTERED;
4833         bnxt_free_ctx_mem(bp);
4834         if (!reconfig_dev) {
4835                 bnxt_free_hwrm_resources(bp);
4836
4837                 if (bp->recovery_info != NULL) {
4838                         rte_free(bp->recovery_info);
4839                         bp->recovery_info = NULL;
4840                 }
4841         }
4842
4843         bnxt_uninit_locks(bp);
4844         rte_free(bp->ptp_cfg);
4845         bp->ptp_cfg = NULL;
4846         return rc;
4847 }
4848
4849 static int
4850 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4851 {
4852         struct bnxt *bp = eth_dev->data->dev_private;
4853         int rc;
4854
4855         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4856                 return -EPERM;
4857
4858         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4859
4860         rc = bnxt_uninit_resources(bp, false);
4861
4862         if (bp->tx_mem_zone) {
4863                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4864                 bp->tx_mem_zone = NULL;
4865         }
4866
4867         if (bp->rx_mem_zone) {
4868                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4869                 bp->rx_mem_zone = NULL;
4870         }
4871
4872         if (bp->dev_stopped == 0)
4873                 bnxt_dev_close_op(eth_dev);
4874         if (bp->pf.vf_info)
4875                 rte_free(bp->pf.vf_info);
4876         eth_dev->dev_ops = NULL;
4877         eth_dev->rx_pkt_burst = NULL;
4878         eth_dev->tx_pkt_burst = NULL;
4879
4880         return rc;
4881 }
4882
4883 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4884         struct rte_pci_device *pci_dev)
4885 {
4886         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4887                 bnxt_dev_init);
4888 }
4889
4890 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4891 {
4892         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4893                 return rte_eth_dev_pci_generic_remove(pci_dev,
4894                                 bnxt_dev_uninit);
4895         else
4896                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4897 }
4898
4899 static struct rte_pci_driver bnxt_rte_pmd = {
4900         .id_table = bnxt_pci_id_map,
4901         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4902         .probe = bnxt_pci_probe,
4903         .remove = bnxt_pci_remove,
4904 };
4905
4906 static bool
4907 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4908 {
4909         if (strcmp(dev->device->driver->name, drv->driver.name))
4910                 return false;
4911
4912         return true;
4913 }
4914
4915 bool is_bnxt_supported(struct rte_eth_dev *dev)
4916 {
4917         return is_device_supported(dev, &bnxt_rte_pmd);
4918 }
4919
4920 RTE_INIT(bnxt_init_log)
4921 {
4922         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4923         if (bnxt_logtype_driver >= 0)
4924                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4925 }
4926
4927 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4928 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4929 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");