drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER | \
 127                                      DEV_RX_OFFLOAD_RSS_HASH)
 128
 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 136
 137 int is_bnxt_in_error(struct bnxt *bp)
 138 {
 139         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 140                 return -EIO;
 141         if (bp->flags & BNXT_FLAG_FW_RESET)
 142                 return -EBUSY;
 143
 144         return 0;
 145 }
 146
 147 /***********************/
 148
 149 /*
 150  * High level utility functions
 151  */
 152
 153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 154 {
 155         if (!BNXT_CHIP_THOR(bp))
 156                 return 1;
 157
 158         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 159                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 160                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 161 }
 162
 163 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 164 {
 165         if (!BNXT_CHIP_THOR(bp))
 166                 return HW_HASH_INDEX_SIZE;
 167
 168         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 169 }
 170
 171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 172 {
 173         bnxt_free_filter_mem(bp);
 174         bnxt_free_vnic_attributes(bp);
 175         bnxt_free_vnic_mem(bp);
 176
 177         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 178          * If the number of rings change across fw update,
 179          * we don't have much choice except to warn the user.
 180          */
 181         if (!reconfig) {
 182                 bnxt_free_stats(bp);
 183                 bnxt_free_tx_rings(bp);
 184                 bnxt_free_rx_rings(bp);
 185         }
 186         bnxt_free_async_cp_ring(bp);
 187         bnxt_free_rxtx_nq_ring(bp);
 188
 189         rte_free(bp->grp_info);
 190         bp->grp_info = NULL;
 191 }
 192
 193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 194 {
 195         int rc;
 196
 197         rc = bnxt_alloc_ring_grps(bp);
 198         if (rc)
 199                 goto alloc_mem_err;
 200
 201         rc = bnxt_alloc_async_ring_struct(bp);
 202         if (rc)
 203                 goto alloc_mem_err;
 204
 205         rc = bnxt_alloc_vnic_mem(bp);
 206         if (rc)
 207                 goto alloc_mem_err;
 208
 209         rc = bnxt_alloc_vnic_attributes(bp);
 210         if (rc)
 211                 goto alloc_mem_err;
 212
 213         rc = bnxt_alloc_filter_mem(bp);
 214         if (rc)
 215                 goto alloc_mem_err;
 216
 217         rc = bnxt_alloc_async_cp_ring(bp);
 218         if (rc)
 219                 goto alloc_mem_err;
 220
 221         rc = bnxt_alloc_rxtx_nq_ring(bp);
 222         if (rc)
 223                 goto alloc_mem_err;
 224
 225         return 0;
 226
 227 alloc_mem_err:
 228         bnxt_free_mem(bp, reconfig);
 229         return rc;
 230 }
 231
 232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 233 {
 234         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 235         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 236         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 237         struct bnxt_rx_queue *rxq;
 238         unsigned int j;
 239         int rc;
 240
 241         rc = bnxt_vnic_grp_alloc(bp, vnic);
 242         if (rc)
 243                 goto err_out;
 244
 245         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 246                     vnic_id, vnic, vnic->fw_grp_ids);
 247
 248         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 249         if (rc)
 250                 goto err_out;
 251
 252         /* Alloc RSS context only if RSS mode is enabled */
 253         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 254                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 255
 256                 rc = 0;
 257                 for (j = 0; j < nr_ctxs; j++) {
 258                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 259                         if (rc)
 260                                 break;
 261                 }
 262                 if (rc) {
 263                         PMD_DRV_LOG(ERR,
 264                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 265                                     vnic_id, j, rc);
 266                         goto err_out;
 267                 }
 268                 vnic->num_lb_ctxts = nr_ctxs;
 269         }
 270
 271         /*
 272          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 273          * setting is not available at this time, it will not be
 274          * configured correctly in the CFA.
 275          */
 276         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 277                 vnic->vlan_strip = true;
 278         else
 279                 vnic->vlan_strip = false;
 280
 281         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 282         if (rc)
 283                 goto err_out;
 284
 285         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 286         if (rc)
 287                 goto err_out;
 288
 289         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 290                 rxq = bp->eth_dev->data->rx_queues[j];
 291
 292                 PMD_DRV_LOG(DEBUG,
 293                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 294                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 295
 296                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 297                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 298                 else
 299                         vnic->rx_queue_cnt++;
 300         }
 301
 302         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 303
 304         rc = bnxt_vnic_rss_configure(bp, vnic);
 305         if (rc)
 306                 goto err_out;
 307
 308         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 309
 310         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 311                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 312         else
 313                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 314
 315         return 0;
 316 err_out:
 317         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 318                     vnic_id, rc);
 319         return rc;
 320 }
 321
 322 static int bnxt_init_chip(struct bnxt *bp)
 323 {
 324         struct rte_eth_link new;
 325         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 326         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 327         uint32_t intr_vector = 0;
 328         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 329         uint32_t vec = BNXT_MISC_VEC_ID;
 330         unsigned int i, j;
 331         int rc;
 332
 333         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 334                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 335                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 336                 bp->flags |= BNXT_FLAG_JUMBO;
 337         } else {
 338                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 339                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 340                 bp->flags &= ~BNXT_FLAG_JUMBO;
 341         }
 342
 343         /* THOR does not support ring groups.
 344          * But we will use the array to save RSS context IDs.
 345          */
 346         if (BNXT_CHIP_THOR(bp))
 347                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 348
 349         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 350         if (rc) {
 351                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 352                 goto err_out;
 353         }
 354
 355         rc = bnxt_alloc_hwrm_rings(bp);
 356         if (rc) {
 357                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 358                 goto err_out;
 359         }
 360
 361         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 362         if (rc) {
 363                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 364                 goto err_out;
 365         }
 366
 367         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 368                 goto skip_cosq_cfg;
 369
 370         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 371                 if (bp->rx_cos_queue[i].id != 0xff) {
 372                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 373
 374                         if (!vnic) {
 375                                 PMD_DRV_LOG(ERR,
 376                                             "Num pools more than FW profile\n");
 377                                 rc = -EINVAL;
 378                                 goto err_out;
 379                         }
 380                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 381                         bp->rx_cosq_cnt++;
 382                 }
 383         }
 384
 385 skip_cosq_cfg:
 386         rc = bnxt_mq_rx_configure(bp);
 387         if (rc) {
 388                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 389                 goto err_out;
 390         }
 391
 392         /* VNIC configuration */
 393         for (i = 0; i < bp->nr_vnics; i++) {
 394                 rc = bnxt_setup_one_vnic(bp, i);
 395                 if (rc)
 396                         goto err_out;
 397         }
 398
 399         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 400         if (rc) {
 401                 PMD_DRV_LOG(ERR,
 402                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 403                 goto err_out;
 404         }
 405
 406         /* check and configure queue intr-vector mapping */
 407         if ((rte_intr_cap_multiple(intr_handle) ||
 408              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 409             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 410                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 411                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 412                 if (intr_vector > bp->rx_cp_nr_rings) {
 413                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 414                                         bp->rx_cp_nr_rings);
 415                         return -ENOTSUP;
 416                 }
 417                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 418                 if (rc)
 419                         return rc;
 420         }
 421
 422         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 423                 intr_handle->intr_vec =
 424                         rte_zmalloc("intr_vec",
 425                                     bp->eth_dev->data->nb_rx_queues *
 426                                     sizeof(int), 0);
 427                 if (intr_handle->intr_vec == NULL) {
 428                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 429                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 430                         rc = -ENOMEM;
 431                         goto err_disable;
 432                 }
 433                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 434                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 435                          intr_handle->intr_vec, intr_handle->nb_efd,
 436                         intr_handle->max_intr);
 437                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 438                      queue_id++) {
 439                         intr_handle->intr_vec[queue_id] =
 440                                                         vec + BNXT_RX_VEC_START;
 441                         if (vec < base + intr_handle->nb_efd - 1)
 442                                 vec++;
 443                 }
 444         }
 445
 446         /* enable uio/vfio intr/eventfd mapping */
 447         rc = rte_intr_enable(intr_handle);
 448 #ifndef RTE_EXEC_ENV_FREEBSD
 449         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 450         if (rc)
 451                 goto err_free;
 452 #endif
 453
 454         rc = bnxt_get_hwrm_link_config(bp, &new);
 455         if (rc) {
 456                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 457                 goto err_free;
 458         }
 459
 460         if (!bp->link_info.link_up) {
 461                 rc = bnxt_set_hwrm_link_config(bp, true);
 462                 if (rc) {
 463                         PMD_DRV_LOG(ERR,
 464                                 "HWRM link config failure rc: %x\n", rc);
 465                         goto err_free;
 466                 }
 467         }
 468         bnxt_print_link_info(bp->eth_dev);
 469
 470         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 471         if (!bp->mark_table)
 472                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 473
 474         return 0;
 475
 476 err_free:
 477         rte_free(intr_handle->intr_vec);
 478 err_disable:
 479         rte_intr_efd_disable(intr_handle);
 480 err_out:
 481         /* Some of the error status returned by FW may not be from errno.h */
 482         if (rc > 0)
 483                 rc = -EIO;
 484
 485         return rc;
 486 }
 487
 488 static int bnxt_shutdown_nic(struct bnxt *bp)
 489 {
 490         bnxt_free_all_hwrm_resources(bp);
 491         bnxt_free_all_filters(bp);
 492         bnxt_free_all_vnics(bp);
 493         return 0;
 494 }
 495
 496 /*
 497  * Device configuration and status function
 498  */
 499
 500 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 501                                 struct rte_eth_dev_info *dev_info)
 502 {
 503         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 504         struct bnxt *bp = eth_dev->data->dev_private;
 505         uint16_t max_vnics, i, j, vpool, vrxq;
 506         unsigned int max_rx_rings;
 507         int rc;
 508
 509         rc = is_bnxt_in_error(bp);
 510         if (rc)
 511                 return rc;
 512
 513         /* MAC Specifics */
 514         dev_info->max_mac_addrs = bp->max_l2_ctx;
 515         dev_info->max_hash_mac_addrs = 0;
 516
 517         /* PF/VF specifics */
 518         if (BNXT_PF(bp))
 519                 dev_info->max_vfs = pdev->max_vfs;
 520
 521         max_rx_rings = BNXT_MAX_RINGS(bp);
 522         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 523         dev_info->max_rx_queues = max_rx_rings;
 524         dev_info->max_tx_queues = max_rx_rings;
 525         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 526         dev_info->hash_key_size = 40;
 527         max_vnics = bp->max_vnics;
 528
 529         /* MTU specifics */
 530         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 531         dev_info->max_mtu = BNXT_MAX_MTU;
 532
 533         /* Fast path specifics */
 534         dev_info->min_rx_bufsize = 1;
 535         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 536
 537         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 538         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 539                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 540         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 541         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 542
 543         /* *INDENT-OFF* */
 544         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 545                 .rx_thresh = {
 546                         .pthresh = 8,
 547                         .hthresh = 8,
 548                         .wthresh = 0,
 549                 },
 550                 .rx_free_thresh = 32,
 551                 /* If no descriptors available, pkts are dropped by default */
 552                 .rx_drop_en = 1,
 553         };
 554
 555         dev_info->default_txconf = (struct rte_eth_txconf) {
 556                 .tx_thresh = {
 557                         .pthresh = 32,
 558                         .hthresh = 0,
 559                         .wthresh = 0,
 560                 },
 561                 .tx_free_thresh = 32,
 562                 .tx_rs_thresh = 32,
 563         };
 564         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 565
 566         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 567         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 568         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 569         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 570         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 571
 572         /* *INDENT-ON* */
 573
 574         /*
 575          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 576          *       need further investigation.
 577          */
 578
 579         /* VMDq resources */
 580         vpool = 64; /* ETH_64_POOLS */
 581         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 582         for (i = 0; i < 4; vpool >>= 1, i++) {
 583                 if (max_vnics > vpool) {
 584                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 585                                 if (dev_info->max_rx_queues > vrxq) {
 586                                         if (vpool > vrxq)
 587                                                 vpool = vrxq;
 588                                         goto found;
 589                                 }
 590                         }
 591                         /* Not enough resources to support VMDq */
 592                         break;
 593                 }
 594         }
 595         /* Not enough resources to support VMDq */
 596         vpool = 0;
 597         vrxq = 0;
 598 found:
 599         dev_info->max_vmdq_pools = vpool;
 600         dev_info->vmdq_queue_num = vrxq;
 601
 602         dev_info->vmdq_pool_base = 0;
 603         dev_info->vmdq_queue_base = 0;
 604
 605         return 0;
 606 }
 607
 608 /* Configure the device based on the configuration provided */
 609 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 610 {
 611         struct bnxt *bp = eth_dev->data->dev_private;
 612         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 613         int rc;
 614
 615         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 616         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 617         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 618         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 619
 620         rc = is_bnxt_in_error(bp);
 621         if (rc)
 622                 return rc;
 623
 624         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 625                 rc = bnxt_hwrm_check_vf_rings(bp);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 628                         return -ENOSPC;
 629                 }
 630
 631                 /* If a resource has already been allocated - in this case
 632                  * it is the async completion ring, free it. Reallocate it after
 633                  * resource reservation. This will ensure the resource counts
 634                  * are calculated correctly.
 635                  */
 636
 637                 pthread_mutex_lock(&bp->def_cp_lock);
 638
 639                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 640                         bnxt_disable_int(bp);
 641                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 642                 }
 643
 644                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 645                 if (rc) {
 646                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 647                         pthread_mutex_unlock(&bp->def_cp_lock);
 648                         return -ENOSPC;
 649                 }
 650
 651                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 652                         rc = bnxt_alloc_async_cp_ring(bp);
 653                         if (rc) {
 654                                 pthread_mutex_unlock(&bp->def_cp_lock);
 655                                 return rc;
 656                         }
 657                         bnxt_enable_int(bp);
 658                 }
 659
 660                 pthread_mutex_unlock(&bp->def_cp_lock);
 661         } else {
 662                 /* legacy driver needs to get updated values */
 663                 rc = bnxt_hwrm_func_qcaps(bp);
 664                 if (rc) {
 665                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 666                         return rc;
 667                 }
 668         }
 669
 670         /* Inherit new configurations */
 671         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 672             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 673             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 674                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 675             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 676             bp->max_stat_ctx)
 677                 goto resource_error;
 678
 679         if (BNXT_HAS_RING_GRPS(bp) &&
 680             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 681                 goto resource_error;
 682
 683         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 684             bp->max_vnics < eth_dev->data->nb_rx_queues)
 685                 goto resource_error;
 686
 687         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 688         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 689
 690         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 691                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 692         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 693
 694         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 695                 eth_dev->data->mtu =
 696                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 697                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 698                         BNXT_NUM_VLANS;
 699                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 700         }
 701         return 0;
 702
 703 resource_error:
 704         PMD_DRV_LOG(ERR,
 705                     "Insufficient resources to support requested config\n");
 706         PMD_DRV_LOG(ERR,
 707                     "Num Queues Requested: Tx %d, Rx %d\n",
 708                     eth_dev->data->nb_tx_queues,
 709                     eth_dev->data->nb_rx_queues);
 710         PMD_DRV_LOG(ERR,
 711                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 712                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 713                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 714         return -ENOSPC;
 715 }
 716
 717 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 718 {
 719         struct rte_eth_link *link = &eth_dev->data->dev_link;
 720
 721         if (link->link_status)
 722                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 723                         eth_dev->data->port_id,
 724                         (uint32_t)link->link_speed,
 725                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 726                         ("full-duplex") : ("half-duplex\n"));
 727         else
 728                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 729                         eth_dev->data->port_id);
 730 }
 731
 732 /*
 733  * Determine whether the current configuration requires support for scattered
 734  * receive; return 1 if scattered receive is required and 0 if not.
 735  */
 736 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 737 {
 738         uint16_t buf_size;
 739         int i;
 740
 741         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 742                 return 1;
 743
 744         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 745                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 746
 747                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 748                                       RTE_PKTMBUF_HEADROOM);
 749                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 750                         return 1;
 751         }
 752         return 0;
 753 }
 754
 755 static eth_rx_burst_t
 756 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 757 {
 758         struct bnxt *bp = eth_dev->data->dev_private;
 759
 760 #ifdef RTE_ARCH_X86
 761 #ifndef RTE_LIBRTE_IEEE1588
 762         /*
 763          * Vector mode receive can be enabled only if scatter rx is not
 764          * in use and rx offloads are limited to VLAN stripping and
 765          * CRC stripping.
 766          */
 767         if (!eth_dev->data->scattered_rx &&
 768             !(eth_dev->data->dev_conf.rxmode.offloads &
 769               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 770                 DEV_RX_OFFLOAD_KEEP_CRC |
 771                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 772                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 773                 DEV_RX_OFFLOAD_UDP_CKSUM |
 774                 DEV_RX_OFFLOAD_TCP_CKSUM |
 775                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 776                 DEV_RX_OFFLOAD_RSS_HASH |
 777                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 778                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 779                             eth_dev->data->port_id);
 780                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 781                 return bnxt_recv_pkts_vec;
 782         }
 783         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 784                     eth_dev->data->port_id);
 785         PMD_DRV_LOG(INFO,
 786                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 787                     eth_dev->data->port_id,
 788                     eth_dev->data->scattered_rx,
 789                     eth_dev->data->dev_conf.rxmode.offloads);
 790 #endif
 791 #endif
 792         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 793         return bnxt_recv_pkts;
 794 }
 795
 796 static eth_tx_burst_t
 797 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 798 {
 799 #ifdef RTE_ARCH_X86
 800 #ifndef RTE_LIBRTE_IEEE1588
 801         /*
 802          * Vector mode transmit can be enabled only if not using scatter rx
 803          * or tx offloads.
 804          */
 805         if (!eth_dev->data->scattered_rx &&
 806             !eth_dev->data->dev_conf.txmode.offloads) {
 807                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 808                             eth_dev->data->port_id);
 809                 return bnxt_xmit_pkts_vec;
 810         }
 811         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 812                     eth_dev->data->port_id);
 813         PMD_DRV_LOG(INFO,
 814                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 815                     eth_dev->data->port_id,
 816                     eth_dev->data->scattered_rx,
 817                     eth_dev->data->dev_conf.txmode.offloads);
 818 #endif
 819 #endif
 820         return bnxt_xmit_pkts;
 821 }
 822
 823 static int bnxt_handle_if_change_status(struct bnxt *bp)
 824 {
 825         int rc;
 826
 827         /* Since fw has undergone a reset and lost all contexts,
 828          * set fatal flag to not issue hwrm during cleanup
 829          */
 830         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 831         bnxt_uninit_resources(bp, true);
 832
 833         /* clear fatal flag so that re-init happens */
 834         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 835         rc = bnxt_init_resources(bp, true);
 836
 837         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 838
 839         return rc;
 840 }
 841
 842 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 843 {
 844         struct bnxt *bp = eth_dev->data->dev_private;
 845         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 846         int vlan_mask = 0;
 847         int rc;
 848
 849         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 850                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 851                 return -EINVAL;
 852         }
 853
 854         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 855                 PMD_DRV_LOG(ERR,
 856                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 857                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 858         }
 859
 860         rc = bnxt_hwrm_if_change(bp, 1);
 861         if (!rc) {
 862                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 863                         rc = bnxt_handle_if_change_status(bp);
 864                         if (rc)
 865                                 return rc;
 866                 }
 867         }
 868         bnxt_enable_int(bp);
 869
 870         rc = bnxt_init_chip(bp);
 871         if (rc)
 872                 goto error;
 873
 874         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 875
 876         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 877         bp->dev_stopped = 0;
 878
 879         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 880                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 881         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 882                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 883         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 884         if (rc)
 885                 goto error;
 886
 887         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 888         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 889
 890         eth_dev->data->dev_started = 1;
 891         pthread_mutex_lock(&bp->def_cp_lock);
 892         bnxt_schedule_fw_health_check(bp);
 893         pthread_mutex_unlock(&bp->def_cp_lock);
 894         return 0;
 895
 896 error:
 897         bnxt_hwrm_if_change(bp, 0);
 898         bnxt_shutdown_nic(bp);
 899         bnxt_free_tx_mbufs(bp);
 900         bnxt_free_rx_mbufs(bp);
 901         bp->dev_stopped = 1;
 902         return rc;
 903 }
 904
 905 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 906 {
 907         struct bnxt *bp = eth_dev->data->dev_private;
 908         int rc = 0;
 909
 910         if (!bp->link_info.link_up)
 911                 rc = bnxt_set_hwrm_link_config(bp, true);
 912         if (!rc)
 913                 eth_dev->data->dev_link.link_status = 1;
 914
 915         bnxt_print_link_info(eth_dev);
 916         return rc;
 917 }
 918
 919 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 920 {
 921         struct bnxt *bp = eth_dev->data->dev_private;
 922
 923         eth_dev->data->dev_link.link_status = 0;
 924         bnxt_set_hwrm_link_config(bp, false);
 925         bp->link_info.link_up = 0;
 926
 927         return 0;
 928 }
 929
 930 /* Unload the driver, release resources */
 931 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 932 {
 933         struct bnxt *bp = eth_dev->data->dev_private;
 934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 935         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 936
 937         eth_dev->data->dev_started = 0;
 938         /* Prevent crashes when queues are still in use */
 939         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 940         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 941
 942         bnxt_disable_int(bp);
 943
 944         /* disable uio/vfio intr/eventfd mapping */
 945         rte_intr_disable(intr_handle);
 946
 947         bnxt_cancel_fw_health_check(bp);
 948
 949         bnxt_dev_set_link_down_op(eth_dev);
 950
 951         /* Wait for link to be reset and the async notification to process.
 952          * During reset recovery, there is no need to wait
 953          */
 954         if (!is_bnxt_in_error(bp))
 955                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 956
 957         /* Clean queue intr-vector mapping */
 958         rte_intr_efd_disable(intr_handle);
 959         if (intr_handle->intr_vec != NULL) {
 960                 rte_free(intr_handle->intr_vec);
 961                 intr_handle->intr_vec = NULL;
 962         }
 963
 964         bnxt_hwrm_port_clr_stats(bp);
 965         bnxt_free_tx_mbufs(bp);
 966         bnxt_free_rx_mbufs(bp);
 967         /* Process any remaining notifications in default completion queue */
 968         bnxt_int_handler(eth_dev);
 969         bnxt_shutdown_nic(bp);
 970         bnxt_hwrm_if_change(bp, 0);
 971
 972         rte_free(bp->mark_table);
 973         bp->mark_table = NULL;
 974
 975         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 976         bp->dev_stopped = 1;
 977         bp->rx_cosq_cnt = 0;
 978 }
 979
 980 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 981 {
 982         struct bnxt *bp = eth_dev->data->dev_private;
 983
 984         if (bp->dev_stopped == 0)
 985                 bnxt_dev_stop_op(eth_dev);
 986
 987         bnxt_uninit_resources(bp, false);
 988
 989         eth_dev->dev_ops = NULL;
 990         eth_dev->rx_pkt_burst = NULL;
 991         eth_dev->tx_pkt_burst = NULL;
 992
 993         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
 994         bp->tx_mem_zone = NULL;
 995         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
 996         bp->rx_mem_zone = NULL;
 997
 998         rte_free(bp->pf.vf_info);
 999         bp->pf.vf_info = NULL;
1000
1001         rte_free(bp->grp_info);
1002         bp->grp_info = NULL;
1003 }
1004
1005 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1006                                     uint32_t index)
1007 {
1008         struct bnxt *bp = eth_dev->data->dev_private;
1009         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1010         struct bnxt_vnic_info *vnic;
1011         struct bnxt_filter_info *filter, *temp_filter;
1012         uint32_t i;
1013
1014         if (is_bnxt_in_error(bp))
1015                 return;
1016
1017         /*
1018          * Loop through all VNICs from the specified filter flow pools to
1019          * remove the corresponding MAC addr filter
1020          */
1021         for (i = 0; i < bp->nr_vnics; i++) {
1022                 if (!(pool_mask & (1ULL << i)))
1023                         continue;
1024
1025                 vnic = &bp->vnic_info[i];
1026                 filter = STAILQ_FIRST(&vnic->filter);
1027                 while (filter) {
1028                         temp_filter = STAILQ_NEXT(filter, next);
1029                         if (filter->mac_index == index) {
1030                                 STAILQ_REMOVE(&vnic->filter, filter,
1031                                                 bnxt_filter_info, next);
1032                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1033                                 bnxt_free_filter(bp, filter);
1034                         }
1035                         filter = temp_filter;
1036                 }
1037         }
1038 }
1039
1040 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1041                                struct rte_ether_addr *mac_addr, uint32_t index,
1042                                uint32_t pool)
1043 {
1044         struct bnxt_filter_info *filter;
1045         int rc = 0;
1046
1047         /* Attach requested MAC address to the new l2_filter */
1048         STAILQ_FOREACH(filter, &vnic->filter, next) {
1049                 if (filter->mac_index == index) {
1050                         PMD_DRV_LOG(DEBUG,
1051                                     "MAC addr already existed for pool %d\n",
1052                                     pool);
1053                         return 0;
1054                 }
1055         }
1056
1057         filter = bnxt_alloc_filter(bp);
1058         if (!filter) {
1059                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1060                 return -ENODEV;
1061         }
1062
1063         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1064          * if the MAC that's been programmed now is a different one, then,
1065          * copy that addr to filter->l2_addr
1066          */
1067         if (mac_addr)
1068                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1069         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1070
1071         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1072         if (!rc) {
1073                 filter->mac_index = index;
1074                 if (filter->mac_index == 0)
1075                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1076                 else
1077                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1078         } else {
1079                 bnxt_free_filter(bp, filter);
1080         }
1081
1082         return rc;
1083 }
1084
1085 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1086                                 struct rte_ether_addr *mac_addr,
1087                                 uint32_t index, uint32_t pool)
1088 {
1089         struct bnxt *bp = eth_dev->data->dev_private;
1090         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1091         int rc = 0;
1092
1093         rc = is_bnxt_in_error(bp);
1094         if (rc)
1095                 return rc;
1096
1097         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1098                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1099                 return -ENOTSUP;
1100         }
1101
1102         if (!vnic) {
1103                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1104                 return -EINVAL;
1105         }
1106
1107         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1108
1109         return rc;
1110 }
1111
1112 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1113                      bool exp_link_status)
1114 {
1115         int rc = 0;
1116         struct bnxt *bp = eth_dev->data->dev_private;
1117         struct rte_eth_link new;
1118         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1119                   BNXT_LINK_DOWN_WAIT_CNT;
1120
1121         rc = is_bnxt_in_error(bp);
1122         if (rc)
1123                 return rc;
1124
1125         memset(&new, 0, sizeof(new));
1126         do {
1127                 /* Retrieve link info from hardware */
1128                 rc = bnxt_get_hwrm_link_config(bp, &new);
1129                 if (rc) {
1130                         new.link_speed = ETH_LINK_SPEED_100M;
1131                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1132                         PMD_DRV_LOG(ERR,
1133                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1134                         goto out;
1135                 }
1136
1137                 if (!wait_to_complete || new.link_status == exp_link_status)
1138                         break;
1139
1140                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1141         } while (cnt--);
1142
1143 out:
1144         /* Timed out or success */
1145         if (new.link_status != eth_dev->data->dev_link.link_status ||
1146         new.link_speed != eth_dev->data->dev_link.link_speed) {
1147                 rte_eth_linkstatus_set(eth_dev, &new);
1148
1149                 _rte_eth_dev_callback_process(eth_dev,
1150                                               RTE_ETH_EVENT_INTR_LSC,
1151                                               NULL);
1152
1153                 bnxt_print_link_info(eth_dev);
1154         }
1155
1156         return rc;
1157 }
1158
1159 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1160                                int wait_to_complete)
1161 {
1162         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1163 }
1164
1165 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1166 {
1167         struct bnxt *bp = eth_dev->data->dev_private;
1168         struct bnxt_vnic_info *vnic;
1169         uint32_t old_flags;
1170         int rc;
1171
1172         rc = is_bnxt_in_error(bp);
1173         if (rc)
1174                 return rc;
1175
1176         /* Filter settings will get applied when port is started */
1177         if (bp->dev_stopped == 1)
1178                 return 0;
1179
1180         if (bp->vnic_info == NULL)
1181                 return 0;
1182
1183         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1184
1185         old_flags = vnic->flags;
1186         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1187         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1188         if (rc != 0)
1189                 vnic->flags = old_flags;
1190
1191         return rc;
1192 }
1193
1194 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1195 {
1196         struct bnxt *bp = eth_dev->data->dev_private;
1197         struct bnxt_vnic_info *vnic;
1198         uint32_t old_flags;
1199         int rc;
1200
1201         rc = is_bnxt_in_error(bp);
1202         if (rc)
1203                 return rc;
1204
1205         /* Filter settings will get applied when port is started */
1206         if (bp->dev_stopped == 1)
1207                 return 0;
1208
1209         if (bp->vnic_info == NULL)
1210                 return 0;
1211
1212         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1213
1214         old_flags = vnic->flags;
1215         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1216         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1217         if (rc != 0)
1218                 vnic->flags = old_flags;
1219
1220         return rc;
1221 }
1222
1223 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1224 {
1225         struct bnxt *bp = eth_dev->data->dev_private;
1226         struct bnxt_vnic_info *vnic;
1227         uint32_t old_flags;
1228         int rc;
1229
1230         rc = is_bnxt_in_error(bp);
1231         if (rc)
1232                 return rc;
1233
1234         /* Filter settings will get applied when port is started */
1235         if (bp->dev_stopped == 1)
1236                 return 0;
1237
1238         if (bp->vnic_info == NULL)
1239                 return 0;
1240
1241         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1242
1243         old_flags = vnic->flags;
1244         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1245         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1246         if (rc != 0)
1247                 vnic->flags = old_flags;
1248
1249         return rc;
1250 }
1251
1252 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1253 {
1254         struct bnxt *bp = eth_dev->data->dev_private;
1255         struct bnxt_vnic_info *vnic;
1256         uint32_t old_flags;
1257         int rc;
1258
1259         rc = is_bnxt_in_error(bp);
1260         if (rc)
1261                 return rc;
1262
1263         /* Filter settings will get applied when port is started */
1264         if (bp->dev_stopped == 1)
1265                 return 0;
1266
1267         if (bp->vnic_info == NULL)
1268                 return 0;
1269
1270         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1271
1272         old_flags = vnic->flags;
1273         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1274         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1275         if (rc != 0)
1276                 vnic->flags = old_flags;
1277
1278         return rc;
1279 }
1280
1281 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1282 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1283 {
1284         if (qid >= bp->rx_nr_rings)
1285                 return NULL;
1286
1287         return bp->eth_dev->data->rx_queues[qid];
1288 }
1289
1290 /* Return rxq corresponding to a given rss table ring/group ID. */
1291 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1292 {
1293         struct bnxt_rx_queue *rxq;
1294         unsigned int i;
1295
1296         if (!BNXT_HAS_RING_GRPS(bp)) {
1297                 for (i = 0; i < bp->rx_nr_rings; i++) {
1298                         rxq = bp->eth_dev->data->rx_queues[i];
1299                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1300                                 return rxq->index;
1301                 }
1302         } else {
1303                 for (i = 0; i < bp->rx_nr_rings; i++) {
1304                         if (bp->grp_info[i].fw_grp_id == fwr)
1305                                 return i;
1306                 }
1307         }
1308
1309         return INVALID_HW_RING_ID;
1310 }
1311
1312 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1313                             struct rte_eth_rss_reta_entry64 *reta_conf,
1314                             uint16_t reta_size)
1315 {
1316         struct bnxt *bp = eth_dev->data->dev_private;
1317         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1318         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1319         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1320         uint16_t idx, sft;
1321         int i, rc;
1322
1323         rc = is_bnxt_in_error(bp);
1324         if (rc)
1325                 return rc;
1326
1327         if (!vnic->rss_table)
1328                 return -EINVAL;
1329
1330         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1331                 return -EINVAL;
1332
1333         if (reta_size != tbl_size) {
1334                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1335                         "(%d) must equal the size supported by the hardware "
1336                         "(%d)\n", reta_size, tbl_size);
1337                 return -EINVAL;
1338         }
1339
1340         for (i = 0; i < reta_size; i++) {
1341                 struct bnxt_rx_queue *rxq;
1342
1343                 idx = i / RTE_RETA_GROUP_SIZE;
1344                 sft = i % RTE_RETA_GROUP_SIZE;
1345
1346                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1347                         continue;
1348
1349                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1350                 if (!rxq) {
1351                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1352                         return -EINVAL;
1353                 }
1354
1355                 if (BNXT_CHIP_THOR(bp)) {
1356                         vnic->rss_table[i * 2] =
1357                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1358                         vnic->rss_table[i * 2 + 1] =
1359                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1360                 } else {
1361                         vnic->rss_table[i] =
1362                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1363                 }
1364         }
1365
1366         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1367         return 0;
1368 }
1369
1370 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1371                               struct rte_eth_rss_reta_entry64 *reta_conf,
1372                               uint16_t reta_size)
1373 {
1374         struct bnxt *bp = eth_dev->data->dev_private;
1375         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1376         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1377         uint16_t idx, sft, i;
1378         int rc;
1379
1380         rc = is_bnxt_in_error(bp);
1381         if (rc)
1382                 return rc;
1383
1384         /* Retrieve from the default VNIC */
1385         if (!vnic)
1386                 return -EINVAL;
1387         if (!vnic->rss_table)
1388                 return -EINVAL;
1389
1390         if (reta_size != tbl_size) {
1391                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1392                         "(%d) must equal the size supported by the hardware "
1393                         "(%d)\n", reta_size, tbl_size);
1394                 return -EINVAL;
1395         }
1396
1397         for (idx = 0, i = 0; i < reta_size; i++) {
1398                 idx = i / RTE_RETA_GROUP_SIZE;
1399                 sft = i % RTE_RETA_GROUP_SIZE;
1400
1401                 if (reta_conf[idx].mask & (1ULL << sft)) {
1402                         uint16_t qid;
1403
1404                         if (BNXT_CHIP_THOR(bp))
1405                                 qid = bnxt_rss_to_qid(bp,
1406                                                       vnic->rss_table[i * 2]);
1407                         else
1408                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1409
1410                         if (qid == INVALID_HW_RING_ID) {
1411                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1412                                 return -EINVAL;
1413                         }
1414                         reta_conf[idx].reta[sft] = qid;
1415                 }
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1422                                    struct rte_eth_rss_conf *rss_conf)
1423 {
1424         struct bnxt *bp = eth_dev->data->dev_private;
1425         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1426         struct bnxt_vnic_info *vnic;
1427         int rc;
1428
1429         rc = is_bnxt_in_error(bp);
1430         if (rc)
1431                 return rc;
1432
1433         /*
1434          * If RSS enablement were different than dev_configure,
1435          * then return -EINVAL
1436          */
1437         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1438                 if (!rss_conf->rss_hf)
1439                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1440         } else {
1441                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1442                         return -EINVAL;
1443         }
1444
1445         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1446         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1447
1448         /* Update the default RSS VNIC(s) */
1449         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1450         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1451
1452         /*
1453          * If hashkey is not specified, use the previously configured
1454          * hashkey
1455          */
1456         if (!rss_conf->rss_key)
1457                 goto rss_config;
1458
1459         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1460                 PMD_DRV_LOG(ERR,
1461                             "Invalid hashkey length, should be 16 bytes\n");
1462                 return -EINVAL;
1463         }
1464         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1465
1466 rss_config:
1467         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1468         return 0;
1469 }
1470
1471 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1472                                      struct rte_eth_rss_conf *rss_conf)
1473 {
1474         struct bnxt *bp = eth_dev->data->dev_private;
1475         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1476         int len, rc;
1477         uint32_t hash_types;
1478
1479         rc = is_bnxt_in_error(bp);
1480         if (rc)
1481                 return rc;
1482
1483         /* RSS configuration is the same for all VNICs */
1484         if (vnic && vnic->rss_hash_key) {
1485                 if (rss_conf->rss_key) {
1486                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1487                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1488                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1489                 }
1490
1491                 hash_types = vnic->hash_type;
1492                 rss_conf->rss_hf = 0;
1493                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1494                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1495                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1496                 }
1497                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1498                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1499                         hash_types &=
1500                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1501                 }
1502                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1503                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1504                         hash_types &=
1505                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1506                 }
1507                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1508                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1509                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1510                 }
1511                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1512                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1513                         hash_types &=
1514                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1515                 }
1516                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1517                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1518                         hash_types &=
1519                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1520                 }
1521                 if (hash_types) {
1522                         PMD_DRV_LOG(ERR,
1523                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1524                                 vnic->hash_type);
1525                         return -ENOTSUP;
1526                 }
1527         } else {
1528                 rss_conf->rss_hf = 0;
1529         }
1530         return 0;
1531 }
1532
1533 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1534                                struct rte_eth_fc_conf *fc_conf)
1535 {
1536         struct bnxt *bp = dev->data->dev_private;
1537         struct rte_eth_link link_info;
1538         int rc;
1539
1540         rc = is_bnxt_in_error(bp);
1541         if (rc)
1542                 return rc;
1543
1544         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1545         if (rc)
1546                 return rc;
1547
1548         memset(fc_conf, 0, sizeof(*fc_conf));
1549         if (bp->link_info.auto_pause)
1550                 fc_conf->autoneg = 1;
1551         switch (bp->link_info.pause) {
1552         case 0:
1553                 fc_conf->mode = RTE_FC_NONE;
1554                 break;
1555         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1556                 fc_conf->mode = RTE_FC_TX_PAUSE;
1557                 break;
1558         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1559                 fc_conf->mode = RTE_FC_RX_PAUSE;
1560                 break;
1561         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1562                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1563                 fc_conf->mode = RTE_FC_FULL;
1564                 break;
1565         }
1566         return 0;
1567 }
1568
1569 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1570                                struct rte_eth_fc_conf *fc_conf)
1571 {
1572         struct bnxt *bp = dev->data->dev_private;
1573         int rc;
1574
1575         rc = is_bnxt_in_error(bp);
1576         if (rc)
1577                 return rc;
1578
1579         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1580                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1581                 return -ENOTSUP;
1582         }
1583
1584         switch (fc_conf->mode) {
1585         case RTE_FC_NONE:
1586                 bp->link_info.auto_pause = 0;
1587                 bp->link_info.force_pause = 0;
1588                 break;
1589         case RTE_FC_RX_PAUSE:
1590                 if (fc_conf->autoneg) {
1591                         bp->link_info.auto_pause =
1592                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1593                         bp->link_info.force_pause = 0;
1594                 } else {
1595                         bp->link_info.auto_pause = 0;
1596                         bp->link_info.force_pause =
1597                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1598                 }
1599                 break;
1600         case RTE_FC_TX_PAUSE:
1601                 if (fc_conf->autoneg) {
1602                         bp->link_info.auto_pause =
1603                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1604                         bp->link_info.force_pause = 0;
1605                 } else {
1606                         bp->link_info.auto_pause = 0;
1607                         bp->link_info.force_pause =
1608                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1609                 }
1610                 break;
1611         case RTE_FC_FULL:
1612                 if (fc_conf->autoneg) {
1613                         bp->link_info.auto_pause =
1614                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1615                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1616                         bp->link_info.force_pause = 0;
1617                 } else {
1618                         bp->link_info.auto_pause = 0;
1619                         bp->link_info.force_pause =
1620                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1621                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1622                 }
1623                 break;
1624         }
1625         return bnxt_set_hwrm_link_config(bp, true);
1626 }
1627
1628 /* Add UDP tunneling port */
1629 static int
1630 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1631                          struct rte_eth_udp_tunnel *udp_tunnel)
1632 {
1633         struct bnxt *bp = eth_dev->data->dev_private;
1634         uint16_t tunnel_type = 0;
1635         int rc = 0;
1636
1637         rc = is_bnxt_in_error(bp);
1638         if (rc)
1639                 return rc;
1640
1641         switch (udp_tunnel->prot_type) {
1642         case RTE_TUNNEL_TYPE_VXLAN:
1643                 if (bp->vxlan_port_cnt) {
1644                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1645                                 udp_tunnel->udp_port);
1646                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1647                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1648                                 return -ENOSPC;
1649                         }
1650                         bp->vxlan_port_cnt++;
1651                         return 0;
1652                 }
1653                 tunnel_type =
1654                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1655                 bp->vxlan_port_cnt++;
1656                 break;
1657         case RTE_TUNNEL_TYPE_GENEVE:
1658                 if (bp->geneve_port_cnt) {
1659                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1660                                 udp_tunnel->udp_port);
1661                         if (bp->geneve_port != udp_tunnel->udp_port) {
1662                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1663                                 return -ENOSPC;
1664                         }
1665                         bp->geneve_port_cnt++;
1666                         return 0;
1667                 }
1668                 tunnel_type =
1669                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1670                 bp->geneve_port_cnt++;
1671                 break;
1672         default:
1673                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1674                 return -ENOTSUP;
1675         }
1676         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1677                                              tunnel_type);
1678         return rc;
1679 }
1680
1681 static int
1682 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1683                          struct rte_eth_udp_tunnel *udp_tunnel)
1684 {
1685         struct bnxt *bp = eth_dev->data->dev_private;
1686         uint16_t tunnel_type = 0;
1687         uint16_t port = 0;
1688         int rc = 0;
1689
1690         rc = is_bnxt_in_error(bp);
1691         if (rc)
1692                 return rc;
1693
1694         switch (udp_tunnel->prot_type) {
1695         case RTE_TUNNEL_TYPE_VXLAN:
1696                 if (!bp->vxlan_port_cnt) {
1697                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1698                         return -EINVAL;
1699                 }
1700                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1701                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1702                                 udp_tunnel->udp_port, bp->vxlan_port);
1703                         return -EINVAL;
1704                 }
1705                 if (--bp->vxlan_port_cnt)
1706                         return 0;
1707
1708                 tunnel_type =
1709                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1710                 port = bp->vxlan_fw_dst_port_id;
1711                 break;
1712         case RTE_TUNNEL_TYPE_GENEVE:
1713                 if (!bp->geneve_port_cnt) {
1714                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1715                         return -EINVAL;
1716                 }
1717                 if (bp->geneve_port != udp_tunnel->udp_port) {
1718                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1719                                 udp_tunnel->udp_port, bp->geneve_port);
1720                         return -EINVAL;
1721                 }
1722                 if (--bp->geneve_port_cnt)
1723                         return 0;
1724
1725                 tunnel_type =
1726                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1727                 port = bp->geneve_fw_dst_port_id;
1728                 break;
1729         default:
1730                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1731                 return -ENOTSUP;
1732         }
1733
1734         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1735         if (!rc) {
1736                 if (tunnel_type ==
1737                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1738                         bp->vxlan_port = 0;
1739                 if (tunnel_type ==
1740                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1741                         bp->geneve_port = 0;
1742         }
1743         return rc;
1744 }
1745
1746 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1747 {
1748         struct bnxt_filter_info *filter;
1749         struct bnxt_vnic_info *vnic;
1750         int rc = 0;
1751         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1752
1753         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1754         filter = STAILQ_FIRST(&vnic->filter);
1755         while (filter) {
1756                 /* Search for this matching MAC+VLAN filter */
1757                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1758                         /* Delete the filter */
1759                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1760                         if (rc)
1761                                 return rc;
1762                         STAILQ_REMOVE(&vnic->filter, filter,
1763                                       bnxt_filter_info, next);
1764                         bnxt_free_filter(bp, filter);
1765                         PMD_DRV_LOG(INFO,
1766                                     "Deleted vlan filter for %d\n",
1767                                     vlan_id);
1768                         return 0;
1769                 }
1770                 filter = STAILQ_NEXT(filter, next);
1771         }
1772         return -ENOENT;
1773 }
1774
1775 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1776 {
1777         struct bnxt_filter_info *filter;
1778         struct bnxt_vnic_info *vnic;
1779         int rc = 0;
1780         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1781                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1782         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1783
1784         /* Implementation notes on the use of VNIC in this command:
1785          *
1786          * By default, these filters belong to default vnic for the function.
1787          * Once these filters are set up, only destination VNIC can be modified.
1788          * If the destination VNIC is not specified in this command,
1789          * then the HWRM shall only create an l2 context id.
1790          */
1791
1792         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1793         filter = STAILQ_FIRST(&vnic->filter);
1794         /* Check if the VLAN has already been added */
1795         while (filter) {
1796                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1797                         return -EEXIST;
1798
1799                 filter = STAILQ_NEXT(filter, next);
1800         }
1801
1802         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1803          * command to create MAC+VLAN filter with the right flags, enables set.
1804          */
1805         filter = bnxt_alloc_filter(bp);
1806         if (!filter) {
1807                 PMD_DRV_LOG(ERR,
1808                             "MAC/VLAN filter alloc failed\n");
1809                 return -ENOMEM;
1810         }
1811         /* MAC + VLAN ID filter */
1812         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1813          * untagged packets are received
1814          *
1815          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1816          * packets and only the programmed vlan's packets are received
1817          */
1818         filter->l2_ivlan = vlan_id;
1819         filter->l2_ivlan_mask = 0x0FFF;
1820         filter->enables |= en;
1821         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1822
1823         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1824         if (rc) {
1825                 /* Free the newly allocated filter as we were
1826                  * not able to create the filter in hardware.
1827                  */
1828                 bnxt_free_filter(bp, filter);
1829                 return rc;
1830         }
1831
1832         filter->mac_index = 0;
1833         /* Add this new filter to the list */
1834         if (vlan_id == 0)
1835                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1836         else
1837                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1838
1839         PMD_DRV_LOG(INFO,
1840                     "Added Vlan filter for %d\n", vlan_id);
1841         return rc;
1842 }
1843
1844 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1845                 uint16_t vlan_id, int on)
1846 {
1847         struct bnxt *bp = eth_dev->data->dev_private;
1848         int rc;
1849
1850         rc = is_bnxt_in_error(bp);
1851         if (rc)
1852                 return rc;
1853
1854         /* These operations apply to ALL existing MAC/VLAN filters */
1855         if (on)
1856                 return bnxt_add_vlan_filter(bp, vlan_id);
1857         else
1858                 return bnxt_del_vlan_filter(bp, vlan_id);
1859 }
1860
1861 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1862                                     struct bnxt_vnic_info *vnic)
1863 {
1864         struct bnxt_filter_info *filter;
1865         int rc;
1866
1867         filter = STAILQ_FIRST(&vnic->filter);
1868         while (filter) {
1869                 if (filter->mac_index == 0 &&
1870                     !memcmp(filter->l2_addr, bp->mac_addr,
1871                             RTE_ETHER_ADDR_LEN)) {
1872                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1873                         if (!rc) {
1874                                 STAILQ_REMOVE(&vnic->filter, filter,
1875                                               bnxt_filter_info, next);
1876                                 bnxt_free_filter(bp, filter);
1877                         }
1878                         return rc;
1879                 }
1880                 filter = STAILQ_NEXT(filter, next);
1881         }
1882         return 0;
1883 }
1884
1885 static int
1886 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1887 {
1888         struct bnxt_vnic_info *vnic;
1889         unsigned int i;
1890         int rc;
1891
1892         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1893         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1894                 /* Remove any VLAN filters programmed */
1895                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1896                         bnxt_del_vlan_filter(bp, i);
1897
1898                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1899                 if (rc)
1900                         return rc;
1901         } else {
1902                 /* Default filter will allow packets that match the
1903                  * dest mac. So, it has to be deleted, otherwise, we
1904                  * will endup receiving vlan packets for which the
1905                  * filter is not programmed, when hw-vlan-filter
1906                  * configuration is ON
1907                  */
1908                 bnxt_del_dflt_mac_filter(bp, vnic);
1909                 /* This filter will allow only untagged packets */
1910                 bnxt_add_vlan_filter(bp, 0);
1911         }
1912         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1913                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1914
1915         return 0;
1916 }
1917
1918 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1919 {
1920         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1921         unsigned int i;
1922         int rc;
1923
1924         /* Destroy vnic filters and vnic */
1925         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1926             DEV_RX_OFFLOAD_VLAN_FILTER) {
1927                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1928                         bnxt_del_vlan_filter(bp, i);
1929         }
1930         bnxt_del_dflt_mac_filter(bp, vnic);
1931
1932         rc = bnxt_hwrm_vnic_free(bp, vnic);
1933         if (rc)
1934                 return rc;
1935
1936         rte_free(vnic->fw_grp_ids);
1937         vnic->fw_grp_ids = NULL;
1938
1939         return 0;
1940 }
1941
1942 static int
1943 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1944 {
1945         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1946         int rc;
1947
1948         /* Destroy, recreate and reconfigure the default vnic */
1949         rc = bnxt_free_one_vnic(bp, 0);
1950         if (rc)
1951                 return rc;
1952
1953         /* default vnic 0 */
1954         rc = bnxt_setup_one_vnic(bp, 0);
1955         if (rc)
1956                 return rc;
1957
1958         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1959             DEV_RX_OFFLOAD_VLAN_FILTER) {
1960                 rc = bnxt_add_vlan_filter(bp, 0);
1961                 bnxt_restore_vlan_filters(bp);
1962         } else {
1963                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1964         }
1965
1966         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1967         if (rc)
1968                 return rc;
1969
1970         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1971                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1972
1973         return rc;
1974 }
1975
1976 static int
1977 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1978 {
1979         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1980         struct bnxt *bp = dev->data->dev_private;
1981         int rc;
1982
1983         rc = is_bnxt_in_error(bp);
1984         if (rc)
1985                 return rc;
1986
1987         /* Filter settings will get applied when port is started */
1988         if (bp->dev_stopped == 1)
1989                 return 0;
1990
1991         if (mask & ETH_VLAN_FILTER_MASK) {
1992                 /* Enable or disable VLAN filtering */
1993                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
1994                 if (rc)
1995                         return rc;
1996         }
1997
1998         if (mask & ETH_VLAN_STRIP_MASK) {
1999                 /* Enable or disable VLAN stripping */
2000                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2001                 if (rc)
2002                         return rc;
2003         }
2004
2005         if (mask & ETH_VLAN_EXTEND_MASK) {
2006                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2007                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2008                 else
2009                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2010         }
2011
2012         return 0;
2013 }
2014
2015 static int
2016 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2017                       uint16_t tpid)
2018 {
2019         struct bnxt *bp = dev->data->dev_private;
2020         int qinq = dev->data->dev_conf.rxmode.offloads &
2021                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2022
2023         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2024             vlan_type != ETH_VLAN_TYPE_OUTER) {
2025                 PMD_DRV_LOG(ERR,
2026                             "Unsupported vlan type.");
2027                 return -EINVAL;
2028         }
2029         if (!qinq) {
2030                 PMD_DRV_LOG(ERR,
2031                             "QinQ not enabled. Needs to be ON as we can "
2032                             "accelerate only outer vlan\n");
2033                 return -EINVAL;
2034         }
2035
2036         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2037                 switch (tpid) {
2038                 case RTE_ETHER_TYPE_QINQ:
2039                         bp->outer_tpid_bd =
2040                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2041                                 break;
2042                 case RTE_ETHER_TYPE_VLAN:
2043                         bp->outer_tpid_bd =
2044                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2045                                 break;
2046                 case 0x9100:
2047                         bp->outer_tpid_bd =
2048                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2049                                 break;
2050                 case 0x9200:
2051                         bp->outer_tpid_bd =
2052                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2053                                 break;
2054                 case 0x9300:
2055                         bp->outer_tpid_bd =
2056                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2057                                 break;
2058                 default:
2059                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2060                         return -EINVAL;
2061                 }
2062                 bp->outer_tpid_bd |= tpid;
2063                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2064         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2065                 PMD_DRV_LOG(ERR,
2066                             "Can accelerate only outer vlan in QinQ\n");
2067                 return -EINVAL;
2068         }
2069
2070         return 0;
2071 }
2072
2073 static int
2074 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2075                              struct rte_ether_addr *addr)
2076 {
2077         struct bnxt *bp = dev->data->dev_private;
2078         /* Default Filter is tied to VNIC 0 */
2079         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2080         int rc;
2081
2082         rc = is_bnxt_in_error(bp);
2083         if (rc)
2084                 return rc;
2085
2086         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2087                 return -EPERM;
2088
2089         if (rte_is_zero_ether_addr(addr))
2090                 return -EINVAL;
2091
2092         /* Check if the requested MAC is already added */
2093         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2094                 return 0;
2095
2096         /* Destroy filter and re-create it */
2097         bnxt_del_dflt_mac_filter(bp, vnic);
2098
2099         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2100         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2101                 /* This filter will allow only untagged packets */
2102                 rc = bnxt_add_vlan_filter(bp, 0);
2103         } else {
2104                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2105         }
2106
2107         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2108         return rc;
2109 }
2110
2111 static int
2112 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2113                           struct rte_ether_addr *mc_addr_set,
2114                           uint32_t nb_mc_addr)
2115 {
2116         struct bnxt *bp = eth_dev->data->dev_private;
2117         char *mc_addr_list = (char *)mc_addr_set;
2118         struct bnxt_vnic_info *vnic;
2119         uint32_t off = 0, i = 0;
2120         int rc;
2121
2122         rc = is_bnxt_in_error(bp);
2123         if (rc)
2124                 return rc;
2125
2126         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2127
2128         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2129                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2130                 goto allmulti;
2131         }
2132
2133         /* TODO Check for Duplicate mcast addresses */
2134         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2135         for (i = 0; i < nb_mc_addr; i++) {
2136                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2137                         RTE_ETHER_ADDR_LEN);
2138                 off += RTE_ETHER_ADDR_LEN;
2139         }
2140
2141         vnic->mc_addr_cnt = i;
2142         if (vnic->mc_addr_cnt)
2143                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2144         else
2145                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2146
2147 allmulti:
2148         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2149 }
2150
2151 static int
2152 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2153 {
2154         struct bnxt *bp = dev->data->dev_private;
2155         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2156         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2157         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2158         int ret;
2159
2160         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2161                         fw_major, fw_minor, fw_updt);
2162
2163         ret += 1; /* add the size of '\0' */
2164         if (fw_size < (uint32_t)ret)
2165                 return ret;
2166         else
2167                 return 0;
2168 }
2169
2170 static void
2171 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2172         struct rte_eth_rxq_info *qinfo)
2173 {
2174         struct bnxt *bp = dev->data->dev_private;
2175         struct bnxt_rx_queue *rxq;
2176
2177         if (is_bnxt_in_error(bp))
2178                 return;
2179
2180         rxq = dev->data->rx_queues[queue_id];
2181
2182         qinfo->mp = rxq->mb_pool;
2183         qinfo->scattered_rx = dev->data->scattered_rx;
2184         qinfo->nb_desc = rxq->nb_rx_desc;
2185
2186         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2187         qinfo->conf.rx_drop_en = 0;
2188         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2189 }
2190
2191 static void
2192 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2193         struct rte_eth_txq_info *qinfo)
2194 {
2195         struct bnxt *bp = dev->data->dev_private;
2196         struct bnxt_tx_queue *txq;
2197
2198         if (is_bnxt_in_error(bp))
2199                 return;
2200
2201         txq = dev->data->tx_queues[queue_id];
2202
2203         qinfo->nb_desc = txq->nb_tx_desc;
2204
2205         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2206         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2207         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2208
2209         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2210         qinfo->conf.tx_rs_thresh = 0;
2211         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2212 }
2213
2214 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2215 {
2216         struct bnxt *bp = eth_dev->data->dev_private;
2217         uint32_t new_pkt_size;
2218         uint32_t rc = 0;
2219         uint32_t i;
2220
2221         rc = is_bnxt_in_error(bp);
2222         if (rc)
2223                 return rc;
2224
2225         /* Exit if receive queues are not configured yet */
2226         if (!eth_dev->data->nb_rx_queues)
2227                 return rc;
2228
2229         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2230                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2231
2232 #ifdef RTE_ARCH_X86
2233         /*
2234          * If vector-mode tx/rx is active, disallow any MTU change that would
2235          * require scattered receive support.
2236          */
2237         if (eth_dev->data->dev_started &&
2238             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2239              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2240             (new_pkt_size >
2241              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2242                 PMD_DRV_LOG(ERR,
2243                             "MTU change would require scattered rx support. ");
2244                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2245                 return -EINVAL;
2246         }
2247 #endif
2248
2249         if (new_mtu > RTE_ETHER_MTU) {
2250                 bp->flags |= BNXT_FLAG_JUMBO;
2251                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2252                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2253         } else {
2254                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2255                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2256                 bp->flags &= ~BNXT_FLAG_JUMBO;
2257         }
2258
2259         /* Is there a change in mtu setting? */
2260         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2261                 return rc;
2262
2263         for (i = 0; i < bp->nr_vnics; i++) {
2264                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2265                 uint16_t size = 0;
2266
2267                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2268                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2269                 if (rc)
2270                         break;
2271
2272                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2273                 size -= RTE_PKTMBUF_HEADROOM;
2274
2275                 if (size < new_mtu) {
2276                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2277                         if (rc)
2278                                 return rc;
2279                 }
2280         }
2281
2282         if (!rc)
2283                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2284
2285         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2286
2287         return rc;
2288 }
2289
2290 static int
2291 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2292 {
2293         struct bnxt *bp = dev->data->dev_private;
2294         uint16_t vlan = bp->vlan;
2295         int rc;
2296
2297         rc = is_bnxt_in_error(bp);
2298         if (rc)
2299                 return rc;
2300
2301         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2302                 PMD_DRV_LOG(ERR,
2303                         "PVID cannot be modified for this function\n");
2304                 return -ENOTSUP;
2305         }
2306         bp->vlan = on ? pvid : 0;
2307
2308         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2309         if (rc)
2310                 bp->vlan = vlan;
2311         return rc;
2312 }
2313
2314 static int
2315 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2316 {
2317         struct bnxt *bp = dev->data->dev_private;
2318         int rc;
2319
2320         rc = is_bnxt_in_error(bp);
2321         if (rc)
2322                 return rc;
2323
2324         return bnxt_hwrm_port_led_cfg(bp, true);
2325 }
2326
2327 static int
2328 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2329 {
2330         struct bnxt *bp = dev->data->dev_private;
2331         int rc;
2332
2333         rc = is_bnxt_in_error(bp);
2334         if (rc)
2335                 return rc;
2336
2337         return bnxt_hwrm_port_led_cfg(bp, false);
2338 }
2339
2340 static uint32_t
2341 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2342 {
2343         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2344         uint32_t desc = 0, raw_cons = 0, cons;
2345         struct bnxt_cp_ring_info *cpr;
2346         struct bnxt_rx_queue *rxq;
2347         struct rx_pkt_cmpl *rxcmp;
2348         int rc;
2349
2350         rc = is_bnxt_in_error(bp);
2351         if (rc)
2352                 return rc;
2353
2354         rxq = dev->data->rx_queues[rx_queue_id];
2355         cpr = rxq->cp_ring;
2356         raw_cons = cpr->cp_raw_cons;
2357
2358         while (1) {
2359                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2360                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2361                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2362
2363                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2364                         break;
2365                 } else {
2366                         raw_cons++;
2367                         desc++;
2368                 }
2369         }
2370
2371         return desc;
2372 }
2373
2374 static int
2375 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2376 {
2377         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2378         struct bnxt_rx_ring_info *rxr;
2379         struct bnxt_cp_ring_info *cpr;
2380         struct bnxt_sw_rx_bd *rx_buf;
2381         struct rx_pkt_cmpl *rxcmp;
2382         uint32_t cons, cp_cons;
2383         int rc;
2384
2385         if (!rxq)
2386                 return -EINVAL;
2387
2388         rc = is_bnxt_in_error(rxq->bp);
2389         if (rc)
2390                 return rc;
2391
2392         cpr = rxq->cp_ring;
2393         rxr = rxq->rx_ring;
2394
2395         if (offset >= rxq->nb_rx_desc)
2396                 return -EINVAL;
2397
2398         cons = RING_CMP(cpr->cp_ring_struct, offset);
2399         cp_cons = cpr->cp_raw_cons;
2400         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2401
2402         if (cons > cp_cons) {
2403                 if (CMPL_VALID(rxcmp, cpr->valid))
2404                         return RTE_ETH_RX_DESC_DONE;
2405         } else {
2406                 if (CMPL_VALID(rxcmp, !cpr->valid))
2407                         return RTE_ETH_RX_DESC_DONE;
2408         }
2409         rx_buf = &rxr->rx_buf_ring[cons];
2410         if (rx_buf->mbuf == NULL)
2411                 return RTE_ETH_RX_DESC_UNAVAIL;
2412
2413
2414         return RTE_ETH_RX_DESC_AVAIL;
2415 }
2416
2417 static int
2418 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2419 {
2420         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2421         struct bnxt_tx_ring_info *txr;
2422         struct bnxt_cp_ring_info *cpr;
2423         struct bnxt_sw_tx_bd *tx_buf;
2424         struct tx_pkt_cmpl *txcmp;
2425         uint32_t cons, cp_cons;
2426         int rc;
2427
2428         if (!txq)
2429                 return -EINVAL;
2430
2431         rc = is_bnxt_in_error(txq->bp);
2432         if (rc)
2433                 return rc;
2434
2435         cpr = txq->cp_ring;
2436         txr = txq->tx_ring;
2437
2438         if (offset >= txq->nb_tx_desc)
2439                 return -EINVAL;
2440
2441         cons = RING_CMP(cpr->cp_ring_struct, offset);
2442         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2443         cp_cons = cpr->cp_raw_cons;
2444
2445         if (cons > cp_cons) {
2446                 if (CMPL_VALID(txcmp, cpr->valid))
2447                         return RTE_ETH_TX_DESC_UNAVAIL;
2448         } else {
2449                 if (CMPL_VALID(txcmp, !cpr->valid))
2450                         return RTE_ETH_TX_DESC_UNAVAIL;
2451         }
2452         tx_buf = &txr->tx_buf_ring[cons];
2453         if (tx_buf->mbuf == NULL)
2454                 return RTE_ETH_TX_DESC_DONE;
2455
2456         return RTE_ETH_TX_DESC_FULL;
2457 }
2458
2459 static struct bnxt_filter_info *
2460 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2461                                 struct rte_eth_ethertype_filter *efilter,
2462                                 struct bnxt_vnic_info *vnic0,
2463                                 struct bnxt_vnic_info *vnic,
2464                                 int *ret)
2465 {
2466         struct bnxt_filter_info *mfilter = NULL;
2467         int match = 0;
2468         *ret = 0;
2469
2470         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2471                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2472                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2473                         " ethertype filter.", efilter->ether_type);
2474                 *ret = -EINVAL;
2475                 goto exit;
2476         }
2477         if (efilter->queue >= bp->rx_nr_rings) {
2478                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2479                 *ret = -EINVAL;
2480                 goto exit;
2481         }
2482
2483         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2484         vnic = &bp->vnic_info[efilter->queue];
2485         if (vnic == NULL) {
2486                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2487                 *ret = -EINVAL;
2488                 goto exit;
2489         }
2490
2491         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2492                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2493                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2494                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2495                              mfilter->flags ==
2496                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2497                              mfilter->ethertype == efilter->ether_type)) {
2498                                 match = 1;
2499                                 break;
2500                         }
2501                 }
2502         } else {
2503                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2504                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2505                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2506                              mfilter->ethertype == efilter->ether_type &&
2507                              mfilter->flags ==
2508                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2509                                 match = 1;
2510                                 break;
2511                         }
2512         }
2513
2514         if (match)
2515                 *ret = -EEXIST;
2516
2517 exit:
2518         return mfilter;
2519 }
2520
2521 static int
2522 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2523                         enum rte_filter_op filter_op,
2524                         void *arg)
2525 {
2526         struct bnxt *bp = dev->data->dev_private;
2527         struct rte_eth_ethertype_filter *efilter =
2528                         (struct rte_eth_ethertype_filter *)arg;
2529         struct bnxt_filter_info *bfilter, *filter1;
2530         struct bnxt_vnic_info *vnic, *vnic0;
2531         int ret;
2532
2533         if (filter_op == RTE_ETH_FILTER_NOP)
2534                 return 0;
2535
2536         if (arg == NULL) {
2537                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2538                             filter_op);
2539                 return -EINVAL;
2540         }
2541
2542         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2543         vnic = &bp->vnic_info[efilter->queue];
2544
2545         switch (filter_op) {
2546         case RTE_ETH_FILTER_ADD:
2547                 bnxt_match_and_validate_ether_filter(bp, efilter,
2548                                                         vnic0, vnic, &ret);
2549                 if (ret < 0)
2550                         return ret;
2551
2552                 bfilter = bnxt_get_unused_filter(bp);
2553                 if (bfilter == NULL) {
2554                         PMD_DRV_LOG(ERR,
2555                                 "Not enough resources for a new filter.\n");
2556                         return -ENOMEM;
2557                 }
2558                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2559                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2560                        RTE_ETHER_ADDR_LEN);
2561                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2562                        RTE_ETHER_ADDR_LEN);
2563                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2564                 bfilter->ethertype = efilter->ether_type;
2565                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2566
2567                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2568                 if (filter1 == NULL) {
2569                         ret = -EINVAL;
2570                         goto cleanup;
2571                 }
2572                 bfilter->enables |=
2573                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2574                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2575
2576                 bfilter->dst_id = vnic->fw_vnic_id;
2577
2578                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2579                         bfilter->flags =
2580                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2581                 }
2582
2583                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2584                 if (ret)
2585                         goto cleanup;
2586                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2587                 break;
2588         case RTE_ETH_FILTER_DELETE:
2589                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2590                                                         vnic0, vnic, &ret);
2591                 if (ret == -EEXIST) {
2592                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2593
2594                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2595                                       next);
2596                         bnxt_free_filter(bp, filter1);
2597                 } else if (ret == 0) {
2598                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2599                 }
2600                 break;
2601         default:
2602                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2603                 ret = -EINVAL;
2604                 goto error;
2605         }
2606         return ret;
2607 cleanup:
2608         bnxt_free_filter(bp, bfilter);
2609 error:
2610         return ret;
2611 }
2612
2613 static inline int
2614 parse_ntuple_filter(struct bnxt *bp,
2615                     struct rte_eth_ntuple_filter *nfilter,
2616                     struct bnxt_filter_info *bfilter)
2617 {
2618         uint32_t en = 0;
2619
2620         if (nfilter->queue >= bp->rx_nr_rings) {
2621                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2622                 return -EINVAL;
2623         }
2624
2625         switch (nfilter->dst_port_mask) {
2626         case UINT16_MAX:
2627                 bfilter->dst_port_mask = -1;
2628                 bfilter->dst_port = nfilter->dst_port;
2629                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2630                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2631                 break;
2632         default:
2633                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2634                 return -EINVAL;
2635         }
2636
2637         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2638         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2639
2640         switch (nfilter->proto_mask) {
2641         case UINT8_MAX:
2642                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2643                         bfilter->ip_protocol = 17;
2644                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2645                         bfilter->ip_protocol = 6;
2646                 else
2647                         return -EINVAL;
2648                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2649                 break;
2650         default:
2651                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2652                 return -EINVAL;
2653         }
2654
2655         switch (nfilter->dst_ip_mask) {
2656         case UINT32_MAX:
2657                 bfilter->dst_ipaddr_mask[0] = -1;
2658                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2659                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2660                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2661                 break;
2662         default:
2663                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2664                 return -EINVAL;
2665         }
2666
2667         switch (nfilter->src_ip_mask) {
2668         case UINT32_MAX:
2669                 bfilter->src_ipaddr_mask[0] = -1;
2670                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2671                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2672                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2673                 break;
2674         default:
2675                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2676                 return -EINVAL;
2677         }
2678
2679         switch (nfilter->src_port_mask) {
2680         case UINT16_MAX:
2681                 bfilter->src_port_mask = -1;
2682                 bfilter->src_port = nfilter->src_port;
2683                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2684                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2685                 break;
2686         default:
2687                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2688                 return -EINVAL;
2689         }
2690
2691         bfilter->enables = en;
2692         return 0;
2693 }
2694
2695 static struct bnxt_filter_info*
2696 bnxt_match_ntuple_filter(struct bnxt *bp,
2697                          struct bnxt_filter_info *bfilter,
2698                          struct bnxt_vnic_info **mvnic)
2699 {
2700         struct bnxt_filter_info *mfilter = NULL;
2701         int i;
2702
2703         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2704                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2705                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2706                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2707                             bfilter->src_ipaddr_mask[0] ==
2708                             mfilter->src_ipaddr_mask[0] &&
2709                             bfilter->src_port == mfilter->src_port &&
2710                             bfilter->src_port_mask == mfilter->src_port_mask &&
2711                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2712                             bfilter->dst_ipaddr_mask[0] ==
2713                             mfilter->dst_ipaddr_mask[0] &&
2714                             bfilter->dst_port == mfilter->dst_port &&
2715                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2716                             bfilter->flags == mfilter->flags &&
2717                             bfilter->enables == mfilter->enables) {
2718                                 if (mvnic)
2719                                         *mvnic = vnic;
2720                                 return mfilter;
2721                         }
2722                 }
2723         }
2724         return NULL;
2725 }
2726
2727 static int
2728 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2729                        struct rte_eth_ntuple_filter *nfilter,
2730                        enum rte_filter_op filter_op)
2731 {
2732         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2733         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2734         int ret;
2735
2736         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2737                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2738                 return -EINVAL;
2739         }
2740
2741         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2742                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2743                 return -EINVAL;
2744         }
2745
2746         bfilter = bnxt_get_unused_filter(bp);
2747         if (bfilter == NULL) {
2748                 PMD_DRV_LOG(ERR,
2749                         "Not enough resources for a new filter.\n");
2750                 return -ENOMEM;
2751         }
2752         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2753         if (ret < 0)
2754                 goto free_filter;
2755
2756         vnic = &bp->vnic_info[nfilter->queue];
2757         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2758         filter1 = STAILQ_FIRST(&vnic0->filter);
2759         if (filter1 == NULL) {
2760                 ret = -EINVAL;
2761                 goto free_filter;
2762         }
2763
2764         bfilter->dst_id = vnic->fw_vnic_id;
2765         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2766         bfilter->enables |=
2767                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2768         bfilter->ethertype = 0x800;
2769         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2770
2771         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2772
2773         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2774             bfilter->dst_id == mfilter->dst_id) {
2775                 PMD_DRV_LOG(ERR, "filter exists.\n");
2776                 ret = -EEXIST;
2777                 goto free_filter;
2778         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2779                    bfilter->dst_id != mfilter->dst_id) {
2780                 mfilter->dst_id = vnic->fw_vnic_id;
2781                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2782                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2783                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2784                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2785                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2786                 goto free_filter;
2787         }
2788         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2789                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2790                 ret = -ENOENT;
2791                 goto free_filter;
2792         }
2793
2794         if (filter_op == RTE_ETH_FILTER_ADD) {
2795                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2796                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2797                 if (ret)
2798                         goto free_filter;
2799                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2800         } else {
2801                 if (mfilter == NULL) {
2802                         /* This should not happen. But for Coverity! */
2803                         ret = -ENOENT;
2804                         goto free_filter;
2805                 }
2806                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2807
2808                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2809                 bnxt_free_filter(bp, mfilter);
2810                 bnxt_free_filter(bp, bfilter);
2811         }
2812
2813         return 0;
2814 free_filter:
2815         bnxt_free_filter(bp, bfilter);
2816         return ret;
2817 }
2818
2819 static int
2820 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2821                         enum rte_filter_op filter_op,
2822                         void *arg)
2823 {
2824         struct bnxt *bp = dev->data->dev_private;
2825         int ret;
2826
2827         if (filter_op == RTE_ETH_FILTER_NOP)
2828                 return 0;
2829
2830         if (arg == NULL) {
2831                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2832                             filter_op);
2833                 return -EINVAL;
2834         }
2835
2836         switch (filter_op) {
2837         case RTE_ETH_FILTER_ADD:
2838                 ret = bnxt_cfg_ntuple_filter(bp,
2839                         (struct rte_eth_ntuple_filter *)arg,
2840                         filter_op);
2841                 break;
2842         case RTE_ETH_FILTER_DELETE:
2843                 ret = bnxt_cfg_ntuple_filter(bp,
2844                         (struct rte_eth_ntuple_filter *)arg,
2845                         filter_op);
2846                 break;
2847         default:
2848                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2849                 ret = -EINVAL;
2850                 break;
2851         }
2852         return ret;
2853 }
2854
2855 static int
2856 bnxt_parse_fdir_filter(struct bnxt *bp,
2857                        struct rte_eth_fdir_filter *fdir,
2858                        struct bnxt_filter_info *filter)
2859 {
2860         enum rte_fdir_mode fdir_mode =
2861                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2862         struct bnxt_vnic_info *vnic0, *vnic;
2863         struct bnxt_filter_info *filter1;
2864         uint32_t en = 0;
2865         int i;
2866
2867         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2868                 return -EINVAL;
2869
2870         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2871         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2872
2873         switch (fdir->input.flow_type) {
2874         case RTE_ETH_FLOW_IPV4:
2875         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2876                 /* FALLTHROUGH */
2877                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2878                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2879                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2881                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2882                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2883                 filter->ip_addr_type =
2884                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2885                 filter->src_ipaddr_mask[0] = 0xffffffff;
2886                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2887                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2888                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2889                 filter->ethertype = 0x800;
2890                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2891                 break;
2892         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2893                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2895                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2896                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2897                 filter->dst_port_mask = 0xffff;
2898                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2899                 filter->src_port_mask = 0xffff;
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2901                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2902                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2903                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2905                 filter->ip_protocol = 6;
2906                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2907                 filter->ip_addr_type =
2908                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2909                 filter->src_ipaddr_mask[0] = 0xffffffff;
2910                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2911                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2912                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2913                 filter->ethertype = 0x800;
2914                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2915                 break;
2916         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2917                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2919                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2920                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2921                 filter->dst_port_mask = 0xffff;
2922                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2923                 filter->src_port_mask = 0xffff;
2924                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2925                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2926                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2927                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2928                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2929                 filter->ip_protocol = 17;
2930                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2931                 filter->ip_addr_type =
2932                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2933                 filter->src_ipaddr_mask[0] = 0xffffffff;
2934                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2935                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2936                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2937                 filter->ethertype = 0x800;
2938                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2939                 break;
2940         case RTE_ETH_FLOW_IPV6:
2941         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2942                 /* FALLTHROUGH */
2943                 filter->ip_addr_type =
2944                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2945                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2946                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2947                 rte_memcpy(filter->src_ipaddr,
2948                            fdir->input.flow.ipv6_flow.src_ip, 16);
2949                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2950                 rte_memcpy(filter->dst_ipaddr,
2951                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2952                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2953                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2954                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2955                 memset(filter->src_ipaddr_mask, 0xff, 16);
2956                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2957                 filter->ethertype = 0x86dd;
2958                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2959                 break;
2960         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2961                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2962                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2963                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2964                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2965                 filter->dst_port_mask = 0xffff;
2966                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2967                 filter->src_port_mask = 0xffff;
2968                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2969                 filter->ip_addr_type =
2970                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2971                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2972                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2973                 rte_memcpy(filter->src_ipaddr,
2974                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2975                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2976                 rte_memcpy(filter->dst_ipaddr,
2977                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2978                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2979                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2980                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2981                 memset(filter->src_ipaddr_mask, 0xff, 16);
2982                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2983                 filter->ethertype = 0x86dd;
2984                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2985                 break;
2986         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2987                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2988                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2989                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2990                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2991                 filter->dst_port_mask = 0xffff;
2992                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2993                 filter->src_port_mask = 0xffff;
2994                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2995                 filter->ip_addr_type =
2996                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2997                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2998                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2999                 rte_memcpy(filter->src_ipaddr,
3000                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3001                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3002                 rte_memcpy(filter->dst_ipaddr,
3003                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3004                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3005                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3006                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3007                 memset(filter->src_ipaddr_mask, 0xff, 16);
3008                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3009                 filter->ethertype = 0x86dd;
3010                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3011                 break;
3012         case RTE_ETH_FLOW_L2_PAYLOAD:
3013                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3014                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3015                 break;
3016         case RTE_ETH_FLOW_VXLAN:
3017                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3018                         return -EINVAL;
3019                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3020                 filter->tunnel_type =
3021                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3022                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3023                 break;
3024         case RTE_ETH_FLOW_NVGRE:
3025                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3026                         return -EINVAL;
3027                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3028                 filter->tunnel_type =
3029                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3030                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3031                 break;
3032         case RTE_ETH_FLOW_UNKNOWN:
3033         case RTE_ETH_FLOW_RAW:
3034         case RTE_ETH_FLOW_FRAG_IPV4:
3035         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3036         case RTE_ETH_FLOW_FRAG_IPV6:
3037         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3038         case RTE_ETH_FLOW_IPV6_EX:
3039         case RTE_ETH_FLOW_IPV6_TCP_EX:
3040         case RTE_ETH_FLOW_IPV6_UDP_EX:
3041         case RTE_ETH_FLOW_GENEVE:
3042                 /* FALLTHROUGH */
3043         default:
3044                 return -EINVAL;
3045         }
3046
3047         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3048         vnic = &bp->vnic_info[fdir->action.rx_queue];
3049         if (vnic == NULL) {
3050                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3051                 return -EINVAL;
3052         }
3053
3054         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3055                 rte_memcpy(filter->dst_macaddr,
3056                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3057                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3058         }
3059
3060         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3061                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3062                 filter1 = STAILQ_FIRST(&vnic0->filter);
3063                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3064         } else {
3065                 filter->dst_id = vnic->fw_vnic_id;
3066                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3067                         if (filter->dst_macaddr[i] == 0x00)
3068                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3069                         else
3070                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3071         }
3072
3073         if (filter1 == NULL)
3074                 return -EINVAL;
3075
3076         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3077         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3078
3079         filter->enables = en;
3080
3081         return 0;
3082 }
3083
3084 static struct bnxt_filter_info *
3085 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3086                 struct bnxt_vnic_info **mvnic)
3087 {
3088         struct bnxt_filter_info *mf = NULL;
3089         int i;
3090
3091         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3092                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3093
3094                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3095                         if (mf->filter_type == nf->filter_type &&
3096                             mf->flags == nf->flags &&
3097                             mf->src_port == nf->src_port &&
3098                             mf->src_port_mask == nf->src_port_mask &&
3099                             mf->dst_port == nf->dst_port &&
3100                             mf->dst_port_mask == nf->dst_port_mask &&
3101                             mf->ip_protocol == nf->ip_protocol &&
3102                             mf->ip_addr_type == nf->ip_addr_type &&
3103                             mf->ethertype == nf->ethertype &&
3104                             mf->vni == nf->vni &&
3105                             mf->tunnel_type == nf->tunnel_type &&
3106                             mf->l2_ovlan == nf->l2_ovlan &&
3107                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3108                             mf->l2_ivlan == nf->l2_ivlan &&
3109                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3110                             !memcmp(mf->l2_addr, nf->l2_addr,
3111                                     RTE_ETHER_ADDR_LEN) &&
3112                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3113                                     RTE_ETHER_ADDR_LEN) &&
3114                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3115                                     RTE_ETHER_ADDR_LEN) &&
3116                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3117                                     RTE_ETHER_ADDR_LEN) &&
3118                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3119                                     sizeof(nf->src_ipaddr)) &&
3120                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3121                                     sizeof(nf->src_ipaddr_mask)) &&
3122                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3123                                     sizeof(nf->dst_ipaddr)) &&
3124                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3125                                     sizeof(nf->dst_ipaddr_mask))) {
3126                                 if (mvnic)
3127                                         *mvnic = vnic;
3128                                 return mf;
3129                         }
3130                 }
3131         }
3132         return NULL;
3133 }
3134
3135 static int
3136 bnxt_fdir_filter(struct rte_eth_dev *dev,
3137                  enum rte_filter_op filter_op,
3138                  void *arg)
3139 {
3140         struct bnxt *bp = dev->data->dev_private;
3141         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3142         struct bnxt_filter_info *filter, *match;
3143         struct bnxt_vnic_info *vnic, *mvnic;
3144         int ret = 0, i;
3145
3146         if (filter_op == RTE_ETH_FILTER_NOP)
3147                 return 0;
3148
3149         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3150                 return -EINVAL;
3151
3152         switch (filter_op) {
3153         case RTE_ETH_FILTER_ADD:
3154         case RTE_ETH_FILTER_DELETE:
3155                 /* FALLTHROUGH */
3156                 filter = bnxt_get_unused_filter(bp);
3157                 if (filter == NULL) {
3158                         PMD_DRV_LOG(ERR,
3159                                 "Not enough resources for a new flow.\n");
3160                         return -ENOMEM;
3161                 }
3162
3163                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3164                 if (ret != 0)
3165                         goto free_filter;
3166                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3167
3168                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3169                         vnic = &bp->vnic_info[0];
3170                 else
3171                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3172
3173                 match = bnxt_match_fdir(bp, filter, &mvnic);
3174                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3175                         if (match->dst_id == vnic->fw_vnic_id) {
3176                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3177                                 ret = -EEXIST;
3178                                 goto free_filter;
3179                         } else {
3180                                 match->dst_id = vnic->fw_vnic_id;
3181                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3182                                                                   match->dst_id,
3183                                                                   match);
3184                                 STAILQ_REMOVE(&mvnic->filter, match,
3185                                               bnxt_filter_info, next);
3186                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3187                                 PMD_DRV_LOG(ERR,
3188                                         "Filter with matching pattern exist\n");
3189                                 PMD_DRV_LOG(ERR,
3190                                         "Updated it to new destination q\n");
3191                                 goto free_filter;
3192                         }
3193                 }
3194                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3195                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3196                         ret = -ENOENT;
3197                         goto free_filter;
3198                 }
3199
3200                 if (filter_op == RTE_ETH_FILTER_ADD) {
3201                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3202                                                           filter->dst_id,
3203                                                           filter);
3204                         if (ret)
3205                                 goto free_filter;
3206                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3207                 } else {
3208                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3209                         STAILQ_REMOVE(&vnic->filter, match,
3210                                       bnxt_filter_info, next);
3211                         bnxt_free_filter(bp, match);
3212                         bnxt_free_filter(bp, filter);
3213                 }
3214                 break;
3215         case RTE_ETH_FILTER_FLUSH:
3216                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3217                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3218
3219                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3220                                 if (filter->filter_type ==
3221                                     HWRM_CFA_NTUPLE_FILTER) {
3222                                         ret =
3223                                         bnxt_hwrm_clear_ntuple_filter(bp,
3224                                                                       filter);
3225                                         STAILQ_REMOVE(&vnic->filter, filter,
3226                                                       bnxt_filter_info, next);
3227                                 }
3228                         }
3229                 }
3230                 return ret;
3231         case RTE_ETH_FILTER_UPDATE:
3232         case RTE_ETH_FILTER_STATS:
3233         case RTE_ETH_FILTER_INFO:
3234                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3235                 break;
3236         default:
3237                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3238                 ret = -EINVAL;
3239                 break;
3240         }
3241         return ret;
3242
3243 free_filter:
3244         bnxt_free_filter(bp, filter);
3245         return ret;
3246 }
3247
3248 static int
3249 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3250                     enum rte_filter_type filter_type,
3251                     enum rte_filter_op filter_op, void *arg)
3252 {
3253         int ret = 0;
3254
3255         ret = is_bnxt_in_error(dev->data->dev_private);
3256         if (ret)
3257                 return ret;
3258
3259         switch (filter_type) {
3260         case RTE_ETH_FILTER_TUNNEL:
3261                 PMD_DRV_LOG(ERR,
3262                         "filter type: %d: To be implemented\n", filter_type);
3263                 break;
3264         case RTE_ETH_FILTER_FDIR:
3265                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3266                 break;
3267         case RTE_ETH_FILTER_NTUPLE:
3268                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3269                 break;
3270         case RTE_ETH_FILTER_ETHERTYPE:
3271                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3272                 break;
3273         case RTE_ETH_FILTER_GENERIC:
3274                 if (filter_op != RTE_ETH_FILTER_GET)
3275                         return -EINVAL;
3276                 *(const void **)arg = &bnxt_flow_ops;
3277                 break;
3278         default:
3279                 PMD_DRV_LOG(ERR,
3280                         "Filter type (%d) not supported", filter_type);
3281                 ret = -EINVAL;
3282                 break;
3283         }
3284         return ret;
3285 }
3286
3287 static const uint32_t *
3288 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3289 {
3290         static const uint32_t ptypes[] = {
3291                 RTE_PTYPE_L2_ETHER_VLAN,
3292                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3293                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3294                 RTE_PTYPE_L4_ICMP,
3295                 RTE_PTYPE_L4_TCP,
3296                 RTE_PTYPE_L4_UDP,
3297                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3298                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3299                 RTE_PTYPE_INNER_L4_ICMP,
3300                 RTE_PTYPE_INNER_L4_TCP,
3301                 RTE_PTYPE_INNER_L4_UDP,
3302                 RTE_PTYPE_UNKNOWN
3303         };
3304
3305         if (!dev->rx_pkt_burst)
3306                 return NULL;
3307
3308         return ptypes;
3309 }
3310
3311 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3312                          int reg_win)
3313 {
3314         uint32_t reg_base = *reg_arr & 0xfffff000;
3315         uint32_t win_off;
3316         int i;
3317
3318         for (i = 0; i < count; i++) {
3319                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3320                         return -ERANGE;
3321         }
3322         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3323         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3324         return 0;
3325 }
3326
3327 static int bnxt_map_ptp_regs(struct bnxt *bp)
3328 {
3329         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3330         uint32_t *reg_arr;
3331         int rc, i;
3332
3333         reg_arr = ptp->rx_regs;
3334         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3335         if (rc)
3336                 return rc;
3337
3338         reg_arr = ptp->tx_regs;
3339         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3340         if (rc)
3341                 return rc;
3342
3343         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3344                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3345
3346         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3347                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3348
3349         return 0;
3350 }
3351
3352 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3353 {
3354         rte_write32(0, (uint8_t *)bp->bar0 +
3355                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3356         rte_write32(0, (uint8_t *)bp->bar0 +
3357                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3358 }
3359
3360 static uint64_t bnxt_cc_read(struct bnxt *bp)
3361 {
3362         uint64_t ns;
3363
3364         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3365                               BNXT_GRCPF_REG_SYNC_TIME));
3366         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3367                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3368         return ns;
3369 }
3370
3371 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3372 {
3373         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3374         uint32_t fifo;
3375
3376         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3377                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3378         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3379                 return -EAGAIN;
3380
3381         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3382                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3383         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3384                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3385         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3386                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3387
3388         return 0;
3389 }
3390
3391 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3392 {
3393         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3394         struct bnxt_pf_info *pf = &bp->pf;
3395         uint16_t port_id;
3396         uint32_t fifo;
3397
3398         if (!ptp)
3399                 return -ENODEV;
3400
3401         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3402                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3403         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3404                 return -EAGAIN;
3405
3406         port_id = pf->port_id;
3407         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3408                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3409
3410         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3411                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3412         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3413 /*              bnxt_clr_rx_ts(bp);       TBD  */
3414                 return -EBUSY;
3415         }
3416
3417         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3418                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3419         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3421
3422         return 0;
3423 }
3424
3425 static int
3426 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3427 {
3428         uint64_t ns;
3429         struct bnxt *bp = dev->data->dev_private;
3430         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3431
3432         if (!ptp)
3433                 return 0;
3434
3435         ns = rte_timespec_to_ns(ts);
3436         /* Set the timecounters to a new value. */
3437         ptp->tc.nsec = ns;
3438
3439         return 0;
3440 }
3441
3442 static int
3443 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3444 {
3445         struct bnxt *bp = dev->data->dev_private;
3446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3447         uint64_t ns, systime_cycles = 0;
3448         int rc = 0;
3449
3450         if (!ptp)
3451                 return 0;
3452
3453         if (BNXT_CHIP_THOR(bp))
3454                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3455                                              &systime_cycles);
3456         else
3457                 systime_cycles = bnxt_cc_read(bp);
3458
3459         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3460         *ts = rte_ns_to_timespec(ns);
3461
3462         return rc;
3463 }
3464 static int
3465 bnxt_timesync_enable(struct rte_eth_dev *dev)
3466 {
3467         struct bnxt *bp = dev->data->dev_private;
3468         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3469         uint32_t shift = 0;
3470         int rc;
3471
3472         if (!ptp)
3473                 return 0;
3474
3475         ptp->rx_filter = 1;
3476         ptp->tx_tstamp_en = 1;
3477         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3478
3479         rc = bnxt_hwrm_ptp_cfg(bp);
3480         if (rc)
3481                 return rc;
3482
3483         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3484         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3485         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3486
3487         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3488         ptp->tc.cc_shift = shift;
3489         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3490
3491         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3492         ptp->rx_tstamp_tc.cc_shift = shift;
3493         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3494
3495         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3496         ptp->tx_tstamp_tc.cc_shift = shift;
3497         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3498
3499         if (!BNXT_CHIP_THOR(bp))
3500                 bnxt_map_ptp_regs(bp);
3501
3502         return 0;
3503 }
3504
3505 static int
3506 bnxt_timesync_disable(struct rte_eth_dev *dev)
3507 {
3508         struct bnxt *bp = dev->data->dev_private;
3509         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3510
3511         if (!ptp)
3512                 return 0;
3513
3514         ptp->rx_filter = 0;
3515         ptp->tx_tstamp_en = 0;
3516         ptp->rxctl = 0;
3517
3518         bnxt_hwrm_ptp_cfg(bp);
3519
3520         if (!BNXT_CHIP_THOR(bp))
3521                 bnxt_unmap_ptp_regs(bp);
3522
3523         return 0;
3524 }
3525
3526 static int
3527 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3528                                  struct timespec *timestamp,
3529                                  uint32_t flags __rte_unused)
3530 {
3531         struct bnxt *bp = dev->data->dev_private;
3532         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3533         uint64_t rx_tstamp_cycles = 0;
3534         uint64_t ns;
3535
3536         if (!ptp)
3537                 return 0;
3538
3539         if (BNXT_CHIP_THOR(bp))
3540                 rx_tstamp_cycles = ptp->rx_timestamp;
3541         else
3542                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3543
3544         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3545         *timestamp = rte_ns_to_timespec(ns);
3546         return  0;
3547 }
3548
3549 static int
3550 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3551                                  struct timespec *timestamp)
3552 {
3553         struct bnxt *bp = dev->data->dev_private;
3554         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3555         uint64_t tx_tstamp_cycles = 0;
3556         uint64_t ns;
3557         int rc = 0;
3558
3559         if (!ptp)
3560                 return 0;
3561
3562         if (BNXT_CHIP_THOR(bp))
3563                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3564                                              &tx_tstamp_cycles);
3565         else
3566                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3567
3568         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3569         *timestamp = rte_ns_to_timespec(ns);
3570
3571         return rc;
3572 }
3573
3574 static int
3575 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3576 {
3577         struct bnxt *bp = dev->data->dev_private;
3578         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3579
3580         if (!ptp)
3581                 return 0;
3582
3583         ptp->tc.nsec += delta;
3584
3585         return 0;
3586 }
3587
3588 static int
3589 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3590 {
3591         struct bnxt *bp = dev->data->dev_private;
3592         int rc;
3593         uint32_t dir_entries;
3594         uint32_t entry_length;
3595
3596         rc = is_bnxt_in_error(bp);
3597         if (rc)
3598                 return rc;
3599
3600         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3601                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3602                     bp->pdev->addr.devid, bp->pdev->addr.function);
3603
3604         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3605         if (rc != 0)
3606                 return rc;
3607
3608         return dir_entries * entry_length;
3609 }
3610
3611 static int
3612 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3613                 struct rte_dev_eeprom_info *in_eeprom)
3614 {
3615         struct bnxt *bp = dev->data->dev_private;
3616         uint32_t index;
3617         uint32_t offset;
3618         int rc;
3619
3620         rc = is_bnxt_in_error(bp);
3621         if (rc)
3622                 return rc;
3623
3624         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3625                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3626                     bp->pdev->addr.devid, bp->pdev->addr.function,
3627                     in_eeprom->offset, in_eeprom->length);
3628
3629         if (in_eeprom->offset == 0) /* special offset value to get directory */
3630                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3631                                                 in_eeprom->data);
3632
3633         index = in_eeprom->offset >> 24;
3634         offset = in_eeprom->offset & 0xffffff;
3635
3636         if (index != 0)
3637                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3638                                            in_eeprom->length, in_eeprom->data);
3639
3640         return 0;
3641 }
3642
3643 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3644 {
3645         switch (dir_type) {
3646         case BNX_DIR_TYPE_CHIMP_PATCH:
3647         case BNX_DIR_TYPE_BOOTCODE:
3648         case BNX_DIR_TYPE_BOOTCODE_2:
3649         case BNX_DIR_TYPE_APE_FW:
3650         case BNX_DIR_TYPE_APE_PATCH:
3651         case BNX_DIR_TYPE_KONG_FW:
3652         case BNX_DIR_TYPE_KONG_PATCH:
3653         case BNX_DIR_TYPE_BONO_FW:
3654         case BNX_DIR_TYPE_BONO_PATCH:
3655                 /* FALLTHROUGH */
3656                 return true;
3657         }
3658
3659         return false;
3660 }
3661
3662 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3663 {
3664         switch (dir_type) {
3665         case BNX_DIR_TYPE_AVS:
3666         case BNX_DIR_TYPE_EXP_ROM_MBA:
3667         case BNX_DIR_TYPE_PCIE:
3668         case BNX_DIR_TYPE_TSCF_UCODE:
3669         case BNX_DIR_TYPE_EXT_PHY:
3670         case BNX_DIR_TYPE_CCM:
3671         case BNX_DIR_TYPE_ISCSI_BOOT:
3672         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3673         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3674                 /* FALLTHROUGH */
3675                 return true;
3676         }
3677
3678         return false;
3679 }
3680
3681 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3682 {
3683         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3684                 bnxt_dir_type_is_other_exec_format(dir_type);
3685 }
3686
3687 static int
3688 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3689                 struct rte_dev_eeprom_info *in_eeprom)
3690 {
3691         struct bnxt *bp = dev->data->dev_private;
3692         uint8_t index, dir_op;
3693         uint16_t type, ext, ordinal, attr;
3694         int rc;
3695
3696         rc = is_bnxt_in_error(bp);
3697         if (rc)
3698                 return rc;
3699
3700         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3701                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3702                     bp->pdev->addr.devid, bp->pdev->addr.function,
3703                     in_eeprom->offset, in_eeprom->length);
3704
3705         if (!BNXT_PF(bp)) {
3706                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3707                 return -EINVAL;
3708         }
3709
3710         type = in_eeprom->magic >> 16;
3711
3712         if (type == 0xffff) { /* special value for directory operations */
3713                 index = in_eeprom->magic & 0xff;
3714                 dir_op = in_eeprom->magic >> 8;
3715                 if (index == 0)
3716                         return -EINVAL;
3717                 switch (dir_op) {
3718                 case 0x0e: /* erase */
3719                         if (in_eeprom->offset != ~in_eeprom->magic)
3720                                 return -EINVAL;
3721                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3722                 default:
3723                         return -EINVAL;
3724                 }
3725         }
3726
3727         /* Create or re-write an NVM item: */
3728         if (bnxt_dir_type_is_executable(type) == true)
3729                 return -EOPNOTSUPP;
3730         ext = in_eeprom->magic & 0xffff;
3731         ordinal = in_eeprom->offset >> 16;
3732         attr = in_eeprom->offset & 0xffff;
3733
3734         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3735                                      in_eeprom->data, in_eeprom->length);
3736 }
3737
3738 /*
3739  * Initialization
3740  */
3741
3742 static const struct eth_dev_ops bnxt_dev_ops = {
3743         .dev_infos_get = bnxt_dev_info_get_op,
3744         .dev_close = bnxt_dev_close_op,
3745         .dev_configure = bnxt_dev_configure_op,
3746         .dev_start = bnxt_dev_start_op,
3747         .dev_stop = bnxt_dev_stop_op,
3748         .dev_set_link_up = bnxt_dev_set_link_up_op,
3749         .dev_set_link_down = bnxt_dev_set_link_down_op,
3750         .stats_get = bnxt_stats_get_op,
3751         .stats_reset = bnxt_stats_reset_op,
3752         .rx_queue_setup = bnxt_rx_queue_setup_op,
3753         .rx_queue_release = bnxt_rx_queue_release_op,
3754         .tx_queue_setup = bnxt_tx_queue_setup_op,
3755         .tx_queue_release = bnxt_tx_queue_release_op,
3756         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3757         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3758         .reta_update = bnxt_reta_update_op,
3759         .reta_query = bnxt_reta_query_op,
3760         .rss_hash_update = bnxt_rss_hash_update_op,
3761         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3762         .link_update = bnxt_link_update_op,
3763         .promiscuous_enable = bnxt_promiscuous_enable_op,
3764         .promiscuous_disable = bnxt_promiscuous_disable_op,
3765         .allmulticast_enable = bnxt_allmulticast_enable_op,
3766         .allmulticast_disable = bnxt_allmulticast_disable_op,
3767         .mac_addr_add = bnxt_mac_addr_add_op,
3768         .mac_addr_remove = bnxt_mac_addr_remove_op,
3769         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3770         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3771         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3772         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3773         .vlan_filter_set = bnxt_vlan_filter_set_op,
3774         .vlan_offload_set = bnxt_vlan_offload_set_op,
3775         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3776         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3777         .mtu_set = bnxt_mtu_set_op,
3778         .mac_addr_set = bnxt_set_default_mac_addr_op,
3779         .xstats_get = bnxt_dev_xstats_get_op,
3780         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3781         .xstats_reset = bnxt_dev_xstats_reset_op,
3782         .fw_version_get = bnxt_fw_version_get,
3783         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3784         .rxq_info_get = bnxt_rxq_info_get_op,
3785         .txq_info_get = bnxt_txq_info_get_op,
3786         .dev_led_on = bnxt_dev_led_on_op,
3787         .dev_led_off = bnxt_dev_led_off_op,
3788         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3789         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3790         .rx_queue_count = bnxt_rx_queue_count_op,
3791         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3792         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3793         .rx_queue_start = bnxt_rx_queue_start,
3794         .rx_queue_stop = bnxt_rx_queue_stop,
3795         .tx_queue_start = bnxt_tx_queue_start,
3796         .tx_queue_stop = bnxt_tx_queue_stop,
3797         .filter_ctrl = bnxt_filter_ctrl_op,
3798         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3799         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3800         .get_eeprom           = bnxt_get_eeprom_op,
3801         .set_eeprom           = bnxt_set_eeprom_op,
3802         .timesync_enable      = bnxt_timesync_enable,
3803         .timesync_disable     = bnxt_timesync_disable,
3804         .timesync_read_time   = bnxt_timesync_read_time,
3805         .timesync_write_time   = bnxt_timesync_write_time,
3806         .timesync_adjust_time = bnxt_timesync_adjust_time,
3807         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3808         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3809 };
3810
3811 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3812 {
3813         uint32_t offset;
3814
3815         /* Only pre-map the reset GRC registers using window 3 */
3816         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3817                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3818
3819         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3820
3821         return offset;
3822 }
3823
3824 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3825 {
3826         struct bnxt_error_recovery_info *info = bp->recovery_info;
3827         uint32_t reg_base = 0xffffffff;
3828         int i;
3829
3830         /* Only pre-map the monitoring GRC registers using window 2 */
3831         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3832                 uint32_t reg = info->status_regs[i];
3833
3834                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3835                         continue;
3836
3837                 if (reg_base == 0xffffffff)
3838                         reg_base = reg & 0xfffff000;
3839                 if ((reg & 0xfffff000) != reg_base)
3840                         return -ERANGE;
3841
3842                 /* Use mask 0xffc as the Lower 2 bits indicates
3843                  * address space location
3844                  */
3845                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3846                                                 (reg & 0xffc);
3847         }
3848
3849         if (reg_base == 0xffffffff)
3850                 return 0;
3851
3852         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3853                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3854
3855         return 0;
3856 }
3857
3858 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3859 {
3860         struct bnxt_error_recovery_info *info = bp->recovery_info;
3861         uint32_t delay = info->delay_after_reset[index];
3862         uint32_t val = info->reset_reg_val[index];
3863         uint32_t reg = info->reset_reg[index];
3864         uint32_t type, offset;
3865
3866         type = BNXT_FW_STATUS_REG_TYPE(reg);
3867         offset = BNXT_FW_STATUS_REG_OFF(reg);
3868
3869         switch (type) {
3870         case BNXT_FW_STATUS_REG_TYPE_CFG:
3871                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3872                 break;
3873         case BNXT_FW_STATUS_REG_TYPE_GRC:
3874                 offset = bnxt_map_reset_regs(bp, offset);
3875                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3876                 break;
3877         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3878                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3879                 break;
3880         }
3881         /* wait on a specific interval of time until core reset is complete */
3882         if (delay)
3883                 rte_delay_ms(delay);
3884 }
3885
3886 static void bnxt_dev_cleanup(struct bnxt *bp)
3887 {
3888         bnxt_set_hwrm_link_config(bp, false);
3889         bp->link_info.link_up = 0;
3890         if (bp->dev_stopped == 0)
3891                 bnxt_dev_stop_op(bp->eth_dev);
3892
3893         bnxt_uninit_resources(bp, true);
3894 }
3895
3896 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3897 {
3898         struct rte_eth_dev *dev = bp->eth_dev;
3899         struct rte_vlan_filter_conf *vfc;
3900         int vidx, vbit, rc;
3901         uint16_t vlan_id;
3902
3903         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3904                 vfc = &dev->data->vlan_filter_conf;
3905                 vidx = vlan_id / 64;
3906                 vbit = vlan_id % 64;
3907
3908                 /* Each bit corresponds to a VLAN id */
3909                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3910                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3911                         if (rc)
3912                                 return rc;
3913                 }
3914         }
3915
3916         return 0;
3917 }
3918
3919 static int bnxt_restore_mac_filters(struct bnxt *bp)
3920 {
3921         struct rte_eth_dev *dev = bp->eth_dev;
3922         struct rte_eth_dev_info dev_info;
3923         struct rte_ether_addr *addr;
3924         uint64_t pool_mask;
3925         uint32_t pool = 0;
3926         uint16_t i;
3927         int rc;
3928
3929         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3930                 return 0;
3931
3932         rc = bnxt_dev_info_get_op(dev, &dev_info);
3933         if (rc)
3934                 return rc;
3935
3936         /* replay MAC address configuration */
3937         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3938                 addr = &dev->data->mac_addrs[i];
3939
3940                 /* skip zero address */
3941                 if (rte_is_zero_ether_addr(addr))
3942                         continue;
3943
3944                 pool = 0;
3945                 pool_mask = dev->data->mac_pool_sel[i];
3946
3947                 do {
3948                         if (pool_mask & 1ULL) {
3949                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3950                                 if (rc)
3951                                         return rc;
3952                         }
3953                         pool_mask >>= 1;
3954                         pool++;
3955                 } while (pool_mask);
3956         }
3957
3958         return 0;
3959 }
3960
3961 static int bnxt_restore_filters(struct bnxt *bp)
3962 {
3963         struct rte_eth_dev *dev = bp->eth_dev;
3964         int ret = 0;
3965
3966         if (dev->data->all_multicast)
3967                 ret = bnxt_allmulticast_enable_op(dev);
3968         if (dev->data->promiscuous)
3969                 ret = bnxt_promiscuous_enable_op(dev);
3970
3971         ret = bnxt_restore_mac_filters(bp);
3972         if (ret)
3973                 return ret;
3974
3975         ret = bnxt_restore_vlan_filters(bp);
3976         /* TODO restore other filters as well */
3977         return ret;
3978 }
3979
3980 static void bnxt_dev_recover(void *arg)
3981 {
3982         struct bnxt *bp = arg;
3983         int timeout = bp->fw_reset_max_msecs;
3984         int rc = 0;
3985
3986         /* Clear Error flag so that device re-init should happen */
3987         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3988
3989         do {
3990                 rc = bnxt_hwrm_ver_get(bp);
3991                 if (rc == 0)
3992                         break;
3993                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3994                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3995         } while (rc && timeout);
3996
3997         if (rc) {
3998                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3999                 goto err;
4000         }
4001
4002         rc = bnxt_init_resources(bp, true);
4003         if (rc) {
4004                 PMD_DRV_LOG(ERR,
4005                             "Failed to initialize resources after reset\n");
4006                 goto err;
4007         }
4008         /* clear reset flag as the device is initialized now */
4009         bp->flags &= ~BNXT_FLAG_FW_RESET;
4010
4011         rc = bnxt_dev_start_op(bp->eth_dev);
4012         if (rc) {
4013                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4014                 goto err;
4015         }
4016
4017         rc = bnxt_restore_filters(bp);
4018         if (rc)
4019                 goto err;
4020
4021         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4022         return;
4023 err:
4024         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4025         bnxt_uninit_resources(bp, false);
4026         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4027 }
4028
4029 void bnxt_dev_reset_and_resume(void *arg)
4030 {
4031         struct bnxt *bp = arg;
4032         int rc;
4033
4034         bnxt_dev_cleanup(bp);
4035
4036         bnxt_wait_for_device_shutdown(bp);
4037
4038         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4039                                bnxt_dev_recover, (void *)bp);
4040         if (rc)
4041                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4042 }
4043
4044 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4045 {
4046         struct bnxt_error_recovery_info *info = bp->recovery_info;
4047         uint32_t reg = info->status_regs[index];
4048         uint32_t type, offset, val = 0;
4049
4050         type = BNXT_FW_STATUS_REG_TYPE(reg);
4051         offset = BNXT_FW_STATUS_REG_OFF(reg);
4052
4053         switch (type) {
4054         case BNXT_FW_STATUS_REG_TYPE_CFG:
4055                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4056                 break;
4057         case BNXT_FW_STATUS_REG_TYPE_GRC:
4058                 offset = info->mapped_status_regs[index];
4059                 /* FALLTHROUGH */
4060         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4061                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4062                                        offset));
4063                 break;
4064         }
4065
4066         return val;
4067 }
4068
4069 static int bnxt_fw_reset_all(struct bnxt *bp)
4070 {
4071         struct bnxt_error_recovery_info *info = bp->recovery_info;
4072         uint32_t i;
4073         int rc = 0;
4074
4075         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4076                 /* Reset through master function driver */
4077                 for (i = 0; i < info->reg_array_cnt; i++)
4078                         bnxt_write_fw_reset_reg(bp, i);
4079                 /* Wait for time specified by FW after triggering reset */
4080                 rte_delay_ms(info->master_func_wait_period_after_reset);
4081         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4082                 /* Reset with the help of Kong processor */
4083                 rc = bnxt_hwrm_fw_reset(bp);
4084                 if (rc)
4085                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4086         }
4087
4088         return rc;
4089 }
4090
4091 static void bnxt_fw_reset_cb(void *arg)
4092 {
4093         struct bnxt *bp = arg;
4094         struct bnxt_error_recovery_info *info = bp->recovery_info;
4095         int rc = 0;
4096
4097         /* Only Master function can do FW reset */
4098         if (bnxt_is_master_func(bp) &&
4099             bnxt_is_recovery_enabled(bp)) {
4100                 rc = bnxt_fw_reset_all(bp);
4101                 if (rc) {
4102                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4103                         return;
4104                 }
4105         }
4106
4107         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4108          * EXCEPTION_FATAL_ASYNC event to all the functions
4109          * (including MASTER FUNC). After receiving this Async, all the active
4110          * drivers should treat this case as FW initiated recovery
4111          */
4112         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4113                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4114                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4115
4116                 /* To recover from error */
4117                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4118                                   (void *)bp);
4119         }
4120 }
4121
4122 /* Driver should poll FW heartbeat, reset_counter with the frequency
4123  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4124  * When the driver detects heartbeat stop or change in reset_counter,
4125  * it has to trigger a reset to recover from the error condition.
4126  * A “master PF” is the function who will have the privilege to
4127  * initiate the chimp reset. The master PF will be elected by the
4128  * firmware and will be notified through async message.
4129  */
4130 static void bnxt_check_fw_health(void *arg)
4131 {
4132         struct bnxt *bp = arg;
4133         struct bnxt_error_recovery_info *info = bp->recovery_info;
4134         uint32_t val = 0, wait_msec;
4135
4136         if (!info || !bnxt_is_recovery_enabled(bp) ||
4137             is_bnxt_in_error(bp))
4138                 return;
4139
4140         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4141         if (val == info->last_heart_beat)
4142                 goto reset;
4143
4144         info->last_heart_beat = val;
4145
4146         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4147         if (val != info->last_reset_counter)
4148                 goto reset;
4149
4150         info->last_reset_counter = val;
4151
4152         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4153                           bnxt_check_fw_health, (void *)bp);
4154
4155         return;
4156 reset:
4157         /* Stop DMA to/from device */
4158         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4159         bp->flags |= BNXT_FLAG_FW_RESET;
4160
4161         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4162
4163         if (bnxt_is_master_func(bp))
4164                 wait_msec = info->master_func_wait_period;
4165         else
4166                 wait_msec = info->normal_func_wait_period;
4167
4168         rte_eal_alarm_set(US_PER_MS * wait_msec,
4169                           bnxt_fw_reset_cb, (void *)bp);
4170 }
4171
4172 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4173 {
4174         uint32_t polling_freq;
4175
4176         if (!bnxt_is_recovery_enabled(bp))
4177                 return;
4178
4179         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4180                 return;
4181
4182         polling_freq = bp->recovery_info->driver_polling_freq;
4183
4184         rte_eal_alarm_set(US_PER_MS * polling_freq,
4185                           bnxt_check_fw_health, (void *)bp);
4186         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4187 }
4188
4189 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4190 {
4191         if (!bnxt_is_recovery_enabled(bp))
4192                 return;
4193
4194         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4195         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4196 }
4197
4198 static bool bnxt_vf_pciid(uint16_t device_id)
4199 {
4200         switch (device_id) {
4201         case BROADCOM_DEV_ID_57304_VF:
4202         case BROADCOM_DEV_ID_57406_VF:
4203         case BROADCOM_DEV_ID_5731X_VF:
4204         case BROADCOM_DEV_ID_5741X_VF:
4205         case BROADCOM_DEV_ID_57414_VF:
4206         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4207         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4208         case BROADCOM_DEV_ID_58802_VF:
4209         case BROADCOM_DEV_ID_57500_VF1:
4210         case BROADCOM_DEV_ID_57500_VF2:
4211                 /* FALLTHROUGH */
4212                 return true;
4213         default:
4214                 return false;
4215         }
4216 }
4217
4218 static bool bnxt_thor_device(uint16_t device_id)
4219 {
4220         switch (device_id) {
4221         case BROADCOM_DEV_ID_57508:
4222         case BROADCOM_DEV_ID_57504:
4223         case BROADCOM_DEV_ID_57502:
4224         case BROADCOM_DEV_ID_57508_MF1:
4225         case BROADCOM_DEV_ID_57504_MF1:
4226         case BROADCOM_DEV_ID_57502_MF1:
4227         case BROADCOM_DEV_ID_57508_MF2:
4228         case BROADCOM_DEV_ID_57504_MF2:
4229         case BROADCOM_DEV_ID_57502_MF2:
4230         case BROADCOM_DEV_ID_57500_VF1:
4231         case BROADCOM_DEV_ID_57500_VF2:
4232                 /* FALLTHROUGH */
4233                 return true;
4234         default:
4235                 return false;
4236         }
4237 }
4238
4239 bool bnxt_stratus_device(struct bnxt *bp)
4240 {
4241         uint16_t device_id = bp->pdev->id.device_id;
4242
4243         switch (device_id) {
4244         case BROADCOM_DEV_ID_STRATUS_NIC:
4245         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4246         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4247                 /* FALLTHROUGH */
4248                 return true;
4249         default:
4250                 return false;
4251         }
4252 }
4253
4254 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4255 {
4256         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4257         struct bnxt *bp = eth_dev->data->dev_private;
4258
4259         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4260         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4261         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4262         if (!bp->bar0 || !bp->doorbell_base) {
4263                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4264                 return -ENODEV;
4265         }
4266
4267         bp->eth_dev = eth_dev;
4268         bp->pdev = pci_dev;
4269
4270         return 0;
4271 }
4272
4273 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4274                                   struct bnxt_ctx_pg_info *ctx_pg,
4275                                   uint32_t mem_size,
4276                                   const char *suffix,
4277                                   uint16_t idx)
4278 {
4279         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4280         const struct rte_memzone *mz = NULL;
4281         char mz_name[RTE_MEMZONE_NAMESIZE];
4282         rte_iova_t mz_phys_addr;
4283         uint64_t valid_bits = 0;
4284         uint32_t sz;
4285         int i;
4286
4287         if (!mem_size)
4288                 return 0;
4289
4290         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4291                          BNXT_PAGE_SIZE;
4292         rmem->page_size = BNXT_PAGE_SIZE;
4293         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4294         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4295         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4296
4297         valid_bits = PTU_PTE_VALID;
4298
4299         if (rmem->nr_pages > 1) {
4300                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4301                          "bnxt_ctx_pg_tbl%s_%x_%d",
4302                          suffix, idx, bp->eth_dev->data->port_id);
4303                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4304                 mz = rte_memzone_lookup(mz_name);
4305                 if (!mz) {
4306                         mz = rte_memzone_reserve_aligned(mz_name,
4307                                                 rmem->nr_pages * 8,
4308                                                 SOCKET_ID_ANY,
4309                                                 RTE_MEMZONE_2MB |
4310                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4311                                                 RTE_MEMZONE_IOVA_CONTIG,
4312                                                 BNXT_PAGE_SIZE);
4313                         if (mz == NULL)
4314                                 return -ENOMEM;
4315                 }
4316
4317                 memset(mz->addr, 0, mz->len);
4318                 mz_phys_addr = mz->iova;
4319
4320                 rmem->pg_tbl = mz->addr;
4321                 rmem->pg_tbl_map = mz_phys_addr;
4322                 rmem->pg_tbl_mz = mz;
4323         }
4324
4325         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4326                  suffix, idx, bp->eth_dev->data->port_id);
4327         mz = rte_memzone_lookup(mz_name);
4328         if (!mz) {
4329                 mz = rte_memzone_reserve_aligned(mz_name,
4330                                                  mem_size,
4331                                                  SOCKET_ID_ANY,
4332                                                  RTE_MEMZONE_1GB |
4333                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4334                                                  RTE_MEMZONE_IOVA_CONTIG,
4335                                                  BNXT_PAGE_SIZE);
4336                 if (mz == NULL)
4337                         return -ENOMEM;
4338         }
4339
4340         memset(mz->addr, 0, mz->len);
4341         mz_phys_addr = mz->iova;
4342
4343         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4344                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4345                 rmem->dma_arr[i] = mz_phys_addr + sz;
4346
4347                 if (rmem->nr_pages > 1) {
4348                         if (i == rmem->nr_pages - 2 &&
4349                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4350                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4351                         else if (i == rmem->nr_pages - 1 &&
4352                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4353                                 valid_bits |= PTU_PTE_LAST;
4354
4355                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4356                                                            valid_bits);
4357                 }
4358         }
4359
4360         rmem->mz = mz;
4361         if (rmem->vmem_size)
4362                 rmem->vmem = (void **)mz->addr;
4363         rmem->dma_arr[0] = mz_phys_addr;
4364         return 0;
4365 }
4366
4367 static void bnxt_free_ctx_mem(struct bnxt *bp)
4368 {
4369         int i;
4370
4371         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4372                 return;
4373
4374         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4375         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4376         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4377         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4378         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4379         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4380         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4381         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4382         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4383         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4384         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4385
4386         for (i = 0; i < BNXT_MAX_Q; i++) {
4387                 if (bp->ctx->tqm_mem[i])
4388                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4389         }
4390
4391         rte_free(bp->ctx);
4392         bp->ctx = NULL;
4393 }
4394
4395 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4396
4397 #define min_t(type, x, y) ({                    \
4398         type __min1 = (x);                      \
4399         type __min2 = (y);                      \
4400         __min1 < __min2 ? __min1 : __min2; })
4401
4402 #define max_t(type, x, y) ({                    \
4403         type __max1 = (x);                      \
4404         type __max2 = (y);                      \
4405         __max1 > __max2 ? __max1 : __max2; })
4406
4407 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4408
4409 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4410 {
4411         struct bnxt_ctx_pg_info *ctx_pg;
4412         struct bnxt_ctx_mem_info *ctx;
4413         uint32_t mem_size, ena, entries;
4414         int i, rc;
4415
4416         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4417         if (rc) {
4418                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4419                 return rc;
4420         }
4421         ctx = bp->ctx;
4422         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4423                 return 0;
4424
4425         ctx_pg = &ctx->qp_mem;
4426         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4427         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4428         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4429         if (rc)
4430                 return rc;
4431
4432         ctx_pg = &ctx->srq_mem;
4433         ctx_pg->entries = ctx->srq_max_l2_entries;
4434         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4435         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4436         if (rc)
4437                 return rc;
4438
4439         ctx_pg = &ctx->cq_mem;
4440         ctx_pg->entries = ctx->cq_max_l2_entries;
4441         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4442         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4443         if (rc)
4444                 return rc;
4445
4446         ctx_pg = &ctx->vnic_mem;
4447         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4448                 ctx->vnic_max_ring_table_entries;
4449         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4450         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4451         if (rc)
4452                 return rc;
4453
4454         ctx_pg = &ctx->stat_mem;
4455         ctx_pg->entries = ctx->stat_max_entries;
4456         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4457         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4458         if (rc)
4459                 return rc;
4460
4461         entries = ctx->qp_max_l2_entries +
4462                   ctx->vnic_max_vnic_entries +
4463                   ctx->tqm_min_entries_per_ring;
4464         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4465         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4466                           ctx->tqm_max_entries_per_ring);
4467         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4468                 ctx_pg = ctx->tqm_mem[i];
4469                 /* use min tqm entries for now. */
4470                 ctx_pg->entries = entries;
4471                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4472                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4473                 if (rc)
4474                         return rc;
4475                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4476         }
4477
4478         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4479         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4480         if (rc)
4481                 PMD_DRV_LOG(ERR,
4482                             "Failed to configure context mem: rc = %d\n", rc);
4483         else
4484                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4485
4486         return rc;
4487 }
4488
4489 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4490 {
4491         struct rte_pci_device *pci_dev = bp->pdev;
4492         char mz_name[RTE_MEMZONE_NAMESIZE];
4493         const struct rte_memzone *mz = NULL;
4494         uint32_t total_alloc_len;
4495         rte_iova_t mz_phys_addr;
4496
4497         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4498                 return 0;
4499
4500         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4501                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4502                  pci_dev->addr.bus, pci_dev->addr.devid,
4503                  pci_dev->addr.function, "rx_port_stats");
4504         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4505         mz = rte_memzone_lookup(mz_name);
4506         total_alloc_len =
4507                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4508                                        sizeof(struct rx_port_stats_ext) + 512);
4509         if (!mz) {
4510                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4511                                          SOCKET_ID_ANY,
4512                                          RTE_MEMZONE_2MB |
4513                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4514                                          RTE_MEMZONE_IOVA_CONTIG);
4515                 if (mz == NULL)
4516                         return -ENOMEM;
4517         }
4518         memset(mz->addr, 0, mz->len);
4519         mz_phys_addr = mz->iova;
4520
4521         bp->rx_mem_zone = (const void *)mz;
4522         bp->hw_rx_port_stats = mz->addr;
4523         bp->hw_rx_port_stats_map = mz_phys_addr;
4524
4525         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4526                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4527                  pci_dev->addr.bus, pci_dev->addr.devid,
4528                  pci_dev->addr.function, "tx_port_stats");
4529         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4530         mz = rte_memzone_lookup(mz_name);
4531         total_alloc_len =
4532                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4533                                        sizeof(struct tx_port_stats_ext) + 512);
4534         if (!mz) {
4535                 mz = rte_memzone_reserve(mz_name,
4536                                          total_alloc_len,
4537                                          SOCKET_ID_ANY,
4538                                          RTE_MEMZONE_2MB |
4539                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4540                                          RTE_MEMZONE_IOVA_CONTIG);
4541                 if (mz == NULL)
4542                         return -ENOMEM;
4543         }
4544         memset(mz->addr, 0, mz->len);
4545         mz_phys_addr = mz->iova;
4546
4547         bp->tx_mem_zone = (const void *)mz;
4548         bp->hw_tx_port_stats = mz->addr;
4549         bp->hw_tx_port_stats_map = mz_phys_addr;
4550         bp->flags |= BNXT_FLAG_PORT_STATS;
4551
4552         /* Display extended statistics if FW supports it */
4553         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4554             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4555             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4556                 return 0;
4557
4558         bp->hw_rx_port_stats_ext = (void *)
4559                 ((uint8_t *)bp->hw_rx_port_stats +
4560                  sizeof(struct rx_port_stats));
4561         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4562                 sizeof(struct rx_port_stats);
4563         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4564
4565         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4566             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4567                 bp->hw_tx_port_stats_ext = (void *)
4568                         ((uint8_t *)bp->hw_tx_port_stats +
4569                          sizeof(struct tx_port_stats));
4570                 bp->hw_tx_port_stats_ext_map =
4571                         bp->hw_tx_port_stats_map +
4572                         sizeof(struct tx_port_stats);
4573                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4574         }
4575
4576         return 0;
4577 }
4578
4579 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4580 {
4581         struct bnxt *bp = eth_dev->data->dev_private;
4582         int rc = 0;
4583
4584         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4585                                                RTE_ETHER_ADDR_LEN *
4586                                                bp->max_l2_ctx,
4587                                                0);
4588         if (eth_dev->data->mac_addrs == NULL) {
4589                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4590                 return -ENOMEM;
4591         }
4592
4593         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4594                 if (BNXT_PF(bp))
4595                         return -EINVAL;
4596
4597                 /* Generate a random MAC address, if none was assigned by PF */
4598                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4599                 bnxt_eth_hw_addr_random(bp->mac_addr);
4600                 PMD_DRV_LOG(INFO,
4601                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4602                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4603                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4604
4605                 rc = bnxt_hwrm_set_mac(bp);
4606                 if (!rc)
4607                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4608                                RTE_ETHER_ADDR_LEN);
4609                 return rc;
4610         }
4611
4612         /* Copy the permanent MAC from the FUNC_QCAPS response */
4613         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4614         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4615
4616         return rc;
4617 }
4618
4619 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4620 {
4621         int rc = 0;
4622
4623         /* MAC is already configured in FW */
4624         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4625                 return 0;
4626
4627         /* Restore the old MAC configured */
4628         rc = bnxt_hwrm_set_mac(bp);
4629         if (rc)
4630                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4631
4632         return rc;
4633 }
4634
4635 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4636 {
4637         if (!BNXT_PF(bp))
4638                 return;
4639
4640 #define ALLOW_FUNC(x)   \
4641         { \
4642                 uint32_t arg = (x); \
4643                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4644                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4645         }
4646
4647         /* Forward all requests if firmware is new enough */
4648         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4649              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4650             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4651                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4652         } else {
4653                 PMD_DRV_LOG(WARNING,
4654                             "Firmware too old for VF mailbox functionality\n");
4655                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4656         }
4657
4658         /*
4659          * The following are used for driver cleanup. If we disallow these,
4660          * VF drivers can't clean up cleanly.
4661          */
4662         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4663         ALLOW_FUNC(HWRM_VNIC_FREE);
4664         ALLOW_FUNC(HWRM_RING_FREE);
4665         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4666         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4667         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4668         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4669         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4670         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4671 }
4672
4673 static int bnxt_init_fw(struct bnxt *bp)
4674 {
4675         uint16_t mtu;
4676         int rc = 0;
4677
4678         bp->fw_cap = 0;
4679
4680         rc = bnxt_hwrm_ver_get(bp);
4681         if (rc)
4682                 return rc;
4683
4684         rc = bnxt_hwrm_func_reset(bp);
4685         if (rc)
4686                 return -EIO;
4687
4688         rc = bnxt_hwrm_vnic_qcaps(bp);
4689         if (rc)
4690                 return rc;
4691
4692         rc = bnxt_hwrm_queue_qportcfg(bp);
4693         if (rc)
4694                 return rc;
4695
4696         /* Get the MAX capabilities for this function.
4697          * This function also allocates context memory for TQM rings and
4698          * informs the firmware about this allocated backing store memory.
4699          */
4700         rc = bnxt_hwrm_func_qcaps(bp);
4701         if (rc)
4702                 return rc;
4703
4704         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4705         if (rc)
4706                 return rc;
4707
4708         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4709         if (rc)
4710                 return rc;
4711
4712         /* Get the adapter error recovery support info */
4713         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4714         if (rc)
4715                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4716
4717         bnxt_hwrm_port_led_qcaps(bp);
4718
4719         return 0;
4720 }
4721
4722 static int
4723 bnxt_init_locks(struct bnxt *bp)
4724 {
4725         int err;
4726
4727         err = pthread_mutex_init(&bp->flow_lock, NULL);
4728         if (err) {
4729                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4730                 return err;
4731         }
4732
4733         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4734         if (err)
4735                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4736         return err;
4737 }
4738
4739 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4740 {
4741         int rc;
4742
4743         rc = bnxt_init_fw(bp);
4744         if (rc)
4745                 return rc;
4746
4747         if (!reconfig_dev) {
4748                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4749                 if (rc)
4750                         return rc;
4751         } else {
4752                 rc = bnxt_restore_dflt_mac(bp);
4753                 if (rc)
4754                         return rc;
4755         }
4756
4757         bnxt_config_vf_req_fwd(bp);
4758
4759         rc = bnxt_hwrm_func_driver_register(bp);
4760         if (rc) {
4761                 PMD_DRV_LOG(ERR, "Failed to register driver");
4762                 return -EBUSY;
4763         }
4764
4765         if (BNXT_PF(bp)) {
4766                 if (bp->pdev->max_vfs) {
4767                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4768                         if (rc) {
4769                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4770                                 return rc;
4771                         }
4772                 } else {
4773                         rc = bnxt_hwrm_allocate_pf_only(bp);
4774                         if (rc) {
4775                                 PMD_DRV_LOG(ERR,
4776                                             "Failed to allocate PF resources");
4777                                 return rc;
4778                         }
4779                 }
4780         }
4781
4782         rc = bnxt_alloc_mem(bp, reconfig_dev);
4783         if (rc)
4784                 return rc;
4785
4786         rc = bnxt_setup_int(bp);
4787         if (rc)
4788                 return rc;
4789
4790         rc = bnxt_request_int(bp);
4791         if (rc)
4792                 return rc;
4793
4794         rc = bnxt_init_locks(bp);
4795         if (rc)
4796                 return rc;
4797
4798         return 0;
4799 }
4800
4801 static int
4802 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4803 {
4804         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4805         static int version_printed;
4806         struct bnxt *bp;
4807         int rc;
4808
4809         if (version_printed++ == 0)
4810                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4811
4812         eth_dev->dev_ops = &bnxt_dev_ops;
4813         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4814         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4815
4816         /*
4817          * For secondary processes, we don't initialise any further
4818          * as primary has already done this work.
4819          */
4820         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4821                 return 0;
4822
4823         rte_eth_copy_pci_info(eth_dev, pci_dev);
4824
4825         bp = eth_dev->data->dev_private;
4826
4827         bp->dev_stopped = 1;
4828         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4829
4830         if (bnxt_vf_pciid(pci_dev->id.device_id))
4831                 bp->flags |= BNXT_FLAG_VF;
4832
4833         if (bnxt_thor_device(pci_dev->id.device_id))
4834                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4835
4836         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4837             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4838             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4839             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4840                 bp->flags |= BNXT_FLAG_STINGRAY;
4841
4842         rc = bnxt_init_board(eth_dev);
4843         if (rc) {
4844                 PMD_DRV_LOG(ERR,
4845                             "Failed to initialize board rc: %x\n", rc);
4846                 return rc;
4847         }
4848
4849         rc = bnxt_alloc_hwrm_resources(bp);
4850         if (rc) {
4851                 PMD_DRV_LOG(ERR,
4852                             "Failed to allocate hwrm resource rc: %x\n", rc);
4853                 goto error_free;
4854         }
4855         rc = bnxt_init_resources(bp, false);
4856         if (rc)
4857                 goto error_free;
4858
4859         rc = bnxt_alloc_stats_mem(bp);
4860         if (rc)
4861                 goto error_free;
4862
4863         /* Pass the information to the rte_eth_dev_close() that it should also
4864          * release the private port resources.
4865          */
4866         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4867
4868         PMD_DRV_LOG(INFO,
4869                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4870                     pci_dev->mem_resource[0].phys_addr,
4871                     pci_dev->mem_resource[0].addr);
4872
4873         return 0;
4874
4875 error_free:
4876         bnxt_dev_uninit(eth_dev);
4877         return rc;
4878 }
4879
4880 static void
4881 bnxt_uninit_locks(struct bnxt *bp)
4882 {
4883         pthread_mutex_destroy(&bp->flow_lock);
4884         pthread_mutex_destroy(&bp->def_cp_lock);
4885 }
4886
4887 static int
4888 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4889 {
4890         int rc;
4891
4892         bnxt_free_int(bp);
4893         bnxt_free_mem(bp, reconfig_dev);
4894         bnxt_hwrm_func_buf_unrgtr(bp);
4895         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4896         bp->flags &= ~BNXT_FLAG_REGISTERED;
4897         bnxt_free_ctx_mem(bp);
4898         if (!reconfig_dev) {
4899                 bnxt_free_hwrm_resources(bp);
4900
4901                 if (bp->recovery_info != NULL) {
4902                         rte_free(bp->recovery_info);
4903                         bp->recovery_info = NULL;
4904                 }
4905         }
4906
4907         bnxt_uninit_locks(bp);
4908         rte_free(bp->ptp_cfg);
4909         bp->ptp_cfg = NULL;
4910         return rc;
4911 }
4912
4913 static int
4914 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4915 {
4916         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4917                 return -EPERM;
4918
4919         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4920
4921         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4922                 bnxt_dev_close_op(eth_dev);
4923
4924         return 0;
4925 }
4926
4927 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4928         struct rte_pci_device *pci_dev)
4929 {
4930         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4931                 bnxt_dev_init);
4932 }
4933
4934 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4935 {
4936         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4937                 return rte_eth_dev_pci_generic_remove(pci_dev,
4938                                 bnxt_dev_uninit);
4939         else
4940                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4941 }
4942
4943 static struct rte_pci_driver bnxt_rte_pmd = {
4944         .id_table = bnxt_pci_id_map,
4945         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4946         .probe = bnxt_pci_probe,
4947         .remove = bnxt_pci_remove,
4948 };
4949
4950 static bool
4951 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4952 {
4953         if (strcmp(dev->device->driver->name, drv->driver.name))
4954                 return false;
4955
4956         return true;
4957 }
4958
4959 bool is_bnxt_supported(struct rte_eth_dev *dev)
4960 {
4961         return is_device_supported(dev, &bnxt_rte_pmd);
4962 }
4963
4964 RTE_INIT(bnxt_init_log)
4965 {
4966         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4967         if (bnxt_logtype_driver >= 0)
4968                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4969 }
4970
4971 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4972 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4973 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");