drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_57508 0x1750
  74 #define BROADCOM_DEV_ID_57504 0x1751
  75 #define BROADCOM_DEV_ID_57502 0x1752
  76 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  77 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 131         { .vendor_id = 0, /* sentinel */ },
 132 };
 133
 134 #define BNXT_ETH_RSS_SUPPORT (  \
 135         ETH_RSS_IPV4 |          \
 136         ETH_RSS_NONFRAG_IPV4_TCP |      \
 137         ETH_RSS_NONFRAG_IPV4_UDP |      \
 138         ETH_RSS_IPV6 |          \
 139         ETH_RSS_NONFRAG_IPV6_TCP |      \
 140         ETH_RSS_NONFRAG_IPV6_UDP)
 141
 142 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 143                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 144                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_TSO | \
 147                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 148                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO | \
 165                                      DEV_RX_OFFLOAD_SCATTER)
 166
 167 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 168 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 169 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 170 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 171 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 172 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 173 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 174
 175 int is_bnxt_in_error(struct bnxt *bp)
 176 {
 177         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 178                 return -EIO;
 179         if (bp->flags & BNXT_FLAG_FW_RESET)
 180                 return -EBUSY;
 181
 182         return 0;
 183 }
 184
 185 /***********************/
 186
 187 /*
 188  * High level utility functions
 189  */
 190
 191 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 192 {
 193         if (!BNXT_CHIP_THOR(bp))
 194                 return 1;
 195
 196         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 197                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 198                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 199 }
 200
 201 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 202 {
 203         if (!BNXT_CHIP_THOR(bp))
 204                 return HW_HASH_INDEX_SIZE;
 205
 206         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 207 }
 208
 209 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 210 {
 211         bnxt_free_filter_mem(bp);
 212         bnxt_free_vnic_attributes(bp);
 213         bnxt_free_vnic_mem(bp);
 214
 215         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 216          * If the number of rings change across fw update,
 217          * we don't have much choice except to warn the user.
 218          */
 219         if (!reconfig) {
 220                 bnxt_free_stats(bp);
 221                 bnxt_free_tx_rings(bp);
 222                 bnxt_free_rx_rings(bp);
 223         }
 224         bnxt_free_async_cp_ring(bp);
 225         bnxt_free_rxtx_nq_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         rc = bnxt_alloc_rxtx_nq_ring(bp);
 257         if (rc)
 258                 goto alloc_mem_err;
 259
 260         return 0;
 261
 262 alloc_mem_err:
 263         bnxt_free_mem(bp, reconfig);
 264         return rc;
 265 }
 266
 267 static int bnxt_init_chip(struct bnxt *bp)
 268 {
 269         struct bnxt_rx_queue *rxq;
 270         struct rte_eth_link new;
 271         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 272         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 273         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 274         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 275         uint32_t intr_vector = 0;
 276         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 277         uint32_t vec = BNXT_MISC_VEC_ID;
 278         unsigned int i, j;
 279         int rc;
 280
 281         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 283                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags |= BNXT_FLAG_JUMBO;
 285         } else {
 286                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 287                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 288                 bp->flags &= ~BNXT_FLAG_JUMBO;
 289         }
 290
 291         /* THOR does not support ring groups.
 292          * But we will use the array to save RSS context IDs.
 293          */
 294         if (BNXT_CHIP_THOR(bp))
 295                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 296
 297         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         rc = bnxt_alloc_hwrm_rings(bp);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 306                 goto err_out;
 307         }
 308
 309         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 310         if (rc) {
 311                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 312                 goto err_out;
 313         }
 314
 315         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 316                 goto skip_cosq_cfg;
 317
 318         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 319                 if (bp->rx_cos_queue[i].id != 0xff) {
 320                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 321
 322                         if (!vnic) {
 323                                 PMD_DRV_LOG(ERR,
 324                                             "Num pools more than FW profile\n");
 325                                 rc = -EINVAL;
 326                                 goto err_out;
 327                         }
 328                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 329                         bp->rx_cosq_cnt++;
 330                 }
 331         }
 332
 333 skip_cosq_cfg:
 334         rc = bnxt_mq_rx_configure(bp);
 335         if (rc) {
 336                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 337                 goto err_out;
 338         }
 339
 340         /* VNIC configuration */
 341         for (i = 0; i < bp->nr_vnics; i++) {
 342                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 343                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 344
 345                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 346                 if (rc)
 347                         goto err_out;
 348
 349                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 350                             i, vnic, vnic->fw_grp_ids);
 351
 352                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 353                 if (rc) {
 354                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 355                                 i, rc);
 356                         goto err_out;
 357                 }
 358
 359                 /* Alloc RSS context only if RSS mode is enabled */
 360                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 361                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 362
 363                         rc = 0;
 364                         for (j = 0; j < nr_ctxs; j++) {
 365                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 366                                 if (rc)
 367                                         break;
 368                         }
 369                         if (rc) {
 370                                 PMD_DRV_LOG(ERR,
 371                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 372                                   i, j, rc);
 373                                 goto err_out;
 374                         }
 375                         vnic->num_lb_ctxts = nr_ctxs;
 376                 }
 377
 378                 /*
 379                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 380                  * setting is not available at this time, it will not be
 381                  * configured correctly in the CFA.
 382                  */
 383                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 384                         vnic->vlan_strip = true;
 385                 else
 386                         vnic->vlan_strip = false;
 387
 388                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 389                 if (rc) {
 390                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 391                                 i, rc);
 392                         goto err_out;
 393                 }
 394
 395                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 396                 if (rc) {
 397                         PMD_DRV_LOG(ERR,
 398                                 "HWRM vnic %d filter failure rc: %x\n",
 399                                 i, rc);
 400                         goto err_out;
 401                 }
 402
 403                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 404                         rxq = bp->eth_dev->data->rx_queues[j];
 405
 406                         PMD_DRV_LOG(DEBUG,
 407                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 408                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 409
 410                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 411                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 412                 }
 413
 414                 rc = bnxt_vnic_rss_configure(bp, vnic);
 415                 if (rc) {
 416                         PMD_DRV_LOG(ERR,
 417                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 418                         goto err_out;
 419                 }
 420
 421                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 422
 423                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 424                     DEV_RX_OFFLOAD_TCP_LRO)
 425                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 426                 else
 427                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 428         }
 429         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 430         if (rc) {
 431                 PMD_DRV_LOG(ERR,
 432                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 433                 goto err_out;
 434         }
 435
 436         /* check and configure queue intr-vector mapping */
 437         if ((rte_intr_cap_multiple(intr_handle) ||
 438              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 439             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 440                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 441                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 442                 if (intr_vector > bp->rx_cp_nr_rings) {
 443                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 444                                         bp->rx_cp_nr_rings);
 445                         return -ENOTSUP;
 446                 }
 447                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 448                 if (rc)
 449                         return rc;
 450         }
 451
 452         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 453                 intr_handle->intr_vec =
 454                         rte_zmalloc("intr_vec",
 455                                     bp->eth_dev->data->nb_rx_queues *
 456                                     sizeof(int), 0);
 457                 if (intr_handle->intr_vec == NULL) {
 458                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 459                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 460                         rc = -ENOMEM;
 461                         goto err_disable;
 462                 }
 463                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 464                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 465                          intr_handle->intr_vec, intr_handle->nb_efd,
 466                         intr_handle->max_intr);
 467                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 468                      queue_id++) {
 469                         intr_handle->intr_vec[queue_id] =
 470                                                         vec + BNXT_RX_VEC_START;
 471                         if (vec < base + intr_handle->nb_efd - 1)
 472                                 vec++;
 473                 }
 474         }
 475
 476         /* enable uio/vfio intr/eventfd mapping */
 477         rc = rte_intr_enable(intr_handle);
 478         if (rc)
 479                 goto err_free;
 480
 481         rc = bnxt_get_hwrm_link_config(bp, &new);
 482         if (rc) {
 483                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 484                 goto err_free;
 485         }
 486
 487         if (!bp->link_info.link_up) {
 488                 rc = bnxt_set_hwrm_link_config(bp, true);
 489                 if (rc) {
 490                         PMD_DRV_LOG(ERR,
 491                                 "HWRM link config failure rc: %x\n", rc);
 492                         goto err_free;
 493                 }
 494         }
 495         bnxt_print_link_info(bp->eth_dev);
 496
 497         return 0;
 498
 499 err_free:
 500         rte_free(intr_handle->intr_vec);
 501 err_disable:
 502         rte_intr_efd_disable(intr_handle);
 503 err_out:
 504         /* Some of the error status returned by FW may not be from errno.h */
 505         if (rc > 0)
 506                 rc = -EIO;
 507
 508         return rc;
 509 }
 510
 511 static int bnxt_shutdown_nic(struct bnxt *bp)
 512 {
 513         bnxt_free_all_hwrm_resources(bp);
 514         bnxt_free_all_filters(bp);
 515         bnxt_free_all_vnics(bp);
 516         return 0;
 517 }
 518
 519 static int bnxt_init_nic(struct bnxt *bp)
 520 {
 521         int rc;
 522
 523         if (BNXT_HAS_RING_GRPS(bp)) {
 524                 rc = bnxt_init_ring_grps(bp);
 525                 if (rc)
 526                         return rc;
 527         }
 528
 529         bnxt_init_vnics(bp);
 530         bnxt_init_filters(bp);
 531
 532         return 0;
 533 }
 534
 535 /*
 536  * Device configuration and status function
 537  */
 538
 539 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 540                                 struct rte_eth_dev_info *dev_info)
 541 {
 542         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 543         struct bnxt *bp = eth_dev->data->dev_private;
 544         uint16_t max_vnics, i, j, vpool, vrxq;
 545         unsigned int max_rx_rings;
 546         int rc;
 547
 548         rc = is_bnxt_in_error(bp);
 549         if (rc)
 550                 return rc;
 551
 552         /* MAC Specifics */
 553         dev_info->max_mac_addrs = bp->max_l2_ctx;
 554         dev_info->max_hash_mac_addrs = 0;
 555
 556         /* PF/VF specifics */
 557         if (BNXT_PF(bp))
 558                 dev_info->max_vfs = pdev->max_vfs;
 559
 560         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 561         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 562         dev_info->max_rx_queues = max_rx_rings;
 563         dev_info->max_tx_queues = max_rx_rings;
 564         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 565         dev_info->hash_key_size = 40;
 566         max_vnics = bp->max_vnics;
 567
 568         /* MTU specifics */
 569         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 570         dev_info->max_mtu = BNXT_MAX_MTU;
 571
 572         /* Fast path specifics */
 573         dev_info->min_rx_bufsize = 1;
 574         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 575
 576         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 577         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 578                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 579         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 580         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 581
 582         /* *INDENT-OFF* */
 583         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 584                 .rx_thresh = {
 585                         .pthresh = 8,
 586                         .hthresh = 8,
 587                         .wthresh = 0,
 588                 },
 589                 .rx_free_thresh = 32,
 590                 /* If no descriptors available, pkts are dropped by default */
 591                 .rx_drop_en = 1,
 592         };
 593
 594         dev_info->default_txconf = (struct rte_eth_txconf) {
 595                 .tx_thresh = {
 596                         .pthresh = 32,
 597                         .hthresh = 0,
 598                         .wthresh = 0,
 599                 },
 600                 .tx_free_thresh = 32,
 601                 .tx_rs_thresh = 32,
 602         };
 603         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 604
 605         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 606         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 607         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 608         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 609         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 610
 611         /* *INDENT-ON* */
 612
 613         /*
 614          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 615          *       need further investigation.
 616          */
 617
 618         /* VMDq resources */
 619         vpool = 64; /* ETH_64_POOLS */
 620         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 621         for (i = 0; i < 4; vpool >>= 1, i++) {
 622                 if (max_vnics > vpool) {
 623                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 624                                 if (dev_info->max_rx_queues > vrxq) {
 625                                         if (vpool > vrxq)
 626                                                 vpool = vrxq;
 627                                         goto found;
 628                                 }
 629                         }
 630                         /* Not enough resources to support VMDq */
 631                         break;
 632                 }
 633         }
 634         /* Not enough resources to support VMDq */
 635         vpool = 0;
 636         vrxq = 0;
 637 found:
 638         dev_info->max_vmdq_pools = vpool;
 639         dev_info->vmdq_queue_num = vrxq;
 640
 641         dev_info->vmdq_pool_base = 0;
 642         dev_info->vmdq_queue_base = 0;
 643
 644         return 0;
 645 }
 646
 647 /* Configure the device based on the configuration provided */
 648 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 649 {
 650         struct bnxt *bp = eth_dev->data->dev_private;
 651         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 652         int rc;
 653
 654         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 655         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 656         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 657         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 658
 659         rc = is_bnxt_in_error(bp);
 660         if (rc)
 661                 return rc;
 662
 663         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 664                 rc = bnxt_hwrm_check_vf_rings(bp);
 665                 if (rc) {
 666                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 667                         return -ENOSPC;
 668                 }
 669
 670                 /* If a resource has already been allocated - in this case
 671                  * it is the async completion ring, free it. Reallocate it after
 672                  * resource reservation. This will ensure the resource counts
 673                  * are calculated correctly.
 674                  */
 675                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 676                         bnxt_disable_int(bp);
 677                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 678                 }
 679
 680                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 681                 if (rc) {
 682                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 683                         return -ENOSPC;
 684                 }
 685
 686                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 687                         rc = bnxt_alloc_async_cp_ring(bp);
 688                         if (rc)
 689                                 return rc;
 690                         bnxt_enable_int(bp);
 691                 }
 692         } else {
 693                 /* legacy driver needs to get updated values */
 694                 rc = bnxt_hwrm_func_qcaps(bp);
 695                 if (rc) {
 696                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 697                         return rc;
 698                 }
 699         }
 700
 701         /* Inherit new configurations */
 702         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 703             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 704             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 705                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 706             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 707             bp->max_stat_ctx)
 708                 goto resource_error;
 709
 710         if (BNXT_HAS_RING_GRPS(bp) &&
 711             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 712                 goto resource_error;
 713
 714         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 715             bp->max_vnics < eth_dev->data->nb_rx_queues)
 716                 goto resource_error;
 717
 718         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 719         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 720
 721         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 722                 eth_dev->data->mtu =
 723                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 724                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 725                         BNXT_NUM_VLANS;
 726                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 727         }
 728         return 0;
 729
 730 resource_error:
 731         PMD_DRV_LOG(ERR,
 732                     "Insufficient resources to support requested config\n");
 733         PMD_DRV_LOG(ERR,
 734                     "Num Queues Requested: Tx %d, Rx %d\n",
 735                     eth_dev->data->nb_tx_queues,
 736                     eth_dev->data->nb_rx_queues);
 737         PMD_DRV_LOG(ERR,
 738                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 739                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 740                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 741         return -ENOSPC;
 742 }
 743
 744 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 745 {
 746         struct rte_eth_link *link = &eth_dev->data->dev_link;
 747
 748         if (link->link_status)
 749                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 750                         eth_dev->data->port_id,
 751                         (uint32_t)link->link_speed,
 752                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 753                         ("full-duplex") : ("half-duplex\n"));
 754         else
 755                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 756                         eth_dev->data->port_id);
 757 }
 758
 759 /*
 760  * Determine whether the current configuration requires support for scattered
 761  * receive; return 1 if scattered receive is required and 0 if not.
 762  */
 763 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 764 {
 765         uint16_t buf_size;
 766         int i;
 767
 768         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 769                 return 1;
 770
 771         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 772                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 773
 774                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 775                                       RTE_PKTMBUF_HEADROOM);
 776                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 777                         return 1;
 778         }
 779         return 0;
 780 }
 781
 782 static eth_rx_burst_t
 783 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 784 {
 785 #ifdef RTE_ARCH_X86
 786 #ifndef RTE_LIBRTE_IEEE1588
 787         /*
 788          * Vector mode receive can be enabled only if scatter rx is not
 789          * in use and rx offloads are limited to VLAN stripping and
 790          * CRC stripping.
 791          */
 792         if (!eth_dev->data->scattered_rx &&
 793             !(eth_dev->data->dev_conf.rxmode.offloads &
 794               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 795                 DEV_RX_OFFLOAD_KEEP_CRC |
 796                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 797                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 798                 DEV_RX_OFFLOAD_UDP_CKSUM |
 799                 DEV_RX_OFFLOAD_TCP_CKSUM |
 800                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 801                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 802                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 803                             eth_dev->data->port_id);
 804                 return bnxt_recv_pkts_vec;
 805         }
 806         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 807                     eth_dev->data->port_id);
 808         PMD_DRV_LOG(INFO,
 809                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 810                     eth_dev->data->port_id,
 811                     eth_dev->data->scattered_rx,
 812                     eth_dev->data->dev_conf.rxmode.offloads);
 813 #endif
 814 #endif
 815         return bnxt_recv_pkts;
 816 }
 817
 818 static eth_tx_burst_t
 819 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 820 {
 821 #ifdef RTE_ARCH_X86
 822 #ifndef RTE_LIBRTE_IEEE1588
 823         /*
 824          * Vector mode transmit can be enabled only if not using scatter rx
 825          * or tx offloads.
 826          */
 827         if (!eth_dev->data->scattered_rx &&
 828             !eth_dev->data->dev_conf.txmode.offloads) {
 829                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 830                             eth_dev->data->port_id);
 831                 return bnxt_xmit_pkts_vec;
 832         }
 833         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 834                     eth_dev->data->port_id);
 835         PMD_DRV_LOG(INFO,
 836                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 837                     eth_dev->data->port_id,
 838                     eth_dev->data->scattered_rx,
 839                     eth_dev->data->dev_conf.txmode.offloads);
 840 #endif
 841 #endif
 842         return bnxt_xmit_pkts;
 843 }
 844
 845 static int bnxt_handle_if_change_status(struct bnxt *bp)
 846 {
 847         int rc;
 848
 849         /* Since fw has undergone a reset and lost all contexts,
 850          * set fatal flag to not issue hwrm during cleanup
 851          */
 852         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 853         bnxt_uninit_resources(bp, true);
 854
 855         /* clear fatal flag so that re-init happens */
 856         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 857         rc = bnxt_init_resources(bp, true);
 858
 859         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 860
 861         return rc;
 862 }
 863
 864 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 865 {
 866         struct bnxt *bp = eth_dev->data->dev_private;
 867         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 868         int vlan_mask = 0;
 869         int rc;
 870
 871         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 872                 PMD_DRV_LOG(ERR,
 873                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 874                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 875         }
 876
 877         rc = bnxt_hwrm_if_change(bp, 1);
 878         if (!rc) {
 879                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 880                         rc = bnxt_handle_if_change_status(bp);
 881                         if (rc)
 882                                 return rc;
 883                 }
 884         }
 885         bnxt_enable_int(bp);
 886
 887         rc = bnxt_init_chip(bp);
 888         if (rc)
 889                 goto error;
 890
 891         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 892
 893         bnxt_link_update_op(eth_dev, 1);
 894
 895         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 896                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 897         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 898                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 899         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 900         if (rc)
 901                 goto error;
 902
 903         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 904         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 905
 906         bp->flags |= BNXT_FLAG_INIT_DONE;
 907         eth_dev->data->dev_started = 1;
 908         bp->dev_stopped = 0;
 909         bnxt_schedule_fw_health_check(bp);
 910         return 0;
 911
 912 error:
 913         bnxt_hwrm_if_change(bp, 0);
 914         bnxt_shutdown_nic(bp);
 915         bnxt_free_tx_mbufs(bp);
 916         bnxt_free_rx_mbufs(bp);
 917         return rc;
 918 }
 919
 920 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 921 {
 922         struct bnxt *bp = eth_dev->data->dev_private;
 923         int rc = 0;
 924
 925         if (!bp->link_info.link_up)
 926                 rc = bnxt_set_hwrm_link_config(bp, true);
 927         if (!rc)
 928                 eth_dev->data->dev_link.link_status = 1;
 929
 930         bnxt_print_link_info(eth_dev);
 931         return rc;
 932 }
 933
 934 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 935 {
 936         struct bnxt *bp = eth_dev->data->dev_private;
 937
 938         eth_dev->data->dev_link.link_status = 0;
 939         bnxt_set_hwrm_link_config(bp, false);
 940         bp->link_info.link_up = 0;
 941
 942         return 0;
 943 }
 944
 945 /* Unload the driver, release resources */
 946 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 947 {
 948         struct bnxt *bp = eth_dev->data->dev_private;
 949         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 950         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 951
 952         eth_dev->data->dev_started = 0;
 953         /* Prevent crashes when queues are still in use */
 954         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 955         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 956
 957         bnxt_disable_int(bp);
 958
 959         /* disable uio/vfio intr/eventfd mapping */
 960         rte_intr_disable(intr_handle);
 961
 962         bnxt_cancel_fw_health_check(bp);
 963
 964         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 965         if (bp->eth_dev->data->dev_started) {
 966                 /* TBD: STOP HW queues DMA */
 967                 eth_dev->data->dev_link.link_status = 0;
 968         }
 969         bnxt_dev_set_link_down_op(eth_dev);
 970
 971         /* Wait for link to be reset and the async notification to process.
 972          * During reset recovery, there is no need to wait
 973          */
 974         if (!is_bnxt_in_error(bp))
 975                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 976
 977         /* Clean queue intr-vector mapping */
 978         rte_intr_efd_disable(intr_handle);
 979         if (intr_handle->intr_vec != NULL) {
 980                 rte_free(intr_handle->intr_vec);
 981                 intr_handle->intr_vec = NULL;
 982         }
 983
 984         bnxt_hwrm_port_clr_stats(bp);
 985         bnxt_free_tx_mbufs(bp);
 986         bnxt_free_rx_mbufs(bp);
 987         /* Process any remaining notifications in default completion queue */
 988         bnxt_int_handler(eth_dev);
 989         bnxt_shutdown_nic(bp);
 990         bnxt_hwrm_if_change(bp, 0);
 991         bp->dev_stopped = 1;
 992 }
 993
 994 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 995 {
 996         struct bnxt *bp = eth_dev->data->dev_private;
 997
 998         if (bp->dev_stopped == 0)
 999                 bnxt_dev_stop_op(eth_dev);
1000
1001         if (eth_dev->data->mac_addrs != NULL) {
1002                 rte_free(eth_dev->data->mac_addrs);
1003                 eth_dev->data->mac_addrs = NULL;
1004         }
1005         if (bp->grp_info != NULL) {
1006                 rte_free(bp->grp_info);
1007                 bp->grp_info = NULL;
1008         }
1009
1010         bnxt_dev_uninit(eth_dev);
1011 }
1012
1013 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1014                                     uint32_t index)
1015 {
1016         struct bnxt *bp = eth_dev->data->dev_private;
1017         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1018         struct bnxt_vnic_info *vnic;
1019         struct bnxt_filter_info *filter, *temp_filter;
1020         uint32_t i;
1021
1022         if (is_bnxt_in_error(bp))
1023                 return;
1024
1025         /*
1026          * Loop through all VNICs from the specified filter flow pools to
1027          * remove the corresponding MAC addr filter
1028          */
1029         for (i = 0; i < bp->nr_vnics; i++) {
1030                 if (!(pool_mask & (1ULL << i)))
1031                         continue;
1032
1033                 vnic = &bp->vnic_info[i];
1034                 filter = STAILQ_FIRST(&vnic->filter);
1035                 while (filter) {
1036                         temp_filter = STAILQ_NEXT(filter, next);
1037                         if (filter->mac_index == index) {
1038                                 STAILQ_REMOVE(&vnic->filter, filter,
1039                                                 bnxt_filter_info, next);
1040                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1041                                 filter->mac_index = INVALID_MAC_INDEX;
1042                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1043                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1044                                                    filter, next);
1045                         }
1046                         filter = temp_filter;
1047                 }
1048         }
1049 }
1050
1051 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1052                                struct rte_ether_addr *mac_addr, uint32_t index)
1053 {
1054         struct bnxt_filter_info *filter;
1055         int rc = 0;
1056
1057         filter = STAILQ_FIRST(&vnic->filter);
1058         /* During bnxt_mac_addr_add_op, default MAC is
1059          * already programmed, so skip it. But, when
1060          * hw-vlan-filter is turned OFF from ON, default
1061          * MAC filter should be restored
1062          */
1063         if (filter->dflt)
1064                 return 0;
1065
1066         filter = bnxt_alloc_filter(bp);
1067         if (!filter) {
1068                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1069                 return -ENODEV;
1070         }
1071
1072         filter->mac_index = index;
1073         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1074          * if the MAC that's been programmed now is a different one, then,
1075          * copy that addr to filter->l2_addr
1076          */
1077         if (mac_addr)
1078                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1079         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1080
1081         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1082         if (!rc) {
1083                 if (filter->mac_index == 0) {
1084                         filter->dflt = true;
1085                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1086                 } else {
1087                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1088                 }
1089         } else {
1090                 filter->mac_index = INVALID_MAC_INDEX;
1091                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1092                 bnxt_free_filter(bp, filter);
1093         }
1094
1095         return rc;
1096 }
1097
1098 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1099                                 struct rte_ether_addr *mac_addr,
1100                                 uint32_t index, uint32_t pool)
1101 {
1102         struct bnxt *bp = eth_dev->data->dev_private;
1103         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1104         struct bnxt_filter_info *filter;
1105         int rc = 0;
1106
1107         rc = is_bnxt_in_error(bp);
1108         if (rc)
1109                 return rc;
1110
1111         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1112                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1113                 return -ENOTSUP;
1114         }
1115
1116         if (!vnic) {
1117                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1118                 return -EINVAL;
1119         }
1120         /* Attach requested MAC address to the new l2_filter */
1121         STAILQ_FOREACH(filter, &vnic->filter, next) {
1122                 if (filter->mac_index == index) {
1123                         PMD_DRV_LOG(ERR,
1124                                 "MAC addr already existed for pool %d\n", pool);
1125                         return 0;
1126                 }
1127         }
1128
1129         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1130
1131         return rc;
1132 }
1133
1134 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1135 {
1136         int rc = 0;
1137         struct bnxt *bp = eth_dev->data->dev_private;
1138         struct rte_eth_link new;
1139         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1140
1141         rc = is_bnxt_in_error(bp);
1142         if (rc)
1143                 return rc;
1144
1145         memset(&new, 0, sizeof(new));
1146         do {
1147                 /* Retrieve link info from hardware */
1148                 rc = bnxt_get_hwrm_link_config(bp, &new);
1149                 if (rc) {
1150                         new.link_speed = ETH_LINK_SPEED_100M;
1151                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1152                         PMD_DRV_LOG(ERR,
1153                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1154                         goto out;
1155                 }
1156
1157                 if (!wait_to_complete || new.link_status)
1158                         break;
1159
1160                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1161         } while (cnt--);
1162
1163 out:
1164         /* Timed out or success */
1165         if (new.link_status != eth_dev->data->dev_link.link_status ||
1166         new.link_speed != eth_dev->data->dev_link.link_speed) {
1167                 rte_eth_linkstatus_set(eth_dev, &new);
1168
1169                 _rte_eth_dev_callback_process(eth_dev,
1170                                               RTE_ETH_EVENT_INTR_LSC,
1171                                               NULL);
1172
1173                 bnxt_print_link_info(eth_dev);
1174         }
1175
1176         return rc;
1177 }
1178
1179 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1180 {
1181         struct bnxt *bp = eth_dev->data->dev_private;
1182         struct bnxt_vnic_info *vnic;
1183         uint32_t old_flags;
1184         int rc;
1185
1186         rc = is_bnxt_in_error(bp);
1187         if (rc)
1188                 return rc;
1189
1190         if (bp->vnic_info == NULL)
1191                 return 0;
1192
1193         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1194
1195         old_flags = vnic->flags;
1196         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1197         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1198         if (rc != 0)
1199                 vnic->flags = old_flags;
1200
1201         return rc;
1202 }
1203
1204 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1205 {
1206         struct bnxt *bp = eth_dev->data->dev_private;
1207         struct bnxt_vnic_info *vnic;
1208         uint32_t old_flags;
1209         int rc;
1210
1211         rc = is_bnxt_in_error(bp);
1212         if (rc)
1213                 return rc;
1214
1215         if (bp->vnic_info == NULL)
1216                 return 0;
1217
1218         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1219
1220         old_flags = vnic->flags;
1221         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1222         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1223         if (rc != 0)
1224                 vnic->flags = old_flags;
1225
1226         return rc;
1227 }
1228
1229 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1230 {
1231         struct bnxt *bp = eth_dev->data->dev_private;
1232         struct bnxt_vnic_info *vnic;
1233         uint32_t old_flags;
1234         int rc;
1235
1236         rc = is_bnxt_in_error(bp);
1237         if (rc)
1238                 return rc;
1239
1240         if (bp->vnic_info == NULL)
1241                 return 0;
1242
1243         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1244
1245         old_flags = vnic->flags;
1246         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1247         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1248         if (rc != 0)
1249                 vnic->flags = old_flags;
1250
1251         return rc;
1252 }
1253
1254 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1255 {
1256         struct bnxt *bp = eth_dev->data->dev_private;
1257         struct bnxt_vnic_info *vnic;
1258         uint32_t old_flags;
1259         int rc;
1260
1261         rc = is_bnxt_in_error(bp);
1262         if (rc)
1263                 return rc;
1264
1265         if (bp->vnic_info == NULL)
1266                 return 0;
1267
1268         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1269
1270         old_flags = vnic->flags;
1271         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1272         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1273         if (rc != 0)
1274                 vnic->flags = old_flags;
1275
1276         return rc;
1277 }
1278
1279 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1280 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1281 {
1282         if (qid >= bp->rx_nr_rings)
1283                 return NULL;
1284
1285         return bp->eth_dev->data->rx_queues[qid];
1286 }
1287
1288 /* Return rxq corresponding to a given rss table ring/group ID. */
1289 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1290 {
1291         struct bnxt_rx_queue *rxq;
1292         unsigned int i;
1293
1294         if (!BNXT_HAS_RING_GRPS(bp)) {
1295                 for (i = 0; i < bp->rx_nr_rings; i++) {
1296                         rxq = bp->eth_dev->data->rx_queues[i];
1297                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1298                                 return rxq->index;
1299                 }
1300         } else {
1301                 for (i = 0; i < bp->rx_nr_rings; i++) {
1302                         if (bp->grp_info[i].fw_grp_id == fwr)
1303                                 return i;
1304                 }
1305         }
1306
1307         return INVALID_HW_RING_ID;
1308 }
1309
1310 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1311                             struct rte_eth_rss_reta_entry64 *reta_conf,
1312                             uint16_t reta_size)
1313 {
1314         struct bnxt *bp = eth_dev->data->dev_private;
1315         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1316         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1317         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1318         uint16_t idx, sft;
1319         int i, rc;
1320
1321         rc = is_bnxt_in_error(bp);
1322         if (rc)
1323                 return rc;
1324
1325         if (!vnic->rss_table)
1326                 return -EINVAL;
1327
1328         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1329                 return -EINVAL;
1330
1331         if (reta_size != tbl_size) {
1332                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1333                         "(%d) must equal the size supported by the hardware "
1334                         "(%d)\n", reta_size, tbl_size);
1335                 return -EINVAL;
1336         }
1337
1338         for (i = 0; i < reta_size; i++) {
1339                 struct bnxt_rx_queue *rxq;
1340
1341                 idx = i / RTE_RETA_GROUP_SIZE;
1342                 sft = i % RTE_RETA_GROUP_SIZE;
1343
1344                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1345                         continue;
1346
1347                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1348                 if (!rxq) {
1349                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1350                         return -EINVAL;
1351                 }
1352
1353                 if (BNXT_CHIP_THOR(bp)) {
1354                         vnic->rss_table[i * 2] =
1355                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1356                         vnic->rss_table[i * 2 + 1] =
1357                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1358                 } else {
1359                         vnic->rss_table[i] =
1360                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1361                 }
1362
1363                 vnic->rss_table[i] =
1364                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1365         }
1366
1367         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1368         return 0;
1369 }
1370
1371 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1372                               struct rte_eth_rss_reta_entry64 *reta_conf,
1373                               uint16_t reta_size)
1374 {
1375         struct bnxt *bp = eth_dev->data->dev_private;
1376         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1377         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1378         uint16_t idx, sft, i;
1379         int rc;
1380
1381         rc = is_bnxt_in_error(bp);
1382         if (rc)
1383                 return rc;
1384
1385         /* Retrieve from the default VNIC */
1386         if (!vnic)
1387                 return -EINVAL;
1388         if (!vnic->rss_table)
1389                 return -EINVAL;
1390
1391         if (reta_size != tbl_size) {
1392                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1393                         "(%d) must equal the size supported by the hardware "
1394                         "(%d)\n", reta_size, tbl_size);
1395                 return -EINVAL;
1396         }
1397
1398         for (idx = 0, i = 0; i < reta_size; i++) {
1399                 idx = i / RTE_RETA_GROUP_SIZE;
1400                 sft = i % RTE_RETA_GROUP_SIZE;
1401
1402                 if (reta_conf[idx].mask & (1ULL << sft)) {
1403                         uint16_t qid;
1404
1405                         if (BNXT_CHIP_THOR(bp))
1406                                 qid = bnxt_rss_to_qid(bp,
1407                                                       vnic->rss_table[i * 2]);
1408                         else
1409                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1410
1411                         if (qid == INVALID_HW_RING_ID) {
1412                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1413                                 return -EINVAL;
1414                         }
1415                         reta_conf[idx].reta[sft] = qid;
1416                 }
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1423                                    struct rte_eth_rss_conf *rss_conf)
1424 {
1425         struct bnxt *bp = eth_dev->data->dev_private;
1426         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1427         struct bnxt_vnic_info *vnic;
1428         int rc;
1429
1430         rc = is_bnxt_in_error(bp);
1431         if (rc)
1432                 return rc;
1433
1434         /*
1435          * If RSS enablement were different than dev_configure,
1436          * then return -EINVAL
1437          */
1438         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1439                 if (!rss_conf->rss_hf)
1440                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1441         } else {
1442                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1443                         return -EINVAL;
1444         }
1445
1446         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1447         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1448
1449         /* Update the default RSS VNIC(s) */
1450         vnic = &bp->vnic_info[0];
1451         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1452
1453         /*
1454          * If hashkey is not specified, use the previously configured
1455          * hashkey
1456          */
1457         if (!rss_conf->rss_key)
1458                 goto rss_config;
1459
1460         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1461                 PMD_DRV_LOG(ERR,
1462                             "Invalid hashkey length, should be 16 bytes\n");
1463                 return -EINVAL;
1464         }
1465         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1466
1467 rss_config:
1468         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1469         return 0;
1470 }
1471
1472 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1473                                      struct rte_eth_rss_conf *rss_conf)
1474 {
1475         struct bnxt *bp = eth_dev->data->dev_private;
1476         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1477         int len, rc;
1478         uint32_t hash_types;
1479
1480         rc = is_bnxt_in_error(bp);
1481         if (rc)
1482                 return rc;
1483
1484         /* RSS configuration is the same for all VNICs */
1485         if (vnic && vnic->rss_hash_key) {
1486                 if (rss_conf->rss_key) {
1487                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1488                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1489                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1490                 }
1491
1492                 hash_types = vnic->hash_type;
1493                 rss_conf->rss_hf = 0;
1494                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1495                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1496                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1497                 }
1498                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1499                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1500                         hash_types &=
1501                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1502                 }
1503                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1504                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1505                         hash_types &=
1506                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1507                 }
1508                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1509                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1510                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1511                 }
1512                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1513                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1514                         hash_types &=
1515                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1516                 }
1517                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1518                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1519                         hash_types &=
1520                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1521                 }
1522                 if (hash_types) {
1523                         PMD_DRV_LOG(ERR,
1524                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1525                                 vnic->hash_type);
1526                         return -ENOTSUP;
1527                 }
1528         } else {
1529                 rss_conf->rss_hf = 0;
1530         }
1531         return 0;
1532 }
1533
1534 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1535                                struct rte_eth_fc_conf *fc_conf)
1536 {
1537         struct bnxt *bp = dev->data->dev_private;
1538         struct rte_eth_link link_info;
1539         int rc;
1540
1541         rc = is_bnxt_in_error(bp);
1542         if (rc)
1543                 return rc;
1544
1545         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1546         if (rc)
1547                 return rc;
1548
1549         memset(fc_conf, 0, sizeof(*fc_conf));
1550         if (bp->link_info.auto_pause)
1551                 fc_conf->autoneg = 1;
1552         switch (bp->link_info.pause) {
1553         case 0:
1554                 fc_conf->mode = RTE_FC_NONE;
1555                 break;
1556         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1557                 fc_conf->mode = RTE_FC_TX_PAUSE;
1558                 break;
1559         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1560                 fc_conf->mode = RTE_FC_RX_PAUSE;
1561                 break;
1562         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1563                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1564                 fc_conf->mode = RTE_FC_FULL;
1565                 break;
1566         }
1567         return 0;
1568 }
1569
1570 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1571                                struct rte_eth_fc_conf *fc_conf)
1572 {
1573         struct bnxt *bp = dev->data->dev_private;
1574         int rc;
1575
1576         rc = is_bnxt_in_error(bp);
1577         if (rc)
1578                 return rc;
1579
1580         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1581                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1582                 return -ENOTSUP;
1583         }
1584
1585         switch (fc_conf->mode) {
1586         case RTE_FC_NONE:
1587                 bp->link_info.auto_pause = 0;
1588                 bp->link_info.force_pause = 0;
1589                 break;
1590         case RTE_FC_RX_PAUSE:
1591                 if (fc_conf->autoneg) {
1592                         bp->link_info.auto_pause =
1593                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1594                         bp->link_info.force_pause = 0;
1595                 } else {
1596                         bp->link_info.auto_pause = 0;
1597                         bp->link_info.force_pause =
1598                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1599                 }
1600                 break;
1601         case RTE_FC_TX_PAUSE:
1602                 if (fc_conf->autoneg) {
1603                         bp->link_info.auto_pause =
1604                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1605                         bp->link_info.force_pause = 0;
1606                 } else {
1607                         bp->link_info.auto_pause = 0;
1608                         bp->link_info.force_pause =
1609                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1610                 }
1611                 break;
1612         case RTE_FC_FULL:
1613                 if (fc_conf->autoneg) {
1614                         bp->link_info.auto_pause =
1615                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1616                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1617                         bp->link_info.force_pause = 0;
1618                 } else {
1619                         bp->link_info.auto_pause = 0;
1620                         bp->link_info.force_pause =
1621                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1622                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1623                 }
1624                 break;
1625         }
1626         return bnxt_set_hwrm_link_config(bp, true);
1627 }
1628
1629 /* Add UDP tunneling port */
1630 static int
1631 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1632                          struct rte_eth_udp_tunnel *udp_tunnel)
1633 {
1634         struct bnxt *bp = eth_dev->data->dev_private;
1635         uint16_t tunnel_type = 0;
1636         int rc = 0;
1637
1638         rc = is_bnxt_in_error(bp);
1639         if (rc)
1640                 return rc;
1641
1642         switch (udp_tunnel->prot_type) {
1643         case RTE_TUNNEL_TYPE_VXLAN:
1644                 if (bp->vxlan_port_cnt) {
1645                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1646                                 udp_tunnel->udp_port);
1647                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1648                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1649                                 return -ENOSPC;
1650                         }
1651                         bp->vxlan_port_cnt++;
1652                         return 0;
1653                 }
1654                 tunnel_type =
1655                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1656                 bp->vxlan_port_cnt++;
1657                 break;
1658         case RTE_TUNNEL_TYPE_GENEVE:
1659                 if (bp->geneve_port_cnt) {
1660                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1661                                 udp_tunnel->udp_port);
1662                         if (bp->geneve_port != udp_tunnel->udp_port) {
1663                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1664                                 return -ENOSPC;
1665                         }
1666                         bp->geneve_port_cnt++;
1667                         return 0;
1668                 }
1669                 tunnel_type =
1670                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1671                 bp->geneve_port_cnt++;
1672                 break;
1673         default:
1674                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1675                 return -ENOTSUP;
1676         }
1677         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1678                                              tunnel_type);
1679         return rc;
1680 }
1681
1682 static int
1683 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1684                          struct rte_eth_udp_tunnel *udp_tunnel)
1685 {
1686         struct bnxt *bp = eth_dev->data->dev_private;
1687         uint16_t tunnel_type = 0;
1688         uint16_t port = 0;
1689         int rc = 0;
1690
1691         rc = is_bnxt_in_error(bp);
1692         if (rc)
1693                 return rc;
1694
1695         switch (udp_tunnel->prot_type) {
1696         case RTE_TUNNEL_TYPE_VXLAN:
1697                 if (!bp->vxlan_port_cnt) {
1698                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1699                         return -EINVAL;
1700                 }
1701                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1702                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1703                                 udp_tunnel->udp_port, bp->vxlan_port);
1704                         return -EINVAL;
1705                 }
1706                 if (--bp->vxlan_port_cnt)
1707                         return 0;
1708
1709                 tunnel_type =
1710                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1711                 port = bp->vxlan_fw_dst_port_id;
1712                 break;
1713         case RTE_TUNNEL_TYPE_GENEVE:
1714                 if (!bp->geneve_port_cnt) {
1715                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1716                         return -EINVAL;
1717                 }
1718                 if (bp->geneve_port != udp_tunnel->udp_port) {
1719                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1720                                 udp_tunnel->udp_port, bp->geneve_port);
1721                         return -EINVAL;
1722                 }
1723                 if (--bp->geneve_port_cnt)
1724                         return 0;
1725
1726                 tunnel_type =
1727                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1728                 port = bp->geneve_fw_dst_port_id;
1729                 break;
1730         default:
1731                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1732                 return -ENOTSUP;
1733         }
1734
1735         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1736         if (!rc) {
1737                 if (tunnel_type ==
1738                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1739                         bp->vxlan_port = 0;
1740                 if (tunnel_type ==
1741                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1742                         bp->geneve_port = 0;
1743         }
1744         return rc;
1745 }
1746
1747 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1748 {
1749         struct bnxt_filter_info *filter;
1750         struct bnxt_vnic_info *vnic;
1751         int rc = 0;
1752         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1753
1754         /* if VLAN exists && VLAN matches vlan_id
1755          *      remove the MAC+VLAN filter
1756          *      add a new MAC only filter
1757          * else
1758          *      VLAN filter doesn't exist, just skip and continue
1759          */
1760         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1761         filter = STAILQ_FIRST(&vnic->filter);
1762         while (filter) {
1763                 /* Search for this matching MAC+VLAN filter */
1764                 if ((filter->enables & chk) &&
1765                     (filter->l2_ivlan == vlan_id &&
1766                      filter->l2_ivlan_mask != 0) &&
1767                     !memcmp(filter->l2_addr, bp->mac_addr,
1768                             RTE_ETHER_ADDR_LEN)) {
1769                         /* Delete the filter */
1770                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1771                         if (rc)
1772                                 return rc;
1773                         STAILQ_REMOVE(&vnic->filter, filter,
1774                                       bnxt_filter_info, next);
1775                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1776
1777                         PMD_DRV_LOG(INFO,
1778                                     "Del Vlan filter for %d\n",
1779                                     vlan_id);
1780                         return rc;
1781                 }
1782                 filter = STAILQ_NEXT(filter, next);
1783         }
1784         return -ENOENT;
1785 }
1786
1787 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1788 {
1789         struct bnxt_filter_info *filter;
1790         struct bnxt_vnic_info *vnic;
1791         int rc = 0;
1792         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1793                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1794         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1795
1796         /* Implementation notes on the use of VNIC in this command:
1797          *
1798          * By default, these filters belong to default vnic for the function.
1799          * Once these filters are set up, only destination VNIC can be modified.
1800          * If the destination VNIC is not specified in this command,
1801          * then the HWRM shall only create an l2 context id.
1802          */
1803
1804         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1805         filter = STAILQ_FIRST(&vnic->filter);
1806         /* Check if the VLAN has already been added */
1807         while (filter) {
1808                 if ((filter->enables & chk) &&
1809                     (filter->l2_ivlan == vlan_id &&
1810                      filter->l2_ivlan_mask == 0x0FFF) &&
1811                      !memcmp(filter->l2_addr, bp->mac_addr,
1812                              RTE_ETHER_ADDR_LEN))
1813                         return -EEXIST;
1814
1815                 filter = STAILQ_NEXT(filter, next);
1816         }
1817
1818         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1819          * command to create MAC+VLAN filter with the right flags, enables set.
1820          */
1821         filter = bnxt_alloc_filter(bp);
1822         if (!filter) {
1823                 PMD_DRV_LOG(ERR,
1824                             "MAC/VLAN filter alloc failed\n");
1825                 return -ENOMEM;
1826         }
1827         /* MAC + VLAN ID filter */
1828         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1829          * untagged packets are received
1830          *
1831          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1832          * packets and only the programmed vlan's packets are received
1833          */
1834         filter->l2_ivlan = vlan_id;
1835         filter->l2_ivlan_mask = 0x0FFF;
1836         filter->enables |= en;
1837         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1838
1839         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1840         if (rc) {
1841                 /* Free the newly allocated filter as we were
1842                  * not able to create the filter in hardware.
1843                  */
1844                 filter->fw_l2_filter_id = UINT64_MAX;
1845                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1846                 return rc;
1847         } else {
1848                 /* Add this new filter to the list */
1849                 if (vlan_id == 0) {
1850                         filter->dflt = true;
1851                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1852                 } else {
1853                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1854                 }
1855         }
1856
1857         PMD_DRV_LOG(INFO,
1858                     "Added Vlan filter for %d\n", vlan_id);
1859         return rc;
1860 }
1861
1862 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1863                 uint16_t vlan_id, int on)
1864 {
1865         struct bnxt *bp = eth_dev->data->dev_private;
1866         int rc;
1867
1868         rc = is_bnxt_in_error(bp);
1869         if (rc)
1870                 return rc;
1871
1872         /* These operations apply to ALL existing MAC/VLAN filters */
1873         if (on)
1874                 return bnxt_add_vlan_filter(bp, vlan_id);
1875         else
1876                 return bnxt_del_vlan_filter(bp, vlan_id);
1877 }
1878
1879 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1880                                     struct bnxt_vnic_info *vnic)
1881 {
1882         struct bnxt_filter_info *filter;
1883         int rc;
1884
1885         filter = STAILQ_FIRST(&vnic->filter);
1886         while (filter) {
1887                 if (filter->dflt &&
1888                     !memcmp(filter->l2_addr, bp->mac_addr,
1889                             RTE_ETHER_ADDR_LEN)) {
1890                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1891                         if (rc)
1892                                 return rc;
1893                         filter->dflt = false;
1894                         STAILQ_REMOVE(&vnic->filter, filter,
1895                                       bnxt_filter_info, next);
1896                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1897                                            filter, next);
1898                         filter->fw_l2_filter_id = -1;
1899                         break;
1900                 }
1901                 filter = STAILQ_NEXT(filter, next);
1902         }
1903         return 0;
1904 }
1905
1906 static int
1907 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1908 {
1909         struct bnxt *bp = dev->data->dev_private;
1910         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1911         struct bnxt_vnic_info *vnic;
1912         unsigned int i;
1913         int rc;
1914
1915         rc = is_bnxt_in_error(bp);
1916         if (rc)
1917                 return rc;
1918
1919         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1920         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1921                 /* Remove any VLAN filters programmed */
1922                 for (i = 0; i < 4095; i++)
1923                         bnxt_del_vlan_filter(bp, i);
1924
1925                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1926                 if (rc)
1927                         return rc;
1928         } else {
1929                 /* Default filter will allow packets that match the
1930                  * dest mac. So, it has to be deleted, otherwise, we
1931                  * will endup receiving vlan packets for which the
1932                  * filter is not programmed, when hw-vlan-filter
1933                  * configuration is ON
1934                  */
1935                 bnxt_del_dflt_mac_filter(bp, vnic);
1936                 /* This filter will allow only untagged packets */
1937                 bnxt_add_vlan_filter(bp, 0);
1938         }
1939         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1940                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1941
1942         if (mask & ETH_VLAN_STRIP_MASK) {
1943                 /* Enable or disable VLAN stripping */
1944                 for (i = 0; i < bp->nr_vnics; i++) {
1945                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1946                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1947                                 vnic->vlan_strip = true;
1948                         else
1949                                 vnic->vlan_strip = false;
1950                         bnxt_hwrm_vnic_cfg(bp, vnic);
1951                 }
1952                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1953                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1954         }
1955
1956         if (mask & ETH_VLAN_EXTEND_MASK) {
1957                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1958                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1959                 else
1960                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1961         }
1962
1963         return 0;
1964 }
1965
1966 static int
1967 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1968                       uint16_t tpid)
1969 {
1970         struct bnxt *bp = dev->data->dev_private;
1971         int qinq = dev->data->dev_conf.rxmode.offloads &
1972                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1973
1974         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1975             vlan_type != ETH_VLAN_TYPE_OUTER) {
1976                 PMD_DRV_LOG(ERR,
1977                             "Unsupported vlan type.");
1978                 return -EINVAL;
1979         }
1980         if (!qinq) {
1981                 PMD_DRV_LOG(ERR,
1982                             "QinQ not enabled. Needs to be ON as we can "
1983                             "accelerate only outer vlan\n");
1984                 return -EINVAL;
1985         }
1986
1987         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1988                 switch (tpid) {
1989                 case RTE_ETHER_TYPE_QINQ:
1990                         bp->outer_tpid_bd =
1991                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1992                                 break;
1993                 case RTE_ETHER_TYPE_VLAN:
1994                         bp->outer_tpid_bd =
1995                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1996                                 break;
1997                 case 0x9100:
1998                         bp->outer_tpid_bd =
1999                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2000                                 break;
2001                 case 0x9200:
2002                         bp->outer_tpid_bd =
2003                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2004                                 break;
2005                 case 0x9300:
2006                         bp->outer_tpid_bd =
2007                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2008                                 break;
2009                 default:
2010                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2011                         return -EINVAL;
2012                 }
2013                 bp->outer_tpid_bd |= tpid;
2014                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2015         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2016                 PMD_DRV_LOG(ERR,
2017                             "Can accelerate only outer vlan in QinQ\n");
2018                 return -EINVAL;
2019         }
2020
2021         return 0;
2022 }
2023
2024 static int
2025 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2026                              struct rte_ether_addr *addr)
2027 {
2028         struct bnxt *bp = dev->data->dev_private;
2029         /* Default Filter is tied to VNIC 0 */
2030         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2031         struct bnxt_filter_info *filter;
2032         int rc;
2033
2034         rc = is_bnxt_in_error(bp);
2035         if (rc)
2036                 return rc;
2037
2038         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2039                 return -EPERM;
2040
2041         if (rte_is_zero_ether_addr(addr))
2042                 return -EINVAL;
2043
2044         STAILQ_FOREACH(filter, &vnic->filter, next) {
2045                 /* Default Filter is at Index 0 */
2046                 if (filter->mac_index != 0)
2047                         continue;
2048
2049                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2050                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2051                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2052                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2053                 filter->enables |=
2054                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2055                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2056
2057                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2058                 if (rc) {
2059                         memcpy(filter->l2_addr, bp->mac_addr,
2060                                RTE_ETHER_ADDR_LEN);
2061                         return rc;
2062                 }
2063
2064                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2065                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2066                 return 0;
2067         }
2068
2069         return 0;
2070 }
2071
2072 static int
2073 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2074                           struct rte_ether_addr *mc_addr_set,
2075                           uint32_t nb_mc_addr)
2076 {
2077         struct bnxt *bp = eth_dev->data->dev_private;
2078         char *mc_addr_list = (char *)mc_addr_set;
2079         struct bnxt_vnic_info *vnic;
2080         uint32_t off = 0, i = 0;
2081         int rc;
2082
2083         rc = is_bnxt_in_error(bp);
2084         if (rc)
2085                 return rc;
2086
2087         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2088
2089         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2090                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2091                 goto allmulti;
2092         }
2093
2094         /* TODO Check for Duplicate mcast addresses */
2095         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2096         for (i = 0; i < nb_mc_addr; i++) {
2097                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2098                         RTE_ETHER_ADDR_LEN);
2099                 off += RTE_ETHER_ADDR_LEN;
2100         }
2101
2102         vnic->mc_addr_cnt = i;
2103         if (vnic->mc_addr_cnt)
2104                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2105         else
2106                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2107
2108 allmulti:
2109         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2110 }
2111
2112 static int
2113 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2114 {
2115         struct bnxt *bp = dev->data->dev_private;
2116         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2117         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2118         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2119         int ret;
2120
2121         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2122                         fw_major, fw_minor, fw_updt);
2123
2124         ret += 1; /* add the size of '\0' */
2125         if (fw_size < (uint32_t)ret)
2126                 return ret;
2127         else
2128                 return 0;
2129 }
2130
2131 static void
2132 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2133         struct rte_eth_rxq_info *qinfo)
2134 {
2135         struct bnxt_rx_queue *rxq;
2136
2137         rxq = dev->data->rx_queues[queue_id];
2138
2139         qinfo->mp = rxq->mb_pool;
2140         qinfo->scattered_rx = dev->data->scattered_rx;
2141         qinfo->nb_desc = rxq->nb_rx_desc;
2142
2143         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2144         qinfo->conf.rx_drop_en = 0;
2145         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2146 }
2147
2148 static void
2149 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2150         struct rte_eth_txq_info *qinfo)
2151 {
2152         struct bnxt_tx_queue *txq;
2153
2154         txq = dev->data->tx_queues[queue_id];
2155
2156         qinfo->nb_desc = txq->nb_tx_desc;
2157
2158         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2159         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2160         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2161
2162         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2163         qinfo->conf.tx_rs_thresh = 0;
2164         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2165 }
2166
2167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2168 {
2169         struct bnxt *bp = eth_dev->data->dev_private;
2170         uint32_t new_pkt_size;
2171         uint32_t rc = 0;
2172         uint32_t i;
2173
2174         rc = is_bnxt_in_error(bp);
2175         if (rc)
2176                 return rc;
2177
2178         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2179                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2180
2181 #ifdef RTE_ARCH_X86
2182         /*
2183          * If vector-mode tx/rx is active, disallow any MTU change that would
2184          * require scattered receive support.
2185          */
2186         if (eth_dev->data->dev_started &&
2187             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2188              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2189             (new_pkt_size >
2190              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2191                 PMD_DRV_LOG(ERR,
2192                             "MTU change would require scattered rx support. ");
2193                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2194                 return -EINVAL;
2195         }
2196 #endif
2197
2198         if (new_mtu > RTE_ETHER_MTU) {
2199                 bp->flags |= BNXT_FLAG_JUMBO;
2200                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2201                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2202         } else {
2203                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2204                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2205                 bp->flags &= ~BNXT_FLAG_JUMBO;
2206         }
2207
2208         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2209
2210         for (i = 0; i < bp->nr_vnics; i++) {
2211                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2212                 uint16_t size = 0;
2213
2214                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2215                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2216                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2217                 if (rc)
2218                         break;
2219
2220                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2221                 size -= RTE_PKTMBUF_HEADROOM;
2222
2223                 if (size < new_mtu) {
2224                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2225                         if (rc)
2226                                 return rc;
2227                 }
2228         }
2229
2230         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2231
2232         return rc;
2233 }
2234
2235 static int
2236 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2237 {
2238         struct bnxt *bp = dev->data->dev_private;
2239         uint16_t vlan = bp->vlan;
2240         int rc;
2241
2242         rc = is_bnxt_in_error(bp);
2243         if (rc)
2244                 return rc;
2245
2246         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2247                 PMD_DRV_LOG(ERR,
2248                         "PVID cannot be modified for this function\n");
2249                 return -ENOTSUP;
2250         }
2251         bp->vlan = on ? pvid : 0;
2252
2253         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2254         if (rc)
2255                 bp->vlan = vlan;
2256         return rc;
2257 }
2258
2259 static int
2260 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2261 {
2262         struct bnxt *bp = dev->data->dev_private;
2263         int rc;
2264
2265         rc = is_bnxt_in_error(bp);
2266         if (rc)
2267                 return rc;
2268
2269         return bnxt_hwrm_port_led_cfg(bp, true);
2270 }
2271
2272 static int
2273 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2274 {
2275         struct bnxt *bp = dev->data->dev_private;
2276         int rc;
2277
2278         rc = is_bnxt_in_error(bp);
2279         if (rc)
2280                 return rc;
2281
2282         return bnxt_hwrm_port_led_cfg(bp, false);
2283 }
2284
2285 static uint32_t
2286 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2287 {
2288         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2289         uint32_t desc = 0, raw_cons = 0, cons;
2290         struct bnxt_cp_ring_info *cpr;
2291         struct bnxt_rx_queue *rxq;
2292         struct rx_pkt_cmpl *rxcmp;
2293         int rc;
2294
2295         rc = is_bnxt_in_error(bp);
2296         if (rc)
2297                 return rc;
2298
2299         rxq = dev->data->rx_queues[rx_queue_id];
2300         cpr = rxq->cp_ring;
2301         raw_cons = cpr->cp_raw_cons;
2302
2303         while (1) {
2304                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2305                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2306                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2307
2308                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2309                         break;
2310                 } else {
2311                         raw_cons++;
2312                         desc++;
2313                 }
2314         }
2315
2316         return desc;
2317 }
2318
2319 static int
2320 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2321 {
2322         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2323         struct bnxt_rx_ring_info *rxr;
2324         struct bnxt_cp_ring_info *cpr;
2325         struct bnxt_sw_rx_bd *rx_buf;
2326         struct rx_pkt_cmpl *rxcmp;
2327         uint32_t cons, cp_cons;
2328         int rc;
2329
2330         if (!rxq)
2331                 return -EINVAL;
2332
2333         rc = is_bnxt_in_error(rxq->bp);
2334         if (rc)
2335                 return rc;
2336
2337         cpr = rxq->cp_ring;
2338         rxr = rxq->rx_ring;
2339
2340         if (offset >= rxq->nb_rx_desc)
2341                 return -EINVAL;
2342
2343         cons = RING_CMP(cpr->cp_ring_struct, offset);
2344         cp_cons = cpr->cp_raw_cons;
2345         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2346
2347         if (cons > cp_cons) {
2348                 if (CMPL_VALID(rxcmp, cpr->valid))
2349                         return RTE_ETH_RX_DESC_DONE;
2350         } else {
2351                 if (CMPL_VALID(rxcmp, !cpr->valid))
2352                         return RTE_ETH_RX_DESC_DONE;
2353         }
2354         rx_buf = &rxr->rx_buf_ring[cons];
2355         if (rx_buf->mbuf == NULL)
2356                 return RTE_ETH_RX_DESC_UNAVAIL;
2357
2358
2359         return RTE_ETH_RX_DESC_AVAIL;
2360 }
2361
2362 static int
2363 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2364 {
2365         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2366         struct bnxt_tx_ring_info *txr;
2367         struct bnxt_cp_ring_info *cpr;
2368         struct bnxt_sw_tx_bd *tx_buf;
2369         struct tx_pkt_cmpl *txcmp;
2370         uint32_t cons, cp_cons;
2371         int rc;
2372
2373         if (!txq)
2374                 return -EINVAL;
2375
2376         rc = is_bnxt_in_error(txq->bp);
2377         if (rc)
2378                 return rc;
2379
2380         cpr = txq->cp_ring;
2381         txr = txq->tx_ring;
2382
2383         if (offset >= txq->nb_tx_desc)
2384                 return -EINVAL;
2385
2386         cons = RING_CMP(cpr->cp_ring_struct, offset);
2387         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2388         cp_cons = cpr->cp_raw_cons;
2389
2390         if (cons > cp_cons) {
2391                 if (CMPL_VALID(txcmp, cpr->valid))
2392                         return RTE_ETH_TX_DESC_UNAVAIL;
2393         } else {
2394                 if (CMPL_VALID(txcmp, !cpr->valid))
2395                         return RTE_ETH_TX_DESC_UNAVAIL;
2396         }
2397         tx_buf = &txr->tx_buf_ring[cons];
2398         if (tx_buf->mbuf == NULL)
2399                 return RTE_ETH_TX_DESC_DONE;
2400
2401         return RTE_ETH_TX_DESC_FULL;
2402 }
2403
2404 static struct bnxt_filter_info *
2405 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2406                                 struct rte_eth_ethertype_filter *efilter,
2407                                 struct bnxt_vnic_info *vnic0,
2408                                 struct bnxt_vnic_info *vnic,
2409                                 int *ret)
2410 {
2411         struct bnxt_filter_info *mfilter = NULL;
2412         int match = 0;
2413         *ret = 0;
2414
2415         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2416                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2417                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2418                         " ethertype filter.", efilter->ether_type);
2419                 *ret = -EINVAL;
2420                 goto exit;
2421         }
2422         if (efilter->queue >= bp->rx_nr_rings) {
2423                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2424                 *ret = -EINVAL;
2425                 goto exit;
2426         }
2427
2428         vnic0 = &bp->vnic_info[0];
2429         vnic = &bp->vnic_info[efilter->queue];
2430         if (vnic == NULL) {
2431                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2432                 *ret = -EINVAL;
2433                 goto exit;
2434         }
2435
2436         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2437                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2438                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2439                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2440                              mfilter->flags ==
2441                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2442                              mfilter->ethertype == efilter->ether_type)) {
2443                                 match = 1;
2444                                 break;
2445                         }
2446                 }
2447         } else {
2448                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2449                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2450                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2451                              mfilter->ethertype == efilter->ether_type &&
2452                              mfilter->flags ==
2453                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2454                                 match = 1;
2455                                 break;
2456                         }
2457         }
2458
2459         if (match)
2460                 *ret = -EEXIST;
2461
2462 exit:
2463         return mfilter;
2464 }
2465
2466 static int
2467 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2468                         enum rte_filter_op filter_op,
2469                         void *arg)
2470 {
2471         struct bnxt *bp = dev->data->dev_private;
2472         struct rte_eth_ethertype_filter *efilter =
2473                         (struct rte_eth_ethertype_filter *)arg;
2474         struct bnxt_filter_info *bfilter, *filter1;
2475         struct bnxt_vnic_info *vnic, *vnic0;
2476         int ret;
2477
2478         if (filter_op == RTE_ETH_FILTER_NOP)
2479                 return 0;
2480
2481         if (arg == NULL) {
2482                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2483                             filter_op);
2484                 return -EINVAL;
2485         }
2486
2487         vnic0 = &bp->vnic_info[0];
2488         vnic = &bp->vnic_info[efilter->queue];
2489
2490         switch (filter_op) {
2491         case RTE_ETH_FILTER_ADD:
2492                 bnxt_match_and_validate_ether_filter(bp, efilter,
2493                                                         vnic0, vnic, &ret);
2494                 if (ret < 0)
2495                         return ret;
2496
2497                 bfilter = bnxt_get_unused_filter(bp);
2498                 if (bfilter == NULL) {
2499                         PMD_DRV_LOG(ERR,
2500                                 "Not enough resources for a new filter.\n");
2501                         return -ENOMEM;
2502                 }
2503                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2504                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2505                        RTE_ETHER_ADDR_LEN);
2506                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2507                        RTE_ETHER_ADDR_LEN);
2508                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2509                 bfilter->ethertype = efilter->ether_type;
2510                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2511
2512                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2513                 if (filter1 == NULL) {
2514                         ret = -EINVAL;
2515                         goto cleanup;
2516                 }
2517                 bfilter->enables |=
2518                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2519                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2520
2521                 bfilter->dst_id = vnic->fw_vnic_id;
2522
2523                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2524                         bfilter->flags =
2525                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2526                 }
2527
2528                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2529                 if (ret)
2530                         goto cleanup;
2531                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2532                 break;
2533         case RTE_ETH_FILTER_DELETE:
2534                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2535                                                         vnic0, vnic, &ret);
2536                 if (ret == -EEXIST) {
2537                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2538
2539                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2540                                       next);
2541                         bnxt_free_filter(bp, filter1);
2542                 } else if (ret == 0) {
2543                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2544                 }
2545                 break;
2546         default:
2547                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2548                 ret = -EINVAL;
2549                 goto error;
2550         }
2551         return ret;
2552 cleanup:
2553         bnxt_free_filter(bp, bfilter);
2554 error:
2555         return ret;
2556 }
2557
2558 static inline int
2559 parse_ntuple_filter(struct bnxt *bp,
2560                     struct rte_eth_ntuple_filter *nfilter,
2561                     struct bnxt_filter_info *bfilter)
2562 {
2563         uint32_t en = 0;
2564
2565         if (nfilter->queue >= bp->rx_nr_rings) {
2566                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2567                 return -EINVAL;
2568         }
2569
2570         switch (nfilter->dst_port_mask) {
2571         case UINT16_MAX:
2572                 bfilter->dst_port_mask = -1;
2573                 bfilter->dst_port = nfilter->dst_port;
2574                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2575                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2576                 break;
2577         default:
2578                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2579                 return -EINVAL;
2580         }
2581
2582         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2583         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2584
2585         switch (nfilter->proto_mask) {
2586         case UINT8_MAX:
2587                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2588                         bfilter->ip_protocol = 17;
2589                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2590                         bfilter->ip_protocol = 6;
2591                 else
2592                         return -EINVAL;
2593                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2594                 break;
2595         default:
2596                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2597                 return -EINVAL;
2598         }
2599
2600         switch (nfilter->dst_ip_mask) {
2601         case UINT32_MAX:
2602                 bfilter->dst_ipaddr_mask[0] = -1;
2603                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2604                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2605                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2606                 break;
2607         default:
2608                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2609                 return -EINVAL;
2610         }
2611
2612         switch (nfilter->src_ip_mask) {
2613         case UINT32_MAX:
2614                 bfilter->src_ipaddr_mask[0] = -1;
2615                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2616                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2617                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2618                 break;
2619         default:
2620                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2621                 return -EINVAL;
2622         }
2623
2624         switch (nfilter->src_port_mask) {
2625         case UINT16_MAX:
2626                 bfilter->src_port_mask = -1;
2627                 bfilter->src_port = nfilter->src_port;
2628                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2629                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2630                 break;
2631         default:
2632                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2633                 return -EINVAL;
2634         }
2635
2636         //TODO Priority
2637         //nfilter->priority = (uint8_t)filter->priority;
2638
2639         bfilter->enables = en;
2640         return 0;
2641 }
2642
2643 static struct bnxt_filter_info*
2644 bnxt_match_ntuple_filter(struct bnxt *bp,
2645                          struct bnxt_filter_info *bfilter,
2646                          struct bnxt_vnic_info **mvnic)
2647 {
2648         struct bnxt_filter_info *mfilter = NULL;
2649         int i;
2650
2651         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2652                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2653                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2654                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2655                             bfilter->src_ipaddr_mask[0] ==
2656                             mfilter->src_ipaddr_mask[0] &&
2657                             bfilter->src_port == mfilter->src_port &&
2658                             bfilter->src_port_mask == mfilter->src_port_mask &&
2659                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2660                             bfilter->dst_ipaddr_mask[0] ==
2661                             mfilter->dst_ipaddr_mask[0] &&
2662                             bfilter->dst_port == mfilter->dst_port &&
2663                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2664                             bfilter->flags == mfilter->flags &&
2665                             bfilter->enables == mfilter->enables) {
2666                                 if (mvnic)
2667                                         *mvnic = vnic;
2668                                 return mfilter;
2669                         }
2670                 }
2671         }
2672         return NULL;
2673 }
2674
2675 static int
2676 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2677                        struct rte_eth_ntuple_filter *nfilter,
2678                        enum rte_filter_op filter_op)
2679 {
2680         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2681         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2682         int ret;
2683
2684         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2685                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2686                 return -EINVAL;
2687         }
2688
2689         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2690                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2691                 return -EINVAL;
2692         }
2693
2694         bfilter = bnxt_get_unused_filter(bp);
2695         if (bfilter == NULL) {
2696                 PMD_DRV_LOG(ERR,
2697                         "Not enough resources for a new filter.\n");
2698                 return -ENOMEM;
2699         }
2700         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2701         if (ret < 0)
2702                 goto free_filter;
2703
2704         vnic = &bp->vnic_info[nfilter->queue];
2705         vnic0 = &bp->vnic_info[0];
2706         filter1 = STAILQ_FIRST(&vnic0->filter);
2707         if (filter1 == NULL) {
2708                 ret = -EINVAL;
2709                 goto free_filter;
2710         }
2711
2712         bfilter->dst_id = vnic->fw_vnic_id;
2713         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2714         bfilter->enables |=
2715                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2716         bfilter->ethertype = 0x800;
2717         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2718
2719         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2720
2721         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2722             bfilter->dst_id == mfilter->dst_id) {
2723                 PMD_DRV_LOG(ERR, "filter exists.\n");
2724                 ret = -EEXIST;
2725                 goto free_filter;
2726         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2727                    bfilter->dst_id != mfilter->dst_id) {
2728                 mfilter->dst_id = vnic->fw_vnic_id;
2729                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2730                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2731                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2732                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2733                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2734                 goto free_filter;
2735         }
2736         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2737                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2738                 ret = -ENOENT;
2739                 goto free_filter;
2740         }
2741
2742         if (filter_op == RTE_ETH_FILTER_ADD) {
2743                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2744                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2745                 if (ret)
2746                         goto free_filter;
2747                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2748         } else {
2749                 if (mfilter == NULL) {
2750                         /* This should not happen. But for Coverity! */
2751                         ret = -ENOENT;
2752                         goto free_filter;
2753                 }
2754                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2755
2756                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2757                 bnxt_free_filter(bp, mfilter);
2758                 mfilter->fw_l2_filter_id = -1;
2759                 bnxt_free_filter(bp, bfilter);
2760                 bfilter->fw_l2_filter_id = -1;
2761         }
2762
2763         return 0;
2764 free_filter:
2765         bfilter->fw_l2_filter_id = -1;
2766         bnxt_free_filter(bp, bfilter);
2767         return ret;
2768 }
2769
2770 static int
2771 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2772                         enum rte_filter_op filter_op,
2773                         void *arg)
2774 {
2775         struct bnxt *bp = dev->data->dev_private;
2776         int ret;
2777
2778         if (filter_op == RTE_ETH_FILTER_NOP)
2779                 return 0;
2780
2781         if (arg == NULL) {
2782                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2783                             filter_op);
2784                 return -EINVAL;
2785         }
2786
2787         switch (filter_op) {
2788         case RTE_ETH_FILTER_ADD:
2789                 ret = bnxt_cfg_ntuple_filter(bp,
2790                         (struct rte_eth_ntuple_filter *)arg,
2791                         filter_op);
2792                 break;
2793         case RTE_ETH_FILTER_DELETE:
2794                 ret = bnxt_cfg_ntuple_filter(bp,
2795                         (struct rte_eth_ntuple_filter *)arg,
2796                         filter_op);
2797                 break;
2798         default:
2799                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2800                 ret = -EINVAL;
2801                 break;
2802         }
2803         return ret;
2804 }
2805
2806 static int
2807 bnxt_parse_fdir_filter(struct bnxt *bp,
2808                        struct rte_eth_fdir_filter *fdir,
2809                        struct bnxt_filter_info *filter)
2810 {
2811         enum rte_fdir_mode fdir_mode =
2812                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2813         struct bnxt_vnic_info *vnic0, *vnic;
2814         struct bnxt_filter_info *filter1;
2815         uint32_t en = 0;
2816         int i;
2817
2818         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2819                 return -EINVAL;
2820
2821         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2822         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2823
2824         switch (fdir->input.flow_type) {
2825         case RTE_ETH_FLOW_IPV4:
2826         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2827                 /* FALLTHROUGH */
2828                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2829                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2830                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2831                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2832                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2833                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2834                 filter->ip_addr_type =
2835                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2836                 filter->src_ipaddr_mask[0] = 0xffffffff;
2837                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2838                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2839                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2840                 filter->ethertype = 0x800;
2841                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2842                 break;
2843         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2844                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2845                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2846                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2847                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2848                 filter->dst_port_mask = 0xffff;
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2850                 filter->src_port_mask = 0xffff;
2851                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2852                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2853                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2854                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2855                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2856                 filter->ip_protocol = 6;
2857                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2858                 filter->ip_addr_type =
2859                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2860                 filter->src_ipaddr_mask[0] = 0xffffffff;
2861                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2862                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2863                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2864                 filter->ethertype = 0x800;
2865                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2866                 break;
2867         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2868                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2869                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2870                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2871                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2872                 filter->dst_port_mask = 0xffff;
2873                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2874                 filter->src_port_mask = 0xffff;
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2876                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2877                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2878                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2879                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2880                 filter->ip_protocol = 17;
2881                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2882                 filter->ip_addr_type =
2883                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2884                 filter->src_ipaddr_mask[0] = 0xffffffff;
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2886                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2887                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2888                 filter->ethertype = 0x800;
2889                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2890                 break;
2891         case RTE_ETH_FLOW_IPV6:
2892         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2893                 /* FALLTHROUGH */
2894                 filter->ip_addr_type =
2895                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2896                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2897                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2898                 rte_memcpy(filter->src_ipaddr,
2899                            fdir->input.flow.ipv6_flow.src_ip, 16);
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2901                 rte_memcpy(filter->dst_ipaddr,
2902                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2904                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2905                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2906                 memset(filter->src_ipaddr_mask, 0xff, 16);
2907                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2908                 filter->ethertype = 0x86dd;
2909                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2910                 break;
2911         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2912                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2913                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2914                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2916                 filter->dst_port_mask = 0xffff;
2917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2918                 filter->src_port_mask = 0xffff;
2919                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2920                 filter->ip_addr_type =
2921                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2922                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2923                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2924                 rte_memcpy(filter->src_ipaddr,
2925                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2926                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2927                 rte_memcpy(filter->dst_ipaddr,
2928                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2930                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2931                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2932                 memset(filter->src_ipaddr_mask, 0xff, 16);
2933                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2934                 filter->ethertype = 0x86dd;
2935                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2936                 break;
2937         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2938                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2939                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2940                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2941                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2942                 filter->dst_port_mask = 0xffff;
2943                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2944                 filter->src_port_mask = 0xffff;
2945                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2946                 filter->ip_addr_type =
2947                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2948                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2949                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2950                 rte_memcpy(filter->src_ipaddr,
2951                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2952                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2953                 rte_memcpy(filter->dst_ipaddr,
2954                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2955                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2956                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2957                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2958                 memset(filter->src_ipaddr_mask, 0xff, 16);
2959                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2960                 filter->ethertype = 0x86dd;
2961                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2962                 break;
2963         case RTE_ETH_FLOW_L2_PAYLOAD:
2964                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2965                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2966                 break;
2967         case RTE_ETH_FLOW_VXLAN:
2968                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2969                         return -EINVAL;
2970                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2971                 filter->tunnel_type =
2972                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2973                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2974                 break;
2975         case RTE_ETH_FLOW_NVGRE:
2976                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2977                         return -EINVAL;
2978                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2979                 filter->tunnel_type =
2980                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2981                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2982                 break;
2983         case RTE_ETH_FLOW_UNKNOWN:
2984         case RTE_ETH_FLOW_RAW:
2985         case RTE_ETH_FLOW_FRAG_IPV4:
2986         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2987         case RTE_ETH_FLOW_FRAG_IPV6:
2988         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2989         case RTE_ETH_FLOW_IPV6_EX:
2990         case RTE_ETH_FLOW_IPV6_TCP_EX:
2991         case RTE_ETH_FLOW_IPV6_UDP_EX:
2992         case RTE_ETH_FLOW_GENEVE:
2993                 /* FALLTHROUGH */
2994         default:
2995                 return -EINVAL;
2996         }
2997
2998         vnic0 = &bp->vnic_info[0];
2999         vnic = &bp->vnic_info[fdir->action.rx_queue];
3000         if (vnic == NULL) {
3001                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3002                 return -EINVAL;
3003         }
3004
3005         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3006                 rte_memcpy(filter->dst_macaddr,
3007                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3008                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3009         }
3010
3011         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3012                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3013                 filter1 = STAILQ_FIRST(&vnic0->filter);
3014                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3015         } else {
3016                 filter->dst_id = vnic->fw_vnic_id;
3017                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3018                         if (filter->dst_macaddr[i] == 0x00)
3019                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3020                         else
3021                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3022         }
3023
3024         if (filter1 == NULL)
3025                 return -EINVAL;
3026
3027         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3028         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3029
3030         filter->enables = en;
3031
3032         return 0;
3033 }
3034
3035 static struct bnxt_filter_info *
3036 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3037                 struct bnxt_vnic_info **mvnic)
3038 {
3039         struct bnxt_filter_info *mf = NULL;
3040         int i;
3041
3042         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3043                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3044
3045                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3046                         if (mf->filter_type == nf->filter_type &&
3047                             mf->flags == nf->flags &&
3048                             mf->src_port == nf->src_port &&
3049                             mf->src_port_mask == nf->src_port_mask &&
3050                             mf->dst_port == nf->dst_port &&
3051                             mf->dst_port_mask == nf->dst_port_mask &&
3052                             mf->ip_protocol == nf->ip_protocol &&
3053                             mf->ip_addr_type == nf->ip_addr_type &&
3054                             mf->ethertype == nf->ethertype &&
3055                             mf->vni == nf->vni &&
3056                             mf->tunnel_type == nf->tunnel_type &&
3057                             mf->l2_ovlan == nf->l2_ovlan &&
3058                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3059                             mf->l2_ivlan == nf->l2_ivlan &&
3060                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3061                             !memcmp(mf->l2_addr, nf->l2_addr,
3062                                     RTE_ETHER_ADDR_LEN) &&
3063                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3064                                     RTE_ETHER_ADDR_LEN) &&
3065                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3066                                     RTE_ETHER_ADDR_LEN) &&
3067                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3068                                     RTE_ETHER_ADDR_LEN) &&
3069                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3070                                     sizeof(nf->src_ipaddr)) &&
3071                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3072                                     sizeof(nf->src_ipaddr_mask)) &&
3073                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3074                                     sizeof(nf->dst_ipaddr)) &&
3075                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3076                                     sizeof(nf->dst_ipaddr_mask))) {
3077                                 if (mvnic)
3078                                         *mvnic = vnic;
3079                                 return mf;
3080                         }
3081                 }
3082         }
3083         return NULL;
3084 }
3085
3086 static int
3087 bnxt_fdir_filter(struct rte_eth_dev *dev,
3088                  enum rte_filter_op filter_op,
3089                  void *arg)
3090 {
3091         struct bnxt *bp = dev->data->dev_private;
3092         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3093         struct bnxt_filter_info *filter, *match;
3094         struct bnxt_vnic_info *vnic, *mvnic;
3095         int ret = 0, i;
3096
3097         if (filter_op == RTE_ETH_FILTER_NOP)
3098                 return 0;
3099
3100         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3101                 return -EINVAL;
3102
3103         switch (filter_op) {
3104         case RTE_ETH_FILTER_ADD:
3105         case RTE_ETH_FILTER_DELETE:
3106                 /* FALLTHROUGH */
3107                 filter = bnxt_get_unused_filter(bp);
3108                 if (filter == NULL) {
3109                         PMD_DRV_LOG(ERR,
3110                                 "Not enough resources for a new flow.\n");
3111                         return -ENOMEM;
3112                 }
3113
3114                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3115                 if (ret != 0)
3116                         goto free_filter;
3117                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3118
3119                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3120                         vnic = &bp->vnic_info[0];
3121                 else
3122                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3123
3124                 match = bnxt_match_fdir(bp, filter, &mvnic);
3125                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3126                         if (match->dst_id == vnic->fw_vnic_id) {
3127                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3128                                 ret = -EEXIST;
3129                                 goto free_filter;
3130                         } else {
3131                                 match->dst_id = vnic->fw_vnic_id;
3132                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3133                                                                   match->dst_id,
3134                                                                   match);
3135                                 STAILQ_REMOVE(&mvnic->filter, match,
3136                                               bnxt_filter_info, next);
3137                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3138                                 PMD_DRV_LOG(ERR,
3139                                         "Filter with matching pattern exist\n");
3140                                 PMD_DRV_LOG(ERR,
3141                                         "Updated it to new destination q\n");
3142                                 goto free_filter;
3143                         }
3144                 }
3145                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3146                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3147                         ret = -ENOENT;
3148                         goto free_filter;
3149                 }
3150
3151                 if (filter_op == RTE_ETH_FILTER_ADD) {
3152                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3153                                                           filter->dst_id,
3154                                                           filter);
3155                         if (ret)
3156                                 goto free_filter;
3157                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3158                 } else {
3159                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3160                         STAILQ_REMOVE(&vnic->filter, match,
3161                                       bnxt_filter_info, next);
3162                         bnxt_free_filter(bp, match);
3163                         filter->fw_l2_filter_id = -1;
3164                         bnxt_free_filter(bp, filter);
3165                 }
3166                 break;
3167         case RTE_ETH_FILTER_FLUSH:
3168                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3169                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3170
3171                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3172                                 if (filter->filter_type ==
3173                                     HWRM_CFA_NTUPLE_FILTER) {
3174                                         ret =
3175                                         bnxt_hwrm_clear_ntuple_filter(bp,
3176                                                                       filter);
3177                                         STAILQ_REMOVE(&vnic->filter, filter,
3178                                                       bnxt_filter_info, next);
3179                                 }
3180                         }
3181                 }
3182                 return ret;
3183         case RTE_ETH_FILTER_UPDATE:
3184         case RTE_ETH_FILTER_STATS:
3185         case RTE_ETH_FILTER_INFO:
3186                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3187                 break;
3188         default:
3189                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3190                 ret = -EINVAL;
3191                 break;
3192         }
3193         return ret;
3194
3195 free_filter:
3196         filter->fw_l2_filter_id = -1;
3197         bnxt_free_filter(bp, filter);
3198         return ret;
3199 }
3200
3201 static int
3202 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3203                     enum rte_filter_type filter_type,
3204                     enum rte_filter_op filter_op, void *arg)
3205 {
3206         int ret = 0;
3207
3208         ret = is_bnxt_in_error(dev->data->dev_private);
3209         if (ret)
3210                 return ret;
3211
3212         switch (filter_type) {
3213         case RTE_ETH_FILTER_TUNNEL:
3214                 PMD_DRV_LOG(ERR,
3215                         "filter type: %d: To be implemented\n", filter_type);
3216                 break;
3217         case RTE_ETH_FILTER_FDIR:
3218                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3219                 break;
3220         case RTE_ETH_FILTER_NTUPLE:
3221                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3222                 break;
3223         case RTE_ETH_FILTER_ETHERTYPE:
3224                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3225                 break;
3226         case RTE_ETH_FILTER_GENERIC:
3227                 if (filter_op != RTE_ETH_FILTER_GET)
3228                         return -EINVAL;
3229                 *(const void **)arg = &bnxt_flow_ops;
3230                 break;
3231         default:
3232                 PMD_DRV_LOG(ERR,
3233                         "Filter type (%d) not supported", filter_type);
3234                 ret = -EINVAL;
3235                 break;
3236         }
3237         return ret;
3238 }
3239
3240 static const uint32_t *
3241 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3242 {
3243         static const uint32_t ptypes[] = {
3244                 RTE_PTYPE_L2_ETHER_VLAN,
3245                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3246                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3247                 RTE_PTYPE_L4_ICMP,
3248                 RTE_PTYPE_L4_TCP,
3249                 RTE_PTYPE_L4_UDP,
3250                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3251                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3252                 RTE_PTYPE_INNER_L4_ICMP,
3253                 RTE_PTYPE_INNER_L4_TCP,
3254                 RTE_PTYPE_INNER_L4_UDP,
3255                 RTE_PTYPE_UNKNOWN
3256         };
3257
3258         if (!dev->rx_pkt_burst)
3259                 return NULL;
3260
3261         return ptypes;
3262 }
3263
3264 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3265                          int reg_win)
3266 {
3267         uint32_t reg_base = *reg_arr & 0xfffff000;
3268         uint32_t win_off;
3269         int i;
3270
3271         for (i = 0; i < count; i++) {
3272                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3273                         return -ERANGE;
3274         }
3275         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3276         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3277         return 0;
3278 }
3279
3280 static int bnxt_map_ptp_regs(struct bnxt *bp)
3281 {
3282         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3283         uint32_t *reg_arr;
3284         int rc, i;
3285
3286         reg_arr = ptp->rx_regs;
3287         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3288         if (rc)
3289                 return rc;
3290
3291         reg_arr = ptp->tx_regs;
3292         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3293         if (rc)
3294                 return rc;
3295
3296         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3297                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3298
3299         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3300                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3301
3302         return 0;
3303 }
3304
3305 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3306 {
3307         rte_write32(0, (uint8_t *)bp->bar0 +
3308                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3309         rte_write32(0, (uint8_t *)bp->bar0 +
3310                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3311 }
3312
3313 static uint64_t bnxt_cc_read(struct bnxt *bp)
3314 {
3315         uint64_t ns;
3316
3317         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3318                               BNXT_GRCPF_REG_SYNC_TIME));
3319         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3320                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3321         return ns;
3322 }
3323
3324 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3325 {
3326         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3327         uint32_t fifo;
3328
3329         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3330                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3331         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3332                 return -EAGAIN;
3333
3334         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3335                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3336         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3337                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3338         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3339                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3340
3341         return 0;
3342 }
3343
3344 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3345 {
3346         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3347         struct bnxt_pf_info *pf = &bp->pf;
3348         uint16_t port_id;
3349         uint32_t fifo;
3350
3351         if (!ptp)
3352                 return -ENODEV;
3353
3354         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3355                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3356         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3357                 return -EAGAIN;
3358
3359         port_id = pf->port_id;
3360         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3361                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3362
3363         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3364                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3365         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3366 /*              bnxt_clr_rx_ts(bp);       TBD  */
3367                 return -EBUSY;
3368         }
3369
3370         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3371                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3372         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3373                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3374
3375         return 0;
3376 }
3377
3378 static int
3379 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3380 {
3381         uint64_t ns;
3382         struct bnxt *bp = dev->data->dev_private;
3383         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3384
3385         if (!ptp)
3386                 return 0;
3387
3388         ns = rte_timespec_to_ns(ts);
3389         /* Set the timecounters to a new value. */
3390         ptp->tc.nsec = ns;
3391
3392         return 0;
3393 }
3394
3395 static int
3396 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3397 {
3398         struct bnxt *bp = dev->data->dev_private;
3399         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3400         uint64_t ns, systime_cycles = 0;
3401         int rc = 0;
3402
3403         if (!ptp)
3404                 return 0;
3405
3406         if (BNXT_CHIP_THOR(bp))
3407                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3408                                              &systime_cycles);
3409         else
3410                 systime_cycles = bnxt_cc_read(bp);
3411
3412         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3413         *ts = rte_ns_to_timespec(ns);
3414
3415         return rc;
3416 }
3417 static int
3418 bnxt_timesync_enable(struct rte_eth_dev *dev)
3419 {
3420         struct bnxt *bp = dev->data->dev_private;
3421         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3422         uint32_t shift = 0;
3423         int rc;
3424
3425         if (!ptp)
3426                 return 0;
3427
3428         ptp->rx_filter = 1;
3429         ptp->tx_tstamp_en = 1;
3430         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3431
3432         rc = bnxt_hwrm_ptp_cfg(bp);
3433         if (rc)
3434                 return rc;
3435
3436         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3437         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3438         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3439
3440         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3441         ptp->tc.cc_shift = shift;
3442         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3443
3444         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3445         ptp->rx_tstamp_tc.cc_shift = shift;
3446         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3447
3448         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3449         ptp->tx_tstamp_tc.cc_shift = shift;
3450         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3451
3452         if (!BNXT_CHIP_THOR(bp))
3453                 bnxt_map_ptp_regs(bp);
3454
3455         return 0;
3456 }
3457
3458 static int
3459 bnxt_timesync_disable(struct rte_eth_dev *dev)
3460 {
3461         struct bnxt *bp = dev->data->dev_private;
3462         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3463
3464         if (!ptp)
3465                 return 0;
3466
3467         ptp->rx_filter = 0;
3468         ptp->tx_tstamp_en = 0;
3469         ptp->rxctl = 0;
3470
3471         bnxt_hwrm_ptp_cfg(bp);
3472
3473         if (!BNXT_CHIP_THOR(bp))
3474                 bnxt_unmap_ptp_regs(bp);
3475
3476         return 0;
3477 }
3478
3479 static int
3480 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3481                                  struct timespec *timestamp,
3482                                  uint32_t flags __rte_unused)
3483 {
3484         struct bnxt *bp = dev->data->dev_private;
3485         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3486         uint64_t rx_tstamp_cycles = 0;
3487         uint64_t ns;
3488
3489         if (!ptp)
3490                 return 0;
3491
3492         if (BNXT_CHIP_THOR(bp))
3493                 rx_tstamp_cycles = ptp->rx_timestamp;
3494         else
3495                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3496
3497         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3498         *timestamp = rte_ns_to_timespec(ns);
3499         return  0;
3500 }
3501
3502 static int
3503 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3504                                  struct timespec *timestamp)
3505 {
3506         struct bnxt *bp = dev->data->dev_private;
3507         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3508         uint64_t tx_tstamp_cycles = 0;
3509         uint64_t ns;
3510         int rc = 0;
3511
3512         if (!ptp)
3513                 return 0;
3514
3515         if (BNXT_CHIP_THOR(bp))
3516                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3517                                              &tx_tstamp_cycles);
3518         else
3519                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3520
3521         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3522         *timestamp = rte_ns_to_timespec(ns);
3523
3524         return rc;
3525 }
3526
3527 static int
3528 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3529 {
3530         struct bnxt *bp = dev->data->dev_private;
3531         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3532
3533         if (!ptp)
3534                 return 0;
3535
3536         ptp->tc.nsec += delta;
3537
3538         return 0;
3539 }
3540
3541 static int
3542 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3543 {
3544         struct bnxt *bp = dev->data->dev_private;
3545         int rc;
3546         uint32_t dir_entries;
3547         uint32_t entry_length;
3548
3549         rc = is_bnxt_in_error(bp);
3550         if (rc)
3551                 return rc;
3552
3553         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3554                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3555                 bp->pdev->addr.devid, bp->pdev->addr.function);
3556
3557         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3558         if (rc != 0)
3559                 return rc;
3560
3561         return dir_entries * entry_length;
3562 }
3563
3564 static int
3565 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3566                 struct rte_dev_eeprom_info *in_eeprom)
3567 {
3568         struct bnxt *bp = dev->data->dev_private;
3569         uint32_t index;
3570         uint32_t offset;
3571         int rc;
3572
3573         rc = is_bnxt_in_error(bp);
3574         if (rc)
3575                 return rc;
3576
3577         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3578                 "len = %d\n", bp->pdev->addr.domain,
3579                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3580                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3581
3582         if (in_eeprom->offset == 0) /* special offset value to get directory */
3583                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3584                                                 in_eeprom->data);
3585
3586         index = in_eeprom->offset >> 24;
3587         offset = in_eeprom->offset & 0xffffff;
3588
3589         if (index != 0)
3590                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3591                                            in_eeprom->length, in_eeprom->data);
3592
3593         return 0;
3594 }
3595
3596 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3597 {
3598         switch (dir_type) {
3599         case BNX_DIR_TYPE_CHIMP_PATCH:
3600         case BNX_DIR_TYPE_BOOTCODE:
3601         case BNX_DIR_TYPE_BOOTCODE_2:
3602         case BNX_DIR_TYPE_APE_FW:
3603         case BNX_DIR_TYPE_APE_PATCH:
3604         case BNX_DIR_TYPE_KONG_FW:
3605         case BNX_DIR_TYPE_KONG_PATCH:
3606         case BNX_DIR_TYPE_BONO_FW:
3607         case BNX_DIR_TYPE_BONO_PATCH:
3608                 /* FALLTHROUGH */
3609                 return true;
3610         }
3611
3612         return false;
3613 }
3614
3615 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3616 {
3617         switch (dir_type) {
3618         case BNX_DIR_TYPE_AVS:
3619         case BNX_DIR_TYPE_EXP_ROM_MBA:
3620         case BNX_DIR_TYPE_PCIE:
3621         case BNX_DIR_TYPE_TSCF_UCODE:
3622         case BNX_DIR_TYPE_EXT_PHY:
3623         case BNX_DIR_TYPE_CCM:
3624         case BNX_DIR_TYPE_ISCSI_BOOT:
3625         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3626         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3627                 /* FALLTHROUGH */
3628                 return true;
3629         }
3630
3631         return false;
3632 }
3633
3634 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3635 {
3636         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3637                 bnxt_dir_type_is_other_exec_format(dir_type);
3638 }
3639
3640 static int
3641 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3642                 struct rte_dev_eeprom_info *in_eeprom)
3643 {
3644         struct bnxt *bp = dev->data->dev_private;
3645         uint8_t index, dir_op;
3646         uint16_t type, ext, ordinal, attr;
3647         int rc;
3648
3649         rc = is_bnxt_in_error(bp);
3650         if (rc)
3651                 return rc;
3652
3653         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3654                 "len = %d\n", bp->pdev->addr.domain,
3655                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3656                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3657
3658         if (!BNXT_PF(bp)) {
3659                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3660                 return -EINVAL;
3661         }
3662
3663         type = in_eeprom->magic >> 16;
3664
3665         if (type == 0xffff) { /* special value for directory operations */
3666                 index = in_eeprom->magic & 0xff;
3667                 dir_op = in_eeprom->magic >> 8;
3668                 if (index == 0)
3669                         return -EINVAL;
3670                 switch (dir_op) {
3671                 case 0x0e: /* erase */
3672                         if (in_eeprom->offset != ~in_eeprom->magic)
3673                                 return -EINVAL;
3674                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3675                 default:
3676                         return -EINVAL;
3677                 }
3678         }
3679
3680         /* Create or re-write an NVM item: */
3681         if (bnxt_dir_type_is_executable(type) == true)
3682                 return -EOPNOTSUPP;
3683         ext = in_eeprom->magic & 0xffff;
3684         ordinal = in_eeprom->offset >> 16;
3685         attr = in_eeprom->offset & 0xffff;
3686
3687         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3688                                      in_eeprom->data, in_eeprom->length);
3689 }
3690
3691 /*
3692  * Initialization
3693  */
3694
3695 static const struct eth_dev_ops bnxt_dev_ops = {
3696         .dev_infos_get = bnxt_dev_info_get_op,
3697         .dev_close = bnxt_dev_close_op,
3698         .dev_configure = bnxt_dev_configure_op,
3699         .dev_start = bnxt_dev_start_op,
3700         .dev_stop = bnxt_dev_stop_op,
3701         .dev_set_link_up = bnxt_dev_set_link_up_op,
3702         .dev_set_link_down = bnxt_dev_set_link_down_op,
3703         .stats_get = bnxt_stats_get_op,
3704         .stats_reset = bnxt_stats_reset_op,
3705         .rx_queue_setup = bnxt_rx_queue_setup_op,
3706         .rx_queue_release = bnxt_rx_queue_release_op,
3707         .tx_queue_setup = bnxt_tx_queue_setup_op,
3708         .tx_queue_release = bnxt_tx_queue_release_op,
3709         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3710         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3711         .reta_update = bnxt_reta_update_op,
3712         .reta_query = bnxt_reta_query_op,
3713         .rss_hash_update = bnxt_rss_hash_update_op,
3714         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3715         .link_update = bnxt_link_update_op,
3716         .promiscuous_enable = bnxt_promiscuous_enable_op,
3717         .promiscuous_disable = bnxt_promiscuous_disable_op,
3718         .allmulticast_enable = bnxt_allmulticast_enable_op,
3719         .allmulticast_disable = bnxt_allmulticast_disable_op,
3720         .mac_addr_add = bnxt_mac_addr_add_op,
3721         .mac_addr_remove = bnxt_mac_addr_remove_op,
3722         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3723         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3724         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3725         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3726         .vlan_filter_set = bnxt_vlan_filter_set_op,
3727         .vlan_offload_set = bnxt_vlan_offload_set_op,
3728         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3729         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3730         .mtu_set = bnxt_mtu_set_op,
3731         .mac_addr_set = bnxt_set_default_mac_addr_op,
3732         .xstats_get = bnxt_dev_xstats_get_op,
3733         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3734         .xstats_reset = bnxt_dev_xstats_reset_op,
3735         .fw_version_get = bnxt_fw_version_get,
3736         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3737         .rxq_info_get = bnxt_rxq_info_get_op,
3738         .txq_info_get = bnxt_txq_info_get_op,
3739         .dev_led_on = bnxt_dev_led_on_op,
3740         .dev_led_off = bnxt_dev_led_off_op,
3741         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3742         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3743         .rx_queue_count = bnxt_rx_queue_count_op,
3744         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3745         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3746         .rx_queue_start = bnxt_rx_queue_start,
3747         .rx_queue_stop = bnxt_rx_queue_stop,
3748         .tx_queue_start = bnxt_tx_queue_start,
3749         .tx_queue_stop = bnxt_tx_queue_stop,
3750         .filter_ctrl = bnxt_filter_ctrl_op,
3751         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3752         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3753         .get_eeprom           = bnxt_get_eeprom_op,
3754         .set_eeprom           = bnxt_set_eeprom_op,
3755         .timesync_enable      = bnxt_timesync_enable,
3756         .timesync_disable     = bnxt_timesync_disable,
3757         .timesync_read_time   = bnxt_timesync_read_time,
3758         .timesync_write_time   = bnxt_timesync_write_time,
3759         .timesync_adjust_time = bnxt_timesync_adjust_time,
3760         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3761         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3762 };
3763
3764 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3765 {
3766         uint32_t offset;
3767
3768         /* Only pre-map the reset GRC registers using window 3 */
3769         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3770                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3771
3772         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3773
3774         return offset;
3775 }
3776
3777 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3778 {
3779         struct bnxt_error_recovery_info *info = bp->recovery_info;
3780         uint32_t reg_base = 0xffffffff;
3781         int i;
3782
3783         /* Only pre-map the monitoring GRC registers using window 2 */
3784         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3785                 uint32_t reg = info->status_regs[i];
3786
3787                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3788                         continue;
3789
3790                 if (reg_base == 0xffffffff)
3791                         reg_base = reg & 0xfffff000;
3792                 if ((reg & 0xfffff000) != reg_base)
3793                         return -ERANGE;
3794
3795                 /* Use mask 0xffc as the Lower 2 bits indicates
3796                  * address space location
3797                  */
3798                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3799                                                 (reg & 0xffc);
3800         }
3801
3802         if (reg_base == 0xffffffff)
3803                 return 0;
3804
3805         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3806                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3807
3808         return 0;
3809 }
3810
3811 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3812 {
3813         struct bnxt_error_recovery_info *info = bp->recovery_info;
3814         uint32_t delay = info->delay_after_reset[index];
3815         uint32_t val = info->reset_reg_val[index];
3816         uint32_t reg = info->reset_reg[index];
3817         uint32_t type, offset;
3818
3819         type = BNXT_FW_STATUS_REG_TYPE(reg);
3820         offset = BNXT_FW_STATUS_REG_OFF(reg);
3821
3822         switch (type) {
3823         case BNXT_FW_STATUS_REG_TYPE_CFG:
3824                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3825                 break;
3826         case BNXT_FW_STATUS_REG_TYPE_GRC:
3827                 offset = bnxt_map_reset_regs(bp, offset);
3828                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3829                 break;
3830         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3831                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3832                 break;
3833         }
3834         /* wait on a specific interval of time until core reset is complete */
3835         if (delay)
3836                 rte_delay_ms(delay);
3837 }
3838
3839 static void bnxt_dev_cleanup(struct bnxt *bp)
3840 {
3841         bnxt_set_hwrm_link_config(bp, false);
3842         bp->link_info.link_up = 0;
3843         if (bp->dev_stopped == 0)
3844                 bnxt_dev_stop_op(bp->eth_dev);
3845
3846         bnxt_uninit_resources(bp, true);
3847 }
3848
3849 static int bnxt_restore_filters(struct bnxt *bp)
3850 {
3851         struct rte_eth_dev *dev = bp->eth_dev;
3852         int ret = 0;
3853
3854         if (dev->data->all_multicast)
3855                 ret = bnxt_allmulticast_enable_op(dev);
3856         if (dev->data->promiscuous)
3857                 ret = bnxt_promiscuous_enable_op(dev);
3858
3859         /* TODO restore other filters as well */
3860         return ret;
3861 }
3862
3863 static void bnxt_dev_recover(void *arg)
3864 {
3865         struct bnxt *bp = arg;
3866         int timeout = bp->fw_reset_max_msecs;
3867         int rc = 0;
3868
3869         /* Clear Error flag so that device re-init should happen */
3870         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3871
3872         do {
3873                 rc = bnxt_hwrm_ver_get(bp);
3874                 if (rc == 0)
3875                         break;
3876                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3877                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3878         } while (rc && timeout);
3879
3880         if (rc) {
3881                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3882                 goto err;
3883         }
3884
3885         rc = bnxt_init_resources(bp, true);
3886         if (rc) {
3887                 PMD_DRV_LOG(ERR,
3888                             "Failed to initialize resources after reset\n");
3889                 goto err;
3890         }
3891         /* clear reset flag as the device is initialized now */
3892         bp->flags &= ~BNXT_FLAG_FW_RESET;
3893
3894         rc = bnxt_dev_start_op(bp->eth_dev);
3895         if (rc) {
3896                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3897                 goto err;
3898         }
3899
3900         rc = bnxt_restore_filters(bp);
3901         if (rc)
3902                 goto err;
3903
3904         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3905         return;
3906 err:
3907         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3908         bnxt_uninit_resources(bp, false);
3909         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3910 }
3911
3912 void bnxt_dev_reset_and_resume(void *arg)
3913 {
3914         struct bnxt *bp = arg;
3915         int rc;
3916
3917         bnxt_dev_cleanup(bp);
3918
3919         bnxt_wait_for_device_shutdown(bp);
3920
3921         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3922                                bnxt_dev_recover, (void *)bp);
3923         if (rc)
3924                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3925 }
3926
3927 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3928 {
3929         struct bnxt_error_recovery_info *info = bp->recovery_info;
3930         uint32_t reg = info->status_regs[index];
3931         uint32_t type, offset, val = 0;
3932
3933         type = BNXT_FW_STATUS_REG_TYPE(reg);
3934         offset = BNXT_FW_STATUS_REG_OFF(reg);
3935
3936         switch (type) {
3937         case BNXT_FW_STATUS_REG_TYPE_CFG:
3938                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3939                 break;
3940         case BNXT_FW_STATUS_REG_TYPE_GRC:
3941                 offset = info->mapped_status_regs[index];
3942                 /* FALLTHROUGH */
3943         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3944                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3945                                        offset));
3946                 break;
3947         }
3948
3949         return val;
3950 }
3951
3952 static int bnxt_fw_reset_all(struct bnxt *bp)
3953 {
3954         struct bnxt_error_recovery_info *info = bp->recovery_info;
3955         uint32_t i;
3956         int rc = 0;
3957
3958         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3959                 /* Reset through master function driver */
3960                 for (i = 0; i < info->reg_array_cnt; i++)
3961                         bnxt_write_fw_reset_reg(bp, i);
3962                 /* Wait for time specified by FW after triggering reset */
3963                 rte_delay_ms(info->master_func_wait_period_after_reset);
3964         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3965                 /* Reset with the help of Kong processor */
3966                 rc = bnxt_hwrm_fw_reset(bp);
3967                 if (rc)
3968                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3969         }
3970
3971         return rc;
3972 }
3973
3974 static void bnxt_fw_reset_cb(void *arg)
3975 {
3976         struct bnxt *bp = arg;
3977         struct bnxt_error_recovery_info *info = bp->recovery_info;
3978         int rc = 0;
3979
3980         /* Only Master function can do FW reset */
3981         if (bnxt_is_master_func(bp) &&
3982             bnxt_is_recovery_enabled(bp)) {
3983                 rc = bnxt_fw_reset_all(bp);
3984                 if (rc) {
3985                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3986                         return;
3987                 }
3988         }
3989
3990         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3991          * EXCEPTION_FATAL_ASYNC event to all the functions
3992          * (including MASTER FUNC). After receiving this Async, all the active
3993          * drivers should treat this case as FW initiated recovery
3994          */
3995         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3996                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3997                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3998
3999                 /* To recover from error */
4000                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4001                                   (void *)bp);
4002         }
4003 }
4004
4005 /* Driver should poll FW heartbeat, reset_counter with the frequency
4006  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4007  * When the driver detects heartbeat stop or change in reset_counter,
4008  * it has to trigger a reset to recover from the error condition.
4009  * A “master PF” is the function who will have the privilege to
4010  * initiate the chimp reset. The master PF will be elected by the
4011  * firmware and will be notified through async message.
4012  */
4013 static void bnxt_check_fw_health(void *arg)
4014 {
4015         struct bnxt *bp = arg;
4016         struct bnxt_error_recovery_info *info = bp->recovery_info;
4017         uint32_t val = 0, wait_msec;
4018
4019         if (!info || !bnxt_is_recovery_enabled(bp) ||
4020             is_bnxt_in_error(bp))
4021                 return;
4022
4023         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4024         if (val == info->last_heart_beat)
4025                 goto reset;
4026
4027         info->last_heart_beat = val;
4028
4029         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4030         if (val != info->last_reset_counter)
4031                 goto reset;
4032
4033         info->last_reset_counter = val;
4034
4035         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4036                           bnxt_check_fw_health, (void *)bp);
4037
4038         return;
4039 reset:
4040         /* Stop DMA to/from device */
4041         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4042         bp->flags |= BNXT_FLAG_FW_RESET;
4043
4044         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4045
4046         if (bnxt_is_master_func(bp))
4047                 wait_msec = info->master_func_wait_period;
4048         else
4049                 wait_msec = info->normal_func_wait_period;
4050
4051         rte_eal_alarm_set(US_PER_MS * wait_msec,
4052                           bnxt_fw_reset_cb, (void *)bp);
4053 }
4054
4055 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4056 {
4057         uint32_t polling_freq;
4058
4059         if (!bnxt_is_recovery_enabled(bp))
4060                 return;
4061
4062         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4063                 return;
4064
4065         polling_freq = bp->recovery_info->driver_polling_freq;
4066
4067         rte_eal_alarm_set(US_PER_MS * polling_freq,
4068                           bnxt_check_fw_health, (void *)bp);
4069         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4070 }
4071
4072 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4073 {
4074         if (!bnxt_is_recovery_enabled(bp))
4075                 return;
4076
4077         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4078         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4079 }
4080
4081 static bool bnxt_vf_pciid(uint16_t id)
4082 {
4083         if (id == BROADCOM_DEV_ID_57304_VF ||
4084             id == BROADCOM_DEV_ID_57406_VF ||
4085             id == BROADCOM_DEV_ID_5731X_VF ||
4086             id == BROADCOM_DEV_ID_5741X_VF ||
4087             id == BROADCOM_DEV_ID_57414_VF ||
4088             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4089             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4090             id == BROADCOM_DEV_ID_58802_VF ||
4091             id == BROADCOM_DEV_ID_57500_VF1 ||
4092             id == BROADCOM_DEV_ID_57500_VF2)
4093                 return true;
4094         return false;
4095 }
4096
4097 bool bnxt_stratus_device(struct bnxt *bp)
4098 {
4099         uint16_t id = bp->pdev->id.device_id;
4100
4101         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4102             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4103             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4104                 return true;
4105         return false;
4106 }
4107
4108 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4109 {
4110         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4111         struct bnxt *bp = eth_dev->data->dev_private;
4112
4113         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4114         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4115         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4116         if (!bp->bar0 || !bp->doorbell_base) {
4117                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4118                 return -ENODEV;
4119         }
4120
4121         bp->eth_dev = eth_dev;
4122         bp->pdev = pci_dev;
4123
4124         return 0;
4125 }
4126
4127 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4128                                   struct bnxt_ctx_pg_info *ctx_pg,
4129                                   uint32_t mem_size,
4130                                   const char *suffix,
4131                                   uint16_t idx)
4132 {
4133         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4134         const struct rte_memzone *mz = NULL;
4135         char mz_name[RTE_MEMZONE_NAMESIZE];
4136         rte_iova_t mz_phys_addr;
4137         uint64_t valid_bits = 0;
4138         uint32_t sz;
4139         int i;
4140
4141         if (!mem_size)
4142                 return 0;
4143
4144         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4145                          BNXT_PAGE_SIZE;
4146         rmem->page_size = BNXT_PAGE_SIZE;
4147         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4148         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4149         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4150
4151         valid_bits = PTU_PTE_VALID;
4152
4153         if (rmem->nr_pages > 1) {
4154                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4155                          "bnxt_ctx_pg_tbl%s_%x_%d",
4156                          suffix, idx, bp->eth_dev->data->port_id);
4157                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4158                 mz = rte_memzone_lookup(mz_name);
4159                 if (!mz) {
4160                         mz = rte_memzone_reserve_aligned(mz_name,
4161                                                 rmem->nr_pages * 8,
4162                                                 SOCKET_ID_ANY,
4163                                                 RTE_MEMZONE_2MB |
4164                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4165                                                 RTE_MEMZONE_IOVA_CONTIG,
4166                                                 BNXT_PAGE_SIZE);
4167                         if (mz == NULL)
4168                                 return -ENOMEM;
4169                 }
4170
4171                 memset(mz->addr, 0, mz->len);
4172                 mz_phys_addr = mz->iova;
4173                 if ((unsigned long)mz->addr == mz_phys_addr) {
4174                         PMD_DRV_LOG(DEBUG,
4175                                     "physical address same as virtual\n");
4176                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4177                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4178                         if (mz_phys_addr == RTE_BAD_IOVA) {
4179                                 PMD_DRV_LOG(ERR,
4180                                         "unable to map addr to phys memory\n");
4181                                 return -ENOMEM;
4182                         }
4183                 }
4184                 rte_mem_lock_page(((char *)mz->addr));
4185
4186                 rmem->pg_tbl = mz->addr;
4187                 rmem->pg_tbl_map = mz_phys_addr;
4188                 rmem->pg_tbl_mz = mz;
4189         }
4190
4191         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4192                  suffix, idx, bp->eth_dev->data->port_id);
4193         mz = rte_memzone_lookup(mz_name);
4194         if (!mz) {
4195                 mz = rte_memzone_reserve_aligned(mz_name,
4196                                                  mem_size,
4197                                                  SOCKET_ID_ANY,
4198                                                  RTE_MEMZONE_1GB |
4199                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4200                                                  RTE_MEMZONE_IOVA_CONTIG,
4201                                                  BNXT_PAGE_SIZE);
4202                 if (mz == NULL)
4203                         return -ENOMEM;
4204         }
4205
4206         memset(mz->addr, 0, mz->len);
4207         mz_phys_addr = mz->iova;
4208         if ((unsigned long)mz->addr == mz_phys_addr) {
4209                 PMD_DRV_LOG(DEBUG,
4210                             "Memzone physical address same as virtual.\n");
4211                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4212                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4213                         rte_mem_lock_page(((char *)mz->addr) + sz);
4214                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4215                 if (mz_phys_addr == RTE_BAD_IOVA) {
4216                         PMD_DRV_LOG(ERR,
4217                                     "unable to map addr to phys memory\n");
4218                         return -ENOMEM;
4219                 }
4220         }
4221
4222         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4223                 rte_mem_lock_page(((char *)mz->addr) + sz);
4224                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4225                 rmem->dma_arr[i] = mz_phys_addr + sz;
4226
4227                 if (rmem->nr_pages > 1) {
4228                         if (i == rmem->nr_pages - 2 &&
4229                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4230                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4231                         else if (i == rmem->nr_pages - 1 &&
4232                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4233                                 valid_bits |= PTU_PTE_LAST;
4234
4235                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4236                                                            valid_bits);
4237                 }
4238         }
4239
4240         rmem->mz = mz;
4241         if (rmem->vmem_size)
4242                 rmem->vmem = (void **)mz->addr;
4243         rmem->dma_arr[0] = mz_phys_addr;
4244         return 0;
4245 }
4246
4247 static void bnxt_free_ctx_mem(struct bnxt *bp)
4248 {
4249         int i;
4250
4251         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4252                 return;
4253
4254         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4255         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4256         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4257         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4258         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4259         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4260         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4261         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4262         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4263         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4264         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4265
4266         for (i = 0; i < BNXT_MAX_Q; i++) {
4267                 if (bp->ctx->tqm_mem[i])
4268                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4269         }
4270
4271         rte_free(bp->ctx);
4272         bp->ctx = NULL;
4273 }
4274
4275 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4276
4277 #define min_t(type, x, y) ({                    \
4278         type __min1 = (x);                      \
4279         type __min2 = (y);                      \
4280         __min1 < __min2 ? __min1 : __min2; })
4281
4282 #define max_t(type, x, y) ({                    \
4283         type __max1 = (x);                      \
4284         type __max2 = (y);                      \
4285         __max1 > __max2 ? __max1 : __max2; })
4286
4287 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4288
4289 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4290 {
4291         struct bnxt_ctx_pg_info *ctx_pg;
4292         struct bnxt_ctx_mem_info *ctx;
4293         uint32_t mem_size, ena, entries;
4294         int i, rc;
4295
4296         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4297         if (rc) {
4298                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4299                 return rc;
4300         }
4301         ctx = bp->ctx;
4302         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4303                 return 0;
4304
4305         ctx_pg = &ctx->qp_mem;
4306         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4307         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4308         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4309         if (rc)
4310                 return rc;
4311
4312         ctx_pg = &ctx->srq_mem;
4313         ctx_pg->entries = ctx->srq_max_l2_entries;
4314         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4315         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4316         if (rc)
4317                 return rc;
4318
4319         ctx_pg = &ctx->cq_mem;
4320         ctx_pg->entries = ctx->cq_max_l2_entries;
4321         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4322         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4323         if (rc)
4324                 return rc;
4325
4326         ctx_pg = &ctx->vnic_mem;
4327         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4328                 ctx->vnic_max_ring_table_entries;
4329         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4330         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4331         if (rc)
4332                 return rc;
4333
4334         ctx_pg = &ctx->stat_mem;
4335         ctx_pg->entries = ctx->stat_max_entries;
4336         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4337         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4338         if (rc)
4339                 return rc;
4340
4341         entries = ctx->qp_max_l2_entries +
4342                   ctx->vnic_max_vnic_entries +
4343                   ctx->tqm_min_entries_per_ring;
4344         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4345         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4346                           ctx->tqm_max_entries_per_ring);
4347         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4348                 ctx_pg = ctx->tqm_mem[i];
4349                 /* use min tqm entries for now. */
4350                 ctx_pg->entries = entries;
4351                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4352                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4353                 if (rc)
4354                         return rc;
4355                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4356         }
4357
4358         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4359         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4360         if (rc)
4361                 PMD_DRV_LOG(ERR,
4362                             "Failed to configure context mem: rc = %d\n", rc);
4363         else
4364                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4365
4366         return rc;
4367 }
4368
4369 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4370 {
4371         struct rte_pci_device *pci_dev = bp->pdev;
4372         char mz_name[RTE_MEMZONE_NAMESIZE];
4373         const struct rte_memzone *mz = NULL;
4374         uint32_t total_alloc_len;
4375         rte_iova_t mz_phys_addr;
4376
4377         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4378                 return 0;
4379
4380         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4381                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4382                  pci_dev->addr.bus, pci_dev->addr.devid,
4383                  pci_dev->addr.function, "rx_port_stats");
4384         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4385         mz = rte_memzone_lookup(mz_name);
4386         total_alloc_len =
4387                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4388                                        sizeof(struct rx_port_stats_ext) + 512);
4389         if (!mz) {
4390                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4391                                          SOCKET_ID_ANY,
4392                                          RTE_MEMZONE_2MB |
4393                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4394                                          RTE_MEMZONE_IOVA_CONTIG);
4395                 if (mz == NULL)
4396                         return -ENOMEM;
4397         }
4398         memset(mz->addr, 0, mz->len);
4399         mz_phys_addr = mz->iova;
4400         if ((unsigned long)mz->addr == mz_phys_addr) {
4401                 PMD_DRV_LOG(DEBUG,
4402                             "Memzone physical address same as virtual.\n");
4403                 PMD_DRV_LOG(DEBUG,
4404                             "Using rte_mem_virt2iova()\n");
4405                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4406                 if (mz_phys_addr == RTE_BAD_IOVA) {
4407                         PMD_DRV_LOG(ERR,
4408                                     "Can't map address to physical memory\n");
4409                         return -ENOMEM;
4410                 }
4411         }
4412
4413         bp->rx_mem_zone = (const void *)mz;
4414         bp->hw_rx_port_stats = mz->addr;
4415         bp->hw_rx_port_stats_map = mz_phys_addr;
4416
4417         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4418                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4419                  pci_dev->addr.bus, pci_dev->addr.devid,
4420                  pci_dev->addr.function, "tx_port_stats");
4421         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4422         mz = rte_memzone_lookup(mz_name);
4423         total_alloc_len =
4424                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4425                                        sizeof(struct tx_port_stats_ext) + 512);
4426         if (!mz) {
4427                 mz = rte_memzone_reserve(mz_name,
4428                                          total_alloc_len,
4429                                          SOCKET_ID_ANY,
4430                                          RTE_MEMZONE_2MB |
4431                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4432                                          RTE_MEMZONE_IOVA_CONTIG);
4433                 if (mz == NULL)
4434                         return -ENOMEM;
4435         }
4436         memset(mz->addr, 0, mz->len);
4437         mz_phys_addr = mz->iova;
4438         if ((unsigned long)mz->addr == mz_phys_addr) {
4439                 PMD_DRV_LOG(DEBUG,
4440                             "Memzone physical address same as virtual\n");
4441                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4442                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4443                 if (mz_phys_addr == RTE_BAD_IOVA) {
4444                         PMD_DRV_LOG(ERR,
4445                                     "Can't map address to physical memory\n");
4446                         return -ENOMEM;
4447                 }
4448         }
4449
4450         bp->tx_mem_zone = (const void *)mz;
4451         bp->hw_tx_port_stats = mz->addr;
4452         bp->hw_tx_port_stats_map = mz_phys_addr;
4453         bp->flags |= BNXT_FLAG_PORT_STATS;
4454
4455         /* Display extended statistics if FW supports it */
4456         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4457             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4458             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4459                 return 0;
4460
4461         bp->hw_rx_port_stats_ext = (void *)
4462                 ((uint8_t *)bp->hw_rx_port_stats +
4463                  sizeof(struct rx_port_stats));
4464         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4465                 sizeof(struct rx_port_stats);
4466         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4467
4468         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4469             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4470                 bp->hw_tx_port_stats_ext = (void *)
4471                         ((uint8_t *)bp->hw_tx_port_stats +
4472                          sizeof(struct tx_port_stats));
4473                 bp->hw_tx_port_stats_ext_map =
4474                         bp->hw_tx_port_stats_map +
4475                         sizeof(struct tx_port_stats);
4476                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4477         }
4478
4479         return 0;
4480 }
4481
4482 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4483 {
4484         struct bnxt *bp = eth_dev->data->dev_private;
4485         int rc = 0;
4486
4487         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4488                                                RTE_ETHER_ADDR_LEN *
4489                                                bp->max_l2_ctx,
4490                                                0);
4491         if (eth_dev->data->mac_addrs == NULL) {
4492                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4493                 return -ENOMEM;
4494         }
4495
4496         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4497                 if (BNXT_PF(bp))
4498                         return -EINVAL;
4499
4500                 /* Generate a random MAC address, if none was assigned by PF */
4501                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4502                 bnxt_eth_hw_addr_random(bp->mac_addr);
4503                 PMD_DRV_LOG(INFO,
4504                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4505                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4506                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4507
4508                 rc = bnxt_hwrm_set_mac(bp);
4509                 if (!rc)
4510                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4511                                RTE_ETHER_ADDR_LEN);
4512                 return rc;
4513         }
4514
4515         /* Copy the permanent MAC from the FUNC_QCAPS response */
4516         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4517         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4518
4519         return rc;
4520 }
4521
4522 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4523 {
4524         int rc = 0;
4525
4526         /* MAC is already configured in FW */
4527         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4528                 return 0;
4529
4530         /* Restore the old MAC configured */
4531         rc = bnxt_hwrm_set_mac(bp);
4532         if (rc)
4533                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4534
4535         return rc;
4536 }
4537
4538 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4539 {
4540         if (!BNXT_PF(bp))
4541                 return;
4542
4543 #define ALLOW_FUNC(x)   \
4544         { \
4545                 uint32_t arg = (x); \
4546                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4547                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4548         }
4549
4550         /* Forward all requests if firmware is new enough */
4551         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4552              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4553             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4554                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4555         } else {
4556                 PMD_DRV_LOG(WARNING,
4557                             "Firmware too old for VF mailbox functionality\n");
4558                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4559         }
4560
4561         /*
4562          * The following are used for driver cleanup. If we disallow these,
4563          * VF drivers can't clean up cleanly.
4564          */
4565         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4566         ALLOW_FUNC(HWRM_VNIC_FREE);
4567         ALLOW_FUNC(HWRM_RING_FREE);
4568         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4569         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4570         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4571         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4572         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4573         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4574 }
4575
4576 static int bnxt_init_fw(struct bnxt *bp)
4577 {
4578         uint16_t mtu;
4579         int rc = 0;
4580
4581         rc = bnxt_hwrm_ver_get(bp);
4582         if (rc)
4583                 return rc;
4584
4585         rc = bnxt_hwrm_func_reset(bp);
4586         if (rc)
4587                 return -EIO;
4588
4589         rc = bnxt_hwrm_vnic_qcaps(bp);
4590         if (rc)
4591                 return rc;
4592
4593         rc = bnxt_hwrm_queue_qportcfg(bp);
4594         if (rc)
4595                 return rc;
4596
4597         /* Get the MAX capabilities for this function.
4598          * This function also allocates context memory for TQM rings and
4599          * informs the firmware about this allocated backing store memory.
4600          */
4601         rc = bnxt_hwrm_func_qcaps(bp);
4602         if (rc)
4603                 return rc;
4604
4605         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4606         if (rc)
4607                 return rc;
4608
4609         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4610         if (rc)
4611                 return rc;
4612
4613         /* Get the adapter error recovery support info */
4614         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4615         if (rc)
4616                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4617
4618         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4619             mtu != bp->eth_dev->data->mtu)
4620                 bp->eth_dev->data->mtu = mtu;
4621
4622         bnxt_hwrm_port_led_qcaps(bp);
4623
4624         return 0;
4625 }
4626
4627 static int
4628 bnxt_init_locks(struct bnxt *bp)
4629 {
4630         int err;
4631
4632         err = pthread_mutex_init(&bp->flow_lock, NULL);
4633         if (err)
4634                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4635         return err;
4636 }
4637
4638 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4639 {
4640         int rc;
4641
4642         rc = bnxt_init_fw(bp);
4643         if (rc)
4644                 return rc;
4645
4646         if (!reconfig_dev) {
4647                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4648                 if (rc)
4649                         return rc;
4650         } else {
4651                 rc = bnxt_restore_dflt_mac(bp);
4652                 if (rc)
4653                         return rc;
4654         }
4655
4656         bnxt_config_vf_req_fwd(bp);
4657
4658         rc = bnxt_hwrm_func_driver_register(bp);
4659         if (rc) {
4660                 PMD_DRV_LOG(ERR, "Failed to register driver");
4661                 return -EBUSY;
4662         }
4663
4664         if (BNXT_PF(bp)) {
4665                 if (bp->pdev->max_vfs) {
4666                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4667                         if (rc) {
4668                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4669                                 return rc;
4670                         }
4671                 } else {
4672                         rc = bnxt_hwrm_allocate_pf_only(bp);
4673                         if (rc) {
4674                                 PMD_DRV_LOG(ERR,
4675                                             "Failed to allocate PF resources");
4676                                 return rc;
4677                         }
4678                 }
4679         }
4680
4681         rc = bnxt_alloc_mem(bp, reconfig_dev);
4682         if (rc)
4683                 return rc;
4684
4685         rc = bnxt_setup_int(bp);
4686         if (rc)
4687                 return rc;
4688
4689         bnxt_init_nic(bp);
4690
4691         rc = bnxt_request_int(bp);
4692         if (rc)
4693                 return rc;
4694
4695         rc = bnxt_init_locks(bp);
4696         if (rc)
4697                 return rc;
4698
4699         return 0;
4700 }
4701
4702 static int
4703 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4704 {
4705         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4706         static int version_printed;
4707         struct bnxt *bp;
4708         int rc;
4709
4710         if (version_printed++ == 0)
4711                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4712
4713         eth_dev->dev_ops = &bnxt_dev_ops;
4714         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4715         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4716
4717         /*
4718          * For secondary processes, we don't initialise any further
4719          * as primary has already done this work.
4720          */
4721         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4722                 return 0;
4723
4724         rte_eth_copy_pci_info(eth_dev, pci_dev);
4725
4726         bp = eth_dev->data->dev_private;
4727
4728         bp->dev_stopped = 1;
4729
4730         if (bnxt_vf_pciid(pci_dev->id.device_id))
4731                 bp->flags |= BNXT_FLAG_VF;
4732
4733         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4734             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4735             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4736             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4737             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4738                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4739
4740         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4741             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4742             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4743             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4744                 bp->flags |= BNXT_FLAG_STINGRAY;
4745
4746         rc = bnxt_init_board(eth_dev);
4747         if (rc) {
4748                 PMD_DRV_LOG(ERR,
4749                             "Failed to initialize board rc: %x\n", rc);
4750                 return rc;
4751         }
4752
4753         rc = bnxt_alloc_hwrm_resources(bp);
4754         if (rc) {
4755                 PMD_DRV_LOG(ERR,
4756                             "Failed to allocate hwrm resource rc: %x\n", rc);
4757                 goto error_free;
4758         }
4759         rc = bnxt_init_resources(bp, false);
4760         if (rc)
4761                 goto error_free;
4762
4763         rc = bnxt_alloc_stats_mem(bp);
4764         if (rc)
4765                 goto error_free;
4766
4767         PMD_DRV_LOG(INFO,
4768                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4769                     pci_dev->mem_resource[0].phys_addr,
4770                     pci_dev->mem_resource[0].addr);
4771
4772         return 0;
4773
4774 error_free:
4775         bnxt_dev_uninit(eth_dev);
4776         return rc;
4777 }
4778
4779 static void
4780 bnxt_uninit_locks(struct bnxt *bp)
4781 {
4782         pthread_mutex_destroy(&bp->flow_lock);
4783 }
4784
4785 static int
4786 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4787 {
4788         int rc;
4789
4790         bnxt_free_int(bp);
4791         bnxt_free_mem(bp, reconfig_dev);
4792         bnxt_hwrm_func_buf_unrgtr(bp);
4793         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4794         bp->flags &= ~BNXT_FLAG_REGISTERED;
4795         bnxt_free_ctx_mem(bp);
4796         if (!reconfig_dev) {
4797                 bnxt_free_hwrm_resources(bp);
4798
4799                 if (bp->recovery_info != NULL) {
4800                         rte_free(bp->recovery_info);
4801                         bp->recovery_info = NULL;
4802                 }
4803         }
4804
4805         rte_free(bp->ptp_cfg);
4806         bp->ptp_cfg = NULL;
4807         return rc;
4808 }
4809
4810 static int
4811 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4812 {
4813         struct bnxt *bp = eth_dev->data->dev_private;
4814         int rc;
4815
4816         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4817                 return -EPERM;
4818
4819         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4820
4821         rc = bnxt_uninit_resources(bp, false);
4822
4823         if (bp->grp_info != NULL) {
4824                 rte_free(bp->grp_info);
4825                 bp->grp_info = NULL;
4826         }
4827
4828         if (bp->tx_mem_zone) {
4829                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4830                 bp->tx_mem_zone = NULL;
4831         }
4832
4833         if (bp->rx_mem_zone) {
4834                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4835                 bp->rx_mem_zone = NULL;
4836         }
4837
4838         if (bp->dev_stopped == 0)
4839                 bnxt_dev_close_op(eth_dev);
4840         if (bp->pf.vf_info)
4841                 rte_free(bp->pf.vf_info);
4842         eth_dev->dev_ops = NULL;
4843         eth_dev->rx_pkt_burst = NULL;
4844         eth_dev->tx_pkt_burst = NULL;
4845
4846         bnxt_uninit_locks(bp);
4847
4848         return rc;
4849 }
4850
4851 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4852         struct rte_pci_device *pci_dev)
4853 {
4854         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4855                 bnxt_dev_init);
4856 }
4857
4858 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4859 {
4860         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4861                 return rte_eth_dev_pci_generic_remove(pci_dev,
4862                                 bnxt_dev_uninit);
4863         else
4864                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4865 }
4866
4867 static struct rte_pci_driver bnxt_rte_pmd = {
4868         .id_table = bnxt_pci_id_map,
4869         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4870         .probe = bnxt_pci_probe,
4871         .remove = bnxt_pci_remove,
4872 };
4873
4874 static bool
4875 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4876 {
4877         if (strcmp(dev->device->driver->name, drv->driver.name))
4878                 return false;
4879
4880         return true;
4881 }
4882
4883 bool is_bnxt_supported(struct rte_eth_dev *dev)
4884 {
4885         return is_device_supported(dev, &bnxt_rte_pmd);
4886 }
4887
4888 RTE_INIT(bnxt_init_log)
4889 {
4890         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4891         if (bnxt_logtype_driver >= 0)
4892                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4893 }
4894
4895 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4896 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4897 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");