drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_58802 0xd802
  74 #define BROADCOM_DEV_ID_58804 0xd804
  75 #define BROADCOM_DEV_ID_58808 0x16f0
  76
  77 static const struct rte_pci_id bnxt_pci_id_map[] = {
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  79                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 119         { .vendor_id = 0, /* sentinel */ },
 120 };
 121
 122 #define BNXT_ETH_RSS_SUPPORT (  \
 123         ETH_RSS_IPV4 |          \
 124         ETH_RSS_NONFRAG_IPV4_TCP |      \
 125         ETH_RSS_NONFRAG_IPV4_UDP |      \
 126         ETH_RSS_IPV6 |          \
 127         ETH_RSS_NONFRAG_IPV6_TCP |      \
 128         ETH_RSS_NONFRAG_IPV6_UDP)
 129
 130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 131                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 132                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 133                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 134                                      DEV_TX_OFFLOAD_TCP_TSO | \
 135                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 136                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 137                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 138                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 139                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 141
 142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 143                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 144                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 146                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 149                                      DEV_RX_OFFLOAD_CRC_STRIP | \
 150                                      DEV_RX_OFFLOAD_TCP_LRO)
 151
 152 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 153 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 154 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static void bnxt_free_mem(struct bnxt *bp)
 163 {
 164         bnxt_free_filter_mem(bp);
 165         bnxt_free_vnic_attributes(bp);
 166         bnxt_free_vnic_mem(bp);
 167
 168         bnxt_free_stats(bp);
 169         bnxt_free_tx_rings(bp);
 170         bnxt_free_rx_rings(bp);
 171         bnxt_free_def_cp_ring(bp);
 172 }
 173
 174 static int bnxt_alloc_mem(struct bnxt *bp)
 175 {
 176         int rc;
 177
 178         /* Default completion ring */
 179         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 180         if (rc)
 181                 goto alloc_mem_err;
 182
 183         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 184                               bp->def_cp_ring, "def_cp");
 185         if (rc)
 186                 goto alloc_mem_err;
 187
 188         rc = bnxt_alloc_vnic_mem(bp);
 189         if (rc)
 190                 goto alloc_mem_err;
 191
 192         rc = bnxt_alloc_vnic_attributes(bp);
 193         if (rc)
 194                 goto alloc_mem_err;
 195
 196         rc = bnxt_alloc_filter_mem(bp);
 197         if (rc)
 198                 goto alloc_mem_err;
 199
 200         return 0;
 201
 202 alloc_mem_err:
 203         bnxt_free_mem(bp);
 204         return rc;
 205 }
 206
 207 static int bnxt_init_chip(struct bnxt *bp)
 208 {
 209         unsigned int i;
 210         struct rte_eth_link new;
 211         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 212         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 213         uint32_t intr_vector = 0;
 214         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 215         uint32_t vec = BNXT_MISC_VEC_ID;
 216         int rc;
 217
 218         /* disable uio/vfio intr/eventfd mapping */
 219         rte_intr_disable(intr_handle);
 220
 221         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 222                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 223                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 224                 bp->flags |= BNXT_FLAG_JUMBO;
 225         } else {
 226                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 227                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 228                 bp->flags &= ~BNXT_FLAG_JUMBO;
 229         }
 230
 231         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 232         if (rc) {
 233                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 234                 goto err_out;
 235         }
 236
 237         rc = bnxt_alloc_hwrm_rings(bp);
 238         if (rc) {
 239                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 240                 goto err_out;
 241         }
 242
 243         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 244         if (rc) {
 245                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 246                 goto err_out;
 247         }
 248
 249         rc = bnxt_mq_rx_configure(bp);
 250         if (rc) {
 251                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 252                 goto err_out;
 253         }
 254
 255         /* VNIC configuration */
 256         for (i = 0; i < bp->nr_vnics; i++) {
 257                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 258
 259                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 260                 if (rc) {
 261                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 262                                 i, rc);
 263                         goto err_out;
 264                 }
 265
 266                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 267                 if (rc) {
 268                         PMD_DRV_LOG(ERR,
 269                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 270                                 i, rc);
 271                         goto err_out;
 272                 }
 273
 274                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 275                 if (rc) {
 276                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 277                                 i, rc);
 278                         goto err_out;
 279                 }
 280
 281                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 282                 if (rc) {
 283                         PMD_DRV_LOG(ERR,
 284                                 "HWRM vnic %d filter failure rc: %x\n",
 285                                 i, rc);
 286                         goto err_out;
 287                 }
 288
 289                 rc = bnxt_vnic_rss_configure(bp, vnic);
 290                 if (rc) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 293                         goto err_out;
 294                 }
 295
 296                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 297
 298                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 299                     DEV_RX_OFFLOAD_TCP_LRO)
 300                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 301                 else
 302                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 303         }
 304         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 305         if (rc) {
 306                 PMD_DRV_LOG(ERR,
 307                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         /* check and configure queue intr-vector mapping */
 312         if ((rte_intr_cap_multiple(intr_handle) ||
 313              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 314             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 315                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 316                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 317                 if (intr_vector > bp->rx_cp_nr_rings) {
 318                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 319                                         bp->rx_cp_nr_rings);
 320                         return -ENOTSUP;
 321                 }
 322                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 323                         return -1;
 324         }
 325
 326         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 327                 intr_handle->intr_vec =
 328                         rte_zmalloc("intr_vec",
 329                                     bp->eth_dev->data->nb_rx_queues *
 330                                     sizeof(int), 0);
 331                 if (intr_handle->intr_vec == NULL) {
 332                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 333                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 334                         return -ENOMEM;
 335                 }
 336                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 337                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 338                          intr_handle->intr_vec, intr_handle->nb_efd,
 339                         intr_handle->max_intr);
 340         }
 341
 342         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 343              queue_id++) {
 344                 intr_handle->intr_vec[queue_id] = vec;
 345                 if (vec < base + intr_handle->nb_efd - 1)
 346                         vec++;
 347         }
 348
 349         /* enable uio/vfio intr/eventfd mapping */
 350         rte_intr_enable(intr_handle);
 351
 352         rc = bnxt_get_hwrm_link_config(bp, &new);
 353         if (rc) {
 354                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 355                 goto err_out;
 356         }
 357
 358         if (!bp->link_info.link_up) {
 359                 rc = bnxt_set_hwrm_link_config(bp, true);
 360                 if (rc) {
 361                         PMD_DRV_LOG(ERR,
 362                                 "HWRM link config failure rc: %x\n", rc);
 363                         goto err_out;
 364                 }
 365         }
 366         bnxt_print_link_info(bp->eth_dev);
 367
 368         return 0;
 369
 370 err_out:
 371         bnxt_free_all_hwrm_resources(bp);
 372
 373         /* Some of the error status returned by FW may not be from errno.h */
 374         if (rc > 0)
 375                 rc = -EIO;
 376
 377         return rc;
 378 }
 379
 380 static int bnxt_shutdown_nic(struct bnxt *bp)
 381 {
 382         bnxt_free_all_hwrm_resources(bp);
 383         bnxt_free_all_filters(bp);
 384         bnxt_free_all_vnics(bp);
 385         return 0;
 386 }
 387
 388 static int bnxt_init_nic(struct bnxt *bp)
 389 {
 390         int rc;
 391
 392         rc = bnxt_init_ring_grps(bp);
 393         if (rc)
 394                 return rc;
 395
 396         bnxt_init_vnics(bp);
 397         bnxt_init_filters(bp);
 398
 399         return 0;
 400 }
 401
 402 /*
 403  * Device configuration and status function
 404  */
 405
 406 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 407                                   struct rte_eth_dev_info *dev_info)
 408 {
 409         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 410         uint16_t max_vnics, i, j, vpool, vrxq;
 411         unsigned int max_rx_rings;
 412
 413         /* MAC Specifics */
 414         dev_info->max_mac_addrs = bp->max_l2_ctx;
 415         dev_info->max_hash_mac_addrs = 0;
 416
 417         /* PF/VF specifics */
 418         if (BNXT_PF(bp))
 419                 dev_info->max_vfs = bp->pdev->max_vfs;
 420         max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
 421                                                 RTE_MIN(bp->max_rsscos_ctx,
 422                                                 bp->max_stat_ctx)));
 423         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 424         dev_info->max_rx_queues = max_rx_rings;
 425         dev_info->max_tx_queues = max_rx_rings;
 426         dev_info->reta_size = bp->max_rsscos_ctx;
 427         dev_info->hash_key_size = 40;
 428         max_vnics = bp->max_vnics;
 429
 430         /* Fast path specifics */
 431         dev_info->min_rx_bufsize = 1;
 432         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 433                                   + VLAN_TAG_SIZE;
 434
 435         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 436         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 437                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 438         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 439         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 440
 441         /* *INDENT-OFF* */
 442         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 443                 .rx_thresh = {
 444                         .pthresh = 8,
 445                         .hthresh = 8,
 446                         .wthresh = 0,
 447                 },
 448                 .rx_free_thresh = 32,
 449                 /* If no descriptors available, pkts are dropped by default */
 450                 .rx_drop_en = 1,
 451         };
 452
 453         dev_info->default_txconf = (struct rte_eth_txconf) {
 454                 .tx_thresh = {
 455                         .pthresh = 32,
 456                         .hthresh = 0,
 457                         .wthresh = 0,
 458                 },
 459                 .tx_free_thresh = 32,
 460                 .tx_rs_thresh = 32,
 461         };
 462         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 463
 464         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 465
 466         /* *INDENT-ON* */
 467
 468         /*
 469          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 470          *       need further investigation.
 471          */
 472
 473         /* VMDq resources */
 474         vpool = 64; /* ETH_64_POOLS */
 475         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 476         for (i = 0; i < 4; vpool >>= 1, i++) {
 477                 if (max_vnics > vpool) {
 478                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 479                                 if (dev_info->max_rx_queues > vrxq) {
 480                                         if (vpool > vrxq)
 481                                                 vpool = vrxq;
 482                                         goto found;
 483                                 }
 484                         }
 485                         /* Not enough resources to support VMDq */
 486                         break;
 487                 }
 488         }
 489         /* Not enough resources to support VMDq */
 490         vpool = 0;
 491         vrxq = 0;
 492 found:
 493         dev_info->max_vmdq_pools = vpool;
 494         dev_info->vmdq_queue_num = vrxq;
 495
 496         dev_info->vmdq_pool_base = 0;
 497         dev_info->vmdq_queue_base = 0;
 498 }
 499
 500 /* Configure the device based on the configuration provided */
 501 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 502 {
 503         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 504         uint64_t tx_offloads = eth_dev->data->dev_conf.txmode.offloads;
 505         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 506
 507         if (tx_offloads != (tx_offloads & BNXT_DEV_TX_OFFLOAD_SUPPORT)) {
 508                 PMD_DRV_LOG
 509                         (ERR,
 510                          "Tx offloads requested 0x%" PRIx64 " supported 0x%x\n",
 511                          tx_offloads, BNXT_DEV_TX_OFFLOAD_SUPPORT);
 512                 return -ENOTSUP;
 513         }
 514
 515         if (rx_offloads != (rx_offloads & BNXT_DEV_RX_OFFLOAD_SUPPORT)) {
 516                 PMD_DRV_LOG
 517                         (ERR,
 518                          "Rx offloads requested 0x%" PRIx64 " supported 0x%x\n",
 519                             rx_offloads, BNXT_DEV_RX_OFFLOAD_SUPPORT);
 520                 return -ENOTSUP;
 521         }
 522
 523         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 524         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 525
 526         /* Inherit new configurations */
 527         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 528             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 529             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
 530             bp->max_cp_rings ||
 531             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 532             bp->max_stat_ctx ||
 533             (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
 534                 PMD_DRV_LOG(ERR,
 535                         "Insufficient resources to support requested config\n");
 536                 PMD_DRV_LOG(ERR,
 537                         "Num Queues Requested: Tx %d, Rx %d\n",
 538                         eth_dev->data->nb_tx_queues,
 539                         eth_dev->data->nb_rx_queues);
 540                 PMD_DRV_LOG(ERR,
 541                         "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
 542                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 543                         bp->max_stat_ctx, bp->max_ring_grps);
 544                 return -ENOSPC;
 545         }
 546
 547         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 548         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 549         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 550         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 551
 552         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 553                 eth_dev->data->mtu =
 554                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 555                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 556                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 557         }
 558         return 0;
 559 }
 560
 561 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 562 {
 563         struct rte_eth_link *link = &eth_dev->data->dev_link;
 564
 565         if (link->link_status)
 566                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 567                         eth_dev->data->port_id,
 568                         (uint32_t)link->link_speed,
 569                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 570                         ("full-duplex") : ("half-duplex\n"));
 571         else
 572                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 573                         eth_dev->data->port_id);
 574 }
 575
 576 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 577 {
 578         bnxt_print_link_info(eth_dev);
 579         return 0;
 580 }
 581
 582 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 583 {
 584         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 585         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 586         int vlan_mask = 0;
 587         int rc;
 588
 589         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 590                 PMD_DRV_LOG(ERR,
 591                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 592                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 593         }
 594         bp->dev_stopped = 0;
 595
 596         rc = bnxt_init_chip(bp);
 597         if (rc)
 598                 goto error;
 599
 600         bnxt_link_update_op(eth_dev, 1);
 601
 602         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 603                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 604         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 605                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 606         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 607         if (rc)
 608                 goto error;
 609
 610         bp->flags |= BNXT_FLAG_INIT_DONE;
 611         return 0;
 612
 613 error:
 614         bnxt_shutdown_nic(bp);
 615         bnxt_free_tx_mbufs(bp);
 616         bnxt_free_rx_mbufs(bp);
 617         return rc;
 618 }
 619
 620 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 621 {
 622         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 623         int rc = 0;
 624
 625         if (!bp->link_info.link_up)
 626                 rc = bnxt_set_hwrm_link_config(bp, true);
 627         if (!rc)
 628                 eth_dev->data->dev_link.link_status = 1;
 629
 630         bnxt_print_link_info(eth_dev);
 631         return 0;
 632 }
 633
 634 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 635 {
 636         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 637
 638         eth_dev->data->dev_link.link_status = 0;
 639         bnxt_set_hwrm_link_config(bp, false);
 640         bp->link_info.link_up = 0;
 641
 642         return 0;
 643 }
 644
 645 /* Unload the driver, release resources */
 646 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 647 {
 648         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 649
 650         if (bp->eth_dev->data->dev_started) {
 651                 /* TBD: STOP HW queues DMA */
 652                 eth_dev->data->dev_link.link_status = 0;
 653         }
 654         bnxt_set_hwrm_link_config(bp, false);
 655         bnxt_hwrm_port_clr_stats(bp);
 656         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 657         bnxt_shutdown_nic(bp);
 658         bp->dev_stopped = 1;
 659 }
 660
 661 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 662 {
 663         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 664
 665         if (bp->dev_stopped == 0)
 666                 bnxt_dev_stop_op(eth_dev);
 667
 668         bnxt_free_tx_mbufs(bp);
 669         bnxt_free_rx_mbufs(bp);
 670         bnxt_free_mem(bp);
 671         if (eth_dev->data->mac_addrs != NULL) {
 672                 rte_free(eth_dev->data->mac_addrs);
 673                 eth_dev->data->mac_addrs = NULL;
 674         }
 675         if (bp->grp_info != NULL) {
 676                 rte_free(bp->grp_info);
 677                 bp->grp_info = NULL;
 678         }
 679 }
 680
 681 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 682                                     uint32_t index)
 683 {
 684         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 685         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 686         struct bnxt_vnic_info *vnic;
 687         struct bnxt_filter_info *filter, *temp_filter;
 688         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 689         uint32_t i;
 690
 691         /*
 692          * Loop through all VNICs from the specified filter flow pools to
 693          * remove the corresponding MAC addr filter
 694          */
 695         for (i = 0; i < pool; i++) {
 696                 if (!(pool_mask & (1ULL << i)))
 697                         continue;
 698
 699                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 700                         filter = STAILQ_FIRST(&vnic->filter);
 701                         while (filter) {
 702                                 temp_filter = STAILQ_NEXT(filter, next);
 703                                 if (filter->mac_index == index) {
 704                                         STAILQ_REMOVE(&vnic->filter, filter,
 705                                                       bnxt_filter_info, next);
 706                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 707                                         filter->mac_index = INVALID_MAC_INDEX;
 708                                         memset(&filter->l2_addr, 0,
 709                                                ETHER_ADDR_LEN);
 710                                         STAILQ_INSERT_TAIL(
 711                                                         &bp->free_filter_list,
 712                                                         filter, next);
 713                                 }
 714                                 filter = temp_filter;
 715                         }
 716                 }
 717         }
 718 }
 719
 720 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 721                                 struct ether_addr *mac_addr,
 722                                 uint32_t index, uint32_t pool)
 723 {
 724         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 725         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 726         struct bnxt_filter_info *filter;
 727
 728         if (BNXT_VF(bp)) {
 729                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 730                 return -ENOTSUP;
 731         }
 732
 733         if (!vnic) {
 734                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 735                 return -EINVAL;
 736         }
 737         /* Attach requested MAC address to the new l2_filter */
 738         STAILQ_FOREACH(filter, &vnic->filter, next) {
 739                 if (filter->mac_index == index) {
 740                         PMD_DRV_LOG(ERR,
 741                                 "MAC addr already existed for pool %d\n", pool);
 742                         return 0;
 743                 }
 744         }
 745         filter = bnxt_alloc_filter(bp);
 746         if (!filter) {
 747                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 748                 return -ENODEV;
 749         }
 750         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 751         filter->mac_index = index;
 752         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 753         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 754 }
 755
 756 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 757 {
 758         int rc = 0;
 759         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 760         struct rte_eth_link new;
 761         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 762
 763         memset(&new, 0, sizeof(new));
 764         do {
 765                 /* Retrieve link info from hardware */
 766                 rc = bnxt_get_hwrm_link_config(bp, &new);
 767                 if (rc) {
 768                         new.link_speed = ETH_LINK_SPEED_100M;
 769                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 770                         PMD_DRV_LOG(ERR,
 771                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 772                         goto out;
 773                 }
 774                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 775
 776                 if (!wait_to_complete)
 777                         break;
 778         } while (!new.link_status && cnt--);
 779
 780 out:
 781         /* Timed out or success */
 782         if (new.link_status != eth_dev->data->dev_link.link_status ||
 783         new.link_speed != eth_dev->data->dev_link.link_speed) {
 784                 memcpy(&eth_dev->data->dev_link, &new,
 785                         sizeof(struct rte_eth_link));
 786
 787                 _rte_eth_dev_callback_process(eth_dev,
 788                                               RTE_ETH_EVENT_INTR_LSC,
 789                                               NULL);
 790
 791                 bnxt_print_link_info(eth_dev);
 792         }
 793
 794         return rc;
 795 }
 796
 797 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 798 {
 799         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 800         struct bnxt_vnic_info *vnic;
 801
 802         if (bp->vnic_info == NULL)
 803                 return;
 804
 805         vnic = &bp->vnic_info[0];
 806
 807         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 808         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 809 }
 810
 811 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 812 {
 813         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 814         struct bnxt_vnic_info *vnic;
 815
 816         if (bp->vnic_info == NULL)
 817                 return;
 818
 819         vnic = &bp->vnic_info[0];
 820
 821         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 822         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 823 }
 824
 825 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 826 {
 827         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 828         struct bnxt_vnic_info *vnic;
 829
 830         if (bp->vnic_info == NULL)
 831                 return;
 832
 833         vnic = &bp->vnic_info[0];
 834
 835         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 836         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 837 }
 838
 839 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 840 {
 841         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 842         struct bnxt_vnic_info *vnic;
 843
 844         if (bp->vnic_info == NULL)
 845                 return;
 846
 847         vnic = &bp->vnic_info[0];
 848
 849         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 850         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 851 }
 852
 853 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 854                             struct rte_eth_rss_reta_entry64 *reta_conf,
 855                             uint16_t reta_size)
 856 {
 857         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 858         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 859         struct bnxt_vnic_info *vnic;
 860         int i;
 861
 862         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 863                 return -EINVAL;
 864
 865         if (reta_size != HW_HASH_INDEX_SIZE) {
 866                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 867                         "(%d) must equal the size supported by the hardware "
 868                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 869                 return -EINVAL;
 870         }
 871         /* Update the RSS VNIC(s) */
 872         for (i = 0; i < MAX_FF_POOLS; i++) {
 873                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 874                         memcpy(vnic->rss_table, reta_conf, reta_size);
 875
 876                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 877                 }
 878         }
 879         return 0;
 880 }
 881
 882 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 883                               struct rte_eth_rss_reta_entry64 *reta_conf,
 884                               uint16_t reta_size)
 885 {
 886         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 887         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 888         struct rte_intr_handle *intr_handle
 889                 = &bp->pdev->intr_handle;
 890
 891         /* Retrieve from the default VNIC */
 892         if (!vnic)
 893                 return -EINVAL;
 894         if (!vnic->rss_table)
 895                 return -EINVAL;
 896
 897         if (reta_size != HW_HASH_INDEX_SIZE) {
 898                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 899                         "(%d) must equal the size supported by the hardware "
 900                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 901                 return -EINVAL;
 902         }
 903         /* EW - need to revisit here copying from uint64_t to uint16_t */
 904         memcpy(reta_conf, vnic->rss_table, reta_size);
 905
 906         if (rte_intr_allow_others(intr_handle)) {
 907                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 908                         bnxt_dev_lsc_intr_setup(eth_dev);
 909         }
 910
 911         return 0;
 912 }
 913
 914 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 915                                    struct rte_eth_rss_conf *rss_conf)
 916 {
 917         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 918         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 919         struct bnxt_vnic_info *vnic;
 920         uint16_t hash_type = 0;
 921         int i;
 922
 923         /*
 924          * If RSS enablement were different than dev_configure,
 925          * then return -EINVAL
 926          */
 927         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 928                 if (!rss_conf->rss_hf)
 929                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 930         } else {
 931                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 932                         return -EINVAL;
 933         }
 934
 935         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 936         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 937
 938         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 939                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 940         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 941                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 942         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 943                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 944         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 945                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 946         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 947                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 948         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 949                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 950
 951         /* Update the RSS VNIC(s) */
 952         for (i = 0; i < MAX_FF_POOLS; i++) {
 953                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 954                         vnic->hash_type = hash_type;
 955
 956                         /*
 957                          * Use the supplied key if the key length is
 958                          * acceptable and the rss_key is not NULL
 959                          */
 960                         if (rss_conf->rss_key &&
 961                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 962                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 963                                        rss_conf->rss_key_len);
 964
 965                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 966                 }
 967         }
 968         return 0;
 969 }
 970
 971 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 972                                      struct rte_eth_rss_conf *rss_conf)
 973 {
 974         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 975         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 976         int len;
 977         uint32_t hash_types;
 978
 979         /* RSS configuration is the same for all VNICs */
 980         if (vnic && vnic->rss_hash_key) {
 981                 if (rss_conf->rss_key) {
 982                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 983                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 984                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 985                 }
 986
 987                 hash_types = vnic->hash_type;
 988                 rss_conf->rss_hf = 0;
 989                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 990                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 991                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 992                 }
 993                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 994                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 995                         hash_types &=
 996                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 997                 }
 998                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 999                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1000                         hash_types &=
1001                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1002                 }
1003                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1004                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1005                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1006                 }
1007                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1008                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1009                         hash_types &=
1010                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1011                 }
1012                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1013                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1014                         hash_types &=
1015                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1016                 }
1017                 if (hash_types) {
1018                         PMD_DRV_LOG(ERR,
1019                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1020                                 vnic->hash_type);
1021                         return -ENOTSUP;
1022                 }
1023         } else {
1024                 rss_conf->rss_hf = 0;
1025         }
1026         return 0;
1027 }
1028
1029 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1030                                struct rte_eth_fc_conf *fc_conf)
1031 {
1032         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1033         struct rte_eth_link link_info;
1034         int rc;
1035
1036         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1037         if (rc)
1038                 return rc;
1039
1040         memset(fc_conf, 0, sizeof(*fc_conf));
1041         if (bp->link_info.auto_pause)
1042                 fc_conf->autoneg = 1;
1043         switch (bp->link_info.pause) {
1044         case 0:
1045                 fc_conf->mode = RTE_FC_NONE;
1046                 break;
1047         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1048                 fc_conf->mode = RTE_FC_TX_PAUSE;
1049                 break;
1050         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1051                 fc_conf->mode = RTE_FC_RX_PAUSE;
1052                 break;
1053         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1054                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1055                 fc_conf->mode = RTE_FC_FULL;
1056                 break;
1057         }
1058         return 0;
1059 }
1060
1061 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1062                                struct rte_eth_fc_conf *fc_conf)
1063 {
1064         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1065
1066         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1067                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1068                 return -ENOTSUP;
1069         }
1070
1071         switch (fc_conf->mode) {
1072         case RTE_FC_NONE:
1073                 bp->link_info.auto_pause = 0;
1074                 bp->link_info.force_pause = 0;
1075                 break;
1076         case RTE_FC_RX_PAUSE:
1077                 if (fc_conf->autoneg) {
1078                         bp->link_info.auto_pause =
1079                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1080                         bp->link_info.force_pause = 0;
1081                 } else {
1082                         bp->link_info.auto_pause = 0;
1083                         bp->link_info.force_pause =
1084                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1085                 }
1086                 break;
1087         case RTE_FC_TX_PAUSE:
1088                 if (fc_conf->autoneg) {
1089                         bp->link_info.auto_pause =
1090                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1091                         bp->link_info.force_pause = 0;
1092                 } else {
1093                         bp->link_info.auto_pause = 0;
1094                         bp->link_info.force_pause =
1095                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1096                 }
1097                 break;
1098         case RTE_FC_FULL:
1099                 if (fc_conf->autoneg) {
1100                         bp->link_info.auto_pause =
1101                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1102                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1103                         bp->link_info.force_pause = 0;
1104                 } else {
1105                         bp->link_info.auto_pause = 0;
1106                         bp->link_info.force_pause =
1107                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1108                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1109                 }
1110                 break;
1111         }
1112         return bnxt_set_hwrm_link_config(bp, true);
1113 }
1114
1115 /* Add UDP tunneling port */
1116 static int
1117 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1118                          struct rte_eth_udp_tunnel *udp_tunnel)
1119 {
1120         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1121         uint16_t tunnel_type = 0;
1122         int rc = 0;
1123
1124         switch (udp_tunnel->prot_type) {
1125         case RTE_TUNNEL_TYPE_VXLAN:
1126                 if (bp->vxlan_port_cnt) {
1127                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1128                                 udp_tunnel->udp_port);
1129                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1130                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1131                                 return -ENOSPC;
1132                         }
1133                         bp->vxlan_port_cnt++;
1134                         return 0;
1135                 }
1136                 tunnel_type =
1137                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1138                 bp->vxlan_port_cnt++;
1139                 break;
1140         case RTE_TUNNEL_TYPE_GENEVE:
1141                 if (bp->geneve_port_cnt) {
1142                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1143                                 udp_tunnel->udp_port);
1144                         if (bp->geneve_port != udp_tunnel->udp_port) {
1145                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1146                                 return -ENOSPC;
1147                         }
1148                         bp->geneve_port_cnt++;
1149                         return 0;
1150                 }
1151                 tunnel_type =
1152                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1153                 bp->geneve_port_cnt++;
1154                 break;
1155         default:
1156                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1157                 return -ENOTSUP;
1158         }
1159         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1160                                              tunnel_type);
1161         return rc;
1162 }
1163
1164 static int
1165 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1166                          struct rte_eth_udp_tunnel *udp_tunnel)
1167 {
1168         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1169         uint16_t tunnel_type = 0;
1170         uint16_t port = 0;
1171         int rc = 0;
1172
1173         switch (udp_tunnel->prot_type) {
1174         case RTE_TUNNEL_TYPE_VXLAN:
1175                 if (!bp->vxlan_port_cnt) {
1176                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1177                         return -EINVAL;
1178                 }
1179                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1180                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1181                                 udp_tunnel->udp_port, bp->vxlan_port);
1182                         return -EINVAL;
1183                 }
1184                 if (--bp->vxlan_port_cnt)
1185                         return 0;
1186
1187                 tunnel_type =
1188                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1189                 port = bp->vxlan_fw_dst_port_id;
1190                 break;
1191         case RTE_TUNNEL_TYPE_GENEVE:
1192                 if (!bp->geneve_port_cnt) {
1193                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1194                         return -EINVAL;
1195                 }
1196                 if (bp->geneve_port != udp_tunnel->udp_port) {
1197                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1198                                 udp_tunnel->udp_port, bp->geneve_port);
1199                         return -EINVAL;
1200                 }
1201                 if (--bp->geneve_port_cnt)
1202                         return 0;
1203
1204                 tunnel_type =
1205                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1206                 port = bp->geneve_fw_dst_port_id;
1207                 break;
1208         default:
1209                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1210                 return -ENOTSUP;
1211         }
1212
1213         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1214         if (!rc) {
1215                 if (tunnel_type ==
1216                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1217                         bp->vxlan_port = 0;
1218                 if (tunnel_type ==
1219                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1220                         bp->geneve_port = 0;
1221         }
1222         return rc;
1223 }
1224
1225 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1226 {
1227         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1228         struct bnxt_vnic_info *vnic;
1229         unsigned int i;
1230         int rc = 0;
1231         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1232
1233         /* Cycle through all VNICs */
1234         for (i = 0; i < bp->nr_vnics; i++) {
1235                 /*
1236                  * For each VNIC and each associated filter(s)
1237                  * if VLAN exists && VLAN matches vlan_id
1238                  *      remove the MAC+VLAN filter
1239                  *      add a new MAC only filter
1240                  * else
1241                  *      VLAN filter doesn't exist, just skip and continue
1242                  */
1243                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1244                         filter = STAILQ_FIRST(&vnic->filter);
1245                         while (filter) {
1246                                 temp_filter = STAILQ_NEXT(filter, next);
1247
1248                                 if (filter->enables & chk &&
1249                                     filter->l2_ovlan == vlan_id) {
1250                                         /* Must delete the filter */
1251                                         STAILQ_REMOVE(&vnic->filter, filter,
1252                                                       bnxt_filter_info, next);
1253                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1254                                         STAILQ_INSERT_TAIL(
1255                                                         &bp->free_filter_list,
1256                                                         filter, next);
1257
1258                                         /*
1259                                          * Need to examine to see if the MAC
1260                                          * filter already existed or not before
1261                                          * allocating a new one
1262                                          */
1263
1264                                         new_filter = bnxt_alloc_filter(bp);
1265                                         if (!new_filter) {
1266                                                 PMD_DRV_LOG(ERR,
1267                                                         "MAC/VLAN filter alloc failed\n");
1268                                                 rc = -ENOMEM;
1269                                                 goto exit;
1270                                         }
1271                                         STAILQ_INSERT_TAIL(&vnic->filter,
1272                                                            new_filter, next);
1273                                         /* Inherit MAC from previous filter */
1274                                         new_filter->mac_index =
1275                                                         filter->mac_index;
1276                                         memcpy(new_filter->l2_addr,
1277                                                filter->l2_addr, ETHER_ADDR_LEN);
1278                                         /* MAC only filter */
1279                                         rc = bnxt_hwrm_set_l2_filter(bp,
1280                                                         vnic->fw_vnic_id,
1281                                                         new_filter);
1282                                         if (rc)
1283                                                 goto exit;
1284                                         PMD_DRV_LOG(INFO,
1285                                                 "Del Vlan filter for %d\n",
1286                                                 vlan_id);
1287                                 }
1288                                 filter = temp_filter;
1289                         }
1290                 }
1291         }
1292 exit:
1293         return rc;
1294 }
1295
1296 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1297 {
1298         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1299         struct bnxt_vnic_info *vnic;
1300         unsigned int i;
1301         int rc = 0;
1302         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1303                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1304         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1305
1306         /* Cycle through all VNICs */
1307         for (i = 0; i < bp->nr_vnics; i++) {
1308                 /*
1309                  * For each VNIC and each associated filter(s)
1310                  * if VLAN exists:
1311                  *   if VLAN matches vlan_id
1312                  *      VLAN filter already exists, just skip and continue
1313                  *   else
1314                  *      add a new MAC+VLAN filter
1315                  * else
1316                  *   Remove the old MAC only filter
1317                  *    Add a new MAC+VLAN filter
1318                  */
1319                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1320                         filter = STAILQ_FIRST(&vnic->filter);
1321                         while (filter) {
1322                                 temp_filter = STAILQ_NEXT(filter, next);
1323
1324                                 if (filter->enables & chk) {
1325                                         if (filter->l2_ovlan == vlan_id)
1326                                                 goto cont;
1327                                 } else {
1328                                         /* Must delete the MAC filter */
1329                                         STAILQ_REMOVE(&vnic->filter, filter,
1330                                                       bnxt_filter_info, next);
1331                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1332                                         filter->l2_ovlan = 0;
1333                                         STAILQ_INSERT_TAIL(
1334                                                         &bp->free_filter_list,
1335                                                         filter, next);
1336                                 }
1337                                 new_filter = bnxt_alloc_filter(bp);
1338                                 if (!new_filter) {
1339                                         PMD_DRV_LOG(ERR,
1340                                                 "MAC/VLAN filter alloc failed\n");
1341                                         rc = -ENOMEM;
1342                                         goto exit;
1343                                 }
1344                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1345                                                    next);
1346                                 /* Inherit MAC from the previous filter */
1347                                 new_filter->mac_index = filter->mac_index;
1348                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1349                                        ETHER_ADDR_LEN);
1350                                 /* MAC + VLAN ID filter */
1351                                 new_filter->l2_ovlan = vlan_id;
1352                                 new_filter->l2_ovlan_mask = 0xF000;
1353                                 new_filter->enables |= en;
1354                                 rc = bnxt_hwrm_set_l2_filter(bp,
1355                                                              vnic->fw_vnic_id,
1356                                                              new_filter);
1357                                 if (rc)
1358                                         goto exit;
1359                                 PMD_DRV_LOG(INFO,
1360                                         "Added Vlan filter for %d\n", vlan_id);
1361 cont:
1362                                 filter = temp_filter;
1363                         }
1364                 }
1365         }
1366 exit:
1367         return rc;
1368 }
1369
1370 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1371                                    uint16_t vlan_id, int on)
1372 {
1373         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1374
1375         /* These operations apply to ALL existing MAC/VLAN filters */
1376         if (on)
1377                 return bnxt_add_vlan_filter(bp, vlan_id);
1378         else
1379                 return bnxt_del_vlan_filter(bp, vlan_id);
1380 }
1381
1382 static int
1383 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1384 {
1385         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1386         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1387         unsigned int i;
1388
1389         if (mask & ETH_VLAN_FILTER_MASK) {
1390                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1391                         /* Remove any VLAN filters programmed */
1392                         for (i = 0; i < 4095; i++)
1393                                 bnxt_del_vlan_filter(bp, i);
1394                 }
1395                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1396                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1397         }
1398
1399         if (mask & ETH_VLAN_STRIP_MASK) {
1400                 /* Enable or disable VLAN stripping */
1401                 for (i = 0; i < bp->nr_vnics; i++) {
1402                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1403                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1404                                 vnic->vlan_strip = true;
1405                         else
1406                                 vnic->vlan_strip = false;
1407                         bnxt_hwrm_vnic_cfg(bp, vnic);
1408                 }
1409                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1410                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1411         }
1412
1413         if (mask & ETH_VLAN_EXTEND_MASK)
1414                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1415
1416         return 0;
1417 }
1418
1419 static int
1420 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1421 {
1422         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1423         /* Default Filter is tied to VNIC 0 */
1424         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1425         struct bnxt_filter_info *filter;
1426         int rc;
1427
1428         if (BNXT_VF(bp))
1429                 return -EPERM;
1430
1431         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1432
1433         STAILQ_FOREACH(filter, &vnic->filter, next) {
1434                 /* Default Filter is at Index 0 */
1435                 if (filter->mac_index != 0)
1436                         continue;
1437                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1438                 if (rc)
1439                         return rc;
1440                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1441                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1442                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1443                 filter->enables |=
1444                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1445                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1446                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1447                 if (rc)
1448                         return rc;
1449                 filter->mac_index = 0;
1450                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1451         }
1452
1453         return 0;
1454 }
1455
1456 static int
1457 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1458                           struct ether_addr *mc_addr_set,
1459                           uint32_t nb_mc_addr)
1460 {
1461         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1462         char *mc_addr_list = (char *)mc_addr_set;
1463         struct bnxt_vnic_info *vnic;
1464         uint32_t off = 0, i = 0;
1465
1466         vnic = &bp->vnic_info[0];
1467
1468         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1469                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1470                 goto allmulti;
1471         }
1472
1473         /* TODO Check for Duplicate mcast addresses */
1474         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1475         for (i = 0; i < nb_mc_addr; i++) {
1476                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1477                 off += ETHER_ADDR_LEN;
1478         }
1479
1480         vnic->mc_addr_cnt = i;
1481
1482 allmulti:
1483         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1484 }
1485
1486 static int
1487 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1488 {
1489         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1490         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1491         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1492         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1493         int ret;
1494
1495         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1496                         fw_major, fw_minor, fw_updt);
1497
1498         ret += 1; /* add the size of '\0' */
1499         if (fw_size < (uint32_t)ret)
1500                 return ret;
1501         else
1502                 return 0;
1503 }
1504
1505 static void
1506 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1507         struct rte_eth_rxq_info *qinfo)
1508 {
1509         struct bnxt_rx_queue *rxq;
1510
1511         rxq = dev->data->rx_queues[queue_id];
1512
1513         qinfo->mp = rxq->mb_pool;
1514         qinfo->scattered_rx = dev->data->scattered_rx;
1515         qinfo->nb_desc = rxq->nb_rx_desc;
1516
1517         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1518         qinfo->conf.rx_drop_en = 0;
1519         qinfo->conf.rx_deferred_start = 0;
1520 }
1521
1522 static void
1523 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1524         struct rte_eth_txq_info *qinfo)
1525 {
1526         struct bnxt_tx_queue *txq;
1527
1528         txq = dev->data->tx_queues[queue_id];
1529
1530         qinfo->nb_desc = txq->nb_tx_desc;
1531
1532         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1533         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1534         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1535
1536         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1537         qinfo->conf.tx_rs_thresh = 0;
1538         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1539 }
1540
1541 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1542 {
1543         struct bnxt *bp = eth_dev->data->dev_private;
1544         struct rte_eth_dev_info dev_info;
1545         uint32_t max_dev_mtu;
1546         uint32_t rc = 0;
1547         uint32_t i;
1548
1549         bnxt_dev_info_get_op(eth_dev, &dev_info);
1550         max_dev_mtu = dev_info.max_rx_pktlen -
1551                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1552
1553         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1554                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1555                         ETHER_MIN_MTU, max_dev_mtu);
1556                 return -EINVAL;
1557         }
1558
1559
1560         if (new_mtu > ETHER_MTU) {
1561                 bp->flags |= BNXT_FLAG_JUMBO;
1562                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1563                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1564         } else {
1565                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1566                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1567                 bp->flags &= ~BNXT_FLAG_JUMBO;
1568         }
1569
1570         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1571                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1572
1573         eth_dev->data->mtu = new_mtu;
1574         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1575
1576         for (i = 0; i < bp->nr_vnics; i++) {
1577                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1578
1579                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1580                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1581                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1582                 if (rc)
1583                         break;
1584
1585                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1586                 if (rc)
1587                         return rc;
1588         }
1589
1590         return rc;
1591 }
1592
1593 static int
1594 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1595 {
1596         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1597         uint16_t vlan = bp->vlan;
1598         int rc;
1599
1600         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1601                 PMD_DRV_LOG(ERR,
1602                         "PVID cannot be modified for this function\n");
1603                 return -ENOTSUP;
1604         }
1605         bp->vlan = on ? pvid : 0;
1606
1607         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1608         if (rc)
1609                 bp->vlan = vlan;
1610         return rc;
1611 }
1612
1613 static int
1614 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1615 {
1616         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1617
1618         return bnxt_hwrm_port_led_cfg(bp, true);
1619 }
1620
1621 static int
1622 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1623 {
1624         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1625
1626         return bnxt_hwrm_port_led_cfg(bp, false);
1627 }
1628
1629 static uint32_t
1630 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1631 {
1632         uint32_t desc = 0, raw_cons = 0, cons;
1633         struct bnxt_cp_ring_info *cpr;
1634         struct bnxt_rx_queue *rxq;
1635         struct rx_pkt_cmpl *rxcmp;
1636         uint16_t cmp_type;
1637         uint8_t cmp = 1;
1638         bool valid;
1639
1640         rxq = dev->data->rx_queues[rx_queue_id];
1641         cpr = rxq->cp_ring;
1642         valid = cpr->valid;
1643
1644         while (raw_cons < rxq->nb_rx_desc) {
1645                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1646                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1647
1648                 if (!CMPL_VALID(rxcmp, valid))
1649                         goto nothing_to_do;
1650                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1651                 cmp_type = CMP_TYPE(rxcmp);
1652                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1653                         cmp = (rte_le_to_cpu_32(
1654                                         ((struct rx_tpa_end_cmpl *)
1655                                          (rxcmp))->agg_bufs_v1) &
1656                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1657                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1658                         desc++;
1659                 } else if (cmp_type == 0x11) {
1660                         desc++;
1661                         cmp = (rxcmp->agg_bufs_v1 &
1662                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1663                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1664                 } else {
1665                         cmp = 1;
1666                 }
1667 nothing_to_do:
1668                 raw_cons += cmp ? cmp : 2;
1669         }
1670
1671         return desc;
1672 }
1673
1674 static int
1675 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1676 {
1677         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1678         struct bnxt_rx_ring_info *rxr;
1679         struct bnxt_cp_ring_info *cpr;
1680         struct bnxt_sw_rx_bd *rx_buf;
1681         struct rx_pkt_cmpl *rxcmp;
1682         uint32_t cons, cp_cons;
1683
1684         if (!rxq)
1685                 return -EINVAL;
1686
1687         cpr = rxq->cp_ring;
1688         rxr = rxq->rx_ring;
1689
1690         if (offset >= rxq->nb_rx_desc)
1691                 return -EINVAL;
1692
1693         cons = RING_CMP(cpr->cp_ring_struct, offset);
1694         cp_cons = cpr->cp_raw_cons;
1695         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1696
1697         if (cons > cp_cons) {
1698                 if (CMPL_VALID(rxcmp, cpr->valid))
1699                         return RTE_ETH_RX_DESC_DONE;
1700         } else {
1701                 if (CMPL_VALID(rxcmp, !cpr->valid))
1702                         return RTE_ETH_RX_DESC_DONE;
1703         }
1704         rx_buf = &rxr->rx_buf_ring[cons];
1705         if (rx_buf->mbuf == NULL)
1706                 return RTE_ETH_RX_DESC_UNAVAIL;
1707
1708
1709         return RTE_ETH_RX_DESC_AVAIL;
1710 }
1711
1712 static int
1713 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1714 {
1715         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1716         struct bnxt_tx_ring_info *txr;
1717         struct bnxt_cp_ring_info *cpr;
1718         struct bnxt_sw_tx_bd *tx_buf;
1719         struct tx_pkt_cmpl *txcmp;
1720         uint32_t cons, cp_cons;
1721
1722         if (!txq)
1723                 return -EINVAL;
1724
1725         cpr = txq->cp_ring;
1726         txr = txq->tx_ring;
1727
1728         if (offset >= txq->nb_tx_desc)
1729                 return -EINVAL;
1730
1731         cons = RING_CMP(cpr->cp_ring_struct, offset);
1732         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1733         cp_cons = cpr->cp_raw_cons;
1734
1735         if (cons > cp_cons) {
1736                 if (CMPL_VALID(txcmp, cpr->valid))
1737                         return RTE_ETH_TX_DESC_UNAVAIL;
1738         } else {
1739                 if (CMPL_VALID(txcmp, !cpr->valid))
1740                         return RTE_ETH_TX_DESC_UNAVAIL;
1741         }
1742         tx_buf = &txr->tx_buf_ring[cons];
1743         if (tx_buf->mbuf == NULL)
1744                 return RTE_ETH_TX_DESC_DONE;
1745
1746         return RTE_ETH_TX_DESC_FULL;
1747 }
1748
1749 static struct bnxt_filter_info *
1750 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1751                                 struct rte_eth_ethertype_filter *efilter,
1752                                 struct bnxt_vnic_info *vnic0,
1753                                 struct bnxt_vnic_info *vnic,
1754                                 int *ret)
1755 {
1756         struct bnxt_filter_info *mfilter = NULL;
1757         int match = 0;
1758         *ret = 0;
1759
1760         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1761                 efilter->ether_type == ETHER_TYPE_IPv6) {
1762                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1763                         " ethertype filter.", efilter->ether_type);
1764                 *ret = -EINVAL;
1765                 goto exit;
1766         }
1767         if (efilter->queue >= bp->rx_nr_rings) {
1768                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1769                 *ret = -EINVAL;
1770                 goto exit;
1771         }
1772
1773         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1774         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1775         if (vnic == NULL) {
1776                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1777                 *ret = -EINVAL;
1778                 goto exit;
1779         }
1780
1781         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1782                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1783                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1784                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1785                              mfilter->flags ==
1786                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1787                              mfilter->ethertype == efilter->ether_type)) {
1788                                 match = 1;
1789                                 break;
1790                         }
1791                 }
1792         } else {
1793                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1794                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1795                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1796                              mfilter->ethertype == efilter->ether_type &&
1797                              mfilter->flags ==
1798                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1799                                 match = 1;
1800                                 break;
1801                         }
1802         }
1803
1804         if (match)
1805                 *ret = -EEXIST;
1806
1807 exit:
1808         return mfilter;
1809 }
1810
1811 static int
1812 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1813                         enum rte_filter_op filter_op,
1814                         void *arg)
1815 {
1816         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1817         struct rte_eth_ethertype_filter *efilter =
1818                         (struct rte_eth_ethertype_filter *)arg;
1819         struct bnxt_filter_info *bfilter, *filter1;
1820         struct bnxt_vnic_info *vnic, *vnic0;
1821         int ret;
1822
1823         if (filter_op == RTE_ETH_FILTER_NOP)
1824                 return 0;
1825
1826         if (arg == NULL) {
1827                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1828                             filter_op);
1829                 return -EINVAL;
1830         }
1831
1832         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1833         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1834
1835         switch (filter_op) {
1836         case RTE_ETH_FILTER_ADD:
1837                 bnxt_match_and_validate_ether_filter(bp, efilter,
1838                                                         vnic0, vnic, &ret);
1839                 if (ret < 0)
1840                         return ret;
1841
1842                 bfilter = bnxt_get_unused_filter(bp);
1843                 if (bfilter == NULL) {
1844                         PMD_DRV_LOG(ERR,
1845                                 "Not enough resources for a new filter.\n");
1846                         return -ENOMEM;
1847                 }
1848                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1849                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1850                        ETHER_ADDR_LEN);
1851                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1852                        ETHER_ADDR_LEN);
1853                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1854                 bfilter->ethertype = efilter->ether_type;
1855                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1856
1857                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1858                 if (filter1 == NULL) {
1859                         ret = -1;
1860                         goto cleanup;
1861                 }
1862                 bfilter->enables |=
1863                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1864                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1865
1866                 bfilter->dst_id = vnic->fw_vnic_id;
1867
1868                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1869                         bfilter->flags =
1870                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1871                 }
1872
1873                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1874                 if (ret)
1875                         goto cleanup;
1876                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1877                 break;
1878         case RTE_ETH_FILTER_DELETE:
1879                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1880                                                         vnic0, vnic, &ret);
1881                 if (ret == -EEXIST) {
1882                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1883
1884                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1885                                       next);
1886                         bnxt_free_filter(bp, filter1);
1887                 } else if (ret == 0) {
1888                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1889                 }
1890                 break;
1891         default:
1892                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1893                 ret = -EINVAL;
1894                 goto error;
1895         }
1896         return ret;
1897 cleanup:
1898         bnxt_free_filter(bp, bfilter);
1899 error:
1900         return ret;
1901 }
1902
1903 static inline int
1904 parse_ntuple_filter(struct bnxt *bp,
1905                     struct rte_eth_ntuple_filter *nfilter,
1906                     struct bnxt_filter_info *bfilter)
1907 {
1908         uint32_t en = 0;
1909
1910         if (nfilter->queue >= bp->rx_nr_rings) {
1911                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1912                 return -EINVAL;
1913         }
1914
1915         switch (nfilter->dst_port_mask) {
1916         case UINT16_MAX:
1917                 bfilter->dst_port_mask = -1;
1918                 bfilter->dst_port = nfilter->dst_port;
1919                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1920                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1921                 break;
1922         default:
1923                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1924                 return -EINVAL;
1925         }
1926
1927         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1928         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1929
1930         switch (nfilter->proto_mask) {
1931         case UINT8_MAX:
1932                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1933                         bfilter->ip_protocol = 17;
1934                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1935                         bfilter->ip_protocol = 6;
1936                 else
1937                         return -EINVAL;
1938                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1939                 break;
1940         default:
1941                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1942                 return -EINVAL;
1943         }
1944
1945         switch (nfilter->dst_ip_mask) {
1946         case UINT32_MAX:
1947                 bfilter->dst_ipaddr_mask[0] = -1;
1948                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1949                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1950                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1951                 break;
1952         default:
1953                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1954                 return -EINVAL;
1955         }
1956
1957         switch (nfilter->src_ip_mask) {
1958         case UINT32_MAX:
1959                 bfilter->src_ipaddr_mask[0] = -1;
1960                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1961                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1962                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1963                 break;
1964         default:
1965                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1966                 return -EINVAL;
1967         }
1968
1969         switch (nfilter->src_port_mask) {
1970         case UINT16_MAX:
1971                 bfilter->src_port_mask = -1;
1972                 bfilter->src_port = nfilter->src_port;
1973                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1974                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1975                 break;
1976         default:
1977                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1978                 return -EINVAL;
1979         }
1980
1981         //TODO Priority
1982         //nfilter->priority = (uint8_t)filter->priority;
1983
1984         bfilter->enables = en;
1985         return 0;
1986 }
1987
1988 static struct bnxt_filter_info*
1989 bnxt_match_ntuple_filter(struct bnxt *bp,
1990                          struct bnxt_filter_info *bfilter,
1991                          struct bnxt_vnic_info **mvnic)
1992 {
1993         struct bnxt_filter_info *mfilter = NULL;
1994         int i;
1995
1996         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1997                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1998                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1999                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2000                             bfilter->src_ipaddr_mask[0] ==
2001                             mfilter->src_ipaddr_mask[0] &&
2002                             bfilter->src_port == mfilter->src_port &&
2003                             bfilter->src_port_mask == mfilter->src_port_mask &&
2004                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2005                             bfilter->dst_ipaddr_mask[0] ==
2006                             mfilter->dst_ipaddr_mask[0] &&
2007                             bfilter->dst_port == mfilter->dst_port &&
2008                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2009                             bfilter->flags == mfilter->flags &&
2010                             bfilter->enables == mfilter->enables) {
2011                                 if (mvnic)
2012                                         *mvnic = vnic;
2013                                 return mfilter;
2014                         }
2015                 }
2016         }
2017         return NULL;
2018 }
2019
2020 static int
2021 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2022                        struct rte_eth_ntuple_filter *nfilter,
2023                        enum rte_filter_op filter_op)
2024 {
2025         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2026         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2027         int ret;
2028
2029         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2030                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2031                 return -EINVAL;
2032         }
2033
2034         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2035                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2036                 return -EINVAL;
2037         }
2038
2039         bfilter = bnxt_get_unused_filter(bp);
2040         if (bfilter == NULL) {
2041                 PMD_DRV_LOG(ERR,
2042                         "Not enough resources for a new filter.\n");
2043                 return -ENOMEM;
2044         }
2045         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2046         if (ret < 0)
2047                 goto free_filter;
2048
2049         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2050         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2051         filter1 = STAILQ_FIRST(&vnic0->filter);
2052         if (filter1 == NULL) {
2053                 ret = -1;
2054                 goto free_filter;
2055         }
2056
2057         bfilter->dst_id = vnic->fw_vnic_id;
2058         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2059         bfilter->enables |=
2060                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2061         bfilter->ethertype = 0x800;
2062         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2063
2064         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2065
2066         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2067             bfilter->dst_id == mfilter->dst_id) {
2068                 PMD_DRV_LOG(ERR, "filter exists.\n");
2069                 ret = -EEXIST;
2070                 goto free_filter;
2071         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2072                    bfilter->dst_id != mfilter->dst_id) {
2073                 mfilter->dst_id = vnic->fw_vnic_id;
2074                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2075                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2076                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2077                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2078                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2079                 goto free_filter;
2080         }
2081         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2082                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2083                 ret = -ENOENT;
2084                 goto free_filter;
2085         }
2086
2087         if (filter_op == RTE_ETH_FILTER_ADD) {
2088                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2089                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2090                 if (ret)
2091                         goto free_filter;
2092                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2093         } else {
2094                 if (mfilter == NULL) {
2095                         /* This should not happen. But for Coverity! */
2096                         ret = -ENOENT;
2097                         goto free_filter;
2098                 }
2099                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2100
2101                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2102                 bnxt_free_filter(bp, mfilter);
2103                 mfilter->fw_l2_filter_id = -1;
2104                 bnxt_free_filter(bp, bfilter);
2105                 bfilter->fw_l2_filter_id = -1;
2106         }
2107
2108         return 0;
2109 free_filter:
2110         bfilter->fw_l2_filter_id = -1;
2111         bnxt_free_filter(bp, bfilter);
2112         return ret;
2113 }
2114
2115 static int
2116 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2117                         enum rte_filter_op filter_op,
2118                         void *arg)
2119 {
2120         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2121         int ret;
2122
2123         if (filter_op == RTE_ETH_FILTER_NOP)
2124                 return 0;
2125
2126         if (arg == NULL) {
2127                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2128                             filter_op);
2129                 return -EINVAL;
2130         }
2131
2132         switch (filter_op) {
2133         case RTE_ETH_FILTER_ADD:
2134                 ret = bnxt_cfg_ntuple_filter(bp,
2135                         (struct rte_eth_ntuple_filter *)arg,
2136                         filter_op);
2137                 break;
2138         case RTE_ETH_FILTER_DELETE:
2139                 ret = bnxt_cfg_ntuple_filter(bp,
2140                         (struct rte_eth_ntuple_filter *)arg,
2141                         filter_op);
2142                 break;
2143         default:
2144                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2145                 ret = -EINVAL;
2146                 break;
2147         }
2148         return ret;
2149 }
2150
2151 static int
2152 bnxt_parse_fdir_filter(struct bnxt *bp,
2153                        struct rte_eth_fdir_filter *fdir,
2154                        struct bnxt_filter_info *filter)
2155 {
2156         enum rte_fdir_mode fdir_mode =
2157                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2158         struct bnxt_vnic_info *vnic0, *vnic;
2159         struct bnxt_filter_info *filter1;
2160         uint32_t en = 0;
2161         int i;
2162
2163         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2164                 return -EINVAL;
2165
2166         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2167         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2168
2169         switch (fdir->input.flow_type) {
2170         case RTE_ETH_FLOW_IPV4:
2171         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2172                 /* FALLTHROUGH */
2173                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2174                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2175                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2176                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2177                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2178                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2179                 filter->ip_addr_type =
2180                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2181                 filter->src_ipaddr_mask[0] = 0xffffffff;
2182                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2183                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2184                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2185                 filter->ethertype = 0x800;
2186                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2187                 break;
2188         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2189                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2190                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2191                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2192                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2193                 filter->dst_port_mask = 0xffff;
2194                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2195                 filter->src_port_mask = 0xffff;
2196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2197                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2198                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2199                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2201                 filter->ip_protocol = 6;
2202                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2203                 filter->ip_addr_type =
2204                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2205                 filter->src_ipaddr_mask[0] = 0xffffffff;
2206                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2207                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2209                 filter->ethertype = 0x800;
2210                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2211                 break;
2212         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2213                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2215                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2217                 filter->dst_port_mask = 0xffff;
2218                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2219                 filter->src_port_mask = 0xffff;
2220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2221                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2222                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2223                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2224                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2225                 filter->ip_protocol = 17;
2226                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2227                 filter->ip_addr_type =
2228                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2229                 filter->src_ipaddr_mask[0] = 0xffffffff;
2230                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2231                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2232                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2233                 filter->ethertype = 0x800;
2234                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2235                 break;
2236         case RTE_ETH_FLOW_IPV6:
2237         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2238                 /* FALLTHROUGH */
2239                 filter->ip_addr_type =
2240                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2241                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2242                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2243                 rte_memcpy(filter->src_ipaddr,
2244                            fdir->input.flow.ipv6_flow.src_ip, 16);
2245                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2246                 rte_memcpy(filter->dst_ipaddr,
2247                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2248                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2249                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2250                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2251                 memset(filter->src_ipaddr_mask, 0xff, 16);
2252                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2253                 filter->ethertype = 0x86dd;
2254                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2255                 break;
2256         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2257                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2258                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2259                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2260                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2261                 filter->dst_port_mask = 0xffff;
2262                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2263                 filter->src_port_mask = 0xffff;
2264                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2265                 filter->ip_addr_type =
2266                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2267                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2268                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2269                 rte_memcpy(filter->src_ipaddr,
2270                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2271                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2272                 rte_memcpy(filter->dst_ipaddr,
2273                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2275                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2276                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2277                 memset(filter->src_ipaddr_mask, 0xff, 16);
2278                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2279                 filter->ethertype = 0x86dd;
2280                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2281                 break;
2282         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2283                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2285                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2286                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2287                 filter->dst_port_mask = 0xffff;
2288                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2289                 filter->src_port_mask = 0xffff;
2290                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2291                 filter->ip_addr_type =
2292                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2293                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2294                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2295                 rte_memcpy(filter->src_ipaddr,
2296                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2297                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2298                 rte_memcpy(filter->dst_ipaddr,
2299                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2300                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2301                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2302                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2303                 memset(filter->src_ipaddr_mask, 0xff, 16);
2304                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2305                 filter->ethertype = 0x86dd;
2306                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2307                 break;
2308         case RTE_ETH_FLOW_L2_PAYLOAD:
2309                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2310                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2311                 break;
2312         case RTE_ETH_FLOW_VXLAN:
2313                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2314                         return -EINVAL;
2315                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2316                 filter->tunnel_type =
2317                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2318                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2319                 break;
2320         case RTE_ETH_FLOW_NVGRE:
2321                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2322                         return -EINVAL;
2323                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2324                 filter->tunnel_type =
2325                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2326                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2327                 break;
2328         case RTE_ETH_FLOW_UNKNOWN:
2329         case RTE_ETH_FLOW_RAW:
2330         case RTE_ETH_FLOW_FRAG_IPV4:
2331         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2332         case RTE_ETH_FLOW_FRAG_IPV6:
2333         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2334         case RTE_ETH_FLOW_IPV6_EX:
2335         case RTE_ETH_FLOW_IPV6_TCP_EX:
2336         case RTE_ETH_FLOW_IPV6_UDP_EX:
2337         case RTE_ETH_FLOW_GENEVE:
2338                 /* FALLTHROUGH */
2339         default:
2340                 return -EINVAL;
2341         }
2342
2343         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2344         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2345         if (vnic == NULL) {
2346                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2347                 return -EINVAL;
2348         }
2349
2350
2351         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2352                 rte_memcpy(filter->dst_macaddr,
2353                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2354                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2355         }
2356
2357         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2358                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2359                 filter1 = STAILQ_FIRST(&vnic0->filter);
2360                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2361         } else {
2362                 filter->dst_id = vnic->fw_vnic_id;
2363                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2364                         if (filter->dst_macaddr[i] == 0x00)
2365                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2366                         else
2367                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2368         }
2369
2370         if (filter1 == NULL)
2371                 return -EINVAL;
2372
2373         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2374         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2375
2376         filter->enables = en;
2377
2378         return 0;
2379 }
2380
2381 static struct bnxt_filter_info *
2382 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2383                 struct bnxt_vnic_info **mvnic)
2384 {
2385         struct bnxt_filter_info *mf = NULL;
2386         int i;
2387
2388         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2389                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2390
2391                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2392                         if (mf->filter_type == nf->filter_type &&
2393                             mf->flags == nf->flags &&
2394                             mf->src_port == nf->src_port &&
2395                             mf->src_port_mask == nf->src_port_mask &&
2396                             mf->dst_port == nf->dst_port &&
2397                             mf->dst_port_mask == nf->dst_port_mask &&
2398                             mf->ip_protocol == nf->ip_protocol &&
2399                             mf->ip_addr_type == nf->ip_addr_type &&
2400                             mf->ethertype == nf->ethertype &&
2401                             mf->vni == nf->vni &&
2402                             mf->tunnel_type == nf->tunnel_type &&
2403                             mf->l2_ovlan == nf->l2_ovlan &&
2404                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2405                             mf->l2_ivlan == nf->l2_ivlan &&
2406                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2407                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2408                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2409                                     ETHER_ADDR_LEN) &&
2410                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2411                                     ETHER_ADDR_LEN) &&
2412                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2413                                     ETHER_ADDR_LEN) &&
2414                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2415                                     sizeof(nf->src_ipaddr)) &&
2416                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2417                                     sizeof(nf->src_ipaddr_mask)) &&
2418                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2419                                     sizeof(nf->dst_ipaddr)) &&
2420                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2421                                     sizeof(nf->dst_ipaddr_mask))) {
2422                                 if (mvnic)
2423                                         *mvnic = vnic;
2424                                 return mf;
2425                         }
2426                 }
2427         }
2428         return NULL;
2429 }
2430
2431 static int
2432 bnxt_fdir_filter(struct rte_eth_dev *dev,
2433                  enum rte_filter_op filter_op,
2434                  void *arg)
2435 {
2436         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2437         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2438         struct bnxt_filter_info *filter, *match;
2439         struct bnxt_vnic_info *vnic, *mvnic;
2440         int ret = 0, i;
2441
2442         if (filter_op == RTE_ETH_FILTER_NOP)
2443                 return 0;
2444
2445         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2446                 return -EINVAL;
2447
2448         switch (filter_op) {
2449         case RTE_ETH_FILTER_ADD:
2450         case RTE_ETH_FILTER_DELETE:
2451                 filter = bnxt_get_unused_filter(bp);
2452                 if (filter == NULL) {
2453                         PMD_DRV_LOG(ERR,
2454                                 "Not enough resources for a new flow.\n");
2455                         return -ENOMEM;
2456                 }
2457
2458                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2459                 if (ret != 0)
2460                         goto free_filter;
2461                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2462
2463                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2464                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2465                 else
2466                         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2467
2468                 match = bnxt_match_fdir(bp, filter, &mvnic);
2469                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2470                         if (match->dst_id == vnic->fw_vnic_id) {
2471                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2472                                 ret = -EEXIST;
2473                                 goto free_filter;
2474                         } else {
2475                                 match->dst_id = vnic->fw_vnic_id;
2476                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2477                                                                   match->dst_id,
2478                                                                   match);
2479                                 STAILQ_REMOVE(&mvnic->filter, match,
2480                                               bnxt_filter_info, next);
2481                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2482                                 PMD_DRV_LOG(ERR,
2483                                         "Filter with matching pattern exist\n");
2484                                 PMD_DRV_LOG(ERR,
2485                                         "Updated it to new destination q\n");
2486                                 goto free_filter;
2487                         }
2488                 }
2489                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2490                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2491                         ret = -ENOENT;
2492                         goto free_filter;
2493                 }
2494
2495                 if (filter_op == RTE_ETH_FILTER_ADD) {
2496                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2497                                                           filter->dst_id,
2498                                                           filter);
2499                         if (ret)
2500                                 goto free_filter;
2501                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2502                 } else {
2503                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2504                         STAILQ_REMOVE(&vnic->filter, match,
2505                                       bnxt_filter_info, next);
2506                         bnxt_free_filter(bp, match);
2507                         filter->fw_l2_filter_id = -1;
2508                         bnxt_free_filter(bp, filter);
2509                 }
2510                 break;
2511         case RTE_ETH_FILTER_FLUSH:
2512                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2513                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2514
2515                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2516                                 if (filter->filter_type ==
2517                                     HWRM_CFA_NTUPLE_FILTER) {
2518                                         ret =
2519                                         bnxt_hwrm_clear_ntuple_filter(bp,
2520                                                                       filter);
2521                                         STAILQ_REMOVE(&vnic->filter, filter,
2522                                                       bnxt_filter_info, next);
2523                                 }
2524                         }
2525                 }
2526                 return ret;
2527         case RTE_ETH_FILTER_UPDATE:
2528         case RTE_ETH_FILTER_STATS:
2529         case RTE_ETH_FILTER_INFO:
2530                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2531                 break;
2532         default:
2533                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2534                 ret = -EINVAL;
2535                 break;
2536         }
2537         return ret;
2538
2539 free_filter:
2540         filter->fw_l2_filter_id = -1;
2541         bnxt_free_filter(bp, filter);
2542         return ret;
2543 }
2544
2545 static int
2546 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2547                     enum rte_filter_type filter_type,
2548                     enum rte_filter_op filter_op, void *arg)
2549 {
2550         int ret = 0;
2551
2552         switch (filter_type) {
2553         case RTE_ETH_FILTER_TUNNEL:
2554                 PMD_DRV_LOG(ERR,
2555                         "filter type: %d: To be implemented\n", filter_type);
2556                 break;
2557         case RTE_ETH_FILTER_FDIR:
2558                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2559                 break;
2560         case RTE_ETH_FILTER_NTUPLE:
2561                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2562                 break;
2563         case RTE_ETH_FILTER_ETHERTYPE:
2564                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2565                 break;
2566         case RTE_ETH_FILTER_GENERIC:
2567                 if (filter_op != RTE_ETH_FILTER_GET)
2568                         return -EINVAL;
2569                 *(const void **)arg = &bnxt_flow_ops;
2570                 break;
2571         default:
2572                 PMD_DRV_LOG(ERR,
2573                         "Filter type (%d) not supported", filter_type);
2574                 ret = -EINVAL;
2575                 break;
2576         }
2577         return ret;
2578 }
2579
2580 static const uint32_t *
2581 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2582 {
2583         static const uint32_t ptypes[] = {
2584                 RTE_PTYPE_L2_ETHER_VLAN,
2585                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2586                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2587                 RTE_PTYPE_L4_ICMP,
2588                 RTE_PTYPE_L4_TCP,
2589                 RTE_PTYPE_L4_UDP,
2590                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2591                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2592                 RTE_PTYPE_INNER_L4_ICMP,
2593                 RTE_PTYPE_INNER_L4_TCP,
2594                 RTE_PTYPE_INNER_L4_UDP,
2595                 RTE_PTYPE_UNKNOWN
2596         };
2597
2598         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2599                 return ptypes;
2600         return NULL;
2601 }
2602
2603 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2604                          int reg_win)
2605 {
2606         uint32_t reg_base = *reg_arr & 0xfffff000;
2607         uint32_t win_off;
2608         int i;
2609
2610         for (i = 0; i < count; i++) {
2611                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2612                         return -ERANGE;
2613         }
2614         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2615         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2616         return 0;
2617 }
2618
2619 static int bnxt_map_ptp_regs(struct bnxt *bp)
2620 {
2621         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2622         uint32_t *reg_arr;
2623         int rc, i;
2624
2625         reg_arr = ptp->rx_regs;
2626         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2627         if (rc)
2628                 return rc;
2629
2630         reg_arr = ptp->tx_regs;
2631         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2632         if (rc)
2633                 return rc;
2634
2635         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2636                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2637
2638         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2639                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2640
2641         return 0;
2642 }
2643
2644 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2645 {
2646         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2647                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2648         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2649                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2650 }
2651
2652 static uint64_t bnxt_cc_read(struct bnxt *bp)
2653 {
2654         uint64_t ns;
2655
2656         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2657                               BNXT_GRCPF_REG_SYNC_TIME));
2658         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2659                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2660         return ns;
2661 }
2662
2663 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2664 {
2665         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2666         uint32_t fifo;
2667
2668         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2669                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2670         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2671                 return -EAGAIN;
2672
2673         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2674                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2675         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2676                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2677         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2678                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2679
2680         return 0;
2681 }
2682
2683 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2684 {
2685         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2686         struct bnxt_pf_info *pf = &bp->pf;
2687         uint16_t port_id;
2688         uint32_t fifo;
2689
2690         if (!ptp)
2691                 return -ENODEV;
2692
2693         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2694                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2695         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2696                 return -EAGAIN;
2697
2698         port_id = pf->port_id;
2699         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2700                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2701
2702         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2703                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2704         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2705 /*              bnxt_clr_rx_ts(bp);       TBD  */
2706                 return -EBUSY;
2707         }
2708
2709         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2710                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2711         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2712                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2713
2714         return 0;
2715 }
2716
2717 static int
2718 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2719 {
2720         uint64_t ns;
2721         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2722         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2723
2724         if (!ptp)
2725                 return 0;
2726
2727         ns = rte_timespec_to_ns(ts);
2728         /* Set the timecounters to a new value. */
2729         ptp->tc.nsec = ns;
2730
2731         return 0;
2732 }
2733
2734 static int
2735 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2736 {
2737         uint64_t ns, systime_cycles;
2738         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2739         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2740
2741         if (!ptp)
2742                 return 0;
2743
2744         systime_cycles = bnxt_cc_read(bp);
2745         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2746         *ts = rte_ns_to_timespec(ns);
2747
2748         return 0;
2749 }
2750 static int
2751 bnxt_timesync_enable(struct rte_eth_dev *dev)
2752 {
2753         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2754         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2755         uint32_t shift = 0;
2756
2757         if (!ptp)
2758                 return 0;
2759
2760         ptp->rx_filter = 1;
2761         ptp->tx_tstamp_en = 1;
2762         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2763
2764         if (!bnxt_hwrm_ptp_cfg(bp))
2765                 bnxt_map_ptp_regs(bp);
2766
2767         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2768         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2769         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2770
2771         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2772         ptp->tc.cc_shift = shift;
2773         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2774
2775         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2776         ptp->rx_tstamp_tc.cc_shift = shift;
2777         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2778
2779         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2780         ptp->tx_tstamp_tc.cc_shift = shift;
2781         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2782
2783         return 0;
2784 }
2785
2786 static int
2787 bnxt_timesync_disable(struct rte_eth_dev *dev)
2788 {
2789         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2790         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2791
2792         if (!ptp)
2793                 return 0;
2794
2795         ptp->rx_filter = 0;
2796         ptp->tx_tstamp_en = 0;
2797         ptp->rxctl = 0;
2798
2799         bnxt_hwrm_ptp_cfg(bp);
2800
2801         bnxt_unmap_ptp_regs(bp);
2802
2803         return 0;
2804 }
2805
2806 static int
2807 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2808                                  struct timespec *timestamp,
2809                                  uint32_t flags __rte_unused)
2810 {
2811         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2812         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2813         uint64_t rx_tstamp_cycles = 0;
2814         uint64_t ns;
2815
2816         if (!ptp)
2817                 return 0;
2818
2819         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2820         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2821         *timestamp = rte_ns_to_timespec(ns);
2822         return  0;
2823 }
2824
2825 static int
2826 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2827                                  struct timespec *timestamp)
2828 {
2829         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2830         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2831         uint64_t tx_tstamp_cycles = 0;
2832         uint64_t ns;
2833
2834         if (!ptp)
2835                 return 0;
2836
2837         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2838         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2839         *timestamp = rte_ns_to_timespec(ns);
2840
2841         return 0;
2842 }
2843
2844 static int
2845 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2846 {
2847         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2848         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2849
2850         if (!ptp)
2851                 return 0;
2852
2853         ptp->tc.nsec += delta;
2854
2855         return 0;
2856 }
2857
2858 static int
2859 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2860 {
2861         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2862         int rc;
2863         uint32_t dir_entries;
2864         uint32_t entry_length;
2865
2866         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2867                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2868                 bp->pdev->addr.devid, bp->pdev->addr.function);
2869
2870         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2871         if (rc != 0)
2872                 return rc;
2873
2874         return dir_entries * entry_length;
2875 }
2876
2877 static int
2878 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2879                 struct rte_dev_eeprom_info *in_eeprom)
2880 {
2881         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2882         uint32_t index;
2883         uint32_t offset;
2884
2885         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2886                 "len = %d\n", bp->pdev->addr.domain,
2887                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2888                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2889
2890         if (in_eeprom->offset == 0) /* special offset value to get directory */
2891                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2892                                                 in_eeprom->data);
2893
2894         index = in_eeprom->offset >> 24;
2895         offset = in_eeprom->offset & 0xffffff;
2896
2897         if (index != 0)
2898                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2899                                            in_eeprom->length, in_eeprom->data);
2900
2901         return 0;
2902 }
2903
2904 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2905 {
2906         switch (dir_type) {
2907         case BNX_DIR_TYPE_CHIMP_PATCH:
2908         case BNX_DIR_TYPE_BOOTCODE:
2909         case BNX_DIR_TYPE_BOOTCODE_2:
2910         case BNX_DIR_TYPE_APE_FW:
2911         case BNX_DIR_TYPE_APE_PATCH:
2912         case BNX_DIR_TYPE_KONG_FW:
2913         case BNX_DIR_TYPE_KONG_PATCH:
2914         case BNX_DIR_TYPE_BONO_FW:
2915         case BNX_DIR_TYPE_BONO_PATCH:
2916                 return true;
2917         }
2918
2919         return false;
2920 }
2921
2922 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2923 {
2924         switch (dir_type) {
2925         case BNX_DIR_TYPE_AVS:
2926         case BNX_DIR_TYPE_EXP_ROM_MBA:
2927         case BNX_DIR_TYPE_PCIE:
2928         case BNX_DIR_TYPE_TSCF_UCODE:
2929         case BNX_DIR_TYPE_EXT_PHY:
2930         case BNX_DIR_TYPE_CCM:
2931         case BNX_DIR_TYPE_ISCSI_BOOT:
2932         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2933         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2934                 return true;
2935         }
2936
2937         return false;
2938 }
2939
2940 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2941 {
2942         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2943                 bnxt_dir_type_is_other_exec_format(dir_type);
2944 }
2945
2946 static int
2947 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2948                 struct rte_dev_eeprom_info *in_eeprom)
2949 {
2950         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2951         uint8_t index, dir_op;
2952         uint16_t type, ext, ordinal, attr;
2953
2954         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2955                 "len = %d\n", bp->pdev->addr.domain,
2956                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2957                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2958
2959         if (!BNXT_PF(bp)) {
2960                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2961                 return -EINVAL;
2962         }
2963
2964         type = in_eeprom->magic >> 16;
2965
2966         if (type == 0xffff) { /* special value for directory operations */
2967                 index = in_eeprom->magic & 0xff;
2968                 dir_op = in_eeprom->magic >> 8;
2969                 if (index == 0)
2970                         return -EINVAL;
2971                 switch (dir_op) {
2972                 case 0x0e: /* erase */
2973                         if (in_eeprom->offset != ~in_eeprom->magic)
2974                                 return -EINVAL;
2975                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2976                 default:
2977                         return -EINVAL;
2978                 }
2979         }
2980
2981         /* Create or re-write an NVM item: */
2982         if (bnxt_dir_type_is_executable(type) == true)
2983                 return -EOPNOTSUPP;
2984         ext = in_eeprom->magic & 0xffff;
2985         ordinal = in_eeprom->offset >> 16;
2986         attr = in_eeprom->offset & 0xffff;
2987
2988         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2989                                      in_eeprom->data, in_eeprom->length);
2990         return 0;
2991 }
2992
2993 /*
2994  * Initialization
2995  */
2996
2997 static const struct eth_dev_ops bnxt_dev_ops = {
2998         .dev_infos_get = bnxt_dev_info_get_op,
2999         .dev_close = bnxt_dev_close_op,
3000         .dev_configure = bnxt_dev_configure_op,
3001         .dev_start = bnxt_dev_start_op,
3002         .dev_stop = bnxt_dev_stop_op,
3003         .dev_set_link_up = bnxt_dev_set_link_up_op,
3004         .dev_set_link_down = bnxt_dev_set_link_down_op,
3005         .stats_get = bnxt_stats_get_op,
3006         .stats_reset = bnxt_stats_reset_op,
3007         .rx_queue_setup = bnxt_rx_queue_setup_op,
3008         .rx_queue_release = bnxt_rx_queue_release_op,
3009         .tx_queue_setup = bnxt_tx_queue_setup_op,
3010         .tx_queue_release = bnxt_tx_queue_release_op,
3011         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3012         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3013         .reta_update = bnxt_reta_update_op,
3014         .reta_query = bnxt_reta_query_op,
3015         .rss_hash_update = bnxt_rss_hash_update_op,
3016         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3017         .link_update = bnxt_link_update_op,
3018         .promiscuous_enable = bnxt_promiscuous_enable_op,
3019         .promiscuous_disable = bnxt_promiscuous_disable_op,
3020         .allmulticast_enable = bnxt_allmulticast_enable_op,
3021         .allmulticast_disable = bnxt_allmulticast_disable_op,
3022         .mac_addr_add = bnxt_mac_addr_add_op,
3023         .mac_addr_remove = bnxt_mac_addr_remove_op,
3024         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3025         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3026         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3027         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3028         .vlan_filter_set = bnxt_vlan_filter_set_op,
3029         .vlan_offload_set = bnxt_vlan_offload_set_op,
3030         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3031         .mtu_set = bnxt_mtu_set_op,
3032         .mac_addr_set = bnxt_set_default_mac_addr_op,
3033         .xstats_get = bnxt_dev_xstats_get_op,
3034         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3035         .xstats_reset = bnxt_dev_xstats_reset_op,
3036         .fw_version_get = bnxt_fw_version_get,
3037         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3038         .rxq_info_get = bnxt_rxq_info_get_op,
3039         .txq_info_get = bnxt_txq_info_get_op,
3040         .dev_led_on = bnxt_dev_led_on_op,
3041         .dev_led_off = bnxt_dev_led_off_op,
3042         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3043         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3044         .rx_queue_count = bnxt_rx_queue_count_op,
3045         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3046         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3047         .rx_queue_start = bnxt_rx_queue_start,
3048         .rx_queue_stop = bnxt_rx_queue_stop,
3049         .tx_queue_start = bnxt_tx_queue_start,
3050         .tx_queue_stop = bnxt_tx_queue_stop,
3051         .filter_ctrl = bnxt_filter_ctrl_op,
3052         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3053         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3054         .get_eeprom           = bnxt_get_eeprom_op,
3055         .set_eeprom           = bnxt_set_eeprom_op,
3056         .timesync_enable      = bnxt_timesync_enable,
3057         .timesync_disable     = bnxt_timesync_disable,
3058         .timesync_read_time   = bnxt_timesync_read_time,
3059         .timesync_write_time   = bnxt_timesync_write_time,
3060         .timesync_adjust_time = bnxt_timesync_adjust_time,
3061         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3062         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3063 };
3064
3065 static bool bnxt_vf_pciid(uint16_t id)
3066 {
3067         if (id == BROADCOM_DEV_ID_57304_VF ||
3068             id == BROADCOM_DEV_ID_57406_VF ||
3069             id == BROADCOM_DEV_ID_5731X_VF ||
3070             id == BROADCOM_DEV_ID_5741X_VF ||
3071             id == BROADCOM_DEV_ID_57414_VF ||
3072             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3073             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3074                 return true;
3075         return false;
3076 }
3077
3078 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3079 {
3080         struct bnxt *bp = eth_dev->data->dev_private;
3081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3082         int rc;
3083
3084         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3085         if (!pci_dev->mem_resource[0].addr) {
3086                 PMD_DRV_LOG(ERR,
3087                         "Cannot find PCI device base address, aborting\n");
3088                 rc = -ENODEV;
3089                 goto init_err_disable;
3090         }
3091
3092         bp->eth_dev = eth_dev;
3093         bp->pdev = pci_dev;
3094
3095         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3096         if (!bp->bar0) {
3097                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3098                 rc = -ENOMEM;
3099                 goto init_err_release;
3100         }
3101
3102         if (!pci_dev->mem_resource[2].addr) {
3103                 PMD_DRV_LOG(ERR,
3104                             "Cannot find PCI device BAR 2 address, aborting\n");
3105                 rc = -ENODEV;
3106                 goto init_err_release;
3107         } else {
3108                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3109         }
3110
3111         return 0;
3112
3113 init_err_release:
3114         if (bp->bar0)
3115                 bp->bar0 = NULL;
3116         if (bp->doorbell_base)
3117                 bp->doorbell_base = NULL;
3118
3119 init_err_disable:
3120
3121         return rc;
3122 }
3123
3124 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3125
3126 #define ALLOW_FUNC(x)   \
3127         { \
3128                 typeof(x) arg = (x); \
3129                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3130                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3131         }
3132 static int
3133 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3134 {
3135         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3136         char mz_name[RTE_MEMZONE_NAMESIZE];
3137         const struct rte_memzone *mz = NULL;
3138         static int version_printed;
3139         uint32_t total_alloc_len;
3140         rte_iova_t mz_phys_addr;
3141         struct bnxt *bp;
3142         int rc;
3143
3144         if (version_printed++ == 0)
3145                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3146
3147         rte_eth_copy_pci_info(eth_dev, pci_dev);
3148
3149         bp = eth_dev->data->dev_private;
3150
3151         bp->dev_stopped = 1;
3152
3153         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3154                 goto skip_init;
3155
3156         if (bnxt_vf_pciid(pci_dev->id.device_id))
3157                 bp->flags |= BNXT_FLAG_VF;
3158
3159         rc = bnxt_init_board(eth_dev);
3160         if (rc) {
3161                 PMD_DRV_LOG(ERR,
3162                         "Board initialization failed rc: %x\n", rc);
3163                 goto error;
3164         }
3165 skip_init:
3166         eth_dev->dev_ops = &bnxt_dev_ops;
3167         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3168                 return 0;
3169         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3170         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3171
3172         if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3173                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3174                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3175                          pci_dev->addr.bus, pci_dev->addr.devid,
3176                          pci_dev->addr.function, "rx_port_stats");
3177                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3178                 mz = rte_memzone_lookup(mz_name);
3179                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3180                                 sizeof(struct rx_port_stats) + 512);
3181                 if (!mz) {
3182                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3183                                         SOCKET_ID_ANY,
3184                                         RTE_MEMZONE_2MB |
3185                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3186                                         RTE_MEMZONE_IOVA_CONTIG);
3187                         if (mz == NULL)
3188                                 return -ENOMEM;
3189                 }
3190                 memset(mz->addr, 0, mz->len);
3191                 mz_phys_addr = mz->iova;
3192                 if ((unsigned long)mz->addr == mz_phys_addr) {
3193                         PMD_DRV_LOG(WARNING,
3194                                 "Memzone physical address same as virtual.\n");
3195                         PMD_DRV_LOG(WARNING,
3196                                 "Using rte_mem_virt2iova()\n");
3197                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3198                         if (mz_phys_addr == 0) {
3199                                 PMD_DRV_LOG(ERR,
3200                                 "unable to map address to physical memory\n");
3201                                 return -ENOMEM;
3202                         }
3203                 }
3204
3205                 bp->rx_mem_zone = (const void *)mz;
3206                 bp->hw_rx_port_stats = mz->addr;
3207                 bp->hw_rx_port_stats_map = mz_phys_addr;
3208
3209                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3210                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3211                          pci_dev->addr.bus, pci_dev->addr.devid,
3212                          pci_dev->addr.function, "tx_port_stats");
3213                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3214                 mz = rte_memzone_lookup(mz_name);
3215                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3216                                 sizeof(struct tx_port_stats) + 512);
3217                 if (!mz) {
3218                         mz = rte_memzone_reserve(mz_name,
3219                                         total_alloc_len,
3220                                         SOCKET_ID_ANY,
3221                                         RTE_MEMZONE_2MB |
3222                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3223                                         RTE_MEMZONE_IOVA_CONTIG);
3224                         if (mz == NULL)
3225                                 return -ENOMEM;
3226                 }
3227                 memset(mz->addr, 0, mz->len);
3228                 mz_phys_addr = mz->iova;
3229                 if ((unsigned long)mz->addr == mz_phys_addr) {
3230                         PMD_DRV_LOG(WARNING,
3231                                 "Memzone physical address same as virtual.\n");
3232                         PMD_DRV_LOG(WARNING,
3233                                 "Using rte_mem_virt2iova()\n");
3234                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3235                         if (mz_phys_addr == 0) {
3236                                 PMD_DRV_LOG(ERR,
3237                                 "unable to map address to physical memory\n");
3238                                 return -ENOMEM;
3239                         }
3240                 }
3241
3242                 bp->tx_mem_zone = (const void *)mz;
3243                 bp->hw_tx_port_stats = mz->addr;
3244                 bp->hw_tx_port_stats_map = mz_phys_addr;
3245
3246                 bp->flags |= BNXT_FLAG_PORT_STATS;
3247         }
3248
3249         rc = bnxt_alloc_hwrm_resources(bp);
3250         if (rc) {
3251                 PMD_DRV_LOG(ERR,
3252                         "hwrm resource allocation failure rc: %x\n", rc);
3253                 goto error_free;
3254         }
3255         rc = bnxt_hwrm_ver_get(bp);
3256         if (rc)
3257                 goto error_free;
3258         rc = bnxt_hwrm_queue_qportcfg(bp);
3259         if (rc) {
3260                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3261                 goto error_free;
3262         }
3263
3264         rc = bnxt_hwrm_func_qcfg(bp);
3265         if (rc) {
3266                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3267                 goto error_free;
3268         }
3269
3270         /* Get the MAX capabilities for this function */
3271         rc = bnxt_hwrm_func_qcaps(bp);
3272         if (rc) {
3273                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3274                 goto error_free;
3275         }
3276         if (bp->max_tx_rings == 0) {
3277                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3278                 rc = -EBUSY;
3279                 goto error_free;
3280         }
3281         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3282                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3283         if (eth_dev->data->mac_addrs == NULL) {
3284                 PMD_DRV_LOG(ERR,
3285                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3286                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3287                 rc = -ENOMEM;
3288                 goto error_free;
3289         }
3290
3291         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3292                 PMD_DRV_LOG(ERR,
3293                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3294                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3295                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3296                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3297                 rc = -EINVAL;
3298                 goto error_free;
3299         }
3300         /* Copy the permanent MAC from the qcap response address now. */
3301         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3302         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3303
3304         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3305                 /* 1 ring is for default completion ring */
3306                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3307                 rc = -ENOSPC;
3308                 goto error_free;
3309         }
3310
3311         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3312                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3313         if (!bp->grp_info) {
3314                 PMD_DRV_LOG(ERR,
3315                         "Failed to alloc %zu bytes to store group info table\n",
3316                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3317                 rc = -ENOMEM;
3318                 goto error_free;
3319         }
3320
3321         /* Forward all requests if firmware is new enough */
3322         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3323             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3324             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3325                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3326         } else {
3327                 PMD_DRV_LOG(WARNING,
3328                         "Firmware too old for VF mailbox functionality\n");
3329                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3330         }
3331
3332         /*
3333          * The following are used for driver cleanup.  If we disallow these,
3334          * VF drivers can't clean up cleanly.
3335          */
3336         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3337         ALLOW_FUNC(HWRM_VNIC_FREE);
3338         ALLOW_FUNC(HWRM_RING_FREE);
3339         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3340         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3341         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3342         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3343         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3344         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3345         rc = bnxt_hwrm_func_driver_register(bp);
3346         if (rc) {
3347                 PMD_DRV_LOG(ERR,
3348                         "Failed to register driver");
3349                 rc = -EBUSY;
3350                 goto error_free;
3351         }
3352
3353         PMD_DRV_LOG(INFO,
3354                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3355                 pci_dev->mem_resource[0].phys_addr,
3356                 pci_dev->mem_resource[0].addr);
3357
3358         rc = bnxt_hwrm_func_reset(bp);
3359         if (rc) {
3360                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3361                 rc = -EIO;
3362                 goto error_free;
3363         }
3364
3365         if (BNXT_PF(bp)) {
3366                 //if (bp->pf.active_vfs) {
3367                         // TODO: Deallocate VF resources?
3368                 //}
3369                 if (bp->pdev->max_vfs) {
3370                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3371                         if (rc) {
3372                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3373                                 goto error_free;
3374                         }
3375                 } else {
3376                         rc = bnxt_hwrm_allocate_pf_only(bp);
3377                         if (rc) {
3378                                 PMD_DRV_LOG(ERR,
3379                                         "Failed to allocate PF resources\n");
3380                                 goto error_free;
3381                         }
3382                 }
3383         }
3384
3385         bnxt_hwrm_port_led_qcaps(bp);
3386
3387         rc = bnxt_setup_int(bp);
3388         if (rc)
3389                 goto error_free;
3390
3391         rc = bnxt_alloc_mem(bp);
3392         if (rc)
3393                 goto error_free_int;
3394
3395         rc = bnxt_request_int(bp);
3396         if (rc)
3397                 goto error_free_int;
3398
3399         rc = bnxt_alloc_def_cp_ring(bp);
3400         if (rc)
3401                 goto error_free_int;
3402
3403         bnxt_enable_int(bp);
3404         bnxt_init_nic(bp);
3405
3406         return 0;
3407
3408 error_free_int:
3409         bnxt_disable_int(bp);
3410         bnxt_free_def_cp_ring(bp);
3411         bnxt_hwrm_func_buf_unrgtr(bp);
3412         bnxt_free_int(bp);
3413         bnxt_free_mem(bp);
3414 error_free:
3415         bnxt_dev_uninit(eth_dev);
3416 error:
3417         return rc;
3418 }
3419
3420 static int
3421 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3422         struct bnxt *bp = eth_dev->data->dev_private;
3423         int rc;
3424
3425         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3426                 return -EPERM;
3427
3428         bnxt_disable_int(bp);
3429         bnxt_free_int(bp);
3430         bnxt_free_mem(bp);
3431         if (eth_dev->data->mac_addrs != NULL) {
3432                 rte_free(eth_dev->data->mac_addrs);
3433                 eth_dev->data->mac_addrs = NULL;
3434         }
3435         if (bp->grp_info != NULL) {
3436                 rte_free(bp->grp_info);
3437                 bp->grp_info = NULL;
3438         }
3439         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3440         bnxt_free_hwrm_resources(bp);
3441         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3442         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3443         if (bp->dev_stopped == 0)
3444                 bnxt_dev_close_op(eth_dev);
3445         if (bp->pf.vf_info)
3446                 rte_free(bp->pf.vf_info);
3447         eth_dev->dev_ops = NULL;
3448         eth_dev->rx_pkt_burst = NULL;
3449         eth_dev->tx_pkt_burst = NULL;
3450
3451         return rc;
3452 }
3453
3454 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3455         struct rte_pci_device *pci_dev)
3456 {
3457         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3458                 bnxt_dev_init);
3459 }
3460
3461 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3462 {
3463         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3464 }
3465
3466 static struct rte_pci_driver bnxt_rte_pmd = {
3467         .id_table = bnxt_pci_id_map,
3468         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3469                 RTE_PCI_DRV_INTR_LSC,
3470         .probe = bnxt_pci_probe,
3471         .remove = bnxt_pci_remove,
3472 };
3473
3474 static bool
3475 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3476 {
3477         if (strcmp(dev->device->driver->name, drv->driver.name))
3478                 return false;
3479
3480         return true;
3481 }
3482
3483 bool is_bnxt_supported(struct rte_eth_dev *dev)
3484 {
3485         return is_device_supported(dev, &bnxt_rte_pmd);
3486 }
3487
3488 RTE_INIT(bnxt_init_log);
3489 static void
3490 bnxt_init_log(void)
3491 {
3492         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3493         if (bnxt_logtype_driver >= 0)
3494                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3495 }
3496
3497 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3498 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3499 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");