drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { .vendor_id = 0, /* sentinel */ },
  87 };
  88
  89 #define BNXT_ETH_RSS_SUPPORT (  \
  90         ETH_RSS_IPV4 |          \
  91         ETH_RSS_NONFRAG_IPV4_TCP |      \
  92         ETH_RSS_NONFRAG_IPV4_UDP |      \
  93         ETH_RSS_IPV6 |          \
  94         ETH_RSS_NONFRAG_IPV6_TCP |      \
  95         ETH_RSS_NONFRAG_IPV6_UDP)
  96
  97 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
  98                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
  99                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 100                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 101                                      DEV_TX_OFFLOAD_TCP_TSO | \
 102                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 103                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 104                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 105                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 106                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 107                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 108                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 109
 110 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 111                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 112                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 113                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 114                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 115                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 116                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 117                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 118                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 119                                      DEV_RX_OFFLOAD_TCP_LRO | \
 120                                      DEV_RX_OFFLOAD_SCATTER)
 121
 122 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 123 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 124 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 125 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 126 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 127 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 128 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 129
 130 int is_bnxt_in_error(struct bnxt *bp)
 131 {
 132         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 133                 return -EIO;
 134         if (bp->flags & BNXT_FLAG_FW_RESET)
 135                 return -EBUSY;
 136
 137         return 0;
 138 }
 139
 140 /***********************/
 141
 142 /*
 143  * High level utility functions
 144  */
 145
 146 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 147 {
 148         if (!BNXT_CHIP_THOR(bp))
 149                 return 1;
 150
 151         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 152                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 153                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 154 }
 155
 156 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 157 {
 158         if (!BNXT_CHIP_THOR(bp))
 159                 return HW_HASH_INDEX_SIZE;
 160
 161         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 162 }
 163
 164 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 165 {
 166         bnxt_free_filter_mem(bp);
 167         bnxt_free_vnic_attributes(bp);
 168         bnxt_free_vnic_mem(bp);
 169
 170         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 171          * If the number of rings change across fw update,
 172          * we don't have much choice except to warn the user.
 173          */
 174         if (!reconfig) {
 175                 bnxt_free_stats(bp);
 176                 bnxt_free_tx_rings(bp);
 177                 bnxt_free_rx_rings(bp);
 178         }
 179         bnxt_free_async_cp_ring(bp);
 180         bnxt_free_rxtx_nq_ring(bp);
 181 }
 182
 183 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 184 {
 185         int rc;
 186
 187         rc = bnxt_alloc_ring_grps(bp);
 188         if (rc)
 189                 goto alloc_mem_err;
 190
 191         rc = bnxt_alloc_async_ring_struct(bp);
 192         if (rc)
 193                 goto alloc_mem_err;
 194
 195         rc = bnxt_alloc_vnic_mem(bp);
 196         if (rc)
 197                 goto alloc_mem_err;
 198
 199         rc = bnxt_alloc_vnic_attributes(bp);
 200         if (rc)
 201                 goto alloc_mem_err;
 202
 203         rc = bnxt_alloc_filter_mem(bp);
 204         if (rc)
 205                 goto alloc_mem_err;
 206
 207         rc = bnxt_alloc_async_cp_ring(bp);
 208         if (rc)
 209                 goto alloc_mem_err;
 210
 211         rc = bnxt_alloc_rxtx_nq_ring(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         return 0;
 216
 217 alloc_mem_err:
 218         bnxt_free_mem(bp, reconfig);
 219         return rc;
 220 }
 221
 222 static int bnxt_init_chip(struct bnxt *bp)
 223 {
 224         struct bnxt_rx_queue *rxq;
 225         struct rte_eth_link new;
 226         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 227         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 229         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 230         uint32_t intr_vector = 0;
 231         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 232         uint32_t vec = BNXT_MISC_VEC_ID;
 233         unsigned int i, j;
 234         int rc;
 235
 236         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 237                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 238                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 239                 bp->flags |= BNXT_FLAG_JUMBO;
 240         } else {
 241                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 242                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 243                 bp->flags &= ~BNXT_FLAG_JUMBO;
 244         }
 245
 246         /* THOR does not support ring groups.
 247          * But we will use the array to save RSS context IDs.
 248          */
 249         if (BNXT_CHIP_THOR(bp))
 250                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 251
 252         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 253         if (rc) {
 254                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 255                 goto err_out;
 256         }
 257
 258         rc = bnxt_alloc_hwrm_rings(bp);
 259         if (rc) {
 260                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 261                 goto err_out;
 262         }
 263
 264         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 265         if (rc) {
 266                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 267                 goto err_out;
 268         }
 269
 270         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 271                 goto skip_cosq_cfg;
 272
 273         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 274                 if (bp->rx_cos_queue[i].id != 0xff) {
 275                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 276
 277                         if (!vnic) {
 278                                 PMD_DRV_LOG(ERR,
 279                                             "Num pools more than FW profile\n");
 280                                 rc = -EINVAL;
 281                                 goto err_out;
 282                         }
 283                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 284                         bp->rx_cosq_cnt++;
 285                 }
 286         }
 287
 288 skip_cosq_cfg:
 289         rc = bnxt_mq_rx_configure(bp);
 290         if (rc) {
 291                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 292                 goto err_out;
 293         }
 294
 295         /* VNIC configuration */
 296         for (i = 0; i < bp->nr_vnics; i++) {
 297                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 298                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 299
 300                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 301                 if (rc)
 302                         goto err_out;
 303
 304                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 305                             i, vnic, vnic->fw_grp_ids);
 306
 307                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 308                 if (rc) {
 309                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 310                                 i, rc);
 311                         goto err_out;
 312                 }
 313
 314                 /* Alloc RSS context only if RSS mode is enabled */
 315                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 316                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 317
 318                         rc = 0;
 319                         for (j = 0; j < nr_ctxs; j++) {
 320                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 321                                 if (rc)
 322                                         break;
 323                         }
 324                         if (rc) {
 325                                 PMD_DRV_LOG(ERR,
 326                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 327                                   i, j, rc);
 328                                 goto err_out;
 329                         }
 330                         vnic->num_lb_ctxts = nr_ctxs;
 331                 }
 332
 333                 /*
 334                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 335                  * setting is not available at this time, it will not be
 336                  * configured correctly in the CFA.
 337                  */
 338                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 339                         vnic->vlan_strip = true;
 340                 else
 341                         vnic->vlan_strip = false;
 342
 343                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 344                 if (rc) {
 345                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 346                                 i, rc);
 347                         goto err_out;
 348                 }
 349
 350                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 351                 if (rc) {
 352                         PMD_DRV_LOG(ERR,
 353                                 "HWRM vnic %d filter failure rc: %x\n",
 354                                 i, rc);
 355                         goto err_out;
 356                 }
 357
 358                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 359                         rxq = bp->eth_dev->data->rx_queues[j];
 360
 361                         PMD_DRV_LOG(DEBUG,
 362                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 363                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 364
 365                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 366                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 367                 }
 368
 369                 rc = bnxt_vnic_rss_configure(bp, vnic);
 370                 if (rc) {
 371                         PMD_DRV_LOG(ERR,
 372                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 373                         goto err_out;
 374                 }
 375
 376                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 377
 378                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 379                     DEV_RX_OFFLOAD_TCP_LRO)
 380                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 381                 else
 382                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 383         }
 384         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 385         if (rc) {
 386                 PMD_DRV_LOG(ERR,
 387                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 388                 goto err_out;
 389         }
 390
 391         /* check and configure queue intr-vector mapping */
 392         if ((rte_intr_cap_multiple(intr_handle) ||
 393              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 394             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 395                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 396                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 397                 if (intr_vector > bp->rx_cp_nr_rings) {
 398                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 399                                         bp->rx_cp_nr_rings);
 400                         return -ENOTSUP;
 401                 }
 402                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 403                 if (rc)
 404                         return rc;
 405         }
 406
 407         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 408                 intr_handle->intr_vec =
 409                         rte_zmalloc("intr_vec",
 410                                     bp->eth_dev->data->nb_rx_queues *
 411                                     sizeof(int), 0);
 412                 if (intr_handle->intr_vec == NULL) {
 413                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 414                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 415                         rc = -ENOMEM;
 416                         goto err_disable;
 417                 }
 418                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 419                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 420                          intr_handle->intr_vec, intr_handle->nb_efd,
 421                         intr_handle->max_intr);
 422                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 423                      queue_id++) {
 424                         intr_handle->intr_vec[queue_id] =
 425                                                         vec + BNXT_RX_VEC_START;
 426                         if (vec < base + intr_handle->nb_efd - 1)
 427                                 vec++;
 428                 }
 429         }
 430
 431         /* enable uio/vfio intr/eventfd mapping */
 432         rc = rte_intr_enable(intr_handle);
 433         if (rc)
 434                 goto err_free;
 435
 436         rc = bnxt_get_hwrm_link_config(bp, &new);
 437         if (rc) {
 438                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 439                 goto err_free;
 440         }
 441
 442         if (!bp->link_info.link_up) {
 443                 rc = bnxt_set_hwrm_link_config(bp, true);
 444                 if (rc) {
 445                         PMD_DRV_LOG(ERR,
 446                                 "HWRM link config failure rc: %x\n", rc);
 447                         goto err_free;
 448                 }
 449         }
 450         bnxt_print_link_info(bp->eth_dev);
 451
 452         return 0;
 453
 454 err_free:
 455         rte_free(intr_handle->intr_vec);
 456 err_disable:
 457         rte_intr_efd_disable(intr_handle);
 458 err_out:
 459         /* Some of the error status returned by FW may not be from errno.h */
 460         if (rc > 0)
 461                 rc = -EIO;
 462
 463         return rc;
 464 }
 465
 466 static int bnxt_shutdown_nic(struct bnxt *bp)
 467 {
 468         bnxt_free_all_hwrm_resources(bp);
 469         bnxt_free_all_filters(bp);
 470         bnxt_free_all_vnics(bp);
 471         return 0;
 472 }
 473
 474 static int bnxt_init_nic(struct bnxt *bp)
 475 {
 476         int rc;
 477
 478         if (BNXT_HAS_RING_GRPS(bp)) {
 479                 rc = bnxt_init_ring_grps(bp);
 480                 if (rc)
 481                         return rc;
 482         }
 483
 484         bnxt_init_vnics(bp);
 485         bnxt_init_filters(bp);
 486
 487         return 0;
 488 }
 489
 490 /*
 491  * Device configuration and status function
 492  */
 493
 494 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 495                                 struct rte_eth_dev_info *dev_info)
 496 {
 497         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 498         struct bnxt *bp = eth_dev->data->dev_private;
 499         uint16_t max_vnics, i, j, vpool, vrxq;
 500         unsigned int max_rx_rings;
 501         int rc;
 502
 503         rc = is_bnxt_in_error(bp);
 504         if (rc)
 505                 return rc;
 506
 507         /* MAC Specifics */
 508         dev_info->max_mac_addrs = bp->max_l2_ctx;
 509         dev_info->max_hash_mac_addrs = 0;
 510
 511         /* PF/VF specifics */
 512         if (BNXT_PF(bp))
 513                 dev_info->max_vfs = pdev->max_vfs;
 514
 515         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 516         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 517         dev_info->max_rx_queues = max_rx_rings;
 518         dev_info->max_tx_queues = max_rx_rings;
 519         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 520         dev_info->hash_key_size = 40;
 521         max_vnics = bp->max_vnics;
 522
 523         /* MTU specifics */
 524         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 525         dev_info->max_mtu = BNXT_MAX_MTU;
 526
 527         /* Fast path specifics */
 528         dev_info->min_rx_bufsize = 1;
 529         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 530
 531         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 532         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 533                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 534         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 535         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 536
 537         /* *INDENT-OFF* */
 538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 539                 .rx_thresh = {
 540                         .pthresh = 8,
 541                         .hthresh = 8,
 542                         .wthresh = 0,
 543                 },
 544                 .rx_free_thresh = 32,
 545                 /* If no descriptors available, pkts are dropped by default */
 546                 .rx_drop_en = 1,
 547         };
 548
 549         dev_info->default_txconf = (struct rte_eth_txconf) {
 550                 .tx_thresh = {
 551                         .pthresh = 32,
 552                         .hthresh = 0,
 553                         .wthresh = 0,
 554                 },
 555                 .tx_free_thresh = 32,
 556                 .tx_rs_thresh = 32,
 557         };
 558         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 559
 560         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 561         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 562         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 563         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 564         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 565
 566         /* *INDENT-ON* */
 567
 568         /*
 569          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 570          *       need further investigation.
 571          */
 572
 573         /* VMDq resources */
 574         vpool = 64; /* ETH_64_POOLS */
 575         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 576         for (i = 0; i < 4; vpool >>= 1, i++) {
 577                 if (max_vnics > vpool) {
 578                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 579                                 if (dev_info->max_rx_queues > vrxq) {
 580                                         if (vpool > vrxq)
 581                                                 vpool = vrxq;
 582                                         goto found;
 583                                 }
 584                         }
 585                         /* Not enough resources to support VMDq */
 586                         break;
 587                 }
 588         }
 589         /* Not enough resources to support VMDq */
 590         vpool = 0;
 591         vrxq = 0;
 592 found:
 593         dev_info->max_vmdq_pools = vpool;
 594         dev_info->vmdq_queue_num = vrxq;
 595
 596         dev_info->vmdq_pool_base = 0;
 597         dev_info->vmdq_queue_base = 0;
 598
 599         return 0;
 600 }
 601
 602 /* Configure the device based on the configuration provided */
 603 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 604 {
 605         struct bnxt *bp = eth_dev->data->dev_private;
 606         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 607         int rc;
 608
 609         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 610         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 611         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 612         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 613
 614         rc = is_bnxt_in_error(bp);
 615         if (rc)
 616                 return rc;
 617
 618         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 619                 rc = bnxt_hwrm_check_vf_rings(bp);
 620                 if (rc) {
 621                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 622                         return -ENOSPC;
 623                 }
 624
 625                 /* If a resource has already been allocated - in this case
 626                  * it is the async completion ring, free it. Reallocate it after
 627                  * resource reservation. This will ensure the resource counts
 628                  * are calculated correctly.
 629                  */
 630
 631                 pthread_mutex_lock(&bp->def_cp_lock);
 632
 633                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 634                         bnxt_disable_int(bp);
 635                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 636                 }
 637
 638                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 639                 if (rc) {
 640                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 641                         pthread_mutex_unlock(&bp->def_cp_lock);
 642                         return -ENOSPC;
 643                 }
 644
 645                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 646                         rc = bnxt_alloc_async_cp_ring(bp);
 647                         if (rc) {
 648                                 pthread_mutex_unlock(&bp->def_cp_lock);
 649                                 return rc;
 650                         }
 651                         bnxt_enable_int(bp);
 652                 }
 653
 654                 pthread_mutex_unlock(&bp->def_cp_lock);
 655         } else {
 656                 /* legacy driver needs to get updated values */
 657                 rc = bnxt_hwrm_func_qcaps(bp);
 658                 if (rc) {
 659                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 660                         return rc;
 661                 }
 662         }
 663
 664         /* Inherit new configurations */
 665         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 666             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 667             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 668                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 669             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 670             bp->max_stat_ctx)
 671                 goto resource_error;
 672
 673         if (BNXT_HAS_RING_GRPS(bp) &&
 674             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 675                 goto resource_error;
 676
 677         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 678             bp->max_vnics < eth_dev->data->nb_rx_queues)
 679                 goto resource_error;
 680
 681         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 682         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 683
 684         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 685                 eth_dev->data->mtu =
 686                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 687                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 688                         BNXT_NUM_VLANS;
 689                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 690         }
 691         return 0;
 692
 693 resource_error:
 694         PMD_DRV_LOG(ERR,
 695                     "Insufficient resources to support requested config\n");
 696         PMD_DRV_LOG(ERR,
 697                     "Num Queues Requested: Tx %d, Rx %d\n",
 698                     eth_dev->data->nb_tx_queues,
 699                     eth_dev->data->nb_rx_queues);
 700         PMD_DRV_LOG(ERR,
 701                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 702                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 703                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 704         return -ENOSPC;
 705 }
 706
 707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 708 {
 709         struct rte_eth_link *link = &eth_dev->data->dev_link;
 710
 711         if (link->link_status)
 712                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 713                         eth_dev->data->port_id,
 714                         (uint32_t)link->link_speed,
 715                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 716                         ("full-duplex") : ("half-duplex\n"));
 717         else
 718                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 719                         eth_dev->data->port_id);
 720 }
 721
 722 /*
 723  * Determine whether the current configuration requires support for scattered
 724  * receive; return 1 if scattered receive is required and 0 if not.
 725  */
 726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 727 {
 728         uint16_t buf_size;
 729         int i;
 730
 731         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 732                 return 1;
 733
 734         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 735                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 736
 737                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 738                                       RTE_PKTMBUF_HEADROOM);
 739                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 740                         return 1;
 741         }
 742         return 0;
 743 }
 744
 745 static eth_rx_burst_t
 746 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 747 {
 748 #ifdef RTE_ARCH_X86
 749 #ifndef RTE_LIBRTE_IEEE1588
 750         /*
 751          * Vector mode receive can be enabled only if scatter rx is not
 752          * in use and rx offloads are limited to VLAN stripping and
 753          * CRC stripping.
 754          */
 755         if (!eth_dev->data->scattered_rx &&
 756             !(eth_dev->data->dev_conf.rxmode.offloads &
 757               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 758                 DEV_RX_OFFLOAD_KEEP_CRC |
 759                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 760                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 761                 DEV_RX_OFFLOAD_UDP_CKSUM |
 762                 DEV_RX_OFFLOAD_TCP_CKSUM |
 763                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 764                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 765                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 766                             eth_dev->data->port_id);
 767                 return bnxt_recv_pkts_vec;
 768         }
 769         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 770                     eth_dev->data->port_id);
 771         PMD_DRV_LOG(INFO,
 772                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 773                     eth_dev->data->port_id,
 774                     eth_dev->data->scattered_rx,
 775                     eth_dev->data->dev_conf.rxmode.offloads);
 776 #endif
 777 #endif
 778         return bnxt_recv_pkts;
 779 }
 780
 781 static eth_tx_burst_t
 782 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 783 {
 784 #ifdef RTE_ARCH_X86
 785 #ifndef RTE_LIBRTE_IEEE1588
 786         /*
 787          * Vector mode transmit can be enabled only if not using scatter rx
 788          * or tx offloads.
 789          */
 790         if (!eth_dev->data->scattered_rx &&
 791             !eth_dev->data->dev_conf.txmode.offloads) {
 792                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 793                             eth_dev->data->port_id);
 794                 return bnxt_xmit_pkts_vec;
 795         }
 796         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 797                     eth_dev->data->port_id);
 798         PMD_DRV_LOG(INFO,
 799                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 800                     eth_dev->data->port_id,
 801                     eth_dev->data->scattered_rx,
 802                     eth_dev->data->dev_conf.txmode.offloads);
 803 #endif
 804 #endif
 805         return bnxt_xmit_pkts;
 806 }
 807
 808 static int bnxt_handle_if_change_status(struct bnxt *bp)
 809 {
 810         int rc;
 811
 812         /* Since fw has undergone a reset and lost all contexts,
 813          * set fatal flag to not issue hwrm during cleanup
 814          */
 815         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 816         bnxt_uninit_resources(bp, true);
 817
 818         /* clear fatal flag so that re-init happens */
 819         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 820         rc = bnxt_init_resources(bp, true);
 821
 822         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 823
 824         return rc;
 825 }
 826
 827 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 828 {
 829         struct bnxt *bp = eth_dev->data->dev_private;
 830         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 831         int vlan_mask = 0;
 832         int rc;
 833
 834         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 835                 PMD_DRV_LOG(ERR,
 836                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 837                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 838         }
 839
 840         rc = bnxt_hwrm_if_change(bp, 1);
 841         if (!rc) {
 842                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 843                         rc = bnxt_handle_if_change_status(bp);
 844                         if (rc)
 845                                 return rc;
 846                 }
 847         }
 848         bnxt_enable_int(bp);
 849
 850         rc = bnxt_init_chip(bp);
 851         if (rc)
 852                 goto error;
 853
 854         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 855
 856         bnxt_link_update_op(eth_dev, 1);
 857
 858         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 859                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 860         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 861                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 862         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 863         if (rc)
 864                 goto error;
 865
 866         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 867         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 868
 869         bp->flags |= BNXT_FLAG_INIT_DONE;
 870         eth_dev->data->dev_started = 1;
 871         bp->dev_stopped = 0;
 872         pthread_mutex_lock(&bp->def_cp_lock);
 873         bnxt_schedule_fw_health_check(bp);
 874         pthread_mutex_unlock(&bp->def_cp_lock);
 875         return 0;
 876
 877 error:
 878         bnxt_hwrm_if_change(bp, 0);
 879         bnxt_shutdown_nic(bp);
 880         bnxt_free_tx_mbufs(bp);
 881         bnxt_free_rx_mbufs(bp);
 882         return rc;
 883 }
 884
 885 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 886 {
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         int rc = 0;
 889
 890         if (!bp->link_info.link_up)
 891                 rc = bnxt_set_hwrm_link_config(bp, true);
 892         if (!rc)
 893                 eth_dev->data->dev_link.link_status = 1;
 894
 895         bnxt_print_link_info(eth_dev);
 896         return rc;
 897 }
 898
 899 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 900 {
 901         struct bnxt *bp = eth_dev->data->dev_private;
 902
 903         eth_dev->data->dev_link.link_status = 0;
 904         bnxt_set_hwrm_link_config(bp, false);
 905         bp->link_info.link_up = 0;
 906
 907         return 0;
 908 }
 909
 910 /* Unload the driver, release resources */
 911 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 912 {
 913         struct bnxt *bp = eth_dev->data->dev_private;
 914         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 915         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 916
 917         eth_dev->data->dev_started = 0;
 918         /* Prevent crashes when queues are still in use */
 919         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 920         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 921
 922         bnxt_disable_int(bp);
 923
 924         /* disable uio/vfio intr/eventfd mapping */
 925         rte_intr_disable(intr_handle);
 926
 927         bnxt_cancel_fw_health_check(bp);
 928
 929         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 930         if (bp->eth_dev->data->dev_started) {
 931                 /* TBD: STOP HW queues DMA */
 932                 eth_dev->data->dev_link.link_status = 0;
 933         }
 934         bnxt_dev_set_link_down_op(eth_dev);
 935
 936         /* Wait for link to be reset and the async notification to process.
 937          * During reset recovery, there is no need to wait
 938          */
 939         if (!is_bnxt_in_error(bp))
 940                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 941
 942         /* Clean queue intr-vector mapping */
 943         rte_intr_efd_disable(intr_handle);
 944         if (intr_handle->intr_vec != NULL) {
 945                 rte_free(intr_handle->intr_vec);
 946                 intr_handle->intr_vec = NULL;
 947         }
 948
 949         bnxt_hwrm_port_clr_stats(bp);
 950         bnxt_free_tx_mbufs(bp);
 951         bnxt_free_rx_mbufs(bp);
 952         /* Process any remaining notifications in default completion queue */
 953         bnxt_int_handler(eth_dev);
 954         bnxt_shutdown_nic(bp);
 955         bnxt_hwrm_if_change(bp, 0);
 956         bp->dev_stopped = 1;
 957 }
 958
 959 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 960 {
 961         struct bnxt *bp = eth_dev->data->dev_private;
 962
 963         if (bp->dev_stopped == 0)
 964                 bnxt_dev_stop_op(eth_dev);
 965
 966         if (eth_dev->data->mac_addrs != NULL) {
 967                 rte_free(eth_dev->data->mac_addrs);
 968                 eth_dev->data->mac_addrs = NULL;
 969         }
 970         if (bp->grp_info != NULL) {
 971                 rte_free(bp->grp_info);
 972                 bp->grp_info = NULL;
 973         }
 974
 975         bnxt_dev_uninit(eth_dev);
 976 }
 977
 978 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 979                                     uint32_t index)
 980 {
 981         struct bnxt *bp = eth_dev->data->dev_private;
 982         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 983         struct bnxt_vnic_info *vnic;
 984         struct bnxt_filter_info *filter, *temp_filter;
 985         uint32_t i;
 986
 987         if (is_bnxt_in_error(bp))
 988                 return;
 989
 990         /*
 991          * Loop through all VNICs from the specified filter flow pools to
 992          * remove the corresponding MAC addr filter
 993          */
 994         for (i = 0; i < bp->nr_vnics; i++) {
 995                 if (!(pool_mask & (1ULL << i)))
 996                         continue;
 997
 998                 vnic = &bp->vnic_info[i];
 999                 filter = STAILQ_FIRST(&vnic->filter);
1000                 while (filter) {
1001                         temp_filter = STAILQ_NEXT(filter, next);
1002                         if (filter->mac_index == index) {
1003                                 STAILQ_REMOVE(&vnic->filter, filter,
1004                                                 bnxt_filter_info, next);
1005                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1006                                 filter->mac_index = INVALID_MAC_INDEX;
1007                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1008                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1009                                                    filter, next);
1010                         }
1011                         filter = temp_filter;
1012                 }
1013         }
1014 }
1015
1016 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1017                                struct rte_ether_addr *mac_addr, uint32_t index)
1018 {
1019         struct bnxt_filter_info *filter;
1020         int rc = 0;
1021
1022         filter = STAILQ_FIRST(&vnic->filter);
1023         /* During bnxt_mac_addr_add_op, default MAC is
1024          * already programmed, so skip it. But, when
1025          * hw-vlan-filter is turned OFF from ON, default
1026          * MAC filter should be restored
1027          */
1028         if (index == 0 && filter->dflt)
1029                 return 0;
1030
1031         filter = bnxt_alloc_filter(bp);
1032         if (!filter) {
1033                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1034                 return -ENODEV;
1035         }
1036
1037         filter->mac_index = index;
1038         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1039          * if the MAC that's been programmed now is a different one, then,
1040          * copy that addr to filter->l2_addr
1041          */
1042         if (mac_addr)
1043                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1044         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1045
1046         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1047         if (!rc) {
1048                 if (filter->mac_index == 0) {
1049                         filter->dflt = true;
1050                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1051                 } else {
1052                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1053                 }
1054         } else {
1055                 filter->mac_index = INVALID_MAC_INDEX;
1056                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1057                 bnxt_free_filter(bp, filter);
1058         }
1059
1060         return rc;
1061 }
1062
1063 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1064                                 struct rte_ether_addr *mac_addr,
1065                                 uint32_t index, uint32_t pool)
1066 {
1067         struct bnxt *bp = eth_dev->data->dev_private;
1068         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1069         struct bnxt_filter_info *filter;
1070         int rc = 0;
1071
1072         rc = is_bnxt_in_error(bp);
1073         if (rc)
1074                 return rc;
1075
1076         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1077                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1078                 return -ENOTSUP;
1079         }
1080
1081         if (!vnic) {
1082                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1083                 return -EINVAL;
1084         }
1085         /* Attach requested MAC address to the new l2_filter */
1086         STAILQ_FOREACH(filter, &vnic->filter, next) {
1087                 if (filter->mac_index == index) {
1088                         PMD_DRV_LOG(ERR,
1089                                 "MAC addr already existed for pool %d\n", pool);
1090                         return 0;
1091                 }
1092         }
1093
1094         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1095
1096         return rc;
1097 }
1098
1099 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1100 {
1101         int rc = 0;
1102         struct bnxt *bp = eth_dev->data->dev_private;
1103         struct rte_eth_link new;
1104         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1105
1106         rc = is_bnxt_in_error(bp);
1107         if (rc)
1108                 return rc;
1109
1110         memset(&new, 0, sizeof(new));
1111         do {
1112                 /* Retrieve link info from hardware */
1113                 rc = bnxt_get_hwrm_link_config(bp, &new);
1114                 if (rc) {
1115                         new.link_speed = ETH_LINK_SPEED_100M;
1116                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1117                         PMD_DRV_LOG(ERR,
1118                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1119                         goto out;
1120                 }
1121
1122                 if (!wait_to_complete || new.link_status)
1123                         break;
1124
1125                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1126         } while (cnt--);
1127
1128 out:
1129         /* Timed out or success */
1130         if (new.link_status != eth_dev->data->dev_link.link_status ||
1131         new.link_speed != eth_dev->data->dev_link.link_speed) {
1132                 rte_eth_linkstatus_set(eth_dev, &new);
1133
1134                 _rte_eth_dev_callback_process(eth_dev,
1135                                               RTE_ETH_EVENT_INTR_LSC,
1136                                               NULL);
1137
1138                 bnxt_print_link_info(eth_dev);
1139         }
1140
1141         return rc;
1142 }
1143
1144 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1145 {
1146         struct bnxt *bp = eth_dev->data->dev_private;
1147         struct bnxt_vnic_info *vnic;
1148         uint32_t old_flags;
1149         int rc;
1150
1151         rc = is_bnxt_in_error(bp);
1152         if (rc)
1153                 return rc;
1154
1155         if (bp->vnic_info == NULL)
1156                 return 0;
1157
1158         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1159
1160         old_flags = vnic->flags;
1161         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1162         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1163         if (rc != 0)
1164                 vnic->flags = old_flags;
1165
1166         return rc;
1167 }
1168
1169 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1170 {
1171         struct bnxt *bp = eth_dev->data->dev_private;
1172         struct bnxt_vnic_info *vnic;
1173         uint32_t old_flags;
1174         int rc;
1175
1176         rc = is_bnxt_in_error(bp);
1177         if (rc)
1178                 return rc;
1179
1180         if (bp->vnic_info == NULL)
1181                 return 0;
1182
1183         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1184
1185         old_flags = vnic->flags;
1186         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1187         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1188         if (rc != 0)
1189                 vnic->flags = old_flags;
1190
1191         return rc;
1192 }
1193
1194 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1195 {
1196         struct bnxt *bp = eth_dev->data->dev_private;
1197         struct bnxt_vnic_info *vnic;
1198         uint32_t old_flags;
1199         int rc;
1200
1201         rc = is_bnxt_in_error(bp);
1202         if (rc)
1203                 return rc;
1204
1205         if (bp->vnic_info == NULL)
1206                 return 0;
1207
1208         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1209
1210         old_flags = vnic->flags;
1211         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1212         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1213         if (rc != 0)
1214                 vnic->flags = old_flags;
1215
1216         return rc;
1217 }
1218
1219 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1220 {
1221         struct bnxt *bp = eth_dev->data->dev_private;
1222         struct bnxt_vnic_info *vnic;
1223         uint32_t old_flags;
1224         int rc;
1225
1226         rc = is_bnxt_in_error(bp);
1227         if (rc)
1228                 return rc;
1229
1230         if (bp->vnic_info == NULL)
1231                 return 0;
1232
1233         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1234
1235         old_flags = vnic->flags;
1236         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1237         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1238         if (rc != 0)
1239                 vnic->flags = old_flags;
1240
1241         return rc;
1242 }
1243
1244 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1245 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1246 {
1247         if (qid >= bp->rx_nr_rings)
1248                 return NULL;
1249
1250         return bp->eth_dev->data->rx_queues[qid];
1251 }
1252
1253 /* Return rxq corresponding to a given rss table ring/group ID. */
1254 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1255 {
1256         struct bnxt_rx_queue *rxq;
1257         unsigned int i;
1258
1259         if (!BNXT_HAS_RING_GRPS(bp)) {
1260                 for (i = 0; i < bp->rx_nr_rings; i++) {
1261                         rxq = bp->eth_dev->data->rx_queues[i];
1262                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1263                                 return rxq->index;
1264                 }
1265         } else {
1266                 for (i = 0; i < bp->rx_nr_rings; i++) {
1267                         if (bp->grp_info[i].fw_grp_id == fwr)
1268                                 return i;
1269                 }
1270         }
1271
1272         return INVALID_HW_RING_ID;
1273 }
1274
1275 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1276                             struct rte_eth_rss_reta_entry64 *reta_conf,
1277                             uint16_t reta_size)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1281         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1282         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1283         uint16_t idx, sft;
1284         int i, rc;
1285
1286         rc = is_bnxt_in_error(bp);
1287         if (rc)
1288                 return rc;
1289
1290         if (!vnic->rss_table)
1291                 return -EINVAL;
1292
1293         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1294                 return -EINVAL;
1295
1296         if (reta_size != tbl_size) {
1297                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1298                         "(%d) must equal the size supported by the hardware "
1299                         "(%d)\n", reta_size, tbl_size);
1300                 return -EINVAL;
1301         }
1302
1303         for (i = 0; i < reta_size; i++) {
1304                 struct bnxt_rx_queue *rxq;
1305
1306                 idx = i / RTE_RETA_GROUP_SIZE;
1307                 sft = i % RTE_RETA_GROUP_SIZE;
1308
1309                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1310                         continue;
1311
1312                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1313                 if (!rxq) {
1314                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1315                         return -EINVAL;
1316                 }
1317
1318                 if (BNXT_CHIP_THOR(bp)) {
1319                         vnic->rss_table[i * 2] =
1320                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1321                         vnic->rss_table[i * 2 + 1] =
1322                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1323                 } else {
1324                         vnic->rss_table[i] =
1325                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1326                 }
1327         }
1328
1329         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1330         return 0;
1331 }
1332
1333 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1334                               struct rte_eth_rss_reta_entry64 *reta_conf,
1335                               uint16_t reta_size)
1336 {
1337         struct bnxt *bp = eth_dev->data->dev_private;
1338         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1339         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1340         uint16_t idx, sft, i;
1341         int rc;
1342
1343         rc = is_bnxt_in_error(bp);
1344         if (rc)
1345                 return rc;
1346
1347         /* Retrieve from the default VNIC */
1348         if (!vnic)
1349                 return -EINVAL;
1350         if (!vnic->rss_table)
1351                 return -EINVAL;
1352
1353         if (reta_size != tbl_size) {
1354                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1355                         "(%d) must equal the size supported by the hardware "
1356                         "(%d)\n", reta_size, tbl_size);
1357                 return -EINVAL;
1358         }
1359
1360         for (idx = 0, i = 0; i < reta_size; i++) {
1361                 idx = i / RTE_RETA_GROUP_SIZE;
1362                 sft = i % RTE_RETA_GROUP_SIZE;
1363
1364                 if (reta_conf[idx].mask & (1ULL << sft)) {
1365                         uint16_t qid;
1366
1367                         if (BNXT_CHIP_THOR(bp))
1368                                 qid = bnxt_rss_to_qid(bp,
1369                                                       vnic->rss_table[i * 2]);
1370                         else
1371                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1372
1373                         if (qid == INVALID_HW_RING_ID) {
1374                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1375                                 return -EINVAL;
1376                         }
1377                         reta_conf[idx].reta[sft] = qid;
1378                 }
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1385                                    struct rte_eth_rss_conf *rss_conf)
1386 {
1387         struct bnxt *bp = eth_dev->data->dev_private;
1388         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1389         struct bnxt_vnic_info *vnic;
1390         int rc;
1391
1392         rc = is_bnxt_in_error(bp);
1393         if (rc)
1394                 return rc;
1395
1396         /*
1397          * If RSS enablement were different than dev_configure,
1398          * then return -EINVAL
1399          */
1400         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1401                 if (!rss_conf->rss_hf)
1402                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1403         } else {
1404                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1405                         return -EINVAL;
1406         }
1407
1408         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1409         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1410
1411         /* Update the default RSS VNIC(s) */
1412         vnic = &bp->vnic_info[0];
1413         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1414
1415         /*
1416          * If hashkey is not specified, use the previously configured
1417          * hashkey
1418          */
1419         if (!rss_conf->rss_key)
1420                 goto rss_config;
1421
1422         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1423                 PMD_DRV_LOG(ERR,
1424                             "Invalid hashkey length, should be 16 bytes\n");
1425                 return -EINVAL;
1426         }
1427         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1428
1429 rss_config:
1430         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1431         return 0;
1432 }
1433
1434 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1435                                      struct rte_eth_rss_conf *rss_conf)
1436 {
1437         struct bnxt *bp = eth_dev->data->dev_private;
1438         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1439         int len, rc;
1440         uint32_t hash_types;
1441
1442         rc = is_bnxt_in_error(bp);
1443         if (rc)
1444                 return rc;
1445
1446         /* RSS configuration is the same for all VNICs */
1447         if (vnic && vnic->rss_hash_key) {
1448                 if (rss_conf->rss_key) {
1449                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1450                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1451                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1452                 }
1453
1454                 hash_types = vnic->hash_type;
1455                 rss_conf->rss_hf = 0;
1456                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1457                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1458                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1459                 }
1460                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1461                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1462                         hash_types &=
1463                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1464                 }
1465                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1466                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1467                         hash_types &=
1468                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1469                 }
1470                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1471                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1472                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1473                 }
1474                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1475                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1476                         hash_types &=
1477                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1478                 }
1479                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1480                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1481                         hash_types &=
1482                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1483                 }
1484                 if (hash_types) {
1485                         PMD_DRV_LOG(ERR,
1486                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1487                                 vnic->hash_type);
1488                         return -ENOTSUP;
1489                 }
1490         } else {
1491                 rss_conf->rss_hf = 0;
1492         }
1493         return 0;
1494 }
1495
1496 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1497                                struct rte_eth_fc_conf *fc_conf)
1498 {
1499         struct bnxt *bp = dev->data->dev_private;
1500         struct rte_eth_link link_info;
1501         int rc;
1502
1503         rc = is_bnxt_in_error(bp);
1504         if (rc)
1505                 return rc;
1506
1507         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1508         if (rc)
1509                 return rc;
1510
1511         memset(fc_conf, 0, sizeof(*fc_conf));
1512         if (bp->link_info.auto_pause)
1513                 fc_conf->autoneg = 1;
1514         switch (bp->link_info.pause) {
1515         case 0:
1516                 fc_conf->mode = RTE_FC_NONE;
1517                 break;
1518         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1519                 fc_conf->mode = RTE_FC_TX_PAUSE;
1520                 break;
1521         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1522                 fc_conf->mode = RTE_FC_RX_PAUSE;
1523                 break;
1524         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1525                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1526                 fc_conf->mode = RTE_FC_FULL;
1527                 break;
1528         }
1529         return 0;
1530 }
1531
1532 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1533                                struct rte_eth_fc_conf *fc_conf)
1534 {
1535         struct bnxt *bp = dev->data->dev_private;
1536         int rc;
1537
1538         rc = is_bnxt_in_error(bp);
1539         if (rc)
1540                 return rc;
1541
1542         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1543                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1544                 return -ENOTSUP;
1545         }
1546
1547         switch (fc_conf->mode) {
1548         case RTE_FC_NONE:
1549                 bp->link_info.auto_pause = 0;
1550                 bp->link_info.force_pause = 0;
1551                 break;
1552         case RTE_FC_RX_PAUSE:
1553                 if (fc_conf->autoneg) {
1554                         bp->link_info.auto_pause =
1555                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1556                         bp->link_info.force_pause = 0;
1557                 } else {
1558                         bp->link_info.auto_pause = 0;
1559                         bp->link_info.force_pause =
1560                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1561                 }
1562                 break;
1563         case RTE_FC_TX_PAUSE:
1564                 if (fc_conf->autoneg) {
1565                         bp->link_info.auto_pause =
1566                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1567                         bp->link_info.force_pause = 0;
1568                 } else {
1569                         bp->link_info.auto_pause = 0;
1570                         bp->link_info.force_pause =
1571                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1572                 }
1573                 break;
1574         case RTE_FC_FULL:
1575                 if (fc_conf->autoneg) {
1576                         bp->link_info.auto_pause =
1577                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1578                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1579                         bp->link_info.force_pause = 0;
1580                 } else {
1581                         bp->link_info.auto_pause = 0;
1582                         bp->link_info.force_pause =
1583                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1584                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1585                 }
1586                 break;
1587         }
1588         return bnxt_set_hwrm_link_config(bp, true);
1589 }
1590
1591 /* Add UDP tunneling port */
1592 static int
1593 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1594                          struct rte_eth_udp_tunnel *udp_tunnel)
1595 {
1596         struct bnxt *bp = eth_dev->data->dev_private;
1597         uint16_t tunnel_type = 0;
1598         int rc = 0;
1599
1600         rc = is_bnxt_in_error(bp);
1601         if (rc)
1602                 return rc;
1603
1604         switch (udp_tunnel->prot_type) {
1605         case RTE_TUNNEL_TYPE_VXLAN:
1606                 if (bp->vxlan_port_cnt) {
1607                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1608                                 udp_tunnel->udp_port);
1609                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1610                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1611                                 return -ENOSPC;
1612                         }
1613                         bp->vxlan_port_cnt++;
1614                         return 0;
1615                 }
1616                 tunnel_type =
1617                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1618                 bp->vxlan_port_cnt++;
1619                 break;
1620         case RTE_TUNNEL_TYPE_GENEVE:
1621                 if (bp->geneve_port_cnt) {
1622                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1623                                 udp_tunnel->udp_port);
1624                         if (bp->geneve_port != udp_tunnel->udp_port) {
1625                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1626                                 return -ENOSPC;
1627                         }
1628                         bp->geneve_port_cnt++;
1629                         return 0;
1630                 }
1631                 tunnel_type =
1632                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1633                 bp->geneve_port_cnt++;
1634                 break;
1635         default:
1636                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1637                 return -ENOTSUP;
1638         }
1639         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1640                                              tunnel_type);
1641         return rc;
1642 }
1643
1644 static int
1645 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1646                          struct rte_eth_udp_tunnel *udp_tunnel)
1647 {
1648         struct bnxt *bp = eth_dev->data->dev_private;
1649         uint16_t tunnel_type = 0;
1650         uint16_t port = 0;
1651         int rc = 0;
1652
1653         rc = is_bnxt_in_error(bp);
1654         if (rc)
1655                 return rc;
1656
1657         switch (udp_tunnel->prot_type) {
1658         case RTE_TUNNEL_TYPE_VXLAN:
1659                 if (!bp->vxlan_port_cnt) {
1660                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1661                         return -EINVAL;
1662                 }
1663                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1664                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1665                                 udp_tunnel->udp_port, bp->vxlan_port);
1666                         return -EINVAL;
1667                 }
1668                 if (--bp->vxlan_port_cnt)
1669                         return 0;
1670
1671                 tunnel_type =
1672                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1673                 port = bp->vxlan_fw_dst_port_id;
1674                 break;
1675         case RTE_TUNNEL_TYPE_GENEVE:
1676                 if (!bp->geneve_port_cnt) {
1677                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1678                         return -EINVAL;
1679                 }
1680                 if (bp->geneve_port != udp_tunnel->udp_port) {
1681                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1682                                 udp_tunnel->udp_port, bp->geneve_port);
1683                         return -EINVAL;
1684                 }
1685                 if (--bp->geneve_port_cnt)
1686                         return 0;
1687
1688                 tunnel_type =
1689                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1690                 port = bp->geneve_fw_dst_port_id;
1691                 break;
1692         default:
1693                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1694                 return -ENOTSUP;
1695         }
1696
1697         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1698         if (!rc) {
1699                 if (tunnel_type ==
1700                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1701                         bp->vxlan_port = 0;
1702                 if (tunnel_type ==
1703                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1704                         bp->geneve_port = 0;
1705         }
1706         return rc;
1707 }
1708
1709 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1710 {
1711         struct bnxt_filter_info *filter;
1712         struct bnxt_vnic_info *vnic;
1713         int rc = 0;
1714         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1715
1716         /* if VLAN exists && VLAN matches vlan_id
1717          *      remove the MAC+VLAN filter
1718          *      add a new MAC only filter
1719          * else
1720          *      VLAN filter doesn't exist, just skip and continue
1721          */
1722         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1723         filter = STAILQ_FIRST(&vnic->filter);
1724         while (filter) {
1725                 /* Search for this matching MAC+VLAN filter */
1726                 if ((filter->enables & chk) &&
1727                     (filter->l2_ivlan == vlan_id &&
1728                      filter->l2_ivlan_mask != 0) &&
1729                     !memcmp(filter->l2_addr, bp->mac_addr,
1730                             RTE_ETHER_ADDR_LEN)) {
1731                         /* Delete the filter */
1732                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1733                         if (rc)
1734                                 return rc;
1735                         STAILQ_REMOVE(&vnic->filter, filter,
1736                                       bnxt_filter_info, next);
1737                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1738
1739                         PMD_DRV_LOG(INFO,
1740                                     "Del Vlan filter for %d\n",
1741                                     vlan_id);
1742                         return rc;
1743                 }
1744                 filter = STAILQ_NEXT(filter, next);
1745         }
1746         return -ENOENT;
1747 }
1748
1749 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1750 {
1751         struct bnxt_filter_info *filter;
1752         struct bnxt_vnic_info *vnic;
1753         int rc = 0;
1754         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1755                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1756         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1757
1758         /* Implementation notes on the use of VNIC in this command:
1759          *
1760          * By default, these filters belong to default vnic for the function.
1761          * Once these filters are set up, only destination VNIC can be modified.
1762          * If the destination VNIC is not specified in this command,
1763          * then the HWRM shall only create an l2 context id.
1764          */
1765
1766         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1767         filter = STAILQ_FIRST(&vnic->filter);
1768         /* Check if the VLAN has already been added */
1769         while (filter) {
1770                 if ((filter->enables & chk) &&
1771                     (filter->l2_ivlan == vlan_id &&
1772                      filter->l2_ivlan_mask == 0x0FFF) &&
1773                      !memcmp(filter->l2_addr, bp->mac_addr,
1774                              RTE_ETHER_ADDR_LEN))
1775                         return -EEXIST;
1776
1777                 filter = STAILQ_NEXT(filter, next);
1778         }
1779
1780         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1781          * command to create MAC+VLAN filter with the right flags, enables set.
1782          */
1783         filter = bnxt_alloc_filter(bp);
1784         if (!filter) {
1785                 PMD_DRV_LOG(ERR,
1786                             "MAC/VLAN filter alloc failed\n");
1787                 return -ENOMEM;
1788         }
1789         /* MAC + VLAN ID filter */
1790         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1791          * untagged packets are received
1792          *
1793          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1794          * packets and only the programmed vlan's packets are received
1795          */
1796         filter->l2_ivlan = vlan_id;
1797         filter->l2_ivlan_mask = 0x0FFF;
1798         filter->enables |= en;
1799         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1800
1801         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1802         if (rc) {
1803                 /* Free the newly allocated filter as we were
1804                  * not able to create the filter in hardware.
1805                  */
1806                 filter->fw_l2_filter_id = UINT64_MAX;
1807                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1808                 return rc;
1809         } else {
1810                 /* Add this new filter to the list */
1811                 if (vlan_id == 0) {
1812                         filter->dflt = true;
1813                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1814                 } else {
1815                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1816                 }
1817         }
1818
1819         PMD_DRV_LOG(INFO,
1820                     "Added Vlan filter for %d\n", vlan_id);
1821         return rc;
1822 }
1823
1824 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1825                 uint16_t vlan_id, int on)
1826 {
1827         struct bnxt *bp = eth_dev->data->dev_private;
1828         int rc;
1829
1830         rc = is_bnxt_in_error(bp);
1831         if (rc)
1832                 return rc;
1833
1834         /* These operations apply to ALL existing MAC/VLAN filters */
1835         if (on)
1836                 return bnxt_add_vlan_filter(bp, vlan_id);
1837         else
1838                 return bnxt_del_vlan_filter(bp, vlan_id);
1839 }
1840
1841 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1842                                     struct bnxt_vnic_info *vnic)
1843 {
1844         struct bnxt_filter_info *filter;
1845         int rc;
1846
1847         filter = STAILQ_FIRST(&vnic->filter);
1848         while (filter) {
1849                 if (filter->dflt &&
1850                     !memcmp(filter->l2_addr, bp->mac_addr,
1851                             RTE_ETHER_ADDR_LEN)) {
1852                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1853                         if (rc)
1854                                 return rc;
1855                         filter->dflt = false;
1856                         STAILQ_REMOVE(&vnic->filter, filter,
1857                                       bnxt_filter_info, next);
1858                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1859                                            filter, next);
1860                         filter->fw_l2_filter_id = -1;
1861                         break;
1862                 }
1863                 filter = STAILQ_NEXT(filter, next);
1864         }
1865         return 0;
1866 }
1867
1868 static int
1869 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1870 {
1871         struct bnxt *bp = dev->data->dev_private;
1872         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1873         struct bnxt_vnic_info *vnic;
1874         unsigned int i;
1875         int rc;
1876
1877         rc = is_bnxt_in_error(bp);
1878         if (rc)
1879                 return rc;
1880
1881         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1882         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1883                 /* Remove any VLAN filters programmed */
1884                 for (i = 0; i < 4095; i++)
1885                         bnxt_del_vlan_filter(bp, i);
1886
1887                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1888                 if (rc)
1889                         return rc;
1890         } else {
1891                 /* Default filter will allow packets that match the
1892                  * dest mac. So, it has to be deleted, otherwise, we
1893                  * will endup receiving vlan packets for which the
1894                  * filter is not programmed, when hw-vlan-filter
1895                  * configuration is ON
1896                  */
1897                 bnxt_del_dflt_mac_filter(bp, vnic);
1898                 /* This filter will allow only untagged packets */
1899                 bnxt_add_vlan_filter(bp, 0);
1900         }
1901         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1902                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1903
1904         if (mask & ETH_VLAN_STRIP_MASK) {
1905                 /* Enable or disable VLAN stripping */
1906                 for (i = 0; i < bp->nr_vnics; i++) {
1907                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1908                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1909                                 vnic->vlan_strip = true;
1910                         else
1911                                 vnic->vlan_strip = false;
1912                         bnxt_hwrm_vnic_cfg(bp, vnic);
1913                 }
1914                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1915                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1916         }
1917
1918         if (mask & ETH_VLAN_EXTEND_MASK) {
1919                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1920                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1921                 else
1922                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int
1929 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1930                       uint16_t tpid)
1931 {
1932         struct bnxt *bp = dev->data->dev_private;
1933         int qinq = dev->data->dev_conf.rxmode.offloads &
1934                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1935
1936         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1937             vlan_type != ETH_VLAN_TYPE_OUTER) {
1938                 PMD_DRV_LOG(ERR,
1939                             "Unsupported vlan type.");
1940                 return -EINVAL;
1941         }
1942         if (!qinq) {
1943                 PMD_DRV_LOG(ERR,
1944                             "QinQ not enabled. Needs to be ON as we can "
1945                             "accelerate only outer vlan\n");
1946                 return -EINVAL;
1947         }
1948
1949         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1950                 switch (tpid) {
1951                 case RTE_ETHER_TYPE_QINQ:
1952                         bp->outer_tpid_bd =
1953                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1954                                 break;
1955                 case RTE_ETHER_TYPE_VLAN:
1956                         bp->outer_tpid_bd =
1957                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1958                                 break;
1959                 case 0x9100:
1960                         bp->outer_tpid_bd =
1961                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1962                                 break;
1963                 case 0x9200:
1964                         bp->outer_tpid_bd =
1965                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1966                                 break;
1967                 case 0x9300:
1968                         bp->outer_tpid_bd =
1969                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1970                                 break;
1971                 default:
1972                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1973                         return -EINVAL;
1974                 }
1975                 bp->outer_tpid_bd |= tpid;
1976                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1977         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1978                 PMD_DRV_LOG(ERR,
1979                             "Can accelerate only outer vlan in QinQ\n");
1980                 return -EINVAL;
1981         }
1982
1983         return 0;
1984 }
1985
1986 static int
1987 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1988                              struct rte_ether_addr *addr)
1989 {
1990         struct bnxt *bp = dev->data->dev_private;
1991         /* Default Filter is tied to VNIC 0 */
1992         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1993         struct bnxt_filter_info *filter;
1994         int rc;
1995
1996         rc = is_bnxt_in_error(bp);
1997         if (rc)
1998                 return rc;
1999
2000         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2001                 return -EPERM;
2002
2003         if (rte_is_zero_ether_addr(addr))
2004                 return -EINVAL;
2005
2006         STAILQ_FOREACH(filter, &vnic->filter, next) {
2007                 /* Default Filter is at Index 0 */
2008                 if (filter->mac_index != 0)
2009                         continue;
2010
2011                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2012                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2013                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2014                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2015                 filter->enables |=
2016                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2017                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2018
2019                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2020                 if (rc) {
2021                         memcpy(filter->l2_addr, bp->mac_addr,
2022                                RTE_ETHER_ADDR_LEN);
2023                         return rc;
2024                 }
2025
2026                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2027                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2028                 return 0;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static int
2035 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2036                           struct rte_ether_addr *mc_addr_set,
2037                           uint32_t nb_mc_addr)
2038 {
2039         struct bnxt *bp = eth_dev->data->dev_private;
2040         char *mc_addr_list = (char *)mc_addr_set;
2041         struct bnxt_vnic_info *vnic;
2042         uint32_t off = 0, i = 0;
2043         int rc;
2044
2045         rc = is_bnxt_in_error(bp);
2046         if (rc)
2047                 return rc;
2048
2049         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2050
2051         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2052                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2053                 goto allmulti;
2054         }
2055
2056         /* TODO Check for Duplicate mcast addresses */
2057         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2058         for (i = 0; i < nb_mc_addr; i++) {
2059                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2060                         RTE_ETHER_ADDR_LEN);
2061                 off += RTE_ETHER_ADDR_LEN;
2062         }
2063
2064         vnic->mc_addr_cnt = i;
2065         if (vnic->mc_addr_cnt)
2066                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2067         else
2068                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2069
2070 allmulti:
2071         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2072 }
2073
2074 static int
2075 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2076 {
2077         struct bnxt *bp = dev->data->dev_private;
2078         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2079         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2080         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2081         int ret;
2082
2083         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2084                         fw_major, fw_minor, fw_updt);
2085
2086         ret += 1; /* add the size of '\0' */
2087         if (fw_size < (uint32_t)ret)
2088                 return ret;
2089         else
2090                 return 0;
2091 }
2092
2093 static void
2094 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2095         struct rte_eth_rxq_info *qinfo)
2096 {
2097         struct bnxt_rx_queue *rxq;
2098
2099         rxq = dev->data->rx_queues[queue_id];
2100
2101         qinfo->mp = rxq->mb_pool;
2102         qinfo->scattered_rx = dev->data->scattered_rx;
2103         qinfo->nb_desc = rxq->nb_rx_desc;
2104
2105         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2106         qinfo->conf.rx_drop_en = 0;
2107         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2108 }
2109
2110 static void
2111 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2112         struct rte_eth_txq_info *qinfo)
2113 {
2114         struct bnxt_tx_queue *txq;
2115
2116         txq = dev->data->tx_queues[queue_id];
2117
2118         qinfo->nb_desc = txq->nb_tx_desc;
2119
2120         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2121         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2122         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2123
2124         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2125         qinfo->conf.tx_rs_thresh = 0;
2126         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2127 }
2128
2129 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2130 {
2131         struct bnxt *bp = eth_dev->data->dev_private;
2132         uint32_t new_pkt_size;
2133         uint32_t rc = 0;
2134         uint32_t i;
2135
2136         rc = is_bnxt_in_error(bp);
2137         if (rc)
2138                 return rc;
2139
2140         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2141                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2142
2143 #ifdef RTE_ARCH_X86
2144         /*
2145          * If vector-mode tx/rx is active, disallow any MTU change that would
2146          * require scattered receive support.
2147          */
2148         if (eth_dev->data->dev_started &&
2149             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2150              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2151             (new_pkt_size >
2152              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2153                 PMD_DRV_LOG(ERR,
2154                             "MTU change would require scattered rx support. ");
2155                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2156                 return -EINVAL;
2157         }
2158 #endif
2159
2160         if (new_mtu > RTE_ETHER_MTU) {
2161                 bp->flags |= BNXT_FLAG_JUMBO;
2162                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2163                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2164         } else {
2165                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2166                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2167                 bp->flags &= ~BNXT_FLAG_JUMBO;
2168         }
2169
2170         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2171
2172         for (i = 0; i < bp->nr_vnics; i++) {
2173                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2174                 uint16_t size = 0;
2175
2176                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2177                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2178                 if (rc)
2179                         break;
2180
2181                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2182                 size -= RTE_PKTMBUF_HEADROOM;
2183
2184                 if (size < new_mtu) {
2185                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2186                         if (rc)
2187                                 return rc;
2188                 }
2189         }
2190
2191         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2192
2193         return rc;
2194 }
2195
2196 static int
2197 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2198 {
2199         struct bnxt *bp = dev->data->dev_private;
2200         uint16_t vlan = bp->vlan;
2201         int rc;
2202
2203         rc = is_bnxt_in_error(bp);
2204         if (rc)
2205                 return rc;
2206
2207         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2208                 PMD_DRV_LOG(ERR,
2209                         "PVID cannot be modified for this function\n");
2210                 return -ENOTSUP;
2211         }
2212         bp->vlan = on ? pvid : 0;
2213
2214         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2215         if (rc)
2216                 bp->vlan = vlan;
2217         return rc;
2218 }
2219
2220 static int
2221 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2222 {
2223         struct bnxt *bp = dev->data->dev_private;
2224         int rc;
2225
2226         rc = is_bnxt_in_error(bp);
2227         if (rc)
2228                 return rc;
2229
2230         return bnxt_hwrm_port_led_cfg(bp, true);
2231 }
2232
2233 static int
2234 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2235 {
2236         struct bnxt *bp = dev->data->dev_private;
2237         int rc;
2238
2239         rc = is_bnxt_in_error(bp);
2240         if (rc)
2241                 return rc;
2242
2243         return bnxt_hwrm_port_led_cfg(bp, false);
2244 }
2245
2246 static uint32_t
2247 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2248 {
2249         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2250         uint32_t desc = 0, raw_cons = 0, cons;
2251         struct bnxt_cp_ring_info *cpr;
2252         struct bnxt_rx_queue *rxq;
2253         struct rx_pkt_cmpl *rxcmp;
2254         int rc;
2255
2256         rc = is_bnxt_in_error(bp);
2257         if (rc)
2258                 return rc;
2259
2260         rxq = dev->data->rx_queues[rx_queue_id];
2261         cpr = rxq->cp_ring;
2262         raw_cons = cpr->cp_raw_cons;
2263
2264         while (1) {
2265                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2266                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2267                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2268
2269                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2270                         break;
2271                 } else {
2272                         raw_cons++;
2273                         desc++;
2274                 }
2275         }
2276
2277         return desc;
2278 }
2279
2280 static int
2281 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2282 {
2283         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2284         struct bnxt_rx_ring_info *rxr;
2285         struct bnxt_cp_ring_info *cpr;
2286         struct bnxt_sw_rx_bd *rx_buf;
2287         struct rx_pkt_cmpl *rxcmp;
2288         uint32_t cons, cp_cons;
2289         int rc;
2290
2291         if (!rxq)
2292                 return -EINVAL;
2293
2294         rc = is_bnxt_in_error(rxq->bp);
2295         if (rc)
2296                 return rc;
2297
2298         cpr = rxq->cp_ring;
2299         rxr = rxq->rx_ring;
2300
2301         if (offset >= rxq->nb_rx_desc)
2302                 return -EINVAL;
2303
2304         cons = RING_CMP(cpr->cp_ring_struct, offset);
2305         cp_cons = cpr->cp_raw_cons;
2306         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2307
2308         if (cons > cp_cons) {
2309                 if (CMPL_VALID(rxcmp, cpr->valid))
2310                         return RTE_ETH_RX_DESC_DONE;
2311         } else {
2312                 if (CMPL_VALID(rxcmp, !cpr->valid))
2313                         return RTE_ETH_RX_DESC_DONE;
2314         }
2315         rx_buf = &rxr->rx_buf_ring[cons];
2316         if (rx_buf->mbuf == NULL)
2317                 return RTE_ETH_RX_DESC_UNAVAIL;
2318
2319
2320         return RTE_ETH_RX_DESC_AVAIL;
2321 }
2322
2323 static int
2324 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2325 {
2326         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2327         struct bnxt_tx_ring_info *txr;
2328         struct bnxt_cp_ring_info *cpr;
2329         struct bnxt_sw_tx_bd *tx_buf;
2330         struct tx_pkt_cmpl *txcmp;
2331         uint32_t cons, cp_cons;
2332         int rc;
2333
2334         if (!txq)
2335                 return -EINVAL;
2336
2337         rc = is_bnxt_in_error(txq->bp);
2338         if (rc)
2339                 return rc;
2340
2341         cpr = txq->cp_ring;
2342         txr = txq->tx_ring;
2343
2344         if (offset >= txq->nb_tx_desc)
2345                 return -EINVAL;
2346
2347         cons = RING_CMP(cpr->cp_ring_struct, offset);
2348         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2349         cp_cons = cpr->cp_raw_cons;
2350
2351         if (cons > cp_cons) {
2352                 if (CMPL_VALID(txcmp, cpr->valid))
2353                         return RTE_ETH_TX_DESC_UNAVAIL;
2354         } else {
2355                 if (CMPL_VALID(txcmp, !cpr->valid))
2356                         return RTE_ETH_TX_DESC_UNAVAIL;
2357         }
2358         tx_buf = &txr->tx_buf_ring[cons];
2359         if (tx_buf->mbuf == NULL)
2360                 return RTE_ETH_TX_DESC_DONE;
2361
2362         return RTE_ETH_TX_DESC_FULL;
2363 }
2364
2365 static struct bnxt_filter_info *
2366 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2367                                 struct rte_eth_ethertype_filter *efilter,
2368                                 struct bnxt_vnic_info *vnic0,
2369                                 struct bnxt_vnic_info *vnic,
2370                                 int *ret)
2371 {
2372         struct bnxt_filter_info *mfilter = NULL;
2373         int match = 0;
2374         *ret = 0;
2375
2376         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2377                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2378                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2379                         " ethertype filter.", efilter->ether_type);
2380                 *ret = -EINVAL;
2381                 goto exit;
2382         }
2383         if (efilter->queue >= bp->rx_nr_rings) {
2384                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2385                 *ret = -EINVAL;
2386                 goto exit;
2387         }
2388
2389         vnic0 = &bp->vnic_info[0];
2390         vnic = &bp->vnic_info[efilter->queue];
2391         if (vnic == NULL) {
2392                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2393                 *ret = -EINVAL;
2394                 goto exit;
2395         }
2396
2397         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2398                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2399                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2400                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2401                              mfilter->flags ==
2402                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2403                              mfilter->ethertype == efilter->ether_type)) {
2404                                 match = 1;
2405                                 break;
2406                         }
2407                 }
2408         } else {
2409                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2410                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2411                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2412                              mfilter->ethertype == efilter->ether_type &&
2413                              mfilter->flags ==
2414                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2415                                 match = 1;
2416                                 break;
2417                         }
2418         }
2419
2420         if (match)
2421                 *ret = -EEXIST;
2422
2423 exit:
2424         return mfilter;
2425 }
2426
2427 static int
2428 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2429                         enum rte_filter_op filter_op,
2430                         void *arg)
2431 {
2432         struct bnxt *bp = dev->data->dev_private;
2433         struct rte_eth_ethertype_filter *efilter =
2434                         (struct rte_eth_ethertype_filter *)arg;
2435         struct bnxt_filter_info *bfilter, *filter1;
2436         struct bnxt_vnic_info *vnic, *vnic0;
2437         int ret;
2438
2439         if (filter_op == RTE_ETH_FILTER_NOP)
2440                 return 0;
2441
2442         if (arg == NULL) {
2443                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2444                             filter_op);
2445                 return -EINVAL;
2446         }
2447
2448         vnic0 = &bp->vnic_info[0];
2449         vnic = &bp->vnic_info[efilter->queue];
2450
2451         switch (filter_op) {
2452         case RTE_ETH_FILTER_ADD:
2453                 bnxt_match_and_validate_ether_filter(bp, efilter,
2454                                                         vnic0, vnic, &ret);
2455                 if (ret < 0)
2456                         return ret;
2457
2458                 bfilter = bnxt_get_unused_filter(bp);
2459                 if (bfilter == NULL) {
2460                         PMD_DRV_LOG(ERR,
2461                                 "Not enough resources for a new filter.\n");
2462                         return -ENOMEM;
2463                 }
2464                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2465                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2466                        RTE_ETHER_ADDR_LEN);
2467                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2468                        RTE_ETHER_ADDR_LEN);
2469                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2470                 bfilter->ethertype = efilter->ether_type;
2471                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2472
2473                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2474                 if (filter1 == NULL) {
2475                         ret = -EINVAL;
2476                         goto cleanup;
2477                 }
2478                 bfilter->enables |=
2479                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2480                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2481
2482                 bfilter->dst_id = vnic->fw_vnic_id;
2483
2484                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2485                         bfilter->flags =
2486                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2487                 }
2488
2489                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2490                 if (ret)
2491                         goto cleanup;
2492                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2493                 break;
2494         case RTE_ETH_FILTER_DELETE:
2495                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2496                                                         vnic0, vnic, &ret);
2497                 if (ret == -EEXIST) {
2498                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2499
2500                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2501                                       next);
2502                         bnxt_free_filter(bp, filter1);
2503                 } else if (ret == 0) {
2504                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2505                 }
2506                 break;
2507         default:
2508                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2509                 ret = -EINVAL;
2510                 goto error;
2511         }
2512         return ret;
2513 cleanup:
2514         bnxt_free_filter(bp, bfilter);
2515 error:
2516         return ret;
2517 }
2518
2519 static inline int
2520 parse_ntuple_filter(struct bnxt *bp,
2521                     struct rte_eth_ntuple_filter *nfilter,
2522                     struct bnxt_filter_info *bfilter)
2523 {
2524         uint32_t en = 0;
2525
2526         if (nfilter->queue >= bp->rx_nr_rings) {
2527                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2528                 return -EINVAL;
2529         }
2530
2531         switch (nfilter->dst_port_mask) {
2532         case UINT16_MAX:
2533                 bfilter->dst_port_mask = -1;
2534                 bfilter->dst_port = nfilter->dst_port;
2535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2536                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2537                 break;
2538         default:
2539                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2540                 return -EINVAL;
2541         }
2542
2543         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2544         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2545
2546         switch (nfilter->proto_mask) {
2547         case UINT8_MAX:
2548                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2549                         bfilter->ip_protocol = 17;
2550                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2551                         bfilter->ip_protocol = 6;
2552                 else
2553                         return -EINVAL;
2554                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2555                 break;
2556         default:
2557                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2558                 return -EINVAL;
2559         }
2560
2561         switch (nfilter->dst_ip_mask) {
2562         case UINT32_MAX:
2563                 bfilter->dst_ipaddr_mask[0] = -1;
2564                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2565                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2566                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2567                 break;
2568         default:
2569                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2570                 return -EINVAL;
2571         }
2572
2573         switch (nfilter->src_ip_mask) {
2574         case UINT32_MAX:
2575                 bfilter->src_ipaddr_mask[0] = -1;
2576                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2577                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2578                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2579                 break;
2580         default:
2581                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2582                 return -EINVAL;
2583         }
2584
2585         switch (nfilter->src_port_mask) {
2586         case UINT16_MAX:
2587                 bfilter->src_port_mask = -1;
2588                 bfilter->src_port = nfilter->src_port;
2589                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2590                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2591                 break;
2592         default:
2593                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2594                 return -EINVAL;
2595         }
2596
2597         //TODO Priority
2598         //nfilter->priority = (uint8_t)filter->priority;
2599
2600         bfilter->enables = en;
2601         return 0;
2602 }
2603
2604 static struct bnxt_filter_info*
2605 bnxt_match_ntuple_filter(struct bnxt *bp,
2606                          struct bnxt_filter_info *bfilter,
2607                          struct bnxt_vnic_info **mvnic)
2608 {
2609         struct bnxt_filter_info *mfilter = NULL;
2610         int i;
2611
2612         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2613                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2614                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2615                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2616                             bfilter->src_ipaddr_mask[0] ==
2617                             mfilter->src_ipaddr_mask[0] &&
2618                             bfilter->src_port == mfilter->src_port &&
2619                             bfilter->src_port_mask == mfilter->src_port_mask &&
2620                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2621                             bfilter->dst_ipaddr_mask[0] ==
2622                             mfilter->dst_ipaddr_mask[0] &&
2623                             bfilter->dst_port == mfilter->dst_port &&
2624                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2625                             bfilter->flags == mfilter->flags &&
2626                             bfilter->enables == mfilter->enables) {
2627                                 if (mvnic)
2628                                         *mvnic = vnic;
2629                                 return mfilter;
2630                         }
2631                 }
2632         }
2633         return NULL;
2634 }
2635
2636 static int
2637 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2638                        struct rte_eth_ntuple_filter *nfilter,
2639                        enum rte_filter_op filter_op)
2640 {
2641         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2642         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2643         int ret;
2644
2645         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2646                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2647                 return -EINVAL;
2648         }
2649
2650         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2651                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2652                 return -EINVAL;
2653         }
2654
2655         bfilter = bnxt_get_unused_filter(bp);
2656         if (bfilter == NULL) {
2657                 PMD_DRV_LOG(ERR,
2658                         "Not enough resources for a new filter.\n");
2659                 return -ENOMEM;
2660         }
2661         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2662         if (ret < 0)
2663                 goto free_filter;
2664
2665         vnic = &bp->vnic_info[nfilter->queue];
2666         vnic0 = &bp->vnic_info[0];
2667         filter1 = STAILQ_FIRST(&vnic0->filter);
2668         if (filter1 == NULL) {
2669                 ret = -EINVAL;
2670                 goto free_filter;
2671         }
2672
2673         bfilter->dst_id = vnic->fw_vnic_id;
2674         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2675         bfilter->enables |=
2676                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2677         bfilter->ethertype = 0x800;
2678         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2679
2680         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2681
2682         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2683             bfilter->dst_id == mfilter->dst_id) {
2684                 PMD_DRV_LOG(ERR, "filter exists.\n");
2685                 ret = -EEXIST;
2686                 goto free_filter;
2687         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2688                    bfilter->dst_id != mfilter->dst_id) {
2689                 mfilter->dst_id = vnic->fw_vnic_id;
2690                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2691                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2692                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2693                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2694                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2695                 goto free_filter;
2696         }
2697         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2698                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2699                 ret = -ENOENT;
2700                 goto free_filter;
2701         }
2702
2703         if (filter_op == RTE_ETH_FILTER_ADD) {
2704                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2705                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2706                 if (ret)
2707                         goto free_filter;
2708                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2709         } else {
2710                 if (mfilter == NULL) {
2711                         /* This should not happen. But for Coverity! */
2712                         ret = -ENOENT;
2713                         goto free_filter;
2714                 }
2715                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2716
2717                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2718                 bnxt_free_filter(bp, mfilter);
2719                 mfilter->fw_l2_filter_id = -1;
2720                 bnxt_free_filter(bp, bfilter);
2721                 bfilter->fw_l2_filter_id = -1;
2722         }
2723
2724         return 0;
2725 free_filter:
2726         bfilter->fw_l2_filter_id = -1;
2727         bnxt_free_filter(bp, bfilter);
2728         return ret;
2729 }
2730
2731 static int
2732 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2733                         enum rte_filter_op filter_op,
2734                         void *arg)
2735 {
2736         struct bnxt *bp = dev->data->dev_private;
2737         int ret;
2738
2739         if (filter_op == RTE_ETH_FILTER_NOP)
2740                 return 0;
2741
2742         if (arg == NULL) {
2743                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2744                             filter_op);
2745                 return -EINVAL;
2746         }
2747
2748         switch (filter_op) {
2749         case RTE_ETH_FILTER_ADD:
2750                 ret = bnxt_cfg_ntuple_filter(bp,
2751                         (struct rte_eth_ntuple_filter *)arg,
2752                         filter_op);
2753                 break;
2754         case RTE_ETH_FILTER_DELETE:
2755                 ret = bnxt_cfg_ntuple_filter(bp,
2756                         (struct rte_eth_ntuple_filter *)arg,
2757                         filter_op);
2758                 break;
2759         default:
2760                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2761                 ret = -EINVAL;
2762                 break;
2763         }
2764         return ret;
2765 }
2766
2767 static int
2768 bnxt_parse_fdir_filter(struct bnxt *bp,
2769                        struct rte_eth_fdir_filter *fdir,
2770                        struct bnxt_filter_info *filter)
2771 {
2772         enum rte_fdir_mode fdir_mode =
2773                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2774         struct bnxt_vnic_info *vnic0, *vnic;
2775         struct bnxt_filter_info *filter1;
2776         uint32_t en = 0;
2777         int i;
2778
2779         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2780                 return -EINVAL;
2781
2782         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2783         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2784
2785         switch (fdir->input.flow_type) {
2786         case RTE_ETH_FLOW_IPV4:
2787         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2788                 /* FALLTHROUGH */
2789                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2790                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2791                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2792                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2793                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2794                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2795                 filter->ip_addr_type =
2796                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2797                 filter->src_ipaddr_mask[0] = 0xffffffff;
2798                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2799                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2800                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2801                 filter->ethertype = 0x800;
2802                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2803                 break;
2804         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2805                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2806                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2807                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2808                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2809                 filter->dst_port_mask = 0xffff;
2810                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2811                 filter->src_port_mask = 0xffff;
2812                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2813                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2814                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2815                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2816                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2817                 filter->ip_protocol = 6;
2818                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2819                 filter->ip_addr_type =
2820                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2821                 filter->src_ipaddr_mask[0] = 0xffffffff;
2822                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2823                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2824                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2825                 filter->ethertype = 0x800;
2826                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2827                 break;
2828         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2829                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2830                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2831                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2832                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2833                 filter->dst_port_mask = 0xffff;
2834                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2835                 filter->src_port_mask = 0xffff;
2836                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2837                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2838                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2839                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2840                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2841                 filter->ip_protocol = 17;
2842                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2843                 filter->ip_addr_type =
2844                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2845                 filter->src_ipaddr_mask[0] = 0xffffffff;
2846                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2847                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2848                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2849                 filter->ethertype = 0x800;
2850                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2851                 break;
2852         case RTE_ETH_FLOW_IPV6:
2853         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2854                 /* FALLTHROUGH */
2855                 filter->ip_addr_type =
2856                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2857                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2858                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2859                 rte_memcpy(filter->src_ipaddr,
2860                            fdir->input.flow.ipv6_flow.src_ip, 16);
2861                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2862                 rte_memcpy(filter->dst_ipaddr,
2863                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2864                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2865                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2866                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2867                 memset(filter->src_ipaddr_mask, 0xff, 16);
2868                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2869                 filter->ethertype = 0x86dd;
2870                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2871                 break;
2872         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2873                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2874                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2875                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2876                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2877                 filter->dst_port_mask = 0xffff;
2878                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2879                 filter->src_port_mask = 0xffff;
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2881                 filter->ip_addr_type =
2882                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2883                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2884                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2885                 rte_memcpy(filter->src_ipaddr,
2886                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2887                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2888                 rte_memcpy(filter->dst_ipaddr,
2889                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2890                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2891                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2893                 memset(filter->src_ipaddr_mask, 0xff, 16);
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2895                 filter->ethertype = 0x86dd;
2896                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2897                 break;
2898         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2899                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2900                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2901                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2902                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2903                 filter->dst_port_mask = 0xffff;
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2905                 filter->src_port_mask = 0xffff;
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2907                 filter->ip_addr_type =
2908                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2909                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2910                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2911                 rte_memcpy(filter->src_ipaddr,
2912                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2913                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2914                 rte_memcpy(filter->dst_ipaddr,
2915                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2916                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2917                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2918                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2919                 memset(filter->src_ipaddr_mask, 0xff, 16);
2920                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2921                 filter->ethertype = 0x86dd;
2922                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2923                 break;
2924         case RTE_ETH_FLOW_L2_PAYLOAD:
2925                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2926                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2927                 break;
2928         case RTE_ETH_FLOW_VXLAN:
2929                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2930                         return -EINVAL;
2931                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2932                 filter->tunnel_type =
2933                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2934                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2935                 break;
2936         case RTE_ETH_FLOW_NVGRE:
2937                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2938                         return -EINVAL;
2939                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2940                 filter->tunnel_type =
2941                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2942                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2943                 break;
2944         case RTE_ETH_FLOW_UNKNOWN:
2945         case RTE_ETH_FLOW_RAW:
2946         case RTE_ETH_FLOW_FRAG_IPV4:
2947         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2948         case RTE_ETH_FLOW_FRAG_IPV6:
2949         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2950         case RTE_ETH_FLOW_IPV6_EX:
2951         case RTE_ETH_FLOW_IPV6_TCP_EX:
2952         case RTE_ETH_FLOW_IPV6_UDP_EX:
2953         case RTE_ETH_FLOW_GENEVE:
2954                 /* FALLTHROUGH */
2955         default:
2956                 return -EINVAL;
2957         }
2958
2959         vnic0 = &bp->vnic_info[0];
2960         vnic = &bp->vnic_info[fdir->action.rx_queue];
2961         if (vnic == NULL) {
2962                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2963                 return -EINVAL;
2964         }
2965
2966         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2967                 rte_memcpy(filter->dst_macaddr,
2968                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2969                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2970         }
2971
2972         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2973                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2974                 filter1 = STAILQ_FIRST(&vnic0->filter);
2975                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2976         } else {
2977                 filter->dst_id = vnic->fw_vnic_id;
2978                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2979                         if (filter->dst_macaddr[i] == 0x00)
2980                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2981                         else
2982                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2983         }
2984
2985         if (filter1 == NULL)
2986                 return -EINVAL;
2987
2988         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2989         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2990
2991         filter->enables = en;
2992
2993         return 0;
2994 }
2995
2996 static struct bnxt_filter_info *
2997 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2998                 struct bnxt_vnic_info **mvnic)
2999 {
3000         struct bnxt_filter_info *mf = NULL;
3001         int i;
3002
3003         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3004                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3005
3006                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3007                         if (mf->filter_type == nf->filter_type &&
3008                             mf->flags == nf->flags &&
3009                             mf->src_port == nf->src_port &&
3010                             mf->src_port_mask == nf->src_port_mask &&
3011                             mf->dst_port == nf->dst_port &&
3012                             mf->dst_port_mask == nf->dst_port_mask &&
3013                             mf->ip_protocol == nf->ip_protocol &&
3014                             mf->ip_addr_type == nf->ip_addr_type &&
3015                             mf->ethertype == nf->ethertype &&
3016                             mf->vni == nf->vni &&
3017                             mf->tunnel_type == nf->tunnel_type &&
3018                             mf->l2_ovlan == nf->l2_ovlan &&
3019                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3020                             mf->l2_ivlan == nf->l2_ivlan &&
3021                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3022                             !memcmp(mf->l2_addr, nf->l2_addr,
3023                                     RTE_ETHER_ADDR_LEN) &&
3024                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3025                                     RTE_ETHER_ADDR_LEN) &&
3026                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3027                                     RTE_ETHER_ADDR_LEN) &&
3028                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3029                                     RTE_ETHER_ADDR_LEN) &&
3030                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3031                                     sizeof(nf->src_ipaddr)) &&
3032                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3033                                     sizeof(nf->src_ipaddr_mask)) &&
3034                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3035                                     sizeof(nf->dst_ipaddr)) &&
3036                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3037                                     sizeof(nf->dst_ipaddr_mask))) {
3038                                 if (mvnic)
3039                                         *mvnic = vnic;
3040                                 return mf;
3041                         }
3042                 }
3043         }
3044         return NULL;
3045 }
3046
3047 static int
3048 bnxt_fdir_filter(struct rte_eth_dev *dev,
3049                  enum rte_filter_op filter_op,
3050                  void *arg)
3051 {
3052         struct bnxt *bp = dev->data->dev_private;
3053         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3054         struct bnxt_filter_info *filter, *match;
3055         struct bnxt_vnic_info *vnic, *mvnic;
3056         int ret = 0, i;
3057
3058         if (filter_op == RTE_ETH_FILTER_NOP)
3059                 return 0;
3060
3061         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3062                 return -EINVAL;
3063
3064         switch (filter_op) {
3065         case RTE_ETH_FILTER_ADD:
3066         case RTE_ETH_FILTER_DELETE:
3067                 /* FALLTHROUGH */
3068                 filter = bnxt_get_unused_filter(bp);
3069                 if (filter == NULL) {
3070                         PMD_DRV_LOG(ERR,
3071                                 "Not enough resources for a new flow.\n");
3072                         return -ENOMEM;
3073                 }
3074
3075                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3076                 if (ret != 0)
3077                         goto free_filter;
3078                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3079
3080                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3081                         vnic = &bp->vnic_info[0];
3082                 else
3083                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3084
3085                 match = bnxt_match_fdir(bp, filter, &mvnic);
3086                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3087                         if (match->dst_id == vnic->fw_vnic_id) {
3088                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3089                                 ret = -EEXIST;
3090                                 goto free_filter;
3091                         } else {
3092                                 match->dst_id = vnic->fw_vnic_id;
3093                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3094                                                                   match->dst_id,
3095                                                                   match);
3096                                 STAILQ_REMOVE(&mvnic->filter, match,
3097                                               bnxt_filter_info, next);
3098                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3099                                 PMD_DRV_LOG(ERR,
3100                                         "Filter with matching pattern exist\n");
3101                                 PMD_DRV_LOG(ERR,
3102                                         "Updated it to new destination q\n");
3103                                 goto free_filter;
3104                         }
3105                 }
3106                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3107                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3108                         ret = -ENOENT;
3109                         goto free_filter;
3110                 }
3111
3112                 if (filter_op == RTE_ETH_FILTER_ADD) {
3113                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3114                                                           filter->dst_id,
3115                                                           filter);
3116                         if (ret)
3117                                 goto free_filter;
3118                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3119                 } else {
3120                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3121                         STAILQ_REMOVE(&vnic->filter, match,
3122                                       bnxt_filter_info, next);
3123                         bnxt_free_filter(bp, match);
3124                         filter->fw_l2_filter_id = -1;
3125                         bnxt_free_filter(bp, filter);
3126                 }
3127                 break;
3128         case RTE_ETH_FILTER_FLUSH:
3129                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3130                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3131
3132                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3133                                 if (filter->filter_type ==
3134                                     HWRM_CFA_NTUPLE_FILTER) {
3135                                         ret =
3136                                         bnxt_hwrm_clear_ntuple_filter(bp,
3137                                                                       filter);
3138                                         STAILQ_REMOVE(&vnic->filter, filter,
3139                                                       bnxt_filter_info, next);
3140                                 }
3141                         }
3142                 }
3143                 return ret;
3144         case RTE_ETH_FILTER_UPDATE:
3145         case RTE_ETH_FILTER_STATS:
3146         case RTE_ETH_FILTER_INFO:
3147                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3148                 break;
3149         default:
3150                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3151                 ret = -EINVAL;
3152                 break;
3153         }
3154         return ret;
3155
3156 free_filter:
3157         filter->fw_l2_filter_id = -1;
3158         bnxt_free_filter(bp, filter);
3159         return ret;
3160 }
3161
3162 static int
3163 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3164                     enum rte_filter_type filter_type,
3165                     enum rte_filter_op filter_op, void *arg)
3166 {
3167         int ret = 0;
3168
3169         ret = is_bnxt_in_error(dev->data->dev_private);
3170         if (ret)
3171                 return ret;
3172
3173         switch (filter_type) {
3174         case RTE_ETH_FILTER_TUNNEL:
3175                 PMD_DRV_LOG(ERR,
3176                         "filter type: %d: To be implemented\n", filter_type);
3177                 break;
3178         case RTE_ETH_FILTER_FDIR:
3179                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3180                 break;
3181         case RTE_ETH_FILTER_NTUPLE:
3182                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3183                 break;
3184         case RTE_ETH_FILTER_ETHERTYPE:
3185                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3186                 break;
3187         case RTE_ETH_FILTER_GENERIC:
3188                 if (filter_op != RTE_ETH_FILTER_GET)
3189                         return -EINVAL;
3190                 *(const void **)arg = &bnxt_flow_ops;
3191                 break;
3192         default:
3193                 PMD_DRV_LOG(ERR,
3194                         "Filter type (%d) not supported", filter_type);
3195                 ret = -EINVAL;
3196                 break;
3197         }
3198         return ret;
3199 }
3200
3201 static const uint32_t *
3202 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3203 {
3204         static const uint32_t ptypes[] = {
3205                 RTE_PTYPE_L2_ETHER_VLAN,
3206                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3207                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3208                 RTE_PTYPE_L4_ICMP,
3209                 RTE_PTYPE_L4_TCP,
3210                 RTE_PTYPE_L4_UDP,
3211                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3212                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3213                 RTE_PTYPE_INNER_L4_ICMP,
3214                 RTE_PTYPE_INNER_L4_TCP,
3215                 RTE_PTYPE_INNER_L4_UDP,
3216                 RTE_PTYPE_UNKNOWN
3217         };
3218
3219         if (!dev->rx_pkt_burst)
3220                 return NULL;
3221
3222         return ptypes;
3223 }
3224
3225 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3226                          int reg_win)
3227 {
3228         uint32_t reg_base = *reg_arr & 0xfffff000;
3229         uint32_t win_off;
3230         int i;
3231
3232         for (i = 0; i < count; i++) {
3233                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3234                         return -ERANGE;
3235         }
3236         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3237         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3238         return 0;
3239 }
3240
3241 static int bnxt_map_ptp_regs(struct bnxt *bp)
3242 {
3243         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3244         uint32_t *reg_arr;
3245         int rc, i;
3246
3247         reg_arr = ptp->rx_regs;
3248         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3249         if (rc)
3250                 return rc;
3251
3252         reg_arr = ptp->tx_regs;
3253         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3254         if (rc)
3255                 return rc;
3256
3257         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3258                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3259
3260         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3261                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3262
3263         return 0;
3264 }
3265
3266 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3267 {
3268         rte_write32(0, (uint8_t *)bp->bar0 +
3269                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3270         rte_write32(0, (uint8_t *)bp->bar0 +
3271                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3272 }
3273
3274 static uint64_t bnxt_cc_read(struct bnxt *bp)
3275 {
3276         uint64_t ns;
3277
3278         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3279                               BNXT_GRCPF_REG_SYNC_TIME));
3280         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3281                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3282         return ns;
3283 }
3284
3285 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3286 {
3287         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3288         uint32_t fifo;
3289
3290         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3291                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3292         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3293                 return -EAGAIN;
3294
3295         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3296                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3297         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3298                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3299         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3300                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3301
3302         return 0;
3303 }
3304
3305 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3306 {
3307         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3308         struct bnxt_pf_info *pf = &bp->pf;
3309         uint16_t port_id;
3310         uint32_t fifo;
3311
3312         if (!ptp)
3313                 return -ENODEV;
3314
3315         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3316                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3317         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3318                 return -EAGAIN;
3319
3320         port_id = pf->port_id;
3321         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3322                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3323
3324         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3325                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3326         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3327 /*              bnxt_clr_rx_ts(bp);       TBD  */
3328                 return -EBUSY;
3329         }
3330
3331         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3332                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3333         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3334                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3335
3336         return 0;
3337 }
3338
3339 static int
3340 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3341 {
3342         uint64_t ns;
3343         struct bnxt *bp = dev->data->dev_private;
3344         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3345
3346         if (!ptp)
3347                 return 0;
3348
3349         ns = rte_timespec_to_ns(ts);
3350         /* Set the timecounters to a new value. */
3351         ptp->tc.nsec = ns;
3352
3353         return 0;
3354 }
3355
3356 static int
3357 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3358 {
3359         struct bnxt *bp = dev->data->dev_private;
3360         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3361         uint64_t ns, systime_cycles = 0;
3362         int rc = 0;
3363
3364         if (!ptp)
3365                 return 0;
3366
3367         if (BNXT_CHIP_THOR(bp))
3368                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3369                                              &systime_cycles);
3370         else
3371                 systime_cycles = bnxt_cc_read(bp);
3372
3373         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3374         *ts = rte_ns_to_timespec(ns);
3375
3376         return rc;
3377 }
3378 static int
3379 bnxt_timesync_enable(struct rte_eth_dev *dev)
3380 {
3381         struct bnxt *bp = dev->data->dev_private;
3382         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3383         uint32_t shift = 0;
3384         int rc;
3385
3386         if (!ptp)
3387                 return 0;
3388
3389         ptp->rx_filter = 1;
3390         ptp->tx_tstamp_en = 1;
3391         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3392
3393         rc = bnxt_hwrm_ptp_cfg(bp);
3394         if (rc)
3395                 return rc;
3396
3397         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3398         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3399         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3400
3401         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3402         ptp->tc.cc_shift = shift;
3403         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3404
3405         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3406         ptp->rx_tstamp_tc.cc_shift = shift;
3407         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3408
3409         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3410         ptp->tx_tstamp_tc.cc_shift = shift;
3411         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3412
3413         if (!BNXT_CHIP_THOR(bp))
3414                 bnxt_map_ptp_regs(bp);
3415
3416         return 0;
3417 }
3418
3419 static int
3420 bnxt_timesync_disable(struct rte_eth_dev *dev)
3421 {
3422         struct bnxt *bp = dev->data->dev_private;
3423         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3424
3425         if (!ptp)
3426                 return 0;
3427
3428         ptp->rx_filter = 0;
3429         ptp->tx_tstamp_en = 0;
3430         ptp->rxctl = 0;
3431
3432         bnxt_hwrm_ptp_cfg(bp);
3433
3434         if (!BNXT_CHIP_THOR(bp))
3435                 bnxt_unmap_ptp_regs(bp);
3436
3437         return 0;
3438 }
3439
3440 static int
3441 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3442                                  struct timespec *timestamp,
3443                                  uint32_t flags __rte_unused)
3444 {
3445         struct bnxt *bp = dev->data->dev_private;
3446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3447         uint64_t rx_tstamp_cycles = 0;
3448         uint64_t ns;
3449
3450         if (!ptp)
3451                 return 0;
3452
3453         if (BNXT_CHIP_THOR(bp))
3454                 rx_tstamp_cycles = ptp->rx_timestamp;
3455         else
3456                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3457
3458         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3459         *timestamp = rte_ns_to_timespec(ns);
3460         return  0;
3461 }
3462
3463 static int
3464 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3465                                  struct timespec *timestamp)
3466 {
3467         struct bnxt *bp = dev->data->dev_private;
3468         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3469         uint64_t tx_tstamp_cycles = 0;
3470         uint64_t ns;
3471         int rc = 0;
3472
3473         if (!ptp)
3474                 return 0;
3475
3476         if (BNXT_CHIP_THOR(bp))
3477                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3478                                              &tx_tstamp_cycles);
3479         else
3480                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3481
3482         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3483         *timestamp = rte_ns_to_timespec(ns);
3484
3485         return rc;
3486 }
3487
3488 static int
3489 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3490 {
3491         struct bnxt *bp = dev->data->dev_private;
3492         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3493
3494         if (!ptp)
3495                 return 0;
3496
3497         ptp->tc.nsec += delta;
3498
3499         return 0;
3500 }
3501
3502 static int
3503 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3504 {
3505         struct bnxt *bp = dev->data->dev_private;
3506         int rc;
3507         uint32_t dir_entries;
3508         uint32_t entry_length;
3509
3510         rc = is_bnxt_in_error(bp);
3511         if (rc)
3512                 return rc;
3513
3514         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3515                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3516                 bp->pdev->addr.devid, bp->pdev->addr.function);
3517
3518         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3519         if (rc != 0)
3520                 return rc;
3521
3522         return dir_entries * entry_length;
3523 }
3524
3525 static int
3526 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3527                 struct rte_dev_eeprom_info *in_eeprom)
3528 {
3529         struct bnxt *bp = dev->data->dev_private;
3530         uint32_t index;
3531         uint32_t offset;
3532         int rc;
3533
3534         rc = is_bnxt_in_error(bp);
3535         if (rc)
3536                 return rc;
3537
3538         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3539                 "len = %d\n", bp->pdev->addr.domain,
3540                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3541                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3542
3543         if (in_eeprom->offset == 0) /* special offset value to get directory */
3544                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3545                                                 in_eeprom->data);
3546
3547         index = in_eeprom->offset >> 24;
3548         offset = in_eeprom->offset & 0xffffff;
3549
3550         if (index != 0)
3551                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3552                                            in_eeprom->length, in_eeprom->data);
3553
3554         return 0;
3555 }
3556
3557 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3558 {
3559         switch (dir_type) {
3560         case BNX_DIR_TYPE_CHIMP_PATCH:
3561         case BNX_DIR_TYPE_BOOTCODE:
3562         case BNX_DIR_TYPE_BOOTCODE_2:
3563         case BNX_DIR_TYPE_APE_FW:
3564         case BNX_DIR_TYPE_APE_PATCH:
3565         case BNX_DIR_TYPE_KONG_FW:
3566         case BNX_DIR_TYPE_KONG_PATCH:
3567         case BNX_DIR_TYPE_BONO_FW:
3568         case BNX_DIR_TYPE_BONO_PATCH:
3569                 /* FALLTHROUGH */
3570                 return true;
3571         }
3572
3573         return false;
3574 }
3575
3576 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3577 {
3578         switch (dir_type) {
3579         case BNX_DIR_TYPE_AVS:
3580         case BNX_DIR_TYPE_EXP_ROM_MBA:
3581         case BNX_DIR_TYPE_PCIE:
3582         case BNX_DIR_TYPE_TSCF_UCODE:
3583         case BNX_DIR_TYPE_EXT_PHY:
3584         case BNX_DIR_TYPE_CCM:
3585         case BNX_DIR_TYPE_ISCSI_BOOT:
3586         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3587         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3588                 /* FALLTHROUGH */
3589                 return true;
3590         }
3591
3592         return false;
3593 }
3594
3595 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3596 {
3597         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3598                 bnxt_dir_type_is_other_exec_format(dir_type);
3599 }
3600
3601 static int
3602 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3603                 struct rte_dev_eeprom_info *in_eeprom)
3604 {
3605         struct bnxt *bp = dev->data->dev_private;
3606         uint8_t index, dir_op;
3607         uint16_t type, ext, ordinal, attr;
3608         int rc;
3609
3610         rc = is_bnxt_in_error(bp);
3611         if (rc)
3612                 return rc;
3613
3614         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3615                 "len = %d\n", bp->pdev->addr.domain,
3616                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3617                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3618
3619         if (!BNXT_PF(bp)) {
3620                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3621                 return -EINVAL;
3622         }
3623
3624         type = in_eeprom->magic >> 16;
3625
3626         if (type == 0xffff) { /* special value for directory operations */
3627                 index = in_eeprom->magic & 0xff;
3628                 dir_op = in_eeprom->magic >> 8;
3629                 if (index == 0)
3630                         return -EINVAL;
3631                 switch (dir_op) {
3632                 case 0x0e: /* erase */
3633                         if (in_eeprom->offset != ~in_eeprom->magic)
3634                                 return -EINVAL;
3635                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3636                 default:
3637                         return -EINVAL;
3638                 }
3639         }
3640
3641         /* Create or re-write an NVM item: */
3642         if (bnxt_dir_type_is_executable(type) == true)
3643                 return -EOPNOTSUPP;
3644         ext = in_eeprom->magic & 0xffff;
3645         ordinal = in_eeprom->offset >> 16;
3646         attr = in_eeprom->offset & 0xffff;
3647
3648         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3649                                      in_eeprom->data, in_eeprom->length);
3650 }
3651
3652 /*
3653  * Initialization
3654  */
3655
3656 static const struct eth_dev_ops bnxt_dev_ops = {
3657         .dev_infos_get = bnxt_dev_info_get_op,
3658         .dev_close = bnxt_dev_close_op,
3659         .dev_configure = bnxt_dev_configure_op,
3660         .dev_start = bnxt_dev_start_op,
3661         .dev_stop = bnxt_dev_stop_op,
3662         .dev_set_link_up = bnxt_dev_set_link_up_op,
3663         .dev_set_link_down = bnxt_dev_set_link_down_op,
3664         .stats_get = bnxt_stats_get_op,
3665         .stats_reset = bnxt_stats_reset_op,
3666         .rx_queue_setup = bnxt_rx_queue_setup_op,
3667         .rx_queue_release = bnxt_rx_queue_release_op,
3668         .tx_queue_setup = bnxt_tx_queue_setup_op,
3669         .tx_queue_release = bnxt_tx_queue_release_op,
3670         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3671         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3672         .reta_update = bnxt_reta_update_op,
3673         .reta_query = bnxt_reta_query_op,
3674         .rss_hash_update = bnxt_rss_hash_update_op,
3675         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3676         .link_update = bnxt_link_update_op,
3677         .promiscuous_enable = bnxt_promiscuous_enable_op,
3678         .promiscuous_disable = bnxt_promiscuous_disable_op,
3679         .allmulticast_enable = bnxt_allmulticast_enable_op,
3680         .allmulticast_disable = bnxt_allmulticast_disable_op,
3681         .mac_addr_add = bnxt_mac_addr_add_op,
3682         .mac_addr_remove = bnxt_mac_addr_remove_op,
3683         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3684         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3685         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3686         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3687         .vlan_filter_set = bnxt_vlan_filter_set_op,
3688         .vlan_offload_set = bnxt_vlan_offload_set_op,
3689         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3690         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3691         .mtu_set = bnxt_mtu_set_op,
3692         .mac_addr_set = bnxt_set_default_mac_addr_op,
3693         .xstats_get = bnxt_dev_xstats_get_op,
3694         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3695         .xstats_reset = bnxt_dev_xstats_reset_op,
3696         .fw_version_get = bnxt_fw_version_get,
3697         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3698         .rxq_info_get = bnxt_rxq_info_get_op,
3699         .txq_info_get = bnxt_txq_info_get_op,
3700         .dev_led_on = bnxt_dev_led_on_op,
3701         .dev_led_off = bnxt_dev_led_off_op,
3702         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3703         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3704         .rx_queue_count = bnxt_rx_queue_count_op,
3705         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3706         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3707         .rx_queue_start = bnxt_rx_queue_start,
3708         .rx_queue_stop = bnxt_rx_queue_stop,
3709         .tx_queue_start = bnxt_tx_queue_start,
3710         .tx_queue_stop = bnxt_tx_queue_stop,
3711         .filter_ctrl = bnxt_filter_ctrl_op,
3712         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3713         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3714         .get_eeprom           = bnxt_get_eeprom_op,
3715         .set_eeprom           = bnxt_set_eeprom_op,
3716         .timesync_enable      = bnxt_timesync_enable,
3717         .timesync_disable     = bnxt_timesync_disable,
3718         .timesync_read_time   = bnxt_timesync_read_time,
3719         .timesync_write_time   = bnxt_timesync_write_time,
3720         .timesync_adjust_time = bnxt_timesync_adjust_time,
3721         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3722         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3723 };
3724
3725 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3726 {
3727         uint32_t offset;
3728
3729         /* Only pre-map the reset GRC registers using window 3 */
3730         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3731                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3732
3733         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3734
3735         return offset;
3736 }
3737
3738 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3739 {
3740         struct bnxt_error_recovery_info *info = bp->recovery_info;
3741         uint32_t reg_base = 0xffffffff;
3742         int i;
3743
3744         /* Only pre-map the monitoring GRC registers using window 2 */
3745         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3746                 uint32_t reg = info->status_regs[i];
3747
3748                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3749                         continue;
3750
3751                 if (reg_base == 0xffffffff)
3752                         reg_base = reg & 0xfffff000;
3753                 if ((reg & 0xfffff000) != reg_base)
3754                         return -ERANGE;
3755
3756                 /* Use mask 0xffc as the Lower 2 bits indicates
3757                  * address space location
3758                  */
3759                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3760                                                 (reg & 0xffc);
3761         }
3762
3763         if (reg_base == 0xffffffff)
3764                 return 0;
3765
3766         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3767                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3768
3769         return 0;
3770 }
3771
3772 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3773 {
3774         struct bnxt_error_recovery_info *info = bp->recovery_info;
3775         uint32_t delay = info->delay_after_reset[index];
3776         uint32_t val = info->reset_reg_val[index];
3777         uint32_t reg = info->reset_reg[index];
3778         uint32_t type, offset;
3779
3780         type = BNXT_FW_STATUS_REG_TYPE(reg);
3781         offset = BNXT_FW_STATUS_REG_OFF(reg);
3782
3783         switch (type) {
3784         case BNXT_FW_STATUS_REG_TYPE_CFG:
3785                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3786                 break;
3787         case BNXT_FW_STATUS_REG_TYPE_GRC:
3788                 offset = bnxt_map_reset_regs(bp, offset);
3789                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3790                 break;
3791         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3792                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3793                 break;
3794         }
3795         /* wait on a specific interval of time until core reset is complete */
3796         if (delay)
3797                 rte_delay_ms(delay);
3798 }
3799
3800 static void bnxt_dev_cleanup(struct bnxt *bp)
3801 {
3802         bnxt_set_hwrm_link_config(bp, false);
3803         bp->link_info.link_up = 0;
3804         if (bp->dev_stopped == 0)
3805                 bnxt_dev_stop_op(bp->eth_dev);
3806
3807         bnxt_uninit_resources(bp, true);
3808 }
3809
3810 static int bnxt_restore_filters(struct bnxt *bp)
3811 {
3812         struct rte_eth_dev *dev = bp->eth_dev;
3813         int ret = 0;
3814
3815         if (dev->data->all_multicast)
3816                 ret = bnxt_allmulticast_enable_op(dev);
3817         if (dev->data->promiscuous)
3818                 ret = bnxt_promiscuous_enable_op(dev);
3819
3820         /* TODO restore other filters as well */
3821         return ret;
3822 }
3823
3824 static void bnxt_dev_recover(void *arg)
3825 {
3826         struct bnxt *bp = arg;
3827         int timeout = bp->fw_reset_max_msecs;
3828         int rc = 0;
3829
3830         /* Clear Error flag so that device re-init should happen */
3831         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3832
3833         do {
3834                 rc = bnxt_hwrm_ver_get(bp);
3835                 if (rc == 0)
3836                         break;
3837                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3838                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3839         } while (rc && timeout);
3840
3841         if (rc) {
3842                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3843                 goto err;
3844         }
3845
3846         rc = bnxt_init_resources(bp, true);
3847         if (rc) {
3848                 PMD_DRV_LOG(ERR,
3849                             "Failed to initialize resources after reset\n");
3850                 goto err;
3851         }
3852         /* clear reset flag as the device is initialized now */
3853         bp->flags &= ~BNXT_FLAG_FW_RESET;
3854
3855         rc = bnxt_dev_start_op(bp->eth_dev);
3856         if (rc) {
3857                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3858                 goto err;
3859         }
3860
3861         rc = bnxt_restore_filters(bp);
3862         if (rc)
3863                 goto err;
3864
3865         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3866         return;
3867 err:
3868         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3869         bnxt_uninit_resources(bp, false);
3870         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3871 }
3872
3873 void bnxt_dev_reset_and_resume(void *arg)
3874 {
3875         struct bnxt *bp = arg;
3876         int rc;
3877
3878         bnxt_dev_cleanup(bp);
3879
3880         bnxt_wait_for_device_shutdown(bp);
3881
3882         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3883                                bnxt_dev_recover, (void *)bp);
3884         if (rc)
3885                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3886 }
3887
3888 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3889 {
3890         struct bnxt_error_recovery_info *info = bp->recovery_info;
3891         uint32_t reg = info->status_regs[index];
3892         uint32_t type, offset, val = 0;
3893
3894         type = BNXT_FW_STATUS_REG_TYPE(reg);
3895         offset = BNXT_FW_STATUS_REG_OFF(reg);
3896
3897         switch (type) {
3898         case BNXT_FW_STATUS_REG_TYPE_CFG:
3899                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3900                 break;
3901         case BNXT_FW_STATUS_REG_TYPE_GRC:
3902                 offset = info->mapped_status_regs[index];
3903                 /* FALLTHROUGH */
3904         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3905                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3906                                        offset));
3907                 break;
3908         }
3909
3910         return val;
3911 }
3912
3913 static int bnxt_fw_reset_all(struct bnxt *bp)
3914 {
3915         struct bnxt_error_recovery_info *info = bp->recovery_info;
3916         uint32_t i;
3917         int rc = 0;
3918
3919         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3920                 /* Reset through master function driver */
3921                 for (i = 0; i < info->reg_array_cnt; i++)
3922                         bnxt_write_fw_reset_reg(bp, i);
3923                 /* Wait for time specified by FW after triggering reset */
3924                 rte_delay_ms(info->master_func_wait_period_after_reset);
3925         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3926                 /* Reset with the help of Kong processor */
3927                 rc = bnxt_hwrm_fw_reset(bp);
3928                 if (rc)
3929                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3930         }
3931
3932         return rc;
3933 }
3934
3935 static void bnxt_fw_reset_cb(void *arg)
3936 {
3937         struct bnxt *bp = arg;
3938         struct bnxt_error_recovery_info *info = bp->recovery_info;
3939         int rc = 0;
3940
3941         /* Only Master function can do FW reset */
3942         if (bnxt_is_master_func(bp) &&
3943             bnxt_is_recovery_enabled(bp)) {
3944                 rc = bnxt_fw_reset_all(bp);
3945                 if (rc) {
3946                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3947                         return;
3948                 }
3949         }
3950
3951         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3952          * EXCEPTION_FATAL_ASYNC event to all the functions
3953          * (including MASTER FUNC). After receiving this Async, all the active
3954          * drivers should treat this case as FW initiated recovery
3955          */
3956         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3957                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3958                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3959
3960                 /* To recover from error */
3961                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3962                                   (void *)bp);
3963         }
3964 }
3965
3966 /* Driver should poll FW heartbeat, reset_counter with the frequency
3967  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3968  * When the driver detects heartbeat stop or change in reset_counter,
3969  * it has to trigger a reset to recover from the error condition.
3970  * A “master PF” is the function who will have the privilege to
3971  * initiate the chimp reset. The master PF will be elected by the
3972  * firmware and will be notified through async message.
3973  */
3974 static void bnxt_check_fw_health(void *arg)
3975 {
3976         struct bnxt *bp = arg;
3977         struct bnxt_error_recovery_info *info = bp->recovery_info;
3978         uint32_t val = 0, wait_msec;
3979
3980         if (!info || !bnxt_is_recovery_enabled(bp) ||
3981             is_bnxt_in_error(bp))
3982                 return;
3983
3984         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3985         if (val == info->last_heart_beat)
3986                 goto reset;
3987
3988         info->last_heart_beat = val;
3989
3990         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3991         if (val != info->last_reset_counter)
3992                 goto reset;
3993
3994         info->last_reset_counter = val;
3995
3996         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3997                           bnxt_check_fw_health, (void *)bp);
3998
3999         return;
4000 reset:
4001         /* Stop DMA to/from device */
4002         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4003         bp->flags |= BNXT_FLAG_FW_RESET;
4004
4005         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4006
4007         if (bnxt_is_master_func(bp))
4008                 wait_msec = info->master_func_wait_period;
4009         else
4010                 wait_msec = info->normal_func_wait_period;
4011
4012         rte_eal_alarm_set(US_PER_MS * wait_msec,
4013                           bnxt_fw_reset_cb, (void *)bp);
4014 }
4015
4016 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4017 {
4018         uint32_t polling_freq;
4019
4020         if (!bnxt_is_recovery_enabled(bp))
4021                 return;
4022
4023         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4024                 return;
4025
4026         polling_freq = bp->recovery_info->driver_polling_freq;
4027
4028         rte_eal_alarm_set(US_PER_MS * polling_freq,
4029                           bnxt_check_fw_health, (void *)bp);
4030         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4031 }
4032
4033 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4034 {
4035         if (!bnxt_is_recovery_enabled(bp))
4036                 return;
4037
4038         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4039         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4040 }
4041
4042 static bool bnxt_vf_pciid(uint16_t id)
4043 {
4044         if (id == BROADCOM_DEV_ID_57304_VF ||
4045             id == BROADCOM_DEV_ID_57406_VF ||
4046             id == BROADCOM_DEV_ID_5731X_VF ||
4047             id == BROADCOM_DEV_ID_5741X_VF ||
4048             id == BROADCOM_DEV_ID_57414_VF ||
4049             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4050             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4051             id == BROADCOM_DEV_ID_58802_VF ||
4052             id == BROADCOM_DEV_ID_57500_VF1 ||
4053             id == BROADCOM_DEV_ID_57500_VF2)
4054                 return true;
4055         return false;
4056 }
4057
4058 bool bnxt_stratus_device(struct bnxt *bp)
4059 {
4060         uint16_t id = bp->pdev->id.device_id;
4061
4062         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4063             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4064             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4065                 return true;
4066         return false;
4067 }
4068
4069 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4070 {
4071         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4072         struct bnxt *bp = eth_dev->data->dev_private;
4073
4074         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4075         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4076         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4077         if (!bp->bar0 || !bp->doorbell_base) {
4078                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4079                 return -ENODEV;
4080         }
4081
4082         bp->eth_dev = eth_dev;
4083         bp->pdev = pci_dev;
4084
4085         return 0;
4086 }
4087
4088 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4089                                   struct bnxt_ctx_pg_info *ctx_pg,
4090                                   uint32_t mem_size,
4091                                   const char *suffix,
4092                                   uint16_t idx)
4093 {
4094         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4095         const struct rte_memzone *mz = NULL;
4096         char mz_name[RTE_MEMZONE_NAMESIZE];
4097         rte_iova_t mz_phys_addr;
4098         uint64_t valid_bits = 0;
4099         uint32_t sz;
4100         int i;
4101
4102         if (!mem_size)
4103                 return 0;
4104
4105         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4106                          BNXT_PAGE_SIZE;
4107         rmem->page_size = BNXT_PAGE_SIZE;
4108         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4109         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4110         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4111
4112         valid_bits = PTU_PTE_VALID;
4113
4114         if (rmem->nr_pages > 1) {
4115                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4116                          "bnxt_ctx_pg_tbl%s_%x_%d",
4117                          suffix, idx, bp->eth_dev->data->port_id);
4118                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4119                 mz = rte_memzone_lookup(mz_name);
4120                 if (!mz) {
4121                         mz = rte_memzone_reserve_aligned(mz_name,
4122                                                 rmem->nr_pages * 8,
4123                                                 SOCKET_ID_ANY,
4124                                                 RTE_MEMZONE_2MB |
4125                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4126                                                 RTE_MEMZONE_IOVA_CONTIG,
4127                                                 BNXT_PAGE_SIZE);
4128                         if (mz == NULL)
4129                                 return -ENOMEM;
4130                 }
4131
4132                 memset(mz->addr, 0, mz->len);
4133                 mz_phys_addr = mz->iova;
4134                 if ((unsigned long)mz->addr == mz_phys_addr) {
4135                         PMD_DRV_LOG(DEBUG,
4136                                     "physical address same as virtual\n");
4137                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4138                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4139                         if (mz_phys_addr == RTE_BAD_IOVA) {
4140                                 PMD_DRV_LOG(ERR,
4141                                         "unable to map addr to phys memory\n");
4142                                 return -ENOMEM;
4143                         }
4144                 }
4145                 rte_mem_lock_page(((char *)mz->addr));
4146
4147                 rmem->pg_tbl = mz->addr;
4148                 rmem->pg_tbl_map = mz_phys_addr;
4149                 rmem->pg_tbl_mz = mz;
4150         }
4151
4152         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4153                  suffix, idx, bp->eth_dev->data->port_id);
4154         mz = rte_memzone_lookup(mz_name);
4155         if (!mz) {
4156                 mz = rte_memzone_reserve_aligned(mz_name,
4157                                                  mem_size,
4158                                                  SOCKET_ID_ANY,
4159                                                  RTE_MEMZONE_1GB |
4160                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4161                                                  RTE_MEMZONE_IOVA_CONTIG,
4162                                                  BNXT_PAGE_SIZE);
4163                 if (mz == NULL)
4164                         return -ENOMEM;
4165         }
4166
4167         memset(mz->addr, 0, mz->len);
4168         mz_phys_addr = mz->iova;
4169         if ((unsigned long)mz->addr == mz_phys_addr) {
4170                 PMD_DRV_LOG(DEBUG,
4171                             "Memzone physical address same as virtual.\n");
4172                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4173                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4174                         rte_mem_lock_page(((char *)mz->addr) + sz);
4175                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4176                 if (mz_phys_addr == RTE_BAD_IOVA) {
4177                         PMD_DRV_LOG(ERR,
4178                                     "unable to map addr to phys memory\n");
4179                         return -ENOMEM;
4180                 }
4181         }
4182
4183         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4184                 rte_mem_lock_page(((char *)mz->addr) + sz);
4185                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4186                 rmem->dma_arr[i] = mz_phys_addr + sz;
4187
4188                 if (rmem->nr_pages > 1) {
4189                         if (i == rmem->nr_pages - 2 &&
4190                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4191                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4192                         else if (i == rmem->nr_pages - 1 &&
4193                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4194                                 valid_bits |= PTU_PTE_LAST;
4195
4196                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4197                                                            valid_bits);
4198                 }
4199         }
4200
4201         rmem->mz = mz;
4202         if (rmem->vmem_size)
4203                 rmem->vmem = (void **)mz->addr;
4204         rmem->dma_arr[0] = mz_phys_addr;
4205         return 0;
4206 }
4207
4208 static void bnxt_free_ctx_mem(struct bnxt *bp)
4209 {
4210         int i;
4211
4212         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4213                 return;
4214
4215         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4216         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4217         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4218         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4219         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4220         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4221         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4222         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4223         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4224         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4225         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4226
4227         for (i = 0; i < BNXT_MAX_Q; i++) {
4228                 if (bp->ctx->tqm_mem[i])
4229                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4230         }
4231
4232         rte_free(bp->ctx);
4233         bp->ctx = NULL;
4234 }
4235
4236 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4237
4238 #define min_t(type, x, y) ({                    \
4239         type __min1 = (x);                      \
4240         type __min2 = (y);                      \
4241         __min1 < __min2 ? __min1 : __min2; })
4242
4243 #define max_t(type, x, y) ({                    \
4244         type __max1 = (x);                      \
4245         type __max2 = (y);                      \
4246         __max1 > __max2 ? __max1 : __max2; })
4247
4248 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4249
4250 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4251 {
4252         struct bnxt_ctx_pg_info *ctx_pg;
4253         struct bnxt_ctx_mem_info *ctx;
4254         uint32_t mem_size, ena, entries;
4255         int i, rc;
4256
4257         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4258         if (rc) {
4259                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4260                 return rc;
4261         }
4262         ctx = bp->ctx;
4263         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4264                 return 0;
4265
4266         ctx_pg = &ctx->qp_mem;
4267         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4268         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4269         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4270         if (rc)
4271                 return rc;
4272
4273         ctx_pg = &ctx->srq_mem;
4274         ctx_pg->entries = ctx->srq_max_l2_entries;
4275         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4276         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4277         if (rc)
4278                 return rc;
4279
4280         ctx_pg = &ctx->cq_mem;
4281         ctx_pg->entries = ctx->cq_max_l2_entries;
4282         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4283         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4284         if (rc)
4285                 return rc;
4286
4287         ctx_pg = &ctx->vnic_mem;
4288         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4289                 ctx->vnic_max_ring_table_entries;
4290         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4291         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4292         if (rc)
4293                 return rc;
4294
4295         ctx_pg = &ctx->stat_mem;
4296         ctx_pg->entries = ctx->stat_max_entries;
4297         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4298         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4299         if (rc)
4300                 return rc;
4301
4302         entries = ctx->qp_max_l2_entries +
4303                   ctx->vnic_max_vnic_entries +
4304                   ctx->tqm_min_entries_per_ring;
4305         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4306         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4307                           ctx->tqm_max_entries_per_ring);
4308         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4309                 ctx_pg = ctx->tqm_mem[i];
4310                 /* use min tqm entries for now. */
4311                 ctx_pg->entries = entries;
4312                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4313                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4314                 if (rc)
4315                         return rc;
4316                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4317         }
4318
4319         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4320         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4321         if (rc)
4322                 PMD_DRV_LOG(ERR,
4323                             "Failed to configure context mem: rc = %d\n", rc);
4324         else
4325                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4326
4327         return rc;
4328 }
4329
4330 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4331 {
4332         struct rte_pci_device *pci_dev = bp->pdev;
4333         char mz_name[RTE_MEMZONE_NAMESIZE];
4334         const struct rte_memzone *mz = NULL;
4335         uint32_t total_alloc_len;
4336         rte_iova_t mz_phys_addr;
4337
4338         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4339                 return 0;
4340
4341         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4342                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4343                  pci_dev->addr.bus, pci_dev->addr.devid,
4344                  pci_dev->addr.function, "rx_port_stats");
4345         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4346         mz = rte_memzone_lookup(mz_name);
4347         total_alloc_len =
4348                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4349                                        sizeof(struct rx_port_stats_ext) + 512);
4350         if (!mz) {
4351                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4352                                          SOCKET_ID_ANY,
4353                                          RTE_MEMZONE_2MB |
4354                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4355                                          RTE_MEMZONE_IOVA_CONTIG);
4356                 if (mz == NULL)
4357                         return -ENOMEM;
4358         }
4359         memset(mz->addr, 0, mz->len);
4360         mz_phys_addr = mz->iova;
4361         if ((unsigned long)mz->addr == mz_phys_addr) {
4362                 PMD_DRV_LOG(DEBUG,
4363                             "Memzone physical address same as virtual.\n");
4364                 PMD_DRV_LOG(DEBUG,
4365                             "Using rte_mem_virt2iova()\n");
4366                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4367                 if (mz_phys_addr == RTE_BAD_IOVA) {
4368                         PMD_DRV_LOG(ERR,
4369                                     "Can't map address to physical memory\n");
4370                         return -ENOMEM;
4371                 }
4372         }
4373
4374         bp->rx_mem_zone = (const void *)mz;
4375         bp->hw_rx_port_stats = mz->addr;
4376         bp->hw_rx_port_stats_map = mz_phys_addr;
4377
4378         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4379                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4380                  pci_dev->addr.bus, pci_dev->addr.devid,
4381                  pci_dev->addr.function, "tx_port_stats");
4382         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4383         mz = rte_memzone_lookup(mz_name);
4384         total_alloc_len =
4385                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4386                                        sizeof(struct tx_port_stats_ext) + 512);
4387         if (!mz) {
4388                 mz = rte_memzone_reserve(mz_name,
4389                                          total_alloc_len,
4390                                          SOCKET_ID_ANY,
4391                                          RTE_MEMZONE_2MB |
4392                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4393                                          RTE_MEMZONE_IOVA_CONTIG);
4394                 if (mz == NULL)
4395                         return -ENOMEM;
4396         }
4397         memset(mz->addr, 0, mz->len);
4398         mz_phys_addr = mz->iova;
4399         if ((unsigned long)mz->addr == mz_phys_addr) {
4400                 PMD_DRV_LOG(DEBUG,
4401                             "Memzone physical address same as virtual\n");
4402                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4403                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4404                 if (mz_phys_addr == RTE_BAD_IOVA) {
4405                         PMD_DRV_LOG(ERR,
4406                                     "Can't map address to physical memory\n");
4407                         return -ENOMEM;
4408                 }
4409         }
4410
4411         bp->tx_mem_zone = (const void *)mz;
4412         bp->hw_tx_port_stats = mz->addr;
4413         bp->hw_tx_port_stats_map = mz_phys_addr;
4414         bp->flags |= BNXT_FLAG_PORT_STATS;
4415
4416         /* Display extended statistics if FW supports it */
4417         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4418             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4419             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4420                 return 0;
4421
4422         bp->hw_rx_port_stats_ext = (void *)
4423                 ((uint8_t *)bp->hw_rx_port_stats +
4424                  sizeof(struct rx_port_stats));
4425         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4426                 sizeof(struct rx_port_stats);
4427         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4428
4429         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4430             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4431                 bp->hw_tx_port_stats_ext = (void *)
4432                         ((uint8_t *)bp->hw_tx_port_stats +
4433                          sizeof(struct tx_port_stats));
4434                 bp->hw_tx_port_stats_ext_map =
4435                         bp->hw_tx_port_stats_map +
4436                         sizeof(struct tx_port_stats);
4437                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4438         }
4439
4440         return 0;
4441 }
4442
4443 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4444 {
4445         struct bnxt *bp = eth_dev->data->dev_private;
4446         int rc = 0;
4447
4448         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4449                                                RTE_ETHER_ADDR_LEN *
4450                                                bp->max_l2_ctx,
4451                                                0);
4452         if (eth_dev->data->mac_addrs == NULL) {
4453                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4454                 return -ENOMEM;
4455         }
4456
4457         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4458                 if (BNXT_PF(bp))
4459                         return -EINVAL;
4460
4461                 /* Generate a random MAC address, if none was assigned by PF */
4462                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4463                 bnxt_eth_hw_addr_random(bp->mac_addr);
4464                 PMD_DRV_LOG(INFO,
4465                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4466                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4467                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4468
4469                 rc = bnxt_hwrm_set_mac(bp);
4470                 if (!rc)
4471                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4472                                RTE_ETHER_ADDR_LEN);
4473                 return rc;
4474         }
4475
4476         /* Copy the permanent MAC from the FUNC_QCAPS response */
4477         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4478         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4479
4480         return rc;
4481 }
4482
4483 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4484 {
4485         int rc = 0;
4486
4487         /* MAC is already configured in FW */
4488         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4489                 return 0;
4490
4491         /* Restore the old MAC configured */
4492         rc = bnxt_hwrm_set_mac(bp);
4493         if (rc)
4494                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4495
4496         return rc;
4497 }
4498
4499 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4500 {
4501         if (!BNXT_PF(bp))
4502                 return;
4503
4504 #define ALLOW_FUNC(x)   \
4505         { \
4506                 uint32_t arg = (x); \
4507                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4508                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4509         }
4510
4511         /* Forward all requests if firmware is new enough */
4512         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4513              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4514             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4515                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4516         } else {
4517                 PMD_DRV_LOG(WARNING,
4518                             "Firmware too old for VF mailbox functionality\n");
4519                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4520         }
4521
4522         /*
4523          * The following are used for driver cleanup. If we disallow these,
4524          * VF drivers can't clean up cleanly.
4525          */
4526         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4527         ALLOW_FUNC(HWRM_VNIC_FREE);
4528         ALLOW_FUNC(HWRM_RING_FREE);
4529         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4530         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4531         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4532         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4533         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4534         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4535 }
4536
4537 static int bnxt_init_fw(struct bnxt *bp)
4538 {
4539         uint16_t mtu;
4540         int rc = 0;
4541
4542         rc = bnxt_hwrm_ver_get(bp);
4543         if (rc)
4544                 return rc;
4545
4546         rc = bnxt_hwrm_func_reset(bp);
4547         if (rc)
4548                 return -EIO;
4549
4550         rc = bnxt_hwrm_vnic_qcaps(bp);
4551         if (rc)
4552                 return rc;
4553
4554         rc = bnxt_hwrm_queue_qportcfg(bp);
4555         if (rc)
4556                 return rc;
4557
4558         /* Get the MAX capabilities for this function.
4559          * This function also allocates context memory for TQM rings and
4560          * informs the firmware about this allocated backing store memory.
4561          */
4562         rc = bnxt_hwrm_func_qcaps(bp);
4563         if (rc)
4564                 return rc;
4565
4566         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4567         if (rc)
4568                 return rc;
4569
4570         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4571         if (rc)
4572                 return rc;
4573
4574         /* Get the adapter error recovery support info */
4575         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4576         if (rc)
4577                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4578
4579         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4580             mtu != bp->eth_dev->data->mtu)
4581                 bp->eth_dev->data->mtu = mtu;
4582
4583         bnxt_hwrm_port_led_qcaps(bp);
4584
4585         return 0;
4586 }
4587
4588 static int
4589 bnxt_init_locks(struct bnxt *bp)
4590 {
4591         int err;
4592
4593         err = pthread_mutex_init(&bp->flow_lock, NULL);
4594         if (err) {
4595                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4596                 return err;
4597         }
4598
4599         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4600         if (err)
4601                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4602         return err;
4603 }
4604
4605 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4606 {
4607         int rc;
4608
4609         rc = bnxt_init_fw(bp);
4610         if (rc)
4611                 return rc;
4612
4613         if (!reconfig_dev) {
4614                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4615                 if (rc)
4616                         return rc;
4617         } else {
4618                 rc = bnxt_restore_dflt_mac(bp);
4619                 if (rc)
4620                         return rc;
4621         }
4622
4623         bnxt_config_vf_req_fwd(bp);
4624
4625         rc = bnxt_hwrm_func_driver_register(bp);
4626         if (rc) {
4627                 PMD_DRV_LOG(ERR, "Failed to register driver");
4628                 return -EBUSY;
4629         }
4630
4631         if (BNXT_PF(bp)) {
4632                 if (bp->pdev->max_vfs) {
4633                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4634                         if (rc) {
4635                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4636                                 return rc;
4637                         }
4638                 } else {
4639                         rc = bnxt_hwrm_allocate_pf_only(bp);
4640                         if (rc) {
4641                                 PMD_DRV_LOG(ERR,
4642                                             "Failed to allocate PF resources");
4643                                 return rc;
4644                         }
4645                 }
4646         }
4647
4648         rc = bnxt_alloc_mem(bp, reconfig_dev);
4649         if (rc)
4650                 return rc;
4651
4652         rc = bnxt_setup_int(bp);
4653         if (rc)
4654                 return rc;
4655
4656         bnxt_init_nic(bp);
4657
4658         rc = bnxt_request_int(bp);
4659         if (rc)
4660                 return rc;
4661
4662         rc = bnxt_init_locks(bp);
4663         if (rc)
4664                 return rc;
4665
4666         return 0;
4667 }
4668
4669 static int
4670 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4671 {
4672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4673         static int version_printed;
4674         struct bnxt *bp;
4675         int rc;
4676
4677         if (version_printed++ == 0)
4678                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4679
4680         eth_dev->dev_ops = &bnxt_dev_ops;
4681         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4682         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4683
4684         /*
4685          * For secondary processes, we don't initialise any further
4686          * as primary has already done this work.
4687          */
4688         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4689                 return 0;
4690
4691         rte_eth_copy_pci_info(eth_dev, pci_dev);
4692
4693         bp = eth_dev->data->dev_private;
4694
4695         bp->dev_stopped = 1;
4696
4697         if (bnxt_vf_pciid(pci_dev->id.device_id))
4698                 bp->flags |= BNXT_FLAG_VF;
4699
4700         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4701             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4702             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4703             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4704             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4705                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4706
4707         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4708             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4709             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4710             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4711                 bp->flags |= BNXT_FLAG_STINGRAY;
4712
4713         rc = bnxt_init_board(eth_dev);
4714         if (rc) {
4715                 PMD_DRV_LOG(ERR,
4716                             "Failed to initialize board rc: %x\n", rc);
4717                 return rc;
4718         }
4719
4720         rc = bnxt_alloc_hwrm_resources(bp);
4721         if (rc) {
4722                 PMD_DRV_LOG(ERR,
4723                             "Failed to allocate hwrm resource rc: %x\n", rc);
4724                 goto error_free;
4725         }
4726         rc = bnxt_init_resources(bp, false);
4727         if (rc)
4728                 goto error_free;
4729
4730         rc = bnxt_alloc_stats_mem(bp);
4731         if (rc)
4732                 goto error_free;
4733
4734         PMD_DRV_LOG(INFO,
4735                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4736                     pci_dev->mem_resource[0].phys_addr,
4737                     pci_dev->mem_resource[0].addr);
4738
4739         return 0;
4740
4741 error_free:
4742         bnxt_dev_uninit(eth_dev);
4743         return rc;
4744 }
4745
4746 static void
4747 bnxt_uninit_locks(struct bnxt *bp)
4748 {
4749         pthread_mutex_destroy(&bp->flow_lock);
4750         pthread_mutex_destroy(&bp->def_cp_lock);
4751 }
4752
4753 static int
4754 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4755 {
4756         int rc;
4757
4758         bnxt_free_int(bp);
4759         bnxt_free_mem(bp, reconfig_dev);
4760         bnxt_hwrm_func_buf_unrgtr(bp);
4761         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4762         bp->flags &= ~BNXT_FLAG_REGISTERED;
4763         bnxt_free_ctx_mem(bp);
4764         if (!reconfig_dev) {
4765                 bnxt_free_hwrm_resources(bp);
4766
4767                 if (bp->recovery_info != NULL) {
4768                         rte_free(bp->recovery_info);
4769                         bp->recovery_info = NULL;
4770                 }
4771         }
4772
4773         rte_free(bp->ptp_cfg);
4774         bp->ptp_cfg = NULL;
4775         return rc;
4776 }
4777
4778 static int
4779 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4780 {
4781         struct bnxt *bp = eth_dev->data->dev_private;
4782         int rc;
4783
4784         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4785                 return -EPERM;
4786
4787         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4788
4789         rc = bnxt_uninit_resources(bp, false);
4790
4791         if (bp->grp_info != NULL) {
4792                 rte_free(bp->grp_info);
4793                 bp->grp_info = NULL;
4794         }
4795
4796         if (bp->tx_mem_zone) {
4797                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4798                 bp->tx_mem_zone = NULL;
4799         }
4800
4801         if (bp->rx_mem_zone) {
4802                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4803                 bp->rx_mem_zone = NULL;
4804         }
4805
4806         if (bp->dev_stopped == 0)
4807                 bnxt_dev_close_op(eth_dev);
4808         if (bp->pf.vf_info)
4809                 rte_free(bp->pf.vf_info);
4810         eth_dev->dev_ops = NULL;
4811         eth_dev->rx_pkt_burst = NULL;
4812         eth_dev->tx_pkt_burst = NULL;
4813
4814         bnxt_uninit_locks(bp);
4815
4816         return rc;
4817 }
4818
4819 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4820         struct rte_pci_device *pci_dev)
4821 {
4822         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4823                 bnxt_dev_init);
4824 }
4825
4826 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4827 {
4828         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4829                 return rte_eth_dev_pci_generic_remove(pci_dev,
4830                                 bnxt_dev_uninit);
4831         else
4832                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4833 }
4834
4835 static struct rte_pci_driver bnxt_rte_pmd = {
4836         .id_table = bnxt_pci_id_map,
4837         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4838         .probe = bnxt_pci_probe,
4839         .remove = bnxt_pci_remove,
4840 };
4841
4842 static bool
4843 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4844 {
4845         if (strcmp(dev->device->driver->name, drv->driver.name))
4846                 return false;
4847
4848         return true;
4849 }
4850
4851 bool is_bnxt_supported(struct rte_eth_dev *dev)
4852 {
4853         return is_device_supported(dev, &bnxt_rte_pmd);
4854 }
4855
4856 RTE_INIT(bnxt_init_log)
4857 {
4858         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4859         if (bnxt_logtype_driver >= 0)
4860                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4861 }
4862
4863 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4864 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4865 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");