drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 155                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 156
 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 158                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 159                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 160                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 162                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 163                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 164                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 165                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 166                                      DEV_RX_OFFLOAD_TCP_LRO)
 167
 168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 175
 176 int is_bnxt_in_error(struct bnxt *bp)
 177 {
 178         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 179                 return -EIO;
 180         if (bp->flags & BNXT_FLAG_FW_RESET)
 181                 return -EBUSY;
 182
 183         return 0;
 184 }
 185
 186 /***********************/
 187
 188 /*
 189  * High level utility functions
 190  */
 191
 192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 193 {
 194         if (!BNXT_CHIP_THOR(bp))
 195                 return 1;
 196
 197         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 198                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 199                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 200 }
 201
 202 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 203 {
 204         if (!BNXT_CHIP_THOR(bp))
 205                 return HW_HASH_INDEX_SIZE;
 206
 207         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 208 }
 209
 210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 211 {
 212         bnxt_free_filter_mem(bp);
 213         bnxt_free_vnic_attributes(bp);
 214         bnxt_free_vnic_mem(bp);
 215
 216         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 217          * If the number of rings change across fw update,
 218          * we don't have much choice except to warn the user.
 219          */
 220         if (!reconfig) {
 221                 bnxt_free_stats(bp);
 222                 bnxt_free_tx_rings(bp);
 223                 bnxt_free_rx_rings(bp);
 224         }
 225         bnxt_free_async_cp_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         return 0;
 257
 258 alloc_mem_err:
 259         bnxt_free_mem(bp, reconfig);
 260         return rc;
 261 }
 262
 263 static int bnxt_init_chip(struct bnxt *bp)
 264 {
 265         struct bnxt_rx_queue *rxq;
 266         struct rte_eth_link new;
 267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 268         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 269         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 270         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 271         uint32_t intr_vector = 0;
 272         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 273         uint32_t vec = BNXT_MISC_VEC_ID;
 274         unsigned int i, j;
 275         int rc;
 276
 277         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 278                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 279                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 280                 bp->flags |= BNXT_FLAG_JUMBO;
 281         } else {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 283                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags &= ~BNXT_FLAG_JUMBO;
 285         }
 286
 287         /* THOR does not support ring groups.
 288          * But we will use the array to save RSS context IDs.
 289          */
 290         if (BNXT_CHIP_THOR(bp))
 291                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 292
 293         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 294         if (rc) {
 295                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 296                 goto err_out;
 297         }
 298
 299         rc = bnxt_alloc_hwrm_rings(bp);
 300         if (rc) {
 301                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 302                 goto err_out;
 303         }
 304
 305         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 306         if (rc) {
 307                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         rc = bnxt_mq_rx_configure(bp);
 312         if (rc) {
 313                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 314                 goto err_out;
 315         }
 316
 317         /* VNIC configuration */
 318         for (i = 0; i < bp->nr_vnics; i++) {
 319                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 320                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 321
 322                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 323                 if (rc)
 324                         goto err_out;
 325
 326                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 327                             i, vnic, vnic->fw_grp_ids);
 328
 329                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 330                 if (rc) {
 331                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 332                                 i, rc);
 333                         goto err_out;
 334                 }
 335
 336                 /* Alloc RSS context only if RSS mode is enabled */
 337                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 338                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 339
 340                         rc = 0;
 341                         for (j = 0; j < nr_ctxs; j++) {
 342                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 343                                 if (rc)
 344                                         break;
 345                         }
 346                         if (rc) {
 347                                 PMD_DRV_LOG(ERR,
 348                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 349                                   i, j, rc);
 350                                 goto err_out;
 351                         }
 352                         vnic->num_lb_ctxts = nr_ctxs;
 353                 }
 354
 355                 /*
 356                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 357                  * setting is not available at this time, it will not be
 358                  * configured correctly in the CFA.
 359                  */
 360                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 361                         vnic->vlan_strip = true;
 362                 else
 363                         vnic->vlan_strip = false;
 364
 365                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 366                 if (rc) {
 367                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 368                                 i, rc);
 369                         goto err_out;
 370                 }
 371
 372                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 373                 if (rc) {
 374                         PMD_DRV_LOG(ERR,
 375                                 "HWRM vnic %d filter failure rc: %x\n",
 376                                 i, rc);
 377                         goto err_out;
 378                 }
 379
 380                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 381                         rxq = bp->eth_dev->data->rx_queues[j];
 382
 383                         PMD_DRV_LOG(DEBUG,
 384                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 385                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 386
 387                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 388                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 389                 }
 390
 391                 rc = bnxt_vnic_rss_configure(bp, vnic);
 392                 if (rc) {
 393                         PMD_DRV_LOG(ERR,
 394                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 395                         goto err_out;
 396                 }
 397
 398                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 399
 400                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 401                     DEV_RX_OFFLOAD_TCP_LRO)
 402                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 403                 else
 404                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 405         }
 406         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 407         if (rc) {
 408                 PMD_DRV_LOG(ERR,
 409                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 410                 goto err_out;
 411         }
 412
 413         /* check and configure queue intr-vector mapping */
 414         if ((rte_intr_cap_multiple(intr_handle) ||
 415              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 416             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 417                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 418                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 419                 if (intr_vector > bp->rx_cp_nr_rings) {
 420                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 421                                         bp->rx_cp_nr_rings);
 422                         return -ENOTSUP;
 423                 }
 424                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 425                 if (rc)
 426                         return rc;
 427         }
 428
 429         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 430                 intr_handle->intr_vec =
 431                         rte_zmalloc("intr_vec",
 432                                     bp->eth_dev->data->nb_rx_queues *
 433                                     sizeof(int), 0);
 434                 if (intr_handle->intr_vec == NULL) {
 435                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 436                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 437                         rc = -ENOMEM;
 438                         goto err_disable;
 439                 }
 440                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 441                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 442                          intr_handle->intr_vec, intr_handle->nb_efd,
 443                         intr_handle->max_intr);
 444                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 445                      queue_id++) {
 446                         intr_handle->intr_vec[queue_id] =
 447                                                         vec + BNXT_RX_VEC_START;
 448                         if (vec < base + intr_handle->nb_efd - 1)
 449                                 vec++;
 450                 }
 451         }
 452
 453         /* enable uio/vfio intr/eventfd mapping */
 454         rc = rte_intr_enable(intr_handle);
 455         if (rc)
 456                 goto err_free;
 457
 458         rc = bnxt_get_hwrm_link_config(bp, &new);
 459         if (rc) {
 460                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 461                 goto err_free;
 462         }
 463
 464         if (!bp->link_info.link_up) {
 465                 rc = bnxt_set_hwrm_link_config(bp, true);
 466                 if (rc) {
 467                         PMD_DRV_LOG(ERR,
 468                                 "HWRM link config failure rc: %x\n", rc);
 469                         goto err_free;
 470                 }
 471         }
 472         bnxt_print_link_info(bp->eth_dev);
 473
 474         return 0;
 475
 476 err_free:
 477         rte_free(intr_handle->intr_vec);
 478 err_disable:
 479         rte_intr_efd_disable(intr_handle);
 480 err_out:
 481         /* Some of the error status returned by FW may not be from errno.h */
 482         if (rc > 0)
 483                 rc = -EIO;
 484
 485         return rc;
 486 }
 487
 488 static int bnxt_shutdown_nic(struct bnxt *bp)
 489 {
 490         bnxt_free_all_hwrm_resources(bp);
 491         bnxt_free_all_filters(bp);
 492         bnxt_free_all_vnics(bp);
 493         return 0;
 494 }
 495
 496 static int bnxt_init_nic(struct bnxt *bp)
 497 {
 498         int rc;
 499
 500         if (BNXT_HAS_RING_GRPS(bp)) {
 501                 rc = bnxt_init_ring_grps(bp);
 502                 if (rc)
 503                         return rc;
 504         }
 505
 506         bnxt_init_vnics(bp);
 507         bnxt_init_filters(bp);
 508
 509         return 0;
 510 }
 511
 512 /*
 513  * Device configuration and status function
 514  */
 515
 516 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 517                                 struct rte_eth_dev_info *dev_info)
 518 {
 519         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 520         struct bnxt *bp = eth_dev->data->dev_private;
 521         uint16_t max_vnics, i, j, vpool, vrxq;
 522         unsigned int max_rx_rings;
 523         int rc;
 524
 525         rc = is_bnxt_in_error(bp);
 526         if (rc)
 527                 return rc;
 528
 529         /* MAC Specifics */
 530         dev_info->max_mac_addrs = bp->max_l2_ctx;
 531         dev_info->max_hash_mac_addrs = 0;
 532
 533         /* PF/VF specifics */
 534         if (BNXT_PF(bp))
 535                 dev_info->max_vfs = pdev->max_vfs;
 536
 537         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 538         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 539         dev_info->max_rx_queues = max_rx_rings;
 540         dev_info->max_tx_queues = max_rx_rings;
 541         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 542         dev_info->hash_key_size = 40;
 543         max_vnics = bp->max_vnics;
 544
 545         /* MTU specifics */
 546         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 547         dev_info->max_mtu = BNXT_MAX_MTU;
 548
 549         /* Fast path specifics */
 550         dev_info->min_rx_bufsize = 1;
 551         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 552
 553         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 554         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 555                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 556         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 557         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 558
 559         /* *INDENT-OFF* */
 560         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 561                 .rx_thresh = {
 562                         .pthresh = 8,
 563                         .hthresh = 8,
 564                         .wthresh = 0,
 565                 },
 566                 .rx_free_thresh = 32,
 567                 /* If no descriptors available, pkts are dropped by default */
 568                 .rx_drop_en = 1,
 569         };
 570
 571         dev_info->default_txconf = (struct rte_eth_txconf) {
 572                 .tx_thresh = {
 573                         .pthresh = 32,
 574                         .hthresh = 0,
 575                         .wthresh = 0,
 576                 },
 577                 .tx_free_thresh = 32,
 578                 .tx_rs_thresh = 32,
 579         };
 580         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 581
 582         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 583         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 585         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 586         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 587
 588         /* *INDENT-ON* */
 589
 590         /*
 591          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 592          *       need further investigation.
 593          */
 594
 595         /* VMDq resources */
 596         vpool = 64; /* ETH_64_POOLS */
 597         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 598         for (i = 0; i < 4; vpool >>= 1, i++) {
 599                 if (max_vnics > vpool) {
 600                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 601                                 if (dev_info->max_rx_queues > vrxq) {
 602                                         if (vpool > vrxq)
 603                                                 vpool = vrxq;
 604                                         goto found;
 605                                 }
 606                         }
 607                         /* Not enough resources to support VMDq */
 608                         break;
 609                 }
 610         }
 611         /* Not enough resources to support VMDq */
 612         vpool = 0;
 613         vrxq = 0;
 614 found:
 615         dev_info->max_vmdq_pools = vpool;
 616         dev_info->vmdq_queue_num = vrxq;
 617
 618         dev_info->vmdq_pool_base = 0;
 619         dev_info->vmdq_queue_base = 0;
 620
 621         return 0;
 622 }
 623
 624 /* Configure the device based on the configuration provided */
 625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 626 {
 627         struct bnxt *bp = eth_dev->data->dev_private;
 628         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 629         int rc;
 630
 631         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 632         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 633         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 634         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 635
 636         rc = is_bnxt_in_error(bp);
 637         if (rc)
 638                 return rc;
 639
 640         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 641                 rc = bnxt_hwrm_check_vf_rings(bp);
 642                 if (rc) {
 643                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 644                         return -ENOSPC;
 645                 }
 646
 647                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 648                 if (rc) {
 649                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 650                         return -ENOSPC;
 651                 }
 652         } else {
 653                 /* legacy driver needs to get updated values */
 654                 rc = bnxt_hwrm_func_qcaps(bp);
 655                 if (rc) {
 656                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 657                         return rc;
 658                 }
 659         }
 660
 661         /* Inherit new configurations */
 662         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 663             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 664             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 665                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 666             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 667             bp->max_stat_ctx)
 668                 goto resource_error;
 669
 670         if (BNXT_HAS_RING_GRPS(bp) &&
 671             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 672                 goto resource_error;
 673
 674         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 675             bp->max_vnics < eth_dev->data->nb_rx_queues)
 676                 goto resource_error;
 677
 678         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 679         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 729                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 730
 731                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 732                                       RTE_PKTMBUF_HEADROOM);
 733                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 734                         return 1;
 735         }
 736         return 0;
 737 }
 738
 739 static eth_rx_burst_t
 740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 741 {
 742 #ifdef RTE_ARCH_X86
 743 #ifndef RTE_LIBRTE_IEEE1588
 744         /*
 745          * Vector mode receive can be enabled only if scatter rx is not
 746          * in use and rx offloads are limited to VLAN stripping and
 747          * CRC stripping.
 748          */
 749         if (!eth_dev->data->scattered_rx &&
 750             !(eth_dev->data->dev_conf.rxmode.offloads &
 751               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 752                 DEV_RX_OFFLOAD_KEEP_CRC |
 753                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 754                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 755                 DEV_RX_OFFLOAD_UDP_CKSUM |
 756                 DEV_RX_OFFLOAD_TCP_CKSUM |
 757                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 759                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 760                             eth_dev->data->port_id);
 761                 return bnxt_recv_pkts_vec;
 762         }
 763         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 764                     eth_dev->data->port_id);
 765         PMD_DRV_LOG(INFO,
 766                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 767                     eth_dev->data->port_id,
 768                     eth_dev->data->scattered_rx,
 769                     eth_dev->data->dev_conf.rxmode.offloads);
 770 #endif
 771 #endif
 772         return bnxt_recv_pkts;
 773 }
 774
 775 static eth_tx_burst_t
 776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 777 {
 778 #ifdef RTE_ARCH_X86
 779 #ifndef RTE_LIBRTE_IEEE1588
 780         /*
 781          * Vector mode transmit can be enabled only if not using scatter rx
 782          * or tx offloads.
 783          */
 784         if (!eth_dev->data->scattered_rx &&
 785             !eth_dev->data->dev_conf.txmode.offloads) {
 786                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 787                             eth_dev->data->port_id);
 788                 return bnxt_xmit_pkts_vec;
 789         }
 790         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 791                     eth_dev->data->port_id);
 792         PMD_DRV_LOG(INFO,
 793                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 794                     eth_dev->data->port_id,
 795                     eth_dev->data->scattered_rx,
 796                     eth_dev->data->dev_conf.txmode.offloads);
 797 #endif
 798 #endif
 799         return bnxt_xmit_pkts;
 800 }
 801
 802 static int bnxt_handle_if_change_status(struct bnxt *bp)
 803 {
 804         int rc;
 805
 806         /* Since fw has undergone a reset and lost all contexts,
 807          * set fatal flag to not issue hwrm during cleanup
 808          */
 809         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 810         bnxt_uninit_resources(bp, true);
 811
 812         /* clear fatal flag so that re-init happens */
 813         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 814         rc = bnxt_init_resources(bp, true);
 815
 816         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 817
 818         return rc;
 819 }
 820
 821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 822 {
 823         struct bnxt *bp = eth_dev->data->dev_private;
 824         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 825         int vlan_mask = 0;
 826         int rc;
 827
 828         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 829                 PMD_DRV_LOG(ERR,
 830                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 831                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 832         }
 833
 834         bnxt_enable_int(bp);
 835         rc = bnxt_hwrm_if_change(bp, 1);
 836         if (!rc) {
 837                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 838                         rc = bnxt_handle_if_change_status(bp);
 839                         if (rc)
 840                                 return rc;
 841                 }
 842         }
 843
 844         rc = bnxt_init_chip(bp);
 845         if (rc)
 846                 goto error;
 847
 848         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 849
 850         bnxt_link_update_op(eth_dev, 1);
 851
 852         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 853                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 854         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 855                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 856         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 857         if (rc)
 858                 goto error;
 859
 860         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 861         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 862
 863         bp->flags |= BNXT_FLAG_INIT_DONE;
 864         eth_dev->data->dev_started = 1;
 865         bp->dev_stopped = 0;
 866         bnxt_schedule_fw_health_check(bp);
 867         return 0;
 868
 869 error:
 870         bnxt_hwrm_if_change(bp, 0);
 871         bnxt_shutdown_nic(bp);
 872         bnxt_free_tx_mbufs(bp);
 873         bnxt_free_rx_mbufs(bp);
 874         return rc;
 875 }
 876
 877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         int rc = 0;
 881
 882         if (!bp->link_info.link_up)
 883                 rc = bnxt_set_hwrm_link_config(bp, true);
 884         if (!rc)
 885                 eth_dev->data->dev_link.link_status = 1;
 886
 887         bnxt_print_link_info(eth_dev);
 888         return 0;
 889 }
 890
 891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 892 {
 893         struct bnxt *bp = eth_dev->data->dev_private;
 894
 895         eth_dev->data->dev_link.link_status = 0;
 896         bnxt_set_hwrm_link_config(bp, false);
 897         bp->link_info.link_up = 0;
 898
 899         return 0;
 900 }
 901
 902 /* Unload the driver, release resources */
 903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 904 {
 905         struct bnxt *bp = eth_dev->data->dev_private;
 906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 907         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 908
 909         eth_dev->data->dev_started = 0;
 910         /* Prevent crashes when queues are still in use */
 911         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 912         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 913
 914         bnxt_disable_int(bp);
 915
 916         /* disable uio/vfio intr/eventfd mapping */
 917         rte_intr_disable(intr_handle);
 918
 919         bnxt_cancel_fw_health_check(bp);
 920
 921         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 922         if (bp->eth_dev->data->dev_started) {
 923                 /* TBD: STOP HW queues DMA */
 924                 eth_dev->data->dev_link.link_status = 0;
 925         }
 926         bnxt_dev_set_link_down_op(eth_dev);
 927         /* Wait for link to be reset and the async notification to process. */
 928         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 929
 930         /* Clean queue intr-vector mapping */
 931         rte_intr_efd_disable(intr_handle);
 932         if (intr_handle->intr_vec != NULL) {
 933                 rte_free(intr_handle->intr_vec);
 934                 intr_handle->intr_vec = NULL;
 935         }
 936
 937         bnxt_hwrm_port_clr_stats(bp);
 938         bnxt_free_tx_mbufs(bp);
 939         bnxt_free_rx_mbufs(bp);
 940         /* Process any remaining notifications in default completion queue */
 941         bnxt_int_handler(eth_dev);
 942         bnxt_shutdown_nic(bp);
 943         bnxt_hwrm_if_change(bp, 0);
 944         bp->dev_stopped = 1;
 945 }
 946
 947 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 948 {
 949         struct bnxt *bp = eth_dev->data->dev_private;
 950
 951         if (bp->dev_stopped == 0)
 952                 bnxt_dev_stop_op(eth_dev);
 953
 954         if (eth_dev->data->mac_addrs != NULL) {
 955                 rte_free(eth_dev->data->mac_addrs);
 956                 eth_dev->data->mac_addrs = NULL;
 957         }
 958         if (bp->grp_info != NULL) {
 959                 rte_free(bp->grp_info);
 960                 bp->grp_info = NULL;
 961         }
 962
 963         bnxt_dev_uninit(eth_dev);
 964 }
 965
 966 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 967                                     uint32_t index)
 968 {
 969         struct bnxt *bp = eth_dev->data->dev_private;
 970         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 971         struct bnxt_vnic_info *vnic;
 972         struct bnxt_filter_info *filter, *temp_filter;
 973         uint32_t i;
 974
 975         if (is_bnxt_in_error(bp))
 976                 return;
 977
 978         /*
 979          * Loop through all VNICs from the specified filter flow pools to
 980          * remove the corresponding MAC addr filter
 981          */
 982         for (i = 0; i < bp->nr_vnics; i++) {
 983                 if (!(pool_mask & (1ULL << i)))
 984                         continue;
 985
 986                 vnic = &bp->vnic_info[i];
 987                 filter = STAILQ_FIRST(&vnic->filter);
 988                 while (filter) {
 989                         temp_filter = STAILQ_NEXT(filter, next);
 990                         if (filter->mac_index == index) {
 991                                 STAILQ_REMOVE(&vnic->filter, filter,
 992                                                 bnxt_filter_info, next);
 993                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 994                                 filter->mac_index = INVALID_MAC_INDEX;
 995                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 996                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 997                                                    filter, next);
 998                         }
 999                         filter = temp_filter;
1000                 }
1001         }
1002 }
1003
1004 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1005                                 struct rte_ether_addr *mac_addr,
1006                                 uint32_t index, uint32_t pool)
1007 {
1008         struct bnxt *bp = eth_dev->data->dev_private;
1009         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1010         struct bnxt_filter_info *filter;
1011         int rc = 0;
1012
1013         rc = is_bnxt_in_error(bp);
1014         if (rc)
1015                 return rc;
1016
1017         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1018                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1019                 return -ENOTSUP;
1020         }
1021
1022         if (!vnic) {
1023                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1024                 return -EINVAL;
1025         }
1026         /* Attach requested MAC address to the new l2_filter */
1027         STAILQ_FOREACH(filter, &vnic->filter, next) {
1028                 if (filter->mac_index == index) {
1029                         PMD_DRV_LOG(ERR,
1030                                 "MAC addr already existed for pool %d\n", pool);
1031                         return 0;
1032                 }
1033         }
1034         filter = bnxt_alloc_filter(bp);
1035         if (!filter) {
1036                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1037                 return -ENODEV;
1038         }
1039
1040         filter->mac_index = index;
1041         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1043
1044         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1045         if (!rc) {
1046                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1047         } else {
1048                 filter->mac_index = INVALID_MAC_INDEX;
1049                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1050                 bnxt_free_filter(bp, filter);
1051         }
1052
1053         return rc;
1054 }
1055
1056 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1057 {
1058         int rc = 0;
1059         struct bnxt *bp = eth_dev->data->dev_private;
1060         struct rte_eth_link new;
1061         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1062
1063         rc = is_bnxt_in_error(bp);
1064         if (rc)
1065                 return rc;
1066
1067         memset(&new, 0, sizeof(new));
1068         do {
1069                 /* Retrieve link info from hardware */
1070                 rc = bnxt_get_hwrm_link_config(bp, &new);
1071                 if (rc) {
1072                         new.link_speed = ETH_LINK_SPEED_100M;
1073                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1074                         PMD_DRV_LOG(ERR,
1075                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1076                         goto out;
1077                 }
1078
1079                 if (!wait_to_complete || new.link_status)
1080                         break;
1081
1082                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1083         } while (cnt--);
1084
1085 out:
1086         /* Timed out or success */
1087         if (new.link_status != eth_dev->data->dev_link.link_status ||
1088         new.link_speed != eth_dev->data->dev_link.link_speed) {
1089                 rte_eth_linkstatus_set(eth_dev, &new);
1090
1091                 _rte_eth_dev_callback_process(eth_dev,
1092                                               RTE_ETH_EVENT_INTR_LSC,
1093                                               NULL);
1094
1095                 bnxt_print_link_info(eth_dev);
1096         }
1097
1098         return rc;
1099 }
1100
1101 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1102 {
1103         struct bnxt *bp = eth_dev->data->dev_private;
1104         struct bnxt_vnic_info *vnic;
1105         uint32_t old_flags;
1106         int rc;
1107
1108         rc = is_bnxt_in_error(bp);
1109         if (rc)
1110                 return rc;
1111
1112         if (bp->vnic_info == NULL)
1113                 return 0;
1114
1115         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1116
1117         old_flags = vnic->flags;
1118         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1119         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1120         if (rc != 0)
1121                 vnic->flags = old_flags;
1122
1123         return rc;
1124 }
1125
1126 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1127 {
1128         struct bnxt *bp = eth_dev->data->dev_private;
1129         struct bnxt_vnic_info *vnic;
1130         uint32_t old_flags;
1131         int rc;
1132
1133         rc = is_bnxt_in_error(bp);
1134         if (rc)
1135                 return rc;
1136
1137         if (bp->vnic_info == NULL)
1138                 return 0;
1139
1140         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1141
1142         old_flags = vnic->flags;
1143         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1144         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1145         if (rc != 0)
1146                 vnic->flags = old_flags;
1147
1148         return rc;
1149 }
1150
1151 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1152 {
1153         struct bnxt *bp = eth_dev->data->dev_private;
1154         struct bnxt_vnic_info *vnic;
1155         uint32_t old_flags;
1156         int rc;
1157
1158         rc = is_bnxt_in_error(bp);
1159         if (rc)
1160                 return rc;
1161
1162         if (bp->vnic_info == NULL)
1163                 return 0;
1164
1165         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1166
1167         old_flags = vnic->flags;
1168         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1169         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1170         if (rc != 0)
1171                 vnic->flags = old_flags;
1172
1173         return rc;
1174 }
1175
1176 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1177 {
1178         struct bnxt *bp = eth_dev->data->dev_private;
1179         struct bnxt_vnic_info *vnic;
1180         uint32_t old_flags;
1181         int rc;
1182
1183         rc = is_bnxt_in_error(bp);
1184         if (rc)
1185                 return rc;
1186
1187         if (bp->vnic_info == NULL)
1188                 return 0;
1189
1190         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1191
1192         old_flags = vnic->flags;
1193         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1194         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1195         if (rc != 0)
1196                 vnic->flags = old_flags;
1197
1198         return rc;
1199 }
1200
1201 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1202 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1203 {
1204         if (qid >= bp->rx_nr_rings)
1205                 return NULL;
1206
1207         return bp->eth_dev->data->rx_queues[qid];
1208 }
1209
1210 /* Return rxq corresponding to a given rss table ring/group ID. */
1211 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1212 {
1213         struct bnxt_rx_queue *rxq;
1214         unsigned int i;
1215
1216         if (!BNXT_HAS_RING_GRPS(bp)) {
1217                 for (i = 0; i < bp->rx_nr_rings; i++) {
1218                         rxq = bp->eth_dev->data->rx_queues[i];
1219                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1220                                 return rxq->index;
1221                 }
1222         } else {
1223                 for (i = 0; i < bp->rx_nr_rings; i++) {
1224                         if (bp->grp_info[i].fw_grp_id == fwr)
1225                                 return i;
1226                 }
1227         }
1228
1229         return INVALID_HW_RING_ID;
1230 }
1231
1232 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1233                             struct rte_eth_rss_reta_entry64 *reta_conf,
1234                             uint16_t reta_size)
1235 {
1236         struct bnxt *bp = eth_dev->data->dev_private;
1237         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1238         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1239         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1240         uint16_t idx, sft;
1241         int i, rc;
1242
1243         rc = is_bnxt_in_error(bp);
1244         if (rc)
1245                 return rc;
1246
1247         if (!vnic->rss_table)
1248                 return -EINVAL;
1249
1250         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1251                 return -EINVAL;
1252
1253         if (reta_size != tbl_size) {
1254                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1255                         "(%d) must equal the size supported by the hardware "
1256                         "(%d)\n", reta_size, tbl_size);
1257                 return -EINVAL;
1258         }
1259
1260         for (i = 0; i < reta_size; i++) {
1261                 struct bnxt_rx_queue *rxq;
1262
1263                 idx = i / RTE_RETA_GROUP_SIZE;
1264                 sft = i % RTE_RETA_GROUP_SIZE;
1265
1266                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1267                         continue;
1268
1269                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1270                 if (!rxq) {
1271                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1272                         return -EINVAL;
1273                 }
1274
1275                 if (BNXT_CHIP_THOR(bp)) {
1276                         vnic->rss_table[i * 2] =
1277                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1278                         vnic->rss_table[i * 2 + 1] =
1279                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1280                 } else {
1281                         vnic->rss_table[i] =
1282                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1283                 }
1284
1285                 vnic->rss_table[i] =
1286                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1287         }
1288
1289         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1290         return 0;
1291 }
1292
1293 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1294                               struct rte_eth_rss_reta_entry64 *reta_conf,
1295                               uint16_t reta_size)
1296 {
1297         struct bnxt *bp = eth_dev->data->dev_private;
1298         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1299         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1300         uint16_t idx, sft, i;
1301         int rc;
1302
1303         rc = is_bnxt_in_error(bp);
1304         if (rc)
1305                 return rc;
1306
1307         /* Retrieve from the default VNIC */
1308         if (!vnic)
1309                 return -EINVAL;
1310         if (!vnic->rss_table)
1311                 return -EINVAL;
1312
1313         if (reta_size != tbl_size) {
1314                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1315                         "(%d) must equal the size supported by the hardware "
1316                         "(%d)\n", reta_size, tbl_size);
1317                 return -EINVAL;
1318         }
1319
1320         for (idx = 0, i = 0; i < reta_size; i++) {
1321                 idx = i / RTE_RETA_GROUP_SIZE;
1322                 sft = i % RTE_RETA_GROUP_SIZE;
1323
1324                 if (reta_conf[idx].mask & (1ULL << sft)) {
1325                         uint16_t qid;
1326
1327                         if (BNXT_CHIP_THOR(bp))
1328                                 qid = bnxt_rss_to_qid(bp,
1329                                                       vnic->rss_table[i * 2]);
1330                         else
1331                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1332
1333                         if (qid == INVALID_HW_RING_ID) {
1334                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1335                                 return -EINVAL;
1336                         }
1337                         reta_conf[idx].reta[sft] = qid;
1338                 }
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1345                                    struct rte_eth_rss_conf *rss_conf)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1349         struct bnxt_vnic_info *vnic;
1350         int rc;
1351
1352         rc = is_bnxt_in_error(bp);
1353         if (rc)
1354                 return rc;
1355
1356         /*
1357          * If RSS enablement were different than dev_configure,
1358          * then return -EINVAL
1359          */
1360         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1361                 if (!rss_conf->rss_hf)
1362                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1363         } else {
1364                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1365                         return -EINVAL;
1366         }
1367
1368         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1369         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1370
1371         /* Update the default RSS VNIC(s) */
1372         vnic = &bp->vnic_info[0];
1373         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1374
1375         /*
1376          * Use the supplied key if the key length is
1377          * acceptable and the rss_key is not NULL
1378          */
1379         if (rss_conf->rss_key && rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1380                 memcpy(vnic->rss_hash_key,
1381                        rss_conf->rss_key,
1382                        rss_conf->rss_key_len);
1383
1384         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1385         return 0;
1386 }
1387
1388 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1389                                      struct rte_eth_rss_conf *rss_conf)
1390 {
1391         struct bnxt *bp = eth_dev->data->dev_private;
1392         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1393         int len, rc;
1394         uint32_t hash_types;
1395
1396         rc = is_bnxt_in_error(bp);
1397         if (rc)
1398                 return rc;
1399
1400         /* RSS configuration is the same for all VNICs */
1401         if (vnic && vnic->rss_hash_key) {
1402                 if (rss_conf->rss_key) {
1403                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1404                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1405                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1406                 }
1407
1408                 hash_types = vnic->hash_type;
1409                 rss_conf->rss_hf = 0;
1410                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1411                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1412                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1413                 }
1414                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1415                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1416                         hash_types &=
1417                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1418                 }
1419                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1420                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1421                         hash_types &=
1422                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1423                 }
1424                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1425                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1426                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1427                 }
1428                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1429                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1430                         hash_types &=
1431                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1432                 }
1433                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1434                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1435                         hash_types &=
1436                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1437                 }
1438                 if (hash_types) {
1439                         PMD_DRV_LOG(ERR,
1440                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1441                                 vnic->hash_type);
1442                         return -ENOTSUP;
1443                 }
1444         } else {
1445                 rss_conf->rss_hf = 0;
1446         }
1447         return 0;
1448 }
1449
1450 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1451                                struct rte_eth_fc_conf *fc_conf)
1452 {
1453         struct bnxt *bp = dev->data->dev_private;
1454         struct rte_eth_link link_info;
1455         int rc;
1456
1457         rc = is_bnxt_in_error(bp);
1458         if (rc)
1459                 return rc;
1460
1461         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1462         if (rc)
1463                 return rc;
1464
1465         memset(fc_conf, 0, sizeof(*fc_conf));
1466         if (bp->link_info.auto_pause)
1467                 fc_conf->autoneg = 1;
1468         switch (bp->link_info.pause) {
1469         case 0:
1470                 fc_conf->mode = RTE_FC_NONE;
1471                 break;
1472         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1473                 fc_conf->mode = RTE_FC_TX_PAUSE;
1474                 break;
1475         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1476                 fc_conf->mode = RTE_FC_RX_PAUSE;
1477                 break;
1478         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1479                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1480                 fc_conf->mode = RTE_FC_FULL;
1481                 break;
1482         }
1483         return 0;
1484 }
1485
1486 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1487                                struct rte_eth_fc_conf *fc_conf)
1488 {
1489         struct bnxt *bp = dev->data->dev_private;
1490         int rc;
1491
1492         rc = is_bnxt_in_error(bp);
1493         if (rc)
1494                 return rc;
1495
1496         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1497                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1498                 return -ENOTSUP;
1499         }
1500
1501         switch (fc_conf->mode) {
1502         case RTE_FC_NONE:
1503                 bp->link_info.auto_pause = 0;
1504                 bp->link_info.force_pause = 0;
1505                 break;
1506         case RTE_FC_RX_PAUSE:
1507                 if (fc_conf->autoneg) {
1508                         bp->link_info.auto_pause =
1509                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1510                         bp->link_info.force_pause = 0;
1511                 } else {
1512                         bp->link_info.auto_pause = 0;
1513                         bp->link_info.force_pause =
1514                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1515                 }
1516                 break;
1517         case RTE_FC_TX_PAUSE:
1518                 if (fc_conf->autoneg) {
1519                         bp->link_info.auto_pause =
1520                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1521                         bp->link_info.force_pause = 0;
1522                 } else {
1523                         bp->link_info.auto_pause = 0;
1524                         bp->link_info.force_pause =
1525                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1526                 }
1527                 break;
1528         case RTE_FC_FULL:
1529                 if (fc_conf->autoneg) {
1530                         bp->link_info.auto_pause =
1531                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1532                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1533                         bp->link_info.force_pause = 0;
1534                 } else {
1535                         bp->link_info.auto_pause = 0;
1536                         bp->link_info.force_pause =
1537                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1538                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1539                 }
1540                 break;
1541         }
1542         return bnxt_set_hwrm_link_config(bp, true);
1543 }
1544
1545 /* Add UDP tunneling port */
1546 static int
1547 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1548                          struct rte_eth_udp_tunnel *udp_tunnel)
1549 {
1550         struct bnxt *bp = eth_dev->data->dev_private;
1551         uint16_t tunnel_type = 0;
1552         int rc = 0;
1553
1554         rc = is_bnxt_in_error(bp);
1555         if (rc)
1556                 return rc;
1557
1558         switch (udp_tunnel->prot_type) {
1559         case RTE_TUNNEL_TYPE_VXLAN:
1560                 if (bp->vxlan_port_cnt) {
1561                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1562                                 udp_tunnel->udp_port);
1563                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1564                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1565                                 return -ENOSPC;
1566                         }
1567                         bp->vxlan_port_cnt++;
1568                         return 0;
1569                 }
1570                 tunnel_type =
1571                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1572                 bp->vxlan_port_cnt++;
1573                 break;
1574         case RTE_TUNNEL_TYPE_GENEVE:
1575                 if (bp->geneve_port_cnt) {
1576                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1577                                 udp_tunnel->udp_port);
1578                         if (bp->geneve_port != udp_tunnel->udp_port) {
1579                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1580                                 return -ENOSPC;
1581                         }
1582                         bp->geneve_port_cnt++;
1583                         return 0;
1584                 }
1585                 tunnel_type =
1586                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1587                 bp->geneve_port_cnt++;
1588                 break;
1589         default:
1590                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1591                 return -ENOTSUP;
1592         }
1593         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1594                                              tunnel_type);
1595         return rc;
1596 }
1597
1598 static int
1599 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1600                          struct rte_eth_udp_tunnel *udp_tunnel)
1601 {
1602         struct bnxt *bp = eth_dev->data->dev_private;
1603         uint16_t tunnel_type = 0;
1604         uint16_t port = 0;
1605         int rc = 0;
1606
1607         rc = is_bnxt_in_error(bp);
1608         if (rc)
1609                 return rc;
1610
1611         switch (udp_tunnel->prot_type) {
1612         case RTE_TUNNEL_TYPE_VXLAN:
1613                 if (!bp->vxlan_port_cnt) {
1614                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1615                         return -EINVAL;
1616                 }
1617                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1618                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1619                                 udp_tunnel->udp_port, bp->vxlan_port);
1620                         return -EINVAL;
1621                 }
1622                 if (--bp->vxlan_port_cnt)
1623                         return 0;
1624
1625                 tunnel_type =
1626                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1627                 port = bp->vxlan_fw_dst_port_id;
1628                 break;
1629         case RTE_TUNNEL_TYPE_GENEVE:
1630                 if (!bp->geneve_port_cnt) {
1631                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1632                         return -EINVAL;
1633                 }
1634                 if (bp->geneve_port != udp_tunnel->udp_port) {
1635                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1636                                 udp_tunnel->udp_port, bp->geneve_port);
1637                         return -EINVAL;
1638                 }
1639                 if (--bp->geneve_port_cnt)
1640                         return 0;
1641
1642                 tunnel_type =
1643                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1644                 port = bp->geneve_fw_dst_port_id;
1645                 break;
1646         default:
1647                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1648                 return -ENOTSUP;
1649         }
1650
1651         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1652         if (!rc) {
1653                 if (tunnel_type ==
1654                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1655                         bp->vxlan_port = 0;
1656                 if (tunnel_type ==
1657                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1658                         bp->geneve_port = 0;
1659         }
1660         return rc;
1661 }
1662
1663 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1664 {
1665         struct bnxt_filter_info *filter;
1666         struct bnxt_vnic_info *vnic;
1667         int rc = 0;
1668         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1669
1670         /* if VLAN exists && VLAN matches vlan_id
1671          *      remove the MAC+VLAN filter
1672          *      add a new MAC only filter
1673          * else
1674          *      VLAN filter doesn't exist, just skip and continue
1675          */
1676         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1677         filter = STAILQ_FIRST(&vnic->filter);
1678         while (filter) {
1679                 /* Search for this matching MAC+VLAN filter */
1680                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1681                     !memcmp(filter->l2_addr,
1682                             bp->mac_addr,
1683                             RTE_ETHER_ADDR_LEN)) {
1684                         /* Delete the filter */
1685                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1686                         if (rc)
1687                                 return rc;
1688                         STAILQ_REMOVE(&vnic->filter, filter,
1689                                       bnxt_filter_info, next);
1690                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1691
1692                         PMD_DRV_LOG(INFO,
1693                                     "Del Vlan filter for %d\n",
1694                                     vlan_id);
1695                         return rc;
1696                 }
1697                 filter = STAILQ_NEXT(filter, next);
1698         }
1699         return -ENOENT;
1700 }
1701
1702 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1703 {
1704         struct bnxt_filter_info *filter;
1705         struct bnxt_vnic_info *vnic;
1706         int rc = 0;
1707         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1708                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1709         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1710
1711         /* Implementation notes on the use of VNIC in this command:
1712          *
1713          * By default, these filters belong to default vnic for the function.
1714          * Once these filters are set up, only destination VNIC can be modified.
1715          * If the destination VNIC is not specified in this command,
1716          * then the HWRM shall only create an l2 context id.
1717          */
1718
1719         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1720         filter = STAILQ_FIRST(&vnic->filter);
1721         /* Check if the VLAN has already been added */
1722         while (filter) {
1723                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1724                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1725                         return -EEXIST;
1726
1727                 filter = STAILQ_NEXT(filter, next);
1728         }
1729
1730         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1731          * command to create MAC+VLAN filter with the right flags, enables set.
1732          */
1733         filter = bnxt_alloc_filter(bp);
1734         if (!filter) {
1735                 PMD_DRV_LOG(ERR,
1736                             "MAC/VLAN filter alloc failed\n");
1737                 return -ENOMEM;
1738         }
1739         /* MAC + VLAN ID filter */
1740         filter->l2_ivlan = vlan_id;
1741         filter->l2_ivlan_mask = 0x0FFF;
1742         filter->enables |= en;
1743         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1744         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1745         if (rc) {
1746                 /* Free the newly allocated filter as we were
1747                  * not able to create the filter in hardware.
1748                  */
1749                 filter->fw_l2_filter_id = UINT64_MAX;
1750                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1751                 return rc;
1752         }
1753
1754         /* Add this new filter to the list */
1755         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1756         PMD_DRV_LOG(INFO,
1757                     "Added Vlan filter for %d\n", vlan_id);
1758         return rc;
1759 }
1760
1761 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1762                 uint16_t vlan_id, int on)
1763 {
1764         struct bnxt *bp = eth_dev->data->dev_private;
1765         int rc;
1766
1767         rc = is_bnxt_in_error(bp);
1768         if (rc)
1769                 return rc;
1770
1771         /* These operations apply to ALL existing MAC/VLAN filters */
1772         if (on)
1773                 return bnxt_add_vlan_filter(bp, vlan_id);
1774         else
1775                 return bnxt_del_vlan_filter(bp, vlan_id);
1776 }
1777
1778 static int
1779 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1780 {
1781         struct bnxt *bp = dev->data->dev_private;
1782         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1783         unsigned int i;
1784         int rc;
1785
1786         rc = is_bnxt_in_error(bp);
1787         if (rc)
1788                 return rc;
1789
1790         if (mask & ETH_VLAN_FILTER_MASK) {
1791                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1792                         /* Remove any VLAN filters programmed */
1793                         for (i = 0; i < 4095; i++)
1794                                 bnxt_del_vlan_filter(bp, i);
1795                 }
1796                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1797                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1798         }
1799
1800         if (mask & ETH_VLAN_STRIP_MASK) {
1801                 /* Enable or disable VLAN stripping */
1802                 for (i = 0; i < bp->nr_vnics; i++) {
1803                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1804                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1805                                 vnic->vlan_strip = true;
1806                         else
1807                                 vnic->vlan_strip = false;
1808                         bnxt_hwrm_vnic_cfg(bp, vnic);
1809                 }
1810                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1811                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1812         }
1813
1814         if (mask & ETH_VLAN_EXTEND_MASK) {
1815                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1816                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1817                 else
1818                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1819         }
1820
1821         return 0;
1822 }
1823
1824 static int
1825 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1826                       uint16_t tpid)
1827 {
1828         struct bnxt *bp = dev->data->dev_private;
1829         int qinq = dev->data->dev_conf.rxmode.offloads &
1830                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1831
1832         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1833             vlan_type != ETH_VLAN_TYPE_OUTER) {
1834                 PMD_DRV_LOG(ERR,
1835                             "Unsupported vlan type.");
1836                 return -EINVAL;
1837         }
1838         if (!qinq) {
1839                 PMD_DRV_LOG(ERR,
1840                             "QinQ not enabled. Needs to be ON as we can "
1841                             "accelerate only outer vlan\n");
1842                 return -EINVAL;
1843         }
1844
1845         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1846                 switch (tpid) {
1847                 case RTE_ETHER_TYPE_QINQ:
1848                         bp->outer_tpid_bd =
1849                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1850                                 break;
1851                 case RTE_ETHER_TYPE_VLAN:
1852                         bp->outer_tpid_bd =
1853                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1854                                 break;
1855                 case 0x9100:
1856                         bp->outer_tpid_bd =
1857                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1858                                 break;
1859                 case 0x9200:
1860                         bp->outer_tpid_bd =
1861                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1862                                 break;
1863                 case 0x9300:
1864                         bp->outer_tpid_bd =
1865                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1866                                 break;
1867                 default:
1868                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1869                         return -EINVAL;
1870                 }
1871                 bp->outer_tpid_bd |= tpid;
1872                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1873         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1874                 PMD_DRV_LOG(ERR,
1875                             "Can accelerate only outer vlan in QinQ\n");
1876                 return -EINVAL;
1877         }
1878
1879         return 0;
1880 }
1881
1882 static int
1883 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1884                              struct rte_ether_addr *addr)
1885 {
1886         struct bnxt *bp = dev->data->dev_private;
1887         /* Default Filter is tied to VNIC 0 */
1888         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1889         struct bnxt_filter_info *filter;
1890         int rc;
1891
1892         rc = is_bnxt_in_error(bp);
1893         if (rc)
1894                 return rc;
1895
1896         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1897                 return -EPERM;
1898
1899         if (rte_is_zero_ether_addr(addr))
1900                 return -EINVAL;
1901
1902         STAILQ_FOREACH(filter, &vnic->filter, next) {
1903                 /* Default Filter is at Index 0 */
1904                 if (filter->mac_index != 0)
1905                         continue;
1906
1907                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1908                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1909                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1910                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1911                 filter->enables |=
1912                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1913                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1914
1915                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1916                 if (rc)
1917                         return rc;
1918
1919                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1920                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1921                 return 0;
1922         }
1923
1924         return 0;
1925 }
1926
1927 static int
1928 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1929                           struct rte_ether_addr *mc_addr_set,
1930                           uint32_t nb_mc_addr)
1931 {
1932         struct bnxt *bp = eth_dev->data->dev_private;
1933         char *mc_addr_list = (char *)mc_addr_set;
1934         struct bnxt_vnic_info *vnic;
1935         uint32_t off = 0, i = 0;
1936         int rc;
1937
1938         rc = is_bnxt_in_error(bp);
1939         if (rc)
1940                 return rc;
1941
1942         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1943
1944         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1945                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1946                 goto allmulti;
1947         }
1948
1949         /* TODO Check for Duplicate mcast addresses */
1950         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1951         for (i = 0; i < nb_mc_addr; i++) {
1952                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1953                         RTE_ETHER_ADDR_LEN);
1954                 off += RTE_ETHER_ADDR_LEN;
1955         }
1956
1957         vnic->mc_addr_cnt = i;
1958
1959 allmulti:
1960         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1961 }
1962
1963 static int
1964 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1965 {
1966         struct bnxt *bp = dev->data->dev_private;
1967         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1968         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1969         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1970         int ret;
1971
1972         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1973                         fw_major, fw_minor, fw_updt);
1974
1975         ret += 1; /* add the size of '\0' */
1976         if (fw_size < (uint32_t)ret)
1977                 return ret;
1978         else
1979                 return 0;
1980 }
1981
1982 static void
1983 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1984         struct rte_eth_rxq_info *qinfo)
1985 {
1986         struct bnxt_rx_queue *rxq;
1987
1988         rxq = dev->data->rx_queues[queue_id];
1989
1990         qinfo->mp = rxq->mb_pool;
1991         qinfo->scattered_rx = dev->data->scattered_rx;
1992         qinfo->nb_desc = rxq->nb_rx_desc;
1993
1994         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1995         qinfo->conf.rx_drop_en = 0;
1996         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1997 }
1998
1999 static void
2000 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2001         struct rte_eth_txq_info *qinfo)
2002 {
2003         struct bnxt_tx_queue *txq;
2004
2005         txq = dev->data->tx_queues[queue_id];
2006
2007         qinfo->nb_desc = txq->nb_tx_desc;
2008
2009         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2010         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2011         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2012
2013         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2014         qinfo->conf.tx_rs_thresh = 0;
2015         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2016 }
2017
2018 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2019 {
2020         struct bnxt *bp = eth_dev->data->dev_private;
2021         uint32_t new_pkt_size;
2022         uint32_t rc = 0;
2023         uint32_t i;
2024
2025         rc = is_bnxt_in_error(bp);
2026         if (rc)
2027                 return rc;
2028
2029         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2030                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2031
2032 #ifdef RTE_ARCH_X86
2033         /*
2034          * If vector-mode tx/rx is active, disallow any MTU change that would
2035          * require scattered receive support.
2036          */
2037         if (eth_dev->data->dev_started &&
2038             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2039              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2040             (new_pkt_size >
2041              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2042                 PMD_DRV_LOG(ERR,
2043                             "MTU change would require scattered rx support. ");
2044                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2045                 return -EINVAL;
2046         }
2047 #endif
2048
2049         if (new_mtu > RTE_ETHER_MTU) {
2050                 bp->flags |= BNXT_FLAG_JUMBO;
2051                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2052                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2053         } else {
2054                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2055                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2056                 bp->flags &= ~BNXT_FLAG_JUMBO;
2057         }
2058
2059         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2060
2061         for (i = 0; i < bp->nr_vnics; i++) {
2062                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2063                 uint16_t size = 0;
2064
2065                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2066                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2067                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2068                 if (rc)
2069                         break;
2070
2071                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2072                 size -= RTE_PKTMBUF_HEADROOM;
2073
2074                 if (size < new_mtu) {
2075                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2076                         if (rc)
2077                                 return rc;
2078                 }
2079         }
2080
2081         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2082
2083         return rc;
2084 }
2085
2086 static int
2087 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2088 {
2089         struct bnxt *bp = dev->data->dev_private;
2090         uint16_t vlan = bp->vlan;
2091         int rc;
2092
2093         rc = is_bnxt_in_error(bp);
2094         if (rc)
2095                 return rc;
2096
2097         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2098                 PMD_DRV_LOG(ERR,
2099                         "PVID cannot be modified for this function\n");
2100                 return -ENOTSUP;
2101         }
2102         bp->vlan = on ? pvid : 0;
2103
2104         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2105         if (rc)
2106                 bp->vlan = vlan;
2107         return rc;
2108 }
2109
2110 static int
2111 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2112 {
2113         struct bnxt *bp = dev->data->dev_private;
2114         int rc;
2115
2116         rc = is_bnxt_in_error(bp);
2117         if (rc)
2118                 return rc;
2119
2120         return bnxt_hwrm_port_led_cfg(bp, true);
2121 }
2122
2123 static int
2124 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2125 {
2126         struct bnxt *bp = dev->data->dev_private;
2127         int rc;
2128
2129         rc = is_bnxt_in_error(bp);
2130         if (rc)
2131                 return rc;
2132
2133         return bnxt_hwrm_port_led_cfg(bp, false);
2134 }
2135
2136 static uint32_t
2137 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2138 {
2139         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2140         uint32_t desc = 0, raw_cons = 0, cons;
2141         struct bnxt_cp_ring_info *cpr;
2142         struct bnxt_rx_queue *rxq;
2143         struct rx_pkt_cmpl *rxcmp;
2144         int rc;
2145
2146         rc = is_bnxt_in_error(bp);
2147         if (rc)
2148                 return rc;
2149
2150         rxq = dev->data->rx_queues[rx_queue_id];
2151         cpr = rxq->cp_ring;
2152         raw_cons = cpr->cp_raw_cons;
2153
2154         while (1) {
2155                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2156                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2157                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2158
2159                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2160                         break;
2161                 } else {
2162                         raw_cons++;
2163                         desc++;
2164                 }
2165         }
2166
2167         return desc;
2168 }
2169
2170 static int
2171 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2172 {
2173         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2174         struct bnxt_rx_ring_info *rxr;
2175         struct bnxt_cp_ring_info *cpr;
2176         struct bnxt_sw_rx_bd *rx_buf;
2177         struct rx_pkt_cmpl *rxcmp;
2178         uint32_t cons, cp_cons;
2179         int rc;
2180
2181         if (!rxq)
2182                 return -EINVAL;
2183
2184         rc = is_bnxt_in_error(rxq->bp);
2185         if (rc)
2186                 return rc;
2187
2188         cpr = rxq->cp_ring;
2189         rxr = rxq->rx_ring;
2190
2191         if (offset >= rxq->nb_rx_desc)
2192                 return -EINVAL;
2193
2194         cons = RING_CMP(cpr->cp_ring_struct, offset);
2195         cp_cons = cpr->cp_raw_cons;
2196         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2197
2198         if (cons > cp_cons) {
2199                 if (CMPL_VALID(rxcmp, cpr->valid))
2200                         return RTE_ETH_RX_DESC_DONE;
2201         } else {
2202                 if (CMPL_VALID(rxcmp, !cpr->valid))
2203                         return RTE_ETH_RX_DESC_DONE;
2204         }
2205         rx_buf = &rxr->rx_buf_ring[cons];
2206         if (rx_buf->mbuf == NULL)
2207                 return RTE_ETH_RX_DESC_UNAVAIL;
2208
2209
2210         return RTE_ETH_RX_DESC_AVAIL;
2211 }
2212
2213 static int
2214 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2215 {
2216         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2217         struct bnxt_tx_ring_info *txr;
2218         struct bnxt_cp_ring_info *cpr;
2219         struct bnxt_sw_tx_bd *tx_buf;
2220         struct tx_pkt_cmpl *txcmp;
2221         uint32_t cons, cp_cons;
2222         int rc;
2223
2224         if (!txq)
2225                 return -EINVAL;
2226
2227         rc = is_bnxt_in_error(txq->bp);
2228         if (rc)
2229                 return rc;
2230
2231         cpr = txq->cp_ring;
2232         txr = txq->tx_ring;
2233
2234         if (offset >= txq->nb_tx_desc)
2235                 return -EINVAL;
2236
2237         cons = RING_CMP(cpr->cp_ring_struct, offset);
2238         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2239         cp_cons = cpr->cp_raw_cons;
2240
2241         if (cons > cp_cons) {
2242                 if (CMPL_VALID(txcmp, cpr->valid))
2243                         return RTE_ETH_TX_DESC_UNAVAIL;
2244         } else {
2245                 if (CMPL_VALID(txcmp, !cpr->valid))
2246                         return RTE_ETH_TX_DESC_UNAVAIL;
2247         }
2248         tx_buf = &txr->tx_buf_ring[cons];
2249         if (tx_buf->mbuf == NULL)
2250                 return RTE_ETH_TX_DESC_DONE;
2251
2252         return RTE_ETH_TX_DESC_FULL;
2253 }
2254
2255 static struct bnxt_filter_info *
2256 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2257                                 struct rte_eth_ethertype_filter *efilter,
2258                                 struct bnxt_vnic_info *vnic0,
2259                                 struct bnxt_vnic_info *vnic,
2260                                 int *ret)
2261 {
2262         struct bnxt_filter_info *mfilter = NULL;
2263         int match = 0;
2264         *ret = 0;
2265
2266         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2267                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2268                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2269                         " ethertype filter.", efilter->ether_type);
2270                 *ret = -EINVAL;
2271                 goto exit;
2272         }
2273         if (efilter->queue >= bp->rx_nr_rings) {
2274                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2275                 *ret = -EINVAL;
2276                 goto exit;
2277         }
2278
2279         vnic0 = &bp->vnic_info[0];
2280         vnic = &bp->vnic_info[efilter->queue];
2281         if (vnic == NULL) {
2282                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2283                 *ret = -EINVAL;
2284                 goto exit;
2285         }
2286
2287         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2288                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2289                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2290                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2291                              mfilter->flags ==
2292                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2293                              mfilter->ethertype == efilter->ether_type)) {
2294                                 match = 1;
2295                                 break;
2296                         }
2297                 }
2298         } else {
2299                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2300                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2301                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2302                              mfilter->ethertype == efilter->ether_type &&
2303                              mfilter->flags ==
2304                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2305                                 match = 1;
2306                                 break;
2307                         }
2308         }
2309
2310         if (match)
2311                 *ret = -EEXIST;
2312
2313 exit:
2314         return mfilter;
2315 }
2316
2317 static int
2318 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2319                         enum rte_filter_op filter_op,
2320                         void *arg)
2321 {
2322         struct bnxt *bp = dev->data->dev_private;
2323         struct rte_eth_ethertype_filter *efilter =
2324                         (struct rte_eth_ethertype_filter *)arg;
2325         struct bnxt_filter_info *bfilter, *filter1;
2326         struct bnxt_vnic_info *vnic, *vnic0;
2327         int ret;
2328
2329         if (filter_op == RTE_ETH_FILTER_NOP)
2330                 return 0;
2331
2332         if (arg == NULL) {
2333                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2334                             filter_op);
2335                 return -EINVAL;
2336         }
2337
2338         vnic0 = &bp->vnic_info[0];
2339         vnic = &bp->vnic_info[efilter->queue];
2340
2341         switch (filter_op) {
2342         case RTE_ETH_FILTER_ADD:
2343                 bnxt_match_and_validate_ether_filter(bp, efilter,
2344                                                         vnic0, vnic, &ret);
2345                 if (ret < 0)
2346                         return ret;
2347
2348                 bfilter = bnxt_get_unused_filter(bp);
2349                 if (bfilter == NULL) {
2350                         PMD_DRV_LOG(ERR,
2351                                 "Not enough resources for a new filter.\n");
2352                         return -ENOMEM;
2353                 }
2354                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2355                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2356                        RTE_ETHER_ADDR_LEN);
2357                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2358                        RTE_ETHER_ADDR_LEN);
2359                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2360                 bfilter->ethertype = efilter->ether_type;
2361                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2362
2363                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2364                 if (filter1 == NULL) {
2365                         ret = -EINVAL;
2366                         goto cleanup;
2367                 }
2368                 bfilter->enables |=
2369                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2370                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2371
2372                 bfilter->dst_id = vnic->fw_vnic_id;
2373
2374                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2375                         bfilter->flags =
2376                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2377                 }
2378
2379                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2380                 if (ret)
2381                         goto cleanup;
2382                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2383                 break;
2384         case RTE_ETH_FILTER_DELETE:
2385                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2386                                                         vnic0, vnic, &ret);
2387                 if (ret == -EEXIST) {
2388                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2389
2390                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2391                                       next);
2392                         bnxt_free_filter(bp, filter1);
2393                 } else if (ret == 0) {
2394                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2395                 }
2396                 break;
2397         default:
2398                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2399                 ret = -EINVAL;
2400                 goto error;
2401         }
2402         return ret;
2403 cleanup:
2404         bnxt_free_filter(bp, bfilter);
2405 error:
2406         return ret;
2407 }
2408
2409 static inline int
2410 parse_ntuple_filter(struct bnxt *bp,
2411                     struct rte_eth_ntuple_filter *nfilter,
2412                     struct bnxt_filter_info *bfilter)
2413 {
2414         uint32_t en = 0;
2415
2416         if (nfilter->queue >= bp->rx_nr_rings) {
2417                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2418                 return -EINVAL;
2419         }
2420
2421         switch (nfilter->dst_port_mask) {
2422         case UINT16_MAX:
2423                 bfilter->dst_port_mask = -1;
2424                 bfilter->dst_port = nfilter->dst_port;
2425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2426                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2427                 break;
2428         default:
2429                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2430                 return -EINVAL;
2431         }
2432
2433         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2434         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2435
2436         switch (nfilter->proto_mask) {
2437         case UINT8_MAX:
2438                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2439                         bfilter->ip_protocol = 17;
2440                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2441                         bfilter->ip_protocol = 6;
2442                 else
2443                         return -EINVAL;
2444                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2445                 break;
2446         default:
2447                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2448                 return -EINVAL;
2449         }
2450
2451         switch (nfilter->dst_ip_mask) {
2452         case UINT32_MAX:
2453                 bfilter->dst_ipaddr_mask[0] = -1;
2454                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2456                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2457                 break;
2458         default:
2459                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2460                 return -EINVAL;
2461         }
2462
2463         switch (nfilter->src_ip_mask) {
2464         case UINT32_MAX:
2465                 bfilter->src_ipaddr_mask[0] = -1;
2466                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2467                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2468                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2469                 break;
2470         default:
2471                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2472                 return -EINVAL;
2473         }
2474
2475         switch (nfilter->src_port_mask) {
2476         case UINT16_MAX:
2477                 bfilter->src_port_mask = -1;
2478                 bfilter->src_port = nfilter->src_port;
2479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2480                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2481                 break;
2482         default:
2483                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2484                 return -EINVAL;
2485         }
2486
2487         //TODO Priority
2488         //nfilter->priority = (uint8_t)filter->priority;
2489
2490         bfilter->enables = en;
2491         return 0;
2492 }
2493
2494 static struct bnxt_filter_info*
2495 bnxt_match_ntuple_filter(struct bnxt *bp,
2496                          struct bnxt_filter_info *bfilter,
2497                          struct bnxt_vnic_info **mvnic)
2498 {
2499         struct bnxt_filter_info *mfilter = NULL;
2500         int i;
2501
2502         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2503                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2504                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2505                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2506                             bfilter->src_ipaddr_mask[0] ==
2507                             mfilter->src_ipaddr_mask[0] &&
2508                             bfilter->src_port == mfilter->src_port &&
2509                             bfilter->src_port_mask == mfilter->src_port_mask &&
2510                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2511                             bfilter->dst_ipaddr_mask[0] ==
2512                             mfilter->dst_ipaddr_mask[0] &&
2513                             bfilter->dst_port == mfilter->dst_port &&
2514                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2515                             bfilter->flags == mfilter->flags &&
2516                             bfilter->enables == mfilter->enables) {
2517                                 if (mvnic)
2518                                         *mvnic = vnic;
2519                                 return mfilter;
2520                         }
2521                 }
2522         }
2523         return NULL;
2524 }
2525
2526 static int
2527 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2528                        struct rte_eth_ntuple_filter *nfilter,
2529                        enum rte_filter_op filter_op)
2530 {
2531         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2532         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2533         int ret;
2534
2535         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2536                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2537                 return -EINVAL;
2538         }
2539
2540         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2541                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2542                 return -EINVAL;
2543         }
2544
2545         bfilter = bnxt_get_unused_filter(bp);
2546         if (bfilter == NULL) {
2547                 PMD_DRV_LOG(ERR,
2548                         "Not enough resources for a new filter.\n");
2549                 return -ENOMEM;
2550         }
2551         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2552         if (ret < 0)
2553                 goto free_filter;
2554
2555         vnic = &bp->vnic_info[nfilter->queue];
2556         vnic0 = &bp->vnic_info[0];
2557         filter1 = STAILQ_FIRST(&vnic0->filter);
2558         if (filter1 == NULL) {
2559                 ret = -EINVAL;
2560                 goto free_filter;
2561         }
2562
2563         bfilter->dst_id = vnic->fw_vnic_id;
2564         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2565         bfilter->enables |=
2566                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2567         bfilter->ethertype = 0x800;
2568         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2569
2570         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2571
2572         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2573             bfilter->dst_id == mfilter->dst_id) {
2574                 PMD_DRV_LOG(ERR, "filter exists.\n");
2575                 ret = -EEXIST;
2576                 goto free_filter;
2577         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2578                    bfilter->dst_id != mfilter->dst_id) {
2579                 mfilter->dst_id = vnic->fw_vnic_id;
2580                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2581                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2582                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2583                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2584                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2585                 goto free_filter;
2586         }
2587         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2588                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2589                 ret = -ENOENT;
2590                 goto free_filter;
2591         }
2592
2593         if (filter_op == RTE_ETH_FILTER_ADD) {
2594                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2595                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2596                 if (ret)
2597                         goto free_filter;
2598                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2599         } else {
2600                 if (mfilter == NULL) {
2601                         /* This should not happen. But for Coverity! */
2602                         ret = -ENOENT;
2603                         goto free_filter;
2604                 }
2605                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2606
2607                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2608                 bnxt_free_filter(bp, mfilter);
2609                 mfilter->fw_l2_filter_id = -1;
2610                 bnxt_free_filter(bp, bfilter);
2611                 bfilter->fw_l2_filter_id = -1;
2612         }
2613
2614         return 0;
2615 free_filter:
2616         bfilter->fw_l2_filter_id = -1;
2617         bnxt_free_filter(bp, bfilter);
2618         return ret;
2619 }
2620
2621 static int
2622 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2623                         enum rte_filter_op filter_op,
2624                         void *arg)
2625 {
2626         struct bnxt *bp = dev->data->dev_private;
2627         int ret;
2628
2629         if (filter_op == RTE_ETH_FILTER_NOP)
2630                 return 0;
2631
2632         if (arg == NULL) {
2633                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2634                             filter_op);
2635                 return -EINVAL;
2636         }
2637
2638         switch (filter_op) {
2639         case RTE_ETH_FILTER_ADD:
2640                 ret = bnxt_cfg_ntuple_filter(bp,
2641                         (struct rte_eth_ntuple_filter *)arg,
2642                         filter_op);
2643                 break;
2644         case RTE_ETH_FILTER_DELETE:
2645                 ret = bnxt_cfg_ntuple_filter(bp,
2646                         (struct rte_eth_ntuple_filter *)arg,
2647                         filter_op);
2648                 break;
2649         default:
2650                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2651                 ret = -EINVAL;
2652                 break;
2653         }
2654         return ret;
2655 }
2656
2657 static int
2658 bnxt_parse_fdir_filter(struct bnxt *bp,
2659                        struct rte_eth_fdir_filter *fdir,
2660                        struct bnxt_filter_info *filter)
2661 {
2662         enum rte_fdir_mode fdir_mode =
2663                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2664         struct bnxt_vnic_info *vnic0, *vnic;
2665         struct bnxt_filter_info *filter1;
2666         uint32_t en = 0;
2667         int i;
2668
2669         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2670                 return -EINVAL;
2671
2672         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2673         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2674
2675         switch (fdir->input.flow_type) {
2676         case RTE_ETH_FLOW_IPV4:
2677         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2678                 /* FALLTHROUGH */
2679                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2680                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2681                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2682                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2683                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2684                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2685                 filter->ip_addr_type =
2686                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2687                 filter->src_ipaddr_mask[0] = 0xffffffff;
2688                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2689                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2690                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2691                 filter->ethertype = 0x800;
2692                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2693                 break;
2694         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2695                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2696                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2697                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2698                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2699                 filter->dst_port_mask = 0xffff;
2700                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2701                 filter->src_port_mask = 0xffff;
2702                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2703                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2704                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2705                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2706                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2707                 filter->ip_protocol = 6;
2708                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2709                 filter->ip_addr_type =
2710                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2711                 filter->src_ipaddr_mask[0] = 0xffffffff;
2712                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2713                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2714                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2715                 filter->ethertype = 0x800;
2716                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2717                 break;
2718         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2719                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2720                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2721                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2722                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2723                 filter->dst_port_mask = 0xffff;
2724                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2725                 filter->src_port_mask = 0xffff;
2726                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2727                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2728                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2729                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2730                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2731                 filter->ip_protocol = 17;
2732                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2733                 filter->ip_addr_type =
2734                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2735                 filter->src_ipaddr_mask[0] = 0xffffffff;
2736                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2737                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2738                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2739                 filter->ethertype = 0x800;
2740                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2741                 break;
2742         case RTE_ETH_FLOW_IPV6:
2743         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2744                 /* FALLTHROUGH */
2745                 filter->ip_addr_type =
2746                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2747                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2748                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2749                 rte_memcpy(filter->src_ipaddr,
2750                            fdir->input.flow.ipv6_flow.src_ip, 16);
2751                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2752                 rte_memcpy(filter->dst_ipaddr,
2753                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2754                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2755                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2756                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2757                 memset(filter->src_ipaddr_mask, 0xff, 16);
2758                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2759                 filter->ethertype = 0x86dd;
2760                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2761                 break;
2762         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2763                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2764                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2765                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2766                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2767                 filter->dst_port_mask = 0xffff;
2768                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2769                 filter->src_port_mask = 0xffff;
2770                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2771                 filter->ip_addr_type =
2772                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2773                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2774                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2775                 rte_memcpy(filter->src_ipaddr,
2776                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2777                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2778                 rte_memcpy(filter->dst_ipaddr,
2779                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2780                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2781                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2782                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2783                 memset(filter->src_ipaddr_mask, 0xff, 16);
2784                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2785                 filter->ethertype = 0x86dd;
2786                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2787                 break;
2788         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2789                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2790                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2791                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2792                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2793                 filter->dst_port_mask = 0xffff;
2794                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2795                 filter->src_port_mask = 0xffff;
2796                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2797                 filter->ip_addr_type =
2798                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2799                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2800                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2801                 rte_memcpy(filter->src_ipaddr,
2802                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2803                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2804                 rte_memcpy(filter->dst_ipaddr,
2805                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2806                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2807                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2808                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2809                 memset(filter->src_ipaddr_mask, 0xff, 16);
2810                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2811                 filter->ethertype = 0x86dd;
2812                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2813                 break;
2814         case RTE_ETH_FLOW_L2_PAYLOAD:
2815                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2816                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2817                 break;
2818         case RTE_ETH_FLOW_VXLAN:
2819                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2820                         return -EINVAL;
2821                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2822                 filter->tunnel_type =
2823                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2824                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2825                 break;
2826         case RTE_ETH_FLOW_NVGRE:
2827                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2828                         return -EINVAL;
2829                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2830                 filter->tunnel_type =
2831                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2832                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2833                 break;
2834         case RTE_ETH_FLOW_UNKNOWN:
2835         case RTE_ETH_FLOW_RAW:
2836         case RTE_ETH_FLOW_FRAG_IPV4:
2837         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2838         case RTE_ETH_FLOW_FRAG_IPV6:
2839         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2840         case RTE_ETH_FLOW_IPV6_EX:
2841         case RTE_ETH_FLOW_IPV6_TCP_EX:
2842         case RTE_ETH_FLOW_IPV6_UDP_EX:
2843         case RTE_ETH_FLOW_GENEVE:
2844                 /* FALLTHROUGH */
2845         default:
2846                 return -EINVAL;
2847         }
2848
2849         vnic0 = &bp->vnic_info[0];
2850         vnic = &bp->vnic_info[fdir->action.rx_queue];
2851         if (vnic == NULL) {
2852                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2853                 return -EINVAL;
2854         }
2855
2856
2857         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2858                 rte_memcpy(filter->dst_macaddr,
2859                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2860                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2861         }
2862
2863         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2864                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2865                 filter1 = STAILQ_FIRST(&vnic0->filter);
2866                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2867         } else {
2868                 filter->dst_id = vnic->fw_vnic_id;
2869                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2870                         if (filter->dst_macaddr[i] == 0x00)
2871                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2872                         else
2873                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2874         }
2875
2876         if (filter1 == NULL)
2877                 return -EINVAL;
2878
2879         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2880         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2881
2882         filter->enables = en;
2883
2884         return 0;
2885 }
2886
2887 static struct bnxt_filter_info *
2888 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2889                 struct bnxt_vnic_info **mvnic)
2890 {
2891         struct bnxt_filter_info *mf = NULL;
2892         int i;
2893
2894         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2895                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2896
2897                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2898                         if (mf->filter_type == nf->filter_type &&
2899                             mf->flags == nf->flags &&
2900                             mf->src_port == nf->src_port &&
2901                             mf->src_port_mask == nf->src_port_mask &&
2902                             mf->dst_port == nf->dst_port &&
2903                             mf->dst_port_mask == nf->dst_port_mask &&
2904                             mf->ip_protocol == nf->ip_protocol &&
2905                             mf->ip_addr_type == nf->ip_addr_type &&
2906                             mf->ethertype == nf->ethertype &&
2907                             mf->vni == nf->vni &&
2908                             mf->tunnel_type == nf->tunnel_type &&
2909                             mf->l2_ovlan == nf->l2_ovlan &&
2910                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2911                             mf->l2_ivlan == nf->l2_ivlan &&
2912                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2913                             !memcmp(mf->l2_addr, nf->l2_addr,
2914                                     RTE_ETHER_ADDR_LEN) &&
2915                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2916                                     RTE_ETHER_ADDR_LEN) &&
2917                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2918                                     RTE_ETHER_ADDR_LEN) &&
2919                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2920                                     RTE_ETHER_ADDR_LEN) &&
2921                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2922                                     sizeof(nf->src_ipaddr)) &&
2923                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2924                                     sizeof(nf->src_ipaddr_mask)) &&
2925                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2926                                     sizeof(nf->dst_ipaddr)) &&
2927                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2928                                     sizeof(nf->dst_ipaddr_mask))) {
2929                                 if (mvnic)
2930                                         *mvnic = vnic;
2931                                 return mf;
2932                         }
2933                 }
2934         }
2935         return NULL;
2936 }
2937
2938 static int
2939 bnxt_fdir_filter(struct rte_eth_dev *dev,
2940                  enum rte_filter_op filter_op,
2941                  void *arg)
2942 {
2943         struct bnxt *bp = dev->data->dev_private;
2944         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2945         struct bnxt_filter_info *filter, *match;
2946         struct bnxt_vnic_info *vnic, *mvnic;
2947         int ret = 0, i;
2948
2949         if (filter_op == RTE_ETH_FILTER_NOP)
2950                 return 0;
2951
2952         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2953                 return -EINVAL;
2954
2955         switch (filter_op) {
2956         case RTE_ETH_FILTER_ADD:
2957         case RTE_ETH_FILTER_DELETE:
2958                 /* FALLTHROUGH */
2959                 filter = bnxt_get_unused_filter(bp);
2960                 if (filter == NULL) {
2961                         PMD_DRV_LOG(ERR,
2962                                 "Not enough resources for a new flow.\n");
2963                         return -ENOMEM;
2964                 }
2965
2966                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2967                 if (ret != 0)
2968                         goto free_filter;
2969                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2970
2971                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2972                         vnic = &bp->vnic_info[0];
2973                 else
2974                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2975
2976                 match = bnxt_match_fdir(bp, filter, &mvnic);
2977                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2978                         if (match->dst_id == vnic->fw_vnic_id) {
2979                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2980                                 ret = -EEXIST;
2981                                 goto free_filter;
2982                         } else {
2983                                 match->dst_id = vnic->fw_vnic_id;
2984                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2985                                                                   match->dst_id,
2986                                                                   match);
2987                                 STAILQ_REMOVE(&mvnic->filter, match,
2988                                               bnxt_filter_info, next);
2989                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2990                                 PMD_DRV_LOG(ERR,
2991                                         "Filter with matching pattern exist\n");
2992                                 PMD_DRV_LOG(ERR,
2993                                         "Updated it to new destination q\n");
2994                                 goto free_filter;
2995                         }
2996                 }
2997                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2998                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2999                         ret = -ENOENT;
3000                         goto free_filter;
3001                 }
3002
3003                 if (filter_op == RTE_ETH_FILTER_ADD) {
3004                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3005                                                           filter->dst_id,
3006                                                           filter);
3007                         if (ret)
3008                                 goto free_filter;
3009                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3010                 } else {
3011                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3012                         STAILQ_REMOVE(&vnic->filter, match,
3013                                       bnxt_filter_info, next);
3014                         bnxt_free_filter(bp, match);
3015                         filter->fw_l2_filter_id = -1;
3016                         bnxt_free_filter(bp, filter);
3017                 }
3018                 break;
3019         case RTE_ETH_FILTER_FLUSH:
3020                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3021                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3022
3023                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3024                                 if (filter->filter_type ==
3025                                     HWRM_CFA_NTUPLE_FILTER) {
3026                                         ret =
3027                                         bnxt_hwrm_clear_ntuple_filter(bp,
3028                                                                       filter);
3029                                         STAILQ_REMOVE(&vnic->filter, filter,
3030                                                       bnxt_filter_info, next);
3031                                 }
3032                         }
3033                 }
3034                 return ret;
3035         case RTE_ETH_FILTER_UPDATE:
3036         case RTE_ETH_FILTER_STATS:
3037         case RTE_ETH_FILTER_INFO:
3038                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3039                 break;
3040         default:
3041                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3042                 ret = -EINVAL;
3043                 break;
3044         }
3045         return ret;
3046
3047 free_filter:
3048         filter->fw_l2_filter_id = -1;
3049         bnxt_free_filter(bp, filter);
3050         return ret;
3051 }
3052
3053 static int
3054 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3055                     enum rte_filter_type filter_type,
3056                     enum rte_filter_op filter_op, void *arg)
3057 {
3058         int ret = 0;
3059
3060         ret = is_bnxt_in_error(dev->data->dev_private);
3061         if (ret)
3062                 return ret;
3063
3064         switch (filter_type) {
3065         case RTE_ETH_FILTER_TUNNEL:
3066                 PMD_DRV_LOG(ERR,
3067                         "filter type: %d: To be implemented\n", filter_type);
3068                 break;
3069         case RTE_ETH_FILTER_FDIR:
3070                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3071                 break;
3072         case RTE_ETH_FILTER_NTUPLE:
3073                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3074                 break;
3075         case RTE_ETH_FILTER_ETHERTYPE:
3076                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3077                 break;
3078         case RTE_ETH_FILTER_GENERIC:
3079                 if (filter_op != RTE_ETH_FILTER_GET)
3080                         return -EINVAL;
3081                 *(const void **)arg = &bnxt_flow_ops;
3082                 break;
3083         default:
3084                 PMD_DRV_LOG(ERR,
3085                         "Filter type (%d) not supported", filter_type);
3086                 ret = -EINVAL;
3087                 break;
3088         }
3089         return ret;
3090 }
3091
3092 static const uint32_t *
3093 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3094 {
3095         static const uint32_t ptypes[] = {
3096                 RTE_PTYPE_L2_ETHER_VLAN,
3097                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3098                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3099                 RTE_PTYPE_L4_ICMP,
3100                 RTE_PTYPE_L4_TCP,
3101                 RTE_PTYPE_L4_UDP,
3102                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3103                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3104                 RTE_PTYPE_INNER_L4_ICMP,
3105                 RTE_PTYPE_INNER_L4_TCP,
3106                 RTE_PTYPE_INNER_L4_UDP,
3107                 RTE_PTYPE_UNKNOWN
3108         };
3109
3110         if (!dev->rx_pkt_burst)
3111                 return NULL;
3112
3113         return ptypes;
3114 }
3115
3116 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3117                          int reg_win)
3118 {
3119         uint32_t reg_base = *reg_arr & 0xfffff000;
3120         uint32_t win_off;
3121         int i;
3122
3123         for (i = 0; i < count; i++) {
3124                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3125                         return -ERANGE;
3126         }
3127         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3128         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3129         return 0;
3130 }
3131
3132 static int bnxt_map_ptp_regs(struct bnxt *bp)
3133 {
3134         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3135         uint32_t *reg_arr;
3136         int rc, i;
3137
3138         reg_arr = ptp->rx_regs;
3139         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3140         if (rc)
3141                 return rc;
3142
3143         reg_arr = ptp->tx_regs;
3144         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3145         if (rc)
3146                 return rc;
3147
3148         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3149                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3150
3151         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3152                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3153
3154         return 0;
3155 }
3156
3157 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3158 {
3159         rte_write32(0, (uint8_t *)bp->bar0 +
3160                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3161         rte_write32(0, (uint8_t *)bp->bar0 +
3162                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3163 }
3164
3165 static uint64_t bnxt_cc_read(struct bnxt *bp)
3166 {
3167         uint64_t ns;
3168
3169         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3170                               BNXT_GRCPF_REG_SYNC_TIME));
3171         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3172                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3173         return ns;
3174 }
3175
3176 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3177 {
3178         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3179         uint32_t fifo;
3180
3181         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3182                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3183         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3184                 return -EAGAIN;
3185
3186         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3187                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3188         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3189                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3190         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3191                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3192
3193         return 0;
3194 }
3195
3196 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3197 {
3198         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3199         struct bnxt_pf_info *pf = &bp->pf;
3200         uint16_t port_id;
3201         uint32_t fifo;
3202
3203         if (!ptp)
3204                 return -ENODEV;
3205
3206         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3207                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3208         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3209                 return -EAGAIN;
3210
3211         port_id = pf->port_id;
3212         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3213                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3214
3215         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3216                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3217         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3218 /*              bnxt_clr_rx_ts(bp);       TBD  */
3219                 return -EBUSY;
3220         }
3221
3222         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3223                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3224         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3225                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3226
3227         return 0;
3228 }
3229
3230 static int
3231 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3232 {
3233         uint64_t ns;
3234         struct bnxt *bp = dev->data->dev_private;
3235         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3236
3237         if (!ptp)
3238                 return 0;
3239
3240         ns = rte_timespec_to_ns(ts);
3241         /* Set the timecounters to a new value. */
3242         ptp->tc.nsec = ns;
3243
3244         return 0;
3245 }
3246
3247 static int
3248 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3249 {
3250         struct bnxt *bp = dev->data->dev_private;
3251         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3252         uint64_t ns, systime_cycles = 0;
3253         int rc = 0;
3254
3255         if (!ptp)
3256                 return 0;
3257
3258         if (BNXT_CHIP_THOR(bp))
3259                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3260                                              &systime_cycles);
3261         else
3262                 systime_cycles = bnxt_cc_read(bp);
3263
3264         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3265         *ts = rte_ns_to_timespec(ns);
3266
3267         return rc;
3268 }
3269 static int
3270 bnxt_timesync_enable(struct rte_eth_dev *dev)
3271 {
3272         struct bnxt *bp = dev->data->dev_private;
3273         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3274         uint32_t shift = 0;
3275         int rc;
3276
3277         if (!ptp)
3278                 return 0;
3279
3280         ptp->rx_filter = 1;
3281         ptp->tx_tstamp_en = 1;
3282         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3283
3284         rc = bnxt_hwrm_ptp_cfg(bp);
3285         if (rc)
3286                 return rc;
3287
3288         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3289         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3290         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3291
3292         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3293         ptp->tc.cc_shift = shift;
3294         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3295
3296         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3297         ptp->rx_tstamp_tc.cc_shift = shift;
3298         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3299
3300         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3301         ptp->tx_tstamp_tc.cc_shift = shift;
3302         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3303
3304         if (!BNXT_CHIP_THOR(bp))
3305                 bnxt_map_ptp_regs(bp);
3306
3307         return 0;
3308 }
3309
3310 static int
3311 bnxt_timesync_disable(struct rte_eth_dev *dev)
3312 {
3313         struct bnxt *bp = dev->data->dev_private;
3314         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3315
3316         if (!ptp)
3317                 return 0;
3318
3319         ptp->rx_filter = 0;
3320         ptp->tx_tstamp_en = 0;
3321         ptp->rxctl = 0;
3322
3323         bnxt_hwrm_ptp_cfg(bp);
3324
3325         if (!BNXT_CHIP_THOR(bp))
3326                 bnxt_unmap_ptp_regs(bp);
3327
3328         return 0;
3329 }
3330
3331 static int
3332 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3333                                  struct timespec *timestamp,
3334                                  uint32_t flags __rte_unused)
3335 {
3336         struct bnxt *bp = dev->data->dev_private;
3337         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3338         uint64_t rx_tstamp_cycles = 0;
3339         uint64_t ns;
3340
3341         if (!ptp)
3342                 return 0;
3343
3344         if (BNXT_CHIP_THOR(bp))
3345                 rx_tstamp_cycles = ptp->rx_timestamp;
3346         else
3347                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3348
3349         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3350         *timestamp = rte_ns_to_timespec(ns);
3351         return  0;
3352 }
3353
3354 static int
3355 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3356                                  struct timespec *timestamp)
3357 {
3358         struct bnxt *bp = dev->data->dev_private;
3359         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3360         uint64_t tx_tstamp_cycles = 0;
3361         uint64_t ns;
3362         int rc = 0;
3363
3364         if (!ptp)
3365                 return 0;
3366
3367         if (BNXT_CHIP_THOR(bp))
3368                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3369                                              &tx_tstamp_cycles);
3370         else
3371                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3372
3373         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3374         *timestamp = rte_ns_to_timespec(ns);
3375
3376         return rc;
3377 }
3378
3379 static int
3380 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3381 {
3382         struct bnxt *bp = dev->data->dev_private;
3383         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3384
3385         if (!ptp)
3386                 return 0;
3387
3388         ptp->tc.nsec += delta;
3389
3390         return 0;
3391 }
3392
3393 static int
3394 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3395 {
3396         struct bnxt *bp = dev->data->dev_private;
3397         int rc;
3398         uint32_t dir_entries;
3399         uint32_t entry_length;
3400
3401         rc = is_bnxt_in_error(bp);
3402         if (rc)
3403                 return rc;
3404
3405         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3406                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3407                 bp->pdev->addr.devid, bp->pdev->addr.function);
3408
3409         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3410         if (rc != 0)
3411                 return rc;
3412
3413         return dir_entries * entry_length;
3414 }
3415
3416 static int
3417 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3418                 struct rte_dev_eeprom_info *in_eeprom)
3419 {
3420         struct bnxt *bp = dev->data->dev_private;
3421         uint32_t index;
3422         uint32_t offset;
3423         int rc;
3424
3425         rc = is_bnxt_in_error(bp);
3426         if (rc)
3427                 return rc;
3428
3429         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3430                 "len = %d\n", bp->pdev->addr.domain,
3431                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3432                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3433
3434         if (in_eeprom->offset == 0) /* special offset value to get directory */
3435                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3436                                                 in_eeprom->data);
3437
3438         index = in_eeprom->offset >> 24;
3439         offset = in_eeprom->offset & 0xffffff;
3440
3441         if (index != 0)
3442                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3443                                            in_eeprom->length, in_eeprom->data);
3444
3445         return 0;
3446 }
3447
3448 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3449 {
3450         switch (dir_type) {
3451         case BNX_DIR_TYPE_CHIMP_PATCH:
3452         case BNX_DIR_TYPE_BOOTCODE:
3453         case BNX_DIR_TYPE_BOOTCODE_2:
3454         case BNX_DIR_TYPE_APE_FW:
3455         case BNX_DIR_TYPE_APE_PATCH:
3456         case BNX_DIR_TYPE_KONG_FW:
3457         case BNX_DIR_TYPE_KONG_PATCH:
3458         case BNX_DIR_TYPE_BONO_FW:
3459         case BNX_DIR_TYPE_BONO_PATCH:
3460                 /* FALLTHROUGH */
3461                 return true;
3462         }
3463
3464         return false;
3465 }
3466
3467 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3468 {
3469         switch (dir_type) {
3470         case BNX_DIR_TYPE_AVS:
3471         case BNX_DIR_TYPE_EXP_ROM_MBA:
3472         case BNX_DIR_TYPE_PCIE:
3473         case BNX_DIR_TYPE_TSCF_UCODE:
3474         case BNX_DIR_TYPE_EXT_PHY:
3475         case BNX_DIR_TYPE_CCM:
3476         case BNX_DIR_TYPE_ISCSI_BOOT:
3477         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3478         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3479                 /* FALLTHROUGH */
3480                 return true;
3481         }
3482
3483         return false;
3484 }
3485
3486 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3487 {
3488         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3489                 bnxt_dir_type_is_other_exec_format(dir_type);
3490 }
3491
3492 static int
3493 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3494                 struct rte_dev_eeprom_info *in_eeprom)
3495 {
3496         struct bnxt *bp = dev->data->dev_private;
3497         uint8_t index, dir_op;
3498         uint16_t type, ext, ordinal, attr;
3499         int rc;
3500
3501         rc = is_bnxt_in_error(bp);
3502         if (rc)
3503                 return rc;
3504
3505         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3506                 "len = %d\n", bp->pdev->addr.domain,
3507                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3508                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3509
3510         if (!BNXT_PF(bp)) {
3511                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3512                 return -EINVAL;
3513         }
3514
3515         type = in_eeprom->magic >> 16;
3516
3517         if (type == 0xffff) { /* special value for directory operations */
3518                 index = in_eeprom->magic & 0xff;
3519                 dir_op = in_eeprom->magic >> 8;
3520                 if (index == 0)
3521                         return -EINVAL;
3522                 switch (dir_op) {
3523                 case 0x0e: /* erase */
3524                         if (in_eeprom->offset != ~in_eeprom->magic)
3525                                 return -EINVAL;
3526                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3527                 default:
3528                         return -EINVAL;
3529                 }
3530         }
3531
3532         /* Create or re-write an NVM item: */
3533         if (bnxt_dir_type_is_executable(type) == true)
3534                 return -EOPNOTSUPP;
3535         ext = in_eeprom->magic & 0xffff;
3536         ordinal = in_eeprom->offset >> 16;
3537         attr = in_eeprom->offset & 0xffff;
3538
3539         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3540                                      in_eeprom->data, in_eeprom->length);
3541 }
3542
3543 /*
3544  * Initialization
3545  */
3546
3547 static const struct eth_dev_ops bnxt_dev_ops = {
3548         .dev_infos_get = bnxt_dev_info_get_op,
3549         .dev_close = bnxt_dev_close_op,
3550         .dev_configure = bnxt_dev_configure_op,
3551         .dev_start = bnxt_dev_start_op,
3552         .dev_stop = bnxt_dev_stop_op,
3553         .dev_set_link_up = bnxt_dev_set_link_up_op,
3554         .dev_set_link_down = bnxt_dev_set_link_down_op,
3555         .stats_get = bnxt_stats_get_op,
3556         .stats_reset = bnxt_stats_reset_op,
3557         .rx_queue_setup = bnxt_rx_queue_setup_op,
3558         .rx_queue_release = bnxt_rx_queue_release_op,
3559         .tx_queue_setup = bnxt_tx_queue_setup_op,
3560         .tx_queue_release = bnxt_tx_queue_release_op,
3561         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3562         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3563         .reta_update = bnxt_reta_update_op,
3564         .reta_query = bnxt_reta_query_op,
3565         .rss_hash_update = bnxt_rss_hash_update_op,
3566         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3567         .link_update = bnxt_link_update_op,
3568         .promiscuous_enable = bnxt_promiscuous_enable_op,
3569         .promiscuous_disable = bnxt_promiscuous_disable_op,
3570         .allmulticast_enable = bnxt_allmulticast_enable_op,
3571         .allmulticast_disable = bnxt_allmulticast_disable_op,
3572         .mac_addr_add = bnxt_mac_addr_add_op,
3573         .mac_addr_remove = bnxt_mac_addr_remove_op,
3574         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3575         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3576         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3577         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3578         .vlan_filter_set = bnxt_vlan_filter_set_op,
3579         .vlan_offload_set = bnxt_vlan_offload_set_op,
3580         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3581         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3582         .mtu_set = bnxt_mtu_set_op,
3583         .mac_addr_set = bnxt_set_default_mac_addr_op,
3584         .xstats_get = bnxt_dev_xstats_get_op,
3585         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3586         .xstats_reset = bnxt_dev_xstats_reset_op,
3587         .fw_version_get = bnxt_fw_version_get,
3588         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3589         .rxq_info_get = bnxt_rxq_info_get_op,
3590         .txq_info_get = bnxt_txq_info_get_op,
3591         .dev_led_on = bnxt_dev_led_on_op,
3592         .dev_led_off = bnxt_dev_led_off_op,
3593         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3594         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3595         .rx_queue_count = bnxt_rx_queue_count_op,
3596         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3597         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3598         .rx_queue_start = bnxt_rx_queue_start,
3599         .rx_queue_stop = bnxt_rx_queue_stop,
3600         .tx_queue_start = bnxt_tx_queue_start,
3601         .tx_queue_stop = bnxt_tx_queue_stop,
3602         .filter_ctrl = bnxt_filter_ctrl_op,
3603         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3604         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3605         .get_eeprom           = bnxt_get_eeprom_op,
3606         .set_eeprom           = bnxt_set_eeprom_op,
3607         .timesync_enable      = bnxt_timesync_enable,
3608         .timesync_disable     = bnxt_timesync_disable,
3609         .timesync_read_time   = bnxt_timesync_read_time,
3610         .timesync_write_time   = bnxt_timesync_write_time,
3611         .timesync_adjust_time = bnxt_timesync_adjust_time,
3612         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3613         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3614 };
3615
3616 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3617 {
3618         uint32_t offset;
3619
3620         /* Only pre-map the reset GRC registers using window 3 */
3621         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3622                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3623
3624         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3625
3626         return offset;
3627 }
3628
3629 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3630 {
3631         struct bnxt_error_recovery_info *info = bp->recovery_info;
3632         uint32_t reg_base = 0xffffffff;
3633         int i;
3634
3635         /* Only pre-map the monitoring GRC registers using window 2 */
3636         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3637                 uint32_t reg = info->status_regs[i];
3638
3639                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3640                         continue;
3641
3642                 if (reg_base == 0xffffffff)
3643                         reg_base = reg & 0xfffff000;
3644                 if ((reg & 0xfffff000) != reg_base)
3645                         return -ERANGE;
3646
3647                 /* Use mask 0xffc as the Lower 2 bits indicates
3648                  * address space location
3649                  */
3650                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3651                                                 (reg & 0xffc);
3652         }
3653
3654         if (reg_base == 0xffffffff)
3655                 return 0;
3656
3657         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3658                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3659
3660         return 0;
3661 }
3662
3663 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3664 {
3665         struct bnxt_error_recovery_info *info = bp->recovery_info;
3666         uint32_t delay = info->delay_after_reset[index];
3667         uint32_t val = info->reset_reg_val[index];
3668         uint32_t reg = info->reset_reg[index];
3669         uint32_t type, offset;
3670
3671         type = BNXT_FW_STATUS_REG_TYPE(reg);
3672         offset = BNXT_FW_STATUS_REG_OFF(reg);
3673
3674         switch (type) {
3675         case BNXT_FW_STATUS_REG_TYPE_CFG:
3676                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3677                 break;
3678         case BNXT_FW_STATUS_REG_TYPE_GRC:
3679                 offset = bnxt_map_reset_regs(bp, offset);
3680                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3681                 break;
3682         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3683                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3684                 break;
3685         }
3686         /* wait on a specific interval of time until core reset is complete */
3687         if (delay)
3688                 rte_delay_ms(delay);
3689 }
3690
3691 static void bnxt_dev_cleanup(struct bnxt *bp)
3692 {
3693         bnxt_set_hwrm_link_config(bp, false);
3694         bp->link_info.link_up = 0;
3695         if (bp->dev_stopped == 0)
3696                 bnxt_dev_stop_op(bp->eth_dev);
3697
3698         bnxt_uninit_resources(bp, true);
3699 }
3700
3701 static int bnxt_restore_filters(struct bnxt *bp)
3702 {
3703         struct rte_eth_dev *dev = bp->eth_dev;
3704         int ret = 0;
3705
3706         if (dev->data->all_multicast)
3707                 ret = bnxt_allmulticast_enable_op(dev);
3708         if (dev->data->promiscuous)
3709                 ret = bnxt_promiscuous_enable_op(dev);
3710
3711         /* TODO restore other filters as well */
3712         return ret;
3713 }
3714
3715 static void bnxt_dev_recover(void *arg)
3716 {
3717         struct bnxt *bp = arg;
3718         int timeout = bp->fw_reset_max_msecs;
3719         int rc = 0;
3720
3721         /* Clear Error flag so that device re-init should happen */
3722         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3723
3724         do {
3725                 rc = bnxt_hwrm_ver_get(bp);
3726                 if (rc == 0)
3727                         break;
3728                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3729                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3730         } while (rc && timeout);
3731
3732         if (rc) {
3733                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3734                 goto err;
3735         }
3736
3737         rc = bnxt_init_resources(bp, true);
3738         if (rc) {
3739                 PMD_DRV_LOG(ERR,
3740                             "Failed to initialize resources after reset\n");
3741                 goto err;
3742         }
3743         /* clear reset flag as the device is initialized now */
3744         bp->flags &= ~BNXT_FLAG_FW_RESET;
3745
3746         rc = bnxt_dev_start_op(bp->eth_dev);
3747         if (rc) {
3748                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3749                 goto err;
3750         }
3751
3752         rc = bnxt_restore_filters(bp);
3753         if (rc)
3754                 goto err;
3755
3756         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3757         return;
3758 err:
3759         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3760         bnxt_uninit_resources(bp, false);
3761         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3762 }
3763
3764 void bnxt_dev_reset_and_resume(void *arg)
3765 {
3766         struct bnxt *bp = arg;
3767         int rc;
3768
3769         bnxt_dev_cleanup(bp);
3770
3771         bnxt_wait_for_device_shutdown(bp);
3772
3773         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3774                                bnxt_dev_recover, (void *)bp);
3775         if (rc)
3776                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3777 }
3778
3779 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3780 {
3781         struct bnxt_error_recovery_info *info = bp->recovery_info;
3782         uint32_t reg = info->status_regs[index];
3783         uint32_t type, offset, val = 0;
3784
3785         type = BNXT_FW_STATUS_REG_TYPE(reg);
3786         offset = BNXT_FW_STATUS_REG_OFF(reg);
3787
3788         switch (type) {
3789         case BNXT_FW_STATUS_REG_TYPE_CFG:
3790                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3791                 break;
3792         case BNXT_FW_STATUS_REG_TYPE_GRC:
3793                 offset = info->mapped_status_regs[index];
3794                 /* FALLTHROUGH */
3795         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3796                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3797                                        offset));
3798                 break;
3799         }
3800
3801         return val;
3802 }
3803
3804 static int bnxt_fw_reset_all(struct bnxt *bp)
3805 {
3806         struct bnxt_error_recovery_info *info = bp->recovery_info;
3807         uint32_t i;
3808         int rc = 0;
3809
3810         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3811                 /* Reset through master function driver */
3812                 for (i = 0; i < info->reg_array_cnt; i++)
3813                         bnxt_write_fw_reset_reg(bp, i);
3814                 /* Wait for time specified by FW after triggering reset */
3815                 rte_delay_ms(info->master_func_wait_period_after_reset);
3816         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3817                 /* Reset with the help of Kong processor */
3818                 rc = bnxt_hwrm_fw_reset(bp);
3819                 if (rc)
3820                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3821         }
3822
3823         return rc;
3824 }
3825
3826 static void bnxt_fw_reset_cb(void *arg)
3827 {
3828         struct bnxt *bp = arg;
3829         struct bnxt_error_recovery_info *info = bp->recovery_info;
3830         int rc = 0;
3831
3832         /* Only Master function can do FW reset */
3833         if (bnxt_is_master_func(bp) &&
3834             bnxt_is_recovery_enabled(bp)) {
3835                 rc = bnxt_fw_reset_all(bp);
3836                 if (rc) {
3837                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3838                         return;
3839                 }
3840         }
3841
3842         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3843          * EXCEPTION_FATAL_ASYNC event to all the functions
3844          * (including MASTER FUNC). After receiving this Async, all the active
3845          * drivers should treat this case as FW initiated recovery
3846          */
3847         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3848                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3849                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3850
3851                 /* To recover from error */
3852                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3853                                   (void *)bp);
3854         }
3855 }
3856
3857 /* Driver should poll FW heartbeat, reset_counter with the frequency
3858  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3859  * When the driver detects heartbeat stop or change in reset_counter,
3860  * it has to trigger a reset to recover from the error condition.
3861  * A “master PF” is the function who will have the privilege to
3862  * initiate the chimp reset. The master PF will be elected by the
3863  * firmware and will be notified through async message.
3864  */
3865 static void bnxt_check_fw_health(void *arg)
3866 {
3867         struct bnxt *bp = arg;
3868         struct bnxt_error_recovery_info *info = bp->recovery_info;
3869         uint32_t val = 0, wait_msec;
3870
3871         if (!info || !bnxt_is_recovery_enabled(bp) ||
3872             is_bnxt_in_error(bp))
3873                 return;
3874
3875         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3876         if (val == info->last_heart_beat)
3877                 goto reset;
3878
3879         info->last_heart_beat = val;
3880
3881         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3882         if (val != info->last_reset_counter)
3883                 goto reset;
3884
3885         info->last_reset_counter = val;
3886
3887         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3888                           bnxt_check_fw_health, (void *)bp);
3889
3890         return;
3891 reset:
3892         /* Stop DMA to/from device */
3893         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3894         bp->flags |= BNXT_FLAG_FW_RESET;
3895
3896         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3897
3898         if (bnxt_is_master_func(bp))
3899                 wait_msec = info->master_func_wait_period;
3900         else
3901                 wait_msec = info->normal_func_wait_period;
3902
3903         rte_eal_alarm_set(US_PER_MS * wait_msec,
3904                           bnxt_fw_reset_cb, (void *)bp);
3905 }
3906
3907 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3908 {
3909         uint32_t polling_freq;
3910
3911         if (!bnxt_is_recovery_enabled(bp))
3912                 return;
3913
3914         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3915                 return;
3916
3917         polling_freq = bp->recovery_info->driver_polling_freq;
3918
3919         rte_eal_alarm_set(US_PER_MS * polling_freq,
3920                           bnxt_check_fw_health, (void *)bp);
3921         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3922 }
3923
3924 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3925 {
3926         if (!bnxt_is_recovery_enabled(bp))
3927                 return;
3928
3929         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3930         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3931 }
3932
3933 static bool bnxt_vf_pciid(uint16_t id)
3934 {
3935         if (id == BROADCOM_DEV_ID_57304_VF ||
3936             id == BROADCOM_DEV_ID_57406_VF ||
3937             id == BROADCOM_DEV_ID_5731X_VF ||
3938             id == BROADCOM_DEV_ID_5741X_VF ||
3939             id == BROADCOM_DEV_ID_57414_VF ||
3940             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3941             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3942             id == BROADCOM_DEV_ID_58802_VF ||
3943             id == BROADCOM_DEV_ID_57500_VF1 ||
3944             id == BROADCOM_DEV_ID_57500_VF2)
3945                 return true;
3946         return false;
3947 }
3948
3949 bool bnxt_stratus_device(struct bnxt *bp)
3950 {
3951         uint16_t id = bp->pdev->id.device_id;
3952
3953         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3954             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3955             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3956                 return true;
3957         return false;
3958 }
3959
3960 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3961 {
3962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3963         struct bnxt *bp = eth_dev->data->dev_private;
3964
3965         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3966         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3967         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3968         if (!bp->bar0 || !bp->doorbell_base) {
3969                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3970                 return -ENODEV;
3971         }
3972
3973         bp->eth_dev = eth_dev;
3974         bp->pdev = pci_dev;
3975
3976         return 0;
3977 }
3978
3979 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3980                                   struct bnxt_ctx_pg_info *ctx_pg,
3981                                   uint32_t mem_size,
3982                                   const char *suffix,
3983                                   uint16_t idx)
3984 {
3985         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3986         const struct rte_memzone *mz = NULL;
3987         char mz_name[RTE_MEMZONE_NAMESIZE];
3988         rte_iova_t mz_phys_addr;
3989         uint64_t valid_bits = 0;
3990         uint32_t sz;
3991         int i;
3992
3993         if (!mem_size)
3994                 return 0;
3995
3996         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3997                          BNXT_PAGE_SIZE;
3998         rmem->page_size = BNXT_PAGE_SIZE;
3999         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4000         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4001         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4002
4003         valid_bits = PTU_PTE_VALID;
4004
4005         if (rmem->nr_pages > 1) {
4006                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4007                          "bnxt_ctx_pg_tbl%s_%x_%d",
4008                          suffix, idx, bp->eth_dev->data->port_id);
4009                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4010                 mz = rte_memzone_lookup(mz_name);
4011                 if (!mz) {
4012                         mz = rte_memzone_reserve_aligned(mz_name,
4013                                                 rmem->nr_pages * 8,
4014                                                 SOCKET_ID_ANY,
4015                                                 RTE_MEMZONE_2MB |
4016                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4017                                                 RTE_MEMZONE_IOVA_CONTIG,
4018                                                 BNXT_PAGE_SIZE);
4019                         if (mz == NULL)
4020                                 return -ENOMEM;
4021                 }
4022
4023                 memset(mz->addr, 0, mz->len);
4024                 mz_phys_addr = mz->iova;
4025                 if ((unsigned long)mz->addr == mz_phys_addr) {
4026                         PMD_DRV_LOG(DEBUG,
4027                                     "physical address same as virtual\n");
4028                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4029                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4030                         if (mz_phys_addr == RTE_BAD_IOVA) {
4031                                 PMD_DRV_LOG(ERR,
4032                                         "unable to map addr to phys memory\n");
4033                                 return -ENOMEM;
4034                         }
4035                 }
4036                 rte_mem_lock_page(((char *)mz->addr));
4037
4038                 rmem->pg_tbl = mz->addr;
4039                 rmem->pg_tbl_map = mz_phys_addr;
4040                 rmem->pg_tbl_mz = mz;
4041         }
4042
4043         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4044                  suffix, idx, bp->eth_dev->data->port_id);
4045         mz = rte_memzone_lookup(mz_name);
4046         if (!mz) {
4047                 mz = rte_memzone_reserve_aligned(mz_name,
4048                                                  mem_size,
4049                                                  SOCKET_ID_ANY,
4050                                                  RTE_MEMZONE_1GB |
4051                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4052                                                  RTE_MEMZONE_IOVA_CONTIG,
4053                                                  BNXT_PAGE_SIZE);
4054                 if (mz == NULL)
4055                         return -ENOMEM;
4056         }
4057
4058         memset(mz->addr, 0, mz->len);
4059         mz_phys_addr = mz->iova;
4060         if ((unsigned long)mz->addr == mz_phys_addr) {
4061                 PMD_DRV_LOG(DEBUG,
4062                             "Memzone physical address same as virtual.\n");
4063                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4064                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4065                         rte_mem_lock_page(((char *)mz->addr) + sz);
4066                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4067                 if (mz_phys_addr == RTE_BAD_IOVA) {
4068                         PMD_DRV_LOG(ERR,
4069                                     "unable to map addr to phys memory\n");
4070                         return -ENOMEM;
4071                 }
4072         }
4073
4074         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4075                 rte_mem_lock_page(((char *)mz->addr) + sz);
4076                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4077                 rmem->dma_arr[i] = mz_phys_addr + sz;
4078
4079                 if (rmem->nr_pages > 1) {
4080                         if (i == rmem->nr_pages - 2 &&
4081                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4082                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4083                         else if (i == rmem->nr_pages - 1 &&
4084                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4085                                 valid_bits |= PTU_PTE_LAST;
4086
4087                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4088                                                            valid_bits);
4089                 }
4090         }
4091
4092         rmem->mz = mz;
4093         if (rmem->vmem_size)
4094                 rmem->vmem = (void **)mz->addr;
4095         rmem->dma_arr[0] = mz_phys_addr;
4096         return 0;
4097 }
4098
4099 static void bnxt_free_ctx_mem(struct bnxt *bp)
4100 {
4101         int i;
4102
4103         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4104                 return;
4105
4106         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4107         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4108         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4109         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4110         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4111         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4112         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4113         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4114         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4115         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4116         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4117
4118         for (i = 0; i < BNXT_MAX_Q; i++) {
4119                 if (bp->ctx->tqm_mem[i])
4120                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4121         }
4122
4123         rte_free(bp->ctx);
4124         bp->ctx = NULL;
4125 }
4126
4127 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4128
4129 #define min_t(type, x, y) ({                    \
4130         type __min1 = (x);                      \
4131         type __min2 = (y);                      \
4132         __min1 < __min2 ? __min1 : __min2; })
4133
4134 #define max_t(type, x, y) ({                    \
4135         type __max1 = (x);                      \
4136         type __max2 = (y);                      \
4137         __max1 > __max2 ? __max1 : __max2; })
4138
4139 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4140
4141 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4142 {
4143         struct bnxt_ctx_pg_info *ctx_pg;
4144         struct bnxt_ctx_mem_info *ctx;
4145         uint32_t mem_size, ena, entries;
4146         int i, rc;
4147
4148         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4149         if (rc) {
4150                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4151                 return rc;
4152         }
4153         ctx = bp->ctx;
4154         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4155                 return 0;
4156
4157         ctx_pg = &ctx->qp_mem;
4158         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4159         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4160         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4161         if (rc)
4162                 return rc;
4163
4164         ctx_pg = &ctx->srq_mem;
4165         ctx_pg->entries = ctx->srq_max_l2_entries;
4166         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4167         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4168         if (rc)
4169                 return rc;
4170
4171         ctx_pg = &ctx->cq_mem;
4172         ctx_pg->entries = ctx->cq_max_l2_entries;
4173         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4174         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4175         if (rc)
4176                 return rc;
4177
4178         ctx_pg = &ctx->vnic_mem;
4179         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4180                 ctx->vnic_max_ring_table_entries;
4181         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4182         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4183         if (rc)
4184                 return rc;
4185
4186         ctx_pg = &ctx->stat_mem;
4187         ctx_pg->entries = ctx->stat_max_entries;
4188         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4189         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4190         if (rc)
4191                 return rc;
4192
4193         entries = ctx->qp_max_l2_entries;
4194         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4195         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4196                           ctx->tqm_max_entries_per_ring);
4197         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4198                 ctx_pg = ctx->tqm_mem[i];
4199                 /* use min tqm entries for now. */
4200                 ctx_pg->entries = entries;
4201                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4202                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4203                 if (rc)
4204                         return rc;
4205                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4206         }
4207
4208         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4209         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4210         if (rc)
4211                 PMD_DRV_LOG(ERR,
4212                             "Failed to configure context mem: rc = %d\n", rc);
4213         else
4214                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4215
4216         return rc;
4217 }
4218
4219 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4220 {
4221         struct rte_pci_device *pci_dev = bp->pdev;
4222         char mz_name[RTE_MEMZONE_NAMESIZE];
4223         const struct rte_memzone *mz = NULL;
4224         uint32_t total_alloc_len;
4225         rte_iova_t mz_phys_addr;
4226
4227         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4228                 return 0;
4229
4230         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4231                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4232                  pci_dev->addr.bus, pci_dev->addr.devid,
4233                  pci_dev->addr.function, "rx_port_stats");
4234         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4235         mz = rte_memzone_lookup(mz_name);
4236         total_alloc_len =
4237                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4238                                        sizeof(struct rx_port_stats_ext) + 512);
4239         if (!mz) {
4240                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4241                                          SOCKET_ID_ANY,
4242                                          RTE_MEMZONE_2MB |
4243                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4244                                          RTE_MEMZONE_IOVA_CONTIG);
4245                 if (mz == NULL)
4246                         return -ENOMEM;
4247         }
4248         memset(mz->addr, 0, mz->len);
4249         mz_phys_addr = mz->iova;
4250         if ((unsigned long)mz->addr == mz_phys_addr) {
4251                 PMD_DRV_LOG(DEBUG,
4252                             "Memzone physical address same as virtual.\n");
4253                 PMD_DRV_LOG(DEBUG,
4254                             "Using rte_mem_virt2iova()\n");
4255                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4256                 if (mz_phys_addr == RTE_BAD_IOVA) {
4257                         PMD_DRV_LOG(ERR,
4258                                     "Can't map address to physical memory\n");
4259                         return -ENOMEM;
4260                 }
4261         }
4262
4263         bp->rx_mem_zone = (const void *)mz;
4264         bp->hw_rx_port_stats = mz->addr;
4265         bp->hw_rx_port_stats_map = mz_phys_addr;
4266
4267         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4268                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4269                  pci_dev->addr.bus, pci_dev->addr.devid,
4270                  pci_dev->addr.function, "tx_port_stats");
4271         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4272         mz = rte_memzone_lookup(mz_name);
4273         total_alloc_len =
4274                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4275                                        sizeof(struct tx_port_stats_ext) + 512);
4276         if (!mz) {
4277                 mz = rte_memzone_reserve(mz_name,
4278                                          total_alloc_len,
4279                                          SOCKET_ID_ANY,
4280                                          RTE_MEMZONE_2MB |
4281                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4282                                          RTE_MEMZONE_IOVA_CONTIG);
4283                 if (mz == NULL)
4284                         return -ENOMEM;
4285         }
4286         memset(mz->addr, 0, mz->len);
4287         mz_phys_addr = mz->iova;
4288         if ((unsigned long)mz->addr == mz_phys_addr) {
4289                 PMD_DRV_LOG(DEBUG,
4290                             "Memzone physical address same as virtual\n");
4291                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4292                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4293                 if (mz_phys_addr == RTE_BAD_IOVA) {
4294                         PMD_DRV_LOG(ERR,
4295                                     "Can't map address to physical memory\n");
4296                         return -ENOMEM;
4297                 }
4298         }
4299
4300         bp->tx_mem_zone = (const void *)mz;
4301         bp->hw_tx_port_stats = mz->addr;
4302         bp->hw_tx_port_stats_map = mz_phys_addr;
4303         bp->flags |= BNXT_FLAG_PORT_STATS;
4304
4305         /* Display extended statistics if FW supports it */
4306         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4307             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4308             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4309                 return 0;
4310
4311         bp->hw_rx_port_stats_ext = (void *)
4312                 ((uint8_t *)bp->hw_rx_port_stats +
4313                  sizeof(struct rx_port_stats));
4314         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4315                 sizeof(struct rx_port_stats);
4316         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4317
4318         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4319             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4320                 bp->hw_tx_port_stats_ext = (void *)
4321                         ((uint8_t *)bp->hw_tx_port_stats +
4322                          sizeof(struct tx_port_stats));
4323                 bp->hw_tx_port_stats_ext_map =
4324                         bp->hw_tx_port_stats_map +
4325                         sizeof(struct tx_port_stats);
4326                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4327         }
4328
4329         return 0;
4330 }
4331
4332 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4333 {
4334         struct bnxt *bp = eth_dev->data->dev_private;
4335         int rc = 0;
4336
4337         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4338                                                RTE_ETHER_ADDR_LEN *
4339                                                bp->max_l2_ctx,
4340                                                0);
4341         if (eth_dev->data->mac_addrs == NULL) {
4342                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4343                 return -ENOMEM;
4344         }
4345
4346         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4347                 if (BNXT_PF(bp))
4348                         return -EINVAL;
4349
4350                 /* Generate a random MAC address, if none was assigned by PF */
4351                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4352                 bnxt_eth_hw_addr_random(bp->mac_addr);
4353                 PMD_DRV_LOG(INFO,
4354                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4355                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4356                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4357
4358                 rc = bnxt_hwrm_set_mac(bp);
4359                 if (!rc)
4360                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4361                                RTE_ETHER_ADDR_LEN);
4362                 return rc;
4363         }
4364
4365         /* Copy the permanent MAC from the FUNC_QCAPS response */
4366         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4367         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4368
4369         return rc;
4370 }
4371
4372 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4373 {
4374         int rc = 0;
4375
4376         /* MAC is already configured in FW */
4377         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4378                 return 0;
4379
4380         /* Restore the old MAC configured */
4381         rc = bnxt_hwrm_set_mac(bp);
4382         if (rc)
4383                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4384
4385         return rc;
4386 }
4387
4388 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4389 {
4390         if (!BNXT_PF(bp))
4391                 return;
4392
4393 #define ALLOW_FUNC(x)   \
4394         { \
4395                 uint32_t arg = (x); \
4396                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4397                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4398         }
4399
4400         /* Forward all requests if firmware is new enough */
4401         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4402              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4403             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4404                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4405         } else {
4406                 PMD_DRV_LOG(WARNING,
4407                             "Firmware too old for VF mailbox functionality\n");
4408                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4409         }
4410
4411         /*
4412          * The following are used for driver cleanup. If we disallow these,
4413          * VF drivers can't clean up cleanly.
4414          */
4415         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4416         ALLOW_FUNC(HWRM_VNIC_FREE);
4417         ALLOW_FUNC(HWRM_RING_FREE);
4418         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4419         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4420         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4421         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4422         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4423         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4424 }
4425
4426 static int bnxt_init_fw(struct bnxt *bp)
4427 {
4428         uint16_t mtu;
4429         int rc = 0;
4430
4431         rc = bnxt_hwrm_ver_get(bp);
4432         if (rc)
4433                 return rc;
4434
4435         rc = bnxt_hwrm_func_reset(bp);
4436         if (rc)
4437                 return -EIO;
4438
4439         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4440         if (rc)
4441                 return rc;
4442
4443         rc = bnxt_hwrm_queue_qportcfg(bp);
4444         if (rc)
4445                 return rc;
4446
4447         /* Get the MAX capabilities for this function */
4448         rc = bnxt_hwrm_func_qcaps(bp);
4449         if (rc)
4450                 return rc;
4451
4452         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4453         if (rc)
4454                 return rc;
4455
4456         /* Get the adapter error recovery support info */
4457         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4458         if (rc)
4459                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4460
4461         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4462             mtu != bp->eth_dev->data->mtu)
4463                 bp->eth_dev->data->mtu = mtu;
4464
4465         bnxt_hwrm_port_led_qcaps(bp);
4466
4467         return 0;
4468 }
4469
4470 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4471 {
4472         int rc;
4473
4474         rc = bnxt_init_fw(bp);
4475         if (rc)
4476                 return rc;
4477
4478         if (!reconfig_dev) {
4479                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4480                 if (rc)
4481                         return rc;
4482         } else {
4483                 rc = bnxt_restore_dflt_mac(bp);
4484                 if (rc)
4485                         return rc;
4486         }
4487
4488         bnxt_config_vf_req_fwd(bp);
4489
4490         rc = bnxt_hwrm_func_driver_register(bp);
4491         if (rc) {
4492                 PMD_DRV_LOG(ERR, "Failed to register driver");
4493                 return -EBUSY;
4494         }
4495
4496         if (BNXT_PF(bp)) {
4497                 if (bp->pdev->max_vfs) {
4498                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4499                         if (rc) {
4500                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4501                                 return rc;
4502                         }
4503                 } else {
4504                         rc = bnxt_hwrm_allocate_pf_only(bp);
4505                         if (rc) {
4506                                 PMD_DRV_LOG(ERR,
4507                                             "Failed to allocate PF resources");
4508                                 return rc;
4509                         }
4510                 }
4511         }
4512
4513         rc = bnxt_alloc_mem(bp, reconfig_dev);
4514         if (rc)
4515                 return rc;
4516
4517         rc = bnxt_setup_int(bp);
4518         if (rc)
4519                 return rc;
4520
4521         bnxt_init_nic(bp);
4522
4523         rc = bnxt_request_int(bp);
4524         if (rc)
4525                 return rc;
4526
4527         return 0;
4528 }
4529
4530 static int
4531 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4532 {
4533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4534         static int version_printed;
4535         struct bnxt *bp;
4536         int rc;
4537
4538         if (version_printed++ == 0)
4539                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4540
4541         eth_dev->dev_ops = &bnxt_dev_ops;
4542         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4543         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4544
4545         /*
4546          * For secondary processes, we don't initialise any further
4547          * as primary has already done this work.
4548          */
4549         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4550                 return 0;
4551
4552         rte_eth_copy_pci_info(eth_dev, pci_dev);
4553
4554         bp = eth_dev->data->dev_private;
4555
4556         bp->dev_stopped = 1;
4557
4558         if (bnxt_vf_pciid(pci_dev->id.device_id))
4559                 bp->flags |= BNXT_FLAG_VF;
4560
4561         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4562             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4563             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4564             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4565             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4566                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4567
4568         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4569             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4570             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4571             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4572                 bp->flags |= BNXT_FLAG_STINGRAY;
4573
4574         rc = bnxt_init_board(eth_dev);
4575         if (rc) {
4576                 PMD_DRV_LOG(ERR,
4577                             "Failed to initialize board rc: %x\n", rc);
4578                 return rc;
4579         }
4580
4581         rc = bnxt_alloc_hwrm_resources(bp);
4582         if (rc) {
4583                 PMD_DRV_LOG(ERR,
4584                             "Failed to allocate hwrm resource rc: %x\n", rc);
4585                 goto error_free;
4586         }
4587         rc = bnxt_init_resources(bp, false);
4588         if (rc)
4589                 goto error_free;
4590
4591         rc = bnxt_alloc_stats_mem(bp);
4592         if (rc)
4593                 goto error_free;
4594
4595         PMD_DRV_LOG(INFO,
4596                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4597                     pci_dev->mem_resource[0].phys_addr,
4598                     pci_dev->mem_resource[0].addr);
4599
4600         return 0;
4601
4602 error_free:
4603         bnxt_dev_uninit(eth_dev);
4604         return rc;
4605 }
4606
4607 static int
4608 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4609 {
4610         int rc;
4611
4612         bnxt_free_int(bp);
4613         bnxt_free_mem(bp, reconfig_dev);
4614         bnxt_hwrm_func_buf_unrgtr(bp);
4615         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4616         bp->flags &= ~BNXT_FLAG_REGISTERED;
4617         bnxt_free_ctx_mem(bp);
4618         if (!reconfig_dev) {
4619                 bnxt_free_hwrm_resources(bp);
4620
4621                 if (bp->recovery_info != NULL) {
4622                         rte_free(bp->recovery_info);
4623                         bp->recovery_info = NULL;
4624                 }
4625         }
4626
4627         rte_free(bp->ptp_cfg);
4628         bp->ptp_cfg = NULL;
4629         return rc;
4630 }
4631
4632 static int
4633 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4634 {
4635         struct bnxt *bp = eth_dev->data->dev_private;
4636         int rc;
4637
4638         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4639                 return -EPERM;
4640
4641         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4642
4643         rc = bnxt_uninit_resources(bp, false);
4644
4645         if (bp->grp_info != NULL) {
4646                 rte_free(bp->grp_info);
4647                 bp->grp_info = NULL;
4648         }
4649
4650         if (bp->tx_mem_zone) {
4651                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4652                 bp->tx_mem_zone = NULL;
4653         }
4654
4655         if (bp->rx_mem_zone) {
4656                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4657                 bp->rx_mem_zone = NULL;
4658         }
4659
4660         if (bp->dev_stopped == 0)
4661                 bnxt_dev_close_op(eth_dev);
4662         if (bp->pf.vf_info)
4663                 rte_free(bp->pf.vf_info);
4664         eth_dev->dev_ops = NULL;
4665         eth_dev->rx_pkt_burst = NULL;
4666         eth_dev->tx_pkt_burst = NULL;
4667
4668         return rc;
4669 }
4670
4671 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4672         struct rte_pci_device *pci_dev)
4673 {
4674         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4675                 bnxt_dev_init);
4676 }
4677
4678 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4679 {
4680         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4681                 return rte_eth_dev_pci_generic_remove(pci_dev,
4682                                 bnxt_dev_uninit);
4683         else
4684                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4685 }
4686
4687 static struct rte_pci_driver bnxt_rte_pmd = {
4688         .id_table = bnxt_pci_id_map,
4689         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4690         .probe = bnxt_pci_probe,
4691         .remove = bnxt_pci_remove,
4692 };
4693
4694 static bool
4695 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4696 {
4697         if (strcmp(dev->device->driver->name, drv->driver.name))
4698                 return false;
4699
4700         return true;
4701 }
4702
4703 bool is_bnxt_supported(struct rte_eth_dev *dev)
4704 {
4705         return is_device_supported(dev, &bnxt_rte_pmd);
4706 }
4707
4708 RTE_INIT(bnxt_init_log)
4709 {
4710         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4711         if (bnxt_logtype_driver >= 0)
4712                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4713 }
4714
4715 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4716 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4717 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");