drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 static const char *const bnxt_dev_args[] = {
 133         BNXT_DEVARG_TRUFLOW,
 134         BNXT_DEVARG_FLOW_XSTAT,
 135         NULL
 136 };
 137
 138 /*
 139  * truflow == false to disable the feature
 140  * truflow == true to enable the feature
 141  */
 142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 143
 144 /*
 145  * flow_xstat == false to disable the feature
 146  * flow_xstat == true to enable the feature
 147  */
 148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 149
 150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 157 static void bnxt_dev_recover(void *arg);
 158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 159
 160 int is_bnxt_in_error(struct bnxt *bp)
 161 {
 162         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 163                 return -EIO;
 164         if (bp->flags & BNXT_FLAG_FW_RESET)
 165                 return -EBUSY;
 166
 167         return 0;
 168 }
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 201          * If the number of rings change across fw update,
 202          * we don't have much choice except to warn the user.
 203          */
 204         if (!reconfig) {
 205                 bnxt_free_stats(bp);
 206                 bnxt_free_tx_rings(bp);
 207                 bnxt_free_rx_rings(bp);
 208         }
 209         bnxt_free_async_cp_ring(bp);
 210         bnxt_free_rxtx_nq_ring(bp);
 211
 212         rte_free(bp->grp_info);
 213         bp->grp_info = NULL;
 214 }
 215
 216 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         int rc;
 219
 220         rc = bnxt_alloc_ring_grps(bp);
 221         if (rc)
 222                 goto alloc_mem_err;
 223
 224         rc = bnxt_alloc_async_ring_struct(bp);
 225         if (rc)
 226                 goto alloc_mem_err;
 227
 228         rc = bnxt_alloc_vnic_mem(bp);
 229         if (rc)
 230                 goto alloc_mem_err;
 231
 232         rc = bnxt_alloc_vnic_attributes(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_filter_mem(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_async_cp_ring(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_rxtx_nq_ring(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         return 0;
 249
 250 alloc_mem_err:
 251         bnxt_free_mem(bp, reconfig);
 252         return rc;
 253 }
 254
 255 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 256 {
 257         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 258         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 259         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 260         struct bnxt_rx_queue *rxq;
 261         unsigned int j;
 262         int rc;
 263
 264         rc = bnxt_vnic_grp_alloc(bp, vnic);
 265         if (rc)
 266                 goto err_out;
 267
 268         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 269                     vnic_id, vnic, vnic->fw_grp_ids);
 270
 271         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 272         if (rc)
 273                 goto err_out;
 274
 275         /* Alloc RSS context only if RSS mode is enabled */
 276         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 277                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 278
 279                 rc = 0;
 280                 for (j = 0; j < nr_ctxs; j++) {
 281                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 282                         if (rc)
 283                                 break;
 284                 }
 285                 if (rc) {
 286                         PMD_DRV_LOG(ERR,
 287                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 288                                     vnic_id, j, rc);
 289                         goto err_out;
 290                 }
 291                 vnic->num_lb_ctxts = nr_ctxs;
 292         }
 293
 294         /*
 295          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 296          * setting is not available at this time, it will not be
 297          * configured correctly in the CFA.
 298          */
 299         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 300                 vnic->vlan_strip = true;
 301         else
 302                 vnic->vlan_strip = false;
 303
 304         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 305         if (rc)
 306                 goto err_out;
 307
 308         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 309         if (rc)
 310                 goto err_out;
 311
 312         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 313                 rxq = bp->eth_dev->data->rx_queues[j];
 314
 315                 PMD_DRV_LOG(DEBUG,
 316                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 317                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 318
 319                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 320                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 321                 else
 322                         vnic->rx_queue_cnt++;
 323         }
 324
 325         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 326
 327         rc = bnxt_vnic_rss_configure(bp, vnic);
 328         if (rc)
 329                 goto err_out;
 330
 331         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 332
 333         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 334                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 335         else
 336                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 337
 338         return 0;
 339 err_out:
 340         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 341                     vnic_id, rc);
 342         return rc;
 343 }
 344
 345 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 346 {
 347         int rc = 0;
 348
 349         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
 350                                 &bp->rx_fc_in_tbl.ctx_id);
 351         if (rc)
 352                 return rc;
 353
 354         PMD_DRV_LOG(DEBUG,
 355                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 356                     " rx_fc_in_tbl.ctx_id = %d\n",
 357                     bp->rx_fc_in_tbl.va,
 358                     (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
 359                     bp->rx_fc_in_tbl.ctx_id);
 360
 361         rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
 362                                 &bp->rx_fc_out_tbl.ctx_id);
 363         if (rc)
 364                 return rc;
 365
 366         PMD_DRV_LOG(DEBUG,
 367                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 368                     " rx_fc_out_tbl.ctx_id = %d\n",
 369                     bp->rx_fc_out_tbl.va,
 370                     (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
 371                     bp->rx_fc_out_tbl.ctx_id);
 372
 373         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
 374                                 &bp->tx_fc_in_tbl.ctx_id);
 375         if (rc)
 376                 return rc;
 377
 378         PMD_DRV_LOG(DEBUG,
 379                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 380                     " tx_fc_in_tbl.ctx_id = %d\n",
 381                     bp->tx_fc_in_tbl.va,
 382                     (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
 383                     bp->tx_fc_in_tbl.ctx_id);
 384
 385         rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
 386                                 &bp->tx_fc_out_tbl.ctx_id);
 387         if (rc)
 388                 return rc;
 389
 390         PMD_DRV_LOG(DEBUG,
 391                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 392                     " tx_fc_out_tbl.ctx_id = %d\n",
 393                     bp->tx_fc_out_tbl.va,
 394                     (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
 395                     bp->tx_fc_out_tbl.ctx_id);
 396
 397         memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
 398         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 399                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 400                                        bp->rx_fc_out_tbl.ctx_id,
 401                                        bp->max_fc,
 402                                        true);
 403         if (rc)
 404                 return rc;
 405
 406         memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
 407         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 408                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 409                                        bp->tx_fc_out_tbl.ctx_id,
 410                                        bp->max_fc,
 411                                        true);
 412
 413         return rc;
 414 }
 415
 416 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 417                                   struct bnxt_ctx_mem_buf_info *ctx)
 418 {
 419         if (!ctx)
 420                 return -EINVAL;
 421
 422         ctx->va = rte_zmalloc(type, size, 0);
 423         if (ctx->va == NULL)
 424                 return -ENOMEM;
 425         rte_mem_lock_page(ctx->va);
 426         ctx->size = size;
 427         ctx->dma = rte_mem_virt2iova(ctx->va);
 428         if (ctx->dma == RTE_BAD_IOVA)
 429                 return -ENOMEM;
 430
 431         return 0;
 432 }
 433
 434 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 435 {
 436         struct rte_pci_device *pdev = bp->pdev;
 437         char type[RTE_MEMZONE_NAMESIZE];
 438         uint16_t max_fc;
 439         int rc = 0;
 440
 441         max_fc = bp->max_fc;
 442
 443         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 444                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 445         /* 4 bytes for each counter-id */
 446         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
 447         if (rc)
 448                 return rc;
 449
 450         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 451                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 452         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 453         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
 454         if (rc)
 455                 return rc;
 456
 457         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 458                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 459         /* 4 bytes for each counter-id */
 460         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
 461         if (rc)
 462                 return rc;
 463
 464         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 465                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 466         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 467         rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
 468         if (rc)
 469                 return rc;
 470
 471         rc = bnxt_register_fc_ctx_mem(bp);
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_init_ctx_mem(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479
 480         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 481             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
 482                 return 0;
 483
 484         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
 485         if (rc)
 486                 return rc;
 487
 488         rc = bnxt_init_fc_ctx_mem(bp);
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_init_chip(struct bnxt *bp)
 494 {
 495         struct rte_eth_link new;
 496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 497         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 498         uint32_t intr_vector = 0;
 499         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 500         uint32_t vec = BNXT_MISC_VEC_ID;
 501         unsigned int i, j;
 502         int rc;
 503
 504         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 505                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 506                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 507                 bp->flags |= BNXT_FLAG_JUMBO;
 508         } else {
 509                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 510                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 511                 bp->flags &= ~BNXT_FLAG_JUMBO;
 512         }
 513
 514         /* THOR does not support ring groups.
 515          * But we will use the array to save RSS context IDs.
 516          */
 517         if (BNXT_CHIP_THOR(bp))
 518                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 519
 520         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 521         if (rc) {
 522                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 523                 goto err_out;
 524         }
 525
 526         rc = bnxt_alloc_hwrm_rings(bp);
 527         if (rc) {
 528                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 529                 goto err_out;
 530         }
 531
 532         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 533         if (rc) {
 534                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 535                 goto err_out;
 536         }
 537
 538         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 539                 goto skip_cosq_cfg;
 540
 541         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 542                 if (bp->rx_cos_queue[i].id != 0xff) {
 543                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 544
 545                         if (!vnic) {
 546                                 PMD_DRV_LOG(ERR,
 547                                             "Num pools more than FW profile\n");
 548                                 rc = -EINVAL;
 549                                 goto err_out;
 550                         }
 551                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 552                         bp->rx_cosq_cnt++;
 553                 }
 554         }
 555
 556 skip_cosq_cfg:
 557         rc = bnxt_mq_rx_configure(bp);
 558         if (rc) {
 559                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 560                 goto err_out;
 561         }
 562
 563         /* VNIC configuration */
 564         for (i = 0; i < bp->nr_vnics; i++) {
 565                 rc = bnxt_setup_one_vnic(bp, i);
 566                 if (rc)
 567                         goto err_out;
 568         }
 569
 570         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 571         if (rc) {
 572                 PMD_DRV_LOG(ERR,
 573                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 574                 goto err_out;
 575         }
 576
 577         /* check and configure queue intr-vector mapping */
 578         if ((rte_intr_cap_multiple(intr_handle) ||
 579              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 580             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 581                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 582                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 583                 if (intr_vector > bp->rx_cp_nr_rings) {
 584                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 585                                         bp->rx_cp_nr_rings);
 586                         return -ENOTSUP;
 587                 }
 588                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 589                 if (rc)
 590                         return rc;
 591         }
 592
 593         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 594                 intr_handle->intr_vec =
 595                         rte_zmalloc("intr_vec",
 596                                     bp->eth_dev->data->nb_rx_queues *
 597                                     sizeof(int), 0);
 598                 if (intr_handle->intr_vec == NULL) {
 599                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 600                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 601                         rc = -ENOMEM;
 602                         goto err_disable;
 603                 }
 604                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 605                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 606                          intr_handle->intr_vec, intr_handle->nb_efd,
 607                         intr_handle->max_intr);
 608                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 609                      queue_id++) {
 610                         intr_handle->intr_vec[queue_id] =
 611                                                         vec + BNXT_RX_VEC_START;
 612                         if (vec < base + intr_handle->nb_efd - 1)
 613                                 vec++;
 614                 }
 615         }
 616
 617         /* enable uio/vfio intr/eventfd mapping */
 618         rc = rte_intr_enable(intr_handle);
 619 #ifndef RTE_EXEC_ENV_FREEBSD
 620         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 621         if (rc)
 622                 goto err_free;
 623 #endif
 624
 625         rc = bnxt_get_hwrm_link_config(bp, &new);
 626         if (rc) {
 627                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 628                 goto err_free;
 629         }
 630
 631         if (!bp->link_info.link_up) {
 632                 rc = bnxt_set_hwrm_link_config(bp, true);
 633                 if (rc) {
 634                         PMD_DRV_LOG(ERR,
 635                                 "HWRM link config failure rc: %x\n", rc);
 636                         goto err_free;
 637                 }
 638         }
 639         bnxt_print_link_info(bp->eth_dev);
 640
 641         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 642         if (!bp->mark_table)
 643                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 644
 645         return 0;
 646
 647 err_free:
 648         rte_free(intr_handle->intr_vec);
 649 err_disable:
 650         rte_intr_efd_disable(intr_handle);
 651 err_out:
 652         /* Some of the error status returned by FW may not be from errno.h */
 653         if (rc > 0)
 654                 rc = -EIO;
 655
 656         return rc;
 657 }
 658
 659 static int bnxt_shutdown_nic(struct bnxt *bp)
 660 {
 661         bnxt_free_all_hwrm_resources(bp);
 662         bnxt_free_all_filters(bp);
 663         bnxt_free_all_vnics(bp);
 664         return 0;
 665 }
 666
 667 /*
 668  * Device configuration and status function
 669  */
 670
 671 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 672 {
 673         uint32_t link_speed = bp->link_info.support_speeds;
 674         uint32_t speed_capa = 0;
 675
 676         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 677                 speed_capa |= ETH_LINK_SPEED_100M;
 678         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 679                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 680         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 681                 speed_capa |= ETH_LINK_SPEED_1G;
 682         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 683                 speed_capa |= ETH_LINK_SPEED_2_5G;
 684         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 685                 speed_capa |= ETH_LINK_SPEED_10G;
 686         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 687                 speed_capa |= ETH_LINK_SPEED_20G;
 688         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 689                 speed_capa |= ETH_LINK_SPEED_25G;
 690         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 691                 speed_capa |= ETH_LINK_SPEED_40G;
 692         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 693                 speed_capa |= ETH_LINK_SPEED_50G;
 694         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 695                 speed_capa |= ETH_LINK_SPEED_100G;
 696         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 697                 speed_capa |= ETH_LINK_SPEED_200G;
 698
 699         if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 700                 speed_capa |= ETH_LINK_SPEED_FIXED;
 701         else
 702                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 703
 704         return speed_capa;
 705 }
 706
 707 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 708                                 struct rte_eth_dev_info *dev_info)
 709 {
 710         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 711         struct bnxt *bp = eth_dev->data->dev_private;
 712         uint16_t max_vnics, i, j, vpool, vrxq;
 713         unsigned int max_rx_rings;
 714         int rc;
 715
 716         rc = is_bnxt_in_error(bp);
 717         if (rc)
 718                 return rc;
 719
 720         /* MAC Specifics */
 721         dev_info->max_mac_addrs = bp->max_l2_ctx;
 722         dev_info->max_hash_mac_addrs = 0;
 723
 724         /* PF/VF specifics */
 725         if (BNXT_PF(bp))
 726                 dev_info->max_vfs = pdev->max_vfs;
 727
 728         max_rx_rings = BNXT_MAX_RINGS(bp);
 729         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 730         dev_info->max_rx_queues = max_rx_rings;
 731         dev_info->max_tx_queues = max_rx_rings;
 732         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 733         dev_info->hash_key_size = 40;
 734         max_vnics = bp->max_vnics;
 735
 736         /* MTU specifics */
 737         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 738         dev_info->max_mtu = BNXT_MAX_MTU;
 739
 740         /* Fast path specifics */
 741         dev_info->min_rx_bufsize = 1;
 742         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 743
 744         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 745         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 746                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 747         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 748         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 749
 750         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 751
 752         /* *INDENT-OFF* */
 753         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 754                 .rx_thresh = {
 755                         .pthresh = 8,
 756                         .hthresh = 8,
 757                         .wthresh = 0,
 758                 },
 759                 .rx_free_thresh = 32,
 760                 /* If no descriptors available, pkts are dropped by default */
 761                 .rx_drop_en = 1,
 762         };
 763
 764         dev_info->default_txconf = (struct rte_eth_txconf) {
 765                 .tx_thresh = {
 766                         .pthresh = 32,
 767                         .hthresh = 0,
 768                         .wthresh = 0,
 769                 },
 770                 .tx_free_thresh = 32,
 771                 .tx_rs_thresh = 32,
 772         };
 773         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 774
 775         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 776         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 777         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 778         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 779         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 780
 781         /* *INDENT-ON* */
 782
 783         /*
 784          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 785          *       need further investigation.
 786          */
 787
 788         /* VMDq resources */
 789         vpool = 64; /* ETH_64_POOLS */
 790         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 791         for (i = 0; i < 4; vpool >>= 1, i++) {
 792                 if (max_vnics > vpool) {
 793                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 794                                 if (dev_info->max_rx_queues > vrxq) {
 795                                         if (vpool > vrxq)
 796                                                 vpool = vrxq;
 797                                         goto found;
 798                                 }
 799                         }
 800                         /* Not enough resources to support VMDq */
 801                         break;
 802                 }
 803         }
 804         /* Not enough resources to support VMDq */
 805         vpool = 0;
 806         vrxq = 0;
 807 found:
 808         dev_info->max_vmdq_pools = vpool;
 809         dev_info->vmdq_queue_num = vrxq;
 810
 811         dev_info->vmdq_pool_base = 0;
 812         dev_info->vmdq_queue_base = 0;
 813
 814         return 0;
 815 }
 816
 817 /* Configure the device based on the configuration provided */
 818 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 819 {
 820         struct bnxt *bp = eth_dev->data->dev_private;
 821         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 822         int rc;
 823
 824         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 825         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 826         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 827         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 828
 829         rc = is_bnxt_in_error(bp);
 830         if (rc)
 831                 return rc;
 832
 833         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 834                 rc = bnxt_hwrm_check_vf_rings(bp);
 835                 if (rc) {
 836                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 837                         return -ENOSPC;
 838                 }
 839
 840                 /* If a resource has already been allocated - in this case
 841                  * it is the async completion ring, free it. Reallocate it after
 842                  * resource reservation. This will ensure the resource counts
 843                  * are calculated correctly.
 844                  */
 845
 846                 pthread_mutex_lock(&bp->def_cp_lock);
 847
 848                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 849                         bnxt_disable_int(bp);
 850                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 851                 }
 852
 853                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 854                 if (rc) {
 855                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 856                         pthread_mutex_unlock(&bp->def_cp_lock);
 857                         return -ENOSPC;
 858                 }
 859
 860                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 861                         rc = bnxt_alloc_async_cp_ring(bp);
 862                         if (rc) {
 863                                 pthread_mutex_unlock(&bp->def_cp_lock);
 864                                 return rc;
 865                         }
 866                         bnxt_enable_int(bp);
 867                 }
 868
 869                 pthread_mutex_unlock(&bp->def_cp_lock);
 870         } else {
 871                 /* legacy driver needs to get updated values */
 872                 rc = bnxt_hwrm_func_qcaps(bp);
 873                 if (rc) {
 874                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 875                         return rc;
 876                 }
 877         }
 878
 879         /* Inherit new configurations */
 880         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 881             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 882             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 883                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 884             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 885             bp->max_stat_ctx)
 886                 goto resource_error;
 887
 888         if (BNXT_HAS_RING_GRPS(bp) &&
 889             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 890                 goto resource_error;
 891
 892         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 893             bp->max_vnics < eth_dev->data->nb_rx_queues)
 894                 goto resource_error;
 895
 896         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 897         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 898
 899         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 900                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 901         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 902
 903         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 904                 eth_dev->data->mtu =
 905                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 906                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 907                         BNXT_NUM_VLANS;
 908                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 909         }
 910         return 0;
 911
 912 resource_error:
 913         PMD_DRV_LOG(ERR,
 914                     "Insufficient resources to support requested config\n");
 915         PMD_DRV_LOG(ERR,
 916                     "Num Queues Requested: Tx %d, Rx %d\n",
 917                     eth_dev->data->nb_tx_queues,
 918                     eth_dev->data->nb_rx_queues);
 919         PMD_DRV_LOG(ERR,
 920                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 921                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 922                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 923         return -ENOSPC;
 924 }
 925
 926 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 927 {
 928         struct rte_eth_link *link = &eth_dev->data->dev_link;
 929
 930         if (link->link_status)
 931                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 932                         eth_dev->data->port_id,
 933                         (uint32_t)link->link_speed,
 934                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 935                         ("full-duplex") : ("half-duplex\n"));
 936         else
 937                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 938                         eth_dev->data->port_id);
 939 }
 940
 941 /*
 942  * Determine whether the current configuration requires support for scattered
 943  * receive; return 1 if scattered receive is required and 0 if not.
 944  */
 945 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 946 {
 947         uint16_t buf_size;
 948         int i;
 949
 950         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 951                 return 1;
 952
 953         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 954                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 955
 956                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 957                                       RTE_PKTMBUF_HEADROOM);
 958                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 959                         return 1;
 960         }
 961         return 0;
 962 }
 963
 964 static eth_rx_burst_t
 965 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 966 {
 967         struct bnxt *bp = eth_dev->data->dev_private;
 968
 969 #ifdef RTE_ARCH_X86
 970 #ifndef RTE_LIBRTE_IEEE1588
 971         /*
 972          * Vector mode receive can be enabled only if scatter rx is not
 973          * in use and rx offloads are limited to VLAN stripping and
 974          * CRC stripping.
 975          */
 976         if (!eth_dev->data->scattered_rx &&
 977             !(eth_dev->data->dev_conf.rxmode.offloads &
 978               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 979                 DEV_RX_OFFLOAD_KEEP_CRC |
 980                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 981                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 982                 DEV_RX_OFFLOAD_UDP_CKSUM |
 983                 DEV_RX_OFFLOAD_TCP_CKSUM |
 984                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 985                 DEV_RX_OFFLOAD_RSS_HASH |
 986                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
 987             !bp->truflow) {
 988                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 989                             eth_dev->data->port_id);
 990                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 991                 return bnxt_recv_pkts_vec;
 992         }
 993         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 994                     eth_dev->data->port_id);
 995         PMD_DRV_LOG(INFO,
 996                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 997                     eth_dev->data->port_id,
 998                     eth_dev->data->scattered_rx,
 999                     eth_dev->data->dev_conf.rxmode.offloads);
1000 #endif
1001 #endif
1002         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1003         return bnxt_recv_pkts;
1004 }
1005
1006 static eth_tx_burst_t
1007 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1008 {
1009 #ifdef RTE_ARCH_X86
1010 #ifndef RTE_LIBRTE_IEEE1588
1011         /*
1012          * Vector mode transmit can be enabled only if not using scatter rx
1013          * or tx offloads.
1014          */
1015         if (!eth_dev->data->scattered_rx &&
1016             !eth_dev->data->dev_conf.txmode.offloads) {
1017                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1018                             eth_dev->data->port_id);
1019                 return bnxt_xmit_pkts_vec;
1020         }
1021         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1022                     eth_dev->data->port_id);
1023         PMD_DRV_LOG(INFO,
1024                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1025                     eth_dev->data->port_id,
1026                     eth_dev->data->scattered_rx,
1027                     eth_dev->data->dev_conf.txmode.offloads);
1028 #endif
1029 #endif
1030         return bnxt_xmit_pkts;
1031 }
1032
1033 static int bnxt_handle_if_change_status(struct bnxt *bp)
1034 {
1035         int rc;
1036
1037         /* Since fw has undergone a reset and lost all contexts,
1038          * set fatal flag to not issue hwrm during cleanup
1039          */
1040         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1041         bnxt_uninit_resources(bp, true);
1042
1043         /* clear fatal flag so that re-init happens */
1044         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1045         rc = bnxt_init_resources(bp, true);
1046
1047         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1048
1049         return rc;
1050 }
1051
1052 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1053 {
1054         struct bnxt *bp = eth_dev->data->dev_private;
1055         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1056         int vlan_mask = 0;
1057         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1058
1059         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1060                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1061                 return -EINVAL;
1062         }
1063
1064         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1065                 PMD_DRV_LOG(ERR,
1066                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1067                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1068         }
1069
1070         do {
1071                 rc = bnxt_hwrm_if_change(bp, true);
1072                 if (rc == 0 || rc != -EAGAIN)
1073                         break;
1074
1075                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1076         } while (retry_cnt--);
1077
1078         if (rc)
1079                 return rc;
1080
1081         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1082                 rc = bnxt_handle_if_change_status(bp);
1083                 if (rc)
1084                         return rc;
1085         }
1086
1087         bnxt_enable_int(bp);
1088
1089         rc = bnxt_init_chip(bp);
1090         if (rc)
1091                 goto error;
1092
1093         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1094         eth_dev->data->dev_started = 1;
1095
1096         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1097
1098         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1099                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1100         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1101                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1102         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1103         if (rc)
1104                 goto error;
1105
1106         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1107         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1108
1109         pthread_mutex_lock(&bp->def_cp_lock);
1110         bnxt_schedule_fw_health_check(bp);
1111         pthread_mutex_unlock(&bp->def_cp_lock);
1112
1113         if (bp->truflow)
1114                 bnxt_ulp_init(bp);
1115
1116         return 0;
1117
1118 error:
1119         bnxt_shutdown_nic(bp);
1120         bnxt_free_tx_mbufs(bp);
1121         bnxt_free_rx_mbufs(bp);
1122         bnxt_hwrm_if_change(bp, false);
1123         eth_dev->data->dev_started = 0;
1124         return rc;
1125 }
1126
1127 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1128 {
1129         struct bnxt *bp = eth_dev->data->dev_private;
1130         int rc = 0;
1131
1132         if (!bp->link_info.link_up)
1133                 rc = bnxt_set_hwrm_link_config(bp, true);
1134         if (!rc)
1135                 eth_dev->data->dev_link.link_status = 1;
1136
1137         bnxt_print_link_info(eth_dev);
1138         return rc;
1139 }
1140
1141 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1142 {
1143         struct bnxt *bp = eth_dev->data->dev_private;
1144
1145         eth_dev->data->dev_link.link_status = 0;
1146         bnxt_set_hwrm_link_config(bp, false);
1147         bp->link_info.link_up = 0;
1148
1149         return 0;
1150 }
1151
1152 /* Unload the driver, release resources */
1153 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1154 {
1155         struct bnxt *bp = eth_dev->data->dev_private;
1156         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1157         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1158
1159         if (bp->truflow)
1160                 bnxt_ulp_deinit(bp);
1161
1162         eth_dev->data->dev_started = 0;
1163         /* Prevent crashes when queues are still in use */
1164         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1165         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1166
1167         bnxt_disable_int(bp);
1168
1169         /* disable uio/vfio intr/eventfd mapping */
1170         rte_intr_disable(intr_handle);
1171
1172         bnxt_cancel_fw_health_check(bp);
1173
1174         bnxt_dev_set_link_down_op(eth_dev);
1175
1176         /* Wait for link to be reset and the async notification to process.
1177          * During reset recovery, there is no need to wait and
1178          * VF/NPAR functions do not have privilege to change PHY config.
1179          */
1180         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1181                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1182
1183         /* Clean queue intr-vector mapping */
1184         rte_intr_efd_disable(intr_handle);
1185         if (intr_handle->intr_vec != NULL) {
1186                 rte_free(intr_handle->intr_vec);
1187                 intr_handle->intr_vec = NULL;
1188         }
1189
1190         bnxt_hwrm_port_clr_stats(bp);
1191         bnxt_free_tx_mbufs(bp);
1192         bnxt_free_rx_mbufs(bp);
1193         /* Process any remaining notifications in default completion queue */
1194         bnxt_int_handler(eth_dev);
1195         bnxt_shutdown_nic(bp);
1196         bnxt_hwrm_if_change(bp, false);
1197
1198         rte_free(bp->mark_table);
1199         bp->mark_table = NULL;
1200
1201         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1202         bp->rx_cosq_cnt = 0;
1203 }
1204
1205 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1206 {
1207         struct bnxt *bp = eth_dev->data->dev_private;
1208
1209         /* cancel the recovery handler before remove dev */
1210         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1211         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1212         bnxt_cancel_fc_thread(bp);
1213
1214         if (eth_dev->data->dev_started)
1215                 bnxt_dev_stop_op(eth_dev);
1216
1217         bnxt_uninit_resources(bp, false);
1218
1219         eth_dev->dev_ops = NULL;
1220         eth_dev->rx_pkt_burst = NULL;
1221         eth_dev->tx_pkt_burst = NULL;
1222
1223         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1224         bp->tx_mem_zone = NULL;
1225         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1226         bp->rx_mem_zone = NULL;
1227
1228         rte_free(bp->pf.vf_info);
1229         bp->pf.vf_info = NULL;
1230
1231         rte_free(bp->grp_info);
1232         bp->grp_info = NULL;
1233 }
1234
1235 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1236                                     uint32_t index)
1237 {
1238         struct bnxt *bp = eth_dev->data->dev_private;
1239         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1240         struct bnxt_vnic_info *vnic;
1241         struct bnxt_filter_info *filter, *temp_filter;
1242         uint32_t i;
1243
1244         if (is_bnxt_in_error(bp))
1245                 return;
1246
1247         /*
1248          * Loop through all VNICs from the specified filter flow pools to
1249          * remove the corresponding MAC addr filter
1250          */
1251         for (i = 0; i < bp->nr_vnics; i++) {
1252                 if (!(pool_mask & (1ULL << i)))
1253                         continue;
1254
1255                 vnic = &bp->vnic_info[i];
1256                 filter = STAILQ_FIRST(&vnic->filter);
1257                 while (filter) {
1258                         temp_filter = STAILQ_NEXT(filter, next);
1259                         if (filter->mac_index == index) {
1260                                 STAILQ_REMOVE(&vnic->filter, filter,
1261                                                 bnxt_filter_info, next);
1262                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1263                                 bnxt_free_filter(bp, filter);
1264                         }
1265                         filter = temp_filter;
1266                 }
1267         }
1268 }
1269
1270 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1271                                struct rte_ether_addr *mac_addr, uint32_t index,
1272                                uint32_t pool)
1273 {
1274         struct bnxt_filter_info *filter;
1275         int rc = 0;
1276
1277         /* Attach requested MAC address to the new l2_filter */
1278         STAILQ_FOREACH(filter, &vnic->filter, next) {
1279                 if (filter->mac_index == index) {
1280                         PMD_DRV_LOG(DEBUG,
1281                                     "MAC addr already existed for pool %d\n",
1282                                     pool);
1283                         return 0;
1284                 }
1285         }
1286
1287         filter = bnxt_alloc_filter(bp);
1288         if (!filter) {
1289                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1290                 return -ENODEV;
1291         }
1292
1293         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1294          * if the MAC that's been programmed now is a different one, then,
1295          * copy that addr to filter->l2_addr
1296          */
1297         if (mac_addr)
1298                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1299         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1300
1301         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1302         if (!rc) {
1303                 filter->mac_index = index;
1304                 if (filter->mac_index == 0)
1305                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1306                 else
1307                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1308         } else {
1309                 bnxt_free_filter(bp, filter);
1310         }
1311
1312         return rc;
1313 }
1314
1315 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1316                                 struct rte_ether_addr *mac_addr,
1317                                 uint32_t index, uint32_t pool)
1318 {
1319         struct bnxt *bp = eth_dev->data->dev_private;
1320         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1321         int rc = 0;
1322
1323         rc = is_bnxt_in_error(bp);
1324         if (rc)
1325                 return rc;
1326
1327         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1328                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1329                 return -ENOTSUP;
1330         }
1331
1332         if (!vnic) {
1333                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1334                 return -EINVAL;
1335         }
1336
1337         /* Filter settings will get applied when port is started */
1338         if (!eth_dev->data->dev_started)
1339                 return 0;
1340
1341         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1342
1343         return rc;
1344 }
1345
1346 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1347                      bool exp_link_status)
1348 {
1349         int rc = 0;
1350         struct bnxt *bp = eth_dev->data->dev_private;
1351         struct rte_eth_link new;
1352         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1353                   BNXT_LINK_DOWN_WAIT_CNT;
1354
1355         rc = is_bnxt_in_error(bp);
1356         if (rc)
1357                 return rc;
1358
1359         memset(&new, 0, sizeof(new));
1360         do {
1361                 /* Retrieve link info from hardware */
1362                 rc = bnxt_get_hwrm_link_config(bp, &new);
1363                 if (rc) {
1364                         new.link_speed = ETH_LINK_SPEED_100M;
1365                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1366                         PMD_DRV_LOG(ERR,
1367                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1368                         goto out;
1369                 }
1370
1371                 if (!wait_to_complete || new.link_status == exp_link_status)
1372                         break;
1373
1374                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1375         } while (cnt--);
1376
1377 out:
1378         /* Timed out or success */
1379         if (new.link_status != eth_dev->data->dev_link.link_status ||
1380         new.link_speed != eth_dev->data->dev_link.link_speed) {
1381                 rte_eth_linkstatus_set(eth_dev, &new);
1382
1383                 _rte_eth_dev_callback_process(eth_dev,
1384                                               RTE_ETH_EVENT_INTR_LSC,
1385                                               NULL);
1386
1387                 bnxt_print_link_info(eth_dev);
1388         }
1389
1390         return rc;
1391 }
1392
1393 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1394                                int wait_to_complete)
1395 {
1396         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1397 }
1398
1399 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1400 {
1401         struct bnxt *bp = eth_dev->data->dev_private;
1402         struct bnxt_vnic_info *vnic;
1403         uint32_t old_flags;
1404         int rc;
1405
1406         rc = is_bnxt_in_error(bp);
1407         if (rc)
1408                 return rc;
1409
1410         /* Filter settings will get applied when port is started */
1411         if (!eth_dev->data->dev_started)
1412                 return 0;
1413
1414         if (bp->vnic_info == NULL)
1415                 return 0;
1416
1417         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1418
1419         old_flags = vnic->flags;
1420         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1421         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1422         if (rc != 0)
1423                 vnic->flags = old_flags;
1424
1425         return rc;
1426 }
1427
1428 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1429 {
1430         struct bnxt *bp = eth_dev->data->dev_private;
1431         struct bnxt_vnic_info *vnic;
1432         uint32_t old_flags;
1433         int rc;
1434
1435         rc = is_bnxt_in_error(bp);
1436         if (rc)
1437                 return rc;
1438
1439         /* Filter settings will get applied when port is started */
1440         if (!eth_dev->data->dev_started)
1441                 return 0;
1442
1443         if (bp->vnic_info == NULL)
1444                 return 0;
1445
1446         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1447
1448         old_flags = vnic->flags;
1449         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1450         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1451         if (rc != 0)
1452                 vnic->flags = old_flags;
1453
1454         return rc;
1455 }
1456
1457 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1458 {
1459         struct bnxt *bp = eth_dev->data->dev_private;
1460         struct bnxt_vnic_info *vnic;
1461         uint32_t old_flags;
1462         int rc;
1463
1464         rc = is_bnxt_in_error(bp);
1465         if (rc)
1466                 return rc;
1467
1468         /* Filter settings will get applied when port is started */
1469         if (!eth_dev->data->dev_started)
1470                 return 0;
1471
1472         if (bp->vnic_info == NULL)
1473                 return 0;
1474
1475         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1476
1477         old_flags = vnic->flags;
1478         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1479         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1480         if (rc != 0)
1481                 vnic->flags = old_flags;
1482
1483         return rc;
1484 }
1485
1486 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1487 {
1488         struct bnxt *bp = eth_dev->data->dev_private;
1489         struct bnxt_vnic_info *vnic;
1490         uint32_t old_flags;
1491         int rc;
1492
1493         rc = is_bnxt_in_error(bp);
1494         if (rc)
1495                 return rc;
1496
1497         /* Filter settings will get applied when port is started */
1498         if (!eth_dev->data->dev_started)
1499                 return 0;
1500
1501         if (bp->vnic_info == NULL)
1502                 return 0;
1503
1504         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1505
1506         old_flags = vnic->flags;
1507         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1508         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1509         if (rc != 0)
1510                 vnic->flags = old_flags;
1511
1512         return rc;
1513 }
1514
1515 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1516 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1517 {
1518         if (qid >= bp->rx_nr_rings)
1519                 return NULL;
1520
1521         return bp->eth_dev->data->rx_queues[qid];
1522 }
1523
1524 /* Return rxq corresponding to a given rss table ring/group ID. */
1525 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1526 {
1527         struct bnxt_rx_queue *rxq;
1528         unsigned int i;
1529
1530         if (!BNXT_HAS_RING_GRPS(bp)) {
1531                 for (i = 0; i < bp->rx_nr_rings; i++) {
1532                         rxq = bp->eth_dev->data->rx_queues[i];
1533                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1534                                 return rxq->index;
1535                 }
1536         } else {
1537                 for (i = 0; i < bp->rx_nr_rings; i++) {
1538                         if (bp->grp_info[i].fw_grp_id == fwr)
1539                                 return i;
1540                 }
1541         }
1542
1543         return INVALID_HW_RING_ID;
1544 }
1545
1546 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1547                             struct rte_eth_rss_reta_entry64 *reta_conf,
1548                             uint16_t reta_size)
1549 {
1550         struct bnxt *bp = eth_dev->data->dev_private;
1551         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1552         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1553         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1554         uint16_t idx, sft;
1555         int i, rc;
1556
1557         rc = is_bnxt_in_error(bp);
1558         if (rc)
1559                 return rc;
1560
1561         if (!vnic->rss_table)
1562                 return -EINVAL;
1563
1564         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1565                 return -EINVAL;
1566
1567         if (reta_size != tbl_size) {
1568                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1569                         "(%d) must equal the size supported by the hardware "
1570                         "(%d)\n", reta_size, tbl_size);
1571                 return -EINVAL;
1572         }
1573
1574         for (i = 0; i < reta_size; i++) {
1575                 struct bnxt_rx_queue *rxq;
1576
1577                 idx = i / RTE_RETA_GROUP_SIZE;
1578                 sft = i % RTE_RETA_GROUP_SIZE;
1579
1580                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1581                         continue;
1582
1583                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1584                 if (!rxq) {
1585                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1586                         return -EINVAL;
1587                 }
1588
1589                 if (BNXT_CHIP_THOR(bp)) {
1590                         vnic->rss_table[i * 2] =
1591                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1592                         vnic->rss_table[i * 2 + 1] =
1593                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1594                 } else {
1595                         vnic->rss_table[i] =
1596                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1597                 }
1598         }
1599
1600         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1601         return 0;
1602 }
1603
1604 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1605                               struct rte_eth_rss_reta_entry64 *reta_conf,
1606                               uint16_t reta_size)
1607 {
1608         struct bnxt *bp = eth_dev->data->dev_private;
1609         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1610         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1611         uint16_t idx, sft, i;
1612         int rc;
1613
1614         rc = is_bnxt_in_error(bp);
1615         if (rc)
1616                 return rc;
1617
1618         /* Retrieve from the default VNIC */
1619         if (!vnic)
1620                 return -EINVAL;
1621         if (!vnic->rss_table)
1622                 return -EINVAL;
1623
1624         if (reta_size != tbl_size) {
1625                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1626                         "(%d) must equal the size supported by the hardware "
1627                         "(%d)\n", reta_size, tbl_size);
1628                 return -EINVAL;
1629         }
1630
1631         for (idx = 0, i = 0; i < reta_size; i++) {
1632                 idx = i / RTE_RETA_GROUP_SIZE;
1633                 sft = i % RTE_RETA_GROUP_SIZE;
1634
1635                 if (reta_conf[idx].mask & (1ULL << sft)) {
1636                         uint16_t qid;
1637
1638                         if (BNXT_CHIP_THOR(bp))
1639                                 qid = bnxt_rss_to_qid(bp,
1640                                                       vnic->rss_table[i * 2]);
1641                         else
1642                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1643
1644                         if (qid == INVALID_HW_RING_ID) {
1645                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1646                                 return -EINVAL;
1647                         }
1648                         reta_conf[idx].reta[sft] = qid;
1649                 }
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1656                                    struct rte_eth_rss_conf *rss_conf)
1657 {
1658         struct bnxt *bp = eth_dev->data->dev_private;
1659         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1660         struct bnxt_vnic_info *vnic;
1661         int rc;
1662
1663         rc = is_bnxt_in_error(bp);
1664         if (rc)
1665                 return rc;
1666
1667         /*
1668          * If RSS enablement were different than dev_configure,
1669          * then return -EINVAL
1670          */
1671         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1672                 if (!rss_conf->rss_hf)
1673                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1674         } else {
1675                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1676                         return -EINVAL;
1677         }
1678
1679         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1680         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1681
1682         /* Update the default RSS VNIC(s) */
1683         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1684         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1685
1686         /*
1687          * If hashkey is not specified, use the previously configured
1688          * hashkey
1689          */
1690         if (!rss_conf->rss_key)
1691                 goto rss_config;
1692
1693         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1694                 PMD_DRV_LOG(ERR,
1695                             "Invalid hashkey length, should be 16 bytes\n");
1696                 return -EINVAL;
1697         }
1698         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1699
1700 rss_config:
1701         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1702         return 0;
1703 }
1704
1705 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1706                                      struct rte_eth_rss_conf *rss_conf)
1707 {
1708         struct bnxt *bp = eth_dev->data->dev_private;
1709         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1710         int len, rc;
1711         uint32_t hash_types;
1712
1713         rc = is_bnxt_in_error(bp);
1714         if (rc)
1715                 return rc;
1716
1717         /* RSS configuration is the same for all VNICs */
1718         if (vnic && vnic->rss_hash_key) {
1719                 if (rss_conf->rss_key) {
1720                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1721                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1722                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1723                 }
1724
1725                 hash_types = vnic->hash_type;
1726                 rss_conf->rss_hf = 0;
1727                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1728                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1729                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1730                 }
1731                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1732                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1733                         hash_types &=
1734                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1735                 }
1736                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1737                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1738                         hash_types &=
1739                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1740                 }
1741                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1742                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1743                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1744                 }
1745                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1746                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1747                         hash_types &=
1748                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1749                 }
1750                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1751                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1752                         hash_types &=
1753                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1754                 }
1755                 if (hash_types) {
1756                         PMD_DRV_LOG(ERR,
1757                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1758                                 vnic->hash_type);
1759                         return -ENOTSUP;
1760                 }
1761         } else {
1762                 rss_conf->rss_hf = 0;
1763         }
1764         return 0;
1765 }
1766
1767 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1768                                struct rte_eth_fc_conf *fc_conf)
1769 {
1770         struct bnxt *bp = dev->data->dev_private;
1771         struct rte_eth_link link_info;
1772         int rc;
1773
1774         rc = is_bnxt_in_error(bp);
1775         if (rc)
1776                 return rc;
1777
1778         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1779         if (rc)
1780                 return rc;
1781
1782         memset(fc_conf, 0, sizeof(*fc_conf));
1783         if (bp->link_info.auto_pause)
1784                 fc_conf->autoneg = 1;
1785         switch (bp->link_info.pause) {
1786         case 0:
1787                 fc_conf->mode = RTE_FC_NONE;
1788                 break;
1789         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1790                 fc_conf->mode = RTE_FC_TX_PAUSE;
1791                 break;
1792         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1793                 fc_conf->mode = RTE_FC_RX_PAUSE;
1794                 break;
1795         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1796                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1797                 fc_conf->mode = RTE_FC_FULL;
1798                 break;
1799         }
1800         return 0;
1801 }
1802
1803 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1804                                struct rte_eth_fc_conf *fc_conf)
1805 {
1806         struct bnxt *bp = dev->data->dev_private;
1807         int rc;
1808
1809         rc = is_bnxt_in_error(bp);
1810         if (rc)
1811                 return rc;
1812
1813         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1814                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1815                 return -ENOTSUP;
1816         }
1817
1818         switch (fc_conf->mode) {
1819         case RTE_FC_NONE:
1820                 bp->link_info.auto_pause = 0;
1821                 bp->link_info.force_pause = 0;
1822                 break;
1823         case RTE_FC_RX_PAUSE:
1824                 if (fc_conf->autoneg) {
1825                         bp->link_info.auto_pause =
1826                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1827                         bp->link_info.force_pause = 0;
1828                 } else {
1829                         bp->link_info.auto_pause = 0;
1830                         bp->link_info.force_pause =
1831                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1832                 }
1833                 break;
1834         case RTE_FC_TX_PAUSE:
1835                 if (fc_conf->autoneg) {
1836                         bp->link_info.auto_pause =
1837                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1838                         bp->link_info.force_pause = 0;
1839                 } else {
1840                         bp->link_info.auto_pause = 0;
1841                         bp->link_info.force_pause =
1842                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1843                 }
1844                 break;
1845         case RTE_FC_FULL:
1846                 if (fc_conf->autoneg) {
1847                         bp->link_info.auto_pause =
1848                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1849                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1850                         bp->link_info.force_pause = 0;
1851                 } else {
1852                         bp->link_info.auto_pause = 0;
1853                         bp->link_info.force_pause =
1854                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1855                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1856                 }
1857                 break;
1858         }
1859         return bnxt_set_hwrm_link_config(bp, true);
1860 }
1861
1862 /* Add UDP tunneling port */
1863 static int
1864 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1865                          struct rte_eth_udp_tunnel *udp_tunnel)
1866 {
1867         struct bnxt *bp = eth_dev->data->dev_private;
1868         uint16_t tunnel_type = 0;
1869         int rc = 0;
1870
1871         rc = is_bnxt_in_error(bp);
1872         if (rc)
1873                 return rc;
1874
1875         switch (udp_tunnel->prot_type) {
1876         case RTE_TUNNEL_TYPE_VXLAN:
1877                 if (bp->vxlan_port_cnt) {
1878                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1879                                 udp_tunnel->udp_port);
1880                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1881                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1882                                 return -ENOSPC;
1883                         }
1884                         bp->vxlan_port_cnt++;
1885                         return 0;
1886                 }
1887                 tunnel_type =
1888                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1889                 bp->vxlan_port_cnt++;
1890                 break;
1891         case RTE_TUNNEL_TYPE_GENEVE:
1892                 if (bp->geneve_port_cnt) {
1893                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1894                                 udp_tunnel->udp_port);
1895                         if (bp->geneve_port != udp_tunnel->udp_port) {
1896                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1897                                 return -ENOSPC;
1898                         }
1899                         bp->geneve_port_cnt++;
1900                         return 0;
1901                 }
1902                 tunnel_type =
1903                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1904                 bp->geneve_port_cnt++;
1905                 break;
1906         default:
1907                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1908                 return -ENOTSUP;
1909         }
1910         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1911                                              tunnel_type);
1912         return rc;
1913 }
1914
1915 static int
1916 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1917                          struct rte_eth_udp_tunnel *udp_tunnel)
1918 {
1919         struct bnxt *bp = eth_dev->data->dev_private;
1920         uint16_t tunnel_type = 0;
1921         uint16_t port = 0;
1922         int rc = 0;
1923
1924         rc = is_bnxt_in_error(bp);
1925         if (rc)
1926                 return rc;
1927
1928         switch (udp_tunnel->prot_type) {
1929         case RTE_TUNNEL_TYPE_VXLAN:
1930                 if (!bp->vxlan_port_cnt) {
1931                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1932                         return -EINVAL;
1933                 }
1934                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1935                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1936                                 udp_tunnel->udp_port, bp->vxlan_port);
1937                         return -EINVAL;
1938                 }
1939                 if (--bp->vxlan_port_cnt)
1940                         return 0;
1941
1942                 tunnel_type =
1943                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1944                 port = bp->vxlan_fw_dst_port_id;
1945                 break;
1946         case RTE_TUNNEL_TYPE_GENEVE:
1947                 if (!bp->geneve_port_cnt) {
1948                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1949                         return -EINVAL;
1950                 }
1951                 if (bp->geneve_port != udp_tunnel->udp_port) {
1952                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1953                                 udp_tunnel->udp_port, bp->geneve_port);
1954                         return -EINVAL;
1955                 }
1956                 if (--bp->geneve_port_cnt)
1957                         return 0;
1958
1959                 tunnel_type =
1960                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1961                 port = bp->geneve_fw_dst_port_id;
1962                 break;
1963         default:
1964                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1965                 return -ENOTSUP;
1966         }
1967
1968         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1969         if (!rc) {
1970                 if (tunnel_type ==
1971                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1972                         bp->vxlan_port = 0;
1973                 if (tunnel_type ==
1974                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1975                         bp->geneve_port = 0;
1976         }
1977         return rc;
1978 }
1979
1980 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1981 {
1982         struct bnxt_filter_info *filter;
1983         struct bnxt_vnic_info *vnic;
1984         int rc = 0;
1985         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1986
1987         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1988         filter = STAILQ_FIRST(&vnic->filter);
1989         while (filter) {
1990                 /* Search for this matching MAC+VLAN filter */
1991                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1992                         /* Delete the filter */
1993                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1994                         if (rc)
1995                                 return rc;
1996                         STAILQ_REMOVE(&vnic->filter, filter,
1997                                       bnxt_filter_info, next);
1998                         bnxt_free_filter(bp, filter);
1999                         PMD_DRV_LOG(INFO,
2000                                     "Deleted vlan filter for %d\n",
2001                                     vlan_id);
2002                         return 0;
2003                 }
2004                 filter = STAILQ_NEXT(filter, next);
2005         }
2006         return -ENOENT;
2007 }
2008
2009 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2010 {
2011         struct bnxt_filter_info *filter;
2012         struct bnxt_vnic_info *vnic;
2013         int rc = 0;
2014         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2015                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2016         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2017
2018         /* Implementation notes on the use of VNIC in this command:
2019          *
2020          * By default, these filters belong to default vnic for the function.
2021          * Once these filters are set up, only destination VNIC can be modified.
2022          * If the destination VNIC is not specified in this command,
2023          * then the HWRM shall only create an l2 context id.
2024          */
2025
2026         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2027         filter = STAILQ_FIRST(&vnic->filter);
2028         /* Check if the VLAN has already been added */
2029         while (filter) {
2030                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2031                         return -EEXIST;
2032
2033                 filter = STAILQ_NEXT(filter, next);
2034         }
2035
2036         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2037          * command to create MAC+VLAN filter with the right flags, enables set.
2038          */
2039         filter = bnxt_alloc_filter(bp);
2040         if (!filter) {
2041                 PMD_DRV_LOG(ERR,
2042                             "MAC/VLAN filter alloc failed\n");
2043                 return -ENOMEM;
2044         }
2045         /* MAC + VLAN ID filter */
2046         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2047          * untagged packets are received
2048          *
2049          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2050          * packets and only the programmed vlan's packets are received
2051          */
2052         filter->l2_ivlan = vlan_id;
2053         filter->l2_ivlan_mask = 0x0FFF;
2054         filter->enables |= en;
2055         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2056
2057         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2058         if (rc) {
2059                 /* Free the newly allocated filter as we were
2060                  * not able to create the filter in hardware.
2061                  */
2062                 bnxt_free_filter(bp, filter);
2063                 return rc;
2064         }
2065
2066         filter->mac_index = 0;
2067         /* Add this new filter to the list */
2068         if (vlan_id == 0)
2069                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2070         else
2071                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2072
2073         PMD_DRV_LOG(INFO,
2074                     "Added Vlan filter for %d\n", vlan_id);
2075         return rc;
2076 }
2077
2078 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2079                 uint16_t vlan_id, int on)
2080 {
2081         struct bnxt *bp = eth_dev->data->dev_private;
2082         int rc;
2083
2084         rc = is_bnxt_in_error(bp);
2085         if (rc)
2086                 return rc;
2087
2088         if (!eth_dev->data->dev_started) {
2089                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2090                 return -EINVAL;
2091         }
2092
2093         /* These operations apply to ALL existing MAC/VLAN filters */
2094         if (on)
2095                 return bnxt_add_vlan_filter(bp, vlan_id);
2096         else
2097                 return bnxt_del_vlan_filter(bp, vlan_id);
2098 }
2099
2100 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2101                                     struct bnxt_vnic_info *vnic)
2102 {
2103         struct bnxt_filter_info *filter;
2104         int rc;
2105
2106         filter = STAILQ_FIRST(&vnic->filter);
2107         while (filter) {
2108                 if (filter->mac_index == 0 &&
2109                     !memcmp(filter->l2_addr, bp->mac_addr,
2110                             RTE_ETHER_ADDR_LEN)) {
2111                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2112                         if (!rc) {
2113                                 STAILQ_REMOVE(&vnic->filter, filter,
2114                                               bnxt_filter_info, next);
2115                                 bnxt_free_filter(bp, filter);
2116                         }
2117                         return rc;
2118                 }
2119                 filter = STAILQ_NEXT(filter, next);
2120         }
2121         return 0;
2122 }
2123
2124 static int
2125 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2126 {
2127         struct bnxt_vnic_info *vnic;
2128         unsigned int i;
2129         int rc;
2130
2131         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2132         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2133                 /* Remove any VLAN filters programmed */
2134                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2135                         bnxt_del_vlan_filter(bp, i);
2136
2137                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2138                 if (rc)
2139                         return rc;
2140         } else {
2141                 /* Default filter will allow packets that match the
2142                  * dest mac. So, it has to be deleted, otherwise, we
2143                  * will endup receiving vlan packets for which the
2144                  * filter is not programmed, when hw-vlan-filter
2145                  * configuration is ON
2146                  */
2147                 bnxt_del_dflt_mac_filter(bp, vnic);
2148                 /* This filter will allow only untagged packets */
2149                 bnxt_add_vlan_filter(bp, 0);
2150         }
2151         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2152                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2153
2154         return 0;
2155 }
2156
2157 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2158 {
2159         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2160         unsigned int i;
2161         int rc;
2162
2163         /* Destroy vnic filters and vnic */
2164         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2165             DEV_RX_OFFLOAD_VLAN_FILTER) {
2166                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2167                         bnxt_del_vlan_filter(bp, i);
2168         }
2169         bnxt_del_dflt_mac_filter(bp, vnic);
2170
2171         rc = bnxt_hwrm_vnic_free(bp, vnic);
2172         if (rc)
2173                 return rc;
2174
2175         rte_free(vnic->fw_grp_ids);
2176         vnic->fw_grp_ids = NULL;
2177
2178         vnic->rx_queue_cnt = 0;
2179
2180         return 0;
2181 }
2182
2183 static int
2184 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2185 {
2186         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2187         int rc;
2188
2189         /* Destroy, recreate and reconfigure the default vnic */
2190         rc = bnxt_free_one_vnic(bp, 0);
2191         if (rc)
2192                 return rc;
2193
2194         /* default vnic 0 */
2195         rc = bnxt_setup_one_vnic(bp, 0);
2196         if (rc)
2197                 return rc;
2198
2199         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2200             DEV_RX_OFFLOAD_VLAN_FILTER) {
2201                 rc = bnxt_add_vlan_filter(bp, 0);
2202                 if (rc)
2203                         return rc;
2204                 rc = bnxt_restore_vlan_filters(bp);
2205                 if (rc)
2206                         return rc;
2207         } else {
2208                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2209                 if (rc)
2210                         return rc;
2211         }
2212
2213         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2214         if (rc)
2215                 return rc;
2216
2217         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2218                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2219
2220         return rc;
2221 }
2222
2223 static int
2224 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2225 {
2226         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2227         struct bnxt *bp = dev->data->dev_private;
2228         int rc;
2229
2230         rc = is_bnxt_in_error(bp);
2231         if (rc)
2232                 return rc;
2233
2234         /* Filter settings will get applied when port is started */
2235         if (!dev->data->dev_started)
2236                 return 0;
2237
2238         if (mask & ETH_VLAN_FILTER_MASK) {
2239                 /* Enable or disable VLAN filtering */
2240                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2241                 if (rc)
2242                         return rc;
2243         }
2244
2245         if (mask & ETH_VLAN_STRIP_MASK) {
2246                 /* Enable or disable VLAN stripping */
2247                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2248                 if (rc)
2249                         return rc;
2250         }
2251
2252         if (mask & ETH_VLAN_EXTEND_MASK) {
2253                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2254                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2255                 else
2256                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2257         }
2258
2259         return 0;
2260 }
2261
2262 static int
2263 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2264                       uint16_t tpid)
2265 {
2266         struct bnxt *bp = dev->data->dev_private;
2267         int qinq = dev->data->dev_conf.rxmode.offloads &
2268                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2269
2270         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2271             vlan_type != ETH_VLAN_TYPE_OUTER) {
2272                 PMD_DRV_LOG(ERR,
2273                             "Unsupported vlan type.");
2274                 return -EINVAL;
2275         }
2276         if (!qinq) {
2277                 PMD_DRV_LOG(ERR,
2278                             "QinQ not enabled. Needs to be ON as we can "
2279                             "accelerate only outer vlan\n");
2280                 return -EINVAL;
2281         }
2282
2283         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2284                 switch (tpid) {
2285                 case RTE_ETHER_TYPE_QINQ:
2286                         bp->outer_tpid_bd =
2287                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2288                                 break;
2289                 case RTE_ETHER_TYPE_VLAN:
2290                         bp->outer_tpid_bd =
2291                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2292                                 break;
2293                 case 0x9100:
2294                         bp->outer_tpid_bd =
2295                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2296                                 break;
2297                 case 0x9200:
2298                         bp->outer_tpid_bd =
2299                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2300                                 break;
2301                 case 0x9300:
2302                         bp->outer_tpid_bd =
2303                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2304                                 break;
2305                 default:
2306                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2307                         return -EINVAL;
2308                 }
2309                 bp->outer_tpid_bd |= tpid;
2310                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2311         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2312                 PMD_DRV_LOG(ERR,
2313                             "Can accelerate only outer vlan in QinQ\n");
2314                 return -EINVAL;
2315         }
2316
2317         return 0;
2318 }
2319
2320 static int
2321 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2322                              struct rte_ether_addr *addr)
2323 {
2324         struct bnxt *bp = dev->data->dev_private;
2325         /* Default Filter is tied to VNIC 0 */
2326         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2327         int rc;
2328
2329         rc = is_bnxt_in_error(bp);
2330         if (rc)
2331                 return rc;
2332
2333         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2334                 return -EPERM;
2335
2336         if (rte_is_zero_ether_addr(addr))
2337                 return -EINVAL;
2338
2339         /* Filter settings will get applied when port is started */
2340         if (!dev->data->dev_started)
2341                 return 0;
2342
2343         /* Check if the requested MAC is already added */
2344         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2345                 return 0;
2346
2347         /* Destroy filter and re-create it */
2348         bnxt_del_dflt_mac_filter(bp, vnic);
2349
2350         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2351         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2352                 /* This filter will allow only untagged packets */
2353                 rc = bnxt_add_vlan_filter(bp, 0);
2354         } else {
2355                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2356         }
2357
2358         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2359         return rc;
2360 }
2361
2362 static int
2363 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2364                           struct rte_ether_addr *mc_addr_set,
2365                           uint32_t nb_mc_addr)
2366 {
2367         struct bnxt *bp = eth_dev->data->dev_private;
2368         char *mc_addr_list = (char *)mc_addr_set;
2369         struct bnxt_vnic_info *vnic;
2370         uint32_t off = 0, i = 0;
2371         int rc;
2372
2373         rc = is_bnxt_in_error(bp);
2374         if (rc)
2375                 return rc;
2376
2377         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2378
2379         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2380                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2381                 goto allmulti;
2382         }
2383
2384         /* TODO Check for Duplicate mcast addresses */
2385         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2386         for (i = 0; i < nb_mc_addr; i++) {
2387                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2388                         RTE_ETHER_ADDR_LEN);
2389                 off += RTE_ETHER_ADDR_LEN;
2390         }
2391
2392         vnic->mc_addr_cnt = i;
2393         if (vnic->mc_addr_cnt)
2394                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2395         else
2396                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2397
2398 allmulti:
2399         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2400 }
2401
2402 static int
2403 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2404 {
2405         struct bnxt *bp = dev->data->dev_private;
2406         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2407         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2408         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2409         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2410         int ret;
2411
2412         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2413                         fw_major, fw_minor, fw_updt, fw_rsvd);
2414
2415         ret += 1; /* add the size of '\0' */
2416         if (fw_size < (uint32_t)ret)
2417                 return ret;
2418         else
2419                 return 0;
2420 }
2421
2422 static void
2423 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2424         struct rte_eth_rxq_info *qinfo)
2425 {
2426         struct bnxt *bp = dev->data->dev_private;
2427         struct bnxt_rx_queue *rxq;
2428
2429         if (is_bnxt_in_error(bp))
2430                 return;
2431
2432         rxq = dev->data->rx_queues[queue_id];
2433
2434         qinfo->mp = rxq->mb_pool;
2435         qinfo->scattered_rx = dev->data->scattered_rx;
2436         qinfo->nb_desc = rxq->nb_rx_desc;
2437
2438         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2439         qinfo->conf.rx_drop_en = 0;
2440         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2441 }
2442
2443 static void
2444 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2445         struct rte_eth_txq_info *qinfo)
2446 {
2447         struct bnxt *bp = dev->data->dev_private;
2448         struct bnxt_tx_queue *txq;
2449
2450         if (is_bnxt_in_error(bp))
2451                 return;
2452
2453         txq = dev->data->tx_queues[queue_id];
2454
2455         qinfo->nb_desc = txq->nb_tx_desc;
2456
2457         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2458         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2459         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2460
2461         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2462         qinfo->conf.tx_rs_thresh = 0;
2463         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2464 }
2465
2466 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2467 {
2468         struct bnxt *bp = eth_dev->data->dev_private;
2469         uint32_t new_pkt_size;
2470         uint32_t rc = 0;
2471         uint32_t i;
2472
2473         rc = is_bnxt_in_error(bp);
2474         if (rc)
2475                 return rc;
2476
2477         /* Exit if receive queues are not configured yet */
2478         if (!eth_dev->data->nb_rx_queues)
2479                 return rc;
2480
2481         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2482                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2483
2484 #ifdef RTE_ARCH_X86
2485         /*
2486          * If vector-mode tx/rx is active, disallow any MTU change that would
2487          * require scattered receive support.
2488          */
2489         if (eth_dev->data->dev_started &&
2490             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2491              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2492             (new_pkt_size >
2493              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2494                 PMD_DRV_LOG(ERR,
2495                             "MTU change would require scattered rx support. ");
2496                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2497                 return -EINVAL;
2498         }
2499 #endif
2500
2501         if (new_mtu > RTE_ETHER_MTU) {
2502                 bp->flags |= BNXT_FLAG_JUMBO;
2503                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2504                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2505         } else {
2506                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2507                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2508                 bp->flags &= ~BNXT_FLAG_JUMBO;
2509         }
2510
2511         /* Is there a change in mtu setting? */
2512         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2513                 return rc;
2514
2515         for (i = 0; i < bp->nr_vnics; i++) {
2516                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2517                 uint16_t size = 0;
2518
2519                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2520                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2521                 if (rc)
2522                         break;
2523
2524                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2525                 size -= RTE_PKTMBUF_HEADROOM;
2526
2527                 if (size < new_mtu) {
2528                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2529                         if (rc)
2530                                 return rc;
2531                 }
2532         }
2533
2534         if (!rc)
2535                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2536
2537         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2538
2539         return rc;
2540 }
2541
2542 static int
2543 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2544 {
2545         struct bnxt *bp = dev->data->dev_private;
2546         uint16_t vlan = bp->vlan;
2547         int rc;
2548
2549         rc = is_bnxt_in_error(bp);
2550         if (rc)
2551                 return rc;
2552
2553         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2554                 PMD_DRV_LOG(ERR,
2555                         "PVID cannot be modified for this function\n");
2556                 return -ENOTSUP;
2557         }
2558         bp->vlan = on ? pvid : 0;
2559
2560         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2561         if (rc)
2562                 bp->vlan = vlan;
2563         return rc;
2564 }
2565
2566 static int
2567 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2568 {
2569         struct bnxt *bp = dev->data->dev_private;
2570         int rc;
2571
2572         rc = is_bnxt_in_error(bp);
2573         if (rc)
2574                 return rc;
2575
2576         return bnxt_hwrm_port_led_cfg(bp, true);
2577 }
2578
2579 static int
2580 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2581 {
2582         struct bnxt *bp = dev->data->dev_private;
2583         int rc;
2584
2585         rc = is_bnxt_in_error(bp);
2586         if (rc)
2587                 return rc;
2588
2589         return bnxt_hwrm_port_led_cfg(bp, false);
2590 }
2591
2592 static uint32_t
2593 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2594 {
2595         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2596         uint32_t desc = 0, raw_cons = 0, cons;
2597         struct bnxt_cp_ring_info *cpr;
2598         struct bnxt_rx_queue *rxq;
2599         struct rx_pkt_cmpl *rxcmp;
2600         int rc;
2601
2602         rc = is_bnxt_in_error(bp);
2603         if (rc)
2604                 return rc;
2605
2606         rxq = dev->data->rx_queues[rx_queue_id];
2607         cpr = rxq->cp_ring;
2608         raw_cons = cpr->cp_raw_cons;
2609
2610         while (1) {
2611                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2612                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2613                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2614
2615                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2616                         break;
2617                 } else {
2618                         raw_cons++;
2619                         desc++;
2620                 }
2621         }
2622
2623         return desc;
2624 }
2625
2626 static int
2627 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2628 {
2629         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2630         struct bnxt_rx_ring_info *rxr;
2631         struct bnxt_cp_ring_info *cpr;
2632         struct bnxt_sw_rx_bd *rx_buf;
2633         struct rx_pkt_cmpl *rxcmp;
2634         uint32_t cons, cp_cons;
2635         int rc;
2636
2637         if (!rxq)
2638                 return -EINVAL;
2639
2640         rc = is_bnxt_in_error(rxq->bp);
2641         if (rc)
2642                 return rc;
2643
2644         cpr = rxq->cp_ring;
2645         rxr = rxq->rx_ring;
2646
2647         if (offset >= rxq->nb_rx_desc)
2648                 return -EINVAL;
2649
2650         cons = RING_CMP(cpr->cp_ring_struct, offset);
2651         cp_cons = cpr->cp_raw_cons;
2652         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2653
2654         if (cons > cp_cons) {
2655                 if (CMPL_VALID(rxcmp, cpr->valid))
2656                         return RTE_ETH_RX_DESC_DONE;
2657         } else {
2658                 if (CMPL_VALID(rxcmp, !cpr->valid))
2659                         return RTE_ETH_RX_DESC_DONE;
2660         }
2661         rx_buf = &rxr->rx_buf_ring[cons];
2662         if (rx_buf->mbuf == NULL)
2663                 return RTE_ETH_RX_DESC_UNAVAIL;
2664
2665
2666         return RTE_ETH_RX_DESC_AVAIL;
2667 }
2668
2669 static int
2670 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2671 {
2672         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2673         struct bnxt_tx_ring_info *txr;
2674         struct bnxt_cp_ring_info *cpr;
2675         struct bnxt_sw_tx_bd *tx_buf;
2676         struct tx_pkt_cmpl *txcmp;
2677         uint32_t cons, cp_cons;
2678         int rc;
2679
2680         if (!txq)
2681                 return -EINVAL;
2682
2683         rc = is_bnxt_in_error(txq->bp);
2684         if (rc)
2685                 return rc;
2686
2687         cpr = txq->cp_ring;
2688         txr = txq->tx_ring;
2689
2690         if (offset >= txq->nb_tx_desc)
2691                 return -EINVAL;
2692
2693         cons = RING_CMP(cpr->cp_ring_struct, offset);
2694         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2695         cp_cons = cpr->cp_raw_cons;
2696
2697         if (cons > cp_cons) {
2698                 if (CMPL_VALID(txcmp, cpr->valid))
2699                         return RTE_ETH_TX_DESC_UNAVAIL;
2700         } else {
2701                 if (CMPL_VALID(txcmp, !cpr->valid))
2702                         return RTE_ETH_TX_DESC_UNAVAIL;
2703         }
2704         tx_buf = &txr->tx_buf_ring[cons];
2705         if (tx_buf->mbuf == NULL)
2706                 return RTE_ETH_TX_DESC_DONE;
2707
2708         return RTE_ETH_TX_DESC_FULL;
2709 }
2710
2711 static struct bnxt_filter_info *
2712 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2713                                 struct rte_eth_ethertype_filter *efilter,
2714                                 struct bnxt_vnic_info *vnic0,
2715                                 struct bnxt_vnic_info *vnic,
2716                                 int *ret)
2717 {
2718         struct bnxt_filter_info *mfilter = NULL;
2719         int match = 0;
2720         *ret = 0;
2721
2722         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2723                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2724                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2725                         " ethertype filter.", efilter->ether_type);
2726                 *ret = -EINVAL;
2727                 goto exit;
2728         }
2729         if (efilter->queue >= bp->rx_nr_rings) {
2730                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2731                 *ret = -EINVAL;
2732                 goto exit;
2733         }
2734
2735         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2736         vnic = &bp->vnic_info[efilter->queue];
2737         if (vnic == NULL) {
2738                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2739                 *ret = -EINVAL;
2740                 goto exit;
2741         }
2742
2743         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2744                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2745                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2746                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2747                              mfilter->flags ==
2748                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2749                              mfilter->ethertype == efilter->ether_type)) {
2750                                 match = 1;
2751                                 break;
2752                         }
2753                 }
2754         } else {
2755                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2756                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2757                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2758                              mfilter->ethertype == efilter->ether_type &&
2759                              mfilter->flags ==
2760                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2761                                 match = 1;
2762                                 break;
2763                         }
2764         }
2765
2766         if (match)
2767                 *ret = -EEXIST;
2768
2769 exit:
2770         return mfilter;
2771 }
2772
2773 static int
2774 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2775                         enum rte_filter_op filter_op,
2776                         void *arg)
2777 {
2778         struct bnxt *bp = dev->data->dev_private;
2779         struct rte_eth_ethertype_filter *efilter =
2780                         (struct rte_eth_ethertype_filter *)arg;
2781         struct bnxt_filter_info *bfilter, *filter1;
2782         struct bnxt_vnic_info *vnic, *vnic0;
2783         int ret;
2784
2785         if (filter_op == RTE_ETH_FILTER_NOP)
2786                 return 0;
2787
2788         if (arg == NULL) {
2789                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2790                             filter_op);
2791                 return -EINVAL;
2792         }
2793
2794         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2795         vnic = &bp->vnic_info[efilter->queue];
2796
2797         switch (filter_op) {
2798         case RTE_ETH_FILTER_ADD:
2799                 bnxt_match_and_validate_ether_filter(bp, efilter,
2800                                                         vnic0, vnic, &ret);
2801                 if (ret < 0)
2802                         return ret;
2803
2804                 bfilter = bnxt_get_unused_filter(bp);
2805                 if (bfilter == NULL) {
2806                         PMD_DRV_LOG(ERR,
2807                                 "Not enough resources for a new filter.\n");
2808                         return -ENOMEM;
2809                 }
2810                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2811                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2812                        RTE_ETHER_ADDR_LEN);
2813                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2814                        RTE_ETHER_ADDR_LEN);
2815                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2816                 bfilter->ethertype = efilter->ether_type;
2817                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2818
2819                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2820                 if (filter1 == NULL) {
2821                         ret = -EINVAL;
2822                         goto cleanup;
2823                 }
2824                 bfilter->enables |=
2825                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2826                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2827
2828                 bfilter->dst_id = vnic->fw_vnic_id;
2829
2830                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2831                         bfilter->flags =
2832                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2833                 }
2834
2835                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2836                 if (ret)
2837                         goto cleanup;
2838                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2839                 break;
2840         case RTE_ETH_FILTER_DELETE:
2841                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2842                                                         vnic0, vnic, &ret);
2843                 if (ret == -EEXIST) {
2844                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2845
2846                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2847                                       next);
2848                         bnxt_free_filter(bp, filter1);
2849                 } else if (ret == 0) {
2850                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2851                 }
2852                 break;
2853         default:
2854                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2855                 ret = -EINVAL;
2856                 goto error;
2857         }
2858         return ret;
2859 cleanup:
2860         bnxt_free_filter(bp, bfilter);
2861 error:
2862         return ret;
2863 }
2864
2865 static inline int
2866 parse_ntuple_filter(struct bnxt *bp,
2867                     struct rte_eth_ntuple_filter *nfilter,
2868                     struct bnxt_filter_info *bfilter)
2869 {
2870         uint32_t en = 0;
2871
2872         if (nfilter->queue >= bp->rx_nr_rings) {
2873                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2874                 return -EINVAL;
2875         }
2876
2877         switch (nfilter->dst_port_mask) {
2878         case UINT16_MAX:
2879                 bfilter->dst_port_mask = -1;
2880                 bfilter->dst_port = nfilter->dst_port;
2881                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2882                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2883                 break;
2884         default:
2885                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2886                 return -EINVAL;
2887         }
2888
2889         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2890         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2891
2892         switch (nfilter->proto_mask) {
2893         case UINT8_MAX:
2894                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2895                         bfilter->ip_protocol = 17;
2896                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2897                         bfilter->ip_protocol = 6;
2898                 else
2899                         return -EINVAL;
2900                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2901                 break;
2902         default:
2903                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2904                 return -EINVAL;
2905         }
2906
2907         switch (nfilter->dst_ip_mask) {
2908         case UINT32_MAX:
2909                 bfilter->dst_ipaddr_mask[0] = -1;
2910                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2912                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2913                 break;
2914         default:
2915                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2916                 return -EINVAL;
2917         }
2918
2919         switch (nfilter->src_ip_mask) {
2920         case UINT32_MAX:
2921                 bfilter->src_ipaddr_mask[0] = -1;
2922                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2923                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2924                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2925                 break;
2926         default:
2927                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2928                 return -EINVAL;
2929         }
2930
2931         switch (nfilter->src_port_mask) {
2932         case UINT16_MAX:
2933                 bfilter->src_port_mask = -1;
2934                 bfilter->src_port = nfilter->src_port;
2935                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2936                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2937                 break;
2938         default:
2939                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2940                 return -EINVAL;
2941         }
2942
2943         bfilter->enables = en;
2944         return 0;
2945 }
2946
2947 static struct bnxt_filter_info*
2948 bnxt_match_ntuple_filter(struct bnxt *bp,
2949                          struct bnxt_filter_info *bfilter,
2950                          struct bnxt_vnic_info **mvnic)
2951 {
2952         struct bnxt_filter_info *mfilter = NULL;
2953         int i;
2954
2955         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2956                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2957                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2958                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2959                             bfilter->src_ipaddr_mask[0] ==
2960                             mfilter->src_ipaddr_mask[0] &&
2961                             bfilter->src_port == mfilter->src_port &&
2962                             bfilter->src_port_mask == mfilter->src_port_mask &&
2963                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2964                             bfilter->dst_ipaddr_mask[0] ==
2965                             mfilter->dst_ipaddr_mask[0] &&
2966                             bfilter->dst_port == mfilter->dst_port &&
2967                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2968                             bfilter->flags == mfilter->flags &&
2969                             bfilter->enables == mfilter->enables) {
2970                                 if (mvnic)
2971                                         *mvnic = vnic;
2972                                 return mfilter;
2973                         }
2974                 }
2975         }
2976         return NULL;
2977 }
2978
2979 static int
2980 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2981                        struct rte_eth_ntuple_filter *nfilter,
2982                        enum rte_filter_op filter_op)
2983 {
2984         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2985         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2986         int ret;
2987
2988         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2989                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2990                 return -EINVAL;
2991         }
2992
2993         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2994                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2995                 return -EINVAL;
2996         }
2997
2998         bfilter = bnxt_get_unused_filter(bp);
2999         if (bfilter == NULL) {
3000                 PMD_DRV_LOG(ERR,
3001                         "Not enough resources for a new filter.\n");
3002                 return -ENOMEM;
3003         }
3004         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3005         if (ret < 0)
3006                 goto free_filter;
3007
3008         vnic = &bp->vnic_info[nfilter->queue];
3009         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3010         filter1 = STAILQ_FIRST(&vnic0->filter);
3011         if (filter1 == NULL) {
3012                 ret = -EINVAL;
3013                 goto free_filter;
3014         }
3015
3016         bfilter->dst_id = vnic->fw_vnic_id;
3017         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3018         bfilter->enables |=
3019                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3020         bfilter->ethertype = 0x800;
3021         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3022
3023         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3024
3025         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3026             bfilter->dst_id == mfilter->dst_id) {
3027                 PMD_DRV_LOG(ERR, "filter exists.\n");
3028                 ret = -EEXIST;
3029                 goto free_filter;
3030         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3031                    bfilter->dst_id != mfilter->dst_id) {
3032                 mfilter->dst_id = vnic->fw_vnic_id;
3033                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3034                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3035                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3036                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3037                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3038                 goto free_filter;
3039         }
3040         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3041                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3042                 ret = -ENOENT;
3043                 goto free_filter;
3044         }
3045
3046         if (filter_op == RTE_ETH_FILTER_ADD) {
3047                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3048                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3049                 if (ret)
3050                         goto free_filter;
3051                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3052         } else {
3053                 if (mfilter == NULL) {
3054                         /* This should not happen. But for Coverity! */
3055                         ret = -ENOENT;
3056                         goto free_filter;
3057                 }
3058                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3059
3060                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3061                 bnxt_free_filter(bp, mfilter);
3062                 bnxt_free_filter(bp, bfilter);
3063         }
3064
3065         return 0;
3066 free_filter:
3067         bnxt_free_filter(bp, bfilter);
3068         return ret;
3069 }
3070
3071 static int
3072 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3073                         enum rte_filter_op filter_op,
3074                         void *arg)
3075 {
3076         struct bnxt *bp = dev->data->dev_private;
3077         int ret;
3078
3079         if (filter_op == RTE_ETH_FILTER_NOP)
3080                 return 0;
3081
3082         if (arg == NULL) {
3083                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3084                             filter_op);
3085                 return -EINVAL;
3086         }
3087
3088         switch (filter_op) {
3089         case RTE_ETH_FILTER_ADD:
3090                 ret = bnxt_cfg_ntuple_filter(bp,
3091                         (struct rte_eth_ntuple_filter *)arg,
3092                         filter_op);
3093                 break;
3094         case RTE_ETH_FILTER_DELETE:
3095                 ret = bnxt_cfg_ntuple_filter(bp,
3096                         (struct rte_eth_ntuple_filter *)arg,
3097                         filter_op);
3098                 break;
3099         default:
3100                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3101                 ret = -EINVAL;
3102                 break;
3103         }
3104         return ret;
3105 }
3106
3107 static int
3108 bnxt_parse_fdir_filter(struct bnxt *bp,
3109                        struct rte_eth_fdir_filter *fdir,
3110                        struct bnxt_filter_info *filter)
3111 {
3112         enum rte_fdir_mode fdir_mode =
3113                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3114         struct bnxt_vnic_info *vnic0, *vnic;
3115         struct bnxt_filter_info *filter1;
3116         uint32_t en = 0;
3117         int i;
3118
3119         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3120                 return -EINVAL;
3121
3122         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3123         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3124
3125         switch (fdir->input.flow_type) {
3126         case RTE_ETH_FLOW_IPV4:
3127         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3128                 /* FALLTHROUGH */
3129                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3130                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3131                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3132                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3133                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3134                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3135                 filter->ip_addr_type =
3136                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3137                 filter->src_ipaddr_mask[0] = 0xffffffff;
3138                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3139                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3140                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3141                 filter->ethertype = 0x800;
3142                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3143                 break;
3144         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3145                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3146                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3147                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3148                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3149                 filter->dst_port_mask = 0xffff;
3150                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3151                 filter->src_port_mask = 0xffff;
3152                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3153                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3154                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3155                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3156                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3157                 filter->ip_protocol = 6;
3158                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3159                 filter->ip_addr_type =
3160                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3161                 filter->src_ipaddr_mask[0] = 0xffffffff;
3162                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3163                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3164                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3165                 filter->ethertype = 0x800;
3166                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3167                 break;
3168         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3169                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3170                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3171                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3172                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3173                 filter->dst_port_mask = 0xffff;
3174                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3175                 filter->src_port_mask = 0xffff;
3176                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3177                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3178                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3179                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3180                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3181                 filter->ip_protocol = 17;
3182                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3183                 filter->ip_addr_type =
3184                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3185                 filter->src_ipaddr_mask[0] = 0xffffffff;
3186                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3187                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3189                 filter->ethertype = 0x800;
3190                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3191                 break;
3192         case RTE_ETH_FLOW_IPV6:
3193         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3194                 /* FALLTHROUGH */
3195                 filter->ip_addr_type =
3196                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3197                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3198                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3199                 rte_memcpy(filter->src_ipaddr,
3200                            fdir->input.flow.ipv6_flow.src_ip, 16);
3201                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3202                 rte_memcpy(filter->dst_ipaddr,
3203                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3204                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3205                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3206                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3207                 memset(filter->src_ipaddr_mask, 0xff, 16);
3208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3209                 filter->ethertype = 0x86dd;
3210                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3211                 break;
3212         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3213                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3214                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3215                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3216                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3217                 filter->dst_port_mask = 0xffff;
3218                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3219                 filter->src_port_mask = 0xffff;
3220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3221                 filter->ip_addr_type =
3222                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3223                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3224                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3225                 rte_memcpy(filter->src_ipaddr,
3226                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3228                 rte_memcpy(filter->dst_ipaddr,
3229                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3230                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3231                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3232                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3233                 memset(filter->src_ipaddr_mask, 0xff, 16);
3234                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3235                 filter->ethertype = 0x86dd;
3236                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3237                 break;
3238         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3239                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3240                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3241                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3242                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3243                 filter->dst_port_mask = 0xffff;
3244                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3245                 filter->src_port_mask = 0xffff;
3246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3247                 filter->ip_addr_type =
3248                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3249                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3250                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3251                 rte_memcpy(filter->src_ipaddr,
3252                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3254                 rte_memcpy(filter->dst_ipaddr,
3255                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3256                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3257                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3258                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3259                 memset(filter->src_ipaddr_mask, 0xff, 16);
3260                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3261                 filter->ethertype = 0x86dd;
3262                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3263                 break;
3264         case RTE_ETH_FLOW_L2_PAYLOAD:
3265                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3266                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3267                 break;
3268         case RTE_ETH_FLOW_VXLAN:
3269                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3270                         return -EINVAL;
3271                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3272                 filter->tunnel_type =
3273                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3274                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3275                 break;
3276         case RTE_ETH_FLOW_NVGRE:
3277                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3278                         return -EINVAL;
3279                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3280                 filter->tunnel_type =
3281                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3282                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3283                 break;
3284         case RTE_ETH_FLOW_UNKNOWN:
3285         case RTE_ETH_FLOW_RAW:
3286         case RTE_ETH_FLOW_FRAG_IPV4:
3287         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3288         case RTE_ETH_FLOW_FRAG_IPV6:
3289         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3290         case RTE_ETH_FLOW_IPV6_EX:
3291         case RTE_ETH_FLOW_IPV6_TCP_EX:
3292         case RTE_ETH_FLOW_IPV6_UDP_EX:
3293         case RTE_ETH_FLOW_GENEVE:
3294                 /* FALLTHROUGH */
3295         default:
3296                 return -EINVAL;
3297         }
3298
3299         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3300         vnic = &bp->vnic_info[fdir->action.rx_queue];
3301         if (vnic == NULL) {
3302                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3303                 return -EINVAL;
3304         }
3305
3306         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3307                 rte_memcpy(filter->dst_macaddr,
3308                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3309                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3310         }
3311
3312         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3313                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3314                 filter1 = STAILQ_FIRST(&vnic0->filter);
3315                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3316         } else {
3317                 filter->dst_id = vnic->fw_vnic_id;
3318                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3319                         if (filter->dst_macaddr[i] == 0x00)
3320                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3321                         else
3322                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3323         }
3324
3325         if (filter1 == NULL)
3326                 return -EINVAL;
3327
3328         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3329         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3330
3331         filter->enables = en;
3332
3333         return 0;
3334 }
3335
3336 static struct bnxt_filter_info *
3337 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3338                 struct bnxt_vnic_info **mvnic)
3339 {
3340         struct bnxt_filter_info *mf = NULL;
3341         int i;
3342
3343         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3344                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3345
3346                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3347                         if (mf->filter_type == nf->filter_type &&
3348                             mf->flags == nf->flags &&
3349                             mf->src_port == nf->src_port &&
3350                             mf->src_port_mask == nf->src_port_mask &&
3351                             mf->dst_port == nf->dst_port &&
3352                             mf->dst_port_mask == nf->dst_port_mask &&
3353                             mf->ip_protocol == nf->ip_protocol &&
3354                             mf->ip_addr_type == nf->ip_addr_type &&
3355                             mf->ethertype == nf->ethertype &&
3356                             mf->vni == nf->vni &&
3357                             mf->tunnel_type == nf->tunnel_type &&
3358                             mf->l2_ovlan == nf->l2_ovlan &&
3359                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3360                             mf->l2_ivlan == nf->l2_ivlan &&
3361                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3362                             !memcmp(mf->l2_addr, nf->l2_addr,
3363                                     RTE_ETHER_ADDR_LEN) &&
3364                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3365                                     RTE_ETHER_ADDR_LEN) &&
3366                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3367                                     RTE_ETHER_ADDR_LEN) &&
3368                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3369                                     RTE_ETHER_ADDR_LEN) &&
3370                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3371                                     sizeof(nf->src_ipaddr)) &&
3372                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3373                                     sizeof(nf->src_ipaddr_mask)) &&
3374                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3375                                     sizeof(nf->dst_ipaddr)) &&
3376                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3377                                     sizeof(nf->dst_ipaddr_mask))) {
3378                                 if (mvnic)
3379                                         *mvnic = vnic;
3380                                 return mf;
3381                         }
3382                 }
3383         }
3384         return NULL;
3385 }
3386
3387 static int
3388 bnxt_fdir_filter(struct rte_eth_dev *dev,
3389                  enum rte_filter_op filter_op,
3390                  void *arg)
3391 {
3392         struct bnxt *bp = dev->data->dev_private;
3393         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3394         struct bnxt_filter_info *filter, *match;
3395         struct bnxt_vnic_info *vnic, *mvnic;
3396         int ret = 0, i;
3397
3398         if (filter_op == RTE_ETH_FILTER_NOP)
3399                 return 0;
3400
3401         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3402                 return -EINVAL;
3403
3404         switch (filter_op) {
3405         case RTE_ETH_FILTER_ADD:
3406         case RTE_ETH_FILTER_DELETE:
3407                 /* FALLTHROUGH */
3408                 filter = bnxt_get_unused_filter(bp);
3409                 if (filter == NULL) {
3410                         PMD_DRV_LOG(ERR,
3411                                 "Not enough resources for a new flow.\n");
3412                         return -ENOMEM;
3413                 }
3414
3415                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3416                 if (ret != 0)
3417                         goto free_filter;
3418                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3419
3420                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3421                         vnic = &bp->vnic_info[0];
3422                 else
3423                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3424
3425                 match = bnxt_match_fdir(bp, filter, &mvnic);
3426                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3427                         if (match->dst_id == vnic->fw_vnic_id) {
3428                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3429                                 ret = -EEXIST;
3430                                 goto free_filter;
3431                         } else {
3432                                 match->dst_id = vnic->fw_vnic_id;
3433                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3434                                                                   match->dst_id,
3435                                                                   match);
3436                                 STAILQ_REMOVE(&mvnic->filter, match,
3437                                               bnxt_filter_info, next);
3438                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3439                                 PMD_DRV_LOG(ERR,
3440                                         "Filter with matching pattern exist\n");
3441                                 PMD_DRV_LOG(ERR,
3442                                         "Updated it to new destination q\n");
3443                                 goto free_filter;
3444                         }
3445                 }
3446                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3447                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3448                         ret = -ENOENT;
3449                         goto free_filter;
3450                 }
3451
3452                 if (filter_op == RTE_ETH_FILTER_ADD) {
3453                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3454                                                           filter->dst_id,
3455                                                           filter);
3456                         if (ret)
3457                                 goto free_filter;
3458                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3459                 } else {
3460                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3461                         STAILQ_REMOVE(&vnic->filter, match,
3462                                       bnxt_filter_info, next);
3463                         bnxt_free_filter(bp, match);
3464                         bnxt_free_filter(bp, filter);
3465                 }
3466                 break;
3467         case RTE_ETH_FILTER_FLUSH:
3468                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3469                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3470
3471                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3472                                 if (filter->filter_type ==
3473                                     HWRM_CFA_NTUPLE_FILTER) {
3474                                         ret =
3475                                         bnxt_hwrm_clear_ntuple_filter(bp,
3476                                                                       filter);
3477                                         STAILQ_REMOVE(&vnic->filter, filter,
3478                                                       bnxt_filter_info, next);
3479                                 }
3480                         }
3481                 }
3482                 return ret;
3483         case RTE_ETH_FILTER_UPDATE:
3484         case RTE_ETH_FILTER_STATS:
3485         case RTE_ETH_FILTER_INFO:
3486                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3487                 break;
3488         default:
3489                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3490                 ret = -EINVAL;
3491                 break;
3492         }
3493         return ret;
3494
3495 free_filter:
3496         bnxt_free_filter(bp, filter);
3497         return ret;
3498 }
3499
3500 static int
3501 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3502                     enum rte_filter_type filter_type,
3503                     enum rte_filter_op filter_op, void *arg)
3504 {
3505         struct bnxt *bp = dev->data->dev_private;
3506         int ret = 0;
3507
3508         ret = is_bnxt_in_error(dev->data->dev_private);
3509         if (ret)
3510                 return ret;
3511
3512         switch (filter_type) {
3513         case RTE_ETH_FILTER_TUNNEL:
3514                 PMD_DRV_LOG(ERR,
3515                         "filter type: %d: To be implemented\n", filter_type);
3516                 break;
3517         case RTE_ETH_FILTER_FDIR:
3518                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3519                 break;
3520         case RTE_ETH_FILTER_NTUPLE:
3521                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3522                 break;
3523         case RTE_ETH_FILTER_ETHERTYPE:
3524                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3525                 break;
3526         case RTE_ETH_FILTER_GENERIC:
3527                 if (filter_op != RTE_ETH_FILTER_GET)
3528                         return -EINVAL;
3529                 if (bp->truflow)
3530                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3531                 else
3532                         *(const void **)arg = &bnxt_flow_ops;
3533                 break;
3534         default:
3535                 PMD_DRV_LOG(ERR,
3536                         "Filter type (%d) not supported", filter_type);
3537                 ret = -EINVAL;
3538                 break;
3539         }
3540         return ret;
3541 }
3542
3543 static const uint32_t *
3544 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3545 {
3546         static const uint32_t ptypes[] = {
3547                 RTE_PTYPE_L2_ETHER_VLAN,
3548                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3549                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3550                 RTE_PTYPE_L4_ICMP,
3551                 RTE_PTYPE_L4_TCP,
3552                 RTE_PTYPE_L4_UDP,
3553                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3554                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3555                 RTE_PTYPE_INNER_L4_ICMP,
3556                 RTE_PTYPE_INNER_L4_TCP,
3557                 RTE_PTYPE_INNER_L4_UDP,
3558                 RTE_PTYPE_UNKNOWN
3559         };
3560
3561         if (!dev->rx_pkt_burst)
3562                 return NULL;
3563
3564         return ptypes;
3565 }
3566
3567 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3568                          int reg_win)
3569 {
3570         uint32_t reg_base = *reg_arr & 0xfffff000;
3571         uint32_t win_off;
3572         int i;
3573
3574         for (i = 0; i < count; i++) {
3575                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3576                         return -ERANGE;
3577         }
3578         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3579         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3580         return 0;
3581 }
3582
3583 static int bnxt_map_ptp_regs(struct bnxt *bp)
3584 {
3585         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3586         uint32_t *reg_arr;
3587         int rc, i;
3588
3589         reg_arr = ptp->rx_regs;
3590         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3591         if (rc)
3592                 return rc;
3593
3594         reg_arr = ptp->tx_regs;
3595         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3596         if (rc)
3597                 return rc;
3598
3599         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3600                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3601
3602         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3603                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3604
3605         return 0;
3606 }
3607
3608 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3609 {
3610         rte_write32(0, (uint8_t *)bp->bar0 +
3611                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3612         rte_write32(0, (uint8_t *)bp->bar0 +
3613                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3614 }
3615
3616 static uint64_t bnxt_cc_read(struct bnxt *bp)
3617 {
3618         uint64_t ns;
3619
3620         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3621                               BNXT_GRCPF_REG_SYNC_TIME));
3622         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3623                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3624         return ns;
3625 }
3626
3627 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3628 {
3629         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3630         uint32_t fifo;
3631
3632         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3633                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3634         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3635                 return -EAGAIN;
3636
3637         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3638                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3639         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3640                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3641         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3642                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3643
3644         return 0;
3645 }
3646
3647 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3648 {
3649         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3650         struct bnxt_pf_info *pf = &bp->pf;
3651         uint16_t port_id;
3652         uint32_t fifo;
3653
3654         if (!ptp)
3655                 return -ENODEV;
3656
3657         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3658                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3659         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3660                 return -EAGAIN;
3661
3662         port_id = pf->port_id;
3663         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3664                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3665
3666         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3667                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3668         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3669 /*              bnxt_clr_rx_ts(bp);       TBD  */
3670                 return -EBUSY;
3671         }
3672
3673         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3674                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3675         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3676                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3677
3678         return 0;
3679 }
3680
3681 static int
3682 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3683 {
3684         uint64_t ns;
3685         struct bnxt *bp = dev->data->dev_private;
3686         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3687
3688         if (!ptp)
3689                 return 0;
3690
3691         ns = rte_timespec_to_ns(ts);
3692         /* Set the timecounters to a new value. */
3693         ptp->tc.nsec = ns;
3694
3695         return 0;
3696 }
3697
3698 static int
3699 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3700 {
3701         struct bnxt *bp = dev->data->dev_private;
3702         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3703         uint64_t ns, systime_cycles = 0;
3704         int rc = 0;
3705
3706         if (!ptp)
3707                 return 0;
3708
3709         if (BNXT_CHIP_THOR(bp))
3710                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3711                                              &systime_cycles);
3712         else
3713                 systime_cycles = bnxt_cc_read(bp);
3714
3715         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3716         *ts = rte_ns_to_timespec(ns);
3717
3718         return rc;
3719 }
3720 static int
3721 bnxt_timesync_enable(struct rte_eth_dev *dev)
3722 {
3723         struct bnxt *bp = dev->data->dev_private;
3724         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3725         uint32_t shift = 0;
3726         int rc;
3727
3728         if (!ptp)
3729                 return 0;
3730
3731         ptp->rx_filter = 1;
3732         ptp->tx_tstamp_en = 1;
3733         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3734
3735         rc = bnxt_hwrm_ptp_cfg(bp);
3736         if (rc)
3737                 return rc;
3738
3739         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3740         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3741         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3742
3743         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3744         ptp->tc.cc_shift = shift;
3745         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3746
3747         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3748         ptp->rx_tstamp_tc.cc_shift = shift;
3749         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3750
3751         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3752         ptp->tx_tstamp_tc.cc_shift = shift;
3753         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3754
3755         if (!BNXT_CHIP_THOR(bp))
3756                 bnxt_map_ptp_regs(bp);
3757
3758         return 0;
3759 }
3760
3761 static int
3762 bnxt_timesync_disable(struct rte_eth_dev *dev)
3763 {
3764         struct bnxt *bp = dev->data->dev_private;
3765         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3766
3767         if (!ptp)
3768                 return 0;
3769
3770         ptp->rx_filter = 0;
3771         ptp->tx_tstamp_en = 0;
3772         ptp->rxctl = 0;
3773
3774         bnxt_hwrm_ptp_cfg(bp);
3775
3776         if (!BNXT_CHIP_THOR(bp))
3777                 bnxt_unmap_ptp_regs(bp);
3778
3779         return 0;
3780 }
3781
3782 static int
3783 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3784                                  struct timespec *timestamp,
3785                                  uint32_t flags __rte_unused)
3786 {
3787         struct bnxt *bp = dev->data->dev_private;
3788         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3789         uint64_t rx_tstamp_cycles = 0;
3790         uint64_t ns;
3791
3792         if (!ptp)
3793                 return 0;
3794
3795         if (BNXT_CHIP_THOR(bp))
3796                 rx_tstamp_cycles = ptp->rx_timestamp;
3797         else
3798                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3799
3800         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3801         *timestamp = rte_ns_to_timespec(ns);
3802         return  0;
3803 }
3804
3805 static int
3806 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3807                                  struct timespec *timestamp)
3808 {
3809         struct bnxt *bp = dev->data->dev_private;
3810         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3811         uint64_t tx_tstamp_cycles = 0;
3812         uint64_t ns;
3813         int rc = 0;
3814
3815         if (!ptp)
3816                 return 0;
3817
3818         if (BNXT_CHIP_THOR(bp))
3819                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3820                                              &tx_tstamp_cycles);
3821         else
3822                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3823
3824         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3825         *timestamp = rte_ns_to_timespec(ns);
3826
3827         return rc;
3828 }
3829
3830 static int
3831 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3832 {
3833         struct bnxt *bp = dev->data->dev_private;
3834         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3835
3836         if (!ptp)
3837                 return 0;
3838
3839         ptp->tc.nsec += delta;
3840
3841         return 0;
3842 }
3843
3844 static int
3845 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3846 {
3847         struct bnxt *bp = dev->data->dev_private;
3848         int rc;
3849         uint32_t dir_entries;
3850         uint32_t entry_length;
3851
3852         rc = is_bnxt_in_error(bp);
3853         if (rc)
3854                 return rc;
3855
3856         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3857                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3858                     bp->pdev->addr.devid, bp->pdev->addr.function);
3859
3860         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3861         if (rc != 0)
3862                 return rc;
3863
3864         return dir_entries * entry_length;
3865 }
3866
3867 static int
3868 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3869                 struct rte_dev_eeprom_info *in_eeprom)
3870 {
3871         struct bnxt *bp = dev->data->dev_private;
3872         uint32_t index;
3873         uint32_t offset;
3874         int rc;
3875
3876         rc = is_bnxt_in_error(bp);
3877         if (rc)
3878                 return rc;
3879
3880         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3881                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3882                     bp->pdev->addr.devid, bp->pdev->addr.function,
3883                     in_eeprom->offset, in_eeprom->length);
3884
3885         if (in_eeprom->offset == 0) /* special offset value to get directory */
3886                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3887                                                 in_eeprom->data);
3888
3889         index = in_eeprom->offset >> 24;
3890         offset = in_eeprom->offset & 0xffffff;
3891
3892         if (index != 0)
3893                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3894                                            in_eeprom->length, in_eeprom->data);
3895
3896         return 0;
3897 }
3898
3899 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3900 {
3901         switch (dir_type) {
3902         case BNX_DIR_TYPE_CHIMP_PATCH:
3903         case BNX_DIR_TYPE_BOOTCODE:
3904         case BNX_DIR_TYPE_BOOTCODE_2:
3905         case BNX_DIR_TYPE_APE_FW:
3906         case BNX_DIR_TYPE_APE_PATCH:
3907         case BNX_DIR_TYPE_KONG_FW:
3908         case BNX_DIR_TYPE_KONG_PATCH:
3909         case BNX_DIR_TYPE_BONO_FW:
3910         case BNX_DIR_TYPE_BONO_PATCH:
3911                 /* FALLTHROUGH */
3912                 return true;
3913         }
3914
3915         return false;
3916 }
3917
3918 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3919 {
3920         switch (dir_type) {
3921         case BNX_DIR_TYPE_AVS:
3922         case BNX_DIR_TYPE_EXP_ROM_MBA:
3923         case BNX_DIR_TYPE_PCIE:
3924         case BNX_DIR_TYPE_TSCF_UCODE:
3925         case BNX_DIR_TYPE_EXT_PHY:
3926         case BNX_DIR_TYPE_CCM:
3927         case BNX_DIR_TYPE_ISCSI_BOOT:
3928         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3929         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3930                 /* FALLTHROUGH */
3931                 return true;
3932         }
3933
3934         return false;
3935 }
3936
3937 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3938 {
3939         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3940                 bnxt_dir_type_is_other_exec_format(dir_type);
3941 }
3942
3943 static int
3944 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3945                 struct rte_dev_eeprom_info *in_eeprom)
3946 {
3947         struct bnxt *bp = dev->data->dev_private;
3948         uint8_t index, dir_op;
3949         uint16_t type, ext, ordinal, attr;
3950         int rc;
3951
3952         rc = is_bnxt_in_error(bp);
3953         if (rc)
3954                 return rc;
3955
3956         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3957                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3958                     bp->pdev->addr.devid, bp->pdev->addr.function,
3959                     in_eeprom->offset, in_eeprom->length);
3960
3961         if (!BNXT_PF(bp)) {
3962                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3963                 return -EINVAL;
3964         }
3965
3966         type = in_eeprom->magic >> 16;
3967
3968         if (type == 0xffff) { /* special value for directory operations */
3969                 index = in_eeprom->magic & 0xff;
3970                 dir_op = in_eeprom->magic >> 8;
3971                 if (index == 0)
3972                         return -EINVAL;
3973                 switch (dir_op) {
3974                 case 0x0e: /* erase */
3975                         if (in_eeprom->offset != ~in_eeprom->magic)
3976                                 return -EINVAL;
3977                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3978                 default:
3979                         return -EINVAL;
3980                 }
3981         }
3982
3983         /* Create or re-write an NVM item: */
3984         if (bnxt_dir_type_is_executable(type) == true)
3985                 return -EOPNOTSUPP;
3986         ext = in_eeprom->magic & 0xffff;
3987         ordinal = in_eeprom->offset >> 16;
3988         attr = in_eeprom->offset & 0xffff;
3989
3990         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3991                                      in_eeprom->data, in_eeprom->length);
3992 }
3993
3994 /*
3995  * Initialization
3996  */
3997
3998 static const struct eth_dev_ops bnxt_dev_ops = {
3999         .dev_infos_get = bnxt_dev_info_get_op,
4000         .dev_close = bnxt_dev_close_op,
4001         .dev_configure = bnxt_dev_configure_op,
4002         .dev_start = bnxt_dev_start_op,
4003         .dev_stop = bnxt_dev_stop_op,
4004         .dev_set_link_up = bnxt_dev_set_link_up_op,
4005         .dev_set_link_down = bnxt_dev_set_link_down_op,
4006         .stats_get = bnxt_stats_get_op,
4007         .stats_reset = bnxt_stats_reset_op,
4008         .rx_queue_setup = bnxt_rx_queue_setup_op,
4009         .rx_queue_release = bnxt_rx_queue_release_op,
4010         .tx_queue_setup = bnxt_tx_queue_setup_op,
4011         .tx_queue_release = bnxt_tx_queue_release_op,
4012         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4013         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4014         .reta_update = bnxt_reta_update_op,
4015         .reta_query = bnxt_reta_query_op,
4016         .rss_hash_update = bnxt_rss_hash_update_op,
4017         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4018         .link_update = bnxt_link_update_op,
4019         .promiscuous_enable = bnxt_promiscuous_enable_op,
4020         .promiscuous_disable = bnxt_promiscuous_disable_op,
4021         .allmulticast_enable = bnxt_allmulticast_enable_op,
4022         .allmulticast_disable = bnxt_allmulticast_disable_op,
4023         .mac_addr_add = bnxt_mac_addr_add_op,
4024         .mac_addr_remove = bnxt_mac_addr_remove_op,
4025         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4026         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4027         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4028         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4029         .vlan_filter_set = bnxt_vlan_filter_set_op,
4030         .vlan_offload_set = bnxt_vlan_offload_set_op,
4031         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4032         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4033         .mtu_set = bnxt_mtu_set_op,
4034         .mac_addr_set = bnxt_set_default_mac_addr_op,
4035         .xstats_get = bnxt_dev_xstats_get_op,
4036         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4037         .xstats_reset = bnxt_dev_xstats_reset_op,
4038         .fw_version_get = bnxt_fw_version_get,
4039         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4040         .rxq_info_get = bnxt_rxq_info_get_op,
4041         .txq_info_get = bnxt_txq_info_get_op,
4042         .dev_led_on = bnxt_dev_led_on_op,
4043         .dev_led_off = bnxt_dev_led_off_op,
4044         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4045         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4046         .rx_queue_count = bnxt_rx_queue_count_op,
4047         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4048         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4049         .rx_queue_start = bnxt_rx_queue_start,
4050         .rx_queue_stop = bnxt_rx_queue_stop,
4051         .tx_queue_start = bnxt_tx_queue_start,
4052         .tx_queue_stop = bnxt_tx_queue_stop,
4053         .filter_ctrl = bnxt_filter_ctrl_op,
4054         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4055         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4056         .get_eeprom           = bnxt_get_eeprom_op,
4057         .set_eeprom           = bnxt_set_eeprom_op,
4058         .timesync_enable      = bnxt_timesync_enable,
4059         .timesync_disable     = bnxt_timesync_disable,
4060         .timesync_read_time   = bnxt_timesync_read_time,
4061         .timesync_write_time   = bnxt_timesync_write_time,
4062         .timesync_adjust_time = bnxt_timesync_adjust_time,
4063         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4064         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4065 };
4066
4067 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4068 {
4069         uint32_t offset;
4070
4071         /* Only pre-map the reset GRC registers using window 3 */
4072         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4073                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4074
4075         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4076
4077         return offset;
4078 }
4079
4080 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4081 {
4082         struct bnxt_error_recovery_info *info = bp->recovery_info;
4083         uint32_t reg_base = 0xffffffff;
4084         int i;
4085
4086         /* Only pre-map the monitoring GRC registers using window 2 */
4087         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4088                 uint32_t reg = info->status_regs[i];
4089
4090                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4091                         continue;
4092
4093                 if (reg_base == 0xffffffff)
4094                         reg_base = reg & 0xfffff000;
4095                 if ((reg & 0xfffff000) != reg_base)
4096                         return -ERANGE;
4097
4098                 /* Use mask 0xffc as the Lower 2 bits indicates
4099                  * address space location
4100                  */
4101                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4102                                                 (reg & 0xffc);
4103         }
4104
4105         if (reg_base == 0xffffffff)
4106                 return 0;
4107
4108         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4109                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4110
4111         return 0;
4112 }
4113
4114 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4115 {
4116         struct bnxt_error_recovery_info *info = bp->recovery_info;
4117         uint32_t delay = info->delay_after_reset[index];
4118         uint32_t val = info->reset_reg_val[index];
4119         uint32_t reg = info->reset_reg[index];
4120         uint32_t type, offset;
4121
4122         type = BNXT_FW_STATUS_REG_TYPE(reg);
4123         offset = BNXT_FW_STATUS_REG_OFF(reg);
4124
4125         switch (type) {
4126         case BNXT_FW_STATUS_REG_TYPE_CFG:
4127                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4128                 break;
4129         case BNXT_FW_STATUS_REG_TYPE_GRC:
4130                 offset = bnxt_map_reset_regs(bp, offset);
4131                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4132                 break;
4133         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4134                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4135                 break;
4136         }
4137         /* wait on a specific interval of time until core reset is complete */
4138         if (delay)
4139                 rte_delay_ms(delay);
4140 }
4141
4142 static void bnxt_dev_cleanup(struct bnxt *bp)
4143 {
4144         bnxt_set_hwrm_link_config(bp, false);
4145         bp->link_info.link_up = 0;
4146         if (bp->eth_dev->data->dev_started)
4147                 bnxt_dev_stop_op(bp->eth_dev);
4148
4149         bnxt_uninit_resources(bp, true);
4150 }
4151
4152 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4153 {
4154         struct rte_eth_dev *dev = bp->eth_dev;
4155         struct rte_vlan_filter_conf *vfc;
4156         int vidx, vbit, rc;
4157         uint16_t vlan_id;
4158
4159         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4160                 vfc = &dev->data->vlan_filter_conf;
4161                 vidx = vlan_id / 64;
4162                 vbit = vlan_id % 64;
4163
4164                 /* Each bit corresponds to a VLAN id */
4165                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4166                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4167                         if (rc)
4168                                 return rc;
4169                 }
4170         }
4171
4172         return 0;
4173 }
4174
4175 static int bnxt_restore_mac_filters(struct bnxt *bp)
4176 {
4177         struct rte_eth_dev *dev = bp->eth_dev;
4178         struct rte_eth_dev_info dev_info;
4179         struct rte_ether_addr *addr;
4180         uint64_t pool_mask;
4181         uint32_t pool = 0;
4182         uint16_t i;
4183         int rc;
4184
4185         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4186                 return 0;
4187
4188         rc = bnxt_dev_info_get_op(dev, &dev_info);
4189         if (rc)
4190                 return rc;
4191
4192         /* replay MAC address configuration */
4193         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4194                 addr = &dev->data->mac_addrs[i];
4195
4196                 /* skip zero address */
4197                 if (rte_is_zero_ether_addr(addr))
4198                         continue;
4199
4200                 pool = 0;
4201                 pool_mask = dev->data->mac_pool_sel[i];
4202
4203                 do {
4204                         if (pool_mask & 1ULL) {
4205                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4206                                 if (rc)
4207                                         return rc;
4208                         }
4209                         pool_mask >>= 1;
4210                         pool++;
4211                 } while (pool_mask);
4212         }
4213
4214         return 0;
4215 }
4216
4217 static int bnxt_restore_filters(struct bnxt *bp)
4218 {
4219         struct rte_eth_dev *dev = bp->eth_dev;
4220         int ret = 0;
4221
4222         if (dev->data->all_multicast) {
4223                 ret = bnxt_allmulticast_enable_op(dev);
4224                 if (ret)
4225                         return ret;
4226         }
4227         if (dev->data->promiscuous) {
4228                 ret = bnxt_promiscuous_enable_op(dev);
4229                 if (ret)
4230                         return ret;
4231         }
4232
4233         ret = bnxt_restore_mac_filters(bp);
4234         if (ret)
4235                 return ret;
4236
4237         ret = bnxt_restore_vlan_filters(bp);
4238         /* TODO restore other filters as well */
4239         return ret;
4240 }
4241
4242 static void bnxt_dev_recover(void *arg)
4243 {
4244         struct bnxt *bp = arg;
4245         int timeout = bp->fw_reset_max_msecs;
4246         int rc = 0;
4247
4248         /* Clear Error flag so that device re-init should happen */
4249         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4250
4251         do {
4252                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4253                 if (rc == 0)
4254                         break;
4255                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4256                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4257         } while (rc && timeout);
4258
4259         if (rc) {
4260                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4261                 goto err;
4262         }
4263
4264         rc = bnxt_init_resources(bp, true);
4265         if (rc) {
4266                 PMD_DRV_LOG(ERR,
4267                             "Failed to initialize resources after reset\n");
4268                 goto err;
4269         }
4270         /* clear reset flag as the device is initialized now */
4271         bp->flags &= ~BNXT_FLAG_FW_RESET;
4272
4273         rc = bnxt_dev_start_op(bp->eth_dev);
4274         if (rc) {
4275                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4276                 goto err_start;
4277         }
4278
4279         rc = bnxt_restore_filters(bp);
4280         if (rc)
4281                 goto err_start;
4282
4283         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4284         return;
4285 err_start:
4286         bnxt_dev_stop_op(bp->eth_dev);
4287 err:
4288         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4289         bnxt_uninit_resources(bp, false);
4290         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4291 }
4292
4293 void bnxt_dev_reset_and_resume(void *arg)
4294 {
4295         struct bnxt *bp = arg;
4296         int rc;
4297
4298         bnxt_dev_cleanup(bp);
4299
4300         bnxt_wait_for_device_shutdown(bp);
4301
4302         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4303                                bnxt_dev_recover, (void *)bp);
4304         if (rc)
4305                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4306 }
4307
4308 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4309 {
4310         struct bnxt_error_recovery_info *info = bp->recovery_info;
4311         uint32_t reg = info->status_regs[index];
4312         uint32_t type, offset, val = 0;
4313
4314         type = BNXT_FW_STATUS_REG_TYPE(reg);
4315         offset = BNXT_FW_STATUS_REG_OFF(reg);
4316
4317         switch (type) {
4318         case BNXT_FW_STATUS_REG_TYPE_CFG:
4319                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4320                 break;
4321         case BNXT_FW_STATUS_REG_TYPE_GRC:
4322                 offset = info->mapped_status_regs[index];
4323                 /* FALLTHROUGH */
4324         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4325                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4326                                        offset));
4327                 break;
4328         }
4329
4330         return val;
4331 }
4332
4333 static int bnxt_fw_reset_all(struct bnxt *bp)
4334 {
4335         struct bnxt_error_recovery_info *info = bp->recovery_info;
4336         uint32_t i;
4337         int rc = 0;
4338
4339         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4340                 /* Reset through master function driver */
4341                 for (i = 0; i < info->reg_array_cnt; i++)
4342                         bnxt_write_fw_reset_reg(bp, i);
4343                 /* Wait for time specified by FW after triggering reset */
4344                 rte_delay_ms(info->master_func_wait_period_after_reset);
4345         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4346                 /* Reset with the help of Kong processor */
4347                 rc = bnxt_hwrm_fw_reset(bp);
4348                 if (rc)
4349                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4350         }
4351
4352         return rc;
4353 }
4354
4355 static void bnxt_fw_reset_cb(void *arg)
4356 {
4357         struct bnxt *bp = arg;
4358         struct bnxt_error_recovery_info *info = bp->recovery_info;
4359         int rc = 0;
4360
4361         /* Only Master function can do FW reset */
4362         if (bnxt_is_master_func(bp) &&
4363             bnxt_is_recovery_enabled(bp)) {
4364                 rc = bnxt_fw_reset_all(bp);
4365                 if (rc) {
4366                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4367                         return;
4368                 }
4369         }
4370
4371         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4372          * EXCEPTION_FATAL_ASYNC event to all the functions
4373          * (including MASTER FUNC). After receiving this Async, all the active
4374          * drivers should treat this case as FW initiated recovery
4375          */
4376         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4377                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4378                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4379
4380                 /* To recover from error */
4381                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4382                                   (void *)bp);
4383         }
4384 }
4385
4386 /* Driver should poll FW heartbeat, reset_counter with the frequency
4387  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4388  * When the driver detects heartbeat stop or change in reset_counter,
4389  * it has to trigger a reset to recover from the error condition.
4390  * A “master PF” is the function who will have the privilege to
4391  * initiate the chimp reset. The master PF will be elected by the
4392  * firmware and will be notified through async message.
4393  */
4394 static void bnxt_check_fw_health(void *arg)
4395 {
4396         struct bnxt *bp = arg;
4397         struct bnxt_error_recovery_info *info = bp->recovery_info;
4398         uint32_t val = 0, wait_msec;
4399
4400         if (!info || !bnxt_is_recovery_enabled(bp) ||
4401             is_bnxt_in_error(bp))
4402                 return;
4403
4404         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4405         if (val == info->last_heart_beat)
4406                 goto reset;
4407
4408         info->last_heart_beat = val;
4409
4410         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4411         if (val != info->last_reset_counter)
4412                 goto reset;
4413
4414         info->last_reset_counter = val;
4415
4416         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4417                           bnxt_check_fw_health, (void *)bp);
4418
4419         return;
4420 reset:
4421         /* Stop DMA to/from device */
4422         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4423         bp->flags |= BNXT_FLAG_FW_RESET;
4424
4425         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4426
4427         if (bnxt_is_master_func(bp))
4428                 wait_msec = info->master_func_wait_period;
4429         else
4430                 wait_msec = info->normal_func_wait_period;
4431
4432         rte_eal_alarm_set(US_PER_MS * wait_msec,
4433                           bnxt_fw_reset_cb, (void *)bp);
4434 }
4435
4436 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4437 {
4438         uint32_t polling_freq;
4439
4440         if (!bnxt_is_recovery_enabled(bp))
4441                 return;
4442
4443         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4444                 return;
4445
4446         polling_freq = bp->recovery_info->driver_polling_freq;
4447
4448         rte_eal_alarm_set(US_PER_MS * polling_freq,
4449                           bnxt_check_fw_health, (void *)bp);
4450         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4451 }
4452
4453 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4454 {
4455         if (!bnxt_is_recovery_enabled(bp))
4456                 return;
4457
4458         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4459         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4460 }
4461
4462 static bool bnxt_vf_pciid(uint16_t device_id)
4463 {
4464         switch (device_id) {
4465         case BROADCOM_DEV_ID_57304_VF:
4466         case BROADCOM_DEV_ID_57406_VF:
4467         case BROADCOM_DEV_ID_5731X_VF:
4468         case BROADCOM_DEV_ID_5741X_VF:
4469         case BROADCOM_DEV_ID_57414_VF:
4470         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4471         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4472         case BROADCOM_DEV_ID_58802_VF:
4473         case BROADCOM_DEV_ID_57500_VF1:
4474         case BROADCOM_DEV_ID_57500_VF2:
4475                 /* FALLTHROUGH */
4476                 return true;
4477         default:
4478                 return false;
4479         }
4480 }
4481
4482 static bool bnxt_thor_device(uint16_t device_id)
4483 {
4484         switch (device_id) {
4485         case BROADCOM_DEV_ID_57508:
4486         case BROADCOM_DEV_ID_57504:
4487         case BROADCOM_DEV_ID_57502:
4488         case BROADCOM_DEV_ID_57508_MF1:
4489         case BROADCOM_DEV_ID_57504_MF1:
4490         case BROADCOM_DEV_ID_57502_MF1:
4491         case BROADCOM_DEV_ID_57508_MF2:
4492         case BROADCOM_DEV_ID_57504_MF2:
4493         case BROADCOM_DEV_ID_57502_MF2:
4494         case BROADCOM_DEV_ID_57500_VF1:
4495         case BROADCOM_DEV_ID_57500_VF2:
4496                 /* FALLTHROUGH */
4497                 return true;
4498         default:
4499                 return false;
4500         }
4501 }
4502
4503 bool bnxt_stratus_device(struct bnxt *bp)
4504 {
4505         uint16_t device_id = bp->pdev->id.device_id;
4506
4507         switch (device_id) {
4508         case BROADCOM_DEV_ID_STRATUS_NIC:
4509         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4510         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4511                 /* FALLTHROUGH */
4512                 return true;
4513         default:
4514                 return false;
4515         }
4516 }
4517
4518 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4519 {
4520         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4521         struct bnxt *bp = eth_dev->data->dev_private;
4522
4523         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4524         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4525         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4526         if (!bp->bar0 || !bp->doorbell_base) {
4527                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4528                 return -ENODEV;
4529         }
4530
4531         bp->eth_dev = eth_dev;
4532         bp->pdev = pci_dev;
4533
4534         return 0;
4535 }
4536
4537 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4538                                   struct bnxt_ctx_pg_info *ctx_pg,
4539                                   uint32_t mem_size,
4540                                   const char *suffix,
4541                                   uint16_t idx)
4542 {
4543         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4544         const struct rte_memzone *mz = NULL;
4545         char mz_name[RTE_MEMZONE_NAMESIZE];
4546         rte_iova_t mz_phys_addr;
4547         uint64_t valid_bits = 0;
4548         uint32_t sz;
4549         int i;
4550
4551         if (!mem_size)
4552                 return 0;
4553
4554         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4555                          BNXT_PAGE_SIZE;
4556         rmem->page_size = BNXT_PAGE_SIZE;
4557         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4558         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4559         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4560
4561         valid_bits = PTU_PTE_VALID;
4562
4563         if (rmem->nr_pages > 1) {
4564                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4565                          "bnxt_ctx_pg_tbl%s_%x_%d",
4566                          suffix, idx, bp->eth_dev->data->port_id);
4567                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4568                 mz = rte_memzone_lookup(mz_name);
4569                 if (!mz) {
4570                         mz = rte_memzone_reserve_aligned(mz_name,
4571                                                 rmem->nr_pages * 8,
4572                                                 SOCKET_ID_ANY,
4573                                                 RTE_MEMZONE_2MB |
4574                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4575                                                 RTE_MEMZONE_IOVA_CONTIG,
4576                                                 BNXT_PAGE_SIZE);
4577                         if (mz == NULL)
4578                                 return -ENOMEM;
4579                 }
4580
4581                 memset(mz->addr, 0, mz->len);
4582                 mz_phys_addr = mz->iova;
4583
4584                 rmem->pg_tbl = mz->addr;
4585                 rmem->pg_tbl_map = mz_phys_addr;
4586                 rmem->pg_tbl_mz = mz;
4587         }
4588
4589         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4590                  suffix, idx, bp->eth_dev->data->port_id);
4591         mz = rte_memzone_lookup(mz_name);
4592         if (!mz) {
4593                 mz = rte_memzone_reserve_aligned(mz_name,
4594                                                  mem_size,
4595                                                  SOCKET_ID_ANY,
4596                                                  RTE_MEMZONE_1GB |
4597                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4598                                                  RTE_MEMZONE_IOVA_CONTIG,
4599                                                  BNXT_PAGE_SIZE);
4600                 if (mz == NULL)
4601                         return -ENOMEM;
4602         }
4603
4604         memset(mz->addr, 0, mz->len);
4605         mz_phys_addr = mz->iova;
4606
4607         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4608                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4609                 rmem->dma_arr[i] = mz_phys_addr + sz;
4610
4611                 if (rmem->nr_pages > 1) {
4612                         if (i == rmem->nr_pages - 2 &&
4613                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4614                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4615                         else if (i == rmem->nr_pages - 1 &&
4616                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4617                                 valid_bits |= PTU_PTE_LAST;
4618
4619                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4620                                                            valid_bits);
4621                 }
4622         }
4623
4624         rmem->mz = mz;
4625         if (rmem->vmem_size)
4626                 rmem->vmem = (void **)mz->addr;
4627         rmem->dma_arr[0] = mz_phys_addr;
4628         return 0;
4629 }
4630
4631 static void bnxt_free_ctx_mem(struct bnxt *bp)
4632 {
4633         int i;
4634
4635         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4636                 return;
4637
4638         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4639         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4640         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4641         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4642         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4643         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4644         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4645         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4646         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4647         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4648         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4649
4650         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4651                 if (bp->ctx->tqm_mem[i])
4652                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4653         }
4654
4655         rte_free(bp->ctx);
4656         bp->ctx = NULL;
4657 }
4658
4659 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4660
4661 #define min_t(type, x, y) ({                    \
4662         type __min1 = (x);                      \
4663         type __min2 = (y);                      \
4664         __min1 < __min2 ? __min1 : __min2; })
4665
4666 #define max_t(type, x, y) ({                    \
4667         type __max1 = (x);                      \
4668         type __max2 = (y);                      \
4669         __max1 > __max2 ? __max1 : __max2; })
4670
4671 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4672
4673 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4674 {
4675         struct bnxt_ctx_pg_info *ctx_pg;
4676         struct bnxt_ctx_mem_info *ctx;
4677         uint32_t mem_size, ena, entries;
4678         uint32_t entries_sp, min;
4679         int i, rc;
4680
4681         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4682         if (rc) {
4683                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4684                 return rc;
4685         }
4686         ctx = bp->ctx;
4687         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4688                 return 0;
4689
4690         ctx_pg = &ctx->qp_mem;
4691         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4692         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4693         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4694         if (rc)
4695                 return rc;
4696
4697         ctx_pg = &ctx->srq_mem;
4698         ctx_pg->entries = ctx->srq_max_l2_entries;
4699         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4700         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4701         if (rc)
4702                 return rc;
4703
4704         ctx_pg = &ctx->cq_mem;
4705         ctx_pg->entries = ctx->cq_max_l2_entries;
4706         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4707         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4708         if (rc)
4709                 return rc;
4710
4711         ctx_pg = &ctx->vnic_mem;
4712         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4713                 ctx->vnic_max_ring_table_entries;
4714         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4715         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4716         if (rc)
4717                 return rc;
4718
4719         ctx_pg = &ctx->stat_mem;
4720         ctx_pg->entries = ctx->stat_max_entries;
4721         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4722         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4723         if (rc)
4724                 return rc;
4725
4726         min = ctx->tqm_min_entries_per_ring;
4727
4728         entries_sp = ctx->qp_max_l2_entries +
4729                      ctx->vnic_max_vnic_entries +
4730                      2 * ctx->qp_min_qp1_entries + min;
4731         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4732
4733         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4734         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4735         entries = clamp_t(uint32_t, entries, min,
4736                           ctx->tqm_max_entries_per_ring);
4737         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4738                 ctx_pg = ctx->tqm_mem[i];
4739                 ctx_pg->entries = i ? entries : entries_sp;
4740                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4741                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4742                 if (rc)
4743                         return rc;
4744                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4745         }
4746
4747         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4748         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4749         if (rc)
4750                 PMD_DRV_LOG(ERR,
4751                             "Failed to configure context mem: rc = %d\n", rc);
4752         else
4753                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4754
4755         return rc;
4756 }
4757
4758 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4759 {
4760         struct rte_pci_device *pci_dev = bp->pdev;
4761         char mz_name[RTE_MEMZONE_NAMESIZE];
4762         const struct rte_memzone *mz = NULL;
4763         uint32_t total_alloc_len;
4764         rte_iova_t mz_phys_addr;
4765
4766         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4767                 return 0;
4768
4769         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4770                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4771                  pci_dev->addr.bus, pci_dev->addr.devid,
4772                  pci_dev->addr.function, "rx_port_stats");
4773         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4774         mz = rte_memzone_lookup(mz_name);
4775         total_alloc_len =
4776                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4777                                        sizeof(struct rx_port_stats_ext) + 512);
4778         if (!mz) {
4779                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4780                                          SOCKET_ID_ANY,
4781                                          RTE_MEMZONE_2MB |
4782                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4783                                          RTE_MEMZONE_IOVA_CONTIG);
4784                 if (mz == NULL)
4785                         return -ENOMEM;
4786         }
4787         memset(mz->addr, 0, mz->len);
4788         mz_phys_addr = mz->iova;
4789
4790         bp->rx_mem_zone = (const void *)mz;
4791         bp->hw_rx_port_stats = mz->addr;
4792         bp->hw_rx_port_stats_map = mz_phys_addr;
4793
4794         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4795                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4796                  pci_dev->addr.bus, pci_dev->addr.devid,
4797                  pci_dev->addr.function, "tx_port_stats");
4798         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4799         mz = rte_memzone_lookup(mz_name);
4800         total_alloc_len =
4801                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4802                                        sizeof(struct tx_port_stats_ext) + 512);
4803         if (!mz) {
4804                 mz = rte_memzone_reserve(mz_name,
4805                                          total_alloc_len,
4806                                          SOCKET_ID_ANY,
4807                                          RTE_MEMZONE_2MB |
4808                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4809                                          RTE_MEMZONE_IOVA_CONTIG);
4810                 if (mz == NULL)
4811                         return -ENOMEM;
4812         }
4813         memset(mz->addr, 0, mz->len);
4814         mz_phys_addr = mz->iova;
4815
4816         bp->tx_mem_zone = (const void *)mz;
4817         bp->hw_tx_port_stats = mz->addr;
4818         bp->hw_tx_port_stats_map = mz_phys_addr;
4819         bp->flags |= BNXT_FLAG_PORT_STATS;
4820
4821         /* Display extended statistics if FW supports it */
4822         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4823             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4824             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4825                 return 0;
4826
4827         bp->hw_rx_port_stats_ext = (void *)
4828                 ((uint8_t *)bp->hw_rx_port_stats +
4829                  sizeof(struct rx_port_stats));
4830         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4831                 sizeof(struct rx_port_stats);
4832         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4833
4834         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4835             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4836                 bp->hw_tx_port_stats_ext = (void *)
4837                         ((uint8_t *)bp->hw_tx_port_stats +
4838                          sizeof(struct tx_port_stats));
4839                 bp->hw_tx_port_stats_ext_map =
4840                         bp->hw_tx_port_stats_map +
4841                         sizeof(struct tx_port_stats);
4842                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4843         }
4844
4845         return 0;
4846 }
4847
4848 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4849 {
4850         struct bnxt *bp = eth_dev->data->dev_private;
4851         int rc = 0;
4852
4853         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4854                                                RTE_ETHER_ADDR_LEN *
4855                                                bp->max_l2_ctx,
4856                                                0);
4857         if (eth_dev->data->mac_addrs == NULL) {
4858                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4859                 return -ENOMEM;
4860         }
4861
4862         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4863                 if (BNXT_PF(bp))
4864                         return -EINVAL;
4865
4866                 /* Generate a random MAC address, if none was assigned by PF */
4867                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4868                 bnxt_eth_hw_addr_random(bp->mac_addr);
4869                 PMD_DRV_LOG(INFO,
4870                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4871                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4872                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4873
4874                 rc = bnxt_hwrm_set_mac(bp);
4875                 if (!rc)
4876                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4877                                RTE_ETHER_ADDR_LEN);
4878                 return rc;
4879         }
4880
4881         /* Copy the permanent MAC from the FUNC_QCAPS response */
4882         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4883         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4884
4885         return rc;
4886 }
4887
4888 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4889 {
4890         int rc = 0;
4891
4892         /* MAC is already configured in FW */
4893         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4894                 return 0;
4895
4896         /* Restore the old MAC configured */
4897         rc = bnxt_hwrm_set_mac(bp);
4898         if (rc)
4899                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4900
4901         return rc;
4902 }
4903
4904 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4905 {
4906         if (!BNXT_PF(bp))
4907                 return;
4908
4909 #define ALLOW_FUNC(x)   \
4910         { \
4911                 uint32_t arg = (x); \
4912                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4913                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4914         }
4915
4916         /* Forward all requests if firmware is new enough */
4917         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4918              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4919             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4920                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4921         } else {
4922                 PMD_DRV_LOG(WARNING,
4923                             "Firmware too old for VF mailbox functionality\n");
4924                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4925         }
4926
4927         /*
4928          * The following are used for driver cleanup. If we disallow these,
4929          * VF drivers can't clean up cleanly.
4930          */
4931         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4932         ALLOW_FUNC(HWRM_VNIC_FREE);
4933         ALLOW_FUNC(HWRM_RING_FREE);
4934         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4935         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4936         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4937         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4938         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4939         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4940 }
4941
4942 uint16_t
4943 bnxt_get_svif(uint16_t port_id, bool func_svif)
4944 {
4945         struct rte_eth_dev *eth_dev;
4946         struct bnxt *bp;
4947
4948         eth_dev = &rte_eth_devices[port_id];
4949         bp = eth_dev->data->dev_private;
4950
4951         return func_svif ? bp->func_svif : bp->port_svif;
4952 }
4953
4954 uint16_t
4955 bnxt_get_vnic_id(uint16_t port)
4956 {
4957         struct rte_eth_dev *eth_dev;
4958         struct bnxt_vnic_info *vnic;
4959         struct bnxt *bp;
4960
4961         eth_dev = &rte_eth_devices[port];
4962         bp = eth_dev->data->dev_private;
4963
4964         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4965
4966         return vnic->fw_vnic_id;
4967 }
4968
4969 uint16_t
4970 bnxt_get_fw_func_id(uint16_t port)
4971 {
4972         struct rte_eth_dev *eth_dev;
4973         struct bnxt *bp;
4974
4975         eth_dev = &rte_eth_devices[port];
4976         bp = eth_dev->data->dev_private;
4977
4978         return bp->fw_fid;
4979 }
4980
4981 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4982 {
4983         struct bnxt_error_recovery_info *info = bp->recovery_info;
4984
4985         if (info) {
4986                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4987                         memset(info, 0, sizeof(*info));
4988                 return;
4989         }
4990
4991         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4992                 return;
4993
4994         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4995                            sizeof(*info), 0);
4996         if (!info)
4997                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4998
4999         bp->recovery_info = info;
5000 }
5001
5002 static void bnxt_check_fw_status(struct bnxt *bp)
5003 {
5004         uint32_t fw_status;
5005
5006         if (!(bp->recovery_info &&
5007               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5008                 return;
5009
5010         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5011         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5012                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5013                             fw_status);
5014 }
5015
5016 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5017 {
5018         struct bnxt_error_recovery_info *info = bp->recovery_info;
5019         uint32_t status_loc;
5020         uint32_t sig_ver;
5021
5022         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5023                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5024         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5025                                    BNXT_GRCP_WINDOW_2_BASE +
5026                                    offsetof(struct hcomm_status,
5027                                             sig_ver)));
5028         /* If the signature is absent, then FW does not support this feature */
5029         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5030             HCOMM_STATUS_SIGNATURE_VAL)
5031                 return 0;
5032
5033         if (!info) {
5034                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5035                                    sizeof(*info), 0);
5036                 if (!info)
5037                         return -ENOMEM;
5038                 bp->recovery_info = info;
5039         } else {
5040                 memset(info, 0, sizeof(*info));
5041         }
5042
5043         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5044                                       BNXT_GRCP_WINDOW_2_BASE +
5045                                       offsetof(struct hcomm_status,
5046                                                fw_status_loc)));
5047
5048         /* Only pre-map the FW health status GRC register */
5049         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5050                 return 0;
5051
5052         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5053         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5054                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5055
5056         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5057                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5058
5059         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5060
5061         return 0;
5062 }
5063
5064 static int bnxt_init_fw(struct bnxt *bp)
5065 {
5066         uint16_t mtu;
5067         int rc = 0;
5068
5069         bp->fw_cap = 0;
5070
5071         rc = bnxt_map_hcomm_fw_status_reg(bp);
5072         if (rc)
5073                 return rc;
5074
5075         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5076         if (rc) {
5077                 bnxt_check_fw_status(bp);
5078                 return rc;
5079         }
5080
5081         rc = bnxt_hwrm_func_reset(bp);
5082         if (rc)
5083                 return -EIO;
5084
5085         rc = bnxt_hwrm_vnic_qcaps(bp);
5086         if (rc)
5087                 return rc;
5088
5089         rc = bnxt_hwrm_queue_qportcfg(bp);
5090         if (rc)
5091                 return rc;
5092
5093         /* Get the MAX capabilities for this function.
5094          * This function also allocates context memory for TQM rings and
5095          * informs the firmware about this allocated backing store memory.
5096          */
5097         rc = bnxt_hwrm_func_qcaps(bp);
5098         if (rc)
5099                 return rc;
5100
5101         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5102         if (rc)
5103                 return rc;
5104
5105         bnxt_hwrm_port_mac_qcfg(bp);
5106
5107         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5108         if (rc)
5109                 return rc;
5110
5111         bnxt_alloc_error_recovery_info(bp);
5112         /* Get the adapter error recovery support info */
5113         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5114         if (rc)
5115                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5116
5117         bnxt_hwrm_port_led_qcaps(bp);
5118
5119         return 0;
5120 }
5121
5122 static int
5123 bnxt_init_locks(struct bnxt *bp)
5124 {
5125         int err;
5126
5127         err = pthread_mutex_init(&bp->flow_lock, NULL);
5128         if (err) {
5129                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5130                 return err;
5131         }
5132
5133         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5134         if (err)
5135                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5136         return err;
5137 }
5138
5139 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5140 {
5141         int rc;
5142
5143         rc = bnxt_init_fw(bp);
5144         if (rc)
5145                 return rc;
5146
5147         if (!reconfig_dev) {
5148                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5149                 if (rc)
5150                         return rc;
5151         } else {
5152                 rc = bnxt_restore_dflt_mac(bp);
5153                 if (rc)
5154                         return rc;
5155         }
5156
5157         bnxt_config_vf_req_fwd(bp);
5158
5159         rc = bnxt_hwrm_func_driver_register(bp);
5160         if (rc) {
5161                 PMD_DRV_LOG(ERR, "Failed to register driver");
5162                 return -EBUSY;
5163         }
5164
5165         if (BNXT_PF(bp)) {
5166                 if (bp->pdev->max_vfs) {
5167                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5168                         if (rc) {
5169                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5170                                 return rc;
5171                         }
5172                 } else {
5173                         rc = bnxt_hwrm_allocate_pf_only(bp);
5174                         if (rc) {
5175                                 PMD_DRV_LOG(ERR,
5176                                             "Failed to allocate PF resources");
5177                                 return rc;
5178                         }
5179                 }
5180         }
5181
5182         rc = bnxt_alloc_mem(bp, reconfig_dev);
5183         if (rc)
5184                 return rc;
5185
5186         rc = bnxt_setup_int(bp);
5187         if (rc)
5188                 return rc;
5189
5190         rc = bnxt_request_int(bp);
5191         if (rc)
5192                 return rc;
5193
5194         rc = bnxt_init_ctx_mem(bp);
5195         if (rc) {
5196                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5197                 return rc;
5198         }
5199
5200         rc = bnxt_init_locks(bp);
5201         if (rc)
5202                 return rc;
5203
5204         return 0;
5205 }
5206
5207 static int
5208 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5209                           const char *value, void *opaque_arg)
5210 {
5211         struct bnxt *bp = opaque_arg;
5212         unsigned long truflow;
5213         char *end = NULL;
5214
5215         if (!value || !opaque_arg) {
5216                 PMD_DRV_LOG(ERR,
5217                             "Invalid parameter passed to truflow devargs.\n");
5218                 return -EINVAL;
5219         }
5220
5221         truflow = strtoul(value, &end, 10);
5222         if (end == NULL || *end != '\0' ||
5223             (truflow == ULONG_MAX && errno == ERANGE)) {
5224                 PMD_DRV_LOG(ERR,
5225                             "Invalid parameter passed to truflow devargs.\n");
5226                 return -EINVAL;
5227         }
5228
5229         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5230                 PMD_DRV_LOG(ERR,
5231                             "Invalid value passed to truflow devargs.\n");
5232                 return -EINVAL;
5233         }
5234
5235         bp->truflow = truflow;
5236         if (bp->truflow)
5237                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5238
5239         return 0;
5240 }
5241
5242 static int
5243 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5244                              const char *value, void *opaque_arg)
5245 {
5246         struct bnxt *bp = opaque_arg;
5247         unsigned long flow_xstat;
5248         char *end = NULL;
5249
5250         if (!value || !opaque_arg) {
5251                 PMD_DRV_LOG(ERR,
5252                             "Invalid parameter passed to flow_xstat devarg.\n");
5253                 return -EINVAL;
5254         }
5255
5256         flow_xstat = strtoul(value, &end, 10);
5257         if (end == NULL || *end != '\0' ||
5258             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5259                 PMD_DRV_LOG(ERR,
5260                             "Invalid parameter passed to flow_xstat devarg.\n");
5261                 return -EINVAL;
5262         }
5263
5264         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5265                 PMD_DRV_LOG(ERR,
5266                             "Invalid value passed to flow_xstat devarg.\n");
5267                 return -EINVAL;
5268         }
5269
5270         bp->flow_xstat = flow_xstat;
5271         if (bp->flow_xstat)
5272                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5273
5274         return 0;
5275 }
5276
5277 static void
5278 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5279 {
5280         struct rte_kvargs *kvlist;
5281
5282         if (devargs == NULL)
5283                 return;
5284
5285         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5286         if (kvlist == NULL)
5287                 return;
5288
5289         /*
5290          * Handler for "truflow" devarg.
5291          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5292          */
5293         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5294                            bnxt_parse_devarg_truflow, bp);
5295
5296         /*
5297          * Handler for "flow_xstat" devarg.
5298          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5299          */
5300         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5301                            bnxt_parse_devarg_flow_xstat, bp);
5302
5303         rte_kvargs_free(kvlist);
5304 }
5305
5306 static int
5307 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5308 {
5309         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5310         static int version_printed;
5311         struct bnxt *bp;
5312         int rc;
5313
5314         if (version_printed++ == 0)
5315                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5316
5317         eth_dev->dev_ops = &bnxt_dev_ops;
5318         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5319         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5320
5321         /*
5322          * For secondary processes, we don't initialise any further
5323          * as primary has already done this work.
5324          */
5325         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5326                 return 0;
5327
5328         rte_eth_copy_pci_info(eth_dev, pci_dev);
5329
5330         bp = eth_dev->data->dev_private;
5331
5332         /* Parse dev arguments passed on when starting the DPDK application. */
5333         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5334
5335         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5336
5337         if (bnxt_vf_pciid(pci_dev->id.device_id))
5338                 bp->flags |= BNXT_FLAG_VF;
5339
5340         if (bnxt_thor_device(pci_dev->id.device_id))
5341                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5342
5343         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5344             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5345             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5346             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5347                 bp->flags |= BNXT_FLAG_STINGRAY;
5348
5349         rc = bnxt_init_board(eth_dev);
5350         if (rc) {
5351                 PMD_DRV_LOG(ERR,
5352                             "Failed to initialize board rc: %x\n", rc);
5353                 return rc;
5354         }
5355
5356         rc = bnxt_alloc_hwrm_resources(bp);
5357         if (rc) {
5358                 PMD_DRV_LOG(ERR,
5359                             "Failed to allocate hwrm resource rc: %x\n", rc);
5360                 goto error_free;
5361         }
5362         rc = bnxt_init_resources(bp, false);
5363         if (rc)
5364                 goto error_free;
5365
5366         rc = bnxt_alloc_stats_mem(bp);
5367         if (rc)
5368                 goto error_free;
5369
5370         /* Pass the information to the rte_eth_dev_close() that it should also
5371          * release the private port resources.
5372          */
5373         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5374
5375         PMD_DRV_LOG(INFO,
5376                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5377                     pci_dev->mem_resource[0].phys_addr,
5378                     pci_dev->mem_resource[0].addr);
5379
5380         return 0;
5381
5382 error_free:
5383         bnxt_dev_uninit(eth_dev);
5384         return rc;
5385 }
5386
5387
5388 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5389 {
5390         if (!ctx)
5391                 return;
5392
5393         if (ctx->va)
5394                 rte_free(ctx->va);
5395
5396         ctx->va = NULL;
5397         ctx->dma = RTE_BAD_IOVA;
5398         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5399 }
5400
5401 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5402 {
5403         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5404                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5405                                   bp->rx_fc_out_tbl.ctx_id,
5406                                   bp->max_fc,
5407                                   false);
5408
5409         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5410                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5411                                   bp->tx_fc_out_tbl.ctx_id,
5412                                   bp->max_fc,
5413                                   false);
5414
5415         if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5416                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5417         bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5418
5419         if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5420                 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5421         bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5422
5423         if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5424                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5425         bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5426
5427         if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5428                 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5429         bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5430 }
5431
5432 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5433 {
5434         bnxt_unregister_fc_ctx_mem(bp);
5435
5436         bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5437         bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5438         bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5439         bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5440 }
5441
5442 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5443 {
5444         bnxt_uninit_fc_ctx_mem(bp);
5445 }
5446
5447 static void
5448 bnxt_free_error_recovery_info(struct bnxt *bp)
5449 {
5450         rte_free(bp->recovery_info);
5451         bp->recovery_info = NULL;
5452         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5453 }
5454
5455 static void
5456 bnxt_uninit_locks(struct bnxt *bp)
5457 {
5458         pthread_mutex_destroy(&bp->flow_lock);
5459         pthread_mutex_destroy(&bp->def_cp_lock);
5460 }
5461
5462 static int
5463 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5464 {
5465         int rc;
5466
5467         bnxt_free_int(bp);
5468         bnxt_free_mem(bp, reconfig_dev);
5469         bnxt_hwrm_func_buf_unrgtr(bp);
5470         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5471         bp->flags &= ~BNXT_FLAG_REGISTERED;
5472         bnxt_free_ctx_mem(bp);
5473         if (!reconfig_dev) {
5474                 bnxt_free_hwrm_resources(bp);
5475                 bnxt_free_error_recovery_info(bp);
5476         }
5477
5478         bnxt_uninit_ctx_mem(bp);
5479
5480         bnxt_uninit_locks(bp);
5481         rte_free(bp->ptp_cfg);
5482         bp->ptp_cfg = NULL;
5483         return rc;
5484 }
5485
5486 static int
5487 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5488 {
5489         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5490                 return -EPERM;
5491
5492         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5493
5494         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5495                 bnxt_dev_close_op(eth_dev);
5496
5497         return 0;
5498 }
5499
5500 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5501         struct rte_pci_device *pci_dev)
5502 {
5503         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5504                 bnxt_dev_init);
5505 }
5506
5507 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5508 {
5509         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5510                 return rte_eth_dev_pci_generic_remove(pci_dev,
5511                                 bnxt_dev_uninit);
5512         else
5513                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5514 }
5515
5516 static struct rte_pci_driver bnxt_rte_pmd = {
5517         .id_table = bnxt_pci_id_map,
5518         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5519         .probe = bnxt_pci_probe,
5520         .remove = bnxt_pci_remove,
5521 };
5522
5523 static bool
5524 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5525 {
5526         if (strcmp(dev->device->driver->name, drv->driver.name))
5527                 return false;
5528
5529         return true;
5530 }
5531
5532 bool is_bnxt_supported(struct rte_eth_dev *dev)
5533 {
5534         return is_device_supported(dev, &bnxt_rte_pmd);
5535 }
5536
5537 RTE_INIT(bnxt_init_log)
5538 {
5539         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5540         if (bnxt_logtype_driver >= 0)
5541                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5542 }
5543
5544 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5545 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5546 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");