drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_58802 0xd802
  74 #define BROADCOM_DEV_ID_58804 0xd804
  75 #define BROADCOM_DEV_ID_58808 0x16f0
  76
  77 static const struct rte_pci_id bnxt_pci_id_map[] = {
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  79                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 119         { .vendor_id = 0, /* sentinel */ },
 120 };
 121
 122 #define BNXT_ETH_RSS_SUPPORT (  \
 123         ETH_RSS_IPV4 |          \
 124         ETH_RSS_NONFRAG_IPV4_TCP |      \
 125         ETH_RSS_NONFRAG_IPV4_UDP |      \
 126         ETH_RSS_IPV6 |          \
 127         ETH_RSS_NONFRAG_IPV6_TCP |      \
 128         ETH_RSS_NONFRAG_IPV6_UDP)
 129
 130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 131                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 132                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 133                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 134                                      DEV_TX_OFFLOAD_TCP_TSO | \
 135                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 136                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 137                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 138                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 139                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 141
 142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 143                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 144                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 146                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 149                                      DEV_RX_OFFLOAD_CRC_STRIP | \
 150                                      DEV_RX_OFFLOAD_TCP_LRO)
 151
 152 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 153 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 154 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static void bnxt_free_mem(struct bnxt *bp)
 163 {
 164         bnxt_free_filter_mem(bp);
 165         bnxt_free_vnic_attributes(bp);
 166         bnxt_free_vnic_mem(bp);
 167
 168         bnxt_free_stats(bp);
 169         bnxt_free_tx_rings(bp);
 170         bnxt_free_rx_rings(bp);
 171         bnxt_free_def_cp_ring(bp);
 172 }
 173
 174 static int bnxt_alloc_mem(struct bnxt *bp)
 175 {
 176         int rc;
 177
 178         /* Default completion ring */
 179         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 180         if (rc)
 181                 goto alloc_mem_err;
 182
 183         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 184                               bp->def_cp_ring, "def_cp");
 185         if (rc)
 186                 goto alloc_mem_err;
 187
 188         rc = bnxt_alloc_vnic_mem(bp);
 189         if (rc)
 190                 goto alloc_mem_err;
 191
 192         rc = bnxt_alloc_vnic_attributes(bp);
 193         if (rc)
 194                 goto alloc_mem_err;
 195
 196         rc = bnxt_alloc_filter_mem(bp);
 197         if (rc)
 198                 goto alloc_mem_err;
 199
 200         return 0;
 201
 202 alloc_mem_err:
 203         bnxt_free_mem(bp);
 204         return rc;
 205 }
 206
 207 static int bnxt_init_chip(struct bnxt *bp)
 208 {
 209         unsigned int i;
 210         struct rte_eth_link new;
 211         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 212         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 213         uint32_t intr_vector = 0;
 214         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 215         uint32_t vec = BNXT_MISC_VEC_ID;
 216         int rc;
 217
 218         /* disable uio/vfio intr/eventfd mapping */
 219         rte_intr_disable(intr_handle);
 220
 221         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 222                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 223                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 224                 bp->flags |= BNXT_FLAG_JUMBO;
 225         } else {
 226                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 227                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 228                 bp->flags &= ~BNXT_FLAG_JUMBO;
 229         }
 230
 231         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 232         if (rc) {
 233                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 234                 goto err_out;
 235         }
 236
 237         rc = bnxt_alloc_hwrm_rings(bp);
 238         if (rc) {
 239                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 240                 goto err_out;
 241         }
 242
 243         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 244         if (rc) {
 245                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 246                 goto err_out;
 247         }
 248
 249         rc = bnxt_mq_rx_configure(bp);
 250         if (rc) {
 251                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 252                 goto err_out;
 253         }
 254
 255         /* VNIC configuration */
 256         for (i = 0; i < bp->nr_vnics; i++) {
 257                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 258
 259                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 260                 if (rc) {
 261                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 262                                 i, rc);
 263                         goto err_out;
 264                 }
 265
 266                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 267                 if (rc) {
 268                         PMD_DRV_LOG(ERR,
 269                                 "HWRM vnic %d ctx alloc failure rc: %x\n",
 270                                 i, rc);
 271                         goto err_out;
 272                 }
 273
 274                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 275                 if (rc) {
 276                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 277                                 i, rc);
 278                         goto err_out;
 279                 }
 280
 281                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 282                 if (rc) {
 283                         PMD_DRV_LOG(ERR,
 284                                 "HWRM vnic %d filter failure rc: %x\n",
 285                                 i, rc);
 286                         goto err_out;
 287                 }
 288
 289                 rc = bnxt_vnic_rss_configure(bp, vnic);
 290                 if (rc) {
 291                         PMD_DRV_LOG(ERR,
 292                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 293                         goto err_out;
 294                 }
 295
 296                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 297
 298                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 299                     DEV_RX_OFFLOAD_TCP_LRO)
 300                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 301                 else
 302                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 303         }
 304         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 305         if (rc) {
 306                 PMD_DRV_LOG(ERR,
 307                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         /* check and configure queue intr-vector mapping */
 312         if ((rte_intr_cap_multiple(intr_handle) ||
 313              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 314             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 315                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 316                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 317                 if (intr_vector > bp->rx_cp_nr_rings) {
 318                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 319                                         bp->rx_cp_nr_rings);
 320                         return -ENOTSUP;
 321                 }
 322                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 323                         return -1;
 324         }
 325
 326         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 327                 intr_handle->intr_vec =
 328                         rte_zmalloc("intr_vec",
 329                                     bp->eth_dev->data->nb_rx_queues *
 330                                     sizeof(int), 0);
 331                 if (intr_handle->intr_vec == NULL) {
 332                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 333                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 334                         return -ENOMEM;
 335                 }
 336                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 337                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 338                          intr_handle->intr_vec, intr_handle->nb_efd,
 339                         intr_handle->max_intr);
 340         }
 341
 342         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 343              queue_id++) {
 344                 intr_handle->intr_vec[queue_id] = vec;
 345                 if (vec < base + intr_handle->nb_efd - 1)
 346                         vec++;
 347         }
 348
 349         /* enable uio/vfio intr/eventfd mapping */
 350         rte_intr_enable(intr_handle);
 351
 352         rc = bnxt_get_hwrm_link_config(bp, &new);
 353         if (rc) {
 354                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 355                 goto err_out;
 356         }
 357
 358         if (!bp->link_info.link_up) {
 359                 rc = bnxt_set_hwrm_link_config(bp, true);
 360                 if (rc) {
 361                         PMD_DRV_LOG(ERR,
 362                                 "HWRM link config failure rc: %x\n", rc);
 363                         goto err_out;
 364                 }
 365         }
 366         bnxt_print_link_info(bp->eth_dev);
 367
 368         return 0;
 369
 370 err_out:
 371         bnxt_free_all_hwrm_resources(bp);
 372
 373         /* Some of the error status returned by FW may not be from errno.h */
 374         if (rc > 0)
 375                 rc = -EIO;
 376
 377         return rc;
 378 }
 379
 380 static int bnxt_shutdown_nic(struct bnxt *bp)
 381 {
 382         bnxt_free_all_hwrm_resources(bp);
 383         bnxt_free_all_filters(bp);
 384         bnxt_free_all_vnics(bp);
 385         return 0;
 386 }
 387
 388 static int bnxt_init_nic(struct bnxt *bp)
 389 {
 390         int rc;
 391
 392         rc = bnxt_init_ring_grps(bp);
 393         if (rc)
 394                 return rc;
 395
 396         bnxt_init_vnics(bp);
 397         bnxt_init_filters(bp);
 398
 399         return 0;
 400 }
 401
 402 /*
 403  * Device configuration and status function
 404  */
 405
 406 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 407                                   struct rte_eth_dev_info *dev_info)
 408 {
 409         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 410         uint16_t max_vnics, i, j, vpool, vrxq;
 411         unsigned int max_rx_rings;
 412
 413         /* MAC Specifics */
 414         dev_info->max_mac_addrs = bp->max_l2_ctx;
 415         dev_info->max_hash_mac_addrs = 0;
 416
 417         /* PF/VF specifics */
 418         if (BNXT_PF(bp))
 419                 dev_info->max_vfs = bp->pdev->max_vfs;
 420         max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
 421                                                 RTE_MIN(bp->max_rsscos_ctx,
 422                                                 bp->max_stat_ctx)));
 423         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 424         dev_info->max_rx_queues = max_rx_rings;
 425         dev_info->max_tx_queues = max_rx_rings;
 426         dev_info->reta_size = bp->max_rsscos_ctx;
 427         dev_info->hash_key_size = 40;
 428         max_vnics = bp->max_vnics;
 429
 430         /* Fast path specifics */
 431         dev_info->min_rx_bufsize = 1;
 432         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 433                                   + VLAN_TAG_SIZE;
 434
 435         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 436         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 437                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 438         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 439         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 440
 441         /* *INDENT-OFF* */
 442         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 443                 .rx_thresh = {
 444                         .pthresh = 8,
 445                         .hthresh = 8,
 446                         .wthresh = 0,
 447                 },
 448                 .rx_free_thresh = 32,
 449                 /* If no descriptors available, pkts are dropped by default */
 450                 .rx_drop_en = 1,
 451         };
 452
 453         dev_info->default_txconf = (struct rte_eth_txconf) {
 454                 .tx_thresh = {
 455                         .pthresh = 32,
 456                         .hthresh = 0,
 457                         .wthresh = 0,
 458                 },
 459                 .tx_free_thresh = 32,
 460                 .tx_rs_thresh = 32,
 461         };
 462         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 463
 464         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 465
 466         /* *INDENT-ON* */
 467
 468         /*
 469          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 470          *       need further investigation.
 471          */
 472
 473         /* VMDq resources */
 474         vpool = 64; /* ETH_64_POOLS */
 475         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 476         for (i = 0; i < 4; vpool >>= 1, i++) {
 477                 if (max_vnics > vpool) {
 478                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 479                                 if (dev_info->max_rx_queues > vrxq) {
 480                                         if (vpool > vrxq)
 481                                                 vpool = vrxq;
 482                                         goto found;
 483                                 }
 484                         }
 485                         /* Not enough resources to support VMDq */
 486                         break;
 487                 }
 488         }
 489         /* Not enough resources to support VMDq */
 490         vpool = 0;
 491         vrxq = 0;
 492 found:
 493         dev_info->max_vmdq_pools = vpool;
 494         dev_info->vmdq_queue_num = vrxq;
 495
 496         dev_info->vmdq_pool_base = 0;
 497         dev_info->vmdq_queue_base = 0;
 498 }
 499
 500 /* Configure the device based on the configuration provided */
 501 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 502 {
 503         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 504         uint64_t tx_offloads = eth_dev->data->dev_conf.txmode.offloads;
 505         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 506
 507         if (tx_offloads != (tx_offloads & BNXT_DEV_TX_OFFLOAD_SUPPORT)) {
 508                 PMD_DRV_LOG
 509                         (ERR,
 510                          "Tx offloads requested 0x%" PRIx64 " supported 0x%x\n",
 511                          tx_offloads, BNXT_DEV_TX_OFFLOAD_SUPPORT);
 512                 return -ENOTSUP;
 513         }
 514
 515         if (rx_offloads != (rx_offloads & BNXT_DEV_RX_OFFLOAD_SUPPORT)) {
 516                 PMD_DRV_LOG
 517                         (ERR,
 518                          "Rx offloads requested 0x%" PRIx64 " supported 0x%x\n",
 519                             rx_offloads, BNXT_DEV_RX_OFFLOAD_SUPPORT);
 520                 return -ENOTSUP;
 521         }
 522
 523         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 524         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 525
 526         /* Inherit new configurations */
 527         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 528             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 529             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
 530             bp->max_cp_rings ||
 531             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 532             bp->max_stat_ctx ||
 533             (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
 534                 PMD_DRV_LOG(ERR,
 535                         "Insufficient resources to support requested config\n");
 536                 PMD_DRV_LOG(ERR,
 537                         "Num Queues Requested: Tx %d, Rx %d\n",
 538                         eth_dev->data->nb_tx_queues,
 539                         eth_dev->data->nb_rx_queues);
 540                 PMD_DRV_LOG(ERR,
 541                         "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
 542                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 543                         bp->max_stat_ctx, bp->max_ring_grps);
 544                 return -ENOSPC;
 545         }
 546
 547         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 548         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 549         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 550         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 551
 552         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 553                 eth_dev->data->mtu =
 554                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 555                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
 556                                 BNXT_NUM_VLANS;
 557                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 558         }
 559         return 0;
 560 }
 561
 562 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 563 {
 564         struct rte_eth_link *link = &eth_dev->data->dev_link;
 565
 566         if (link->link_status)
 567                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 568                         eth_dev->data->port_id,
 569                         (uint32_t)link->link_speed,
 570                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 571                         ("full-duplex") : ("half-duplex\n"));
 572         else
 573                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 574                         eth_dev->data->port_id);
 575 }
 576
 577 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 578 {
 579         bnxt_print_link_info(eth_dev);
 580         return 0;
 581 }
 582
 583 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 584 {
 585         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 586         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 587         int vlan_mask = 0;
 588         int rc;
 589
 590         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 591                 PMD_DRV_LOG(ERR,
 592                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 593                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 594         }
 595         bp->dev_stopped = 0;
 596
 597         rc = bnxt_init_chip(bp);
 598         if (rc)
 599                 goto error;
 600
 601         bnxt_link_update_op(eth_dev, 1);
 602
 603         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 604                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 605         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 606                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 607         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 608         if (rc)
 609                 goto error;
 610
 611         bp->flags |= BNXT_FLAG_INIT_DONE;
 612         return 0;
 613
 614 error:
 615         bnxt_shutdown_nic(bp);
 616         bnxt_free_tx_mbufs(bp);
 617         bnxt_free_rx_mbufs(bp);
 618         return rc;
 619 }
 620
 621 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 622 {
 623         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 624         int rc = 0;
 625
 626         if (!bp->link_info.link_up)
 627                 rc = bnxt_set_hwrm_link_config(bp, true);
 628         if (!rc)
 629                 eth_dev->data->dev_link.link_status = 1;
 630
 631         bnxt_print_link_info(eth_dev);
 632         return 0;
 633 }
 634
 635 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 636 {
 637         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 638
 639         eth_dev->data->dev_link.link_status = 0;
 640         bnxt_set_hwrm_link_config(bp, false);
 641         bp->link_info.link_up = 0;
 642
 643         return 0;
 644 }
 645
 646 /* Unload the driver, release resources */
 647 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 648 {
 649         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 650
 651         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 652         if (bp->eth_dev->data->dev_started) {
 653                 /* TBD: STOP HW queues DMA */
 654                 eth_dev->data->dev_link.link_status = 0;
 655         }
 656         bnxt_set_hwrm_link_config(bp, false);
 657         bnxt_hwrm_port_clr_stats(bp);
 658         bnxt_shutdown_nic(bp);
 659         bp->dev_stopped = 1;
 660 }
 661
 662 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 663 {
 664         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 665
 666         if (bp->dev_stopped == 0)
 667                 bnxt_dev_stop_op(eth_dev);
 668
 669         bnxt_free_tx_mbufs(bp);
 670         bnxt_free_rx_mbufs(bp);
 671         bnxt_free_mem(bp);
 672         if (eth_dev->data->mac_addrs != NULL) {
 673                 rte_free(eth_dev->data->mac_addrs);
 674                 eth_dev->data->mac_addrs = NULL;
 675         }
 676         if (bp->grp_info != NULL) {
 677                 rte_free(bp->grp_info);
 678                 bp->grp_info = NULL;
 679         }
 680 }
 681
 682 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 683                                     uint32_t index)
 684 {
 685         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 686         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 687         struct bnxt_vnic_info *vnic;
 688         struct bnxt_filter_info *filter, *temp_filter;
 689         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 690         uint32_t i;
 691
 692         /*
 693          * Loop through all VNICs from the specified filter flow pools to
 694          * remove the corresponding MAC addr filter
 695          */
 696         for (i = 0; i < pool; i++) {
 697                 if (!(pool_mask & (1ULL << i)))
 698                         continue;
 699
 700                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 701                         filter = STAILQ_FIRST(&vnic->filter);
 702                         while (filter) {
 703                                 temp_filter = STAILQ_NEXT(filter, next);
 704                                 if (filter->mac_index == index) {
 705                                         STAILQ_REMOVE(&vnic->filter, filter,
 706                                                       bnxt_filter_info, next);
 707                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 708                                         filter->mac_index = INVALID_MAC_INDEX;
 709                                         memset(&filter->l2_addr, 0,
 710                                                ETHER_ADDR_LEN);
 711                                         STAILQ_INSERT_TAIL(
 712                                                         &bp->free_filter_list,
 713                                                         filter, next);
 714                                 }
 715                                 filter = temp_filter;
 716                         }
 717                 }
 718         }
 719 }
 720
 721 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 722                                 struct ether_addr *mac_addr,
 723                                 uint32_t index, uint32_t pool)
 724 {
 725         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 726         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 727         struct bnxt_filter_info *filter;
 728
 729         if (BNXT_VF(bp)) {
 730                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 731                 return -ENOTSUP;
 732         }
 733
 734         if (!vnic) {
 735                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 736                 return -EINVAL;
 737         }
 738         /* Attach requested MAC address to the new l2_filter */
 739         STAILQ_FOREACH(filter, &vnic->filter, next) {
 740                 if (filter->mac_index == index) {
 741                         PMD_DRV_LOG(ERR,
 742                                 "MAC addr already existed for pool %d\n", pool);
 743                         return 0;
 744                 }
 745         }
 746         filter = bnxt_alloc_filter(bp);
 747         if (!filter) {
 748                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 749                 return -ENODEV;
 750         }
 751         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 752         filter->mac_index = index;
 753         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 754         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 755 }
 756
 757 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 758 {
 759         int rc = 0;
 760         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 761         struct rte_eth_link new;
 762         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 763
 764         memset(&new, 0, sizeof(new));
 765         do {
 766                 /* Retrieve link info from hardware */
 767                 rc = bnxt_get_hwrm_link_config(bp, &new);
 768                 if (rc) {
 769                         new.link_speed = ETH_LINK_SPEED_100M;
 770                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 771                         PMD_DRV_LOG(ERR,
 772                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 773                         goto out;
 774                 }
 775                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 776
 777                 if (!wait_to_complete)
 778                         break;
 779         } while (!new.link_status && cnt--);
 780
 781 out:
 782         /* Timed out or success */
 783         if (new.link_status != eth_dev->data->dev_link.link_status ||
 784         new.link_speed != eth_dev->data->dev_link.link_speed) {
 785                 memcpy(&eth_dev->data->dev_link, &new,
 786                         sizeof(struct rte_eth_link));
 787
 788                 _rte_eth_dev_callback_process(eth_dev,
 789                                               RTE_ETH_EVENT_INTR_LSC,
 790                                               NULL);
 791
 792                 bnxt_print_link_info(eth_dev);
 793         }
 794
 795         return rc;
 796 }
 797
 798 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 799 {
 800         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 801         struct bnxt_vnic_info *vnic;
 802
 803         if (bp->vnic_info == NULL)
 804                 return;
 805
 806         vnic = &bp->vnic_info[0];
 807
 808         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 809         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 810 }
 811
 812 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 813 {
 814         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 815         struct bnxt_vnic_info *vnic;
 816
 817         if (bp->vnic_info == NULL)
 818                 return;
 819
 820         vnic = &bp->vnic_info[0];
 821
 822         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 823         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 824 }
 825
 826 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 827 {
 828         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 829         struct bnxt_vnic_info *vnic;
 830
 831         if (bp->vnic_info == NULL)
 832                 return;
 833
 834         vnic = &bp->vnic_info[0];
 835
 836         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 837         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 838 }
 839
 840 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 841 {
 842         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 843         struct bnxt_vnic_info *vnic;
 844
 845         if (bp->vnic_info == NULL)
 846                 return;
 847
 848         vnic = &bp->vnic_info[0];
 849
 850         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 851         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 852 }
 853
 854 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 855                             struct rte_eth_rss_reta_entry64 *reta_conf,
 856                             uint16_t reta_size)
 857 {
 858         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 859         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 860         struct bnxt_vnic_info *vnic;
 861         int i;
 862
 863         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 864                 return -EINVAL;
 865
 866         if (reta_size != HW_HASH_INDEX_SIZE) {
 867                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 868                         "(%d) must equal the size supported by the hardware "
 869                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 870                 return -EINVAL;
 871         }
 872         /* Update the RSS VNIC(s) */
 873         for (i = 0; i < MAX_FF_POOLS; i++) {
 874                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 875                         memcpy(vnic->rss_table, reta_conf, reta_size);
 876
 877                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 878                 }
 879         }
 880         return 0;
 881 }
 882
 883 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 884                               struct rte_eth_rss_reta_entry64 *reta_conf,
 885                               uint16_t reta_size)
 886 {
 887         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 888         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 889         struct rte_intr_handle *intr_handle
 890                 = &bp->pdev->intr_handle;
 891
 892         /* Retrieve from the default VNIC */
 893         if (!vnic)
 894                 return -EINVAL;
 895         if (!vnic->rss_table)
 896                 return -EINVAL;
 897
 898         if (reta_size != HW_HASH_INDEX_SIZE) {
 899                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 900                         "(%d) must equal the size supported by the hardware "
 901                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 902                 return -EINVAL;
 903         }
 904         /* EW - need to revisit here copying from uint64_t to uint16_t */
 905         memcpy(reta_conf, vnic->rss_table, reta_size);
 906
 907         if (rte_intr_allow_others(intr_handle)) {
 908                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 909                         bnxt_dev_lsc_intr_setup(eth_dev);
 910         }
 911
 912         return 0;
 913 }
 914
 915 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 916                                    struct rte_eth_rss_conf *rss_conf)
 917 {
 918         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 919         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 920         struct bnxt_vnic_info *vnic;
 921         uint16_t hash_type = 0;
 922         int i;
 923
 924         /*
 925          * If RSS enablement were different than dev_configure,
 926          * then return -EINVAL
 927          */
 928         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 929                 if (!rss_conf->rss_hf)
 930                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 931         } else {
 932                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 933                         return -EINVAL;
 934         }
 935
 936         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 937         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 938
 939         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 940                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 941         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 942                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 943         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 944                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 945         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 946                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 947         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 948                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 949         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 950                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 951
 952         /* Update the RSS VNIC(s) */
 953         for (i = 0; i < MAX_FF_POOLS; i++) {
 954                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 955                         vnic->hash_type = hash_type;
 956
 957                         /*
 958                          * Use the supplied key if the key length is
 959                          * acceptable and the rss_key is not NULL
 960                          */
 961                         if (rss_conf->rss_key &&
 962                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 963                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 964                                        rss_conf->rss_key_len);
 965
 966                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 967                 }
 968         }
 969         return 0;
 970 }
 971
 972 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 973                                      struct rte_eth_rss_conf *rss_conf)
 974 {
 975         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 976         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 977         int len;
 978         uint32_t hash_types;
 979
 980         /* RSS configuration is the same for all VNICs */
 981         if (vnic && vnic->rss_hash_key) {
 982                 if (rss_conf->rss_key) {
 983                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 984                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 985                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 986                 }
 987
 988                 hash_types = vnic->hash_type;
 989                 rss_conf->rss_hf = 0;
 990                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 991                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 992                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 993                 }
 994                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 995                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 996                         hash_types &=
 997                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 998                 }
 999                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1000                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1001                         hash_types &=
1002                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1003                 }
1004                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1005                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1006                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1007                 }
1008                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1009                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1010                         hash_types &=
1011                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1012                 }
1013                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1014                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1015                         hash_types &=
1016                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1017                 }
1018                 if (hash_types) {
1019                         PMD_DRV_LOG(ERR,
1020                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1021                                 vnic->hash_type);
1022                         return -ENOTSUP;
1023                 }
1024         } else {
1025                 rss_conf->rss_hf = 0;
1026         }
1027         return 0;
1028 }
1029
1030 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1031                                struct rte_eth_fc_conf *fc_conf)
1032 {
1033         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1034         struct rte_eth_link link_info;
1035         int rc;
1036
1037         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1038         if (rc)
1039                 return rc;
1040
1041         memset(fc_conf, 0, sizeof(*fc_conf));
1042         if (bp->link_info.auto_pause)
1043                 fc_conf->autoneg = 1;
1044         switch (bp->link_info.pause) {
1045         case 0:
1046                 fc_conf->mode = RTE_FC_NONE;
1047                 break;
1048         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1049                 fc_conf->mode = RTE_FC_TX_PAUSE;
1050                 break;
1051         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1052                 fc_conf->mode = RTE_FC_RX_PAUSE;
1053                 break;
1054         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1055                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1056                 fc_conf->mode = RTE_FC_FULL;
1057                 break;
1058         }
1059         return 0;
1060 }
1061
1062 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1063                                struct rte_eth_fc_conf *fc_conf)
1064 {
1065         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1066
1067         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1068                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1069                 return -ENOTSUP;
1070         }
1071
1072         switch (fc_conf->mode) {
1073         case RTE_FC_NONE:
1074                 bp->link_info.auto_pause = 0;
1075                 bp->link_info.force_pause = 0;
1076                 break;
1077         case RTE_FC_RX_PAUSE:
1078                 if (fc_conf->autoneg) {
1079                         bp->link_info.auto_pause =
1080                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1081                         bp->link_info.force_pause = 0;
1082                 } else {
1083                         bp->link_info.auto_pause = 0;
1084                         bp->link_info.force_pause =
1085                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1086                 }
1087                 break;
1088         case RTE_FC_TX_PAUSE:
1089                 if (fc_conf->autoneg) {
1090                         bp->link_info.auto_pause =
1091                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1092                         bp->link_info.force_pause = 0;
1093                 } else {
1094                         bp->link_info.auto_pause = 0;
1095                         bp->link_info.force_pause =
1096                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1097                 }
1098                 break;
1099         case RTE_FC_FULL:
1100                 if (fc_conf->autoneg) {
1101                         bp->link_info.auto_pause =
1102                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1103                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1104                         bp->link_info.force_pause = 0;
1105                 } else {
1106                         bp->link_info.auto_pause = 0;
1107                         bp->link_info.force_pause =
1108                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1109                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1110                 }
1111                 break;
1112         }
1113         return bnxt_set_hwrm_link_config(bp, true);
1114 }
1115
1116 /* Add UDP tunneling port */
1117 static int
1118 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1119                          struct rte_eth_udp_tunnel *udp_tunnel)
1120 {
1121         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1122         uint16_t tunnel_type = 0;
1123         int rc = 0;
1124
1125         switch (udp_tunnel->prot_type) {
1126         case RTE_TUNNEL_TYPE_VXLAN:
1127                 if (bp->vxlan_port_cnt) {
1128                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1129                                 udp_tunnel->udp_port);
1130                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1131                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1132                                 return -ENOSPC;
1133                         }
1134                         bp->vxlan_port_cnt++;
1135                         return 0;
1136                 }
1137                 tunnel_type =
1138                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1139                 bp->vxlan_port_cnt++;
1140                 break;
1141         case RTE_TUNNEL_TYPE_GENEVE:
1142                 if (bp->geneve_port_cnt) {
1143                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1144                                 udp_tunnel->udp_port);
1145                         if (bp->geneve_port != udp_tunnel->udp_port) {
1146                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1147                                 return -ENOSPC;
1148                         }
1149                         bp->geneve_port_cnt++;
1150                         return 0;
1151                 }
1152                 tunnel_type =
1153                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1154                 bp->geneve_port_cnt++;
1155                 break;
1156         default:
1157                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1158                 return -ENOTSUP;
1159         }
1160         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1161                                              tunnel_type);
1162         return rc;
1163 }
1164
1165 static int
1166 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1167                          struct rte_eth_udp_tunnel *udp_tunnel)
1168 {
1169         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1170         uint16_t tunnel_type = 0;
1171         uint16_t port = 0;
1172         int rc = 0;
1173
1174         switch (udp_tunnel->prot_type) {
1175         case RTE_TUNNEL_TYPE_VXLAN:
1176                 if (!bp->vxlan_port_cnt) {
1177                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1178                         return -EINVAL;
1179                 }
1180                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1181                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1182                                 udp_tunnel->udp_port, bp->vxlan_port);
1183                         return -EINVAL;
1184                 }
1185                 if (--bp->vxlan_port_cnt)
1186                         return 0;
1187
1188                 tunnel_type =
1189                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1190                 port = bp->vxlan_fw_dst_port_id;
1191                 break;
1192         case RTE_TUNNEL_TYPE_GENEVE:
1193                 if (!bp->geneve_port_cnt) {
1194                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1195                         return -EINVAL;
1196                 }
1197                 if (bp->geneve_port != udp_tunnel->udp_port) {
1198                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1199                                 udp_tunnel->udp_port, bp->geneve_port);
1200                         return -EINVAL;
1201                 }
1202                 if (--bp->geneve_port_cnt)
1203                         return 0;
1204
1205                 tunnel_type =
1206                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1207                 port = bp->geneve_fw_dst_port_id;
1208                 break;
1209         default:
1210                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1211                 return -ENOTSUP;
1212         }
1213
1214         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1215         if (!rc) {
1216                 if (tunnel_type ==
1217                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1218                         bp->vxlan_port = 0;
1219                 if (tunnel_type ==
1220                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1221                         bp->geneve_port = 0;
1222         }
1223         return rc;
1224 }
1225
1226 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1227 {
1228         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1229         struct bnxt_vnic_info *vnic;
1230         unsigned int i;
1231         int rc = 0;
1232         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1233
1234         /* Cycle through all VNICs */
1235         for (i = 0; i < bp->nr_vnics; i++) {
1236                 /*
1237                  * For each VNIC and each associated filter(s)
1238                  * if VLAN exists && VLAN matches vlan_id
1239                  *      remove the MAC+VLAN filter
1240                  *      add a new MAC only filter
1241                  * else
1242                  *      VLAN filter doesn't exist, just skip and continue
1243                  */
1244                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1245                         filter = STAILQ_FIRST(&vnic->filter);
1246                         while (filter) {
1247                                 temp_filter = STAILQ_NEXT(filter, next);
1248
1249                                 if (filter->enables & chk &&
1250                                     filter->l2_ovlan == vlan_id) {
1251                                         /* Must delete the filter */
1252                                         STAILQ_REMOVE(&vnic->filter, filter,
1253                                                       bnxt_filter_info, next);
1254                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1255                                         STAILQ_INSERT_TAIL(
1256                                                         &bp->free_filter_list,
1257                                                         filter, next);
1258
1259                                         /*
1260                                          * Need to examine to see if the MAC
1261                                          * filter already existed or not before
1262                                          * allocating a new one
1263                                          */
1264
1265                                         new_filter = bnxt_alloc_filter(bp);
1266                                         if (!new_filter) {
1267                                                 PMD_DRV_LOG(ERR,
1268                                                         "MAC/VLAN filter alloc failed\n");
1269                                                 rc = -ENOMEM;
1270                                                 goto exit;
1271                                         }
1272                                         STAILQ_INSERT_TAIL(&vnic->filter,
1273                                                            new_filter, next);
1274                                         /* Inherit MAC from previous filter */
1275                                         new_filter->mac_index =
1276                                                         filter->mac_index;
1277                                         memcpy(new_filter->l2_addr,
1278                                                filter->l2_addr, ETHER_ADDR_LEN);
1279                                         /* MAC only filter */
1280                                         rc = bnxt_hwrm_set_l2_filter(bp,
1281                                                         vnic->fw_vnic_id,
1282                                                         new_filter);
1283                                         if (rc)
1284                                                 goto exit;
1285                                         PMD_DRV_LOG(INFO,
1286                                                 "Del Vlan filter for %d\n",
1287                                                 vlan_id);
1288                                 }
1289                                 filter = temp_filter;
1290                         }
1291                 }
1292         }
1293 exit:
1294         return rc;
1295 }
1296
1297 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1298 {
1299         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1300         struct bnxt_vnic_info *vnic;
1301         unsigned int i;
1302         int rc = 0;
1303         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1304                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1305         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1306
1307         /* Cycle through all VNICs */
1308         for (i = 0; i < bp->nr_vnics; i++) {
1309                 /*
1310                  * For each VNIC and each associated filter(s)
1311                  * if VLAN exists:
1312                  *   if VLAN matches vlan_id
1313                  *      VLAN filter already exists, just skip and continue
1314                  *   else
1315                  *      add a new MAC+VLAN filter
1316                  * else
1317                  *   Remove the old MAC only filter
1318                  *    Add a new MAC+VLAN filter
1319                  */
1320                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1321                         filter = STAILQ_FIRST(&vnic->filter);
1322                         while (filter) {
1323                                 temp_filter = STAILQ_NEXT(filter, next);
1324
1325                                 if (filter->enables & chk) {
1326                                         if (filter->l2_ovlan == vlan_id)
1327                                                 goto cont;
1328                                 } else {
1329                                         /* Must delete the MAC filter */
1330                                         STAILQ_REMOVE(&vnic->filter, filter,
1331                                                       bnxt_filter_info, next);
1332                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1333                                         filter->l2_ovlan = 0;
1334                                         STAILQ_INSERT_TAIL(
1335                                                         &bp->free_filter_list,
1336                                                         filter, next);
1337                                 }
1338                                 new_filter = bnxt_alloc_filter(bp);
1339                                 if (!new_filter) {
1340                                         PMD_DRV_LOG(ERR,
1341                                                 "MAC/VLAN filter alloc failed\n");
1342                                         rc = -ENOMEM;
1343                                         goto exit;
1344                                 }
1345                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1346                                                    next);
1347                                 /* Inherit MAC from the previous filter */
1348                                 new_filter->mac_index = filter->mac_index;
1349                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1350                                        ETHER_ADDR_LEN);
1351                                 /* MAC + VLAN ID filter */
1352                                 new_filter->l2_ovlan = vlan_id;
1353                                 new_filter->l2_ovlan_mask = 0xF000;
1354                                 new_filter->enables |= en;
1355                                 rc = bnxt_hwrm_set_l2_filter(bp,
1356                                                              vnic->fw_vnic_id,
1357                                                              new_filter);
1358                                 if (rc)
1359                                         goto exit;
1360                                 PMD_DRV_LOG(INFO,
1361                                         "Added Vlan filter for %d\n", vlan_id);
1362 cont:
1363                                 filter = temp_filter;
1364                         }
1365                 }
1366         }
1367 exit:
1368         return rc;
1369 }
1370
1371 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1372                                    uint16_t vlan_id, int on)
1373 {
1374         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1375
1376         /* These operations apply to ALL existing MAC/VLAN filters */
1377         if (on)
1378                 return bnxt_add_vlan_filter(bp, vlan_id);
1379         else
1380                 return bnxt_del_vlan_filter(bp, vlan_id);
1381 }
1382
1383 static int
1384 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1385 {
1386         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1387         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1388         unsigned int i;
1389
1390         if (mask & ETH_VLAN_FILTER_MASK) {
1391                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1392                         /* Remove any VLAN filters programmed */
1393                         for (i = 0; i < 4095; i++)
1394                                 bnxt_del_vlan_filter(bp, i);
1395                 }
1396                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1397                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1398         }
1399
1400         if (mask & ETH_VLAN_STRIP_MASK) {
1401                 /* Enable or disable VLAN stripping */
1402                 for (i = 0; i < bp->nr_vnics; i++) {
1403                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1404                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1405                                 vnic->vlan_strip = true;
1406                         else
1407                                 vnic->vlan_strip = false;
1408                         bnxt_hwrm_vnic_cfg(bp, vnic);
1409                 }
1410                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1411                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1412         }
1413
1414         if (mask & ETH_VLAN_EXTEND_MASK)
1415                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1416
1417         return 0;
1418 }
1419
1420 static int
1421 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1422 {
1423         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1424         /* Default Filter is tied to VNIC 0 */
1425         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1426         struct bnxt_filter_info *filter;
1427         int rc;
1428
1429         if (BNXT_VF(bp))
1430                 return -EPERM;
1431
1432         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1433
1434         STAILQ_FOREACH(filter, &vnic->filter, next) {
1435                 /* Default Filter is at Index 0 */
1436                 if (filter->mac_index != 0)
1437                         continue;
1438                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1439                 if (rc)
1440                         return rc;
1441                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1442                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1443                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1444                 filter->enables |=
1445                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1446                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1447                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1448                 if (rc)
1449                         return rc;
1450                 filter->mac_index = 0;
1451                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int
1458 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1459                           struct ether_addr *mc_addr_set,
1460                           uint32_t nb_mc_addr)
1461 {
1462         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1463         char *mc_addr_list = (char *)mc_addr_set;
1464         struct bnxt_vnic_info *vnic;
1465         uint32_t off = 0, i = 0;
1466
1467         vnic = &bp->vnic_info[0];
1468
1469         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1470                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1471                 goto allmulti;
1472         }
1473
1474         /* TODO Check for Duplicate mcast addresses */
1475         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1476         for (i = 0; i < nb_mc_addr; i++) {
1477                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1478                 off += ETHER_ADDR_LEN;
1479         }
1480
1481         vnic->mc_addr_cnt = i;
1482
1483 allmulti:
1484         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1485 }
1486
1487 static int
1488 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1489 {
1490         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1491         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1492         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1493         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1494         int ret;
1495
1496         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1497                         fw_major, fw_minor, fw_updt);
1498
1499         ret += 1; /* add the size of '\0' */
1500         if (fw_size < (uint32_t)ret)
1501                 return ret;
1502         else
1503                 return 0;
1504 }
1505
1506 static void
1507 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1508         struct rte_eth_rxq_info *qinfo)
1509 {
1510         struct bnxt_rx_queue *rxq;
1511
1512         rxq = dev->data->rx_queues[queue_id];
1513
1514         qinfo->mp = rxq->mb_pool;
1515         qinfo->scattered_rx = dev->data->scattered_rx;
1516         qinfo->nb_desc = rxq->nb_rx_desc;
1517
1518         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1519         qinfo->conf.rx_drop_en = 0;
1520         qinfo->conf.rx_deferred_start = 0;
1521 }
1522
1523 static void
1524 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1525         struct rte_eth_txq_info *qinfo)
1526 {
1527         struct bnxt_tx_queue *txq;
1528
1529         txq = dev->data->tx_queues[queue_id];
1530
1531         qinfo->nb_desc = txq->nb_tx_desc;
1532
1533         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1534         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1535         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1536
1537         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1538         qinfo->conf.tx_rs_thresh = 0;
1539         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1540 }
1541
1542 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1543 {
1544         struct bnxt *bp = eth_dev->data->dev_private;
1545         struct rte_eth_dev_info dev_info;
1546         uint32_t max_dev_mtu;
1547         uint32_t rc = 0;
1548         uint32_t i;
1549
1550         bnxt_dev_info_get_op(eth_dev, &dev_info);
1551         max_dev_mtu = dev_info.max_rx_pktlen -
1552                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1553
1554         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1555                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1556                         ETHER_MIN_MTU, max_dev_mtu);
1557                 return -EINVAL;
1558         }
1559
1560
1561         if (new_mtu > ETHER_MTU) {
1562                 bp->flags |= BNXT_FLAG_JUMBO;
1563                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1564                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1565         } else {
1566                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1567                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1568                 bp->flags &= ~BNXT_FLAG_JUMBO;
1569         }
1570
1571         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1572                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1573
1574         eth_dev->data->mtu = new_mtu;
1575         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1576
1577         for (i = 0; i < bp->nr_vnics; i++) {
1578                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1579
1580                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1581                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1582                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1583                 if (rc)
1584                         break;
1585
1586                 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1587                 if (rc)
1588                         return rc;
1589         }
1590
1591         return rc;
1592 }
1593
1594 static int
1595 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1596 {
1597         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1598         uint16_t vlan = bp->vlan;
1599         int rc;
1600
1601         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1602                 PMD_DRV_LOG(ERR,
1603                         "PVID cannot be modified for this function\n");
1604                 return -ENOTSUP;
1605         }
1606         bp->vlan = on ? pvid : 0;
1607
1608         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1609         if (rc)
1610                 bp->vlan = vlan;
1611         return rc;
1612 }
1613
1614 static int
1615 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1616 {
1617         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1618
1619         return bnxt_hwrm_port_led_cfg(bp, true);
1620 }
1621
1622 static int
1623 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1624 {
1625         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1626
1627         return bnxt_hwrm_port_led_cfg(bp, false);
1628 }
1629
1630 static uint32_t
1631 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1632 {
1633         uint32_t desc = 0, raw_cons = 0, cons;
1634         struct bnxt_cp_ring_info *cpr;
1635         struct bnxt_rx_queue *rxq;
1636         struct rx_pkt_cmpl *rxcmp;
1637         uint16_t cmp_type;
1638         uint8_t cmp = 1;
1639         bool valid;
1640
1641         rxq = dev->data->rx_queues[rx_queue_id];
1642         cpr = rxq->cp_ring;
1643         valid = cpr->valid;
1644
1645         while (raw_cons < rxq->nb_rx_desc) {
1646                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1647                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1648
1649                 if (!CMPL_VALID(rxcmp, valid))
1650                         goto nothing_to_do;
1651                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1652                 cmp_type = CMP_TYPE(rxcmp);
1653                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1654                         cmp = (rte_le_to_cpu_32(
1655                                         ((struct rx_tpa_end_cmpl *)
1656                                          (rxcmp))->agg_bufs_v1) &
1657                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1658                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1659                         desc++;
1660                 } else if (cmp_type == 0x11) {
1661                         desc++;
1662                         cmp = (rxcmp->agg_bufs_v1 &
1663                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1664                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1665                 } else {
1666                         cmp = 1;
1667                 }
1668 nothing_to_do:
1669                 raw_cons += cmp ? cmp : 2;
1670         }
1671
1672         return desc;
1673 }
1674
1675 static int
1676 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1677 {
1678         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1679         struct bnxt_rx_ring_info *rxr;
1680         struct bnxt_cp_ring_info *cpr;
1681         struct bnxt_sw_rx_bd *rx_buf;
1682         struct rx_pkt_cmpl *rxcmp;
1683         uint32_t cons, cp_cons;
1684
1685         if (!rxq)
1686                 return -EINVAL;
1687
1688         cpr = rxq->cp_ring;
1689         rxr = rxq->rx_ring;
1690
1691         if (offset >= rxq->nb_rx_desc)
1692                 return -EINVAL;
1693
1694         cons = RING_CMP(cpr->cp_ring_struct, offset);
1695         cp_cons = cpr->cp_raw_cons;
1696         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1697
1698         if (cons > cp_cons) {
1699                 if (CMPL_VALID(rxcmp, cpr->valid))
1700                         return RTE_ETH_RX_DESC_DONE;
1701         } else {
1702                 if (CMPL_VALID(rxcmp, !cpr->valid))
1703                         return RTE_ETH_RX_DESC_DONE;
1704         }
1705         rx_buf = &rxr->rx_buf_ring[cons];
1706         if (rx_buf->mbuf == NULL)
1707                 return RTE_ETH_RX_DESC_UNAVAIL;
1708
1709
1710         return RTE_ETH_RX_DESC_AVAIL;
1711 }
1712
1713 static int
1714 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1715 {
1716         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1717         struct bnxt_tx_ring_info *txr;
1718         struct bnxt_cp_ring_info *cpr;
1719         struct bnxt_sw_tx_bd *tx_buf;
1720         struct tx_pkt_cmpl *txcmp;
1721         uint32_t cons, cp_cons;
1722
1723         if (!txq)
1724                 return -EINVAL;
1725
1726         cpr = txq->cp_ring;
1727         txr = txq->tx_ring;
1728
1729         if (offset >= txq->nb_tx_desc)
1730                 return -EINVAL;
1731
1732         cons = RING_CMP(cpr->cp_ring_struct, offset);
1733         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1734         cp_cons = cpr->cp_raw_cons;
1735
1736         if (cons > cp_cons) {
1737                 if (CMPL_VALID(txcmp, cpr->valid))
1738                         return RTE_ETH_TX_DESC_UNAVAIL;
1739         } else {
1740                 if (CMPL_VALID(txcmp, !cpr->valid))
1741                         return RTE_ETH_TX_DESC_UNAVAIL;
1742         }
1743         tx_buf = &txr->tx_buf_ring[cons];
1744         if (tx_buf->mbuf == NULL)
1745                 return RTE_ETH_TX_DESC_DONE;
1746
1747         return RTE_ETH_TX_DESC_FULL;
1748 }
1749
1750 static struct bnxt_filter_info *
1751 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1752                                 struct rte_eth_ethertype_filter *efilter,
1753                                 struct bnxt_vnic_info *vnic0,
1754                                 struct bnxt_vnic_info *vnic,
1755                                 int *ret)
1756 {
1757         struct bnxt_filter_info *mfilter = NULL;
1758         int match = 0;
1759         *ret = 0;
1760
1761         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1762                 efilter->ether_type == ETHER_TYPE_IPv6) {
1763                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1764                         " ethertype filter.", efilter->ether_type);
1765                 *ret = -EINVAL;
1766                 goto exit;
1767         }
1768         if (efilter->queue >= bp->rx_nr_rings) {
1769                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1770                 *ret = -EINVAL;
1771                 goto exit;
1772         }
1773
1774         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1775         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1776         if (vnic == NULL) {
1777                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1778                 *ret = -EINVAL;
1779                 goto exit;
1780         }
1781
1782         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1783                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1784                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1785                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1786                              mfilter->flags ==
1787                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1788                              mfilter->ethertype == efilter->ether_type)) {
1789                                 match = 1;
1790                                 break;
1791                         }
1792                 }
1793         } else {
1794                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1795                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1796                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1797                              mfilter->ethertype == efilter->ether_type &&
1798                              mfilter->flags ==
1799                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1800                                 match = 1;
1801                                 break;
1802                         }
1803         }
1804
1805         if (match)
1806                 *ret = -EEXIST;
1807
1808 exit:
1809         return mfilter;
1810 }
1811
1812 static int
1813 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1814                         enum rte_filter_op filter_op,
1815                         void *arg)
1816 {
1817         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1818         struct rte_eth_ethertype_filter *efilter =
1819                         (struct rte_eth_ethertype_filter *)arg;
1820         struct bnxt_filter_info *bfilter, *filter1;
1821         struct bnxt_vnic_info *vnic, *vnic0;
1822         int ret;
1823
1824         if (filter_op == RTE_ETH_FILTER_NOP)
1825                 return 0;
1826
1827         if (arg == NULL) {
1828                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1829                             filter_op);
1830                 return -EINVAL;
1831         }
1832
1833         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1834         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1835
1836         switch (filter_op) {
1837         case RTE_ETH_FILTER_ADD:
1838                 bnxt_match_and_validate_ether_filter(bp, efilter,
1839                                                         vnic0, vnic, &ret);
1840                 if (ret < 0)
1841                         return ret;
1842
1843                 bfilter = bnxt_get_unused_filter(bp);
1844                 if (bfilter == NULL) {
1845                         PMD_DRV_LOG(ERR,
1846                                 "Not enough resources for a new filter.\n");
1847                         return -ENOMEM;
1848                 }
1849                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1850                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1851                        ETHER_ADDR_LEN);
1852                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1853                        ETHER_ADDR_LEN);
1854                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1855                 bfilter->ethertype = efilter->ether_type;
1856                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1857
1858                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1859                 if (filter1 == NULL) {
1860                         ret = -1;
1861                         goto cleanup;
1862                 }
1863                 bfilter->enables |=
1864                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1865                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1866
1867                 bfilter->dst_id = vnic->fw_vnic_id;
1868
1869                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1870                         bfilter->flags =
1871                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1872                 }
1873
1874                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1875                 if (ret)
1876                         goto cleanup;
1877                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1878                 break;
1879         case RTE_ETH_FILTER_DELETE:
1880                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1881                                                         vnic0, vnic, &ret);
1882                 if (ret == -EEXIST) {
1883                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1884
1885                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1886                                       next);
1887                         bnxt_free_filter(bp, filter1);
1888                 } else if (ret == 0) {
1889                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1890                 }
1891                 break;
1892         default:
1893                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1894                 ret = -EINVAL;
1895                 goto error;
1896         }
1897         return ret;
1898 cleanup:
1899         bnxt_free_filter(bp, bfilter);
1900 error:
1901         return ret;
1902 }
1903
1904 static inline int
1905 parse_ntuple_filter(struct bnxt *bp,
1906                     struct rte_eth_ntuple_filter *nfilter,
1907                     struct bnxt_filter_info *bfilter)
1908 {
1909         uint32_t en = 0;
1910
1911         if (nfilter->queue >= bp->rx_nr_rings) {
1912                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1913                 return -EINVAL;
1914         }
1915
1916         switch (nfilter->dst_port_mask) {
1917         case UINT16_MAX:
1918                 bfilter->dst_port_mask = -1;
1919                 bfilter->dst_port = nfilter->dst_port;
1920                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1921                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1922                 break;
1923         default:
1924                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1925                 return -EINVAL;
1926         }
1927
1928         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1929         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1930
1931         switch (nfilter->proto_mask) {
1932         case UINT8_MAX:
1933                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1934                         bfilter->ip_protocol = 17;
1935                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1936                         bfilter->ip_protocol = 6;
1937                 else
1938                         return -EINVAL;
1939                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1940                 break;
1941         default:
1942                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1943                 return -EINVAL;
1944         }
1945
1946         switch (nfilter->dst_ip_mask) {
1947         case UINT32_MAX:
1948                 bfilter->dst_ipaddr_mask[0] = -1;
1949                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1950                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1951                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1952                 break;
1953         default:
1954                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1955                 return -EINVAL;
1956         }
1957
1958         switch (nfilter->src_ip_mask) {
1959         case UINT32_MAX:
1960                 bfilter->src_ipaddr_mask[0] = -1;
1961                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1962                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1963                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1964                 break;
1965         default:
1966                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1967                 return -EINVAL;
1968         }
1969
1970         switch (nfilter->src_port_mask) {
1971         case UINT16_MAX:
1972                 bfilter->src_port_mask = -1;
1973                 bfilter->src_port = nfilter->src_port;
1974                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1975                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1976                 break;
1977         default:
1978                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1979                 return -EINVAL;
1980         }
1981
1982         //TODO Priority
1983         //nfilter->priority = (uint8_t)filter->priority;
1984
1985         bfilter->enables = en;
1986         return 0;
1987 }
1988
1989 static struct bnxt_filter_info*
1990 bnxt_match_ntuple_filter(struct bnxt *bp,
1991                          struct bnxt_filter_info *bfilter,
1992                          struct bnxt_vnic_info **mvnic)
1993 {
1994         struct bnxt_filter_info *mfilter = NULL;
1995         int i;
1996
1997         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1998                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1999                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2000                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2001                             bfilter->src_ipaddr_mask[0] ==
2002                             mfilter->src_ipaddr_mask[0] &&
2003                             bfilter->src_port == mfilter->src_port &&
2004                             bfilter->src_port_mask == mfilter->src_port_mask &&
2005                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2006                             bfilter->dst_ipaddr_mask[0] ==
2007                             mfilter->dst_ipaddr_mask[0] &&
2008                             bfilter->dst_port == mfilter->dst_port &&
2009                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2010                             bfilter->flags == mfilter->flags &&
2011                             bfilter->enables == mfilter->enables) {
2012                                 if (mvnic)
2013                                         *mvnic = vnic;
2014                                 return mfilter;
2015                         }
2016                 }
2017         }
2018         return NULL;
2019 }
2020
2021 static int
2022 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2023                        struct rte_eth_ntuple_filter *nfilter,
2024                        enum rte_filter_op filter_op)
2025 {
2026         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2027         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2028         int ret;
2029
2030         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2031                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2032                 return -EINVAL;
2033         }
2034
2035         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2036                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2037                 return -EINVAL;
2038         }
2039
2040         bfilter = bnxt_get_unused_filter(bp);
2041         if (bfilter == NULL) {
2042                 PMD_DRV_LOG(ERR,
2043                         "Not enough resources for a new filter.\n");
2044                 return -ENOMEM;
2045         }
2046         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2047         if (ret < 0)
2048                 goto free_filter;
2049
2050         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2051         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2052         filter1 = STAILQ_FIRST(&vnic0->filter);
2053         if (filter1 == NULL) {
2054                 ret = -1;
2055                 goto free_filter;
2056         }
2057
2058         bfilter->dst_id = vnic->fw_vnic_id;
2059         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2060         bfilter->enables |=
2061                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2062         bfilter->ethertype = 0x800;
2063         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2064
2065         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2066
2067         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2068             bfilter->dst_id == mfilter->dst_id) {
2069                 PMD_DRV_LOG(ERR, "filter exists.\n");
2070                 ret = -EEXIST;
2071                 goto free_filter;
2072         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2073                    bfilter->dst_id != mfilter->dst_id) {
2074                 mfilter->dst_id = vnic->fw_vnic_id;
2075                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2076                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2077                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2078                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2079                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2080                 goto free_filter;
2081         }
2082         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2083                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2084                 ret = -ENOENT;
2085                 goto free_filter;
2086         }
2087
2088         if (filter_op == RTE_ETH_FILTER_ADD) {
2089                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2090                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2091                 if (ret)
2092                         goto free_filter;
2093                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2094         } else {
2095                 if (mfilter == NULL) {
2096                         /* This should not happen. But for Coverity! */
2097                         ret = -ENOENT;
2098                         goto free_filter;
2099                 }
2100                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2101
2102                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2103                 bnxt_free_filter(bp, mfilter);
2104                 mfilter->fw_l2_filter_id = -1;
2105                 bnxt_free_filter(bp, bfilter);
2106                 bfilter->fw_l2_filter_id = -1;
2107         }
2108
2109         return 0;
2110 free_filter:
2111         bfilter->fw_l2_filter_id = -1;
2112         bnxt_free_filter(bp, bfilter);
2113         return ret;
2114 }
2115
2116 static int
2117 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2118                         enum rte_filter_op filter_op,
2119                         void *arg)
2120 {
2121         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2122         int ret;
2123
2124         if (filter_op == RTE_ETH_FILTER_NOP)
2125                 return 0;
2126
2127         if (arg == NULL) {
2128                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2129                             filter_op);
2130                 return -EINVAL;
2131         }
2132
2133         switch (filter_op) {
2134         case RTE_ETH_FILTER_ADD:
2135                 ret = bnxt_cfg_ntuple_filter(bp,
2136                         (struct rte_eth_ntuple_filter *)arg,
2137                         filter_op);
2138                 break;
2139         case RTE_ETH_FILTER_DELETE:
2140                 ret = bnxt_cfg_ntuple_filter(bp,
2141                         (struct rte_eth_ntuple_filter *)arg,
2142                         filter_op);
2143                 break;
2144         default:
2145                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2146                 ret = -EINVAL;
2147                 break;
2148         }
2149         return ret;
2150 }
2151
2152 static int
2153 bnxt_parse_fdir_filter(struct bnxt *bp,
2154                        struct rte_eth_fdir_filter *fdir,
2155                        struct bnxt_filter_info *filter)
2156 {
2157         enum rte_fdir_mode fdir_mode =
2158                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2159         struct bnxt_vnic_info *vnic0, *vnic;
2160         struct bnxt_filter_info *filter1;
2161         uint32_t en = 0;
2162         int i;
2163
2164         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2165                 return -EINVAL;
2166
2167         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2168         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2169
2170         switch (fdir->input.flow_type) {
2171         case RTE_ETH_FLOW_IPV4:
2172         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2173                 /* FALLTHROUGH */
2174                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2175                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2176                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2177                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2178                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2179                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2180                 filter->ip_addr_type =
2181                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2182                 filter->src_ipaddr_mask[0] = 0xffffffff;
2183                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2184                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2185                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2186                 filter->ethertype = 0x800;
2187                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2188                 break;
2189         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2190                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2191                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2192                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2194                 filter->dst_port_mask = 0xffff;
2195                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2196                 filter->src_port_mask = 0xffff;
2197                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2198                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2199                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2200                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2201                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2202                 filter->ip_protocol = 6;
2203                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2204                 filter->ip_addr_type =
2205                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2206                 filter->src_ipaddr_mask[0] = 0xffffffff;
2207                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2208                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2209                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2210                 filter->ethertype = 0x800;
2211                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2212                 break;
2213         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2214                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2215                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2216                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2217                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2218                 filter->dst_port_mask = 0xffff;
2219                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2220                 filter->src_port_mask = 0xffff;
2221                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2222                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2223                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2224                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2225                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2226                 filter->ip_protocol = 17;
2227                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2228                 filter->ip_addr_type =
2229                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2230                 filter->src_ipaddr_mask[0] = 0xffffffff;
2231                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2232                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2233                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2234                 filter->ethertype = 0x800;
2235                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2236                 break;
2237         case RTE_ETH_FLOW_IPV6:
2238         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2239                 /* FALLTHROUGH */
2240                 filter->ip_addr_type =
2241                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2242                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2243                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2244                 rte_memcpy(filter->src_ipaddr,
2245                            fdir->input.flow.ipv6_flow.src_ip, 16);
2246                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2247                 rte_memcpy(filter->dst_ipaddr,
2248                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2249                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2250                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2251                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2252                 memset(filter->src_ipaddr_mask, 0xff, 16);
2253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2254                 filter->ethertype = 0x86dd;
2255                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2256                 break;
2257         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2258                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2259                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2260                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2261                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2262                 filter->dst_port_mask = 0xffff;
2263                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2264                 filter->src_port_mask = 0xffff;
2265                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2266                 filter->ip_addr_type =
2267                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2268                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2269                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2270                 rte_memcpy(filter->src_ipaddr,
2271                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2273                 rte_memcpy(filter->dst_ipaddr,
2274                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2275                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2276                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2277                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2278                 memset(filter->src_ipaddr_mask, 0xff, 16);
2279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2280                 filter->ethertype = 0x86dd;
2281                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2282                 break;
2283         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2284                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2285                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2286                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2287                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2288                 filter->dst_port_mask = 0xffff;
2289                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2290                 filter->src_port_mask = 0xffff;
2291                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2292                 filter->ip_addr_type =
2293                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2294                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2295                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2296                 rte_memcpy(filter->src_ipaddr,
2297                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2298                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2299                 rte_memcpy(filter->dst_ipaddr,
2300                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2301                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2302                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2303                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2304                 memset(filter->src_ipaddr_mask, 0xff, 16);
2305                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2306                 filter->ethertype = 0x86dd;
2307                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2308                 break;
2309         case RTE_ETH_FLOW_L2_PAYLOAD:
2310                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2311                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2312                 break;
2313         case RTE_ETH_FLOW_VXLAN:
2314                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2315                         return -EINVAL;
2316                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2317                 filter->tunnel_type =
2318                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2319                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2320                 break;
2321         case RTE_ETH_FLOW_NVGRE:
2322                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2323                         return -EINVAL;
2324                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2325                 filter->tunnel_type =
2326                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2327                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2328                 break;
2329         case RTE_ETH_FLOW_UNKNOWN:
2330         case RTE_ETH_FLOW_RAW:
2331         case RTE_ETH_FLOW_FRAG_IPV4:
2332         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2333         case RTE_ETH_FLOW_FRAG_IPV6:
2334         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2335         case RTE_ETH_FLOW_IPV6_EX:
2336         case RTE_ETH_FLOW_IPV6_TCP_EX:
2337         case RTE_ETH_FLOW_IPV6_UDP_EX:
2338         case RTE_ETH_FLOW_GENEVE:
2339                 /* FALLTHROUGH */
2340         default:
2341                 return -EINVAL;
2342         }
2343
2344         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2345         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2346         if (vnic == NULL) {
2347                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2348                 return -EINVAL;
2349         }
2350
2351
2352         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2353                 rte_memcpy(filter->dst_macaddr,
2354                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2355                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2356         }
2357
2358         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2359                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2360                 filter1 = STAILQ_FIRST(&vnic0->filter);
2361                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2362         } else {
2363                 filter->dst_id = vnic->fw_vnic_id;
2364                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2365                         if (filter->dst_macaddr[i] == 0x00)
2366                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2367                         else
2368                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2369         }
2370
2371         if (filter1 == NULL)
2372                 return -EINVAL;
2373
2374         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2375         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2376
2377         filter->enables = en;
2378
2379         return 0;
2380 }
2381
2382 static struct bnxt_filter_info *
2383 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2384                 struct bnxt_vnic_info **mvnic)
2385 {
2386         struct bnxt_filter_info *mf = NULL;
2387         int i;
2388
2389         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2390                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2391
2392                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2393                         if (mf->filter_type == nf->filter_type &&
2394                             mf->flags == nf->flags &&
2395                             mf->src_port == nf->src_port &&
2396                             mf->src_port_mask == nf->src_port_mask &&
2397                             mf->dst_port == nf->dst_port &&
2398                             mf->dst_port_mask == nf->dst_port_mask &&
2399                             mf->ip_protocol == nf->ip_protocol &&
2400                             mf->ip_addr_type == nf->ip_addr_type &&
2401                             mf->ethertype == nf->ethertype &&
2402                             mf->vni == nf->vni &&
2403                             mf->tunnel_type == nf->tunnel_type &&
2404                             mf->l2_ovlan == nf->l2_ovlan &&
2405                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2406                             mf->l2_ivlan == nf->l2_ivlan &&
2407                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2408                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2409                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2410                                     ETHER_ADDR_LEN) &&
2411                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2412                                     ETHER_ADDR_LEN) &&
2413                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2414                                     ETHER_ADDR_LEN) &&
2415                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2416                                     sizeof(nf->src_ipaddr)) &&
2417                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2418                                     sizeof(nf->src_ipaddr_mask)) &&
2419                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2420                                     sizeof(nf->dst_ipaddr)) &&
2421                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2422                                     sizeof(nf->dst_ipaddr_mask))) {
2423                                 if (mvnic)
2424                                         *mvnic = vnic;
2425                                 return mf;
2426                         }
2427                 }
2428         }
2429         return NULL;
2430 }
2431
2432 static int
2433 bnxt_fdir_filter(struct rte_eth_dev *dev,
2434                  enum rte_filter_op filter_op,
2435                  void *arg)
2436 {
2437         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2438         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2439         struct bnxt_filter_info *filter, *match;
2440         struct bnxt_vnic_info *vnic, *mvnic;
2441         int ret = 0, i;
2442
2443         if (filter_op == RTE_ETH_FILTER_NOP)
2444                 return 0;
2445
2446         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2447                 return -EINVAL;
2448
2449         switch (filter_op) {
2450         case RTE_ETH_FILTER_ADD:
2451         case RTE_ETH_FILTER_DELETE:
2452                 filter = bnxt_get_unused_filter(bp);
2453                 if (filter == NULL) {
2454                         PMD_DRV_LOG(ERR,
2455                                 "Not enough resources for a new flow.\n");
2456                         return -ENOMEM;
2457                 }
2458
2459                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2460                 if (ret != 0)
2461                         goto free_filter;
2462                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2463
2464                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2465                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2466                 else
2467                         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2468
2469                 match = bnxt_match_fdir(bp, filter, &mvnic);
2470                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2471                         if (match->dst_id == vnic->fw_vnic_id) {
2472                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2473                                 ret = -EEXIST;
2474                                 goto free_filter;
2475                         } else {
2476                                 match->dst_id = vnic->fw_vnic_id;
2477                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2478                                                                   match->dst_id,
2479                                                                   match);
2480                                 STAILQ_REMOVE(&mvnic->filter, match,
2481                                               bnxt_filter_info, next);
2482                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2483                                 PMD_DRV_LOG(ERR,
2484                                         "Filter with matching pattern exist\n");
2485                                 PMD_DRV_LOG(ERR,
2486                                         "Updated it to new destination q\n");
2487                                 goto free_filter;
2488                         }
2489                 }
2490                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2491                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2492                         ret = -ENOENT;
2493                         goto free_filter;
2494                 }
2495
2496                 if (filter_op == RTE_ETH_FILTER_ADD) {
2497                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2498                                                           filter->dst_id,
2499                                                           filter);
2500                         if (ret)
2501                                 goto free_filter;
2502                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2503                 } else {
2504                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2505                         STAILQ_REMOVE(&vnic->filter, match,
2506                                       bnxt_filter_info, next);
2507                         bnxt_free_filter(bp, match);
2508                         filter->fw_l2_filter_id = -1;
2509                         bnxt_free_filter(bp, filter);
2510                 }
2511                 break;
2512         case RTE_ETH_FILTER_FLUSH:
2513                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2514                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2515
2516                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2517                                 if (filter->filter_type ==
2518                                     HWRM_CFA_NTUPLE_FILTER) {
2519                                         ret =
2520                                         bnxt_hwrm_clear_ntuple_filter(bp,
2521                                                                       filter);
2522                                         STAILQ_REMOVE(&vnic->filter, filter,
2523                                                       bnxt_filter_info, next);
2524                                 }
2525                         }
2526                 }
2527                 return ret;
2528         case RTE_ETH_FILTER_UPDATE:
2529         case RTE_ETH_FILTER_STATS:
2530         case RTE_ETH_FILTER_INFO:
2531                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2532                 break;
2533         default:
2534                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2535                 ret = -EINVAL;
2536                 break;
2537         }
2538         return ret;
2539
2540 free_filter:
2541         filter->fw_l2_filter_id = -1;
2542         bnxt_free_filter(bp, filter);
2543         return ret;
2544 }
2545
2546 static int
2547 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2548                     enum rte_filter_type filter_type,
2549                     enum rte_filter_op filter_op, void *arg)
2550 {
2551         int ret = 0;
2552
2553         switch (filter_type) {
2554         case RTE_ETH_FILTER_TUNNEL:
2555                 PMD_DRV_LOG(ERR,
2556                         "filter type: %d: To be implemented\n", filter_type);
2557                 break;
2558         case RTE_ETH_FILTER_FDIR:
2559                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2560                 break;
2561         case RTE_ETH_FILTER_NTUPLE:
2562                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2563                 break;
2564         case RTE_ETH_FILTER_ETHERTYPE:
2565                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2566                 break;
2567         case RTE_ETH_FILTER_GENERIC:
2568                 if (filter_op != RTE_ETH_FILTER_GET)
2569                         return -EINVAL;
2570                 *(const void **)arg = &bnxt_flow_ops;
2571                 break;
2572         default:
2573                 PMD_DRV_LOG(ERR,
2574                         "Filter type (%d) not supported", filter_type);
2575                 ret = -EINVAL;
2576                 break;
2577         }
2578         return ret;
2579 }
2580
2581 static const uint32_t *
2582 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2583 {
2584         static const uint32_t ptypes[] = {
2585                 RTE_PTYPE_L2_ETHER_VLAN,
2586                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2587                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2588                 RTE_PTYPE_L4_ICMP,
2589                 RTE_PTYPE_L4_TCP,
2590                 RTE_PTYPE_L4_UDP,
2591                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2592                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2593                 RTE_PTYPE_INNER_L4_ICMP,
2594                 RTE_PTYPE_INNER_L4_TCP,
2595                 RTE_PTYPE_INNER_L4_UDP,
2596                 RTE_PTYPE_UNKNOWN
2597         };
2598
2599         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2600                 return ptypes;
2601         return NULL;
2602 }
2603
2604 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2605                          int reg_win)
2606 {
2607         uint32_t reg_base = *reg_arr & 0xfffff000;
2608         uint32_t win_off;
2609         int i;
2610
2611         for (i = 0; i < count; i++) {
2612                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2613                         return -ERANGE;
2614         }
2615         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2616         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2617         return 0;
2618 }
2619
2620 static int bnxt_map_ptp_regs(struct bnxt *bp)
2621 {
2622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2623         uint32_t *reg_arr;
2624         int rc, i;
2625
2626         reg_arr = ptp->rx_regs;
2627         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2628         if (rc)
2629                 return rc;
2630
2631         reg_arr = ptp->tx_regs;
2632         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2633         if (rc)
2634                 return rc;
2635
2636         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2637                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2638
2639         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2640                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2641
2642         return 0;
2643 }
2644
2645 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2646 {
2647         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2648                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2649         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2650                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2651 }
2652
2653 static uint64_t bnxt_cc_read(struct bnxt *bp)
2654 {
2655         uint64_t ns;
2656
2657         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2658                               BNXT_GRCPF_REG_SYNC_TIME));
2659         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2660                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2661         return ns;
2662 }
2663
2664 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2665 {
2666         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2667         uint32_t fifo;
2668
2669         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2670                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2671         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2672                 return -EAGAIN;
2673
2674         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2675                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2676         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2677                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2678         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2679                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2680
2681         return 0;
2682 }
2683
2684 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2685 {
2686         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2687         struct bnxt_pf_info *pf = &bp->pf;
2688         uint16_t port_id;
2689         uint32_t fifo;
2690
2691         if (!ptp)
2692                 return -ENODEV;
2693
2694         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2695                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2696         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2697                 return -EAGAIN;
2698
2699         port_id = pf->port_id;
2700         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2701                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2702
2703         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2704                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2705         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2706 /*              bnxt_clr_rx_ts(bp);       TBD  */
2707                 return -EBUSY;
2708         }
2709
2710         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2711                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2712         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2713                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2714
2715         return 0;
2716 }
2717
2718 static int
2719 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2720 {
2721         uint64_t ns;
2722         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2723         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2724
2725         if (!ptp)
2726                 return 0;
2727
2728         ns = rte_timespec_to_ns(ts);
2729         /* Set the timecounters to a new value. */
2730         ptp->tc.nsec = ns;
2731
2732         return 0;
2733 }
2734
2735 static int
2736 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2737 {
2738         uint64_t ns, systime_cycles;
2739         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2741
2742         if (!ptp)
2743                 return 0;
2744
2745         systime_cycles = bnxt_cc_read(bp);
2746         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2747         *ts = rte_ns_to_timespec(ns);
2748
2749         return 0;
2750 }
2751 static int
2752 bnxt_timesync_enable(struct rte_eth_dev *dev)
2753 {
2754         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2755         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2756         uint32_t shift = 0;
2757
2758         if (!ptp)
2759                 return 0;
2760
2761         ptp->rx_filter = 1;
2762         ptp->tx_tstamp_en = 1;
2763         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2764
2765         if (!bnxt_hwrm_ptp_cfg(bp))
2766                 bnxt_map_ptp_regs(bp);
2767
2768         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2769         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2770         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2771
2772         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2773         ptp->tc.cc_shift = shift;
2774         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2775
2776         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2777         ptp->rx_tstamp_tc.cc_shift = shift;
2778         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2779
2780         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2781         ptp->tx_tstamp_tc.cc_shift = shift;
2782         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2783
2784         return 0;
2785 }
2786
2787 static int
2788 bnxt_timesync_disable(struct rte_eth_dev *dev)
2789 {
2790         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2791         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2792
2793         if (!ptp)
2794                 return 0;
2795
2796         ptp->rx_filter = 0;
2797         ptp->tx_tstamp_en = 0;
2798         ptp->rxctl = 0;
2799
2800         bnxt_hwrm_ptp_cfg(bp);
2801
2802         bnxt_unmap_ptp_regs(bp);
2803
2804         return 0;
2805 }
2806
2807 static int
2808 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2809                                  struct timespec *timestamp,
2810                                  uint32_t flags __rte_unused)
2811 {
2812         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2813         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2814         uint64_t rx_tstamp_cycles = 0;
2815         uint64_t ns;
2816
2817         if (!ptp)
2818                 return 0;
2819
2820         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2821         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2822         *timestamp = rte_ns_to_timespec(ns);
2823         return  0;
2824 }
2825
2826 static int
2827 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2828                                  struct timespec *timestamp)
2829 {
2830         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2831         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2832         uint64_t tx_tstamp_cycles = 0;
2833         uint64_t ns;
2834
2835         if (!ptp)
2836                 return 0;
2837
2838         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2839         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2840         *timestamp = rte_ns_to_timespec(ns);
2841
2842         return 0;
2843 }
2844
2845 static int
2846 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2847 {
2848         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2849         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2850
2851         if (!ptp)
2852                 return 0;
2853
2854         ptp->tc.nsec += delta;
2855
2856         return 0;
2857 }
2858
2859 static int
2860 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2861 {
2862         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2863         int rc;
2864         uint32_t dir_entries;
2865         uint32_t entry_length;
2866
2867         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2868                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2869                 bp->pdev->addr.devid, bp->pdev->addr.function);
2870
2871         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2872         if (rc != 0)
2873                 return rc;
2874
2875         return dir_entries * entry_length;
2876 }
2877
2878 static int
2879 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2880                 struct rte_dev_eeprom_info *in_eeprom)
2881 {
2882         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2883         uint32_t index;
2884         uint32_t offset;
2885
2886         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2887                 "len = %d\n", bp->pdev->addr.domain,
2888                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2889                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2890
2891         if (in_eeprom->offset == 0) /* special offset value to get directory */
2892                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2893                                                 in_eeprom->data);
2894
2895         index = in_eeprom->offset >> 24;
2896         offset = in_eeprom->offset & 0xffffff;
2897
2898         if (index != 0)
2899                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2900                                            in_eeprom->length, in_eeprom->data);
2901
2902         return 0;
2903 }
2904
2905 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2906 {
2907         switch (dir_type) {
2908         case BNX_DIR_TYPE_CHIMP_PATCH:
2909         case BNX_DIR_TYPE_BOOTCODE:
2910         case BNX_DIR_TYPE_BOOTCODE_2:
2911         case BNX_DIR_TYPE_APE_FW:
2912         case BNX_DIR_TYPE_APE_PATCH:
2913         case BNX_DIR_TYPE_KONG_FW:
2914         case BNX_DIR_TYPE_KONG_PATCH:
2915         case BNX_DIR_TYPE_BONO_FW:
2916         case BNX_DIR_TYPE_BONO_PATCH:
2917                 return true;
2918         }
2919
2920         return false;
2921 }
2922
2923 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2924 {
2925         switch (dir_type) {
2926         case BNX_DIR_TYPE_AVS:
2927         case BNX_DIR_TYPE_EXP_ROM_MBA:
2928         case BNX_DIR_TYPE_PCIE:
2929         case BNX_DIR_TYPE_TSCF_UCODE:
2930         case BNX_DIR_TYPE_EXT_PHY:
2931         case BNX_DIR_TYPE_CCM:
2932         case BNX_DIR_TYPE_ISCSI_BOOT:
2933         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2934         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2935                 return true;
2936         }
2937
2938         return false;
2939 }
2940
2941 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2942 {
2943         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2944                 bnxt_dir_type_is_other_exec_format(dir_type);
2945 }
2946
2947 static int
2948 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2949                 struct rte_dev_eeprom_info *in_eeprom)
2950 {
2951         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2952         uint8_t index, dir_op;
2953         uint16_t type, ext, ordinal, attr;
2954
2955         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2956                 "len = %d\n", bp->pdev->addr.domain,
2957                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2958                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2959
2960         if (!BNXT_PF(bp)) {
2961                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2962                 return -EINVAL;
2963         }
2964
2965         type = in_eeprom->magic >> 16;
2966
2967         if (type == 0xffff) { /* special value for directory operations */
2968                 index = in_eeprom->magic & 0xff;
2969                 dir_op = in_eeprom->magic >> 8;
2970                 if (index == 0)
2971                         return -EINVAL;
2972                 switch (dir_op) {
2973                 case 0x0e: /* erase */
2974                         if (in_eeprom->offset != ~in_eeprom->magic)
2975                                 return -EINVAL;
2976                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2977                 default:
2978                         return -EINVAL;
2979                 }
2980         }
2981
2982         /* Create or re-write an NVM item: */
2983         if (bnxt_dir_type_is_executable(type) == true)
2984                 return -EOPNOTSUPP;
2985         ext = in_eeprom->magic & 0xffff;
2986         ordinal = in_eeprom->offset >> 16;
2987         attr = in_eeprom->offset & 0xffff;
2988
2989         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2990                                      in_eeprom->data, in_eeprom->length);
2991         return 0;
2992 }
2993
2994 /*
2995  * Initialization
2996  */
2997
2998 static const struct eth_dev_ops bnxt_dev_ops = {
2999         .dev_infos_get = bnxt_dev_info_get_op,
3000         .dev_close = bnxt_dev_close_op,
3001         .dev_configure = bnxt_dev_configure_op,
3002         .dev_start = bnxt_dev_start_op,
3003         .dev_stop = bnxt_dev_stop_op,
3004         .dev_set_link_up = bnxt_dev_set_link_up_op,
3005         .dev_set_link_down = bnxt_dev_set_link_down_op,
3006         .stats_get = bnxt_stats_get_op,
3007         .stats_reset = bnxt_stats_reset_op,
3008         .rx_queue_setup = bnxt_rx_queue_setup_op,
3009         .rx_queue_release = bnxt_rx_queue_release_op,
3010         .tx_queue_setup = bnxt_tx_queue_setup_op,
3011         .tx_queue_release = bnxt_tx_queue_release_op,
3012         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3013         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3014         .reta_update = bnxt_reta_update_op,
3015         .reta_query = bnxt_reta_query_op,
3016         .rss_hash_update = bnxt_rss_hash_update_op,
3017         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3018         .link_update = bnxt_link_update_op,
3019         .promiscuous_enable = bnxt_promiscuous_enable_op,
3020         .promiscuous_disable = bnxt_promiscuous_disable_op,
3021         .allmulticast_enable = bnxt_allmulticast_enable_op,
3022         .allmulticast_disable = bnxt_allmulticast_disable_op,
3023         .mac_addr_add = bnxt_mac_addr_add_op,
3024         .mac_addr_remove = bnxt_mac_addr_remove_op,
3025         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3026         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3027         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3028         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3029         .vlan_filter_set = bnxt_vlan_filter_set_op,
3030         .vlan_offload_set = bnxt_vlan_offload_set_op,
3031         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3032         .mtu_set = bnxt_mtu_set_op,
3033         .mac_addr_set = bnxt_set_default_mac_addr_op,
3034         .xstats_get = bnxt_dev_xstats_get_op,
3035         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3036         .xstats_reset = bnxt_dev_xstats_reset_op,
3037         .fw_version_get = bnxt_fw_version_get,
3038         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3039         .rxq_info_get = bnxt_rxq_info_get_op,
3040         .txq_info_get = bnxt_txq_info_get_op,
3041         .dev_led_on = bnxt_dev_led_on_op,
3042         .dev_led_off = bnxt_dev_led_off_op,
3043         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3044         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3045         .rx_queue_count = bnxt_rx_queue_count_op,
3046         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3047         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3048         .rx_queue_start = bnxt_rx_queue_start,
3049         .rx_queue_stop = bnxt_rx_queue_stop,
3050         .tx_queue_start = bnxt_tx_queue_start,
3051         .tx_queue_stop = bnxt_tx_queue_stop,
3052         .filter_ctrl = bnxt_filter_ctrl_op,
3053         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3054         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3055         .get_eeprom           = bnxt_get_eeprom_op,
3056         .set_eeprom           = bnxt_set_eeprom_op,
3057         .timesync_enable      = bnxt_timesync_enable,
3058         .timesync_disable     = bnxt_timesync_disable,
3059         .timesync_read_time   = bnxt_timesync_read_time,
3060         .timesync_write_time   = bnxt_timesync_write_time,
3061         .timesync_adjust_time = bnxt_timesync_adjust_time,
3062         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3063         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3064 };
3065
3066 static bool bnxt_vf_pciid(uint16_t id)
3067 {
3068         if (id == BROADCOM_DEV_ID_57304_VF ||
3069             id == BROADCOM_DEV_ID_57406_VF ||
3070             id == BROADCOM_DEV_ID_5731X_VF ||
3071             id == BROADCOM_DEV_ID_5741X_VF ||
3072             id == BROADCOM_DEV_ID_57414_VF ||
3073             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3074             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3075                 return true;
3076         return false;
3077 }
3078
3079 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3080 {
3081         struct bnxt *bp = eth_dev->data->dev_private;
3082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3083         int rc;
3084
3085         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3086         if (!pci_dev->mem_resource[0].addr) {
3087                 PMD_DRV_LOG(ERR,
3088                         "Cannot find PCI device base address, aborting\n");
3089                 rc = -ENODEV;
3090                 goto init_err_disable;
3091         }
3092
3093         bp->eth_dev = eth_dev;
3094         bp->pdev = pci_dev;
3095
3096         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3097         if (!bp->bar0) {
3098                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3099                 rc = -ENOMEM;
3100                 goto init_err_release;
3101         }
3102
3103         if (!pci_dev->mem_resource[2].addr) {
3104                 PMD_DRV_LOG(ERR,
3105                             "Cannot find PCI device BAR 2 address, aborting\n");
3106                 rc = -ENODEV;
3107                 goto init_err_release;
3108         } else {
3109                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3110         }
3111
3112         return 0;
3113
3114 init_err_release:
3115         if (bp->bar0)
3116                 bp->bar0 = NULL;
3117         if (bp->doorbell_base)
3118                 bp->doorbell_base = NULL;
3119
3120 init_err_disable:
3121
3122         return rc;
3123 }
3124
3125 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3126
3127 #define ALLOW_FUNC(x)   \
3128         { \
3129                 typeof(x) arg = (x); \
3130                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3131                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3132         }
3133 static int
3134 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3135 {
3136         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3137         char mz_name[RTE_MEMZONE_NAMESIZE];
3138         const struct rte_memzone *mz = NULL;
3139         static int version_printed;
3140         uint32_t total_alloc_len;
3141         rte_iova_t mz_phys_addr;
3142         struct bnxt *bp;
3143         int rc;
3144
3145         if (version_printed++ == 0)
3146                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3147
3148         rte_eth_copy_pci_info(eth_dev, pci_dev);
3149
3150         bp = eth_dev->data->dev_private;
3151
3152         bp->dev_stopped = 1;
3153
3154         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3155                 goto skip_init;
3156
3157         if (bnxt_vf_pciid(pci_dev->id.device_id))
3158                 bp->flags |= BNXT_FLAG_VF;
3159
3160         rc = bnxt_init_board(eth_dev);
3161         if (rc) {
3162                 PMD_DRV_LOG(ERR,
3163                         "Board initialization failed rc: %x\n", rc);
3164                 goto error;
3165         }
3166 skip_init:
3167         eth_dev->dev_ops = &bnxt_dev_ops;
3168         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3169                 return 0;
3170         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3171         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3172
3173         if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3174                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3175                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3176                          pci_dev->addr.bus, pci_dev->addr.devid,
3177                          pci_dev->addr.function, "rx_port_stats");
3178                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3179                 mz = rte_memzone_lookup(mz_name);
3180                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3181                                 sizeof(struct rx_port_stats) + 512);
3182                 if (!mz) {
3183                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3184                                         SOCKET_ID_ANY,
3185                                         RTE_MEMZONE_2MB |
3186                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3187                                         RTE_MEMZONE_IOVA_CONTIG);
3188                         if (mz == NULL)
3189                                 return -ENOMEM;
3190                 }
3191                 memset(mz->addr, 0, mz->len);
3192                 mz_phys_addr = mz->iova;
3193                 if ((unsigned long)mz->addr == mz_phys_addr) {
3194                         PMD_DRV_LOG(WARNING,
3195                                 "Memzone physical address same as virtual.\n");
3196                         PMD_DRV_LOG(WARNING,
3197                                 "Using rte_mem_virt2iova()\n");
3198                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3199                         if (mz_phys_addr == 0) {
3200                                 PMD_DRV_LOG(ERR,
3201                                 "unable to map address to physical memory\n");
3202                                 return -ENOMEM;
3203                         }
3204                 }
3205
3206                 bp->rx_mem_zone = (const void *)mz;
3207                 bp->hw_rx_port_stats = mz->addr;
3208                 bp->hw_rx_port_stats_map = mz_phys_addr;
3209
3210                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3211                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3212                          pci_dev->addr.bus, pci_dev->addr.devid,
3213                          pci_dev->addr.function, "tx_port_stats");
3214                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3215                 mz = rte_memzone_lookup(mz_name);
3216                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3217                                 sizeof(struct tx_port_stats) + 512);
3218                 if (!mz) {
3219                         mz = rte_memzone_reserve(mz_name,
3220                                         total_alloc_len,
3221                                         SOCKET_ID_ANY,
3222                                         RTE_MEMZONE_2MB |
3223                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3224                                         RTE_MEMZONE_IOVA_CONTIG);
3225                         if (mz == NULL)
3226                                 return -ENOMEM;
3227                 }
3228                 memset(mz->addr, 0, mz->len);
3229                 mz_phys_addr = mz->iova;
3230                 if ((unsigned long)mz->addr == mz_phys_addr) {
3231                         PMD_DRV_LOG(WARNING,
3232                                 "Memzone physical address same as virtual.\n");
3233                         PMD_DRV_LOG(WARNING,
3234                                 "Using rte_mem_virt2iova()\n");
3235                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3236                         if (mz_phys_addr == 0) {
3237                                 PMD_DRV_LOG(ERR,
3238                                 "unable to map address to physical memory\n");
3239                                 return -ENOMEM;
3240                         }
3241                 }
3242
3243                 bp->tx_mem_zone = (const void *)mz;
3244                 bp->hw_tx_port_stats = mz->addr;
3245                 bp->hw_tx_port_stats_map = mz_phys_addr;
3246
3247                 bp->flags |= BNXT_FLAG_PORT_STATS;
3248         }
3249
3250         rc = bnxt_alloc_hwrm_resources(bp);
3251         if (rc) {
3252                 PMD_DRV_LOG(ERR,
3253                         "hwrm resource allocation failure rc: %x\n", rc);
3254                 goto error_free;
3255         }
3256         rc = bnxt_hwrm_ver_get(bp);
3257         if (rc)
3258                 goto error_free;
3259         rc = bnxt_hwrm_queue_qportcfg(bp);
3260         if (rc) {
3261                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3262                 goto error_free;
3263         }
3264
3265         rc = bnxt_hwrm_func_qcfg(bp);
3266         if (rc) {
3267                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3268                 goto error_free;
3269         }
3270
3271         /* Get the MAX capabilities for this function */
3272         rc = bnxt_hwrm_func_qcaps(bp);
3273         if (rc) {
3274                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3275                 goto error_free;
3276         }
3277         if (bp->max_tx_rings == 0) {
3278                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3279                 rc = -EBUSY;
3280                 goto error_free;
3281         }
3282         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3283                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3284         if (eth_dev->data->mac_addrs == NULL) {
3285                 PMD_DRV_LOG(ERR,
3286                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3287                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3288                 rc = -ENOMEM;
3289                 goto error_free;
3290         }
3291
3292         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3293                 PMD_DRV_LOG(ERR,
3294                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3295                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3296                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3297                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3298                 rc = -EINVAL;
3299                 goto error_free;
3300         }
3301         /* Copy the permanent MAC from the qcap response address now. */
3302         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3303         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3304
3305         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3306                 /* 1 ring is for default completion ring */
3307                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3308                 rc = -ENOSPC;
3309                 goto error_free;
3310         }
3311
3312         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3313                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3314         if (!bp->grp_info) {
3315                 PMD_DRV_LOG(ERR,
3316                         "Failed to alloc %zu bytes to store group info table\n",
3317                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3318                 rc = -ENOMEM;
3319                 goto error_free;
3320         }
3321
3322         /* Forward all requests if firmware is new enough */
3323         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3324             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3325             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3326                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3327         } else {
3328                 PMD_DRV_LOG(WARNING,
3329                         "Firmware too old for VF mailbox functionality\n");
3330                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3331         }
3332
3333         /*
3334          * The following are used for driver cleanup.  If we disallow these,
3335          * VF drivers can't clean up cleanly.
3336          */
3337         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3338         ALLOW_FUNC(HWRM_VNIC_FREE);
3339         ALLOW_FUNC(HWRM_RING_FREE);
3340         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3341         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3342         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3343         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3344         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3345         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3346         rc = bnxt_hwrm_func_driver_register(bp);
3347         if (rc) {
3348                 PMD_DRV_LOG(ERR,
3349                         "Failed to register driver");
3350                 rc = -EBUSY;
3351                 goto error_free;
3352         }
3353
3354         PMD_DRV_LOG(INFO,
3355                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3356                 pci_dev->mem_resource[0].phys_addr,
3357                 pci_dev->mem_resource[0].addr);
3358
3359         rc = bnxt_hwrm_func_reset(bp);
3360         if (rc) {
3361                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3362                 rc = -EIO;
3363                 goto error_free;
3364         }
3365
3366         if (BNXT_PF(bp)) {
3367                 //if (bp->pf.active_vfs) {
3368                         // TODO: Deallocate VF resources?
3369                 //}
3370                 if (bp->pdev->max_vfs) {
3371                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3372                         if (rc) {
3373                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3374                                 goto error_free;
3375                         }
3376                 } else {
3377                         rc = bnxt_hwrm_allocate_pf_only(bp);
3378                         if (rc) {
3379                                 PMD_DRV_LOG(ERR,
3380                                         "Failed to allocate PF resources\n");
3381                                 goto error_free;
3382                         }
3383                 }
3384         }
3385
3386         bnxt_hwrm_port_led_qcaps(bp);
3387
3388         rc = bnxt_setup_int(bp);
3389         if (rc)
3390                 goto error_free;
3391
3392         rc = bnxt_alloc_mem(bp);
3393         if (rc)
3394                 goto error_free_int;
3395
3396         rc = bnxt_request_int(bp);
3397         if (rc)
3398                 goto error_free_int;
3399
3400         rc = bnxt_alloc_def_cp_ring(bp);
3401         if (rc)
3402                 goto error_free_int;
3403
3404         bnxt_enable_int(bp);
3405         bnxt_init_nic(bp);
3406
3407         return 0;
3408
3409 error_free_int:
3410         bnxt_disable_int(bp);
3411         bnxt_free_def_cp_ring(bp);
3412         bnxt_hwrm_func_buf_unrgtr(bp);
3413         bnxt_free_int(bp);
3414         bnxt_free_mem(bp);
3415 error_free:
3416         bnxt_dev_uninit(eth_dev);
3417 error:
3418         return rc;
3419 }
3420
3421 static int
3422 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3423         struct bnxt *bp = eth_dev->data->dev_private;
3424         int rc;
3425
3426         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3427                 return -EPERM;
3428
3429         bnxt_disable_int(bp);
3430         bnxt_free_int(bp);
3431         bnxt_free_mem(bp);
3432         if (eth_dev->data->mac_addrs != NULL) {
3433                 rte_free(eth_dev->data->mac_addrs);
3434                 eth_dev->data->mac_addrs = NULL;
3435         }
3436         if (bp->grp_info != NULL) {
3437                 rte_free(bp->grp_info);
3438                 bp->grp_info = NULL;
3439         }
3440         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3441         bnxt_free_hwrm_resources(bp);
3442         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3443         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3444         if (bp->dev_stopped == 0)
3445                 bnxt_dev_close_op(eth_dev);
3446         if (bp->pf.vf_info)
3447                 rte_free(bp->pf.vf_info);
3448         eth_dev->dev_ops = NULL;
3449         eth_dev->rx_pkt_burst = NULL;
3450         eth_dev->tx_pkt_burst = NULL;
3451
3452         return rc;
3453 }
3454
3455 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3456         struct rte_pci_device *pci_dev)
3457 {
3458         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3459                 bnxt_dev_init);
3460 }
3461
3462 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3463 {
3464         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3465 }
3466
3467 static struct rte_pci_driver bnxt_rte_pmd = {
3468         .id_table = bnxt_pci_id_map,
3469         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3470                 RTE_PCI_DRV_INTR_LSC,
3471         .probe = bnxt_pci_probe,
3472         .remove = bnxt_pci_remove,
3473 };
3474
3475 static bool
3476 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3477 {
3478         if (strcmp(dev->device->driver->name, drv->driver.name))
3479                 return false;
3480
3481         return true;
3482 }
3483
3484 bool is_bnxt_supported(struct rte_eth_dev *dev)
3485 {
3486         return is_device_supported(dev, &bnxt_rte_pmd);
3487 }
3488
3489 RTE_INIT(bnxt_init_log);
3490 static void
3491 bnxt_init_log(void)
3492 {
3493         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3494         if (bnxt_logtype_driver >= 0)
3495                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3496 }
3497
3498 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3499 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3500 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");