drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  79 #define BROADCOM_DEV_ID_58802 0xd802
  80 #define BROADCOM_DEV_ID_58804 0xd804
  81 #define BROADCOM_DEV_ID_58808 0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF 0xd800
  83
  84 static const struct rte_pci_id bnxt_pci_id_map[] = {
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  86                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  88                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 132         { .vendor_id = 0, /* sentinel */ },
 133 };
 134
 135 #define BNXT_ETH_RSS_SUPPORT (  \
 136         ETH_RSS_IPV4 |          \
 137         ETH_RSS_NONFRAG_IPV4_TCP |      \
 138         ETH_RSS_NONFRAG_IPV4_UDP |      \
 139         ETH_RSS_IPV6 |          \
 140         ETH_RSS_NONFRAG_IPV6_TCP |      \
 141         ETH_RSS_NONFRAG_IPV6_UDP)
 142
 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 144                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_TCP_TSO | \
 148                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 149                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_TCP_LRO)
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         bnxt_free_stats(bp);
 201         bnxt_free_tx_rings(bp);
 202         bnxt_free_rx_rings(bp);
 203 }
 204
 205 static int bnxt_alloc_mem(struct bnxt *bp)
 206 {
 207         int rc;
 208
 209         rc = bnxt_alloc_vnic_mem(bp);
 210         if (rc)
 211                 goto alloc_mem_err;
 212
 213         rc = bnxt_alloc_vnic_attributes(bp);
 214         if (rc)
 215                 goto alloc_mem_err;
 216
 217         rc = bnxt_alloc_filter_mem(bp);
 218         if (rc)
 219                 goto alloc_mem_err;
 220
 221         return 0;
 222
 223 alloc_mem_err:
 224         bnxt_free_mem(bp);
 225         return rc;
 226 }
 227
 228 static int bnxt_init_chip(struct bnxt *bp)
 229 {
 230         struct bnxt_rx_queue *rxq;
 231         struct rte_eth_link new;
 232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 233         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 235         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 236         uint32_t intr_vector = 0;
 237         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 238         uint32_t vec = BNXT_MISC_VEC_ID;
 239         unsigned int i, j;
 240         int rc;
 241
 242         /* disable uio/vfio intr/eventfd mapping */
 243         rte_intr_disable(intr_handle);
 244
 245         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 246                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 247                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 248                 bp->flags |= BNXT_FLAG_JUMBO;
 249         } else {
 250                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 251                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 252                 bp->flags &= ~BNXT_FLAG_JUMBO;
 253         }
 254
 255         /* THOR does not support ring groups.
 256          * But we will use the array to save RSS context IDs.
 257          */
 258         if (BNXT_CHIP_THOR(bp))
 259                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 260
 261         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 262         if (rc) {
 263                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 264                 goto err_out;
 265         }
 266
 267         rc = bnxt_alloc_hwrm_rings(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         rc = bnxt_mq_rx_configure(bp);
 280         if (rc) {
 281                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 282                 goto err_out;
 283         }
 284
 285         /* VNIC configuration */
 286         for (i = 0; i < bp->nr_vnics; i++) {
 287                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 288                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 289                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 290
 291                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 292                 if (!vnic->fw_grp_ids) {
 293                         PMD_DRV_LOG(ERR,
 294                                     "Failed to alloc %d bytes for group ids\n",
 295                                     size);
 296                         rc = -ENOMEM;
 297                         goto err_out;
 298                 }
 299                 memset(vnic->fw_grp_ids, -1, size);
 300
 301                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 302                             i, vnic, vnic->fw_grp_ids);
 303
 304                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 305                 if (rc) {
 306                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 307                                 i, rc);
 308                         goto err_out;
 309                 }
 310
 311                 /* Alloc RSS context only if RSS mode is enabled */
 312                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 313                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 314
 315                         rc = 0;
 316                         for (j = 0; j < nr_ctxs; j++) {
 317                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 318                                 if (rc)
 319                                         break;
 320                         }
 321                         if (rc) {
 322                                 PMD_DRV_LOG(ERR,
 323                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 324                                   i, j, rc);
 325                                 goto err_out;
 326                         }
 327                         vnic->num_lb_ctxts = nr_ctxs;
 328                 }
 329
 330                 /*
 331                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 332                  * setting is not available at this time, it will not be
 333                  * configured correctly in the CFA.
 334                  */
 335                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 336                         vnic->vlan_strip = true;
 337                 else
 338                         vnic->vlan_strip = false;
 339
 340                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 341                 if (rc) {
 342                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 343                                 i, rc);
 344                         goto err_out;
 345                 }
 346
 347                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 348                 if (rc) {
 349                         PMD_DRV_LOG(ERR,
 350                                 "HWRM vnic %d filter failure rc: %x\n",
 351                                 i, rc);
 352                         goto err_out;
 353                 }
 354
 355                 for (j = 0; j < bp->rx_nr_rings; j++) {
 356                         rxq = bp->eth_dev->data->rx_queues[j];
 357
 358                         PMD_DRV_LOG(DEBUG,
 359                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 360                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 361
 362                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 363                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 364                 }
 365
 366                 rc = bnxt_vnic_rss_configure(bp, vnic);
 367                 if (rc) {
 368                         PMD_DRV_LOG(ERR,
 369                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 370                         goto err_out;
 371                 }
 372
 373                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 374
 375                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 376                     DEV_RX_OFFLOAD_TCP_LRO)
 377                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 378                 else
 379                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 380         }
 381         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 382         if (rc) {
 383                 PMD_DRV_LOG(ERR,
 384                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 385                 goto err_out;
 386         }
 387
 388         /* check and configure queue intr-vector mapping */
 389         if ((rte_intr_cap_multiple(intr_handle) ||
 390              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 391             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 392                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 393                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 394                 if (intr_vector > bp->rx_cp_nr_rings) {
 395                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 396                                         bp->rx_cp_nr_rings);
 397                         return -ENOTSUP;
 398                 }
 399                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 400                 if (rc)
 401                         return rc;
 402         }
 403
 404         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 405                 intr_handle->intr_vec =
 406                         rte_zmalloc("intr_vec",
 407                                     bp->eth_dev->data->nb_rx_queues *
 408                                     sizeof(int), 0);
 409                 if (intr_handle->intr_vec == NULL) {
 410                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 411                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 412                         rc = -ENOMEM;
 413                         goto err_disable;
 414                 }
 415                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 416                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 417                          intr_handle->intr_vec, intr_handle->nb_efd,
 418                         intr_handle->max_intr);
 419                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 420                      queue_id++) {
 421                         intr_handle->intr_vec[queue_id] =
 422                                                         vec + BNXT_RX_VEC_START;
 423                         if (vec < base + intr_handle->nb_efd - 1)
 424                                 vec++;
 425                 }
 426         }
 427
 428         /* enable uio/vfio intr/eventfd mapping */
 429         rc = rte_intr_enable(intr_handle);
 430         if (rc)
 431                 goto err_free;
 432
 433         rc = bnxt_get_hwrm_link_config(bp, &new);
 434         if (rc) {
 435                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 436                 goto err_free;
 437         }
 438
 439         if (!bp->link_info.link_up) {
 440                 rc = bnxt_set_hwrm_link_config(bp, true);
 441                 if (rc) {
 442                         PMD_DRV_LOG(ERR,
 443                                 "HWRM link config failure rc: %x\n", rc);
 444                         goto err_free;
 445                 }
 446         }
 447         bnxt_print_link_info(bp->eth_dev);
 448
 449         return 0;
 450
 451 err_free:
 452         rte_free(intr_handle->intr_vec);
 453 err_disable:
 454         rte_intr_efd_disable(intr_handle);
 455 err_out:
 456         /* Some of the error status returned by FW may not be from errno.h */
 457         if (rc > 0)
 458                 rc = -EIO;
 459
 460         return rc;
 461 }
 462
 463 static int bnxt_shutdown_nic(struct bnxt *bp)
 464 {
 465         bnxt_free_all_hwrm_resources(bp);
 466         bnxt_free_all_filters(bp);
 467         bnxt_free_all_vnics(bp);
 468         return 0;
 469 }
 470
 471 static int bnxt_init_nic(struct bnxt *bp)
 472 {
 473         int rc;
 474
 475         if (BNXT_HAS_RING_GRPS(bp)) {
 476                 rc = bnxt_init_ring_grps(bp);
 477                 if (rc)
 478                         return rc;
 479         }
 480
 481         bnxt_init_vnics(bp);
 482         bnxt_init_filters(bp);
 483
 484         return 0;
 485 }
 486
 487 /*
 488  * Device configuration and status function
 489  */
 490
 491 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 492                                   struct rte_eth_dev_info *dev_info)
 493 {
 494         struct bnxt *bp = eth_dev->data->dev_private;
 495         uint16_t max_vnics, i, j, vpool, vrxq;
 496         unsigned int max_rx_rings;
 497
 498         /* MAC Specifics */
 499         dev_info->max_mac_addrs = bp->max_l2_ctx;
 500         dev_info->max_hash_mac_addrs = 0;
 501
 502         /* PF/VF specifics */
 503         if (BNXT_PF(bp))
 504                 dev_info->max_vfs = bp->pdev->max_vfs;
 505         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 506         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 507         dev_info->max_rx_queues = max_rx_rings;
 508         dev_info->max_tx_queues = max_rx_rings;
 509         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 510         dev_info->hash_key_size = 40;
 511         max_vnics = bp->max_vnics;
 512
 513         /* Fast path specifics */
 514         dev_info->min_rx_bufsize = 1;
 515         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 516                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 517
 518         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 519         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 520                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 521         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 522         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 523
 524         /* *INDENT-OFF* */
 525         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 526                 .rx_thresh = {
 527                         .pthresh = 8,
 528                         .hthresh = 8,
 529                         .wthresh = 0,
 530                 },
 531                 .rx_free_thresh = 32,
 532                 /* If no descriptors available, pkts are dropped by default */
 533                 .rx_drop_en = 1,
 534         };
 535
 536         dev_info->default_txconf = (struct rte_eth_txconf) {
 537                 .tx_thresh = {
 538                         .pthresh = 32,
 539                         .hthresh = 0,
 540                         .wthresh = 0,
 541                 },
 542                 .tx_free_thresh = 32,
 543                 .tx_rs_thresh = 32,
 544         };
 545         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 546
 547         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 548         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 549         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 550         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 551         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 552
 553         /* *INDENT-ON* */
 554
 555         /*
 556          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 557          *       need further investigation.
 558          */
 559
 560         /* VMDq resources */
 561         vpool = 64; /* ETH_64_POOLS */
 562         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 563         for (i = 0; i < 4; vpool >>= 1, i++) {
 564                 if (max_vnics > vpool) {
 565                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 566                                 if (dev_info->max_rx_queues > vrxq) {
 567                                         if (vpool > vrxq)
 568                                                 vpool = vrxq;
 569                                         goto found;
 570                                 }
 571                         }
 572                         /* Not enough resources to support VMDq */
 573                         break;
 574                 }
 575         }
 576         /* Not enough resources to support VMDq */
 577         vpool = 0;
 578         vrxq = 0;
 579 found:
 580         dev_info->max_vmdq_pools = vpool;
 581         dev_info->vmdq_queue_num = vrxq;
 582
 583         dev_info->vmdq_pool_base = 0;
 584         dev_info->vmdq_queue_base = 0;
 585 }
 586
 587 /* Configure the device based on the configuration provided */
 588 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 589 {
 590         struct bnxt *bp = eth_dev->data->dev_private;
 591         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 592         int rc;
 593
 594         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 595         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 596         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 597         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 598
 599         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 600                 rc = bnxt_hwrm_check_vf_rings(bp);
 601                 if (rc) {
 602                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 603                         return -ENOSPC;
 604                 }
 605
 606                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 607                 if (rc) {
 608                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 609                         return -ENOSPC;
 610                 }
 611         } else {
 612                 /* legacy driver needs to get updated values */
 613                 rc = bnxt_hwrm_func_qcaps(bp);
 614                 if (rc) {
 615                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 616                         return rc;
 617                 }
 618         }
 619
 620         /* Inherit new configurations */
 621         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 622             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 623             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 624             bp->max_cp_rings ||
 625             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 626             bp->max_stat_ctx)
 627                 goto resource_error;
 628
 629         if (BNXT_HAS_RING_GRPS(bp) &&
 630             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 631                 goto resource_error;
 632
 633         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 634             bp->max_vnics < eth_dev->data->nb_rx_queues)
 635                 goto resource_error;
 636
 637         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 638         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 639
 640         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 641                 eth_dev->data->mtu =
 642                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 643                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 644                         BNXT_NUM_VLANS;
 645                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 646         }
 647         return 0;
 648
 649 resource_error:
 650         PMD_DRV_LOG(ERR,
 651                     "Insufficient resources to support requested config\n");
 652         PMD_DRV_LOG(ERR,
 653                     "Num Queues Requested: Tx %d, Rx %d\n",
 654                     eth_dev->data->nb_tx_queues,
 655                     eth_dev->data->nb_rx_queues);
 656         PMD_DRV_LOG(ERR,
 657                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 658                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 659                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 660         return -ENOSPC;
 661 }
 662
 663 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 664 {
 665         struct rte_eth_link *link = &eth_dev->data->dev_link;
 666
 667         if (link->link_status)
 668                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 669                         eth_dev->data->port_id,
 670                         (uint32_t)link->link_speed,
 671                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 672                         ("full-duplex") : ("half-duplex\n"));
 673         else
 674                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 675                         eth_dev->data->port_id);
 676 }
 677
 678 /*
 679  * Determine whether the current configuration requires support for scattered
 680  * receive; return 1 if scattered receive is required and 0 if not.
 681  */
 682 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 683 {
 684         uint16_t buf_size;
 685         int i;
 686
 687         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 688                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 689
 690                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 691                                       RTE_PKTMBUF_HEADROOM);
 692                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 693                         return 1;
 694         }
 695         return 0;
 696 }
 697
 698 static eth_rx_burst_t
 699 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 700 {
 701 #ifdef RTE_ARCH_X86
 702         /*
 703          * Vector mode receive can be enabled only if scatter rx is not
 704          * in use and rx offloads are limited to VLAN stripping and
 705          * CRC stripping.
 706          */
 707         if (!eth_dev->data->scattered_rx &&
 708             !(eth_dev->data->dev_conf.rxmode.offloads &
 709               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 710                 DEV_RX_OFFLOAD_KEEP_CRC |
 711                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 712                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 713                 DEV_RX_OFFLOAD_UDP_CKSUM |
 714                 DEV_RX_OFFLOAD_TCP_CKSUM |
 715                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 716                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 717                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 718                             eth_dev->data->port_id);
 719                 return bnxt_recv_pkts_vec;
 720         }
 721         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 722                     eth_dev->data->port_id);
 723         PMD_DRV_LOG(INFO,
 724                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 725                     eth_dev->data->port_id,
 726                     eth_dev->data->scattered_rx,
 727                     eth_dev->data->dev_conf.rxmode.offloads);
 728 #endif
 729         return bnxt_recv_pkts;
 730 }
 731
 732 static eth_tx_burst_t
 733 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 734 {
 735 #ifdef RTE_ARCH_X86
 736         /*
 737          * Vector mode transmit can be enabled only if not using scatter rx
 738          * or tx offloads.
 739          */
 740         if (!eth_dev->data->scattered_rx &&
 741             !eth_dev->data->dev_conf.txmode.offloads) {
 742                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 743                             eth_dev->data->port_id);
 744                 return bnxt_xmit_pkts_vec;
 745         }
 746         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 747                     eth_dev->data->port_id);
 748         PMD_DRV_LOG(INFO,
 749                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 750                     eth_dev->data->port_id,
 751                     eth_dev->data->scattered_rx,
 752                     eth_dev->data->dev_conf.txmode.offloads);
 753 #endif
 754         return bnxt_xmit_pkts;
 755 }
 756
 757 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 758 {
 759         struct bnxt *bp = eth_dev->data->dev_private;
 760         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 761         int vlan_mask = 0;
 762         int rc;
 763
 764         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 765                 PMD_DRV_LOG(ERR,
 766                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 767                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 768         }
 769
 770         rc = bnxt_init_chip(bp);
 771         if (rc)
 772                 goto error;
 773
 774         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 775
 776         bnxt_link_update_op(eth_dev, 1);
 777
 778         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 779                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 780         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 781                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 782         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 783         if (rc)
 784                 goto error;
 785
 786         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 787         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 788         bnxt_enable_int(bp);
 789         bp->flags |= BNXT_FLAG_INIT_DONE;
 790         bp->dev_stopped = 0;
 791         return 0;
 792
 793 error:
 794         bnxt_shutdown_nic(bp);
 795         bnxt_free_tx_mbufs(bp);
 796         bnxt_free_rx_mbufs(bp);
 797         return rc;
 798 }
 799
 800 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 801 {
 802         struct bnxt *bp = eth_dev->data->dev_private;
 803         int rc = 0;
 804
 805         if (!bp->link_info.link_up)
 806                 rc = bnxt_set_hwrm_link_config(bp, true);
 807         if (!rc)
 808                 eth_dev->data->dev_link.link_status = 1;
 809
 810         bnxt_print_link_info(eth_dev);
 811         return 0;
 812 }
 813
 814 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 815 {
 816         struct bnxt *bp = eth_dev->data->dev_private;
 817
 818         eth_dev->data->dev_link.link_status = 0;
 819         bnxt_set_hwrm_link_config(bp, false);
 820         bp->link_info.link_up = 0;
 821
 822         return 0;
 823 }
 824
 825 /* Unload the driver, release resources */
 826 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 827 {
 828         struct bnxt *bp = eth_dev->data->dev_private;
 829         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 830         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 831
 832         bnxt_disable_int(bp);
 833
 834         /* disable uio/vfio intr/eventfd mapping */
 835         rte_intr_disable(intr_handle);
 836
 837         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 838         if (bp->eth_dev->data->dev_started) {
 839                 /* TBD: STOP HW queues DMA */
 840                 eth_dev->data->dev_link.link_status = 0;
 841         }
 842         bnxt_set_hwrm_link_config(bp, false);
 843
 844         /* Clean queue intr-vector mapping */
 845         rte_intr_efd_disable(intr_handle);
 846         if (intr_handle->intr_vec != NULL) {
 847                 rte_free(intr_handle->intr_vec);
 848                 intr_handle->intr_vec = NULL;
 849         }
 850
 851         bnxt_hwrm_port_clr_stats(bp);
 852         bnxt_free_tx_mbufs(bp);
 853         bnxt_free_rx_mbufs(bp);
 854         bnxt_shutdown_nic(bp);
 855         bp->dev_stopped = 1;
 856 }
 857
 858 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 859 {
 860         struct bnxt *bp = eth_dev->data->dev_private;
 861
 862         if (bp->dev_stopped == 0)
 863                 bnxt_dev_stop_op(eth_dev);
 864
 865         if (eth_dev->data->mac_addrs != NULL) {
 866                 rte_free(eth_dev->data->mac_addrs);
 867                 eth_dev->data->mac_addrs = NULL;
 868         }
 869         if (bp->grp_info != NULL) {
 870                 rte_free(bp->grp_info);
 871                 bp->grp_info = NULL;
 872         }
 873
 874         bnxt_dev_uninit(eth_dev);
 875 }
 876
 877 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 878                                     uint32_t index)
 879 {
 880         struct bnxt *bp = eth_dev->data->dev_private;
 881         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 882         struct bnxt_vnic_info *vnic;
 883         struct bnxt_filter_info *filter, *temp_filter;
 884         uint32_t i;
 885
 886         /*
 887          * Loop through all VNICs from the specified filter flow pools to
 888          * remove the corresponding MAC addr filter
 889          */
 890         for (i = 0; i < bp->nr_vnics; i++) {
 891                 if (!(pool_mask & (1ULL << i)))
 892                         continue;
 893
 894                 vnic = &bp->vnic_info[i];
 895                 filter = STAILQ_FIRST(&vnic->filter);
 896                 while (filter) {
 897                         temp_filter = STAILQ_NEXT(filter, next);
 898                         if (filter->mac_index == index) {
 899                                 STAILQ_REMOVE(&vnic->filter, filter,
 900                                                 bnxt_filter_info, next);
 901                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 902                                 filter->mac_index = INVALID_MAC_INDEX;
 903                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 904                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 905                                                    filter, next);
 906                         }
 907                         filter = temp_filter;
 908                 }
 909         }
 910 }
 911
 912 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 913                                 struct rte_ether_addr *mac_addr,
 914                                 uint32_t index, uint32_t pool)
 915 {
 916         struct bnxt *bp = eth_dev->data->dev_private;
 917         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 918         struct bnxt_filter_info *filter;
 919         int rc = 0;
 920
 921         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 922                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 923                 return -ENOTSUP;
 924         }
 925
 926         if (!vnic) {
 927                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 928                 return -EINVAL;
 929         }
 930         /* Attach requested MAC address to the new l2_filter */
 931         STAILQ_FOREACH(filter, &vnic->filter, next) {
 932                 if (filter->mac_index == index) {
 933                         PMD_DRV_LOG(ERR,
 934                                 "MAC addr already existed for pool %d\n", pool);
 935                         return 0;
 936                 }
 937         }
 938         filter = bnxt_alloc_filter(bp);
 939         if (!filter) {
 940                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 941                 return -ENODEV;
 942         }
 943
 944         filter->mac_index = index;
 945         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 946
 947         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 948         if (!rc) {
 949                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 950         } else {
 951                 filter->mac_index = INVALID_MAC_INDEX;
 952                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 953                 bnxt_free_filter(bp, filter);
 954         }
 955
 956         return rc;
 957 }
 958
 959 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 960 {
 961         int rc = 0;
 962         struct bnxt *bp = eth_dev->data->dev_private;
 963         struct rte_eth_link new;
 964         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 965
 966         memset(&new, 0, sizeof(new));
 967         do {
 968                 /* Retrieve link info from hardware */
 969                 rc = bnxt_get_hwrm_link_config(bp, &new);
 970                 if (rc) {
 971                         new.link_speed = ETH_LINK_SPEED_100M;
 972                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 973                         PMD_DRV_LOG(ERR,
 974                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 975                         goto out;
 976                 }
 977
 978                 if (!wait_to_complete || new.link_status)
 979                         break;
 980
 981                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 982         } while (cnt--);
 983
 984 out:
 985         /* Timed out or success */
 986         if (new.link_status != eth_dev->data->dev_link.link_status ||
 987         new.link_speed != eth_dev->data->dev_link.link_speed) {
 988                 memcpy(&eth_dev->data->dev_link, &new,
 989                         sizeof(struct rte_eth_link));
 990
 991                 _rte_eth_dev_callback_process(eth_dev,
 992                                               RTE_ETH_EVENT_INTR_LSC,
 993                                               NULL);
 994
 995                 bnxt_print_link_info(eth_dev);
 996         }
 997
 998         return rc;
 999 }
1000
1001 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004         struct bnxt_vnic_info *vnic;
1005
1006         if (bp->vnic_info == NULL)
1007                 return;
1008
1009         vnic = &bp->vnic_info[0];
1010
1011         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1012         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1013 }
1014
1015 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1016 {
1017         struct bnxt *bp = eth_dev->data->dev_private;
1018         struct bnxt_vnic_info *vnic;
1019
1020         if (bp->vnic_info == NULL)
1021                 return;
1022
1023         vnic = &bp->vnic_info[0];
1024
1025         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1026         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1027 }
1028
1029 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1030 {
1031         struct bnxt *bp = eth_dev->data->dev_private;
1032         struct bnxt_vnic_info *vnic;
1033
1034         if (bp->vnic_info == NULL)
1035                 return;
1036
1037         vnic = &bp->vnic_info[0];
1038
1039         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1040         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1041 }
1042
1043 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1044 {
1045         struct bnxt *bp = eth_dev->data->dev_private;
1046         struct bnxt_vnic_info *vnic;
1047
1048         if (bp->vnic_info == NULL)
1049                 return;
1050
1051         vnic = &bp->vnic_info[0];
1052
1053         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1054         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1055 }
1056
1057 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1058 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1059 {
1060         if (qid >= bp->rx_nr_rings)
1061                 return NULL;
1062
1063         return bp->eth_dev->data->rx_queues[qid];
1064 }
1065
1066 /* Return rxq corresponding to a given rss table ring/group ID. */
1067 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1068 {
1069         struct bnxt_rx_queue *rxq;
1070         unsigned int i;
1071
1072         if (!BNXT_HAS_RING_GRPS(bp)) {
1073                 for (i = 0; i < bp->rx_nr_rings; i++) {
1074                         rxq = bp->eth_dev->data->rx_queues[i];
1075                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1076                                 return rxq->index;
1077                 }
1078         } else {
1079                 for (i = 0; i < bp->rx_nr_rings; i++) {
1080                         if (bp->grp_info[i].fw_grp_id == fwr)
1081                                 return i;
1082                 }
1083         }
1084
1085         return INVALID_HW_RING_ID;
1086 }
1087
1088 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1089                             struct rte_eth_rss_reta_entry64 *reta_conf,
1090                             uint16_t reta_size)
1091 {
1092         struct bnxt *bp = eth_dev->data->dev_private;
1093         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1094         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1095         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1096         uint16_t idx, sft;
1097         int i;
1098
1099         if (!vnic->rss_table)
1100                 return -EINVAL;
1101
1102         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1103                 return -EINVAL;
1104
1105         if (reta_size != tbl_size) {
1106                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1107                         "(%d) must equal the size supported by the hardware "
1108                         "(%d)\n", reta_size, tbl_size);
1109                 return -EINVAL;
1110         }
1111
1112         for (i = 0; i < reta_size; i++) {
1113                 struct bnxt_rx_queue *rxq;
1114
1115                 idx = i / RTE_RETA_GROUP_SIZE;
1116                 sft = i % RTE_RETA_GROUP_SIZE;
1117
1118                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1119                         continue;
1120
1121                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1122                 if (!rxq) {
1123                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1124                         return -EINVAL;
1125                 }
1126
1127                 if (BNXT_CHIP_THOR(bp)) {
1128                         vnic->rss_table[i * 2] =
1129                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1130                         vnic->rss_table[i * 2 + 1] =
1131                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1132                 } else {
1133                         vnic->rss_table[i] =
1134                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1135                 }
1136
1137                 vnic->rss_table[i] =
1138                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1139         }
1140
1141         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1142         return 0;
1143 }
1144
1145 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1146                               struct rte_eth_rss_reta_entry64 *reta_conf,
1147                               uint16_t reta_size)
1148 {
1149         struct bnxt *bp = eth_dev->data->dev_private;
1150         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1151         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1152         uint16_t idx, sft, i;
1153
1154         /* Retrieve from the default VNIC */
1155         if (!vnic)
1156                 return -EINVAL;
1157         if (!vnic->rss_table)
1158                 return -EINVAL;
1159
1160         if (reta_size != tbl_size) {
1161                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1162                         "(%d) must equal the size supported by the hardware "
1163                         "(%d)\n", reta_size, tbl_size);
1164                 return -EINVAL;
1165         }
1166
1167         for (idx = 0, i = 0; i < reta_size; i++) {
1168                 idx = i / RTE_RETA_GROUP_SIZE;
1169                 sft = i % RTE_RETA_GROUP_SIZE;
1170
1171                 if (reta_conf[idx].mask & (1ULL << sft)) {
1172                         uint16_t qid;
1173
1174                         if (BNXT_CHIP_THOR(bp))
1175                                 qid = bnxt_rss_to_qid(bp,
1176                                                       vnic->rss_table[i * 2]);
1177                         else
1178                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1179
1180                         if (qid == INVALID_HW_RING_ID) {
1181                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1182                                 return -EINVAL;
1183                         }
1184                         reta_conf[idx].reta[sft] = qid;
1185                 }
1186         }
1187
1188         return 0;
1189 }
1190
1191 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1192                                    struct rte_eth_rss_conf *rss_conf)
1193 {
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1196         struct bnxt_vnic_info *vnic;
1197         uint16_t hash_type = 0;
1198         unsigned int i;
1199
1200         /*
1201          * If RSS enablement were different than dev_configure,
1202          * then return -EINVAL
1203          */
1204         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1205                 if (!rss_conf->rss_hf)
1206                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1207         } else {
1208                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1209                         return -EINVAL;
1210         }
1211
1212         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1213         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1214
1215         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1216                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1217         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1218                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1219         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1220                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1221         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1222                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1223         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1224                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1225         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1226                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1227
1228         /* Update the RSS VNIC(s) */
1229         for (i = 0; i < bp->nr_vnics; i++) {
1230                 vnic = &bp->vnic_info[i];
1231                 vnic->hash_type = hash_type;
1232
1233                 /*
1234                  * Use the supplied key if the key length is
1235                  * acceptable and the rss_key is not NULL
1236                  */
1237                 if (rss_conf->rss_key &&
1238                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1239                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1240                                rss_conf->rss_key_len);
1241
1242                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1243         }
1244         return 0;
1245 }
1246
1247 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1248                                      struct rte_eth_rss_conf *rss_conf)
1249 {
1250         struct bnxt *bp = eth_dev->data->dev_private;
1251         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1252         int len;
1253         uint32_t hash_types;
1254
1255         /* RSS configuration is the same for all VNICs */
1256         if (vnic && vnic->rss_hash_key) {
1257                 if (rss_conf->rss_key) {
1258                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1259                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1260                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1261                 }
1262
1263                 hash_types = vnic->hash_type;
1264                 rss_conf->rss_hf = 0;
1265                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1266                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1267                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1268                 }
1269                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1270                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1271                         hash_types &=
1272                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1273                 }
1274                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1275                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1276                         hash_types &=
1277                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1278                 }
1279                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1280                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1281                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1282                 }
1283                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1284                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1285                         hash_types &=
1286                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1287                 }
1288                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1289                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1290                         hash_types &=
1291                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1292                 }
1293                 if (hash_types) {
1294                         PMD_DRV_LOG(ERR,
1295                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1296                                 vnic->hash_type);
1297                         return -ENOTSUP;
1298                 }
1299         } else {
1300                 rss_conf->rss_hf = 0;
1301         }
1302         return 0;
1303 }
1304
1305 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1306                                struct rte_eth_fc_conf *fc_conf)
1307 {
1308         struct bnxt *bp = dev->data->dev_private;
1309         struct rte_eth_link link_info;
1310         int rc;
1311
1312         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1313         if (rc)
1314                 return rc;
1315
1316         memset(fc_conf, 0, sizeof(*fc_conf));
1317         if (bp->link_info.auto_pause)
1318                 fc_conf->autoneg = 1;
1319         switch (bp->link_info.pause) {
1320         case 0:
1321                 fc_conf->mode = RTE_FC_NONE;
1322                 break;
1323         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1324                 fc_conf->mode = RTE_FC_TX_PAUSE;
1325                 break;
1326         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1327                 fc_conf->mode = RTE_FC_RX_PAUSE;
1328                 break;
1329         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1330                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1331                 fc_conf->mode = RTE_FC_FULL;
1332                 break;
1333         }
1334         return 0;
1335 }
1336
1337 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1338                                struct rte_eth_fc_conf *fc_conf)
1339 {
1340         struct bnxt *bp = dev->data->dev_private;
1341
1342         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1343                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1344                 return -ENOTSUP;
1345         }
1346
1347         switch (fc_conf->mode) {
1348         case RTE_FC_NONE:
1349                 bp->link_info.auto_pause = 0;
1350                 bp->link_info.force_pause = 0;
1351                 break;
1352         case RTE_FC_RX_PAUSE:
1353                 if (fc_conf->autoneg) {
1354                         bp->link_info.auto_pause =
1355                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1356                         bp->link_info.force_pause = 0;
1357                 } else {
1358                         bp->link_info.auto_pause = 0;
1359                         bp->link_info.force_pause =
1360                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1361                 }
1362                 break;
1363         case RTE_FC_TX_PAUSE:
1364                 if (fc_conf->autoneg) {
1365                         bp->link_info.auto_pause =
1366                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1367                         bp->link_info.force_pause = 0;
1368                 } else {
1369                         bp->link_info.auto_pause = 0;
1370                         bp->link_info.force_pause =
1371                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1372                 }
1373                 break;
1374         case RTE_FC_FULL:
1375                 if (fc_conf->autoneg) {
1376                         bp->link_info.auto_pause =
1377                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1378                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1379                         bp->link_info.force_pause = 0;
1380                 } else {
1381                         bp->link_info.auto_pause = 0;
1382                         bp->link_info.force_pause =
1383                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1384                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1385                 }
1386                 break;
1387         }
1388         return bnxt_set_hwrm_link_config(bp, true);
1389 }
1390
1391 /* Add UDP tunneling port */
1392 static int
1393 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1394                          struct rte_eth_udp_tunnel *udp_tunnel)
1395 {
1396         struct bnxt *bp = eth_dev->data->dev_private;
1397         uint16_t tunnel_type = 0;
1398         int rc = 0;
1399
1400         switch (udp_tunnel->prot_type) {
1401         case RTE_TUNNEL_TYPE_VXLAN:
1402                 if (bp->vxlan_port_cnt) {
1403                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1404                                 udp_tunnel->udp_port);
1405                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1406                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1407                                 return -ENOSPC;
1408                         }
1409                         bp->vxlan_port_cnt++;
1410                         return 0;
1411                 }
1412                 tunnel_type =
1413                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1414                 bp->vxlan_port_cnt++;
1415                 break;
1416         case RTE_TUNNEL_TYPE_GENEVE:
1417                 if (bp->geneve_port_cnt) {
1418                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1419                                 udp_tunnel->udp_port);
1420                         if (bp->geneve_port != udp_tunnel->udp_port) {
1421                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1422                                 return -ENOSPC;
1423                         }
1424                         bp->geneve_port_cnt++;
1425                         return 0;
1426                 }
1427                 tunnel_type =
1428                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1429                 bp->geneve_port_cnt++;
1430                 break;
1431         default:
1432                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1433                 return -ENOTSUP;
1434         }
1435         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1436                                              tunnel_type);
1437         return rc;
1438 }
1439
1440 static int
1441 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1442                          struct rte_eth_udp_tunnel *udp_tunnel)
1443 {
1444         struct bnxt *bp = eth_dev->data->dev_private;
1445         uint16_t tunnel_type = 0;
1446         uint16_t port = 0;
1447         int rc = 0;
1448
1449         switch (udp_tunnel->prot_type) {
1450         case RTE_TUNNEL_TYPE_VXLAN:
1451                 if (!bp->vxlan_port_cnt) {
1452                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1453                         return -EINVAL;
1454                 }
1455                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1456                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1457                                 udp_tunnel->udp_port, bp->vxlan_port);
1458                         return -EINVAL;
1459                 }
1460                 if (--bp->vxlan_port_cnt)
1461                         return 0;
1462
1463                 tunnel_type =
1464                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1465                 port = bp->vxlan_fw_dst_port_id;
1466                 break;
1467         case RTE_TUNNEL_TYPE_GENEVE:
1468                 if (!bp->geneve_port_cnt) {
1469                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1470                         return -EINVAL;
1471                 }
1472                 if (bp->geneve_port != udp_tunnel->udp_port) {
1473                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1474                                 udp_tunnel->udp_port, bp->geneve_port);
1475                         return -EINVAL;
1476                 }
1477                 if (--bp->geneve_port_cnt)
1478                         return 0;
1479
1480                 tunnel_type =
1481                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1482                 port = bp->geneve_fw_dst_port_id;
1483                 break;
1484         default:
1485                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1486                 return -ENOTSUP;
1487         }
1488
1489         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1490         if (!rc) {
1491                 if (tunnel_type ==
1492                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1493                         bp->vxlan_port = 0;
1494                 if (tunnel_type ==
1495                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1496                         bp->geneve_port = 0;
1497         }
1498         return rc;
1499 }
1500
1501 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1502 {
1503         struct bnxt_filter_info *filter;
1504         struct bnxt_vnic_info *vnic;
1505         int rc = 0;
1506         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1507
1508         /* if VLAN exists && VLAN matches vlan_id
1509          *      remove the MAC+VLAN filter
1510          *      add a new MAC only filter
1511          * else
1512          *      VLAN filter doesn't exist, just skip and continue
1513          */
1514         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1515         filter = STAILQ_FIRST(&vnic->filter);
1516         while (filter) {
1517                 /* Search for this matching MAC+VLAN filter */
1518                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1519                     !memcmp(filter->l2_addr,
1520                             bp->mac_addr,
1521                             RTE_ETHER_ADDR_LEN)) {
1522                         /* Delete the filter */
1523                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1524                         if (rc)
1525                                 return rc;
1526                         STAILQ_REMOVE(&vnic->filter, filter,
1527                                       bnxt_filter_info, next);
1528                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1529
1530                         PMD_DRV_LOG(INFO,
1531                                     "Del Vlan filter for %d\n",
1532                                     vlan_id);
1533                         return rc;
1534                 }
1535                 filter = STAILQ_NEXT(filter, next);
1536         }
1537         return -ENOENT;
1538 }
1539
1540 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1541 {
1542         struct bnxt_filter_info *filter;
1543         struct bnxt_vnic_info *vnic;
1544         int rc = 0;
1545         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1546                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1547         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1548
1549         /* Implementation notes on the use of VNIC in this command:
1550          *
1551          * By default, these filters belong to default vnic for the function.
1552          * Once these filters are set up, only destination VNIC can be modified.
1553          * If the destination VNIC is not specified in this command,
1554          * then the HWRM shall only create an l2 context id.
1555          */
1556
1557         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1558         filter = STAILQ_FIRST(&vnic->filter);
1559         /* Check if the VLAN has already been added */
1560         while (filter) {
1561                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1562                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1563                         return -EEXIST;
1564
1565                 filter = STAILQ_NEXT(filter, next);
1566         }
1567
1568         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1569          * command to create MAC+VLAN filter with the right flags, enables set.
1570          */
1571         filter = bnxt_alloc_filter(bp);
1572         if (!filter) {
1573                 PMD_DRV_LOG(ERR,
1574                             "MAC/VLAN filter alloc failed\n");
1575                 return -ENOMEM;
1576         }
1577         /* MAC + VLAN ID filter */
1578         filter->l2_ivlan = vlan_id;
1579         filter->l2_ivlan_mask = 0x0FFF;
1580         filter->enables |= en;
1581         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1582         if (rc) {
1583                 /* Free the newly allocated filter as we were
1584                  * not able to create the filter in hardware.
1585                  */
1586                 filter->fw_l2_filter_id = UINT64_MAX;
1587                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1588                 return rc;
1589         }
1590
1591         /* Add this new filter to the list */
1592         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1593         PMD_DRV_LOG(INFO,
1594                     "Added Vlan filter for %d\n", vlan_id);
1595         return rc;
1596 }
1597
1598 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1599                 uint16_t vlan_id, int on)
1600 {
1601         struct bnxt *bp = eth_dev->data->dev_private;
1602
1603         /* These operations apply to ALL existing MAC/VLAN filters */
1604         if (on)
1605                 return bnxt_add_vlan_filter(bp, vlan_id);
1606         else
1607                 return bnxt_del_vlan_filter(bp, vlan_id);
1608 }
1609
1610 static int
1611 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1612 {
1613         struct bnxt *bp = dev->data->dev_private;
1614         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1615         unsigned int i;
1616
1617         if (mask & ETH_VLAN_FILTER_MASK) {
1618                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1619                         /* Remove any VLAN filters programmed */
1620                         for (i = 0; i < 4095; i++)
1621                                 bnxt_del_vlan_filter(bp, i);
1622                 }
1623                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1624                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1625         }
1626
1627         if (mask & ETH_VLAN_STRIP_MASK) {
1628                 /* Enable or disable VLAN stripping */
1629                 for (i = 0; i < bp->nr_vnics; i++) {
1630                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1631                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1632                                 vnic->vlan_strip = true;
1633                         else
1634                                 vnic->vlan_strip = false;
1635                         bnxt_hwrm_vnic_cfg(bp, vnic);
1636                 }
1637                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1638                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1639         }
1640
1641         if (mask & ETH_VLAN_EXTEND_MASK)
1642                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1643
1644         return 0;
1645 }
1646
1647 static int
1648 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1649                         struct rte_ether_addr *addr)
1650 {
1651         struct bnxt *bp = dev->data->dev_private;
1652         /* Default Filter is tied to VNIC 0 */
1653         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1654         struct bnxt_filter_info *filter;
1655         int rc;
1656
1657         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1658                 return -EPERM;
1659
1660         if (rte_is_zero_ether_addr(addr))
1661                 return -EINVAL;
1662
1663         STAILQ_FOREACH(filter, &vnic->filter, next) {
1664                 /* Default Filter is at Index 0 */
1665                 if (filter->mac_index != 0)
1666                         continue;
1667
1668                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1669                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1670                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1671                 filter->enables |=
1672                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1673                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1674
1675                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1676                 if (rc)
1677                         return rc;
1678
1679                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1680                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1681                 return 0;
1682         }
1683
1684         return 0;
1685 }
1686
1687 static int
1688 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1689                           struct rte_ether_addr *mc_addr_set,
1690                           uint32_t nb_mc_addr)
1691 {
1692         struct bnxt *bp = eth_dev->data->dev_private;
1693         char *mc_addr_list = (char *)mc_addr_set;
1694         struct bnxt_vnic_info *vnic;
1695         uint32_t off = 0, i = 0;
1696
1697         vnic = &bp->vnic_info[0];
1698
1699         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1700                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1701                 goto allmulti;
1702         }
1703
1704         /* TODO Check for Duplicate mcast addresses */
1705         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1706         for (i = 0; i < nb_mc_addr; i++) {
1707                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1708                         RTE_ETHER_ADDR_LEN);
1709                 off += RTE_ETHER_ADDR_LEN;
1710         }
1711
1712         vnic->mc_addr_cnt = i;
1713
1714 allmulti:
1715         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1716 }
1717
1718 static int
1719 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1720 {
1721         struct bnxt *bp = dev->data->dev_private;
1722         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1723         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1724         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1725         int ret;
1726
1727         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1728                         fw_major, fw_minor, fw_updt);
1729
1730         ret += 1; /* add the size of '\0' */
1731         if (fw_size < (uint32_t)ret)
1732                 return ret;
1733         else
1734                 return 0;
1735 }
1736
1737 static void
1738 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1739         struct rte_eth_rxq_info *qinfo)
1740 {
1741         struct bnxt_rx_queue *rxq;
1742
1743         rxq = dev->data->rx_queues[queue_id];
1744
1745         qinfo->mp = rxq->mb_pool;
1746         qinfo->scattered_rx = dev->data->scattered_rx;
1747         qinfo->nb_desc = rxq->nb_rx_desc;
1748
1749         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1750         qinfo->conf.rx_drop_en = 0;
1751         qinfo->conf.rx_deferred_start = 0;
1752 }
1753
1754 static void
1755 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1756         struct rte_eth_txq_info *qinfo)
1757 {
1758         struct bnxt_tx_queue *txq;
1759
1760         txq = dev->data->tx_queues[queue_id];
1761
1762         qinfo->nb_desc = txq->nb_tx_desc;
1763
1764         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1765         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1766         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1767
1768         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1769         qinfo->conf.tx_rs_thresh = 0;
1770         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1771 }
1772
1773 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1774 {
1775         struct bnxt *bp = eth_dev->data->dev_private;
1776         struct rte_eth_dev_info dev_info;
1777         uint32_t new_pkt_size;
1778         uint32_t rc = 0;
1779         uint32_t i;
1780
1781         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1782                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1783
1784         bnxt_dev_info_get_op(eth_dev, &dev_info);
1785
1786         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1787                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1788                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1789                 return -EINVAL;
1790         }
1791
1792 #ifdef RTE_ARCH_X86
1793         /*
1794          * If vector-mode tx/rx is active, disallow any MTU change that would
1795          * require scattered receive support.
1796          */
1797         if (eth_dev->data->dev_started &&
1798             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1799              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1800             (new_pkt_size >
1801              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1802                 PMD_DRV_LOG(ERR,
1803                             "MTU change would require scattered rx support. ");
1804                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1805                 return -EINVAL;
1806         }
1807 #endif
1808
1809         if (new_mtu > RTE_ETHER_MTU) {
1810                 bp->flags |= BNXT_FLAG_JUMBO;
1811                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1812                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1813         } else {
1814                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1815                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1816                 bp->flags &= ~BNXT_FLAG_JUMBO;
1817         }
1818
1819         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1820
1821         eth_dev->data->mtu = new_mtu;
1822         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1823
1824         for (i = 0; i < bp->nr_vnics; i++) {
1825                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1826                 uint16_t size = 0;
1827
1828                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1829                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1830                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1831                 if (rc)
1832                         break;
1833
1834                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1835                 size -= RTE_PKTMBUF_HEADROOM;
1836
1837                 if (size < new_mtu) {
1838                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1839                         if (rc)
1840                                 return rc;
1841                 }
1842         }
1843
1844         return rc;
1845 }
1846
1847 static int
1848 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1849 {
1850         struct bnxt *bp = dev->data->dev_private;
1851         uint16_t vlan = bp->vlan;
1852         int rc;
1853
1854         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1855                 PMD_DRV_LOG(ERR,
1856                         "PVID cannot be modified for this function\n");
1857                 return -ENOTSUP;
1858         }
1859         bp->vlan = on ? pvid : 0;
1860
1861         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1862         if (rc)
1863                 bp->vlan = vlan;
1864         return rc;
1865 }
1866
1867 static int
1868 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1869 {
1870         struct bnxt *bp = dev->data->dev_private;
1871
1872         return bnxt_hwrm_port_led_cfg(bp, true);
1873 }
1874
1875 static int
1876 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1877 {
1878         struct bnxt *bp = dev->data->dev_private;
1879
1880         return bnxt_hwrm_port_led_cfg(bp, false);
1881 }
1882
1883 static uint32_t
1884 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1885 {
1886         uint32_t desc = 0, raw_cons = 0, cons;
1887         struct bnxt_cp_ring_info *cpr;
1888         struct bnxt_rx_queue *rxq;
1889         struct rx_pkt_cmpl *rxcmp;
1890         uint16_t cmp_type;
1891         uint8_t cmp = 1;
1892         bool valid;
1893
1894         rxq = dev->data->rx_queues[rx_queue_id];
1895         cpr = rxq->cp_ring;
1896         valid = cpr->valid;
1897
1898         while (raw_cons < rxq->nb_rx_desc) {
1899                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1900                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1901
1902                 if (!CMPL_VALID(rxcmp, valid))
1903                         goto nothing_to_do;
1904                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1905                 cmp_type = CMP_TYPE(rxcmp);
1906                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1907                         cmp = (rte_le_to_cpu_32(
1908                                         ((struct rx_tpa_end_cmpl *)
1909                                          (rxcmp))->agg_bufs_v1) &
1910                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1911                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1912                         desc++;
1913                 } else if (cmp_type == 0x11) {
1914                         desc++;
1915                         cmp = (rxcmp->agg_bufs_v1 &
1916                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1917                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1918                 } else {
1919                         cmp = 1;
1920                 }
1921 nothing_to_do:
1922                 raw_cons += cmp ? cmp : 2;
1923         }
1924
1925         return desc;
1926 }
1927
1928 static int
1929 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1930 {
1931         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1932         struct bnxt_rx_ring_info *rxr;
1933         struct bnxt_cp_ring_info *cpr;
1934         struct bnxt_sw_rx_bd *rx_buf;
1935         struct rx_pkt_cmpl *rxcmp;
1936         uint32_t cons, cp_cons;
1937
1938         if (!rxq)
1939                 return -EINVAL;
1940
1941         cpr = rxq->cp_ring;
1942         rxr = rxq->rx_ring;
1943
1944         if (offset >= rxq->nb_rx_desc)
1945                 return -EINVAL;
1946
1947         cons = RING_CMP(cpr->cp_ring_struct, offset);
1948         cp_cons = cpr->cp_raw_cons;
1949         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1950
1951         if (cons > cp_cons) {
1952                 if (CMPL_VALID(rxcmp, cpr->valid))
1953                         return RTE_ETH_RX_DESC_DONE;
1954         } else {
1955                 if (CMPL_VALID(rxcmp, !cpr->valid))
1956                         return RTE_ETH_RX_DESC_DONE;
1957         }
1958         rx_buf = &rxr->rx_buf_ring[cons];
1959         if (rx_buf->mbuf == NULL)
1960                 return RTE_ETH_RX_DESC_UNAVAIL;
1961
1962
1963         return RTE_ETH_RX_DESC_AVAIL;
1964 }
1965
1966 static int
1967 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1968 {
1969         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1970         struct bnxt_tx_ring_info *txr;
1971         struct bnxt_cp_ring_info *cpr;
1972         struct bnxt_sw_tx_bd *tx_buf;
1973         struct tx_pkt_cmpl *txcmp;
1974         uint32_t cons, cp_cons;
1975
1976         if (!txq)
1977                 return -EINVAL;
1978
1979         cpr = txq->cp_ring;
1980         txr = txq->tx_ring;
1981
1982         if (offset >= txq->nb_tx_desc)
1983                 return -EINVAL;
1984
1985         cons = RING_CMP(cpr->cp_ring_struct, offset);
1986         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1987         cp_cons = cpr->cp_raw_cons;
1988
1989         if (cons > cp_cons) {
1990                 if (CMPL_VALID(txcmp, cpr->valid))
1991                         return RTE_ETH_TX_DESC_UNAVAIL;
1992         } else {
1993                 if (CMPL_VALID(txcmp, !cpr->valid))
1994                         return RTE_ETH_TX_DESC_UNAVAIL;
1995         }
1996         tx_buf = &txr->tx_buf_ring[cons];
1997         if (tx_buf->mbuf == NULL)
1998                 return RTE_ETH_TX_DESC_DONE;
1999
2000         return RTE_ETH_TX_DESC_FULL;
2001 }
2002
2003 static struct bnxt_filter_info *
2004 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2005                                 struct rte_eth_ethertype_filter *efilter,
2006                                 struct bnxt_vnic_info *vnic0,
2007                                 struct bnxt_vnic_info *vnic,
2008                                 int *ret)
2009 {
2010         struct bnxt_filter_info *mfilter = NULL;
2011         int match = 0;
2012         *ret = 0;
2013
2014         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2015                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2016                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2017                         " ethertype filter.", efilter->ether_type);
2018                 *ret = -EINVAL;
2019                 goto exit;
2020         }
2021         if (efilter->queue >= bp->rx_nr_rings) {
2022                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2023                 *ret = -EINVAL;
2024                 goto exit;
2025         }
2026
2027         vnic0 = &bp->vnic_info[0];
2028         vnic = &bp->vnic_info[efilter->queue];
2029         if (vnic == NULL) {
2030                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2031                 *ret = -EINVAL;
2032                 goto exit;
2033         }
2034
2035         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2036                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2037                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2038                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2039                              mfilter->flags ==
2040                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2041                              mfilter->ethertype == efilter->ether_type)) {
2042                                 match = 1;
2043                                 break;
2044                         }
2045                 }
2046         } else {
2047                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2048                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2049                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2050                              mfilter->ethertype == efilter->ether_type &&
2051                              mfilter->flags ==
2052                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2053                                 match = 1;
2054                                 break;
2055                         }
2056         }
2057
2058         if (match)
2059                 *ret = -EEXIST;
2060
2061 exit:
2062         return mfilter;
2063 }
2064
2065 static int
2066 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2067                         enum rte_filter_op filter_op,
2068                         void *arg)
2069 {
2070         struct bnxt *bp = dev->data->dev_private;
2071         struct rte_eth_ethertype_filter *efilter =
2072                         (struct rte_eth_ethertype_filter *)arg;
2073         struct bnxt_filter_info *bfilter, *filter1;
2074         struct bnxt_vnic_info *vnic, *vnic0;
2075         int ret;
2076
2077         if (filter_op == RTE_ETH_FILTER_NOP)
2078                 return 0;
2079
2080         if (arg == NULL) {
2081                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2082                             filter_op);
2083                 return -EINVAL;
2084         }
2085
2086         vnic0 = &bp->vnic_info[0];
2087         vnic = &bp->vnic_info[efilter->queue];
2088
2089         switch (filter_op) {
2090         case RTE_ETH_FILTER_ADD:
2091                 bnxt_match_and_validate_ether_filter(bp, efilter,
2092                                                         vnic0, vnic, &ret);
2093                 if (ret < 0)
2094                         return ret;
2095
2096                 bfilter = bnxt_get_unused_filter(bp);
2097                 if (bfilter == NULL) {
2098                         PMD_DRV_LOG(ERR,
2099                                 "Not enough resources for a new filter.\n");
2100                         return -ENOMEM;
2101                 }
2102                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2103                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2104                        RTE_ETHER_ADDR_LEN);
2105                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2106                        RTE_ETHER_ADDR_LEN);
2107                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2108                 bfilter->ethertype = efilter->ether_type;
2109                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2110
2111                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2112                 if (filter1 == NULL) {
2113                         ret = -EINVAL;
2114                         goto cleanup;
2115                 }
2116                 bfilter->enables |=
2117                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2118                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2119
2120                 bfilter->dst_id = vnic->fw_vnic_id;
2121
2122                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2123                         bfilter->flags =
2124                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2125                 }
2126
2127                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2128                 if (ret)
2129                         goto cleanup;
2130                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2131                 break;
2132         case RTE_ETH_FILTER_DELETE:
2133                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2134                                                         vnic0, vnic, &ret);
2135                 if (ret == -EEXIST) {
2136                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2137
2138                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2139                                       next);
2140                         bnxt_free_filter(bp, filter1);
2141                 } else if (ret == 0) {
2142                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2143                 }
2144                 break;
2145         default:
2146                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2147                 ret = -EINVAL;
2148                 goto error;
2149         }
2150         return ret;
2151 cleanup:
2152         bnxt_free_filter(bp, bfilter);
2153 error:
2154         return ret;
2155 }
2156
2157 static inline int
2158 parse_ntuple_filter(struct bnxt *bp,
2159                     struct rte_eth_ntuple_filter *nfilter,
2160                     struct bnxt_filter_info *bfilter)
2161 {
2162         uint32_t en = 0;
2163
2164         if (nfilter->queue >= bp->rx_nr_rings) {
2165                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2166                 return -EINVAL;
2167         }
2168
2169         switch (nfilter->dst_port_mask) {
2170         case UINT16_MAX:
2171                 bfilter->dst_port_mask = -1;
2172                 bfilter->dst_port = nfilter->dst_port;
2173                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2174                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2175                 break;
2176         default:
2177                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2178                 return -EINVAL;
2179         }
2180
2181         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2182         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2183
2184         switch (nfilter->proto_mask) {
2185         case UINT8_MAX:
2186                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2187                         bfilter->ip_protocol = 17;
2188                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2189                         bfilter->ip_protocol = 6;
2190                 else
2191                         return -EINVAL;
2192                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2193                 break;
2194         default:
2195                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2196                 return -EINVAL;
2197         }
2198
2199         switch (nfilter->dst_ip_mask) {
2200         case UINT32_MAX:
2201                 bfilter->dst_ipaddr_mask[0] = -1;
2202                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2203                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2204                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2205                 break;
2206         default:
2207                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2208                 return -EINVAL;
2209         }
2210
2211         switch (nfilter->src_ip_mask) {
2212         case UINT32_MAX:
2213                 bfilter->src_ipaddr_mask[0] = -1;
2214                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2215                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2216                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2217                 break;
2218         default:
2219                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2220                 return -EINVAL;
2221         }
2222
2223         switch (nfilter->src_port_mask) {
2224         case UINT16_MAX:
2225                 bfilter->src_port_mask = -1;
2226                 bfilter->src_port = nfilter->src_port;
2227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2228                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2229                 break;
2230         default:
2231                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2232                 return -EINVAL;
2233         }
2234
2235         //TODO Priority
2236         //nfilter->priority = (uint8_t)filter->priority;
2237
2238         bfilter->enables = en;
2239         return 0;
2240 }
2241
2242 static struct bnxt_filter_info*
2243 bnxt_match_ntuple_filter(struct bnxt *bp,
2244                          struct bnxt_filter_info *bfilter,
2245                          struct bnxt_vnic_info **mvnic)
2246 {
2247         struct bnxt_filter_info *mfilter = NULL;
2248         int i;
2249
2250         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2251                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2252                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2253                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2254                             bfilter->src_ipaddr_mask[0] ==
2255                             mfilter->src_ipaddr_mask[0] &&
2256                             bfilter->src_port == mfilter->src_port &&
2257                             bfilter->src_port_mask == mfilter->src_port_mask &&
2258                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2259                             bfilter->dst_ipaddr_mask[0] ==
2260                             mfilter->dst_ipaddr_mask[0] &&
2261                             bfilter->dst_port == mfilter->dst_port &&
2262                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2263                             bfilter->flags == mfilter->flags &&
2264                             bfilter->enables == mfilter->enables) {
2265                                 if (mvnic)
2266                                         *mvnic = vnic;
2267                                 return mfilter;
2268                         }
2269                 }
2270         }
2271         return NULL;
2272 }
2273
2274 static int
2275 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2276                        struct rte_eth_ntuple_filter *nfilter,
2277                        enum rte_filter_op filter_op)
2278 {
2279         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2280         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2281         int ret;
2282
2283         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2284                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2285                 return -EINVAL;
2286         }
2287
2288         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2289                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2290                 return -EINVAL;
2291         }
2292
2293         bfilter = bnxt_get_unused_filter(bp);
2294         if (bfilter == NULL) {
2295                 PMD_DRV_LOG(ERR,
2296                         "Not enough resources for a new filter.\n");
2297                 return -ENOMEM;
2298         }
2299         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2300         if (ret < 0)
2301                 goto free_filter;
2302
2303         vnic = &bp->vnic_info[nfilter->queue];
2304         vnic0 = &bp->vnic_info[0];
2305         filter1 = STAILQ_FIRST(&vnic0->filter);
2306         if (filter1 == NULL) {
2307                 ret = -EINVAL;
2308                 goto free_filter;
2309         }
2310
2311         bfilter->dst_id = vnic->fw_vnic_id;
2312         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2313         bfilter->enables |=
2314                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2315         bfilter->ethertype = 0x800;
2316         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2317
2318         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2319
2320         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2321             bfilter->dst_id == mfilter->dst_id) {
2322                 PMD_DRV_LOG(ERR, "filter exists.\n");
2323                 ret = -EEXIST;
2324                 goto free_filter;
2325         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2326                    bfilter->dst_id != mfilter->dst_id) {
2327                 mfilter->dst_id = vnic->fw_vnic_id;
2328                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2329                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2330                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2331                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2332                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2333                 goto free_filter;
2334         }
2335         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2336                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2337                 ret = -ENOENT;
2338                 goto free_filter;
2339         }
2340
2341         if (filter_op == RTE_ETH_FILTER_ADD) {
2342                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2343                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2344                 if (ret)
2345                         goto free_filter;
2346                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2347         } else {
2348                 if (mfilter == NULL) {
2349                         /* This should not happen. But for Coverity! */
2350                         ret = -ENOENT;
2351                         goto free_filter;
2352                 }
2353                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2354
2355                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2356                 bnxt_free_filter(bp, mfilter);
2357                 mfilter->fw_l2_filter_id = -1;
2358                 bnxt_free_filter(bp, bfilter);
2359                 bfilter->fw_l2_filter_id = -1;
2360         }
2361
2362         return 0;
2363 free_filter:
2364         bfilter->fw_l2_filter_id = -1;
2365         bnxt_free_filter(bp, bfilter);
2366         return ret;
2367 }
2368
2369 static int
2370 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2371                         enum rte_filter_op filter_op,
2372                         void *arg)
2373 {
2374         struct bnxt *bp = dev->data->dev_private;
2375         int ret;
2376
2377         if (filter_op == RTE_ETH_FILTER_NOP)
2378                 return 0;
2379
2380         if (arg == NULL) {
2381                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2382                             filter_op);
2383                 return -EINVAL;
2384         }
2385
2386         switch (filter_op) {
2387         case RTE_ETH_FILTER_ADD:
2388                 ret = bnxt_cfg_ntuple_filter(bp,
2389                         (struct rte_eth_ntuple_filter *)arg,
2390                         filter_op);
2391                 break;
2392         case RTE_ETH_FILTER_DELETE:
2393                 ret = bnxt_cfg_ntuple_filter(bp,
2394                         (struct rte_eth_ntuple_filter *)arg,
2395                         filter_op);
2396                 break;
2397         default:
2398                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2399                 ret = -EINVAL;
2400                 break;
2401         }
2402         return ret;
2403 }
2404
2405 static int
2406 bnxt_parse_fdir_filter(struct bnxt *bp,
2407                        struct rte_eth_fdir_filter *fdir,
2408                        struct bnxt_filter_info *filter)
2409 {
2410         enum rte_fdir_mode fdir_mode =
2411                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2412         struct bnxt_vnic_info *vnic0, *vnic;
2413         struct bnxt_filter_info *filter1;
2414         uint32_t en = 0;
2415         int i;
2416
2417         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2418                 return -EINVAL;
2419
2420         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2421         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2422
2423         switch (fdir->input.flow_type) {
2424         case RTE_ETH_FLOW_IPV4:
2425         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2426                 /* FALLTHROUGH */
2427                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2429                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2431                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2432                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2433                 filter->ip_addr_type =
2434                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2435                 filter->src_ipaddr_mask[0] = 0xffffffff;
2436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2437                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2439                 filter->ethertype = 0x800;
2440                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2441                 break;
2442         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2443                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2445                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2447                 filter->dst_port_mask = 0xffff;
2448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2449                 filter->src_port_mask = 0xffff;
2450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2451                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2453                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2455                 filter->ip_protocol = 6;
2456                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2457                 filter->ip_addr_type =
2458                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2459                 filter->src_ipaddr_mask[0] = 0xffffffff;
2460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2461                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2463                 filter->ethertype = 0x800;
2464                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2465                 break;
2466         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2467                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2469                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2471                 filter->dst_port_mask = 0xffff;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2473                 filter->src_port_mask = 0xffff;
2474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2475                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2477                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2479                 filter->ip_protocol = 17;
2480                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2481                 filter->ip_addr_type =
2482                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2483                 filter->src_ipaddr_mask[0] = 0xffffffff;
2484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2485                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2487                 filter->ethertype = 0x800;
2488                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2489                 break;
2490         case RTE_ETH_FLOW_IPV6:
2491         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2492                 /* FALLTHROUGH */
2493                 filter->ip_addr_type =
2494                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2495                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2496                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2497                 rte_memcpy(filter->src_ipaddr,
2498                            fdir->input.flow.ipv6_flow.src_ip, 16);
2499                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2500                 rte_memcpy(filter->dst_ipaddr,
2501                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2503                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2505                 memset(filter->src_ipaddr_mask, 0xff, 16);
2506                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2507                 filter->ethertype = 0x86dd;
2508                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2509                 break;
2510         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2511                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2513                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2515                 filter->dst_port_mask = 0xffff;
2516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2517                 filter->src_port_mask = 0xffff;
2518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2519                 filter->ip_addr_type =
2520                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2521                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2522                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2523                 rte_memcpy(filter->src_ipaddr,
2524                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2526                 rte_memcpy(filter->dst_ipaddr,
2527                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2529                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2531                 memset(filter->src_ipaddr_mask, 0xff, 16);
2532                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2533                 filter->ethertype = 0x86dd;
2534                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2535                 break;
2536         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2537                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2538                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2539                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2540                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2541                 filter->dst_port_mask = 0xffff;
2542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2543                 filter->src_port_mask = 0xffff;
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2545                 filter->ip_addr_type =
2546                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2547                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2548                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2549                 rte_memcpy(filter->src_ipaddr,
2550                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2551                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2552                 rte_memcpy(filter->dst_ipaddr,
2553                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2554                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2555                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2557                 memset(filter->src_ipaddr_mask, 0xff, 16);
2558                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2559                 filter->ethertype = 0x86dd;
2560                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2561                 break;
2562         case RTE_ETH_FLOW_L2_PAYLOAD:
2563                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2564                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2565                 break;
2566         case RTE_ETH_FLOW_VXLAN:
2567                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2568                         return -EINVAL;
2569                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2570                 filter->tunnel_type =
2571                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2572                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2573                 break;
2574         case RTE_ETH_FLOW_NVGRE:
2575                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2576                         return -EINVAL;
2577                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2578                 filter->tunnel_type =
2579                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2580                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2581                 break;
2582         case RTE_ETH_FLOW_UNKNOWN:
2583         case RTE_ETH_FLOW_RAW:
2584         case RTE_ETH_FLOW_FRAG_IPV4:
2585         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2586         case RTE_ETH_FLOW_FRAG_IPV6:
2587         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2588         case RTE_ETH_FLOW_IPV6_EX:
2589         case RTE_ETH_FLOW_IPV6_TCP_EX:
2590         case RTE_ETH_FLOW_IPV6_UDP_EX:
2591         case RTE_ETH_FLOW_GENEVE:
2592                 /* FALLTHROUGH */
2593         default:
2594                 return -EINVAL;
2595         }
2596
2597         vnic0 = &bp->vnic_info[0];
2598         vnic = &bp->vnic_info[fdir->action.rx_queue];
2599         if (vnic == NULL) {
2600                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2601                 return -EINVAL;
2602         }
2603
2604
2605         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2606                 rte_memcpy(filter->dst_macaddr,
2607                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2608                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2609         }
2610
2611         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2612                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2613                 filter1 = STAILQ_FIRST(&vnic0->filter);
2614                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2615         } else {
2616                 filter->dst_id = vnic->fw_vnic_id;
2617                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2618                         if (filter->dst_macaddr[i] == 0x00)
2619                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2620                         else
2621                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2622         }
2623
2624         if (filter1 == NULL)
2625                 return -EINVAL;
2626
2627         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2628         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2629
2630         filter->enables = en;
2631
2632         return 0;
2633 }
2634
2635 static struct bnxt_filter_info *
2636 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2637                 struct bnxt_vnic_info **mvnic)
2638 {
2639         struct bnxt_filter_info *mf = NULL;
2640         int i;
2641
2642         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2643                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2644
2645                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2646                         if (mf->filter_type == nf->filter_type &&
2647                             mf->flags == nf->flags &&
2648                             mf->src_port == nf->src_port &&
2649                             mf->src_port_mask == nf->src_port_mask &&
2650                             mf->dst_port == nf->dst_port &&
2651                             mf->dst_port_mask == nf->dst_port_mask &&
2652                             mf->ip_protocol == nf->ip_protocol &&
2653                             mf->ip_addr_type == nf->ip_addr_type &&
2654                             mf->ethertype == nf->ethertype &&
2655                             mf->vni == nf->vni &&
2656                             mf->tunnel_type == nf->tunnel_type &&
2657                             mf->l2_ovlan == nf->l2_ovlan &&
2658                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2659                             mf->l2_ivlan == nf->l2_ivlan &&
2660                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2661                             !memcmp(mf->l2_addr, nf->l2_addr,
2662                                     RTE_ETHER_ADDR_LEN) &&
2663                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2664                                     RTE_ETHER_ADDR_LEN) &&
2665                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2666                                     RTE_ETHER_ADDR_LEN) &&
2667                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2668                                     RTE_ETHER_ADDR_LEN) &&
2669                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2670                                     sizeof(nf->src_ipaddr)) &&
2671                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2672                                     sizeof(nf->src_ipaddr_mask)) &&
2673                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2674                                     sizeof(nf->dst_ipaddr)) &&
2675                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2676                                     sizeof(nf->dst_ipaddr_mask))) {
2677                                 if (mvnic)
2678                                         *mvnic = vnic;
2679                                 return mf;
2680                         }
2681                 }
2682         }
2683         return NULL;
2684 }
2685
2686 static int
2687 bnxt_fdir_filter(struct rte_eth_dev *dev,
2688                  enum rte_filter_op filter_op,
2689                  void *arg)
2690 {
2691         struct bnxt *bp = dev->data->dev_private;
2692         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2693         struct bnxt_filter_info *filter, *match;
2694         struct bnxt_vnic_info *vnic, *mvnic;
2695         int ret = 0, i;
2696
2697         if (filter_op == RTE_ETH_FILTER_NOP)
2698                 return 0;
2699
2700         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2701                 return -EINVAL;
2702
2703         switch (filter_op) {
2704         case RTE_ETH_FILTER_ADD:
2705         case RTE_ETH_FILTER_DELETE:
2706                 /* FALLTHROUGH */
2707                 filter = bnxt_get_unused_filter(bp);
2708                 if (filter == NULL) {
2709                         PMD_DRV_LOG(ERR,
2710                                 "Not enough resources for a new flow.\n");
2711                         return -ENOMEM;
2712                 }
2713
2714                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2715                 if (ret != 0)
2716                         goto free_filter;
2717                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2718
2719                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2720                         vnic = &bp->vnic_info[0];
2721                 else
2722                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2723
2724                 match = bnxt_match_fdir(bp, filter, &mvnic);
2725                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2726                         if (match->dst_id == vnic->fw_vnic_id) {
2727                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2728                                 ret = -EEXIST;
2729                                 goto free_filter;
2730                         } else {
2731                                 match->dst_id = vnic->fw_vnic_id;
2732                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2733                                                                   match->dst_id,
2734                                                                   match);
2735                                 STAILQ_REMOVE(&mvnic->filter, match,
2736                                               bnxt_filter_info, next);
2737                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2738                                 PMD_DRV_LOG(ERR,
2739                                         "Filter with matching pattern exist\n");
2740                                 PMD_DRV_LOG(ERR,
2741                                         "Updated it to new destination q\n");
2742                                 goto free_filter;
2743                         }
2744                 }
2745                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2746                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2747                         ret = -ENOENT;
2748                         goto free_filter;
2749                 }
2750
2751                 if (filter_op == RTE_ETH_FILTER_ADD) {
2752                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2753                                                           filter->dst_id,
2754                                                           filter);
2755                         if (ret)
2756                                 goto free_filter;
2757                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2758                 } else {
2759                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2760                         STAILQ_REMOVE(&vnic->filter, match,
2761                                       bnxt_filter_info, next);
2762                         bnxt_free_filter(bp, match);
2763                         filter->fw_l2_filter_id = -1;
2764                         bnxt_free_filter(bp, filter);
2765                 }
2766                 break;
2767         case RTE_ETH_FILTER_FLUSH:
2768                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2769                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2770
2771                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2772                                 if (filter->filter_type ==
2773                                     HWRM_CFA_NTUPLE_FILTER) {
2774                                         ret =
2775                                         bnxt_hwrm_clear_ntuple_filter(bp,
2776                                                                       filter);
2777                                         STAILQ_REMOVE(&vnic->filter, filter,
2778                                                       bnxt_filter_info, next);
2779                                 }
2780                         }
2781                 }
2782                 return ret;
2783         case RTE_ETH_FILTER_UPDATE:
2784         case RTE_ETH_FILTER_STATS:
2785         case RTE_ETH_FILTER_INFO:
2786                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2787                 break;
2788         default:
2789                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2790                 ret = -EINVAL;
2791                 break;
2792         }
2793         return ret;
2794
2795 free_filter:
2796         filter->fw_l2_filter_id = -1;
2797         bnxt_free_filter(bp, filter);
2798         return ret;
2799 }
2800
2801 static int
2802 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2803                     enum rte_filter_type filter_type,
2804                     enum rte_filter_op filter_op, void *arg)
2805 {
2806         int ret = 0;
2807
2808         switch (filter_type) {
2809         case RTE_ETH_FILTER_TUNNEL:
2810                 PMD_DRV_LOG(ERR,
2811                         "filter type: %d: To be implemented\n", filter_type);
2812                 break;
2813         case RTE_ETH_FILTER_FDIR:
2814                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2815                 break;
2816         case RTE_ETH_FILTER_NTUPLE:
2817                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2818                 break;
2819         case RTE_ETH_FILTER_ETHERTYPE:
2820                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2821                 break;
2822         case RTE_ETH_FILTER_GENERIC:
2823                 if (filter_op != RTE_ETH_FILTER_GET)
2824                         return -EINVAL;
2825                 *(const void **)arg = &bnxt_flow_ops;
2826                 break;
2827         default:
2828                 PMD_DRV_LOG(ERR,
2829                         "Filter type (%d) not supported", filter_type);
2830                 ret = -EINVAL;
2831                 break;
2832         }
2833         return ret;
2834 }
2835
2836 static const uint32_t *
2837 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2838 {
2839         static const uint32_t ptypes[] = {
2840                 RTE_PTYPE_L2_ETHER_VLAN,
2841                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2842                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2843                 RTE_PTYPE_L4_ICMP,
2844                 RTE_PTYPE_L4_TCP,
2845                 RTE_PTYPE_L4_UDP,
2846                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2847                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2848                 RTE_PTYPE_INNER_L4_ICMP,
2849                 RTE_PTYPE_INNER_L4_TCP,
2850                 RTE_PTYPE_INNER_L4_UDP,
2851                 RTE_PTYPE_UNKNOWN
2852         };
2853
2854         if (!dev->rx_pkt_burst)
2855                 return NULL;
2856
2857         return ptypes;
2858 }
2859
2860 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2861                          int reg_win)
2862 {
2863         uint32_t reg_base = *reg_arr & 0xfffff000;
2864         uint32_t win_off;
2865         int i;
2866
2867         for (i = 0; i < count; i++) {
2868                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2869                         return -ERANGE;
2870         }
2871         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2872         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2873         return 0;
2874 }
2875
2876 static int bnxt_map_ptp_regs(struct bnxt *bp)
2877 {
2878         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2879         uint32_t *reg_arr;
2880         int rc, i;
2881
2882         reg_arr = ptp->rx_regs;
2883         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2884         if (rc)
2885                 return rc;
2886
2887         reg_arr = ptp->tx_regs;
2888         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2889         if (rc)
2890                 return rc;
2891
2892         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2893                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2894
2895         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2896                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2897
2898         return 0;
2899 }
2900
2901 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2902 {
2903         rte_write32(0, (uint8_t *)bp->bar0 +
2904                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2905         rte_write32(0, (uint8_t *)bp->bar0 +
2906                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2907 }
2908
2909 static uint64_t bnxt_cc_read(struct bnxt *bp)
2910 {
2911         uint64_t ns;
2912
2913         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2914                               BNXT_GRCPF_REG_SYNC_TIME));
2915         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2916                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2917         return ns;
2918 }
2919
2920 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2921 {
2922         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2923         uint32_t fifo;
2924
2925         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2926                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2927         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2928                 return -EAGAIN;
2929
2930         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2932         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2933                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2934         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2935                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2936
2937         return 0;
2938 }
2939
2940 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2941 {
2942         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2943         struct bnxt_pf_info *pf = &bp->pf;
2944         uint16_t port_id;
2945         uint32_t fifo;
2946
2947         if (!ptp)
2948                 return -ENODEV;
2949
2950         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2951                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2952         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2953                 return -EAGAIN;
2954
2955         port_id = pf->port_id;
2956         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2957                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2958
2959         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2960                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2961         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2962 /*              bnxt_clr_rx_ts(bp);       TBD  */
2963                 return -EBUSY;
2964         }
2965
2966         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2967                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2968         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2969                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2970
2971         return 0;
2972 }
2973
2974 static int
2975 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2976 {
2977         uint64_t ns;
2978         struct bnxt *bp = dev->data->dev_private;
2979         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2980
2981         if (!ptp)
2982                 return 0;
2983
2984         ns = rte_timespec_to_ns(ts);
2985         /* Set the timecounters to a new value. */
2986         ptp->tc.nsec = ns;
2987
2988         return 0;
2989 }
2990
2991 static int
2992 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2993 {
2994         uint64_t ns, systime_cycles;
2995         struct bnxt *bp = dev->data->dev_private;
2996         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2997
2998         if (!ptp)
2999                 return 0;
3000
3001         systime_cycles = bnxt_cc_read(bp);
3002         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3003         *ts = rte_ns_to_timespec(ns);
3004
3005         return 0;
3006 }
3007 static int
3008 bnxt_timesync_enable(struct rte_eth_dev *dev)
3009 {
3010         struct bnxt *bp = dev->data->dev_private;
3011         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3012         uint32_t shift = 0;
3013
3014         if (!ptp)
3015                 return 0;
3016
3017         ptp->rx_filter = 1;
3018         ptp->tx_tstamp_en = 1;
3019         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3020
3021         if (!bnxt_hwrm_ptp_cfg(bp))
3022                 bnxt_map_ptp_regs(bp);
3023
3024         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3025         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3026         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3027
3028         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3029         ptp->tc.cc_shift = shift;
3030         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3031
3032         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3033         ptp->rx_tstamp_tc.cc_shift = shift;
3034         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3035
3036         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3037         ptp->tx_tstamp_tc.cc_shift = shift;
3038         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3039
3040         return 0;
3041 }
3042
3043 static int
3044 bnxt_timesync_disable(struct rte_eth_dev *dev)
3045 {
3046         struct bnxt *bp = dev->data->dev_private;
3047         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3048
3049         if (!ptp)
3050                 return 0;
3051
3052         ptp->rx_filter = 0;
3053         ptp->tx_tstamp_en = 0;
3054         ptp->rxctl = 0;
3055
3056         bnxt_hwrm_ptp_cfg(bp);
3057
3058         bnxt_unmap_ptp_regs(bp);
3059
3060         return 0;
3061 }
3062
3063 static int
3064 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3065                                  struct timespec *timestamp,
3066                                  uint32_t flags __rte_unused)
3067 {
3068         struct bnxt *bp = dev->data->dev_private;
3069         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3070         uint64_t rx_tstamp_cycles = 0;
3071         uint64_t ns;
3072
3073         if (!ptp)
3074                 return 0;
3075
3076         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3077         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3078         *timestamp = rte_ns_to_timespec(ns);
3079         return  0;
3080 }
3081
3082 static int
3083 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3084                                  struct timespec *timestamp)
3085 {
3086         struct bnxt *bp = dev->data->dev_private;
3087         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3088         uint64_t tx_tstamp_cycles = 0;
3089         uint64_t ns;
3090
3091         if (!ptp)
3092                 return 0;
3093
3094         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3095         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3096         *timestamp = rte_ns_to_timespec(ns);
3097
3098         return 0;
3099 }
3100
3101 static int
3102 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3103 {
3104         struct bnxt *bp = dev->data->dev_private;
3105         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3106
3107         if (!ptp)
3108                 return 0;
3109
3110         ptp->tc.nsec += delta;
3111
3112         return 0;
3113 }
3114
3115 static int
3116 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3117 {
3118         struct bnxt *bp = dev->data->dev_private;
3119         int rc;
3120         uint32_t dir_entries;
3121         uint32_t entry_length;
3122
3123         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3124                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3125                 bp->pdev->addr.devid, bp->pdev->addr.function);
3126
3127         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3128         if (rc != 0)
3129                 return rc;
3130
3131         return dir_entries * entry_length;
3132 }
3133
3134 static int
3135 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3136                 struct rte_dev_eeprom_info *in_eeprom)
3137 {
3138         struct bnxt *bp = dev->data->dev_private;
3139         uint32_t index;
3140         uint32_t offset;
3141
3142         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3143                 "len = %d\n", bp->pdev->addr.domain,
3144                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3145                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3146
3147         if (in_eeprom->offset == 0) /* special offset value to get directory */
3148                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3149                                                 in_eeprom->data);
3150
3151         index = in_eeprom->offset >> 24;
3152         offset = in_eeprom->offset & 0xffffff;
3153
3154         if (index != 0)
3155                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3156                                            in_eeprom->length, in_eeprom->data);
3157
3158         return 0;
3159 }
3160
3161 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3162 {
3163         switch (dir_type) {
3164         case BNX_DIR_TYPE_CHIMP_PATCH:
3165         case BNX_DIR_TYPE_BOOTCODE:
3166         case BNX_DIR_TYPE_BOOTCODE_2:
3167         case BNX_DIR_TYPE_APE_FW:
3168         case BNX_DIR_TYPE_APE_PATCH:
3169         case BNX_DIR_TYPE_KONG_FW:
3170         case BNX_DIR_TYPE_KONG_PATCH:
3171         case BNX_DIR_TYPE_BONO_FW:
3172         case BNX_DIR_TYPE_BONO_PATCH:
3173                 /* FALLTHROUGH */
3174                 return true;
3175         }
3176
3177         return false;
3178 }
3179
3180 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3181 {
3182         switch (dir_type) {
3183         case BNX_DIR_TYPE_AVS:
3184         case BNX_DIR_TYPE_EXP_ROM_MBA:
3185         case BNX_DIR_TYPE_PCIE:
3186         case BNX_DIR_TYPE_TSCF_UCODE:
3187         case BNX_DIR_TYPE_EXT_PHY:
3188         case BNX_DIR_TYPE_CCM:
3189         case BNX_DIR_TYPE_ISCSI_BOOT:
3190         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3191         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3192                 /* FALLTHROUGH */
3193                 return true;
3194         }
3195
3196         return false;
3197 }
3198
3199 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3200 {
3201         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3202                 bnxt_dir_type_is_other_exec_format(dir_type);
3203 }
3204
3205 static int
3206 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3207                 struct rte_dev_eeprom_info *in_eeprom)
3208 {
3209         struct bnxt *bp = dev->data->dev_private;
3210         uint8_t index, dir_op;
3211         uint16_t type, ext, ordinal, attr;
3212
3213         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3214                 "len = %d\n", bp->pdev->addr.domain,
3215                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3216                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3217
3218         if (!BNXT_PF(bp)) {
3219                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3220                 return -EINVAL;
3221         }
3222
3223         type = in_eeprom->magic >> 16;
3224
3225         if (type == 0xffff) { /* special value for directory operations */
3226                 index = in_eeprom->magic & 0xff;
3227                 dir_op = in_eeprom->magic >> 8;
3228                 if (index == 0)
3229                         return -EINVAL;
3230                 switch (dir_op) {
3231                 case 0x0e: /* erase */
3232                         if (in_eeprom->offset != ~in_eeprom->magic)
3233                                 return -EINVAL;
3234                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3235                 default:
3236                         return -EINVAL;
3237                 }
3238         }
3239
3240         /* Create or re-write an NVM item: */
3241         if (bnxt_dir_type_is_executable(type) == true)
3242                 return -EOPNOTSUPP;
3243         ext = in_eeprom->magic & 0xffff;
3244         ordinal = in_eeprom->offset >> 16;
3245         attr = in_eeprom->offset & 0xffff;
3246
3247         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3248                                      in_eeprom->data, in_eeprom->length);
3249 }
3250
3251 /*
3252  * Initialization
3253  */
3254
3255 static const struct eth_dev_ops bnxt_dev_ops = {
3256         .dev_infos_get = bnxt_dev_info_get_op,
3257         .dev_close = bnxt_dev_close_op,
3258         .dev_configure = bnxt_dev_configure_op,
3259         .dev_start = bnxt_dev_start_op,
3260         .dev_stop = bnxt_dev_stop_op,
3261         .dev_set_link_up = bnxt_dev_set_link_up_op,
3262         .dev_set_link_down = bnxt_dev_set_link_down_op,
3263         .stats_get = bnxt_stats_get_op,
3264         .stats_reset = bnxt_stats_reset_op,
3265         .rx_queue_setup = bnxt_rx_queue_setup_op,
3266         .rx_queue_release = bnxt_rx_queue_release_op,
3267         .tx_queue_setup = bnxt_tx_queue_setup_op,
3268         .tx_queue_release = bnxt_tx_queue_release_op,
3269         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3270         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3271         .reta_update = bnxt_reta_update_op,
3272         .reta_query = bnxt_reta_query_op,
3273         .rss_hash_update = bnxt_rss_hash_update_op,
3274         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3275         .link_update = bnxt_link_update_op,
3276         .promiscuous_enable = bnxt_promiscuous_enable_op,
3277         .promiscuous_disable = bnxt_promiscuous_disable_op,
3278         .allmulticast_enable = bnxt_allmulticast_enable_op,
3279         .allmulticast_disable = bnxt_allmulticast_disable_op,
3280         .mac_addr_add = bnxt_mac_addr_add_op,
3281         .mac_addr_remove = bnxt_mac_addr_remove_op,
3282         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3283         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3284         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3285         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3286         .vlan_filter_set = bnxt_vlan_filter_set_op,
3287         .vlan_offload_set = bnxt_vlan_offload_set_op,
3288         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3289         .mtu_set = bnxt_mtu_set_op,
3290         .mac_addr_set = bnxt_set_default_mac_addr_op,
3291         .xstats_get = bnxt_dev_xstats_get_op,
3292         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3293         .xstats_reset = bnxt_dev_xstats_reset_op,
3294         .fw_version_get = bnxt_fw_version_get,
3295         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3296         .rxq_info_get = bnxt_rxq_info_get_op,
3297         .txq_info_get = bnxt_txq_info_get_op,
3298         .dev_led_on = bnxt_dev_led_on_op,
3299         .dev_led_off = bnxt_dev_led_off_op,
3300         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3301         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3302         .rx_queue_count = bnxt_rx_queue_count_op,
3303         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3304         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3305         .rx_queue_start = bnxt_rx_queue_start,
3306         .rx_queue_stop = bnxt_rx_queue_stop,
3307         .tx_queue_start = bnxt_tx_queue_start,
3308         .tx_queue_stop = bnxt_tx_queue_stop,
3309         .filter_ctrl = bnxt_filter_ctrl_op,
3310         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3311         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3312         .get_eeprom           = bnxt_get_eeprom_op,
3313         .set_eeprom           = bnxt_set_eeprom_op,
3314         .timesync_enable      = bnxt_timesync_enable,
3315         .timesync_disable     = bnxt_timesync_disable,
3316         .timesync_read_time   = bnxt_timesync_read_time,
3317         .timesync_write_time   = bnxt_timesync_write_time,
3318         .timesync_adjust_time = bnxt_timesync_adjust_time,
3319         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3320         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3321 };
3322
3323 static bool bnxt_vf_pciid(uint16_t id)
3324 {
3325         if (id == BROADCOM_DEV_ID_57304_VF ||
3326             id == BROADCOM_DEV_ID_57406_VF ||
3327             id == BROADCOM_DEV_ID_5731X_VF ||
3328             id == BROADCOM_DEV_ID_5741X_VF ||
3329             id == BROADCOM_DEV_ID_57414_VF ||
3330             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3331             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3332             id == BROADCOM_DEV_ID_58802_VF ||
3333             id == BROADCOM_DEV_ID_57500_VF1 ||
3334             id == BROADCOM_DEV_ID_57500_VF2)
3335                 return true;
3336         return false;
3337 }
3338
3339 bool bnxt_stratus_device(struct bnxt *bp)
3340 {
3341         uint16_t id = bp->pdev->id.device_id;
3342
3343         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3344             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3345             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3346                 return true;
3347         return false;
3348 }
3349
3350 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3351 {
3352         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3353         struct bnxt *bp = eth_dev->data->dev_private;
3354
3355         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3356         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3357         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3358         if (!bp->bar0 || !bp->doorbell_base) {
3359                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3360                 return -ENODEV;
3361         }
3362
3363         bp->eth_dev = eth_dev;
3364         bp->pdev = pci_dev;
3365
3366         return 0;
3367 }
3368
3369 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3370                                   struct bnxt_ctx_pg_info *ctx_pg,
3371                                   uint32_t mem_size,
3372                                   const char *suffix,
3373                                   uint16_t idx)
3374 {
3375         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3376         const struct rte_memzone *mz = NULL;
3377         char mz_name[RTE_MEMZONE_NAMESIZE];
3378         rte_iova_t mz_phys_addr;
3379         uint64_t valid_bits = 0;
3380         uint32_t sz;
3381         int i;
3382
3383         if (!mem_size)
3384                 return 0;
3385
3386         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3387                          BNXT_PAGE_SIZE;
3388         rmem->page_size = BNXT_PAGE_SIZE;
3389         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3390         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3391         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3392
3393         valid_bits = PTU_PTE_VALID;
3394
3395         if (rmem->nr_pages > 1) {
3396                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3397                          suffix, idx);
3398                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3399                 mz = rte_memzone_lookup(mz_name);
3400                 if (!mz) {
3401                         mz = rte_memzone_reserve_aligned(mz_name,
3402                                                 rmem->nr_pages * 8,
3403                                                 SOCKET_ID_ANY,
3404                                                 RTE_MEMZONE_2MB |
3405                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3406                                                 RTE_MEMZONE_IOVA_CONTIG,
3407                                                 BNXT_PAGE_SIZE);
3408                         if (mz == NULL)
3409                                 return -ENOMEM;
3410                 }
3411
3412                 memset(mz->addr, 0, mz->len);
3413                 mz_phys_addr = mz->iova;
3414                 if ((unsigned long)mz->addr == mz_phys_addr) {
3415                         PMD_DRV_LOG(WARNING,
3416                                 "Memzone physical address same as virtual.\n");
3417                         PMD_DRV_LOG(WARNING,
3418                                     "Using rte_mem_virt2iova()\n");
3419                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3420                         if (mz_phys_addr == RTE_BAD_IOVA) {
3421                                 PMD_DRV_LOG(ERR,
3422                                         "unable to map addr to phys memory\n");
3423                                 return -ENOMEM;
3424                         }
3425                 }
3426                 rte_mem_lock_page(((char *)mz->addr));
3427
3428                 rmem->pg_tbl = mz->addr;
3429                 rmem->pg_tbl_map = mz_phys_addr;
3430                 rmem->pg_tbl_mz = mz;
3431         }
3432
3433         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3434         mz = rte_memzone_lookup(mz_name);
3435         if (!mz) {
3436                 mz = rte_memzone_reserve_aligned(mz_name,
3437                                                  mem_size,
3438                                                  SOCKET_ID_ANY,
3439                                                  RTE_MEMZONE_1GB |
3440                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3441                                                  RTE_MEMZONE_IOVA_CONTIG,
3442                                                  BNXT_PAGE_SIZE);
3443                 if (mz == NULL)
3444                         return -ENOMEM;
3445         }
3446
3447         memset(mz->addr, 0, mz->len);
3448         mz_phys_addr = mz->iova;
3449         if ((unsigned long)mz->addr == mz_phys_addr) {
3450                 PMD_DRV_LOG(WARNING,
3451                             "Memzone physical address same as virtual.\n");
3452                 PMD_DRV_LOG(WARNING,
3453                             "Using rte_mem_virt2iova()\n");
3454                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3455                         rte_mem_lock_page(((char *)mz->addr) + sz);
3456                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3457                 if (mz_phys_addr == RTE_BAD_IOVA) {
3458                         PMD_DRV_LOG(ERR,
3459                                     "unable to map addr to phys memory\n");
3460                         return -ENOMEM;
3461                 }
3462         }
3463
3464         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3465                 rte_mem_lock_page(((char *)mz->addr) + sz);
3466                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3467                 rmem->dma_arr[i] = mz_phys_addr + sz;
3468
3469                 if (rmem->nr_pages > 1) {
3470                         if (i == rmem->nr_pages - 2 &&
3471                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3472                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3473                         else if (i == rmem->nr_pages - 1 &&
3474                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3475                                 valid_bits |= PTU_PTE_LAST;
3476
3477                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3478                                                            valid_bits);
3479                 }
3480         }
3481
3482         rmem->mz = mz;
3483         if (rmem->vmem_size)
3484                 rmem->vmem = (void **)mz->addr;
3485         rmem->dma_arr[0] = mz_phys_addr;
3486         return 0;
3487 }
3488
3489 static void bnxt_free_ctx_mem(struct bnxt *bp)
3490 {
3491         int i;
3492
3493         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3494                 return;
3495
3496         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3497         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3498         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3499         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3500         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3501         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3502         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3503         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3504         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3505         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3506         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3507
3508         for (i = 0; i < BNXT_MAX_Q; i++) {
3509                 if (bp->ctx->tqm_mem[i])
3510                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3511         }
3512
3513         rte_free(bp->ctx);
3514         bp->ctx = NULL;
3515 }
3516
3517 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3518
3519 #define min_t(type, x, y) ({                    \
3520         type __min1 = (x);                      \
3521         type __min2 = (y);                      \
3522         __min1 < __min2 ? __min1 : __min2; })
3523
3524 #define max_t(type, x, y) ({                    \
3525         type __max1 = (x);                      \
3526         type __max2 = (y);                      \
3527         __max1 > __max2 ? __max1 : __max2; })
3528
3529 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3530
3531 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3532 {
3533         struct bnxt_ctx_pg_info *ctx_pg;
3534         struct bnxt_ctx_mem_info *ctx;
3535         uint32_t mem_size, ena, entries;
3536         int i, rc;
3537
3538         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3539         if (rc) {
3540                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3541                 return rc;
3542         }
3543         ctx = bp->ctx;
3544         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3545                 return 0;
3546
3547         ctx_pg = &ctx->qp_mem;
3548         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3549         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3550         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3551         if (rc)
3552                 return rc;
3553
3554         ctx_pg = &ctx->srq_mem;
3555         ctx_pg->entries = ctx->srq_max_l2_entries;
3556         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3557         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3558         if (rc)
3559                 return rc;
3560
3561         ctx_pg = &ctx->cq_mem;
3562         ctx_pg->entries = ctx->cq_max_l2_entries;
3563         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3564         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3565         if (rc)
3566                 return rc;
3567
3568         ctx_pg = &ctx->vnic_mem;
3569         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3570                 ctx->vnic_max_ring_table_entries;
3571         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3572         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3573         if (rc)
3574                 return rc;
3575
3576         ctx_pg = &ctx->stat_mem;
3577         ctx_pg->entries = ctx->stat_max_entries;
3578         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3579         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3580         if (rc)
3581                 return rc;
3582
3583         entries = ctx->qp_max_l2_entries;
3584         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3585         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3586                           ctx->tqm_max_entries_per_ring);
3587         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3588                 ctx_pg = ctx->tqm_mem[i];
3589                 /* use min tqm entries for now. */
3590                 ctx_pg->entries = entries;
3591                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3592                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3593                 if (rc)
3594                         return rc;
3595                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3596         }
3597
3598         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3599         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3600         if (rc)
3601                 PMD_DRV_LOG(ERR,
3602                             "Failed to configure context mem: rc = %d\n", rc);
3603         else
3604                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3605
3606         return rc;
3607 }
3608
3609 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3610 {
3611         struct rte_pci_device *pci_dev = bp->pdev;
3612         char mz_name[RTE_MEMZONE_NAMESIZE];
3613         const struct rte_memzone *mz = NULL;
3614         uint32_t total_alloc_len;
3615         rte_iova_t mz_phys_addr;
3616
3617         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3618                 return 0;
3619
3620         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3621                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3622                  pci_dev->addr.bus, pci_dev->addr.devid,
3623                  pci_dev->addr.function, "rx_port_stats");
3624         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3625         mz = rte_memzone_lookup(mz_name);
3626         total_alloc_len =
3627                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3628                                        sizeof(struct rx_port_stats_ext) + 512);
3629         if (!mz) {
3630                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3631                                          SOCKET_ID_ANY,
3632                                          RTE_MEMZONE_2MB |
3633                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3634                                          RTE_MEMZONE_IOVA_CONTIG);
3635                 if (mz == NULL)
3636                         return -ENOMEM;
3637         }
3638         memset(mz->addr, 0, mz->len);
3639         mz_phys_addr = mz->iova;
3640         if ((unsigned long)mz->addr == mz_phys_addr) {
3641                 PMD_DRV_LOG(WARNING,
3642                             "Memzone physical address same as virtual.\n");
3643                 PMD_DRV_LOG(WARNING,
3644                             "Using rte_mem_virt2iova()\n");
3645                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3646                 if (mz_phys_addr == RTE_BAD_IOVA) {
3647                         PMD_DRV_LOG(ERR,
3648                                     "Can't map address to physical memory\n");
3649                         return -ENOMEM;
3650                 }
3651         }
3652
3653         bp->rx_mem_zone = (const void *)mz;
3654         bp->hw_rx_port_stats = mz->addr;
3655         bp->hw_rx_port_stats_map = mz_phys_addr;
3656
3657         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3658                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3659                  pci_dev->addr.bus, pci_dev->addr.devid,
3660                  pci_dev->addr.function, "tx_port_stats");
3661         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3662         mz = rte_memzone_lookup(mz_name);
3663         total_alloc_len =
3664                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3665                                        sizeof(struct tx_port_stats_ext) + 512);
3666         if (!mz) {
3667                 mz = rte_memzone_reserve(mz_name,
3668                                          total_alloc_len,
3669                                          SOCKET_ID_ANY,
3670                                          RTE_MEMZONE_2MB |
3671                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3672                                          RTE_MEMZONE_IOVA_CONTIG);
3673                 if (mz == NULL)
3674                         return -ENOMEM;
3675         }
3676         memset(mz->addr, 0, mz->len);
3677         mz_phys_addr = mz->iova;
3678         if ((unsigned long)mz->addr == mz_phys_addr) {
3679                 PMD_DRV_LOG(WARNING,
3680                             "Memzone physical address same as virtual\n");
3681                 PMD_DRV_LOG(WARNING,
3682                             "Using rte_mem_virt2iova()\n");
3683                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3684                 if (mz_phys_addr == RTE_BAD_IOVA) {
3685                         PMD_DRV_LOG(ERR,
3686                                     "Can't map address to physical memory\n");
3687                         return -ENOMEM;
3688                 }
3689         }
3690
3691         bp->tx_mem_zone = (const void *)mz;
3692         bp->hw_tx_port_stats = mz->addr;
3693         bp->hw_tx_port_stats_map = mz_phys_addr;
3694         bp->flags |= BNXT_FLAG_PORT_STATS;
3695
3696         /* Display extended statistics if FW supports it */
3697         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3698             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3699             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3700                 return 0;
3701
3702         bp->hw_rx_port_stats_ext = (void *)
3703                 ((uint8_t *)bp->hw_rx_port_stats +
3704                  sizeof(struct rx_port_stats));
3705         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3706                 sizeof(struct rx_port_stats);
3707         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3708
3709         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3710             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3711                 bp->hw_tx_port_stats_ext = (void *)
3712                         ((uint8_t *)bp->hw_tx_port_stats +
3713                          sizeof(struct tx_port_stats));
3714                 bp->hw_tx_port_stats_ext_map =
3715                         bp->hw_tx_port_stats_map +
3716                         sizeof(struct tx_port_stats);
3717                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3718         }
3719
3720         return 0;
3721 }
3722
3723 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3724 {
3725         struct bnxt *bp = eth_dev->data->dev_private;
3726         int rc = 0;
3727
3728         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3729                                                RTE_ETHER_ADDR_LEN *
3730                                                bp->max_l2_ctx,
3731                                                0);
3732         if (eth_dev->data->mac_addrs == NULL) {
3733                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3734                 return -ENOMEM;
3735         }
3736
3737         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3738                 if (BNXT_PF(bp))
3739                         return -EINVAL;
3740
3741                 /* Generate a random MAC address, if none was assigned by PF */
3742                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3743                 bnxt_eth_hw_addr_random(bp->mac_addr);
3744                 PMD_DRV_LOG(INFO,
3745                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3746                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3747                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3748
3749                 rc = bnxt_hwrm_set_mac(bp);
3750                 if (!rc)
3751                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3752                                RTE_ETHER_ADDR_LEN);
3753                 return rc;
3754         }
3755
3756         /* Copy the permanent MAC from the FUNC_QCAPS response */
3757         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3758         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3759
3760         return rc;
3761 }
3762
3763 #define ALLOW_FUNC(x)   \
3764         { \
3765                 uint32_t arg = (x); \
3766                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3767                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3768         }
3769 static int
3770 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3771 {
3772         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3773         static int version_printed;
3774         struct bnxt *bp;
3775         uint16_t mtu;
3776         int rc;
3777
3778         if (version_printed++ == 0)
3779                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3780
3781         rte_eth_copy_pci_info(eth_dev, pci_dev);
3782
3783         bp = eth_dev->data->dev_private;
3784
3785         bp->dev_stopped = 1;
3786
3787         eth_dev->dev_ops = &bnxt_dev_ops;
3788         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3789         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3790
3791         /*
3792          * For secondary processes, we don't initialise any further
3793          * as primary has already done this work.
3794          */
3795         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3796                 return 0;
3797
3798         if (bnxt_vf_pciid(pci_dev->id.device_id))
3799                 bp->flags |= BNXT_FLAG_VF;
3800
3801         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3802             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3803             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3804             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
3805             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
3806                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3807
3808         rc = bnxt_init_board(eth_dev);
3809         if (rc) {
3810                 PMD_DRV_LOG(ERR,
3811                         "Board initialization failed rc: %x\n", rc);
3812                 goto error;
3813         }
3814
3815         rc = bnxt_alloc_hwrm_resources(bp);
3816         if (rc) {
3817                 PMD_DRV_LOG(ERR,
3818                         "hwrm resource allocation failure rc: %x\n", rc);
3819                 goto error_free;
3820         }
3821         rc = bnxt_hwrm_ver_get(bp);
3822         if (rc)
3823                 goto error_free;
3824
3825         rc = bnxt_hwrm_func_reset(bp);
3826         if (rc) {
3827                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3828                 rc = -EIO;
3829                 goto error_free;
3830         }
3831
3832         rc = bnxt_hwrm_queue_qportcfg(bp);
3833         if (rc) {
3834                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3835                 goto error_free;
3836         }
3837         /* Get the MAX capabilities for this function */
3838         rc = bnxt_hwrm_func_qcaps(bp);
3839         if (rc) {
3840                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3841                 goto error_free;
3842         }
3843
3844         rc = bnxt_alloc_stats_mem(bp);
3845         if (rc)
3846                 goto error_free;
3847
3848         if (bp->max_tx_rings == 0) {
3849                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3850                 rc = -EBUSY;
3851                 goto error_free;
3852         }
3853
3854         rc = bnxt_setup_mac_addr(eth_dev);
3855         if (rc)
3856                 goto error_free;
3857
3858         /* THOR does not support ring groups.
3859          * But we will use the array to save RSS context IDs.
3860          */
3861         if (BNXT_CHIP_THOR(bp)) {
3862                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3863         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3864                 /* 1 ring is for default completion ring */
3865                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3866                 rc = -ENOSPC;
3867                 goto error_free;
3868         }
3869
3870         if (BNXT_HAS_RING_GRPS(bp)) {
3871                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3872                                         sizeof(*bp->grp_info) *
3873                                                 bp->max_ring_grps, 0);
3874                 if (!bp->grp_info) {
3875                         PMD_DRV_LOG(ERR,
3876                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3877                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3878                         rc = -ENOMEM;
3879                         goto error_free;
3880                 }
3881         }
3882
3883         /* Forward all requests if firmware is new enough */
3884         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3885             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3886             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3887                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3888         } else {
3889                 PMD_DRV_LOG(WARNING,
3890                         "Firmware too old for VF mailbox functionality\n");
3891                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3892         }
3893
3894         /*
3895          * The following are used for driver cleanup.  If we disallow these,
3896          * VF drivers can't clean up cleanly.
3897          */
3898         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3899         ALLOW_FUNC(HWRM_VNIC_FREE);
3900         ALLOW_FUNC(HWRM_RING_FREE);
3901         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3902         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3903         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3904         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3905         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3906         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3907         rc = bnxt_hwrm_func_driver_register(bp);
3908         if (rc) {
3909                 PMD_DRV_LOG(ERR,
3910                         "Failed to register driver");
3911                 rc = -EBUSY;
3912                 goto error_free;
3913         }
3914
3915         PMD_DRV_LOG(INFO,
3916                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3917                 pci_dev->mem_resource[0].phys_addr,
3918                 pci_dev->mem_resource[0].addr);
3919
3920         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3921         if (rc) {
3922                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3923                 goto error_free;
3924         }
3925
3926         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3927             mtu != eth_dev->data->mtu)
3928                 eth_dev->data->mtu = mtu;
3929
3930         if (BNXT_PF(bp)) {
3931                 //if (bp->pf.active_vfs) {
3932                         // TODO: Deallocate VF resources?
3933                 //}
3934                 if (bp->pdev->max_vfs) {
3935                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3936                         if (rc) {
3937                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3938                                 goto error_free;
3939                         }
3940                 } else {
3941                         rc = bnxt_hwrm_allocate_pf_only(bp);
3942                         if (rc) {
3943                                 PMD_DRV_LOG(ERR,
3944                                         "Failed to allocate PF resources\n");
3945                                 goto error_free;
3946                         }
3947                 }
3948         }
3949
3950         bnxt_hwrm_port_led_qcaps(bp);
3951
3952         rc = bnxt_setup_int(bp);
3953         if (rc)
3954                 goto error_free;
3955
3956         rc = bnxt_alloc_mem(bp);
3957         if (rc)
3958                 goto error_free;
3959
3960         bnxt_init_nic(bp);
3961
3962         rc = bnxt_request_int(bp);
3963         if (rc)
3964                 goto error_free;
3965
3966         return 0;
3967
3968 error_free:
3969         bnxt_dev_uninit(eth_dev);
3970 error:
3971         return rc;
3972 }
3973
3974 static int
3975 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3976 {
3977         struct bnxt *bp = eth_dev->data->dev_private;
3978         int rc;
3979
3980         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3981                 return -EPERM;
3982
3983         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3984         bnxt_disable_int(bp);
3985         bnxt_free_int(bp);
3986         bnxt_free_mem(bp);
3987
3988         bnxt_hwrm_func_buf_unrgtr(bp);
3989
3990         if (bp->grp_info != NULL) {
3991                 rte_free(bp->grp_info);
3992                 bp->grp_info = NULL;
3993         }
3994         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3995         bnxt_free_hwrm_resources(bp);
3996
3997         if (bp->tx_mem_zone) {
3998                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3999                 bp->tx_mem_zone = NULL;
4000         }
4001
4002         if (bp->rx_mem_zone) {
4003                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4004                 bp->rx_mem_zone = NULL;
4005         }
4006
4007         if (bp->dev_stopped == 0)
4008                 bnxt_dev_close_op(eth_dev);
4009         if (bp->pf.vf_info)
4010                 rte_free(bp->pf.vf_info);
4011         bnxt_free_ctx_mem(bp);
4012         eth_dev->dev_ops = NULL;
4013         eth_dev->rx_pkt_burst = NULL;
4014         eth_dev->tx_pkt_burst = NULL;
4015
4016         return rc;
4017 }
4018
4019 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4020         struct rte_pci_device *pci_dev)
4021 {
4022         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4023                 bnxt_dev_init);
4024 }
4025
4026 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4027 {
4028         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4029                 return rte_eth_dev_pci_generic_remove(pci_dev,
4030                                 bnxt_dev_uninit);
4031         else
4032                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4033 }
4034
4035 static struct rte_pci_driver bnxt_rte_pmd = {
4036         .id_table = bnxt_pci_id_map,
4037         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4038         .probe = bnxt_pci_probe,
4039         .remove = bnxt_pci_remove,
4040 };
4041
4042 static bool
4043 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4044 {
4045         if (strcmp(dev->device->driver->name, drv->driver.name))
4046                 return false;
4047
4048         return true;
4049 }
4050
4051 bool is_bnxt_supported(struct rte_eth_dev *dev)
4052 {
4053         return is_device_supported(dev, &bnxt_rte_pmd);
4054 }
4055
4056 RTE_INIT(bnxt_init_log)
4057 {
4058         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4059         if (bnxt_logtype_driver >= 0)
4060                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4061 }
4062
4063 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4064 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4065 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");