drivers/net/bnxt/bnxt_filter.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_FILTER_H_
   7 #define _BNXT_FILTER_H_
   8
   9 #include <rte_ether.h>
  10
  11 struct bnxt;
  12 struct bnxt_filter_info {
  13         STAILQ_ENTRY(bnxt_filter_info)  next;
  14         uint64_t                fw_l2_filter_id;
  15         uint64_t                fw_em_filter_id;
  16         uint64_t                fw_ntuple_filter_id;
  17 #define INVALID_MAC_INDEX       ((uint16_t)-1)
  18         uint16_t                mac_index;
  19 #define HWRM_CFA_L2_FILTER      0
  20 #define HWRM_CFA_EM_FILTER      1
  21 #define HWRM_CFA_NTUPLE_FILTER  2
  22 #define HWRM_CFA_TUNNEL_REDIRECT_FILTER 3
  23         uint8_t                 filter_type;
  24         uint32_t                dst_id;
  25
  26         /* Filter Characteristics */
  27         uint32_t                flags;
  28         uint32_t                enables;
  29         uint8_t                 l2_addr[RTE_ETHER_ADDR_LEN];
  30         uint8_t                 l2_addr_mask[RTE_ETHER_ADDR_LEN];
  31         uint16_t                l2_ovlan;
  32         uint16_t                l2_ovlan_mask;
  33         uint16_t                l2_ivlan;
  34         uint16_t                l2_ivlan_mask;
  35         uint8_t                 t_l2_addr[RTE_ETHER_ADDR_LEN];
  36         uint8_t                 t_l2_addr_mask[RTE_ETHER_ADDR_LEN];
  37         uint16_t                t_l2_ovlan;
  38         uint16_t                t_l2_ovlan_mask;
  39         uint16_t                t_l2_ivlan;
  40         uint16_t                t_l2_ivlan_mask;
  41         uint8_t                 tunnel_type;
  42         uint16_t                mirror_vnic_id;
  43         uint32_t                vni;
  44         uint8_t                 pri_hint;
  45         uint64_t                l2_filter_id_hint;
  46         uint32_t                src_id;
  47         uint8_t                 src_type;
  48         uint8_t                 src_macaddr[6];
  49         uint8_t                 dst_macaddr[6];
  50         uint32_t                dst_ipaddr[4];
  51         uint32_t                dst_ipaddr_mask[4];
  52         uint32_t                src_ipaddr[4];
  53         uint32_t                src_ipaddr_mask[4];
  54         uint16_t                dst_port;
  55         uint16_t                dst_port_mask;
  56         uint16_t                src_port;
  57         uint16_t                src_port_mask;
  58         uint16_t                ip_protocol;
  59         uint16_t                ip_addr_type;
  60         uint16_t                ethertype;
  61 };
  62
  63 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
  64 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
  65 void bnxt_init_filters(struct bnxt *bp);
  66 void bnxt_free_all_filters(struct bnxt *bp);
  67 void bnxt_free_filter_mem(struct bnxt *bp);
  68 int bnxt_alloc_filter_mem(struct bnxt *bp);
  69 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
  70 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
  71 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
  72                 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
  73
  74 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR  \
  75         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
  76 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR      \
  77         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
  78 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR  \
  79         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
  80 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR      \
  81         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
  82 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE   \
  83         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
  84 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE       \
  85         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
  86 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID       \
  87         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
  88 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR  \
  89         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
  90 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK     \
  91         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
  92 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR  \
  93         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
  94 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK     \
  95         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
  96 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT    \
  97         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
  98 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK       \
  99         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
 100 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT    \
 101         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
 102 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK       \
 103         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
 104 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO        \
 105         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
 106 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR       \
 107         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
 108 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR       \
 109         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
 110 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
 111         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
 112 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
 113         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
 114 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
 115         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
 116 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6   \
 117         HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
 118 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6       \
 119         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
 120 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN   \
 121         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
 122 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE   \
 123         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
 124 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE  \
 125         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE
 126 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK   \
 127         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
 128 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
 129         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
 130 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
 131         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
 132 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN     \
 133         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
 134 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4       \
 135         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
 136 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID       \
 137         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
 138 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID       \
 139         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
 140 #endif