1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
6 #ifndef _BNXT_FILTER_H_
7 #define _BNXT_FILTER_H_
11 #define bnxt_vlan_filter_exists(bp, filter, chk, vlan_id) \
12 (((filter)->enables & (chk)) && \
13 ((filter)->l2_ivlan == (vlan_id) && \
14 (filter)->l2_ivlan_mask == 0x0FFF) && \
15 !memcmp((filter)->l2_addr, (bp)->mac_addr, \
19 #define BNXT_FLOW_L2_VALID_FLAG BIT(0)
20 #define BNXT_FLOW_L2_SRC_VALID_FLAG BIT(1)
21 #define BNXT_FLOW_L2_INNER_SRC_VALID_FLAG BIT(2)
22 #define BNXT_FLOW_L2_DST_VALID_FLAG BIT(3)
23 #define BNXT_FLOW_L2_INNER_DST_VALID_FLAG BIT(4)
24 #define BNXT_FLOW_L2_DROP_FLAG BIT(5)
25 #define BNXT_FLOW_PARSE_INNER_FLAG BIT(6)
27 struct bnxt_filter_info {
28 STAILQ_ENTRY(bnxt_filter_info) next;
29 uint64_t fw_l2_filter_id;
30 struct bnxt_filter_info *matching_l2_fltr_ptr;
31 uint64_t fw_em_filter_id;
32 uint64_t fw_ntuple_filter_id;
33 #define INVALID_MAC_INDEX ((uint16_t)-1)
35 #define HWRM_CFA_L2_FILTER 0
36 #define HWRM_CFA_EM_FILTER 1
37 #define HWRM_CFA_NTUPLE_FILTER 2
38 #define HWRM_CFA_TUNNEL_REDIRECT_FILTER 3
42 /* Filter Characteristics */
46 uint8_t l2_addr[RTE_ETHER_ADDR_LEN];
47 uint8_t l2_addr_mask[RTE_ETHER_ADDR_LEN];
50 uint16_t l2_ovlan_mask;
52 uint16_t l2_ivlan_mask;
53 uint8_t t_l2_addr[RTE_ETHER_ADDR_LEN];
54 uint8_t t_l2_addr_mask[RTE_ETHER_ADDR_LEN];
56 uint16_t t_l2_ovlan_mask;
58 uint16_t t_l2_ivlan_mask;
60 uint16_t mirror_vnic_id;
63 uint64_t l2_filter_id_hint;
66 uint8_t src_macaddr[6];
67 uint8_t dst_macaddr[6];
68 uint32_t dst_ipaddr[4];
69 uint32_t dst_ipaddr_mask[4];
70 uint32_t src_ipaddr[4];
71 uint32_t src_ipaddr_mask[4];
73 uint16_t dst_port_mask;
75 uint16_t src_port_mask;
77 uint16_t ip_addr_type;
80 /* Backptr to vnic. As of now, used only by an L2 filter
81 * to remember which vnic it was created on
83 struct bnxt_vnic_info *vnic;
86 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
87 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
88 void bnxt_free_all_filters(struct bnxt *bp);
89 void bnxt_free_filter_mem(struct bnxt *bp);
90 int bnxt_alloc_filter_mem(struct bnxt *bp);
91 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
92 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
93 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
94 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
96 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR \
97 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
98 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR \
99 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
100 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR \
101 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
102 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR \
103 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
104 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE \
105 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
106 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE \
107 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
108 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID \
109 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
110 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR \
111 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
112 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK \
113 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
114 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR \
115 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
116 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK \
117 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
118 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT \
119 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
120 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK \
121 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
122 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT \
123 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
124 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK \
125 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
126 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO \
127 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
128 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR \
129 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
130 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR \
131 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
132 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
133 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
134 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
135 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
136 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
137 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
138 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
139 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
140 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
141 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
142 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN \
143 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
144 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE \
145 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
146 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE \
147 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE
148 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK \
149 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
150 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
151 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
152 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
153 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
154 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
155 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
156 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
157 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
158 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
159 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
160 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
161 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
162 #define L2_FILTER_ALLOC_INPUT_EN_T_NUM_VLANS \
163 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS
164 #define L2_FILTER_ALLOC_INPUT_EN_NUM_VLANS \
165 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS