drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         if (bp->hwrm_cmd_resp_addr == NULL) { \
 188                 rte_spinlock_unlock(&bp->hwrm_lock); \
 189                 return -EACCES; \
 190         } \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         (req)->req_type = rte_cpu_to_le_16(type); \
 193         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 194         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 196         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 197         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 261                                 bool use_kong_mb,
 262                                 uint16_t msg_type,
 263                                 void *msg,
 264                                 uint32_t msg_len,
 265                                 void *resp_msg,
 266                                 uint32_t resp_len)
 267 {
 268         int rc = 0;
 269         bool mailbox = BNXT_USE_CHIMP_MB;
 270         struct input *req = msg;
 271         struct output *resp = bp->hwrm_cmd_resp_addr;
 272
 273         if (use_kong_mb)
 274                 mailbox = BNXT_USE_KONG(bp);
 275
 276         HWRM_PREP(req, msg_type, mailbox);
 277
 278         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 279
 280         HWRM_CHECK_RESULT();
 281
 282         if (resp_msg)
 283                 memcpy(resp_msg, resp, resp_len);
 284
 285         HWRM_UNLOCK();
 286
 287         return rc;
 288 }
 289
 290 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 291                                   bool use_kong_mb,
 292                                   uint16_t tf_type,
 293                                   uint16_t tf_subtype,
 294                                   uint32_t *tf_response_code,
 295                                   void *msg,
 296                                   uint32_t msg_len,
 297                                   void *response,
 298                                   uint32_t response_len)
 299 {
 300         int rc = 0;
 301         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 302         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 303         bool mailbox = BNXT_USE_CHIMP_MB;
 304
 305         if (msg_len > sizeof(req.tf_req))
 306                 return -ENOMEM;
 307
 308         if (use_kong_mb)
 309                 mailbox = BNXT_USE_KONG(bp);
 310
 311         HWRM_PREP(&req, HWRM_TF, mailbox);
 312         /* Build request using the user supplied request payload.
 313          * TLV request size is checked at build time against HWRM
 314          * request max size, thus no checking required.
 315          */
 316         req.tf_type = tf_type;
 317         req.tf_subtype = tf_subtype;
 318         memcpy(req.tf_req, msg, msg_len);
 319
 320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 321         HWRM_CHECK_RESULT();
 322
 323         /* Copy the resp to user provided response buffer */
 324         if (response != NULL)
 325                 /* Post process response data. We need to copy only
 326                  * the 'payload' as the HWRM data structure really is
 327                  * HWRM header + msg header + payload and the TFLIB
 328                  * only provided a payload place holder.
 329                  */
 330                 if (response_len != 0) {
 331                         memcpy(response,
 332                                resp->tf_resp,
 333                                response_len);
 334                 }
 335
 336         /* Extract the internal tflib response code */
 337         *tf_response_code = resp->tf_resp_code;
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 344 {
 345         int rc = 0;
 346         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 347         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 348
 349         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 350         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 351         req.mask = 0;
 352
 353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 354
 355         HWRM_CHECK_RESULT();
 356         HWRM_UNLOCK();
 357
 358         return rc;
 359 }
 360
 361 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 362                                  struct bnxt_vnic_info *vnic,
 363                                  uint16_t vlan_count,
 364                                  struct bnxt_vlan_table_entry *vlan_table)
 365 {
 366         int rc = 0;
 367         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 368         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 369         uint32_t mask = 0;
 370
 371         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 372                 return rc;
 373
 374         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 375         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 376
 377         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 378                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 379         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 380                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 384
 385         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 386                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 387         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 389                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 390                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 391         }
 392         if (vlan_table) {
 393                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 394                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 395                 req.vlan_tag_tbl_addr =
 396                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 397                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 398         }
 399         req.mask = rte_cpu_to_le_32(mask);
 400
 401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 402
 403         HWRM_CHECK_RESULT();
 404         HWRM_UNLOCK();
 405
 406         return rc;
 407 }
 408
 409 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 410                         uint16_t vlan_count,
 411                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 412 {
 413         int rc = 0;
 414         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 415         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 416                                                 bp->hwrm_cmd_resp_addr;
 417
 418         /*
 419          * Older HWRM versions did not support this command, and the set_rx_mask
 420          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 421          * removed from set_rx_mask call, and this command was added.
 422          *
 423          * This command is also present from 1.7.8.11 and higher,
 424          * as well as 1.7.8.0
 425          */
 426         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 427                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 428                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 429                                         (11)))
 430                                 return 0;
 431                 }
 432         }
 433         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 434         req.fid = rte_cpu_to_le_16(fid);
 435
 436         req.vlan_tag_mask_tbl_addr =
 437                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 438         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 441
 442         HWRM_CHECK_RESULT();
 443         HWRM_UNLOCK();
 444
 445         return rc;
 446 }
 447
 448 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 449                              struct bnxt_filter_info *filter)
 450 {
 451         int rc = 0;
 452         struct bnxt_filter_info *l2_filter = filter;
 453         struct bnxt_vnic_info *vnic = NULL;
 454         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 455         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 456
 457         if (filter->fw_l2_filter_id == UINT64_MAX)
 458                 return 0;
 459
 460         if (filter->matching_l2_fltr_ptr)
 461                 l2_filter = filter->matching_l2_fltr_ptr;
 462
 463         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 464                     filter, l2_filter, l2_filter->l2_ref_cnt);
 465
 466         if (l2_filter->l2_ref_cnt == 0)
 467                 return 0;
 468
 469         if (l2_filter->l2_ref_cnt > 0)
 470                 l2_filter->l2_ref_cnt--;
 471
 472         if (l2_filter->l2_ref_cnt > 0)
 473                 return 0;
 474
 475         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 476
 477         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 478
 479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 480
 481         HWRM_CHECK_RESULT();
 482         HWRM_UNLOCK();
 483
 484         filter->fw_l2_filter_id = UINT64_MAX;
 485         if (l2_filter->l2_ref_cnt == 0) {
 486                 vnic = l2_filter->vnic;
 487                 if (vnic) {
 488                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 489                                       bnxt_filter_info, next);
 490                         bnxt_free_filter(bp, l2_filter);
 491                 }
 492         }
 493
 494         return 0;
 495 }
 496
 497 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 498                          uint16_t dst_id,
 499                          struct bnxt_filter_info *filter)
 500 {
 501         int rc = 0;
 502         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 503         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 504         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 505         const struct rte_eth_vmdq_rx_conf *conf =
 506                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 507         uint32_t enables = 0;
 508         uint16_t j = dst_id - 1;
 509
 510         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 511         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 512             conf->pool_map[j].pools & (1UL << j)) {
 513                 PMD_DRV_LOG(DEBUG,
 514                         "Add vlan %u to vmdq pool %u\n",
 515                         conf->pool_map[j].vlan_id, j);
 516
 517                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 518                 filter->enables |=
 519                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 520                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 521         }
 522
 523         if (filter->fw_l2_filter_id != UINT64_MAX)
 524                 bnxt_hwrm_clear_l2_filter(bp, filter);
 525
 526         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 527
 528         req.flags = rte_cpu_to_le_32(filter->flags);
 529
 530         enables = filter->enables |
 531               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 532         req.dst_id = rte_cpu_to_le_16(dst_id);
 533
 534         if (enables &
 535             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 536                 memcpy(req.l2_addr, filter->l2_addr,
 537                        RTE_ETHER_ADDR_LEN);
 538         if (enables &
 539             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 540                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 541                        RTE_ETHER_ADDR_LEN);
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 544                 req.l2_ovlan = filter->l2_ovlan;
 545         if (enables &
 546             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 547                 req.l2_ivlan = filter->l2_ivlan;
 548         if (enables &
 549             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 550                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 551         if (enables &
 552             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 553                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 554         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 555                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 556         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 557                 req.src_type = filter->src_type;
 558         if (filter->pri_hint) {
 559                 req.pri_hint = filter->pri_hint;
 560                 req.l2_filter_id_hint =
 561                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 562         }
 563
 564         req.enables = rte_cpu_to_le_32(enables);
 565
 566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 567
 568         HWRM_CHECK_RESULT();
 569
 570         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 571         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 572         HWRM_UNLOCK();
 573
 574         filter->l2_ref_cnt++;
 575
 576         return rc;
 577 }
 578
 579 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 580 {
 581         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 582         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 583         uint32_t flags = 0;
 584         int rc;
 585
 586         if (!ptp)
 587                 return 0;
 588
 589         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 590
 591         if (ptp->rx_filter)
 592                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 593         else
 594                 flags |=
 595                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 596         if (ptp->tx_tstamp_en)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 601         req.flags = rte_cpu_to_le_32(flags);
 602         req.enables = rte_cpu_to_le_32
 603                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 604         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 605
 606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 607         HWRM_UNLOCK();
 608
 609         return rc;
 610 }
 611
 612 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 613 {
 614         int rc = 0;
 615         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 616         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 617         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 618
 619         if (ptp)
 620                 return 0;
 621
 622         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 623
 624         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 625
 626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 627
 628         HWRM_CHECK_RESULT();
 629
 630         if (!BNXT_CHIP_THOR(bp) &&
 631             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 632                 return 0;
 633
 634         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 635                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 636
 637         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 638         if (!ptp)
 639                 return -ENOMEM;
 640
 641         if (!BNXT_CHIP_THOR(bp)) {
 642                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 643                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 644                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 645                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 646                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 647                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 648                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 649                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 650                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 652                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 653                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 654                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 655                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 656                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 657                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 658                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 659                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 660         }
 661
 662         ptp->bp = bp;
 663         bp->ptp_cfg = ptp;
 664
 665         return 0;
 666 }
 667
 668 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 669 {
 670         int rc = 0;
 671         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 672         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 673         uint16_t new_max_vfs;
 674         uint32_t flags;
 675         int i;
 676
 677         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 678
 679         req.fid = rte_cpu_to_le_16(0xffff);
 680
 681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 682
 683         HWRM_CHECK_RESULT();
 684
 685         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 686         flags = rte_le_to_cpu_32(resp->flags);
 687         if (BNXT_PF(bp)) {
 688                 bp->pf.port_id = resp->port_id;
 689                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 690                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 691                 new_max_vfs = bp->pdev->max_vfs;
 692                 if (new_max_vfs != bp->pf.max_vfs) {
 693                         if (bp->pf.vf_info)
 694                                 rte_free(bp->pf.vf_info);
 695                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 696                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 697                         bp->pf.max_vfs = new_max_vfs;
 698                         for (i = 0; i < new_max_vfs; i++) {
 699                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 700                                 bp->pf.vf_info[i].vlan_table =
 701                                         rte_zmalloc("VF VLAN table",
 702                                                     getpagesize(),
 703                                                     getpagesize());
 704                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 705                                         PMD_DRV_LOG(ERR,
 706                                         "Fail to alloc VLAN table for VF %d\n",
 707                                         i);
 708                                 else
 709                                         rte_mem_lock_page(
 710                                                 bp->pf.vf_info[i].vlan_table);
 711                                 bp->pf.vf_info[i].vlan_as_table =
 712                                         rte_zmalloc("VF VLAN AS table",
 713                                                     getpagesize(),
 714                                                     getpagesize());
 715                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 716                                         PMD_DRV_LOG(ERR,
 717                                         "Alloc VLAN AS table for VF %d fail\n",
 718                                         i);
 719                                 else
 720                                         rte_mem_lock_page(
 721                                                bp->pf.vf_info[i].vlan_as_table);
 722                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 723                         }
 724                 }
 725         }
 726
 727         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 728         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 729         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 730         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 731         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 732         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 733         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 734         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 735         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 736         if (!BNXT_CHIP_THOR(bp))
 737                 bp->max_l2_ctx += bp->max_rx_em_flows;
 738         /* TODO: For now, do not support VMDq/RFS on VFs. */
 739         if (BNXT_PF(bp)) {
 740                 if (bp->pf.max_vfs)
 741                         bp->max_vnics = 1;
 742                 else
 743                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 744         } else {
 745                 bp->max_vnics = 1;
 746         }
 747         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 748                     bp->max_l2_ctx, bp->max_vnics);
 749         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 750         if (BNXT_PF(bp)) {
 751                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 752                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 753                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 754                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 755                         HWRM_UNLOCK();
 756                         bnxt_hwrm_ptp_qcfg(bp);
 757                 }
 758         }
 759
 760         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 761                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 762
 763         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 764                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 765                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 766         }
 767
 768         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 769                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 770
 771         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 772                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 773
 774         HWRM_UNLOCK();
 775
 776         return rc;
 777 }
 778
 779 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 780 {
 781         int rc;
 782
 783         rc = __bnxt_hwrm_func_qcaps(bp);
 784         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 785                 rc = bnxt_alloc_ctx_mem(bp);
 786                 if (rc)
 787                         return rc;
 788
 789                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 790                 if (!rc)
 791                         bp->flags |= BNXT_FLAG_NEW_RM;
 792         }
 793
 794         /* On older FW,
 795          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 796          * But the error can be ignored. Return success.
 797          */
 798
 799         return 0;
 800 }
 801
 802 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 803 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 804 {
 805         int rc = 0;
 806         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 807         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 808
 809         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 810
 811         req.target_id = rte_cpu_to_le_16(0xffff);
 812
 813         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 814
 815         HWRM_CHECK_RESULT();
 816
 817         if (rte_le_to_cpu_32(resp->flags) &
 818             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 819                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 820                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 821         }
 822
 823         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 824
 825         HWRM_UNLOCK();
 826
 827         return rc;
 828 }
 829
 830 int bnxt_hwrm_func_reset(struct bnxt *bp)
 831 {
 832         int rc = 0;
 833         struct hwrm_func_reset_input req = {.req_type = 0 };
 834         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 835
 836         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 837
 838         req.enables = rte_cpu_to_le_32(0);
 839
 840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 841
 842         HWRM_CHECK_RESULT();
 843         HWRM_UNLOCK();
 844
 845         return rc;
 846 }
 847
 848 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 849 {
 850         int rc;
 851         uint32_t flags = 0;
 852         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 853         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 854
 855         if (bp->flags & BNXT_FLAG_REGISTERED)
 856                 return 0;
 857
 858         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 859                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 860         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 861                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 862
 863         /* PFs and trusted VFs should indicate the support of the
 864          * Master capability on non Stingray platform
 865          */
 866         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 867                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 868
 869         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 870         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 871                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 872         req.ver_maj = RTE_VER_YEAR;
 873         req.ver_min = RTE_VER_MONTH;
 874         req.ver_upd = RTE_VER_MINOR;
 875
 876         if (BNXT_PF(bp)) {
 877                 req.enables |= rte_cpu_to_le_32(
 878                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 879                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 880                        RTE_MIN(sizeof(req.vf_req_fwd),
 881                                sizeof(bp->pf.vf_req_fwd)));
 882
 883                 /*
 884                  * PF can sniff HWRM API issued by VF. This can be set up by
 885                  * linux driver and inherited by the DPDK PF driver. Clear
 886                  * this HWRM sniffer list in FW because DPDK PF driver does
 887                  * not support this.
 888                  */
 889                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 890         }
 891
 892         req.flags = rte_cpu_to_le_32(flags);
 893
 894         req.async_event_fwd[0] |=
 895                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 896                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 897                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 898                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 899                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 900         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 901                 req.async_event_fwd[0] |=
 902                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 903         req.async_event_fwd[1] |=
 904                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 905                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 906         if (BNXT_PF(bp))
 907                 req.async_event_fwd[1] |=
 908                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 909
 910         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 911
 912         HWRM_CHECK_RESULT();
 913
 914         flags = rte_le_to_cpu_32(resp->flags);
 915         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 916                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 917
 918         HWRM_UNLOCK();
 919
 920         bp->flags |= BNXT_FLAG_REGISTERED;
 921
 922         return rc;
 923 }
 924
 925 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 926 {
 927         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 928                 return 0;
 929
 930         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 931 }
 932
 933 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 934 {
 935         int rc;
 936         uint32_t flags = 0;
 937         uint32_t enables;
 938         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 939         struct hwrm_func_vf_cfg_input req = {0};
 940
 941         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 942
 943         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 944                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 945                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 946                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 947                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 948
 949         if (BNXT_HAS_RING_GRPS(bp)) {
 950                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 951                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 952         }
 953
 954         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 955         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 956                                             AGG_RING_MULTIPLIER);
 957         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 958         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 959                                               bp->tx_nr_rings +
 960                                               BNXT_NUM_ASYNC_CPR(bp));
 961         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 962         if (bp->vf_resv_strategy ==
 963             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 964                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 965                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 966                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 967                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 968                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 969                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 970         } else if (bp->vf_resv_strategy ==
 971                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 972                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 973                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 974         }
 975
 976         if (test)
 977                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 978                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 979                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 980                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 981                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 982                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 983
 984         if (test && BNXT_HAS_RING_GRPS(bp))
 985                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 986
 987         req.flags = rte_cpu_to_le_32(flags);
 988         req.enables |= rte_cpu_to_le_32(enables);
 989
 990         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 991
 992         if (test)
 993                 HWRM_CHECK_RESULT_SILENT();
 994         else
 995                 HWRM_CHECK_RESULT();
 996
 997         HWRM_UNLOCK();
 998         return rc;
 999 }
1000
1001 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1002 {
1003         int rc;
1004         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1005         struct hwrm_func_resource_qcaps_input req = {0};
1006
1007         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1008         req.fid = rte_cpu_to_le_16(0xffff);
1009
1010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1011
1012         HWRM_CHECK_RESULT_SILENT();
1013
1014         if (BNXT_VF(bp)) {
1015                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1016                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1017                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1018                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1019                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1020                 /* func_resource_qcaps does not return max_rx_em_flows.
1021                  * So use the value provided by func_qcaps.
1022                  */
1023                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1024                 if (!BNXT_CHIP_THOR(bp))
1025                         bp->max_l2_ctx += bp->max_rx_em_flows;
1026                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1027                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1028         }
1029         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1030         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1031         if (bp->vf_resv_strategy >
1032             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1033                 bp->vf_resv_strategy =
1034                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1035
1036         HWRM_UNLOCK();
1037         return rc;
1038 }
1039
1040 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1041 {
1042         int rc = 0;
1043         struct hwrm_ver_get_input req = {.req_type = 0 };
1044         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1045         uint32_t fw_version;
1046         uint16_t max_resp_len;
1047         char type[RTE_MEMZONE_NAMESIZE];
1048         uint32_t dev_caps_cfg;
1049
1050         bp->max_req_len = HWRM_MAX_REQ_LEN;
1051         bp->hwrm_cmd_timeout = timeout;
1052         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1053
1054         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1055         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1056         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1057
1058         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1059
1060         if (bp->flags & BNXT_FLAG_FW_RESET)
1061                 HWRM_CHECK_RESULT_SILENT();
1062         else
1063                 HWRM_CHECK_RESULT();
1064
1065         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1066                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1067                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1068                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1069         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1070                      (resp->hwrm_fw_min_8b << 16) |
1071                      (resp->hwrm_fw_bld_8b << 8) |
1072                      resp->hwrm_fw_rsvd_8b;
1073         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1074                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1075
1076         fw_version = resp->hwrm_intf_maj_8b << 16;
1077         fw_version |= resp->hwrm_intf_min_8b << 8;
1078         fw_version |= resp->hwrm_intf_upd_8b;
1079         bp->hwrm_spec_code = fw_version;
1080
1081         /* def_req_timeout value is in milliseconds */
1082         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1083         /* convert timeout to usec */
1084         bp->hwrm_cmd_timeout *= 1000;
1085         if (!bp->hwrm_cmd_timeout)
1086                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1087
1088         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1089                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1090                 rc = -EINVAL;
1091                 goto error;
1092         }
1093
1094         if (bp->max_req_len > resp->max_req_win_len) {
1095                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1096                 rc = -EINVAL;
1097         }
1098         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1099         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1100         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1101                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1102
1103         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1104         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1105
1106         if (bp->max_resp_len != max_resp_len) {
1107                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1108                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1109                         bp->pdev->addr.devid, bp->pdev->addr.function);
1110
1111                 rte_free(bp->hwrm_cmd_resp_addr);
1112
1113                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1114                 if (bp->hwrm_cmd_resp_addr == NULL) {
1115                         rc = -ENOMEM;
1116                         goto error;
1117                 }
1118                 bp->hwrm_cmd_resp_dma_addr =
1119                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1120                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1121                         PMD_DRV_LOG(ERR,
1122                         "Unable to map response buffer to physical memory.\n");
1123                         rc = -ENOMEM;
1124                         goto error;
1125                 }
1126                 bp->max_resp_len = max_resp_len;
1127         }
1128
1129         if ((dev_caps_cfg &
1130                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1131             (dev_caps_cfg &
1132              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1133                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1134                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1135         }
1136
1137         if (((dev_caps_cfg &
1138               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1139              (dev_caps_cfg &
1140               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1141             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1142                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1143                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1144                         bp->pdev->addr.devid, bp->pdev->addr.function);
1145
1146                 rte_free(bp->hwrm_short_cmd_req_addr);
1147
1148                 bp->hwrm_short_cmd_req_addr =
1149                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1150                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1151                         rc = -ENOMEM;
1152                         goto error;
1153                 }
1154                 bp->hwrm_short_cmd_req_dma_addr =
1155                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1156                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1157                         rte_free(bp->hwrm_short_cmd_req_addr);
1158                         PMD_DRV_LOG(ERR,
1159                                 "Unable to map buffer to physical memory.\n");
1160                         rc = -ENOMEM;
1161                         goto error;
1162                 }
1163         }
1164         if (dev_caps_cfg &
1165             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1166                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1167                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1168         }
1169         if (dev_caps_cfg &
1170             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1171                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1172         if (dev_caps_cfg &
1173             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1174                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1175                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1176         }
1177
1178         if (dev_caps_cfg &
1179             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1180                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1181                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1182         }
1183
1184
1185 error:
1186         HWRM_UNLOCK();
1187         return rc;
1188 }
1189
1190 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1191 {
1192         int rc;
1193         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1194         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1195
1196         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1197                 return 0;
1198
1199         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1200         req.flags = flags;
1201
1202         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1203
1204         HWRM_CHECK_RESULT();
1205         HWRM_UNLOCK();
1206
1207         return rc;
1208 }
1209
1210 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1211 {
1212         int rc = 0;
1213         struct hwrm_port_phy_cfg_input req = {0};
1214         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1215         uint32_t enables = 0;
1216
1217         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1218
1219         if (conf->link_up) {
1220                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1221                 if (bp->link_info.auto_mode && conf->link_speed) {
1222                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1223                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1224                 }
1225
1226                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1227                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1228                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1229                 /*
1230                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1231                  * any auto mode, even "none".
1232                  */
1233                 if (!conf->link_speed) {
1234                         /* No speeds specified. Enable AutoNeg - all speeds */
1235                         req.auto_mode =
1236                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1237                 }
1238                 /* AutoNeg - Advertise speeds specified. */
1239                 if (conf->auto_link_speed_mask &&
1240                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1241                         req.auto_mode =
1242                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1243                         req.auto_link_speed_mask =
1244                                 conf->auto_link_speed_mask;
1245                         enables |=
1246                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1247                 }
1248
1249                 req.auto_duplex = conf->duplex;
1250                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1251                 req.auto_pause = conf->auto_pause;
1252                 req.force_pause = conf->force_pause;
1253                 /* Set force_pause if there is no auto or if there is a force */
1254                 if (req.auto_pause && !req.force_pause)
1255                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1256                 else
1257                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1258
1259                 req.enables = rte_cpu_to_le_32(enables);
1260         } else {
1261                 req.flags =
1262                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1263                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1264         }
1265
1266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1267
1268         HWRM_CHECK_RESULT();
1269         HWRM_UNLOCK();
1270
1271         return rc;
1272 }
1273
1274 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1275                                    struct bnxt_link_info *link_info)
1276 {
1277         int rc = 0;
1278         struct hwrm_port_phy_qcfg_input req = {0};
1279         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1280
1281         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1282
1283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1284
1285         HWRM_CHECK_RESULT();
1286
1287         link_info->phy_link_status = resp->link;
1288         link_info->link_up =
1289                 (link_info->phy_link_status ==
1290                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1291         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1292         link_info->duplex = resp->duplex_cfg;
1293         link_info->pause = resp->pause;
1294         link_info->auto_pause = resp->auto_pause;
1295         link_info->force_pause = resp->force_pause;
1296         link_info->auto_mode = resp->auto_mode;
1297         link_info->phy_type = resp->phy_type;
1298         link_info->media_type = resp->media_type;
1299
1300         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1301         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1302         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1303         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1304         link_info->phy_ver[0] = resp->phy_maj;
1305         link_info->phy_ver[1] = resp->phy_min;
1306         link_info->phy_ver[2] = resp->phy_bld;
1307
1308         HWRM_UNLOCK();
1309
1310         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1311         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1312         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1313         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1314         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1315                     link_info->auto_link_speed_mask);
1316         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1317                     link_info->force_link_speed);
1318
1319         return rc;
1320 }
1321
1322 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1323 {
1324         int i = 0;
1325
1326         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1327                 if (bp->tx_cos_queue[i].profile ==
1328                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1329                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1330                         return true;
1331                 }
1332         }
1333         return false;
1334 }
1335
1336 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1337 {
1338         int i = 0;
1339
1340         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1341                 if (bp->tx_cos_queue[i].profile !=
1342                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1343                     bp->tx_cos_queue[i].id !=
1344                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1345                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1346                         break;
1347                 }
1348         }
1349 }
1350
1351 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1352 {
1353         int rc = 0;
1354         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1355         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1356         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1357         int i;
1358
1359 get_rx_info:
1360         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1361
1362         req.flags = rte_cpu_to_le_32(dir);
1363         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1364         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1365             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1366                 req.drv_qmap_cap =
1367                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1368         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1369
1370         HWRM_CHECK_RESULT();
1371
1372         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1373                 GET_TX_QUEUE_INFO(0);
1374                 GET_TX_QUEUE_INFO(1);
1375                 GET_TX_QUEUE_INFO(2);
1376                 GET_TX_QUEUE_INFO(3);
1377                 GET_TX_QUEUE_INFO(4);
1378                 GET_TX_QUEUE_INFO(5);
1379                 GET_TX_QUEUE_INFO(6);
1380                 GET_TX_QUEUE_INFO(7);
1381         } else  {
1382                 GET_RX_QUEUE_INFO(0);
1383                 GET_RX_QUEUE_INFO(1);
1384                 GET_RX_QUEUE_INFO(2);
1385                 GET_RX_QUEUE_INFO(3);
1386                 GET_RX_QUEUE_INFO(4);
1387                 GET_RX_QUEUE_INFO(5);
1388                 GET_RX_QUEUE_INFO(6);
1389                 GET_RX_QUEUE_INFO(7);
1390         }
1391
1392         HWRM_UNLOCK();
1393
1394         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1395                 goto done;
1396
1397         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1398                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1399         } else {
1400                 int j;
1401
1402                 /* iterate and find the COSq profile to use for Tx */
1403                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1404                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1405                                 if (bp->tx_cos_queue[i].id != 0xff)
1406                                         bp->tx_cosq_id[j++] =
1407                                                 bp->tx_cos_queue[i].id;
1408                         }
1409                 } else {
1410                         /* When CoS classification is disabled, for normal NIC
1411                          * operations, ideally we should look to use LOSSY.
1412                          * If not found, fallback to the first valid profile
1413                          */
1414                         if (!bnxt_find_lossy_profile(bp))
1415                                 bnxt_find_first_valid_profile(bp);
1416
1417                 }
1418         }
1419
1420         bp->max_tc = resp->max_configurable_queues;
1421         bp->max_lltc = resp->max_configurable_lossless_queues;
1422         if (bp->max_tc > BNXT_MAX_QUEUE)
1423                 bp->max_tc = BNXT_MAX_QUEUE;
1424         bp->max_q = bp->max_tc;
1425
1426         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1427                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1428                 goto get_rx_info;
1429         }
1430
1431 done:
1432         return rc;
1433 }
1434
1435 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1436                          struct bnxt_ring *ring,
1437                          uint32_t ring_type, uint32_t map_index,
1438                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1439                          uint16_t tx_cosq_id)
1440 {
1441         int rc = 0;
1442         uint32_t enables = 0;
1443         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1444         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1445         struct rte_mempool *mb_pool;
1446         uint16_t rx_buf_size;
1447
1448         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1449
1450         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1451         req.fbo = rte_cpu_to_le_32(0);
1452         /* Association of ring index with doorbell index */
1453         req.logical_id = rte_cpu_to_le_16(map_index);
1454         req.length = rte_cpu_to_le_32(ring->ring_size);
1455
1456         switch (ring_type) {
1457         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1458                 req.ring_type = ring_type;
1459                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1460                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1461                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1462                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1463                         enables |=
1464                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1465                 break;
1466         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1467                 req.ring_type = ring_type;
1468                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1469                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1470                 if (BNXT_CHIP_THOR(bp)) {
1471                         mb_pool = bp->rx_queues[0]->mb_pool;
1472                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1473                                       RTE_PKTMBUF_HEADROOM;
1474                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1475                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1476                         enables |=
1477                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1478                 }
1479                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1480                         enables |=
1481                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1482                 break;
1483         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1484                 req.ring_type = ring_type;
1485                 if (BNXT_HAS_NQ(bp)) {
1486                         /* Association of cp ring with nq */
1487                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1488                         enables |=
1489                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1490                 }
1491                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1492                 break;
1493         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1494                 req.ring_type = ring_type;
1495                 req.page_size = BNXT_PAGE_SHFT;
1496                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1497                 break;
1498         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1499                 req.ring_type = ring_type;
1500                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1501
1502                 mb_pool = bp->rx_queues[0]->mb_pool;
1503                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1504                               RTE_PKTMBUF_HEADROOM;
1505                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1506                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1507
1508                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1509                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1510                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1511                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1512                 break;
1513         default:
1514                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1515                         ring_type);
1516                 HWRM_UNLOCK();
1517                 return -EINVAL;
1518         }
1519         req.enables = rte_cpu_to_le_32(enables);
1520
1521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1522
1523         if (rc || resp->error_code) {
1524                 if (rc == 0 && resp->error_code)
1525                         rc = rte_le_to_cpu_16(resp->error_code);
1526                 switch (ring_type) {
1527                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1528                         PMD_DRV_LOG(ERR,
1529                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1530                         HWRM_UNLOCK();
1531                         return rc;
1532                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1533                         PMD_DRV_LOG(ERR,
1534                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1535                         HWRM_UNLOCK();
1536                         return rc;
1537                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1538                         PMD_DRV_LOG(ERR,
1539                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1540                                     rc);
1541                         HWRM_UNLOCK();
1542                         return rc;
1543                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1544                         PMD_DRV_LOG(ERR,
1545                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1546                         HWRM_UNLOCK();
1547                         return rc;
1548                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1549                         PMD_DRV_LOG(ERR,
1550                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1551                         HWRM_UNLOCK();
1552                         return rc;
1553                 default:
1554                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1555                         HWRM_UNLOCK();
1556                         return rc;
1557                 }
1558         }
1559
1560         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1561         HWRM_UNLOCK();
1562         return rc;
1563 }
1564
1565 int bnxt_hwrm_ring_free(struct bnxt *bp,
1566                         struct bnxt_ring *ring, uint32_t ring_type)
1567 {
1568         int rc;
1569         struct hwrm_ring_free_input req = {.req_type = 0 };
1570         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1571
1572         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1573
1574         req.ring_type = ring_type;
1575         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1576
1577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1578
1579         if (rc || resp->error_code) {
1580                 if (rc == 0 && resp->error_code)
1581                         rc = rte_le_to_cpu_16(resp->error_code);
1582                 HWRM_UNLOCK();
1583
1584                 switch (ring_type) {
1585                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1586                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1587                                 rc);
1588                         return rc;
1589                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1590                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1591                                 rc);
1592                         return rc;
1593                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1594                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1595                                 rc);
1596                         return rc;
1597                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1598                         PMD_DRV_LOG(ERR,
1599                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1600                         return rc;
1601                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1602                         PMD_DRV_LOG(ERR,
1603                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1604                         return rc;
1605                 default:
1606                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1607                         return rc;
1608                 }
1609         }
1610         HWRM_UNLOCK();
1611         return 0;
1612 }
1613
1614 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1615 {
1616         int rc = 0;
1617         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1618         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1619
1620         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1621
1622         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1623         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1624         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1625         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1626
1627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1628
1629         HWRM_CHECK_RESULT();
1630
1631         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1632
1633         HWRM_UNLOCK();
1634
1635         return rc;
1636 }
1637
1638 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1639 {
1640         int rc;
1641         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1642         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1643
1644         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1645
1646         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1647
1648         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1649
1650         HWRM_CHECK_RESULT();
1651         HWRM_UNLOCK();
1652
1653         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1654         return rc;
1655 }
1656
1657 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1658 {
1659         int rc = 0;
1660         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1661         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1662
1663         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1664                 return rc;
1665
1666         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1667
1668         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1669
1670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1671
1672         HWRM_CHECK_RESULT();
1673         HWRM_UNLOCK();
1674
1675         return rc;
1676 }
1677
1678 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1679                                 unsigned int idx __rte_unused)
1680 {
1681         int rc;
1682         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1683         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1684
1685         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1686
1687         req.update_period_ms = rte_cpu_to_le_32(0);
1688
1689         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1690
1691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1692
1693         HWRM_CHECK_RESULT();
1694
1695         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1696
1697         HWRM_UNLOCK();
1698
1699         return rc;
1700 }
1701
1702 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1703                                 unsigned int idx __rte_unused)
1704 {
1705         int rc;
1706         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1707         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1708
1709         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1710
1711         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1712
1713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1714
1715         HWRM_CHECK_RESULT();
1716         HWRM_UNLOCK();
1717
1718         return rc;
1719 }
1720
1721 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1722 {
1723         int rc = 0, i, j;
1724         struct hwrm_vnic_alloc_input req = { 0 };
1725         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1726
1727         if (!BNXT_HAS_RING_GRPS(bp))
1728                 goto skip_ring_grps;
1729
1730         /* map ring groups to this vnic */
1731         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1732                 vnic->start_grp_id, vnic->end_grp_id);
1733         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1734                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1735
1736         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1737         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1738         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1739         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1740
1741 skip_ring_grps:
1742         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1743         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1744
1745         if (vnic->func_default)
1746                 req.flags =
1747                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1748         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1749
1750         HWRM_CHECK_RESULT();
1751
1752         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1753         HWRM_UNLOCK();
1754         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1755         return rc;
1756 }
1757
1758 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1759                                         struct bnxt_vnic_info *vnic,
1760                                         struct bnxt_plcmodes_cfg *pmode)
1761 {
1762         int rc = 0;
1763         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1764         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1765
1766         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1767
1768         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1769
1770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1771
1772         HWRM_CHECK_RESULT();
1773
1774         pmode->flags = rte_le_to_cpu_32(resp->flags);
1775         /* dflt_vnic bit doesn't exist in the _cfg command */
1776         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1777         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1778         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1779         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1780
1781         HWRM_UNLOCK();
1782
1783         return rc;
1784 }
1785
1786 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1787                                        struct bnxt_vnic_info *vnic,
1788                                        struct bnxt_plcmodes_cfg *pmode)
1789 {
1790         int rc = 0;
1791         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1792         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1793
1794         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1795                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1796                 return rc;
1797         }
1798
1799         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1800
1801         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1802         req.flags = rte_cpu_to_le_32(pmode->flags);
1803         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1804         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1805         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1806         req.enables = rte_cpu_to_le_32(
1807             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1808             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1809             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1810         );
1811
1812         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1813
1814         HWRM_CHECK_RESULT();
1815         HWRM_UNLOCK();
1816
1817         return rc;
1818 }
1819
1820 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1821 {
1822         int rc = 0;
1823         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1824         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1825         struct bnxt_plcmodes_cfg pmodes = { 0 };
1826         uint32_t ctx_enable_flag = 0;
1827         uint32_t enables = 0;
1828
1829         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1830                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1831                 return rc;
1832         }
1833
1834         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1835         if (rc)
1836                 return rc;
1837
1838         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1839
1840         if (BNXT_CHIP_THOR(bp)) {
1841                 int dflt_rxq = vnic->start_grp_id;
1842                 struct bnxt_rx_ring_info *rxr;
1843                 struct bnxt_cp_ring_info *cpr;
1844                 struct bnxt_rx_queue *rxq;
1845                 int i;
1846
1847                 /*
1848                  * The first active receive ring is used as the VNIC
1849                  * default receive ring. If there are no active receive
1850                  * rings (all corresponding receive queues are stopped),
1851                  * the first receive ring is used.
1852                  */
1853                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1854                         rxq = bp->eth_dev->data->rx_queues[i];
1855                         if (rxq->rx_started) {
1856                                 dflt_rxq = i;
1857                                 break;
1858                         }
1859                 }
1860
1861                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1862                 rxr = rxq->rx_ring;
1863                 cpr = rxq->cp_ring;
1864
1865                 req.default_rx_ring_id =
1866                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1867                 req.default_cmpl_ring_id =
1868                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1869                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1870                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1871                 goto config_mru;
1872         }
1873
1874         /* Only RSS support for now TBD: COS & LB */
1875         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1876         if (vnic->lb_rule != 0xffff)
1877                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1878         if (vnic->cos_rule != 0xffff)
1879                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1880         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1881                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1882                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1883         }
1884         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1885                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1886                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1887         }
1888
1889         enables |= ctx_enable_flag;
1890         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1891         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1892         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1893         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1894
1895 config_mru:
1896         req.enables = rte_cpu_to_le_32(enables);
1897         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1898         req.mru = rte_cpu_to_le_16(vnic->mru);
1899         /* Configure default VNIC only once. */
1900         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1901                 req.flags |=
1902                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1903                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1904         }
1905         if (vnic->vlan_strip)
1906                 req.flags |=
1907                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1908         if (vnic->bd_stall)
1909                 req.flags |=
1910                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1911         if (vnic->roce_dual)
1912                 req.flags |= rte_cpu_to_le_32(
1913                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1914         if (vnic->roce_only)
1915                 req.flags |= rte_cpu_to_le_32(
1916                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1917         if (vnic->rss_dflt_cr)
1918                 req.flags |= rte_cpu_to_le_32(
1919                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1920
1921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922
1923         HWRM_CHECK_RESULT();
1924         HWRM_UNLOCK();
1925
1926         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1927
1928         return rc;
1929 }
1930
1931 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1932                 int16_t fw_vf_id)
1933 {
1934         int rc = 0;
1935         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1936         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1937
1938         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1939                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1940                 return rc;
1941         }
1942         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1943
1944         req.enables =
1945                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1946         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1947         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1948
1949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1950
1951         HWRM_CHECK_RESULT();
1952
1953         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1954         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1955         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1956         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1957         vnic->mru = rte_le_to_cpu_16(resp->mru);
1958         vnic->func_default = rte_le_to_cpu_32(
1959                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1960         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1961                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1962         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1963                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1964         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1965                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1966         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1967                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1968         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1969                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1970
1971         HWRM_UNLOCK();
1972
1973         return rc;
1974 }
1975
1976 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1977                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1978 {
1979         int rc = 0;
1980         uint16_t ctx_id;
1981         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1982         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1983                                                 bp->hwrm_cmd_resp_addr;
1984
1985         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1986
1987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1988         HWRM_CHECK_RESULT();
1989
1990         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1991         if (!BNXT_HAS_RING_GRPS(bp))
1992                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1993         else if (ctx_idx == 0)
1994                 vnic->rss_rule = ctx_id;
1995
1996         HWRM_UNLOCK();
1997
1998         return rc;
1999 }
2000
2001 static
2002 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2003                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2004 {
2005         int rc = 0;
2006         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2007         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2008                                                 bp->hwrm_cmd_resp_addr;
2009
2010         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2011                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2012                 return rc;
2013         }
2014         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2015
2016         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2017
2018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2019
2020         HWRM_CHECK_RESULT();
2021         HWRM_UNLOCK();
2022
2023         return rc;
2024 }
2025
2026 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2027 {
2028         int rc = 0;
2029
2030         if (BNXT_CHIP_THOR(bp)) {
2031                 int j;
2032
2033                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2034                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2035                                                       vnic,
2036                                                       vnic->fw_grp_ids[j]);
2037                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2038                 }
2039                 vnic->num_lb_ctxts = 0;
2040         } else {
2041                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2042                 vnic->rss_rule = INVALID_HW_RING_ID;
2043         }
2044
2045         return rc;
2046 }
2047
2048 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2049 {
2050         int rc = 0;
2051         struct hwrm_vnic_free_input req = {.req_type = 0 };
2052         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2053
2054         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2055                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2056                 return rc;
2057         }
2058
2059         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2060
2061         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2062
2063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2064
2065         HWRM_CHECK_RESULT();
2066         HWRM_UNLOCK();
2067
2068         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2069         /* Configure default VNIC again if necessary. */
2070         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2071                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2072
2073         return rc;
2074 }
2075
2076 static int
2077 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2078 {
2079         int i;
2080         int rc = 0;
2081         int nr_ctxs = vnic->num_lb_ctxts;
2082         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2083         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2084
2085         for (i = 0; i < nr_ctxs; i++) {
2086                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2087
2088                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2089                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2090                 req.hash_mode_flags = vnic->hash_mode;
2091
2092                 req.hash_key_tbl_addr =
2093                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2094
2095                 req.ring_grp_tbl_addr =
2096                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2097                                          i * HW_HASH_INDEX_SIZE);
2098                 req.ring_table_pair_index = i;
2099                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2100
2101                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2102                                             BNXT_USE_CHIMP_MB);
2103
2104                 HWRM_CHECK_RESULT();
2105                 HWRM_UNLOCK();
2106         }
2107
2108         return rc;
2109 }
2110
2111 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2112                            struct bnxt_vnic_info *vnic)
2113 {
2114         int rc = 0;
2115         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2116         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2117
2118         if (!vnic->rss_table)
2119                 return 0;
2120
2121         if (BNXT_CHIP_THOR(bp))
2122                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2123
2124         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2125
2126         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2127         req.hash_mode_flags = vnic->hash_mode;
2128
2129         req.ring_grp_tbl_addr =
2130             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2131         req.hash_key_tbl_addr =
2132             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2133         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2134         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2135
2136         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2137
2138         HWRM_CHECK_RESULT();
2139         HWRM_UNLOCK();
2140
2141         return rc;
2142 }
2143
2144 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2145                         struct bnxt_vnic_info *vnic)
2146 {
2147         int rc = 0;
2148         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2149         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2150         uint16_t size;
2151
2152         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2153                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2154                 return rc;
2155         }
2156
2157         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2158
2159         req.flags = rte_cpu_to_le_32(
2160                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2161
2162         req.enables = rte_cpu_to_le_32(
2163                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2164
2165         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2166         size -= RTE_PKTMBUF_HEADROOM;
2167         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2168
2169         req.jumbo_thresh = rte_cpu_to_le_16(size);
2170         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2171
2172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2173
2174         HWRM_CHECK_RESULT();
2175         HWRM_UNLOCK();
2176
2177         return rc;
2178 }
2179
2180 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2181                         struct bnxt_vnic_info *vnic, bool enable)
2182 {
2183         int rc = 0;
2184         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2185         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2186
2187         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2188                 if (enable)
2189                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2190                 return -ENOTSUP;
2191         }
2192
2193         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2194                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2195                 return 0;
2196         }
2197
2198         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2199
2200         if (enable) {
2201                 req.enables = rte_cpu_to_le_32(
2202                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2203                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2204                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2205                 req.flags = rte_cpu_to_le_32(
2206                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2207                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2208                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2209                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2210                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2211                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2212                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2213                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2214                 req.min_agg_len = rte_cpu_to_le_32(512);
2215         }
2216         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2217
2218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2219
2220         HWRM_CHECK_RESULT();
2221         HWRM_UNLOCK();
2222
2223         return rc;
2224 }
2225
2226 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2227 {
2228         struct hwrm_func_cfg_input req = {0};
2229         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2230         int rc;
2231
2232         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2233         req.enables = rte_cpu_to_le_32(
2234                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2235         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2236         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2237
2238         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2239
2240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2241         HWRM_CHECK_RESULT();
2242         HWRM_UNLOCK();
2243
2244         bp->pf.vf_info[vf].random_mac = false;
2245
2246         return rc;
2247 }
2248
2249 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2250                                   uint64_t *dropped)
2251 {
2252         int rc = 0;
2253         struct hwrm_func_qstats_input req = {.req_type = 0};
2254         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2255
2256         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2257
2258         req.fid = rte_cpu_to_le_16(fid);
2259
2260         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2261
2262         HWRM_CHECK_RESULT();
2263
2264         if (dropped)
2265                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2266
2267         HWRM_UNLOCK();
2268
2269         return rc;
2270 }
2271
2272 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2273                           struct rte_eth_stats *stats,
2274                           struct hwrm_func_qstats_output *func_qstats)
2275 {
2276         int rc = 0;
2277         struct hwrm_func_qstats_input req = {.req_type = 0};
2278         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2279
2280         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2281
2282         req.fid = rte_cpu_to_le_16(fid);
2283
2284         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2285
2286         HWRM_CHECK_RESULT();
2287         if (func_qstats)
2288                 memcpy(func_qstats, resp,
2289                        sizeof(struct hwrm_func_qstats_output));
2290
2291         if (!stats)
2292                 goto exit;
2293
2294         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2295         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2296         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2297         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2298         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2299         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2300
2301         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2302         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2303         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2304         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2305         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2306         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2307
2308         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2309         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2310         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2311
2312 exit:
2313         HWRM_UNLOCK();
2314
2315         return rc;
2316 }
2317
2318 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2319 {
2320         int rc = 0;
2321         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2322         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2323
2324         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2325
2326         req.fid = rte_cpu_to_le_16(fid);
2327
2328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2329
2330         HWRM_CHECK_RESULT();
2331         HWRM_UNLOCK();
2332
2333         return rc;
2334 }
2335
2336 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2337 {
2338         unsigned int i;
2339         int rc = 0;
2340
2341         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2342                 struct bnxt_tx_queue *txq;
2343                 struct bnxt_rx_queue *rxq;
2344                 struct bnxt_cp_ring_info *cpr;
2345
2346                 if (i >= bp->rx_cp_nr_rings) {
2347                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2348                         cpr = txq->cp_ring;
2349                 } else {
2350                         rxq = bp->rx_queues[i];
2351                         cpr = rxq->cp_ring;
2352                 }
2353
2354                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2355                 if (rc)
2356                         return rc;
2357         }
2358         return 0;
2359 }
2360
2361 static int
2362 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2363 {
2364         int rc;
2365         unsigned int i;
2366         struct bnxt_cp_ring_info *cpr;
2367
2368         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2369
2370                 if (i >= bp->rx_cp_nr_rings) {
2371                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2372                 } else {
2373                         cpr = bp->rx_queues[i]->cp_ring;
2374                         if (BNXT_HAS_RING_GRPS(bp))
2375                                 bp->grp_info[i].fw_stats_ctx = -1;
2376                 }
2377                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2378                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2379                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2380                         if (rc)
2381                                 return rc;
2382                 }
2383         }
2384         return 0;
2385 }
2386
2387 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2388 {
2389         unsigned int i;
2390         int rc = 0;
2391
2392         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2393                 struct bnxt_tx_queue *txq;
2394                 struct bnxt_rx_queue *rxq;
2395                 struct bnxt_cp_ring_info *cpr;
2396
2397                 if (i >= bp->rx_cp_nr_rings) {
2398                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2399                         cpr = txq->cp_ring;
2400                 } else {
2401                         rxq = bp->rx_queues[i];
2402                         cpr = rxq->cp_ring;
2403                 }
2404
2405                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2406
2407                 if (rc)
2408                         return rc;
2409         }
2410         return rc;
2411 }
2412
2413 static int
2414 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2415 {
2416         uint16_t idx;
2417         uint32_t rc = 0;
2418
2419         if (!BNXT_HAS_RING_GRPS(bp))
2420                 return 0;
2421
2422         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2423
2424                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2425                         continue;
2426
2427                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2428
2429                 if (rc)
2430                         return rc;
2431         }
2432         return rc;
2433 }
2434
2435 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2436 {
2437         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2438
2439         bnxt_hwrm_ring_free(bp, cp_ring,
2440                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2441         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2442         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2443                                      sizeof(*cpr->cp_desc_ring));
2444         cpr->cp_raw_cons = 0;
2445         cpr->valid = 0;
2446 }
2447
2448 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2449 {
2450         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2451
2452         bnxt_hwrm_ring_free(bp, cp_ring,
2453                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2454         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2455         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2456                         sizeof(*cpr->cp_desc_ring));
2457         cpr->cp_raw_cons = 0;
2458         cpr->valid = 0;
2459 }
2460
2461 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2462 {
2463         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2464         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2465         struct bnxt_ring *ring = rxr->rx_ring_struct;
2466         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2467
2468         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2469                 bnxt_hwrm_ring_free(bp, ring,
2470                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2471                 ring->fw_ring_id = INVALID_HW_RING_ID;
2472                 if (BNXT_HAS_RING_GRPS(bp))
2473                         bp->grp_info[queue_index].rx_fw_ring_id =
2474                                                         INVALID_HW_RING_ID;
2475                 memset(rxr->rx_desc_ring, 0,
2476                        rxr->rx_ring_struct->ring_size *
2477                        sizeof(*rxr->rx_desc_ring));
2478                 memset(rxr->rx_buf_ring, 0,
2479                        rxr->rx_ring_struct->ring_size *
2480                        sizeof(*rxr->rx_buf_ring));
2481                 rxr->rx_prod = 0;
2482         }
2483         ring = rxr->ag_ring_struct;
2484         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2485                 bnxt_hwrm_ring_free(bp, ring,
2486                                     BNXT_CHIP_THOR(bp) ?
2487                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2488                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2489                 ring->fw_ring_id = INVALID_HW_RING_ID;
2490                 memset(rxr->ag_buf_ring, 0,
2491                        rxr->ag_ring_struct->ring_size *
2492                        sizeof(*rxr->ag_buf_ring));
2493                 rxr->ag_prod = 0;
2494                 if (BNXT_HAS_RING_GRPS(bp))
2495                         bp->grp_info[queue_index].ag_fw_ring_id =
2496                                                         INVALID_HW_RING_ID;
2497         }
2498         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2499                 bnxt_free_cp_ring(bp, cpr);
2500
2501         if (BNXT_HAS_RING_GRPS(bp))
2502                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2503 }
2504
2505 static int
2506 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2507 {
2508         unsigned int i;
2509
2510         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2511                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2512                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2513                 struct bnxt_ring *ring = txr->tx_ring_struct;
2514                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2515
2516                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2517                         bnxt_hwrm_ring_free(bp, ring,
2518                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2519                         ring->fw_ring_id = INVALID_HW_RING_ID;
2520                         memset(txr->tx_desc_ring, 0,
2521                                         txr->tx_ring_struct->ring_size *
2522                                         sizeof(*txr->tx_desc_ring));
2523                         memset(txr->tx_buf_ring, 0,
2524                                         txr->tx_ring_struct->ring_size *
2525                                         sizeof(*txr->tx_buf_ring));
2526                         txr->tx_prod = 0;
2527                         txr->tx_cons = 0;
2528                 }
2529                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2530                         bnxt_free_cp_ring(bp, cpr);
2531                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2532                 }
2533         }
2534
2535         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2536                 bnxt_free_hwrm_rx_ring(bp, i);
2537
2538         return 0;
2539 }
2540
2541 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2542 {
2543         uint16_t i;
2544         uint32_t rc = 0;
2545
2546         if (!BNXT_HAS_RING_GRPS(bp))
2547                 return 0;
2548
2549         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2550                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2551                 if (rc)
2552                         return rc;
2553         }
2554         return rc;
2555 }
2556
2557 /*
2558  * HWRM utility functions
2559  */
2560
2561 void bnxt_free_hwrm_resources(struct bnxt *bp)
2562 {
2563         /* Release memzone */
2564         rte_free(bp->hwrm_cmd_resp_addr);
2565         rte_free(bp->hwrm_short_cmd_req_addr);
2566         bp->hwrm_cmd_resp_addr = NULL;
2567         bp->hwrm_short_cmd_req_addr = NULL;
2568         bp->hwrm_cmd_resp_dma_addr = 0;
2569         bp->hwrm_short_cmd_req_dma_addr = 0;
2570 }
2571
2572 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2573 {
2574         struct rte_pci_device *pdev = bp->pdev;
2575         char type[RTE_MEMZONE_NAMESIZE];
2576
2577         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2578                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2579         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2580         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2581         if (bp->hwrm_cmd_resp_addr == NULL)
2582                 return -ENOMEM;
2583         bp->hwrm_cmd_resp_dma_addr =
2584                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2585         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2586                 PMD_DRV_LOG(ERR,
2587                         "unable to map response address to physical memory\n");
2588                 return -ENOMEM;
2589         }
2590         rte_spinlock_init(&bp->hwrm_lock);
2591
2592         return 0;
2593 }
2594
2595 static int
2596 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2597 {
2598         struct bnxt_filter_info *filter;
2599         int rc = 0;
2600
2601         STAILQ_FOREACH(filter, &vnic->filter, next) {
2602                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2603                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2604                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2605                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2606                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2607                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2608                 bnxt_free_filter(bp, filter);
2609         }
2610         return rc;
2611 }
2612
2613 static int
2614 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2615 {
2616         struct bnxt_filter_info *filter;
2617         struct rte_flow *flow;
2618         int rc = 0;
2619
2620         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2621                 flow = STAILQ_FIRST(&vnic->flow_list);
2622                 filter = flow->filter;
2623                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2624                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2625                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2626                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2627                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2628                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2629
2630                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2631                 rte_free(flow);
2632         }
2633         return rc;
2634 }
2635
2636 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2637 {
2638         struct bnxt_filter_info *filter;
2639         int rc = 0;
2640
2641         STAILQ_FOREACH(filter, &vnic->filter, next) {
2642                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2643                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2644                                                      filter);
2645                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2646                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2647                                                          filter);
2648                 else
2649                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2650                                                      filter);
2651                 if (rc)
2652                         break;
2653         }
2654         return rc;
2655 }
2656
2657 static void
2658 bnxt_free_tunnel_ports(struct bnxt *bp)
2659 {
2660         if (bp->vxlan_port_cnt)
2661                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2662                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2663         bp->vxlan_port = 0;
2664         if (bp->geneve_port_cnt)
2665                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2666                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2667         bp->geneve_port = 0;
2668 }
2669
2670 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2671 {
2672         int i;
2673
2674         if (bp->vnic_info == NULL)
2675                 return;
2676
2677         /*
2678          * Cleanup VNICs in reverse order, to make sure the L2 filter
2679          * from vnic0 is last to be cleaned up.
2680          */
2681         for (i = bp->max_vnics - 1; i >= 0; i--) {
2682                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2683
2684                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2685                         continue;
2686
2687                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2688
2689                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2690
2691                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2692
2693                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2694
2695                 bnxt_hwrm_vnic_free(bp, vnic);
2696
2697                 rte_free(vnic->fw_grp_ids);
2698         }
2699         /* Ring resources */
2700         bnxt_free_all_hwrm_rings(bp);
2701         bnxt_free_all_hwrm_ring_grps(bp);
2702         bnxt_free_all_hwrm_stat_ctxs(bp);
2703         bnxt_free_tunnel_ports(bp);
2704 }
2705
2706 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2707 {
2708         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2709
2710         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2711                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2712
2713         switch (conf_link_speed) {
2714         case ETH_LINK_SPEED_10M_HD:
2715         case ETH_LINK_SPEED_100M_HD:
2716                 /* FALLTHROUGH */
2717                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2718         }
2719         return hw_link_duplex;
2720 }
2721
2722 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2723 {
2724         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2725 }
2726
2727 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2728 {
2729         uint16_t eth_link_speed = 0;
2730
2731         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2732                 return ETH_LINK_SPEED_AUTONEG;
2733
2734         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2735         case ETH_LINK_SPEED_100M:
2736         case ETH_LINK_SPEED_100M_HD:
2737                 /* FALLTHROUGH */
2738                 eth_link_speed =
2739                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2740                 break;
2741         case ETH_LINK_SPEED_1G:
2742                 eth_link_speed =
2743                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2744                 break;
2745         case ETH_LINK_SPEED_2_5G:
2746                 eth_link_speed =
2747                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2748                 break;
2749         case ETH_LINK_SPEED_10G:
2750                 eth_link_speed =
2751                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2752                 break;
2753         case ETH_LINK_SPEED_20G:
2754                 eth_link_speed =
2755                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2756                 break;
2757         case ETH_LINK_SPEED_25G:
2758                 eth_link_speed =
2759                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2760                 break;
2761         case ETH_LINK_SPEED_40G:
2762                 eth_link_speed =
2763                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2764                 break;
2765         case ETH_LINK_SPEED_50G:
2766                 eth_link_speed =
2767                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2768                 break;
2769         case ETH_LINK_SPEED_100G:
2770                 eth_link_speed =
2771                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2772                 break;
2773         default:
2774                 PMD_DRV_LOG(ERR,
2775                         "Unsupported link speed %d; default to AUTO\n",
2776                         conf_link_speed);
2777                 break;
2778         }
2779         return eth_link_speed;
2780 }
2781
2782 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2783                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2784                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2785                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2786
2787 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2788 {
2789         uint32_t one_speed;
2790
2791         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2792                 return 0;
2793
2794         if (link_speed & ETH_LINK_SPEED_FIXED) {
2795                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2796
2797                 if (one_speed & (one_speed - 1)) {
2798                         PMD_DRV_LOG(ERR,
2799                                 "Invalid advertised speeds (%u) for port %u\n",
2800                                 link_speed, port_id);
2801                         return -EINVAL;
2802                 }
2803                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2804                         PMD_DRV_LOG(ERR,
2805                                 "Unsupported advertised speed (%u) for port %u\n",
2806                                 link_speed, port_id);
2807                         return -EINVAL;
2808                 }
2809         } else {
2810                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2811                         PMD_DRV_LOG(ERR,
2812                                 "Unsupported advertised speeds (%u) for port %u\n",
2813                                 link_speed, port_id);
2814                         return -EINVAL;
2815                 }
2816         }
2817         return 0;
2818 }
2819
2820 static uint16_t
2821 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2822 {
2823         uint16_t ret = 0;
2824
2825         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2826                 if (bp->link_info.support_speeds)
2827                         return bp->link_info.support_speeds;
2828                 link_speed = BNXT_SUPPORTED_SPEEDS;
2829         }
2830
2831         if (link_speed & ETH_LINK_SPEED_100M)
2832                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2833         if (link_speed & ETH_LINK_SPEED_100M_HD)
2834                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2835         if (link_speed & ETH_LINK_SPEED_1G)
2836                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2837         if (link_speed & ETH_LINK_SPEED_2_5G)
2838                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2839         if (link_speed & ETH_LINK_SPEED_10G)
2840                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2841         if (link_speed & ETH_LINK_SPEED_20G)
2842                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2843         if (link_speed & ETH_LINK_SPEED_25G)
2844                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2845         if (link_speed & ETH_LINK_SPEED_40G)
2846                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2847         if (link_speed & ETH_LINK_SPEED_50G)
2848                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2849         if (link_speed & ETH_LINK_SPEED_100G)
2850                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2851         return ret;
2852 }
2853
2854 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2855 {
2856         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2857
2858         switch (hw_link_speed) {
2859         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2860                 eth_link_speed = ETH_SPEED_NUM_100M;
2861                 break;
2862         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2863                 eth_link_speed = ETH_SPEED_NUM_1G;
2864                 break;
2865         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2866                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2867                 break;
2868         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2869                 eth_link_speed = ETH_SPEED_NUM_10G;
2870                 break;
2871         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2872                 eth_link_speed = ETH_SPEED_NUM_20G;
2873                 break;
2874         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2875                 eth_link_speed = ETH_SPEED_NUM_25G;
2876                 break;
2877         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2878                 eth_link_speed = ETH_SPEED_NUM_40G;
2879                 break;
2880         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2881                 eth_link_speed = ETH_SPEED_NUM_50G;
2882                 break;
2883         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2884                 eth_link_speed = ETH_SPEED_NUM_100G;
2885                 break;
2886         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2887         default:
2888                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2889                         hw_link_speed);
2890                 break;
2891         }
2892         return eth_link_speed;
2893 }
2894
2895 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2896 {
2897         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2898
2899         switch (hw_link_duplex) {
2900         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2901         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2902                 /* FALLTHROUGH */
2903                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2904                 break;
2905         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2906                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2907                 break;
2908         default:
2909                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2910                         hw_link_duplex);
2911                 break;
2912         }
2913         return eth_link_duplex;
2914 }
2915
2916 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2917 {
2918         int rc = 0;
2919         struct bnxt_link_info *link_info = &bp->link_info;
2920
2921         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2922         if (rc) {
2923                 PMD_DRV_LOG(ERR,
2924                         "Get link config failed with rc %d\n", rc);
2925                 goto exit;
2926         }
2927         if (link_info->link_speed)
2928                 link->link_speed =
2929                         bnxt_parse_hw_link_speed(link_info->link_speed);
2930         else
2931                 link->link_speed = ETH_SPEED_NUM_NONE;
2932         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2933         link->link_status = link_info->link_up;
2934         link->link_autoneg = link_info->auto_mode ==
2935                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2936                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2937 exit:
2938         return rc;
2939 }
2940
2941 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2942 {
2943         int rc = 0;
2944         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2945         struct bnxt_link_info link_req;
2946         uint16_t speed, autoneg;
2947
2948         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2949                 return 0;
2950
2951         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2952                         bp->eth_dev->data->port_id);
2953         if (rc)
2954                 goto error;
2955
2956         memset(&link_req, 0, sizeof(link_req));
2957         link_req.link_up = link_up;
2958         if (!link_up)
2959                 goto port_phy_cfg;
2960
2961         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2962         if (BNXT_CHIP_THOR(bp) &&
2963             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2964                 /* 40G is not supported as part of media auto detect.
2965                  * The speed should be forced and autoneg disabled
2966                  * to configure 40G speed.
2967                  */
2968                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2969                 autoneg = 0;
2970         }
2971
2972         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2973         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2974         /* Autoneg can be done only when the FW allows.
2975          * When user configures fixed speed of 40G and later changes to
2976          * any other speed, auto_link_speed/force_link_speed is still set
2977          * to 40G until link comes up at new speed.
2978          */
2979         if (autoneg == 1 &&
2980             !(!BNXT_CHIP_THOR(bp) &&
2981               (bp->link_info.auto_link_speed ||
2982                bp->link_info.force_link_speed))) {
2983                 link_req.phy_flags |=
2984                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2985                 link_req.auto_link_speed_mask =
2986                         bnxt_parse_eth_link_speed_mask(bp,
2987                                                        dev_conf->link_speeds);
2988         } else {
2989                 if (bp->link_info.phy_type ==
2990                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2991                     bp->link_info.phy_type ==
2992                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2993                     bp->link_info.media_type ==
2994                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2995                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2996                         return -EINVAL;
2997                 }
2998
2999                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3000                 /* If user wants a particular speed try that first. */
3001                 if (speed)
3002                         link_req.link_speed = speed;
3003                 else if (bp->link_info.force_link_speed)
3004                         link_req.link_speed = bp->link_info.force_link_speed;
3005                 else
3006                         link_req.link_speed = bp->link_info.auto_link_speed;
3007         }
3008         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3009         link_req.auto_pause = bp->link_info.auto_pause;
3010         link_req.force_pause = bp->link_info.force_pause;
3011
3012 port_phy_cfg:
3013         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3014         if (rc) {
3015                 PMD_DRV_LOG(ERR,
3016                         "Set link config failed with rc %d\n", rc);
3017         }
3018
3019 error:
3020         return rc;
3021 }
3022
3023 /* JIRA 22088 */
3024 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3025 {
3026         struct hwrm_func_qcfg_input req = {0};
3027         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3028         uint16_t flags;
3029         int rc = 0;
3030         bp->func_svif = BNXT_SVIF_INVALID;
3031         uint16_t svif_info;
3032
3033         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3034         req.fid = rte_cpu_to_le_16(0xffff);
3035
3036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3037
3038         HWRM_CHECK_RESULT();
3039
3040         /* Hard Coded.. 0xfff VLAN ID mask */
3041         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3042
3043         svif_info = rte_le_to_cpu_16(resp->svif_info);
3044         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3045                 bp->func_svif = svif_info &
3046                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3047
3048         flags = rte_le_to_cpu_16(resp->flags);
3049         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3050                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3051
3052         if (BNXT_VF(bp) &&
3053             !BNXT_VF_IS_TRUSTED(bp) &&
3054             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3055                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3056                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3057         } else if (BNXT_VF(bp) &&
3058                    BNXT_VF_IS_TRUSTED(bp) &&
3059                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3060                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3061                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3062         }
3063
3064         if (mtu)
3065                 *mtu = rte_le_to_cpu_16(resp->mtu);
3066
3067         switch (resp->port_partition_type) {
3068         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3069         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3070         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3071                 /* FALLTHROUGH */
3072                 bp->flags |= BNXT_FLAG_NPAR_PF;
3073                 break;
3074         default:
3075                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3076                 break;
3077         }
3078
3079         HWRM_UNLOCK();
3080
3081         return rc;
3082 }
3083
3084 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3085 {
3086         struct hwrm_port_mac_qcfg_input req = {0};
3087         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3088         uint16_t port_svif_info;
3089         int rc;
3090
3091         bp->port_svif = BNXT_SVIF_INVALID;
3092
3093         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3094
3095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3096
3097         HWRM_CHECK_RESULT();
3098
3099         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3100         if (port_svif_info &
3101             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3102                 bp->port_svif = port_svif_info &
3103                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3104
3105         HWRM_UNLOCK();
3106
3107         return 0;
3108 }
3109
3110 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3111                                    struct hwrm_func_qcaps_output *qcaps)
3112 {
3113         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3114         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3115                sizeof(qcaps->mac_address));
3116         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3117         qcaps->max_rx_rings = fcfg->num_rx_rings;
3118         qcaps->max_tx_rings = fcfg->num_tx_rings;
3119         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3120         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3121         qcaps->max_vfs = 0;
3122         qcaps->first_vf_id = 0;
3123         qcaps->max_vnics = fcfg->num_vnics;
3124         qcaps->max_decap_records = 0;
3125         qcaps->max_encap_records = 0;
3126         qcaps->max_tx_wm_flows = 0;
3127         qcaps->max_tx_em_flows = 0;
3128         qcaps->max_rx_wm_flows = 0;
3129         qcaps->max_rx_em_flows = 0;
3130         qcaps->max_flow_id = 0;
3131         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3132         qcaps->max_sp_tx_rings = 0;
3133         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3134 }
3135
3136 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3137 {
3138         struct hwrm_func_cfg_input req = {0};
3139         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3140         uint32_t enables;
3141         int rc;
3142
3143         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3144                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3145                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3146                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3147                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3148                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3149                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3150                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3151                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3152
3153         if (BNXT_HAS_RING_GRPS(bp)) {
3154                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3155                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3156         } else if (BNXT_HAS_NQ(bp)) {
3157                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3158                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3159         }
3160
3161         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3162         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3163         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3164         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3165         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3166         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3167         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3168         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3169         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3170         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3171         req.fid = rte_cpu_to_le_16(0xffff);
3172         req.enables = rte_cpu_to_le_32(enables);
3173
3174         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3175
3176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3177
3178         HWRM_CHECK_RESULT();
3179         HWRM_UNLOCK();
3180
3181         return rc;
3182 }
3183
3184 static void populate_vf_func_cfg_req(struct bnxt *bp,
3185                                      struct hwrm_func_cfg_input *req,
3186                                      int num_vfs)
3187 {
3188         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3189                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3190                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3191                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3192                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3193                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3194                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3195                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3196                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3197                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3198
3199         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3200                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3201                                     BNXT_NUM_VLANS);
3202         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3203         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3204                                                 (num_vfs + 1));
3205         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3206         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3207                                                (num_vfs + 1));
3208         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3209         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3210         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3211         /* TODO: For now, do not support VMDq/RFS on VFs. */
3212         req->num_vnics = rte_cpu_to_le_16(1);
3213         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3214                                                  (num_vfs + 1));
3215 }
3216
3217 static void add_random_mac_if_needed(struct bnxt *bp,
3218                                      struct hwrm_func_cfg_input *cfg_req,
3219                                      int vf)
3220 {
3221         struct rte_ether_addr mac;
3222
3223         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3224                 return;
3225
3226         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3227                 cfg_req->enables |=
3228                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3229                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3230                 bp->pf.vf_info[vf].random_mac = true;
3231         } else {
3232                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3233                         RTE_ETHER_ADDR_LEN);
3234         }
3235 }
3236
3237 static int reserve_resources_from_vf(struct bnxt *bp,
3238                                      struct hwrm_func_cfg_input *cfg_req,
3239                                      int vf)
3240 {
3241         struct hwrm_func_qcaps_input req = {0};
3242         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3243         int rc;
3244
3245         /* Get the actual allocated values now */
3246         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3247         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3248         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3249
3250         if (rc) {
3251                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3252                 copy_func_cfg_to_qcaps(cfg_req, resp);
3253         } else if (resp->error_code) {
3254                 rc = rte_le_to_cpu_16(resp->error_code);
3255                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3256                 copy_func_cfg_to_qcaps(cfg_req, resp);
3257         }
3258
3259         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3260         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3261         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3262         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3263         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3264         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3265         /*
3266          * TODO: While not supporting VMDq with VFs, max_vnics is always
3267          * forced to 1 in this case
3268          */
3269         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3270         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3271
3272         HWRM_UNLOCK();
3273
3274         return 0;
3275 }
3276
3277 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3278 {
3279         struct hwrm_func_qcfg_input req = {0};
3280         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3281         int rc;
3282
3283         /* Check for zero MAC address */
3284         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3285         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3286         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3287         HWRM_CHECK_RESULT();
3288         rc = rte_le_to_cpu_16(resp->vlan);
3289
3290         HWRM_UNLOCK();
3291
3292         return rc;
3293 }
3294
3295 static int update_pf_resource_max(struct bnxt *bp)
3296 {
3297         struct hwrm_func_qcfg_input req = {0};
3298         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3299         int rc;
3300
3301         /* And copy the allocated numbers into the pf struct */
3302         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3303         req.fid = rte_cpu_to_le_16(0xffff);
3304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3305         HWRM_CHECK_RESULT();
3306
3307         /* Only TX ring value reflects actual allocation? TODO */
3308         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3309         bp->pf.evb_mode = resp->evb_mode;
3310
3311         HWRM_UNLOCK();
3312
3313         return rc;
3314 }
3315
3316 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3317 {
3318         int rc;
3319
3320         if (!BNXT_PF(bp)) {
3321                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3322                 return -EINVAL;
3323         }
3324
3325         rc = bnxt_hwrm_func_qcaps(bp);
3326         if (rc)
3327                 return rc;
3328
3329         bp->pf.func_cfg_flags &=
3330                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3331                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3332         bp->pf.func_cfg_flags |=
3333                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3334         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3335         rc = __bnxt_hwrm_func_qcaps(bp);
3336         return rc;
3337 }
3338
3339 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3340 {
3341         struct hwrm_func_cfg_input req = {0};
3342         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3343         int i;
3344         size_t sz;
3345         int rc = 0;
3346         size_t req_buf_sz;
3347
3348         if (!BNXT_PF(bp)) {
3349                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3350                 return -EINVAL;
3351         }
3352
3353         rc = bnxt_hwrm_func_qcaps(bp);
3354
3355         if (rc)
3356                 return rc;
3357
3358         bp->pf.active_vfs = num_vfs;
3359
3360         /*
3361          * First, configure the PF to only use one TX ring.  This ensures that
3362          * there are enough rings for all VFs.
3363          *
3364          * If we don't do this, when we call func_alloc() later, we will lock
3365          * extra rings to the PF that won't be available during func_cfg() of
3366          * the VFs.
3367          *
3368          * This has been fixed with firmware versions above 20.6.54
3369          */
3370         bp->pf.func_cfg_flags &=
3371                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3372                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3373         bp->pf.func_cfg_flags |=
3374                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3375         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3376         if (rc)
3377                 return rc;
3378
3379         /*
3380          * Now, create and register a buffer to hold forwarded VF requests
3381          */
3382         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3383         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3384                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3385         if (bp->pf.vf_req_buf == NULL) {
3386                 rc = -ENOMEM;
3387                 goto error_free;
3388         }
3389         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3390                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3391         for (i = 0; i < num_vfs; i++)
3392                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3393                                         (i * HWRM_MAX_REQ_LEN);
3394
3395         rc = bnxt_hwrm_func_buf_rgtr(bp);
3396         if (rc)
3397                 goto error_free;
3398
3399         populate_vf_func_cfg_req(bp, &req, num_vfs);
3400
3401         bp->pf.active_vfs = 0;
3402         for (i = 0; i < num_vfs; i++) {
3403                 add_random_mac_if_needed(bp, &req, i);
3404
3405                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3406                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3407                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3408                 rc = bnxt_hwrm_send_message(bp,
3409                                             &req,
3410                                             sizeof(req),
3411                                             BNXT_USE_CHIMP_MB);
3412
3413                 /* Clear enable flag for next pass */
3414                 req.enables &= ~rte_cpu_to_le_32(
3415                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3416
3417                 if (rc || resp->error_code) {
3418                         PMD_DRV_LOG(ERR,
3419                                 "Failed to initizlie VF %d\n", i);
3420                         PMD_DRV_LOG(ERR,
3421                                 "Not all VFs available. (%d, %d)\n",
3422                                 rc, resp->error_code);
3423                         HWRM_UNLOCK();
3424                         break;
3425                 }
3426
3427                 HWRM_UNLOCK();
3428
3429                 reserve_resources_from_vf(bp, &req, i);
3430                 bp->pf.active_vfs++;
3431                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3432         }
3433
3434         /*
3435          * Now configure the PF to use "the rest" of the resources
3436          * We're using STD_TX_RING_MODE here though which will limit the TX
3437          * rings.  This will allow QoS to function properly.  Not setting this
3438          * will cause PF rings to break bandwidth settings.
3439          */
3440         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3441         if (rc)
3442                 goto error_free;
3443
3444         rc = update_pf_resource_max(bp);
3445         if (rc)
3446                 goto error_free;
3447
3448         return rc;
3449
3450 error_free:
3451         bnxt_hwrm_func_buf_unrgtr(bp);
3452         return rc;
3453 }
3454
3455 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3456 {
3457         struct hwrm_func_cfg_input req = {0};
3458         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3459         int rc;
3460
3461         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3462
3463         req.fid = rte_cpu_to_le_16(0xffff);
3464         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3465         req.evb_mode = bp->pf.evb_mode;
3466
3467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3468         HWRM_CHECK_RESULT();
3469         HWRM_UNLOCK();
3470
3471         return rc;
3472 }
3473
3474 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3475                                 uint8_t tunnel_type)
3476 {
3477         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3478         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3479         int rc = 0;
3480
3481         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3482         req.tunnel_type = tunnel_type;
3483         req.tunnel_dst_port_val = port;
3484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3485         HWRM_CHECK_RESULT();
3486
3487         switch (tunnel_type) {
3488         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3489                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3490                 bp->vxlan_port = port;
3491                 break;
3492         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3493                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3494                 bp->geneve_port = port;
3495                 break;
3496         default:
3497                 break;
3498         }
3499
3500         HWRM_UNLOCK();
3501
3502         return rc;
3503 }
3504
3505 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3506                                 uint8_t tunnel_type)
3507 {
3508         struct hwrm_tunnel_dst_port_free_input req = {0};
3509         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3510         int rc = 0;
3511
3512         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3513
3514         req.tunnel_type = tunnel_type;
3515         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3517
3518         HWRM_CHECK_RESULT();
3519         HWRM_UNLOCK();
3520
3521         return rc;
3522 }
3523
3524 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3525                                         uint32_t flags)
3526 {
3527         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3528         struct hwrm_func_cfg_input req = {0};
3529         int rc;
3530
3531         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3532
3533         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3534         req.flags = rte_cpu_to_le_32(flags);
3535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3536
3537         HWRM_CHECK_RESULT();
3538         HWRM_UNLOCK();
3539
3540         return rc;
3541 }
3542
3543 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3544 {
3545         uint32_t *flag = flagp;
3546
3547         vnic->flags = *flag;
3548 }
3549
3550 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3551 {
3552         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3553 }
3554
3555 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3556 {
3557         int rc = 0;
3558         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3559         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3560
3561         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3562
3563         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3564         req.req_buf_page_size = rte_cpu_to_le_16(
3565                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3566         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3567         req.req_buf_page_addr0 =
3568                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3569         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3570                 PMD_DRV_LOG(ERR,
3571                         "unable to map buffer address to physical memory\n");
3572                 return -ENOMEM;
3573         }
3574
3575         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3576
3577         HWRM_CHECK_RESULT();
3578         HWRM_UNLOCK();
3579
3580         return rc;
3581 }
3582
3583 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3584 {
3585         int rc = 0;
3586         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3587         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3588
3589         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3590                 return 0;
3591
3592         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3593
3594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3595
3596         HWRM_CHECK_RESULT();
3597         HWRM_UNLOCK();
3598
3599         return rc;
3600 }
3601
3602 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3603 {
3604         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3605         struct hwrm_func_cfg_input req = {0};
3606         int rc;
3607
3608         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3609
3610         req.fid = rte_cpu_to_le_16(0xffff);
3611         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3612         req.enables = rte_cpu_to_le_32(
3613                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3614         req.async_event_cr = rte_cpu_to_le_16(
3615                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3616         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3617
3618         HWRM_CHECK_RESULT();
3619         HWRM_UNLOCK();
3620
3621         return rc;
3622 }
3623
3624 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3625 {
3626         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3627         struct hwrm_func_vf_cfg_input req = {0};
3628         int rc;
3629
3630         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3631
3632         req.enables = rte_cpu_to_le_32(
3633                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3634         req.async_event_cr = rte_cpu_to_le_16(
3635                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3636         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3637
3638         HWRM_CHECK_RESULT();
3639         HWRM_UNLOCK();
3640
3641         return rc;
3642 }
3643
3644 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3645 {
3646         struct hwrm_func_cfg_input req = {0};
3647         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3648         uint16_t dflt_vlan, fid;
3649         uint32_t func_cfg_flags;
3650         int rc = 0;
3651
3652         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3653
3654         if (is_vf) {
3655                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3656                 fid = bp->pf.vf_info[vf].fid;
3657                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3658         } else {
3659                 fid = rte_cpu_to_le_16(0xffff);
3660                 func_cfg_flags = bp->pf.func_cfg_flags;
3661                 dflt_vlan = bp->vlan;
3662         }
3663
3664         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3665         req.fid = rte_cpu_to_le_16(fid);
3666         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3667         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3668
3669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3670
3671         HWRM_CHECK_RESULT();
3672         HWRM_UNLOCK();
3673
3674         return rc;
3675 }
3676
3677 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3678                         uint16_t max_bw, uint16_t enables)
3679 {
3680         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3681         struct hwrm_func_cfg_input req = {0};
3682         int rc;
3683
3684         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3685
3686         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3687         req.enables |= rte_cpu_to_le_32(enables);
3688         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3689         req.max_bw = rte_cpu_to_le_32(max_bw);
3690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3691
3692         HWRM_CHECK_RESULT();
3693         HWRM_UNLOCK();
3694
3695         return rc;
3696 }
3697
3698 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3699 {
3700         struct hwrm_func_cfg_input req = {0};
3701         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3702         int rc = 0;
3703
3704         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3705
3706         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3707         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3708         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3709         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3710
3711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3712
3713         HWRM_CHECK_RESULT();
3714         HWRM_UNLOCK();
3715
3716         return rc;
3717 }
3718
3719 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3720 {
3721         int rc;
3722
3723         if (BNXT_PF(bp))
3724                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3725         else
3726                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3727
3728         return rc;
3729 }
3730
3731 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3732                               void *encaped, size_t ec_size)
3733 {
3734         int rc = 0;
3735         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3736         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3737
3738         if (ec_size > sizeof(req.encap_request))
3739                 return -1;
3740
3741         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3742
3743         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3744         memcpy(req.encap_request, encaped, ec_size);
3745
3746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3747
3748         HWRM_CHECK_RESULT();
3749         HWRM_UNLOCK();
3750
3751         return rc;
3752 }
3753
3754 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3755                                        struct rte_ether_addr *mac)
3756 {
3757         struct hwrm_func_qcfg_input req = {0};
3758         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3759         int rc;
3760
3761         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3762
3763         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3764         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3765
3766         HWRM_CHECK_RESULT();
3767
3768         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3769
3770         HWRM_UNLOCK();
3771
3772         return rc;
3773 }
3774
3775 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3776                             void *encaped, size_t ec_size)
3777 {
3778         int rc = 0;
3779         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3780         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3781
3782         if (ec_size > sizeof(req.encap_request))
3783                 return -1;
3784
3785         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3786
3787         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3788         memcpy(req.encap_request, encaped, ec_size);
3789
3790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3791
3792         HWRM_CHECK_RESULT();
3793         HWRM_UNLOCK();
3794
3795         return rc;
3796 }
3797
3798 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3799                          struct rte_eth_stats *stats, uint8_t rx)
3800 {
3801         int rc = 0;
3802         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3803         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3804
3805         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3806
3807         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3808
3809         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3810
3811         HWRM_CHECK_RESULT();
3812
3813         if (rx) {
3814                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3815                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3816                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3817                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3818                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3819                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3820                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3821                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3822         } else {
3823                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3824                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3825                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3826                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3827                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3828                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3829         }
3830
3831         HWRM_UNLOCK();
3832
3833         return rc;
3834 }
3835
3836 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3837 {
3838         struct hwrm_port_qstats_input req = {0};
3839         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3840         struct bnxt_pf_info *pf = &bp->pf;
3841         int rc;
3842
3843         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3844
3845         req.port_id = rte_cpu_to_le_16(pf->port_id);
3846         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3847         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3849
3850         HWRM_CHECK_RESULT();
3851         HWRM_UNLOCK();
3852
3853         return rc;
3854 }
3855
3856 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3857 {
3858         struct hwrm_port_clr_stats_input req = {0};
3859         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3860         struct bnxt_pf_info *pf = &bp->pf;
3861         int rc;
3862
3863         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3864         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3865             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3866                 return 0;
3867
3868         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3869
3870         req.port_id = rte_cpu_to_le_16(pf->port_id);
3871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3872
3873         HWRM_CHECK_RESULT();
3874         HWRM_UNLOCK();
3875
3876         return rc;
3877 }
3878
3879 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3880 {
3881         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3882         struct hwrm_port_led_qcaps_input req = {0};
3883         int rc;
3884
3885         if (BNXT_VF(bp))
3886                 return 0;
3887
3888         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3889         req.port_id = bp->pf.port_id;
3890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3891
3892         HWRM_CHECK_RESULT();
3893
3894         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3895                 unsigned int i;
3896
3897                 bp->num_leds = resp->num_leds;
3898                 memcpy(bp->leds, &resp->led0_id,
3899                         sizeof(bp->leds[0]) * bp->num_leds);
3900                 for (i = 0; i < bp->num_leds; i++) {
3901                         struct bnxt_led_info *led = &bp->leds[i];
3902
3903                         uint16_t caps = led->led_state_caps;
3904
3905                         if (!led->led_group_id ||
3906                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3907                                 bp->num_leds = 0;
3908                                 break;
3909                         }
3910                 }
3911         }
3912
3913         HWRM_UNLOCK();
3914
3915         return rc;
3916 }
3917
3918 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3919 {
3920         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3921         struct hwrm_port_led_cfg_input req = {0};
3922         struct bnxt_led_cfg *led_cfg;
3923         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3924         uint16_t duration = 0;
3925         int rc, i;
3926
3927         if (!bp->num_leds || BNXT_VF(bp))
3928                 return -EOPNOTSUPP;
3929
3930         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3931
3932         if (led_on) {
3933                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3934                 duration = rte_cpu_to_le_16(500);
3935         }
3936         req.port_id = bp->pf.port_id;
3937         req.num_leds = bp->num_leds;
3938         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3939         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3940                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3941                 led_cfg->led_id = bp->leds[i].led_id;
3942                 led_cfg->led_state = led_state;
3943                 led_cfg->led_blink_on = duration;
3944                 led_cfg->led_blink_off = duration;
3945                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3946         }
3947
3948         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3949
3950         HWRM_CHECK_RESULT();
3951         HWRM_UNLOCK();
3952
3953         return rc;
3954 }
3955
3956 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3957                                uint32_t *length)
3958 {
3959         int rc;
3960         struct hwrm_nvm_get_dir_info_input req = {0};
3961         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3962
3963         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3964
3965         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3966
3967         HWRM_CHECK_RESULT();
3968
3969         *entries = rte_le_to_cpu_32(resp->entries);
3970         *length = rte_le_to_cpu_32(resp->entry_length);
3971
3972         HWRM_UNLOCK();
3973         return rc;
3974 }
3975
3976 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3977 {
3978         int rc;
3979         uint32_t dir_entries;
3980         uint32_t entry_length;
3981         uint8_t *buf;
3982         size_t buflen;
3983         rte_iova_t dma_handle;
3984         struct hwrm_nvm_get_dir_entries_input req = {0};
3985         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3986
3987         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3988         if (rc != 0)
3989                 return rc;
3990
3991         *data++ = dir_entries;
3992         *data++ = entry_length;
3993         len -= 2;
3994         memset(data, 0xff, len);
3995
3996         buflen = dir_entries * entry_length;
3997         buf = rte_malloc("nvm_dir", buflen, 0);
3998         if (buf == NULL)
3999                 return -ENOMEM;
4000         dma_handle = rte_malloc_virt2iova(buf);
4001         if (dma_handle == RTE_BAD_IOVA) {
4002                 PMD_DRV_LOG(ERR,
4003                         "unable to map response address to physical memory\n");
4004                 return -ENOMEM;
4005         }
4006         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4007         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4009
4010         if (rc == 0)
4011                 memcpy(data, buf, len > buflen ? buflen : len);
4012
4013         rte_free(buf);
4014         HWRM_CHECK_RESULT();
4015         HWRM_UNLOCK();
4016
4017         return rc;
4018 }
4019
4020 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4021                              uint32_t offset, uint32_t length,
4022                              uint8_t *data)
4023 {
4024         int rc;
4025         uint8_t *buf;
4026         rte_iova_t dma_handle;
4027         struct hwrm_nvm_read_input req = {0};
4028         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4029
4030         buf = rte_malloc("nvm_item", length, 0);
4031         if (!buf)
4032                 return -ENOMEM;
4033
4034         dma_handle = rte_malloc_virt2iova(buf);
4035         if (dma_handle == RTE_BAD_IOVA) {
4036                 PMD_DRV_LOG(ERR,
4037                         "unable to map response address to physical memory\n");
4038                 return -ENOMEM;
4039         }
4040         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4041         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4042         req.dir_idx = rte_cpu_to_le_16(index);
4043         req.offset = rte_cpu_to_le_32(offset);
4044         req.len = rte_cpu_to_le_32(length);
4045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4046         if (rc == 0)
4047                 memcpy(data, buf, length);
4048
4049         rte_free(buf);
4050         HWRM_CHECK_RESULT();
4051         HWRM_UNLOCK();
4052
4053         return rc;
4054 }
4055
4056 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4057 {
4058         int rc;
4059         struct hwrm_nvm_erase_dir_entry_input req = {0};
4060         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4061
4062         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4063         req.dir_idx = rte_cpu_to_le_16(index);
4064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4065         HWRM_CHECK_RESULT();
4066         HWRM_UNLOCK();
4067
4068         return rc;
4069 }
4070
4071
4072 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4073                           uint16_t dir_ordinal, uint16_t dir_ext,
4074                           uint16_t dir_attr, const uint8_t *data,
4075                           size_t data_len)
4076 {
4077         int rc;
4078         struct hwrm_nvm_write_input req = {0};
4079         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4080         rte_iova_t dma_handle;
4081         uint8_t *buf;
4082
4083         buf = rte_malloc("nvm_write", data_len, 0);
4084         if (!buf)
4085                 return -ENOMEM;
4086
4087         dma_handle = rte_malloc_virt2iova(buf);
4088         if (dma_handle == RTE_BAD_IOVA) {
4089                 PMD_DRV_LOG(ERR,
4090                         "unable to map response address to physical memory\n");
4091                 return -ENOMEM;
4092         }
4093         memcpy(buf, data, data_len);
4094
4095         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4096
4097         req.dir_type = rte_cpu_to_le_16(dir_type);
4098         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4099         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4100         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4101         req.dir_data_length = rte_cpu_to_le_32(data_len);
4102         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4103
4104         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4105
4106         rte_free(buf);
4107         HWRM_CHECK_RESULT();
4108         HWRM_UNLOCK();
4109
4110         return rc;
4111 }
4112
4113 static void
4114 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4115 {
4116         uint32_t *count = cbdata;
4117
4118         *count = *count + 1;
4119 }
4120
4121 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4122                                      struct bnxt_vnic_info *vnic __rte_unused)
4123 {
4124         return 0;
4125 }
4126
4127 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4128 {
4129         uint32_t count = 0;
4130
4131         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4132             &count, bnxt_vnic_count_hwrm_stub);
4133
4134         return count;
4135 }
4136
4137 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4138                                         uint16_t *vnic_ids)
4139 {
4140         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4141         struct hwrm_func_vf_vnic_ids_query_output *resp =
4142                                                 bp->hwrm_cmd_resp_addr;
4143         int rc;
4144
4145         /* First query all VNIC ids */
4146         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4147
4148         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4149         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4150         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4151
4152         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4153                 HWRM_UNLOCK();
4154                 PMD_DRV_LOG(ERR,
4155                 "unable to map VNIC ID table address to physical memory\n");
4156                 return -ENOMEM;
4157         }
4158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4159         HWRM_CHECK_RESULT();
4160         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4161
4162         HWRM_UNLOCK();
4163
4164         return rc;
4165 }
4166
4167 /*
4168  * This function queries the VNIC IDs  for a specified VF. It then calls
4169  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4170  * Then it calls the hwrm_cb function to program this new vnic configuration.
4171  */
4172 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4173         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4174         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4175 {
4176         struct bnxt_vnic_info vnic;
4177         int rc = 0;
4178         int i, num_vnic_ids;
4179         uint16_t *vnic_ids;
4180         size_t vnic_id_sz;
4181         size_t sz;
4182
4183         /* First query all VNIC ids */
4184         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4185         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4186                         RTE_CACHE_LINE_SIZE);
4187         if (vnic_ids == NULL)
4188                 return -ENOMEM;
4189
4190         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4191                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4192
4193         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4194
4195         if (num_vnic_ids < 0)
4196                 return num_vnic_ids;
4197
4198         /* Retrieve VNIC, update bd_stall then update */
4199
4200         for (i = 0; i < num_vnic_ids; i++) {
4201                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4202                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4203                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4204                 if (rc)
4205                         break;
4206                 if (vnic.mru <= 4)      /* Indicates unallocated */
4207                         continue;
4208
4209                 vnic_cb(&vnic, cbdata);
4210
4211                 rc = hwrm_cb(bp, &vnic);
4212                 if (rc)
4213                         break;
4214         }
4215
4216         rte_free(vnic_ids);
4217
4218         return rc;
4219 }
4220
4221 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4222                                               bool on)
4223 {
4224         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4225         struct hwrm_func_cfg_input req = {0};
4226         int rc;
4227
4228         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4229
4230         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4231         req.enables |= rte_cpu_to_le_32(
4232                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4233         req.vlan_antispoof_mode = on ?
4234                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4235                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4237
4238         HWRM_CHECK_RESULT();
4239         HWRM_UNLOCK();
4240
4241         return rc;
4242 }
4243
4244 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4245 {
4246         struct bnxt_vnic_info vnic;
4247         uint16_t *vnic_ids;
4248         size_t vnic_id_sz;
4249         int num_vnic_ids, i;
4250         size_t sz;
4251         int rc;
4252
4253         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4254         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4255                         RTE_CACHE_LINE_SIZE);
4256         if (vnic_ids == NULL)
4257                 return -ENOMEM;
4258
4259         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4260                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4261
4262         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4263         if (rc <= 0)
4264                 goto exit;
4265         num_vnic_ids = rc;
4266
4267         /*
4268          * Loop through to find the default VNIC ID.
4269          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4270          * by sending the hwrm_func_qcfg command to the firmware.
4271          */
4272         for (i = 0; i < num_vnic_ids; i++) {
4273                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4274                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4275                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4276                                         bp->pf.first_vf_id + vf);
4277                 if (rc)
4278                         goto exit;
4279                 if (vnic.func_default) {
4280                         rte_free(vnic_ids);
4281                         return vnic.fw_vnic_id;
4282                 }
4283         }
4284         /* Could not find a default VNIC. */
4285         PMD_DRV_LOG(ERR, "No default VNIC\n");
4286 exit:
4287         rte_free(vnic_ids);
4288         return rc;
4289 }
4290
4291 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4292                          uint16_t dst_id,
4293                          struct bnxt_filter_info *filter)
4294 {
4295         int rc = 0;
4296         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4297         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4298         uint32_t enables = 0;
4299
4300         if (filter->fw_em_filter_id != UINT64_MAX)
4301                 bnxt_hwrm_clear_em_filter(bp, filter);
4302
4303         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4304
4305         req.flags = rte_cpu_to_le_32(filter->flags);
4306
4307         enables = filter->enables |
4308               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4309         req.dst_id = rte_cpu_to_le_16(dst_id);
4310
4311         if (filter->ip_addr_type) {
4312                 req.ip_addr_type = filter->ip_addr_type;
4313                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4314         }
4315         if (enables &
4316             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4317                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4318         if (enables &
4319             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4320                 memcpy(req.src_macaddr, filter->src_macaddr,
4321                        RTE_ETHER_ADDR_LEN);
4322         if (enables &
4323             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4324                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4325                        RTE_ETHER_ADDR_LEN);
4326         if (enables &
4327             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4328                 req.ovlan_vid = filter->l2_ovlan;
4329         if (enables &
4330             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4331                 req.ivlan_vid = filter->l2_ivlan;
4332         if (enables &
4333             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4334                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4335         if (enables &
4336             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4337                 req.ip_protocol = filter->ip_protocol;
4338         if (enables &
4339             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4340                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4341         if (enables &
4342             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4343                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4344         if (enables &
4345             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4346                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4347         if (enables &
4348             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4349                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4350         if (enables &
4351             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4352                 req.mirror_vnic_id = filter->mirror_vnic_id;
4353
4354         req.enables = rte_cpu_to_le_32(enables);
4355
4356         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4357
4358         HWRM_CHECK_RESULT();
4359
4360         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4361         HWRM_UNLOCK();
4362
4363         return rc;
4364 }
4365
4366 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4367 {
4368         int rc = 0;
4369         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4370         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4371
4372         if (filter->fw_em_filter_id == UINT64_MAX)
4373                 return 0;
4374
4375         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4376
4377         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4378
4379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4380
4381         HWRM_CHECK_RESULT();
4382         HWRM_UNLOCK();
4383
4384         filter->fw_em_filter_id = UINT64_MAX;
4385         filter->fw_l2_filter_id = UINT64_MAX;
4386
4387         return 0;
4388 }
4389
4390 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4391                          uint16_t dst_id,
4392                          struct bnxt_filter_info *filter)
4393 {
4394         int rc = 0;
4395         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4396         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4397                                                 bp->hwrm_cmd_resp_addr;
4398         uint32_t enables = 0;
4399
4400         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4401                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4402
4403         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4404
4405         req.flags = rte_cpu_to_le_32(filter->flags);
4406
4407         enables = filter->enables |
4408               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4409         req.dst_id = rte_cpu_to_le_16(dst_id);
4410
4411         if (filter->ip_addr_type) {
4412                 req.ip_addr_type = filter->ip_addr_type;
4413                 enables |=
4414                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4415         }
4416         if (enables &
4417             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4418                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4419         if (enables &
4420             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4421                 memcpy(req.src_macaddr, filter->src_macaddr,
4422                        RTE_ETHER_ADDR_LEN);
4423         if (enables &
4424             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4425                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4426         if (enables &
4427             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4428                 req.ip_protocol = filter->ip_protocol;
4429         if (enables &
4430             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4431                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4432         if (enables &
4433             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4434                 req.src_ipaddr_mask[0] =
4435                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4436         if (enables &
4437             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4438                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4439         if (enables &
4440             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4441                 req.dst_ipaddr_mask[0] =
4442                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4443         if (enables &
4444             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4445                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4446         if (enables &
4447             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4448                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4449         if (enables &
4450             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4451                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4452         if (enables &
4453             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4454                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4455         if (enables &
4456             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4457                 req.mirror_vnic_id = filter->mirror_vnic_id;
4458
4459         req.enables = rte_cpu_to_le_32(enables);
4460
4461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4462
4463         HWRM_CHECK_RESULT();
4464
4465         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4466         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4467         HWRM_UNLOCK();
4468
4469         return rc;
4470 }
4471
4472 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4473                                 struct bnxt_filter_info *filter)
4474 {
4475         int rc = 0;
4476         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4477         struct hwrm_cfa_ntuple_filter_free_output *resp =
4478                                                 bp->hwrm_cmd_resp_addr;
4479
4480         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4481                 return 0;
4482
4483         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4484
4485         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4486
4487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4488
4489         HWRM_CHECK_RESULT();
4490         HWRM_UNLOCK();
4491
4492         filter->fw_ntuple_filter_id = UINT64_MAX;
4493
4494         return 0;
4495 }
4496
4497 static int
4498 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4499 {
4500         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4501         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4502         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4503         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4504         uint16_t *ring_tbl = vnic->rss_table;
4505         int nr_ctxs = vnic->num_lb_ctxts;
4506         int max_rings = bp->rx_nr_rings;
4507         int i, j, k, cnt;
4508         int rc = 0;
4509
4510         for (i = 0, k = 0; i < nr_ctxs; i++) {
4511                 struct bnxt_rx_ring_info *rxr;
4512                 struct bnxt_cp_ring_info *cpr;
4513
4514                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4515
4516                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4517                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4518                 req.hash_mode_flags = vnic->hash_mode;
4519
4520                 req.ring_grp_tbl_addr =
4521                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4522                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4523                                      2 * sizeof(*ring_tbl));
4524                 req.hash_key_tbl_addr =
4525                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4526
4527                 req.ring_table_pair_index = i;
4528                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4529
4530                 for (j = 0; j < 64; j++) {
4531                         uint16_t ring_id;
4532
4533                         /* Find next active ring. */
4534                         for (cnt = 0; cnt < max_rings; cnt++) {
4535                                 if (rx_queue_state[k] !=
4536                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4537                                         break;
4538                                 if (++k == max_rings)
4539                                         k = 0;
4540                         }
4541
4542                         /* Return if no rings are active. */
4543                         if (cnt == max_rings) {
4544                                 HWRM_UNLOCK();
4545                                 return 0;
4546                         }
4547
4548                         /* Add rx/cp ring pair to RSS table. */
4549                         rxr = rxqs[k]->rx_ring;
4550                         cpr = rxqs[k]->cp_ring;
4551
4552                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4553                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4554                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4555                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4556
4557                         if (++k == max_rings)
4558                                 k = 0;
4559                 }
4560                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4561                                             BNXT_USE_CHIMP_MB);
4562
4563                 HWRM_CHECK_RESULT();
4564                 HWRM_UNLOCK();
4565         }
4566
4567         return rc;
4568 }
4569
4570 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4571 {
4572         unsigned int rss_idx, fw_idx, i;
4573
4574         if (!(vnic->rss_table && vnic->hash_type))
4575                 return 0;
4576
4577         if (BNXT_CHIP_THOR(bp))
4578                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4579
4580         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4581                 return 0;
4582
4583         if (vnic->rss_table && vnic->hash_type) {
4584                 /*
4585                  * Fill the RSS hash & redirection table with
4586                  * ring group ids for all VNICs
4587                  */
4588                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4589                         rss_idx++, fw_idx++) {
4590                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4591                                 fw_idx %= bp->rx_cp_nr_rings;
4592                                 if (vnic->fw_grp_ids[fw_idx] !=
4593                                     INVALID_HW_RING_ID)
4594                                         break;
4595                                 fw_idx++;
4596                         }
4597                         if (i == bp->rx_cp_nr_rings)
4598                                 return 0;
4599                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4600                 }
4601                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4602         }
4603
4604         return 0;
4605 }
4606
4607 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4608         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4609 {
4610         uint16_t flags;
4611
4612         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4613
4614         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4615         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4616
4617         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4618         req->num_cmpl_dma_aggr_during_int =
4619                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4620
4621         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4622
4623         /* min timer set to 1/2 of interrupt timer */
4624         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4625
4626         /* buf timer set to 1/4 of interrupt timer */
4627         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4628
4629         req->cmpl_aggr_dma_tmr_during_int =
4630                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4631
4632         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4633                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4634         req->flags = rte_cpu_to_le_16(flags);
4635 }
4636
4637 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4638                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4639 {
4640         struct hwrm_ring_aggint_qcaps_input req = {0};
4641         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4642         uint32_t enables;
4643         uint16_t flags;
4644         int rc;
4645
4646         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4648         HWRM_CHECK_RESULT();
4649
4650         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4651         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4652
4653         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4654                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4655         agg_req->flags = rte_cpu_to_le_16(flags);
4656         enables =
4657          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4658          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4659         agg_req->enables = rte_cpu_to_le_32(enables);
4660
4661         HWRM_UNLOCK();
4662         return rc;
4663 }
4664
4665 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4666                         struct bnxt_coal *coal, uint16_t ring_id)
4667 {
4668         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4669         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4670                                                 bp->hwrm_cmd_resp_addr;
4671         int rc;
4672
4673         /* Set ring coalesce parameters only for 100G NICs */
4674         if (BNXT_CHIP_THOR(bp)) {
4675                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4676                         return -1;
4677         } else if (bnxt_stratus_device(bp)) {
4678                 bnxt_hwrm_set_coal_params(coal, &req);
4679         } else {
4680                 return 0;
4681         }
4682
4683         HWRM_PREP(&req,
4684                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4685                   BNXT_USE_CHIMP_MB);
4686         req.ring_id = rte_cpu_to_le_16(ring_id);
4687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4688         HWRM_CHECK_RESULT();
4689         HWRM_UNLOCK();
4690         return 0;
4691 }
4692
4693 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4694 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4695 {
4696         struct hwrm_func_backing_store_qcaps_input req = {0};
4697         struct hwrm_func_backing_store_qcaps_output *resp =
4698                 bp->hwrm_cmd_resp_addr;
4699         struct bnxt_ctx_pg_info *ctx_pg;
4700         struct bnxt_ctx_mem_info *ctx;
4701         int total_alloc_len;
4702         int rc, i;
4703
4704         if (!BNXT_CHIP_THOR(bp) ||
4705             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4706             BNXT_VF(bp) ||
4707             bp->ctx)
4708                 return 0;
4709
4710         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4712         HWRM_CHECK_RESULT_SILENT();
4713
4714         total_alloc_len = sizeof(*ctx);
4715         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4716                           RTE_CACHE_LINE_SIZE);
4717         if (!ctx) {
4718                 rc = -ENOMEM;
4719                 goto ctx_err;
4720         }
4721
4722         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4723                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4724                             RTE_CACHE_LINE_SIZE);
4725         if (!ctx_pg) {
4726                 rc = -ENOMEM;
4727                 goto ctx_err;
4728         }
4729         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4730                 ctx->tqm_mem[i] = ctx_pg;
4731
4732         bp->ctx = ctx;
4733         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4734         ctx->qp_min_qp1_entries =
4735                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4736         ctx->qp_max_l2_entries =
4737                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4738         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4739         ctx->srq_max_l2_entries =
4740                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4741         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4742         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4743         ctx->cq_max_l2_entries =
4744                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4745         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4746         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4747         ctx->vnic_max_vnic_entries =
4748                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4749         ctx->vnic_max_ring_table_entries =
4750                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4751         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4752         ctx->stat_max_entries =
4753                 rte_le_to_cpu_32(resp->stat_max_entries);
4754         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4755         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4756         ctx->tqm_min_entries_per_ring =
4757                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4758         ctx->tqm_max_entries_per_ring =
4759                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4760         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4761         if (!ctx->tqm_entries_multiple)
4762                 ctx->tqm_entries_multiple = 1;
4763         ctx->mrav_max_entries =
4764                 rte_le_to_cpu_32(resp->mrav_max_entries);
4765         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4766         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4767         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4768 ctx_err:
4769         HWRM_UNLOCK();
4770         return rc;
4771 }
4772
4773 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4774 {
4775         struct hwrm_func_backing_store_cfg_input req = {0};
4776         struct hwrm_func_backing_store_cfg_output *resp =
4777                 bp->hwrm_cmd_resp_addr;
4778         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4779         struct bnxt_ctx_pg_info *ctx_pg;
4780         uint32_t *num_entries;
4781         uint64_t *pg_dir;
4782         uint8_t *pg_attr;
4783         uint32_t ena;
4784         int i, rc;
4785
4786         if (!ctx)
4787                 return 0;
4788
4789         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4790         req.enables = rte_cpu_to_le_32(enables);
4791
4792         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4793                 ctx_pg = &ctx->qp_mem;
4794                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4795                 req.qp_num_qp1_entries =
4796                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4797                 req.qp_num_l2_entries =
4798                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4799                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4800                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4801                                       &req.qpc_pg_size_qpc_lvl,
4802                                       &req.qpc_page_dir);
4803         }
4804
4805         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4806                 ctx_pg = &ctx->srq_mem;
4807                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4808                 req.srq_num_l2_entries =
4809                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4810                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4811                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4812                                       &req.srq_pg_size_srq_lvl,
4813                                       &req.srq_page_dir);
4814         }
4815
4816         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4817                 ctx_pg = &ctx->cq_mem;
4818                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4819                 req.cq_num_l2_entries =
4820                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4821                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4822                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4823                                       &req.cq_pg_size_cq_lvl,
4824                                       &req.cq_page_dir);
4825         }
4826
4827         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4828                 ctx_pg = &ctx->vnic_mem;
4829                 req.vnic_num_vnic_entries =
4830                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4831                 req.vnic_num_ring_table_entries =
4832                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4833                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4834                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4835                                       &req.vnic_pg_size_vnic_lvl,
4836                                       &req.vnic_page_dir);
4837         }
4838
4839         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4840                 ctx_pg = &ctx->stat_mem;
4841                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4842                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4843                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4844                                       &req.stat_pg_size_stat_lvl,
4845                                       &req.stat_page_dir);
4846         }
4847
4848         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4849         num_entries = &req.tqm_sp_num_entries;
4850         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4851         pg_dir = &req.tqm_sp_page_dir;
4852         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4853         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4854                 if (!(enables & ena))
4855                         continue;
4856
4857                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4858
4859                 ctx_pg = ctx->tqm_mem[i];
4860                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4861                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4862         }
4863
4864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4865         HWRM_CHECK_RESULT();
4866         HWRM_UNLOCK();
4867
4868         return rc;
4869 }
4870
4871 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4872 {
4873         struct hwrm_port_qstats_ext_input req = {0};
4874         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4875         struct bnxt_pf_info *pf = &bp->pf;
4876         int rc;
4877
4878         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4879               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4880                 return 0;
4881
4882         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4883
4884         req.port_id = rte_cpu_to_le_16(pf->port_id);
4885         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4886                 req.tx_stat_host_addr =
4887                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4888                 req.tx_stat_size =
4889                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4890         }
4891         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4892                 req.rx_stat_host_addr =
4893                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4894                 req.rx_stat_size =
4895                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4896         }
4897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4898
4899         if (rc) {
4900                 bp->fw_rx_port_stats_ext_size = 0;
4901                 bp->fw_tx_port_stats_ext_size = 0;
4902         } else {
4903                 bp->fw_rx_port_stats_ext_size =
4904                         rte_le_to_cpu_16(resp->rx_stat_size);
4905                 bp->fw_tx_port_stats_ext_size =
4906                         rte_le_to_cpu_16(resp->tx_stat_size);
4907         }
4908
4909         HWRM_CHECK_RESULT();
4910         HWRM_UNLOCK();
4911
4912         return rc;
4913 }
4914
4915 int
4916 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4917 {
4918         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4919         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4920                 bp->hwrm_cmd_resp_addr;
4921         int rc = 0;
4922
4923         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4924         req.tunnel_type = type;
4925         req.dest_fid = bp->fw_fid;
4926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4927         HWRM_CHECK_RESULT();
4928
4929         HWRM_UNLOCK();
4930
4931         return rc;
4932 }
4933
4934 int
4935 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4936 {
4937         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4938         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4939                 bp->hwrm_cmd_resp_addr;
4940         int rc = 0;
4941
4942         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4943         req.tunnel_type = type;
4944         req.dest_fid = bp->fw_fid;
4945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4946         HWRM_CHECK_RESULT();
4947
4948         HWRM_UNLOCK();
4949
4950         return rc;
4951 }
4952
4953 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4954 {
4955         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4956         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4957                 bp->hwrm_cmd_resp_addr;
4958         int rc = 0;
4959
4960         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4961         req.src_fid = bp->fw_fid;
4962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4963         HWRM_CHECK_RESULT();
4964
4965         if (type)
4966                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4967
4968         HWRM_UNLOCK();
4969
4970         return rc;
4971 }
4972
4973 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4974                                    uint16_t *dst_fid)
4975 {
4976         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4977         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4978                 bp->hwrm_cmd_resp_addr;
4979         int rc = 0;
4980
4981         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4982         req.src_fid = bp->fw_fid;
4983         req.tunnel_type = tun_type;
4984         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4985         HWRM_CHECK_RESULT();
4986
4987         if (dst_fid)
4988                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4989
4990         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4991
4992         HWRM_UNLOCK();
4993
4994         return rc;
4995 }
4996
4997 int bnxt_hwrm_set_mac(struct bnxt *bp)
4998 {
4999         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5000         struct hwrm_func_vf_cfg_input req = {0};
5001         int rc = 0;
5002
5003         if (!BNXT_VF(bp))
5004                 return 0;
5005
5006         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5007
5008         req.enables =
5009                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5010         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5011
5012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5013
5014         HWRM_CHECK_RESULT();
5015
5016         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5017         HWRM_UNLOCK();
5018
5019         return rc;
5020 }
5021
5022 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5023 {
5024         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5025         struct hwrm_func_drv_if_change_input req = {0};
5026         uint32_t flags;
5027         int rc;
5028
5029         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5030                 return 0;
5031
5032         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5033          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5034          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5035          */
5036         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5037                 return 0;
5038
5039         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5040
5041         if (up)
5042                 req.flags =
5043                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5044
5045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5046
5047         HWRM_CHECK_RESULT();
5048         flags = rte_le_to_cpu_32(resp->flags);
5049         HWRM_UNLOCK();
5050
5051         if (!up)
5052                 return 0;
5053
5054         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5055                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5056                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5057         }
5058
5059         return 0;
5060 }
5061
5062 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5063 {
5064         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5065         struct bnxt_error_recovery_info *info = bp->recovery_info;
5066         struct hwrm_error_recovery_qcfg_input req = {0};
5067         uint32_t flags = 0;
5068         unsigned int i;
5069         int rc;
5070
5071         /* Older FW does not have error recovery support */
5072         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5073                 return 0;
5074
5075         if (!info) {
5076                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5077                                    sizeof(*info), 0);
5078                 bp->recovery_info = info;
5079                 if (info == NULL)
5080                         return -ENOMEM;
5081         } else {
5082                 memset(info, 0, sizeof(*info));
5083         }
5084
5085         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5086
5087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5088
5089         HWRM_CHECK_RESULT();
5090
5091         flags = rte_le_to_cpu_32(resp->flags);
5092         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5093                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5094         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5095                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5096
5097         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5098             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5099                 rc = -EINVAL;
5100                 goto err;
5101         }
5102
5103         /* FW returned values are in units of 100msec */
5104         info->driver_polling_freq =
5105                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5106         info->master_func_wait_period =
5107                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5108         info->normal_func_wait_period =
5109                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5110         info->master_func_wait_period_after_reset =
5111                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5112         info->max_bailout_time_after_reset =
5113                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5114         info->status_regs[BNXT_FW_STATUS_REG] =
5115                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5116         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5117                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5118         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5119                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5120         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5121                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5122         info->reg_array_cnt =
5123                 rte_le_to_cpu_32(resp->reg_array_cnt);
5124
5125         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5126                 rc = -EINVAL;
5127                 goto err;
5128         }
5129
5130         for (i = 0; i < info->reg_array_cnt; i++) {
5131                 info->reset_reg[i] =
5132                         rte_le_to_cpu_32(resp->reset_reg[i]);
5133                 info->reset_reg_val[i] =
5134                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5135                 info->delay_after_reset[i] =
5136                         resp->delay_after_reset[i];
5137         }
5138 err:
5139         HWRM_UNLOCK();
5140
5141         /* Map the FW status registers */
5142         if (!rc)
5143                 rc = bnxt_map_fw_health_status_regs(bp);
5144
5145         if (rc) {
5146                 rte_free(bp->recovery_info);
5147                 bp->recovery_info = NULL;
5148         }
5149         return rc;
5150 }
5151
5152 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5153 {
5154         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5155         struct hwrm_fw_reset_input req = {0};
5156         int rc;
5157
5158         if (!BNXT_PF(bp))
5159                 return -EOPNOTSUPP;
5160
5161         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5162
5163         req.embedded_proc_type =
5164                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5165         req.selfrst_status =
5166                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5167         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5168
5169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5170                                     BNXT_USE_KONG(bp));
5171
5172         HWRM_CHECK_RESULT();
5173         HWRM_UNLOCK();
5174
5175         return rc;
5176 }
5177
5178 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5179 {
5180         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5181         struct hwrm_port_ts_query_input req = {0};
5182         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5183         uint32_t flags = 0;
5184         int rc;
5185
5186         if (!ptp)
5187                 return 0;
5188
5189         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5190
5191         switch (path) {
5192         case BNXT_PTP_FLAGS_PATH_TX:
5193                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5194                 break;
5195         case BNXT_PTP_FLAGS_PATH_RX:
5196                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5197                 break;
5198         case BNXT_PTP_FLAGS_CURRENT_TIME:
5199                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5200                 break;
5201         }
5202
5203         req.flags = rte_cpu_to_le_32(flags);
5204         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5205
5206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5207
5208         HWRM_CHECK_RESULT();
5209
5210         if (timestamp) {
5211                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5212                 *timestamp |=
5213                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5214         }
5215         HWRM_UNLOCK();
5216
5217         return rc;
5218 }
5219
5220 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5221 {
5222         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5223                                         bp->hwrm_cmd_resp_addr;
5224         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5225         uint32_t flags = 0;
5226         int rc = 0;
5227
5228         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5229                 return rc;
5230
5231         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5232                 PMD_DRV_LOG(DEBUG,
5233                             "Not a PF or trusted VF. Command not supported\n");
5234                 return 0;
5235         }
5236
5237         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5238         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5239
5240         HWRM_CHECK_RESULT();
5241         flags = rte_le_to_cpu_32(resp->flags);
5242         HWRM_UNLOCK();
5243
5244         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5245                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5246                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5247         }
5248
5249         return rc;
5250 }
5251
5252 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5253 {
5254         int rc = 0;
5255
5256         struct hwrm_cfa_counter_qcaps_input req = {0};
5257         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5258
5259         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5260                 PMD_DRV_LOG(DEBUG,
5261                             "Not a PF or trusted VF. Command not supported\n");
5262                 return 0;
5263         }
5264
5265         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5266         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5267         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5268
5269         HWRM_CHECK_RESULT();
5270         if (max_fc)
5271                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5272         HWRM_UNLOCK();
5273
5274         PMD_DRV_LOG(DEBUG, "max_fc = %d\n", *max_fc);
5275         return 0;
5276 }
5277
5278 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5279 {
5280         int rc = 0;
5281         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5282         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5283
5284         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5285                 PMD_DRV_LOG(DEBUG,
5286                             "Not a PF or trusted VF. Command not supported\n");
5287                 return 0;
5288         }
5289
5290         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5291
5292         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5293         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5294         req.page_dir = rte_cpu_to_le_64(dma_addr);
5295
5296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5297
5298         HWRM_CHECK_RESULT();
5299         if (ctx_id) {
5300                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5301                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5302         }
5303         HWRM_UNLOCK();
5304
5305         return 0;
5306 }
5307
5308 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5309 {
5310         int rc = 0;
5311         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5312         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5313
5314         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5315                 PMD_DRV_LOG(DEBUG,
5316                             "Not a PF or trusted VF. Command not supported\n");
5317                 return 0;
5318         }
5319
5320         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5321
5322         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5323
5324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5325
5326         HWRM_CHECK_RESULT();
5327         HWRM_UNLOCK();
5328
5329         return rc;
5330 }
5331
5332 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5333                               uint16_t cntr, uint16_t ctx_id,
5334                               uint32_t num_entries, bool enable)
5335 {
5336         struct hwrm_cfa_counter_cfg_input req = {0};
5337         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5338         uint16_t flags = 0;
5339         int rc;
5340
5341         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5342                 PMD_DRV_LOG(DEBUG,
5343                             "Not a PF or trusted VF. Command not supported\n");
5344                 return 0;
5345         }
5346
5347         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5348
5349         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5350         req.counter_type = rte_cpu_to_le_16(cntr);
5351         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5352                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5353         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5354         if (dir == BNXT_DIR_RX)
5355                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5356         else if (dir == BNXT_DIR_TX)
5357                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5358         req.flags = rte_cpu_to_le_16(flags);
5359         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5360         req.num_entries = rte_cpu_to_le_32(num_entries);
5361
5362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5363         HWRM_CHECK_RESULT();
5364         HWRM_UNLOCK();
5365
5366         return 0;
5367 }
5368
5369 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5370                                  enum bnxt_flow_dir dir,
5371                                  uint16_t cntr,
5372                                  uint16_t num_entries)
5373 {
5374         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5375         struct hwrm_cfa_counter_qstats_input req = {0};
5376         uint16_t flow_ctx_id = 0;
5377         uint16_t flags = 0;
5378         int rc = 0;
5379
5380         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5381                 PMD_DRV_LOG(DEBUG,
5382                             "Not a PF or trusted VF. Command not supported\n");
5383                 return 0;
5384         }
5385
5386         if (dir == BNXT_DIR_RX) {
5387                 flow_ctx_id = bp->rx_fc_in_tbl.ctx_id;
5388                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5389         } else if (dir == BNXT_DIR_TX) {
5390                 flow_ctx_id = bp->tx_fc_in_tbl.ctx_id;
5391                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5392         }
5393
5394         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5395         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5396         req.counter_type = rte_cpu_to_le_16(cntr);
5397         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5398         req.num_entries = rte_cpu_to_le_16(num_entries);
5399         req.flags = rte_cpu_to_le_16(flags);
5400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5401
5402         HWRM_CHECK_RESULT();
5403         HWRM_UNLOCK();
5404
5405         return 0;
5406 }