drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         } else {
 667                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 668         }
 669
 670         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 671                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 672         else
 673                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 674
 675         HWRM_UNLOCK();
 676
 677         return rc;
 678 }
 679
 680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 681 {
 682         int rc;
 683
 684         rc = __bnxt_hwrm_func_qcaps(bp);
 685         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 686                 rc = bnxt_alloc_ctx_mem(bp);
 687                 if (rc)
 688                         return rc;
 689
 690                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 691                 if (!rc)
 692                         bp->flags |= BNXT_FLAG_NEW_RM;
 693         }
 694
 695         return rc;
 696 }
 697
 698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 700 {
 701         int rc = 0;
 702         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 703         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 704
 705         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 706
 707         req.target_id = rte_cpu_to_le_16(0xffff);
 708
 709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 710
 711         HWRM_CHECK_RESULT();
 712
 713         if (rte_le_to_cpu_32(resp->flags) &
 714             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 715                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 716                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 717         }
 718
 719         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 720
 721         HWRM_UNLOCK();
 722
 723         return rc;
 724 }
 725
 726 int bnxt_hwrm_func_reset(struct bnxt *bp)
 727 {
 728         int rc = 0;
 729         struct hwrm_func_reset_input req = {.req_type = 0 };
 730         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 731
 732         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 733
 734         req.enables = rte_cpu_to_le_32(0);
 735
 736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 737
 738         HWRM_CHECK_RESULT();
 739         HWRM_UNLOCK();
 740
 741         return rc;
 742 }
 743
 744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 745 {
 746         int rc;
 747         uint32_t flags = 0;
 748         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 749         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         if (bp->flags & BNXT_FLAG_REGISTERED)
 752                 return 0;
 753
 754         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 755         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 756                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 757
 758         /* PFs and trusted VFs should indicate the support of the
 759          * Master capability on non Stingray platform
 760          */
 761         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 762                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 763
 764         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 765         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 766                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 767         req.ver_maj = RTE_VER_YEAR;
 768         req.ver_min = RTE_VER_MONTH;
 769         req.ver_upd = RTE_VER_MINOR;
 770
 771         if (BNXT_PF(bp)) {
 772                 req.enables |= rte_cpu_to_le_32(
 773                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 774                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 775                        RTE_MIN(sizeof(req.vf_req_fwd),
 776                                sizeof(bp->pf.vf_req_fwd)));
 777
 778                 /*
 779                  * PF can sniff HWRM API issued by VF. This can be set up by
 780                  * linux driver and inherited by the DPDK PF driver. Clear
 781                  * this HWRM sniffer list in FW because DPDK PF driver does
 782                  * not support this.
 783                  */
 784                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 785         }
 786
 787         req.flags = rte_cpu_to_le_32(flags);
 788
 789         req.async_event_fwd[0] |=
 790                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 791                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 792                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 793                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 794                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 795         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 796                 req.async_event_fwd[0] |=
 797                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 798         req.async_event_fwd[1] |=
 799                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 800                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 801
 802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 803
 804         HWRM_CHECK_RESULT();
 805
 806         flags = rte_le_to_cpu_32(resp->flags);
 807         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 808                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 809
 810         HWRM_UNLOCK();
 811
 812         bp->flags |= BNXT_FLAG_REGISTERED;
 813
 814         return rc;
 815 }
 816
 817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 818 {
 819         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 820                 return 0;
 821
 822         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 823 }
 824
 825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 826 {
 827         int rc;
 828         uint32_t flags = 0;
 829         uint32_t enables;
 830         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 831         struct hwrm_func_vf_cfg_input req = {0};
 832
 833         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 834
 835         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 836                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 838                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 839                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 840
 841         if (BNXT_HAS_RING_GRPS(bp)) {
 842                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 843                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 844         }
 845
 846         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 847         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 848                                             AGG_RING_MULTIPLIER);
 849         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 850         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 851                                               bp->tx_nr_rings +
 852                                               BNXT_NUM_ASYNC_CPR(bp));
 853         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 854         if (bp->vf_resv_strategy ==
 855             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 856                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 857                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 859                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 860                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 861                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 862         }
 863
 864         if (test)
 865                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 866                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 867                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 868                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 869                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 871
 872         if (test && BNXT_HAS_RING_GRPS(bp))
 873                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 874
 875         req.flags = rte_cpu_to_le_32(flags);
 876         req.enables |= rte_cpu_to_le_32(enables);
 877
 878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 879
 880         if (test)
 881                 HWRM_CHECK_RESULT_SILENT();
 882         else
 883                 HWRM_CHECK_RESULT();
 884
 885         HWRM_UNLOCK();
 886         return rc;
 887 }
 888
 889 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 890 {
 891         int rc;
 892         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 893         struct hwrm_func_resource_qcaps_input req = {0};
 894
 895         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 896         req.fid = rte_cpu_to_le_16(0xffff);
 897
 898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 899
 900         HWRM_CHECK_RESULT();
 901
 902         if (BNXT_VF(bp)) {
 903                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 904                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 905                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 906                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 907                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 908                 /* func_resource_qcaps does not return max_rx_em_flows.
 909                  * So use the value provided by func_qcaps.
 910                  */
 911                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 912                 if (!BNXT_CHIP_THOR(bp))
 913                         bp->max_l2_ctx += bp->max_rx_em_flows;
 914                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 915                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 916         }
 917         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 918         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 919         if (bp->vf_resv_strategy >
 920             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 921                 bp->vf_resv_strategy =
 922                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 923
 924         HWRM_UNLOCK();
 925         return rc;
 926 }
 927
 928 int bnxt_hwrm_ver_get(struct bnxt *bp)
 929 {
 930         int rc = 0;
 931         struct hwrm_ver_get_input req = {.req_type = 0 };
 932         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 933         uint32_t fw_version;
 934         uint16_t max_resp_len;
 935         char type[RTE_MEMZONE_NAMESIZE];
 936         uint32_t dev_caps_cfg;
 937
 938         bp->max_req_len = HWRM_MAX_REQ_LEN;
 939         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 940
 941         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 942         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 943         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 944
 945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 946
 947         if (bp->flags & BNXT_FLAG_FW_RESET)
 948                 HWRM_CHECK_RESULT_SILENT();
 949         else
 950                 HWRM_CHECK_RESULT();
 951
 952         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 953                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 954                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 955                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 956         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 957                      (resp->hwrm_fw_min_8b << 16) |
 958                      (resp->hwrm_fw_bld_8b << 8) |
 959                      resp->hwrm_fw_rsvd_8b;
 960         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 961                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 962
 963         fw_version = resp->hwrm_intf_maj_8b << 16;
 964         fw_version |= resp->hwrm_intf_min_8b << 8;
 965         fw_version |= resp->hwrm_intf_upd_8b;
 966         bp->hwrm_spec_code = fw_version;
 967
 968         /* def_req_timeout value is in milliseconds */
 969         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 970         /* convert timeout to usec */
 971         bp->hwrm_cmd_timeout *= 1000;
 972         if (!bp->hwrm_cmd_timeout)
 973                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 974
 975         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 976                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 977                 rc = -EINVAL;
 978                 goto error;
 979         }
 980
 981         if (bp->max_req_len > resp->max_req_win_len) {
 982                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 983                 rc = -EINVAL;
 984         }
 985         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 986         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 987         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 988                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 989
 990         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 991         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 992
 993         if (bp->max_resp_len != max_resp_len) {
 994                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 995                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 996                         bp->pdev->addr.devid, bp->pdev->addr.function);
 997
 998                 rte_free(bp->hwrm_cmd_resp_addr);
 999
1000                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1001                 if (bp->hwrm_cmd_resp_addr == NULL) {
1002                         rc = -ENOMEM;
1003                         goto error;
1004                 }
1005                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1006                 bp->hwrm_cmd_resp_dma_addr =
1007                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1008                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1009                         PMD_DRV_LOG(ERR,
1010                         "Unable to map response buffer to physical memory.\n");
1011                         rc = -ENOMEM;
1012                         goto error;
1013                 }
1014                 bp->max_resp_len = max_resp_len;
1015         }
1016
1017         if ((dev_caps_cfg &
1018                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1019             (dev_caps_cfg &
1020              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1021                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1022                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1023         }
1024
1025         if (((dev_caps_cfg &
1026               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1027              (dev_caps_cfg &
1028               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1029             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1030                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1031                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1032                         bp->pdev->addr.devid, bp->pdev->addr.function);
1033
1034                 rte_free(bp->hwrm_short_cmd_req_addr);
1035
1036                 bp->hwrm_short_cmd_req_addr =
1037                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1038                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1039                         rc = -ENOMEM;
1040                         goto error;
1041                 }
1042                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1043                 bp->hwrm_short_cmd_req_dma_addr =
1044                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1045                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1046                         rte_free(bp->hwrm_short_cmd_req_addr);
1047                         PMD_DRV_LOG(ERR,
1048                                 "Unable to map buffer to physical memory.\n");
1049                         rc = -ENOMEM;
1050                         goto error;
1051                 }
1052         }
1053         if (dev_caps_cfg &
1054             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1055                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1056                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1057         }
1058         if (dev_caps_cfg &
1059             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1060                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1061         if (dev_caps_cfg &
1062             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1063                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1064                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1065         }
1066
1067 error:
1068         HWRM_UNLOCK();
1069         return rc;
1070 }
1071
1072 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1073 {
1074         int rc;
1075         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1076         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1077
1078         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1079                 return 0;
1080
1081         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1082         req.flags = flags;
1083
1084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1085
1086         HWRM_CHECK_RESULT();
1087         HWRM_UNLOCK();
1088
1089         return rc;
1090 }
1091
1092 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1093 {
1094         int rc = 0;
1095         struct hwrm_port_phy_cfg_input req = {0};
1096         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1097         uint32_t enables = 0;
1098
1099         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1100
1101         if (conf->link_up) {
1102                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1103                 if (bp->link_info.auto_mode && conf->link_speed) {
1104                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1105                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1106                 }
1107
1108                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1109                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1110                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1111                 /*
1112                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1113                  * any auto mode, even "none".
1114                  */
1115                 if (!conf->link_speed) {
1116                         /* No speeds specified. Enable AutoNeg - all speeds */
1117                         req.auto_mode =
1118                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1119                 }
1120                 /* AutoNeg - Advertise speeds specified. */
1121                 if (conf->auto_link_speed_mask &&
1122                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1123                         req.auto_mode =
1124                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1125                         req.auto_link_speed_mask =
1126                                 conf->auto_link_speed_mask;
1127                         enables |=
1128                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1129                 }
1130
1131                 req.auto_duplex = conf->duplex;
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1133                 req.auto_pause = conf->auto_pause;
1134                 req.force_pause = conf->force_pause;
1135                 /* Set force_pause if there is no auto or if there is a force */
1136                 if (req.auto_pause && !req.force_pause)
1137                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1138                 else
1139                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1140
1141                 req.enables = rte_cpu_to_le_32(enables);
1142         } else {
1143                 req.flags =
1144                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1145                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1146         }
1147
1148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1149
1150         HWRM_CHECK_RESULT();
1151         HWRM_UNLOCK();
1152
1153         return rc;
1154 }
1155
1156 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1157                                    struct bnxt_link_info *link_info)
1158 {
1159         int rc = 0;
1160         struct hwrm_port_phy_qcfg_input req = {0};
1161         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1162
1163         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1164
1165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1166
1167         HWRM_CHECK_RESULT();
1168
1169         link_info->phy_link_status = resp->link;
1170         link_info->link_up =
1171                 (link_info->phy_link_status ==
1172                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1173         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1174         link_info->duplex = resp->duplex_cfg;
1175         link_info->pause = resp->pause;
1176         link_info->auto_pause = resp->auto_pause;
1177         link_info->force_pause = resp->force_pause;
1178         link_info->auto_mode = resp->auto_mode;
1179         link_info->phy_type = resp->phy_type;
1180         link_info->media_type = resp->media_type;
1181
1182         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1183         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1184         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1185         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1186         link_info->phy_ver[0] = resp->phy_maj;
1187         link_info->phy_ver[1] = resp->phy_min;
1188         link_info->phy_ver[2] = resp->phy_bld;
1189
1190         HWRM_UNLOCK();
1191
1192         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1193         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1194         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1195         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1196         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1197                     link_info->auto_link_speed_mask);
1198         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1199                     link_info->force_link_speed);
1200
1201         return rc;
1202 }
1203
1204 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1205 {
1206         int rc = 0;
1207         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1208         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1210         int i;
1211
1212 get_rx_info:
1213         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1214
1215         req.flags = rte_cpu_to_le_32(dir);
1216         /* HWRM Version >= 1.9.1 */
1217         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1218                 req.drv_qmap_cap =
1219                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1221
1222         HWRM_CHECK_RESULT();
1223
1224         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1225                 GET_TX_QUEUE_INFO(0);
1226                 GET_TX_QUEUE_INFO(1);
1227                 GET_TX_QUEUE_INFO(2);
1228                 GET_TX_QUEUE_INFO(3);
1229                 GET_TX_QUEUE_INFO(4);
1230                 GET_TX_QUEUE_INFO(5);
1231                 GET_TX_QUEUE_INFO(6);
1232                 GET_TX_QUEUE_INFO(7);
1233         } else  {
1234                 GET_RX_QUEUE_INFO(0);
1235                 GET_RX_QUEUE_INFO(1);
1236                 GET_RX_QUEUE_INFO(2);
1237                 GET_RX_QUEUE_INFO(3);
1238                 GET_RX_QUEUE_INFO(4);
1239                 GET_RX_QUEUE_INFO(5);
1240                 GET_RX_QUEUE_INFO(6);
1241                 GET_RX_QUEUE_INFO(7);
1242         }
1243
1244         HWRM_UNLOCK();
1245
1246         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1247                 goto done;
1248
1249         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1250                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1251         } else {
1252                 int j;
1253
1254                 /* iterate and find the COSq profile to use for Tx */
1255                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1256                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1257                                 if (bp->tx_cos_queue[i].id != 0xff)
1258                                         bp->tx_cosq_id[j++] =
1259                                                 bp->tx_cos_queue[i].id;
1260                         }
1261                 } else {
1262                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1263                                 if (bp->tx_cos_queue[i].profile ==
1264                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1265                                         bp->tx_cosq_id[0] =
1266                                                 bp->tx_cos_queue[i].id;
1267                                         break;
1268                                 }
1269                         }
1270                 }
1271         }
1272
1273         bp->max_tc = resp->max_configurable_queues;
1274         bp->max_lltc = resp->max_configurable_lossless_queues;
1275         if (bp->max_tc > BNXT_MAX_QUEUE)
1276                 bp->max_tc = BNXT_MAX_QUEUE;
1277         bp->max_q = bp->max_tc;
1278
1279         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1280                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1281                 goto get_rx_info;
1282         }
1283
1284 done:
1285         return rc;
1286 }
1287
1288 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1289                          struct bnxt_ring *ring,
1290                          uint32_t ring_type, uint32_t map_index,
1291                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1292                          uint16_t tx_cosq_id)
1293 {
1294         int rc = 0;
1295         uint32_t enables = 0;
1296         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1297         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1298         struct rte_mempool *mb_pool;
1299         uint16_t rx_buf_size;
1300
1301         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1302
1303         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1304         req.fbo = rte_cpu_to_le_32(0);
1305         /* Association of ring index with doorbell index */
1306         req.logical_id = rte_cpu_to_le_16(map_index);
1307         req.length = rte_cpu_to_le_32(ring->ring_size);
1308
1309         switch (ring_type) {
1310         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311                 req.ring_type = ring_type;
1312                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1313                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1314                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1315                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1316                         enables |=
1317                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1318                 break;
1319         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1320                 req.ring_type = ring_type;
1321                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1322                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1323                 if (BNXT_CHIP_THOR(bp)) {
1324                         mb_pool = bp->rx_queues[0]->mb_pool;
1325                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1326                                       RTE_PKTMBUF_HEADROOM;
1327                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1328                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1329                         enables |=
1330                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1331                 }
1332                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1333                         enables |=
1334                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1335                 break;
1336         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1337                 req.ring_type = ring_type;
1338                 if (BNXT_HAS_NQ(bp)) {
1339                         /* Association of cp ring with nq */
1340                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1341                         enables |=
1342                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1343                 }
1344                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1345                 break;
1346         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1347                 req.ring_type = ring_type;
1348                 req.page_size = BNXT_PAGE_SHFT;
1349                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350                 break;
1351         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1352                 req.ring_type = ring_type;
1353                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1354
1355                 mb_pool = bp->rx_queues[0]->mb_pool;
1356                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1357                               RTE_PKTMBUF_HEADROOM;
1358                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1359                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1360
1361                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1362                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1363                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1364                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1365                 break;
1366         default:
1367                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1368                         ring_type);
1369                 HWRM_UNLOCK();
1370                 return -EINVAL;
1371         }
1372         req.enables = rte_cpu_to_le_32(enables);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         if (rc || resp->error_code) {
1377                 if (rc == 0 && resp->error_code)
1378                         rc = rte_le_to_cpu_16(resp->error_code);
1379                 switch (ring_type) {
1380                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1381                         PMD_DRV_LOG(ERR,
1382                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1383                         HWRM_UNLOCK();
1384                         return rc;
1385                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1386                         PMD_DRV_LOG(ERR,
1387                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1388                         HWRM_UNLOCK();
1389                         return rc;
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1391                         PMD_DRV_LOG(ERR,
1392                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1393                                     rc);
1394                         HWRM_UNLOCK();
1395                         return rc;
1396                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1397                         PMD_DRV_LOG(ERR,
1398                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 default:
1407                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1408                         HWRM_UNLOCK();
1409                         return rc;
1410                 }
1411         }
1412
1413         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1414         HWRM_UNLOCK();
1415         return rc;
1416 }
1417
1418 int bnxt_hwrm_ring_free(struct bnxt *bp,
1419                         struct bnxt_ring *ring, uint32_t ring_type)
1420 {
1421         int rc;
1422         struct hwrm_ring_free_input req = {.req_type = 0 };
1423         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1424
1425         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1426
1427         req.ring_type = ring_type;
1428         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1429
1430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1431
1432         if (rc || resp->error_code) {
1433                 if (rc == 0 && resp->error_code)
1434                         rc = rte_le_to_cpu_16(resp->error_code);
1435                 HWRM_UNLOCK();
1436
1437                 switch (ring_type) {
1438                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1439                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1440                                 rc);
1441                         return rc;
1442                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1443                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1444                                 rc);
1445                         return rc;
1446                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1447                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1448                                 rc);
1449                         return rc;
1450                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1451                         PMD_DRV_LOG(ERR,
1452                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1453                         return rc;
1454                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1455                         PMD_DRV_LOG(ERR,
1456                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1457                         return rc;
1458                 default:
1459                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1460                         return rc;
1461                 }
1462         }
1463         HWRM_UNLOCK();
1464         return 0;
1465 }
1466
1467 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1468 {
1469         int rc = 0;
1470         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1471         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1472
1473         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1474
1475         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1476         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1477         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1478         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483
1484         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1485
1486         HWRM_UNLOCK();
1487
1488         return rc;
1489 }
1490
1491 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1492 {
1493         int rc;
1494         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1495         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1496
1497         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1498
1499         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1500
1501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1502
1503         HWRM_CHECK_RESULT();
1504         HWRM_UNLOCK();
1505
1506         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1507         return rc;
1508 }
1509
1510 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1511 {
1512         int rc = 0;
1513         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1514         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1515
1516         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1517                 return rc;
1518
1519         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1520
1521         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1522
1523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1524
1525         HWRM_CHECK_RESULT();
1526         HWRM_UNLOCK();
1527
1528         return rc;
1529 }
1530
1531 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1532                                 unsigned int idx __rte_unused)
1533 {
1534         int rc;
1535         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1536         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1537
1538         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1539
1540         req.update_period_ms = rte_cpu_to_le_32(0);
1541
1542         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1543
1544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1545
1546         HWRM_CHECK_RESULT();
1547
1548         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1549
1550         HWRM_UNLOCK();
1551
1552         return rc;
1553 }
1554
1555 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1556                                 unsigned int idx __rte_unused)
1557 {
1558         int rc;
1559         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1560         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1561
1562         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1563
1564         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1565
1566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1567
1568         HWRM_CHECK_RESULT();
1569         HWRM_UNLOCK();
1570
1571         return rc;
1572 }
1573
1574 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1575 {
1576         int rc = 0, i, j;
1577         struct hwrm_vnic_alloc_input req = { 0 };
1578         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1579
1580         if (!BNXT_HAS_RING_GRPS(bp))
1581                 goto skip_ring_grps;
1582
1583         /* map ring groups to this vnic */
1584         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1585                 vnic->start_grp_id, vnic->end_grp_id);
1586         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1587                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1588
1589         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1590         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1591         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1592         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1593
1594 skip_ring_grps:
1595         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1596                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1597         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1598
1599         if (vnic->func_default)
1600                 req.flags =
1601                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1603
1604         HWRM_CHECK_RESULT();
1605
1606         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1607         HWRM_UNLOCK();
1608         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1609         return rc;
1610 }
1611
1612 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1613                                         struct bnxt_vnic_info *vnic,
1614                                         struct bnxt_plcmodes_cfg *pmode)
1615 {
1616         int rc = 0;
1617         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1618         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1619
1620         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1621
1622         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1623
1624         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1625
1626         HWRM_CHECK_RESULT();
1627
1628         pmode->flags = rte_le_to_cpu_32(resp->flags);
1629         /* dflt_vnic bit doesn't exist in the _cfg command */
1630         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1631         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1632         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1633         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1634
1635         HWRM_UNLOCK();
1636
1637         return rc;
1638 }
1639
1640 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1641                                        struct bnxt_vnic_info *vnic,
1642                                        struct bnxt_plcmodes_cfg *pmode)
1643 {
1644         int rc = 0;
1645         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1646         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1647
1648         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1649                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1650                 return rc;
1651         }
1652
1653         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1654
1655         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1656         req.flags = rte_cpu_to_le_32(pmode->flags);
1657         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1658         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1659         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1660         req.enables = rte_cpu_to_le_32(
1661             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1662             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1663             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1664         );
1665
1666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667
1668         HWRM_CHECK_RESULT();
1669         HWRM_UNLOCK();
1670
1671         return rc;
1672 }
1673
1674 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1675 {
1676         int rc = 0;
1677         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1678         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1679         struct bnxt_plcmodes_cfg pmodes = { 0 };
1680         uint32_t ctx_enable_flag = 0;
1681         uint32_t enables = 0;
1682
1683         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1684                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1685                 return rc;
1686         }
1687
1688         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1689         if (rc)
1690                 return rc;
1691
1692         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1693
1694         if (BNXT_CHIP_THOR(bp)) {
1695                 struct bnxt_rx_queue *rxq =
1696                         bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1697                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1698                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1699
1700                 req.default_rx_ring_id =
1701                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1702                 req.default_cmpl_ring_id =
1703                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1704                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1705                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1706                 goto config_mru;
1707         }
1708
1709         /* Only RSS support for now TBD: COS & LB */
1710         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1711         if (vnic->lb_rule != 0xffff)
1712                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1713         if (vnic->cos_rule != 0xffff)
1714                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1715         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1716                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1717                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1718         }
1719         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1720                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1721                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1722         }
1723
1724         enables |= ctx_enable_flag;
1725         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1726         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1727         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1728         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1729
1730 config_mru:
1731         req.enables = rte_cpu_to_le_32(enables);
1732         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1733         req.mru = rte_cpu_to_le_16(vnic->mru);
1734         /* Configure default VNIC only once. */
1735         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1736                 req.flags |=
1737                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1738                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1739         }
1740         if (vnic->vlan_strip)
1741                 req.flags |=
1742                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1743         if (vnic->bd_stall)
1744                 req.flags |=
1745                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1746         if (vnic->roce_dual)
1747                 req.flags |= rte_cpu_to_le_32(
1748                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1749         if (vnic->roce_only)
1750                 req.flags |= rte_cpu_to_le_32(
1751                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1752         if (vnic->rss_dflt_cr)
1753                 req.flags |= rte_cpu_to_le_32(
1754                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1755
1756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1757
1758         HWRM_CHECK_RESULT();
1759         HWRM_UNLOCK();
1760
1761         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1762
1763         return rc;
1764 }
1765
1766 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1767                 int16_t fw_vf_id)
1768 {
1769         int rc = 0;
1770         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1771         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1772
1773         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1774                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1775                 return rc;
1776         }
1777         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1778
1779         req.enables =
1780                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1781         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1782         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1783
1784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1785
1786         HWRM_CHECK_RESULT();
1787
1788         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1789         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1790         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1791         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1792         vnic->mru = rte_le_to_cpu_16(resp->mru);
1793         vnic->func_default = rte_le_to_cpu_32(
1794                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1795         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1796                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1797         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1798                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1799         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1800                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1801         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1802                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1803         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1804                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1805
1806         HWRM_UNLOCK();
1807
1808         return rc;
1809 }
1810
1811 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1812                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1813 {
1814         int rc = 0;
1815         uint16_t ctx_id;
1816         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1817         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1818                                                 bp->hwrm_cmd_resp_addr;
1819
1820         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1821
1822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1823         HWRM_CHECK_RESULT();
1824
1825         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1826         if (!BNXT_HAS_RING_GRPS(bp))
1827                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1828         else if (ctx_idx == 0)
1829                 vnic->rss_rule = ctx_id;
1830
1831         HWRM_UNLOCK();
1832
1833         return rc;
1834 }
1835
1836 static
1837 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1838                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1839 {
1840         int rc = 0;
1841         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1842         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1843                                                 bp->hwrm_cmd_resp_addr;
1844
1845         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1846                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1847                 return rc;
1848         }
1849         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1850
1851         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1852
1853         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854
1855         HWRM_CHECK_RESULT();
1856         HWRM_UNLOCK();
1857
1858         return rc;
1859 }
1860
1861 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1862 {
1863         int rc = 0;
1864
1865         if (BNXT_CHIP_THOR(bp)) {
1866                 int j;
1867
1868                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1869                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1870                                                       vnic,
1871                                                       vnic->fw_grp_ids[j]);
1872                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1873                 }
1874                 vnic->num_lb_ctxts = 0;
1875         } else {
1876                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1877                 vnic->rss_rule = INVALID_HW_RING_ID;
1878         }
1879
1880         return rc;
1881 }
1882
1883 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1884 {
1885         int rc = 0;
1886         struct hwrm_vnic_free_input req = {.req_type = 0 };
1887         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1888
1889         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1890                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1891                 return rc;
1892         }
1893
1894         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1895
1896         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1897
1898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899
1900         HWRM_CHECK_RESULT();
1901         HWRM_UNLOCK();
1902
1903         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1904         /* Configure default VNIC again if necessary. */
1905         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1906                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1907
1908         return rc;
1909 }
1910
1911 static int
1912 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1913 {
1914         int i;
1915         int rc = 0;
1916         int nr_ctxs = vnic->num_lb_ctxts;
1917         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1918         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1919
1920         for (i = 0; i < nr_ctxs; i++) {
1921                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1922
1923                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1924                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1925                 req.hash_mode_flags = vnic->hash_mode;
1926
1927                 req.hash_key_tbl_addr =
1928                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1929
1930                 req.ring_grp_tbl_addr =
1931                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1932                                          i * HW_HASH_INDEX_SIZE);
1933                 req.ring_table_pair_index = i;
1934                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1935
1936                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1937                                             BNXT_USE_CHIMP_MB);
1938
1939                 HWRM_CHECK_RESULT();
1940                 HWRM_UNLOCK();
1941         }
1942
1943         return rc;
1944 }
1945
1946 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1947                            struct bnxt_vnic_info *vnic)
1948 {
1949         int rc = 0;
1950         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1951         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1952
1953         if (!vnic->rss_table)
1954                 return 0;
1955
1956         if (BNXT_CHIP_THOR(bp))
1957                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1958
1959         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1960
1961         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1962         req.hash_mode_flags = vnic->hash_mode;
1963
1964         req.ring_grp_tbl_addr =
1965             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1966         req.hash_key_tbl_addr =
1967             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1968         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1969         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1970
1971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972
1973         HWRM_CHECK_RESULT();
1974         HWRM_UNLOCK();
1975
1976         return rc;
1977 }
1978
1979 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1980                         struct bnxt_vnic_info *vnic)
1981 {
1982         int rc = 0;
1983         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1984         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1985         uint16_t size;
1986
1987         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1988                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1989                 return rc;
1990         }
1991
1992         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1993
1994         req.flags = rte_cpu_to_le_32(
1995                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1996
1997         req.enables = rte_cpu_to_le_32(
1998                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1999
2000         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2001         size -= RTE_PKTMBUF_HEADROOM;
2002         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2003
2004         req.jumbo_thresh = rte_cpu_to_le_16(size);
2005         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2006
2007         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2008
2009         HWRM_CHECK_RESULT();
2010         HWRM_UNLOCK();
2011
2012         return rc;
2013 }
2014
2015 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2016                         struct bnxt_vnic_info *vnic, bool enable)
2017 {
2018         int rc = 0;
2019         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2020         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021
2022         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2023                 if (enable)
2024                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2025                 return -ENOTSUP;
2026         }
2027
2028         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2029                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2030                 return 0;
2031         }
2032
2033         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2034
2035         if (enable) {
2036                 req.enables = rte_cpu_to_le_32(
2037                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2038                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2039                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2040                 req.flags = rte_cpu_to_le_32(
2041                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2042                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2043                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2044                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2045                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2046                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2047                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2048                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2049                 req.min_agg_len = rte_cpu_to_le_32(512);
2050         }
2051         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2052
2053         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2054
2055         HWRM_CHECK_RESULT();
2056         HWRM_UNLOCK();
2057
2058         return rc;
2059 }
2060
2061 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2062 {
2063         struct hwrm_func_cfg_input req = {0};
2064         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2065         int rc;
2066
2067         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2068         req.enables = rte_cpu_to_le_32(
2069                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2070         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2071         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2072
2073         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2074
2075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2076         HWRM_CHECK_RESULT();
2077         HWRM_UNLOCK();
2078
2079         bp->pf.vf_info[vf].random_mac = false;
2080
2081         return rc;
2082 }
2083
2084 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2085                                   uint64_t *dropped)
2086 {
2087         int rc = 0;
2088         struct hwrm_func_qstats_input req = {.req_type = 0};
2089         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2090
2091         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2092
2093         req.fid = rte_cpu_to_le_16(fid);
2094
2095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2096
2097         HWRM_CHECK_RESULT();
2098
2099         if (dropped)
2100                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2101
2102         HWRM_UNLOCK();
2103
2104         return rc;
2105 }
2106
2107 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2108                           struct rte_eth_stats *stats)
2109 {
2110         int rc = 0;
2111         struct hwrm_func_qstats_input req = {.req_type = 0};
2112         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2113
2114         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2115
2116         req.fid = rte_cpu_to_le_16(fid);
2117
2118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2119
2120         HWRM_CHECK_RESULT();
2121
2122         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2123         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2124         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2125         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2126         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2127         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2128
2129         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2130         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2131         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2132         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2133         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2134         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2135
2136         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2137         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2138         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2139
2140         HWRM_UNLOCK();
2141
2142         return rc;
2143 }
2144
2145 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2146 {
2147         int rc = 0;
2148         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2149         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2150
2151         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2152
2153         req.fid = rte_cpu_to_le_16(fid);
2154
2155         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2156
2157         HWRM_CHECK_RESULT();
2158         HWRM_UNLOCK();
2159
2160         return rc;
2161 }
2162
2163 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2164 {
2165         unsigned int i;
2166         int rc = 0;
2167
2168         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2169                 struct bnxt_tx_queue *txq;
2170                 struct bnxt_rx_queue *rxq;
2171                 struct bnxt_cp_ring_info *cpr;
2172
2173                 if (i >= bp->rx_cp_nr_rings) {
2174                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2175                         cpr = txq->cp_ring;
2176                 } else {
2177                         rxq = bp->rx_queues[i];
2178                         cpr = rxq->cp_ring;
2179                 }
2180
2181                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2182                 if (rc)
2183                         return rc;
2184         }
2185         return 0;
2186 }
2187
2188 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2189 {
2190         int rc;
2191         unsigned int i;
2192         struct bnxt_cp_ring_info *cpr;
2193
2194         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2195
2196                 if (i >= bp->rx_cp_nr_rings) {
2197                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2198                 } else {
2199                         cpr = bp->rx_queues[i]->cp_ring;
2200                         if (BNXT_HAS_RING_GRPS(bp))
2201                                 bp->grp_info[i].fw_stats_ctx = -1;
2202                 }
2203                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2204                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2205                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2206                         if (rc)
2207                                 return rc;
2208                 }
2209         }
2210         return 0;
2211 }
2212
2213 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2214 {
2215         unsigned int i;
2216         int rc = 0;
2217
2218         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2219                 struct bnxt_tx_queue *txq;
2220                 struct bnxt_rx_queue *rxq;
2221                 struct bnxt_cp_ring_info *cpr;
2222
2223                 if (i >= bp->rx_cp_nr_rings) {
2224                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2225                         cpr = txq->cp_ring;
2226                 } else {
2227                         rxq = bp->rx_queues[i];
2228                         cpr = rxq->cp_ring;
2229                 }
2230
2231                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2232
2233                 if (rc)
2234                         return rc;
2235         }
2236         return rc;
2237 }
2238
2239 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2240 {
2241         uint16_t idx;
2242         uint32_t rc = 0;
2243
2244         if (!BNXT_HAS_RING_GRPS(bp))
2245                 return 0;
2246
2247         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2248
2249                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2250                         continue;
2251
2252                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2253
2254                 if (rc)
2255                         return rc;
2256         }
2257         return rc;
2258 }
2259
2260 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2261 {
2262         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2263
2264         bnxt_hwrm_ring_free(bp, cp_ring,
2265                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2266         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2267         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2268                                      sizeof(*cpr->cp_desc_ring));
2269         cpr->cp_raw_cons = 0;
2270         cpr->valid = 0;
2271 }
2272
2273 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2274 {
2275         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2276
2277         bnxt_hwrm_ring_free(bp, cp_ring,
2278                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2279         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2280         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2281                         sizeof(*cpr->cp_desc_ring));
2282         cpr->cp_raw_cons = 0;
2283         cpr->valid = 0;
2284 }
2285
2286 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2287 {
2288         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2289         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2290         struct bnxt_ring *ring = rxr->rx_ring_struct;
2291         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2292
2293         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2294                 bnxt_hwrm_ring_free(bp, ring,
2295                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2296                 ring->fw_ring_id = INVALID_HW_RING_ID;
2297                 if (BNXT_HAS_RING_GRPS(bp))
2298                         bp->grp_info[queue_index].rx_fw_ring_id =
2299                                                         INVALID_HW_RING_ID;
2300                 memset(rxr->rx_desc_ring, 0,
2301                        rxr->rx_ring_struct->ring_size *
2302                        sizeof(*rxr->rx_desc_ring));
2303                 memset(rxr->rx_buf_ring, 0,
2304                        rxr->rx_ring_struct->ring_size *
2305                        sizeof(*rxr->rx_buf_ring));
2306                 rxr->rx_prod = 0;
2307         }
2308         ring = rxr->ag_ring_struct;
2309         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2310                 bnxt_hwrm_ring_free(bp, ring,
2311                                     BNXT_CHIP_THOR(bp) ?
2312                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2313                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2314                 ring->fw_ring_id = INVALID_HW_RING_ID;
2315                 memset(rxr->ag_buf_ring, 0,
2316                        rxr->ag_ring_struct->ring_size *
2317                        sizeof(*rxr->ag_buf_ring));
2318                 rxr->ag_prod = 0;
2319                 if (BNXT_HAS_RING_GRPS(bp))
2320                         bp->grp_info[queue_index].ag_fw_ring_id =
2321                                                         INVALID_HW_RING_ID;
2322         }
2323         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2324                 bnxt_free_cp_ring(bp, cpr);
2325
2326         if (BNXT_HAS_RING_GRPS(bp))
2327                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2328 }
2329
2330 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2331 {
2332         unsigned int i;
2333
2334         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2335                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2336                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2337                 struct bnxt_ring *ring = txr->tx_ring_struct;
2338                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2339
2340                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2341                         bnxt_hwrm_ring_free(bp, ring,
2342                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2343                         ring->fw_ring_id = INVALID_HW_RING_ID;
2344                         memset(txr->tx_desc_ring, 0,
2345                                         txr->tx_ring_struct->ring_size *
2346                                         sizeof(*txr->tx_desc_ring));
2347                         memset(txr->tx_buf_ring, 0,
2348                                         txr->tx_ring_struct->ring_size *
2349                                         sizeof(*txr->tx_buf_ring));
2350                         txr->tx_prod = 0;
2351                         txr->tx_cons = 0;
2352                 }
2353                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2354                         bnxt_free_cp_ring(bp, cpr);
2355                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2356                 }
2357         }
2358
2359         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2360                 bnxt_free_hwrm_rx_ring(bp, i);
2361
2362         return 0;
2363 }
2364
2365 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2366 {
2367         uint16_t i;
2368         uint32_t rc = 0;
2369
2370         if (!BNXT_HAS_RING_GRPS(bp))
2371                 return 0;
2372
2373         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2374                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2375                 if (rc)
2376                         return rc;
2377         }
2378         return rc;
2379 }
2380
2381 /*
2382  * HWRM utility functions
2383  */
2384
2385 void bnxt_free_hwrm_resources(struct bnxt *bp)
2386 {
2387         /* Release memzone */
2388         rte_free(bp->hwrm_cmd_resp_addr);
2389         rte_free(bp->hwrm_short_cmd_req_addr);
2390         bp->hwrm_cmd_resp_addr = NULL;
2391         bp->hwrm_short_cmd_req_addr = NULL;
2392         bp->hwrm_cmd_resp_dma_addr = 0;
2393         bp->hwrm_short_cmd_req_dma_addr = 0;
2394 }
2395
2396 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2397 {
2398         struct rte_pci_device *pdev = bp->pdev;
2399         char type[RTE_MEMZONE_NAMESIZE];
2400
2401         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2402                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2403         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2404         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2405         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2406         if (bp->hwrm_cmd_resp_addr == NULL)
2407                 return -ENOMEM;
2408         bp->hwrm_cmd_resp_dma_addr =
2409                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2410         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2411                 PMD_DRV_LOG(ERR,
2412                         "unable to map response address to physical memory\n");
2413                 return -ENOMEM;
2414         }
2415         rte_spinlock_init(&bp->hwrm_lock);
2416
2417         return 0;
2418 }
2419
2420 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2421 {
2422         struct bnxt_filter_info *filter;
2423         int rc = 0;
2424
2425         STAILQ_FOREACH(filter, &vnic->filter, next) {
2426                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2427                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2428                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2429                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2430                 else
2431                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2432                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2433                 bnxt_free_filter(bp, filter);
2434         }
2435         return rc;
2436 }
2437
2438 static int
2439 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2440 {
2441         struct bnxt_filter_info *filter;
2442         struct rte_flow *flow;
2443         int rc = 0;
2444
2445         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2446                 flow = STAILQ_FIRST(&vnic->flow_list);
2447                 filter = flow->filter;
2448                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2449                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2450                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2451                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2452                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2453                 else
2454                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2455
2456                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2457                 rte_free(flow);
2458         }
2459         return rc;
2460 }
2461
2462 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2463 {
2464         struct bnxt_filter_info *filter;
2465         int rc = 0;
2466
2467         STAILQ_FOREACH(filter, &vnic->filter, next) {
2468                 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2469                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2470                                                      filter);
2471                 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2472                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2473                                                          filter);
2474                 } else {
2475                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2476                                                      filter);
2477                         if (!rc)
2478                                 filter->dflt = 1;
2479                 }
2480                 if (rc)
2481                         break;
2482         }
2483         return rc;
2484 }
2485
2486 void bnxt_free_tunnel_ports(struct bnxt *bp)
2487 {
2488         if (bp->vxlan_port_cnt)
2489                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2490                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2491         bp->vxlan_port = 0;
2492         if (bp->geneve_port_cnt)
2493                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2494                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2495         bp->geneve_port = 0;
2496 }
2497
2498 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2499 {
2500         int i;
2501
2502         if (bp->vnic_info == NULL)
2503                 return;
2504
2505         /*
2506          * Cleanup VNICs in reverse order, to make sure the L2 filter
2507          * from vnic0 is last to be cleaned up.
2508          */
2509         for (i = bp->max_vnics - 1; i >= 0; i--) {
2510                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2511
2512                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2513                         continue;
2514
2515                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2516
2517                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2518
2519                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2520
2521                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2522
2523                 bnxt_hwrm_vnic_free(bp, vnic);
2524
2525                 rte_free(vnic->fw_grp_ids);
2526         }
2527         /* Ring resources */
2528         bnxt_free_all_hwrm_rings(bp);
2529         bnxt_free_all_hwrm_ring_grps(bp);
2530         bnxt_free_all_hwrm_stat_ctxs(bp);
2531         bnxt_free_tunnel_ports(bp);
2532 }
2533
2534 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2535 {
2536         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2537
2538         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2539                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2540
2541         switch (conf_link_speed) {
2542         case ETH_LINK_SPEED_10M_HD:
2543         case ETH_LINK_SPEED_100M_HD:
2544                 /* FALLTHROUGH */
2545                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2546         }
2547         return hw_link_duplex;
2548 }
2549
2550 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2551 {
2552         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2553 }
2554
2555 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2556 {
2557         uint16_t eth_link_speed = 0;
2558
2559         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2560                 return ETH_LINK_SPEED_AUTONEG;
2561
2562         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2563         case ETH_LINK_SPEED_100M:
2564         case ETH_LINK_SPEED_100M_HD:
2565                 /* FALLTHROUGH */
2566                 eth_link_speed =
2567                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2568                 break;
2569         case ETH_LINK_SPEED_1G:
2570                 eth_link_speed =
2571                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2572                 break;
2573         case ETH_LINK_SPEED_2_5G:
2574                 eth_link_speed =
2575                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2576                 break;
2577         case ETH_LINK_SPEED_10G:
2578                 eth_link_speed =
2579                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2580                 break;
2581         case ETH_LINK_SPEED_20G:
2582                 eth_link_speed =
2583                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2584                 break;
2585         case ETH_LINK_SPEED_25G:
2586                 eth_link_speed =
2587                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2588                 break;
2589         case ETH_LINK_SPEED_40G:
2590                 eth_link_speed =
2591                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2592                 break;
2593         case ETH_LINK_SPEED_50G:
2594                 eth_link_speed =
2595                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2596                 break;
2597         case ETH_LINK_SPEED_100G:
2598                 eth_link_speed =
2599                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2600                 break;
2601         default:
2602                 PMD_DRV_LOG(ERR,
2603                         "Unsupported link speed %d; default to AUTO\n",
2604                         conf_link_speed);
2605                 break;
2606         }
2607         return eth_link_speed;
2608 }
2609
2610 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2611                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2612                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2613                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2614
2615 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2616 {
2617         uint32_t one_speed;
2618
2619         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2620                 return 0;
2621
2622         if (link_speed & ETH_LINK_SPEED_FIXED) {
2623                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2624
2625                 if (one_speed & (one_speed - 1)) {
2626                         PMD_DRV_LOG(ERR,
2627                                 "Invalid advertised speeds (%u) for port %u\n",
2628                                 link_speed, port_id);
2629                         return -EINVAL;
2630                 }
2631                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2632                         PMD_DRV_LOG(ERR,
2633                                 "Unsupported advertised speed (%u) for port %u\n",
2634                                 link_speed, port_id);
2635                         return -EINVAL;
2636                 }
2637         } else {
2638                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2639                         PMD_DRV_LOG(ERR,
2640                                 "Unsupported advertised speeds (%u) for port %u\n",
2641                                 link_speed, port_id);
2642                         return -EINVAL;
2643                 }
2644         }
2645         return 0;
2646 }
2647
2648 static uint16_t
2649 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2650 {
2651         uint16_t ret = 0;
2652
2653         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2654                 if (bp->link_info.support_speeds)
2655                         return bp->link_info.support_speeds;
2656                 link_speed = BNXT_SUPPORTED_SPEEDS;
2657         }
2658
2659         if (link_speed & ETH_LINK_SPEED_100M)
2660                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2661         if (link_speed & ETH_LINK_SPEED_100M_HD)
2662                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2663         if (link_speed & ETH_LINK_SPEED_1G)
2664                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2665         if (link_speed & ETH_LINK_SPEED_2_5G)
2666                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2667         if (link_speed & ETH_LINK_SPEED_10G)
2668                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2669         if (link_speed & ETH_LINK_SPEED_20G)
2670                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2671         if (link_speed & ETH_LINK_SPEED_25G)
2672                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2673         if (link_speed & ETH_LINK_SPEED_40G)
2674                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2675         if (link_speed & ETH_LINK_SPEED_50G)
2676                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2677         if (link_speed & ETH_LINK_SPEED_100G)
2678                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2679         return ret;
2680 }
2681
2682 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2683 {
2684         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2685
2686         switch (hw_link_speed) {
2687         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2688                 eth_link_speed = ETH_SPEED_NUM_100M;
2689                 break;
2690         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2691                 eth_link_speed = ETH_SPEED_NUM_1G;
2692                 break;
2693         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2694                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2695                 break;
2696         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2697                 eth_link_speed = ETH_SPEED_NUM_10G;
2698                 break;
2699         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2700                 eth_link_speed = ETH_SPEED_NUM_20G;
2701                 break;
2702         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2703                 eth_link_speed = ETH_SPEED_NUM_25G;
2704                 break;
2705         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2706                 eth_link_speed = ETH_SPEED_NUM_40G;
2707                 break;
2708         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2709                 eth_link_speed = ETH_SPEED_NUM_50G;
2710                 break;
2711         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2712                 eth_link_speed = ETH_SPEED_NUM_100G;
2713                 break;
2714         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2715         default:
2716                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2717                         hw_link_speed);
2718                 break;
2719         }
2720         return eth_link_speed;
2721 }
2722
2723 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2724 {
2725         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2726
2727         switch (hw_link_duplex) {
2728         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2729         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2730                 /* FALLTHROUGH */
2731                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2732                 break;
2733         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2734                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2735                 break;
2736         default:
2737                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2738                         hw_link_duplex);
2739                 break;
2740         }
2741         return eth_link_duplex;
2742 }
2743
2744 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2745 {
2746         int rc = 0;
2747         struct bnxt_link_info *link_info = &bp->link_info;
2748
2749         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2750         if (rc) {
2751                 PMD_DRV_LOG(ERR,
2752                         "Get link config failed with rc %d\n", rc);
2753                 goto exit;
2754         }
2755         if (link_info->link_speed)
2756                 link->link_speed =
2757                         bnxt_parse_hw_link_speed(link_info->link_speed);
2758         else
2759                 link->link_speed = ETH_SPEED_NUM_NONE;
2760         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2761         link->link_status = link_info->link_up;
2762         link->link_autoneg = link_info->auto_mode ==
2763                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2764                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2765 exit:
2766         return rc;
2767 }
2768
2769 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2770 {
2771         int rc = 0;
2772         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2773         struct bnxt_link_info link_req;
2774         uint16_t speed, autoneg;
2775
2776         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2777                 return 0;
2778
2779         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2780                         bp->eth_dev->data->port_id);
2781         if (rc)
2782                 goto error;
2783
2784         memset(&link_req, 0, sizeof(link_req));
2785         link_req.link_up = link_up;
2786         if (!link_up)
2787                 goto port_phy_cfg;
2788
2789         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2790         if (BNXT_CHIP_THOR(bp) &&
2791             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2792                 /* 40G is not supported as part of media auto detect.
2793                  * The speed should be forced and autoneg disabled
2794                  * to configure 40G speed.
2795                  */
2796                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2797                 autoneg = 0;
2798         }
2799
2800         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2801         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2802         /* Autoneg can be done only when the FW allows.
2803          * When user configures fixed speed of 40G and later changes to
2804          * any other speed, auto_link_speed/force_link_speed is still set
2805          * to 40G until link comes up at new speed.
2806          */
2807         if (autoneg == 1 &&
2808             !(!BNXT_CHIP_THOR(bp) &&
2809               (bp->link_info.auto_link_speed ||
2810                bp->link_info.force_link_speed))) {
2811                 link_req.phy_flags |=
2812                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2813                 link_req.auto_link_speed_mask =
2814                         bnxt_parse_eth_link_speed_mask(bp,
2815                                                        dev_conf->link_speeds);
2816         } else {
2817                 if (bp->link_info.phy_type ==
2818                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2819                     bp->link_info.phy_type ==
2820                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2821                     bp->link_info.media_type ==
2822                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2823                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2824                         return -EINVAL;
2825                 }
2826
2827                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2828                 /* If user wants a particular speed try that first. */
2829                 if (speed)
2830                         link_req.link_speed = speed;
2831                 else if (bp->link_info.force_link_speed)
2832                         link_req.link_speed = bp->link_info.force_link_speed;
2833                 else
2834                         link_req.link_speed = bp->link_info.auto_link_speed;
2835         }
2836         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2837         link_req.auto_pause = bp->link_info.auto_pause;
2838         link_req.force_pause = bp->link_info.force_pause;
2839
2840 port_phy_cfg:
2841         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2842         if (rc) {
2843                 PMD_DRV_LOG(ERR,
2844                         "Set link config failed with rc %d\n", rc);
2845         }
2846
2847 error:
2848         return rc;
2849 }
2850
2851 /* JIRA 22088 */
2852 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2853 {
2854         struct hwrm_func_qcfg_input req = {0};
2855         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2856         uint16_t flags;
2857         int rc = 0;
2858
2859         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2860         req.fid = rte_cpu_to_le_16(0xffff);
2861
2862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2863
2864         HWRM_CHECK_RESULT();
2865
2866         /* Hard Coded.. 0xfff VLAN ID mask */
2867         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2868         flags = rte_le_to_cpu_16(resp->flags);
2869         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2870                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2871
2872         if (BNXT_VF(bp) &&
2873             !BNXT_VF_IS_TRUSTED(bp) &&
2874             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2875                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2876                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2877         } else if (BNXT_VF(bp) &&
2878                    BNXT_VF_IS_TRUSTED(bp) &&
2879                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2880                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2881                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2882         }
2883
2884         if (mtu)
2885                 *mtu = rte_le_to_cpu_16(resp->mtu);
2886
2887         switch (resp->port_partition_type) {
2888         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2889         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2890         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2891                 /* FALLTHROUGH */
2892                 bp->port_partition_type = resp->port_partition_type;
2893                 break;
2894         default:
2895                 bp->port_partition_type = 0;
2896                 break;
2897         }
2898
2899         HWRM_UNLOCK();
2900
2901         return rc;
2902 }
2903
2904 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2905                                    struct hwrm_func_qcaps_output *qcaps)
2906 {
2907         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2908         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2909                sizeof(qcaps->mac_address));
2910         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2911         qcaps->max_rx_rings = fcfg->num_rx_rings;
2912         qcaps->max_tx_rings = fcfg->num_tx_rings;
2913         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2914         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2915         qcaps->max_vfs = 0;
2916         qcaps->first_vf_id = 0;
2917         qcaps->max_vnics = fcfg->num_vnics;
2918         qcaps->max_decap_records = 0;
2919         qcaps->max_encap_records = 0;
2920         qcaps->max_tx_wm_flows = 0;
2921         qcaps->max_tx_em_flows = 0;
2922         qcaps->max_rx_wm_flows = 0;
2923         qcaps->max_rx_em_flows = 0;
2924         qcaps->max_flow_id = 0;
2925         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2926         qcaps->max_sp_tx_rings = 0;
2927         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2928 }
2929
2930 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2931 {
2932         struct hwrm_func_cfg_input req = {0};
2933         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2934         uint32_t enables;
2935         int rc;
2936
2937         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2938                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2939                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2940                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2941                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2942                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2943                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2944                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2945                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2946
2947         if (BNXT_HAS_RING_GRPS(bp)) {
2948                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2949                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2950         } else if (BNXT_HAS_NQ(bp)) {
2951                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2952                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2953         }
2954
2955         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2956         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2957         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2958                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2959                                    BNXT_NUM_VLANS);
2960         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2961         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2962         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2963         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2964         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2965         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2966         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2967         req.fid = rte_cpu_to_le_16(0xffff);
2968         req.enables = rte_cpu_to_le_32(enables);
2969
2970         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2971
2972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2973
2974         HWRM_CHECK_RESULT();
2975         HWRM_UNLOCK();
2976
2977         return rc;
2978 }
2979
2980 static void populate_vf_func_cfg_req(struct bnxt *bp,
2981                                      struct hwrm_func_cfg_input *req,
2982                                      int num_vfs)
2983 {
2984         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2985                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2986                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2987                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2988                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2989                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2990                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2991                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2992                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2993                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2994
2995         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2996                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2997                                     BNXT_NUM_VLANS);
2998         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2999                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3000                                     BNXT_NUM_VLANS);
3001         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3002                                                 (num_vfs + 1));
3003         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3004         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3005                                                (num_vfs + 1));
3006         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3007         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3008         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3009         /* TODO: For now, do not support VMDq/RFS on VFs. */
3010         req->num_vnics = rte_cpu_to_le_16(1);
3011         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3012                                                  (num_vfs + 1));
3013 }
3014
3015 static void add_random_mac_if_needed(struct bnxt *bp,
3016                                      struct hwrm_func_cfg_input *cfg_req,
3017                                      int vf)
3018 {
3019         struct rte_ether_addr mac;
3020
3021         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3022                 return;
3023
3024         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3025                 cfg_req->enables |=
3026                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3027                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3028                 bp->pf.vf_info[vf].random_mac = true;
3029         } else {
3030                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3031                         RTE_ETHER_ADDR_LEN);
3032         }
3033 }
3034
3035 static void reserve_resources_from_vf(struct bnxt *bp,
3036                                       struct hwrm_func_cfg_input *cfg_req,
3037                                       int vf)
3038 {
3039         struct hwrm_func_qcaps_input req = {0};
3040         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3041         int rc;
3042
3043         /* Get the actual allocated values now */
3044         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3045         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3047
3048         if (rc) {
3049                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3050                 copy_func_cfg_to_qcaps(cfg_req, resp);
3051         } else if (resp->error_code) {
3052                 rc = rte_le_to_cpu_16(resp->error_code);
3053                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3054                 copy_func_cfg_to_qcaps(cfg_req, resp);
3055         }
3056
3057         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3058         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3059         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3060         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3061         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3062         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3063         /*
3064          * TODO: While not supporting VMDq with VFs, max_vnics is always
3065          * forced to 1 in this case
3066          */
3067         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3068         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3069
3070         HWRM_UNLOCK();
3071 }
3072
3073 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3074 {
3075         struct hwrm_func_qcfg_input req = {0};
3076         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3077         int rc;
3078
3079         /* Check for zero MAC address */
3080         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3081         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3082         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3083         HWRM_CHECK_RESULT();
3084         rc = rte_le_to_cpu_16(resp->vlan);
3085
3086         HWRM_UNLOCK();
3087
3088         return rc;
3089 }
3090
3091 static int update_pf_resource_max(struct bnxt *bp)
3092 {
3093         struct hwrm_func_qcfg_input req = {0};
3094         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3095         int rc;
3096
3097         /* And copy the allocated numbers into the pf struct */
3098         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3099         req.fid = rte_cpu_to_le_16(0xffff);
3100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3101         HWRM_CHECK_RESULT();
3102
3103         /* Only TX ring value reflects actual allocation? TODO */
3104         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3105         bp->pf.evb_mode = resp->evb_mode;
3106
3107         HWRM_UNLOCK();
3108
3109         return rc;
3110 }
3111
3112 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3113 {
3114         int rc;
3115
3116         if (!BNXT_PF(bp)) {
3117                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3118                 return -EINVAL;
3119         }
3120
3121         rc = bnxt_hwrm_func_qcaps(bp);
3122         if (rc)
3123                 return rc;
3124
3125         bp->pf.func_cfg_flags &=
3126                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3127                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3128         bp->pf.func_cfg_flags |=
3129                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3130         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3131         rc = __bnxt_hwrm_func_qcaps(bp);
3132         return rc;
3133 }
3134
3135 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3136 {
3137         struct hwrm_func_cfg_input req = {0};
3138         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3139         int i;
3140         size_t sz;
3141         int rc = 0;
3142         size_t req_buf_sz;
3143
3144         if (!BNXT_PF(bp)) {
3145                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3146                 return -EINVAL;
3147         }
3148
3149         rc = bnxt_hwrm_func_qcaps(bp);
3150
3151         if (rc)
3152                 return rc;
3153
3154         bp->pf.active_vfs = num_vfs;
3155
3156         /*
3157          * First, configure the PF to only use one TX ring.  This ensures that
3158          * there are enough rings for all VFs.
3159          *
3160          * If we don't do this, when we call func_alloc() later, we will lock
3161          * extra rings to the PF that won't be available during func_cfg() of
3162          * the VFs.
3163          *
3164          * This has been fixed with firmware versions above 20.6.54
3165          */
3166         bp->pf.func_cfg_flags &=
3167                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3168                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3169         bp->pf.func_cfg_flags |=
3170                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3171         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3172         if (rc)
3173                 return rc;
3174
3175         /*
3176          * Now, create and register a buffer to hold forwarded VF requests
3177          */
3178         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3179         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3180                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3181         if (bp->pf.vf_req_buf == NULL) {
3182                 rc = -ENOMEM;
3183                 goto error_free;
3184         }
3185         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3186                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3187         for (i = 0; i < num_vfs; i++)
3188                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3189                                         (i * HWRM_MAX_REQ_LEN);
3190
3191         rc = bnxt_hwrm_func_buf_rgtr(bp);
3192         if (rc)
3193                 goto error_free;
3194
3195         populate_vf_func_cfg_req(bp, &req, num_vfs);
3196
3197         bp->pf.active_vfs = 0;
3198         for (i = 0; i < num_vfs; i++) {
3199                 add_random_mac_if_needed(bp, &req, i);
3200
3201                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3202                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3203                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3204                 rc = bnxt_hwrm_send_message(bp,
3205                                             &req,
3206                                             sizeof(req),
3207                                             BNXT_USE_CHIMP_MB);
3208
3209                 /* Clear enable flag for next pass */
3210                 req.enables &= ~rte_cpu_to_le_32(
3211                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3212
3213                 if (rc || resp->error_code) {
3214                         PMD_DRV_LOG(ERR,
3215                                 "Failed to initizlie VF %d\n", i);
3216                         PMD_DRV_LOG(ERR,
3217                                 "Not all VFs available. (%d, %d)\n",
3218                                 rc, resp->error_code);
3219                         HWRM_UNLOCK();
3220                         break;
3221                 }
3222
3223                 HWRM_UNLOCK();
3224
3225                 reserve_resources_from_vf(bp, &req, i);
3226                 bp->pf.active_vfs++;
3227                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3228         }
3229
3230         /*
3231          * Now configure the PF to use "the rest" of the resources
3232          * We're using STD_TX_RING_MODE here though which will limit the TX
3233          * rings.  This will allow QoS to function properly.  Not setting this
3234          * will cause PF rings to break bandwidth settings.
3235          */
3236         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3237         if (rc)
3238                 goto error_free;
3239
3240         rc = update_pf_resource_max(bp);
3241         if (rc)
3242                 goto error_free;
3243
3244         return rc;
3245
3246 error_free:
3247         bnxt_hwrm_func_buf_unrgtr(bp);
3248         return rc;
3249 }
3250
3251 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3252 {
3253         struct hwrm_func_cfg_input req = {0};
3254         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3255         int rc;
3256
3257         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3258
3259         req.fid = rte_cpu_to_le_16(0xffff);
3260         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3261         req.evb_mode = bp->pf.evb_mode;
3262
3263         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3264         HWRM_CHECK_RESULT();
3265         HWRM_UNLOCK();
3266
3267         return rc;
3268 }
3269
3270 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3271                                 uint8_t tunnel_type)
3272 {
3273         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3274         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3275         int rc = 0;
3276
3277         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3278         req.tunnel_type = tunnel_type;
3279         req.tunnel_dst_port_val = port;
3280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281         HWRM_CHECK_RESULT();
3282
3283         switch (tunnel_type) {
3284         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3285                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3286                 bp->vxlan_port = port;
3287                 break;
3288         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3289                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3290                 bp->geneve_port = port;
3291                 break;
3292         default:
3293                 break;
3294         }
3295
3296         HWRM_UNLOCK();
3297
3298         return rc;
3299 }
3300
3301 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3302                                 uint8_t tunnel_type)
3303 {
3304         struct hwrm_tunnel_dst_port_free_input req = {0};
3305         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3306         int rc = 0;
3307
3308         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3309
3310         req.tunnel_type = tunnel_type;
3311         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313
3314         HWRM_CHECK_RESULT();
3315         HWRM_UNLOCK();
3316
3317         return rc;
3318 }
3319
3320 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3321                                         uint32_t flags)
3322 {
3323         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3324         struct hwrm_func_cfg_input req = {0};
3325         int rc;
3326
3327         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3328
3329         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3330         req.flags = rte_cpu_to_le_32(flags);
3331         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3332
3333         HWRM_CHECK_RESULT();
3334         HWRM_UNLOCK();
3335
3336         return rc;
3337 }
3338
3339 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3340 {
3341         uint32_t *flag = flagp;
3342
3343         vnic->flags = *flag;
3344 }
3345
3346 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3347 {
3348         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3349 }
3350
3351 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3352 {
3353         int rc = 0;
3354         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3355         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3356
3357         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3358
3359         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3360         req.req_buf_page_size = rte_cpu_to_le_16(
3361                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3362         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3363         req.req_buf_page_addr0 =
3364                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3365         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3366                 PMD_DRV_LOG(ERR,
3367                         "unable to map buffer address to physical memory\n");
3368                 return -ENOMEM;
3369         }
3370
3371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372
3373         HWRM_CHECK_RESULT();
3374         HWRM_UNLOCK();
3375
3376         return rc;
3377 }
3378
3379 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3380 {
3381         int rc = 0;
3382         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3383         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3384
3385         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3386                 return 0;
3387
3388         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3389
3390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3391
3392         HWRM_CHECK_RESULT();
3393         HWRM_UNLOCK();
3394
3395         return rc;
3396 }
3397
3398 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3399 {
3400         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3401         struct hwrm_func_cfg_input req = {0};
3402         int rc;
3403
3404         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3405
3406         req.fid = rte_cpu_to_le_16(0xffff);
3407         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3408         req.enables = rte_cpu_to_le_32(
3409                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3410         req.async_event_cr = rte_cpu_to_le_16(
3411                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3412         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3413
3414         HWRM_CHECK_RESULT();
3415         HWRM_UNLOCK();
3416
3417         return rc;
3418 }
3419
3420 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3421 {
3422         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3423         struct hwrm_func_vf_cfg_input req = {0};
3424         int rc;
3425
3426         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3427
3428         req.enables = rte_cpu_to_le_32(
3429                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3430         req.async_event_cr = rte_cpu_to_le_16(
3431                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3433
3434         HWRM_CHECK_RESULT();
3435         HWRM_UNLOCK();
3436
3437         return rc;
3438 }
3439
3440 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3441 {
3442         struct hwrm_func_cfg_input req = {0};
3443         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3444         uint16_t dflt_vlan, fid;
3445         uint32_t func_cfg_flags;
3446         int rc = 0;
3447
3448         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3449
3450         if (is_vf) {
3451                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3452                 fid = bp->pf.vf_info[vf].fid;
3453                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3454         } else {
3455                 fid = rte_cpu_to_le_16(0xffff);
3456                 func_cfg_flags = bp->pf.func_cfg_flags;
3457                 dflt_vlan = bp->vlan;
3458         }
3459
3460         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3461         req.fid = rte_cpu_to_le_16(fid);
3462         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3463         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3464
3465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3466
3467         HWRM_CHECK_RESULT();
3468         HWRM_UNLOCK();
3469
3470         return rc;
3471 }
3472
3473 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3474                         uint16_t max_bw, uint16_t enables)
3475 {
3476         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3477         struct hwrm_func_cfg_input req = {0};
3478         int rc;
3479
3480         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3481
3482         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3483         req.enables |= rte_cpu_to_le_32(enables);
3484         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3485         req.max_bw = rte_cpu_to_le_32(max_bw);
3486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3487
3488         HWRM_CHECK_RESULT();
3489         HWRM_UNLOCK();
3490
3491         return rc;
3492 }
3493
3494 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3495 {
3496         struct hwrm_func_cfg_input req = {0};
3497         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3498         int rc = 0;
3499
3500         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3501
3502         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3503         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3504         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3505         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3506
3507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3508
3509         HWRM_CHECK_RESULT();
3510         HWRM_UNLOCK();
3511
3512         return rc;
3513 }
3514
3515 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3516 {
3517         int rc;
3518
3519         if (BNXT_PF(bp))
3520                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3521         else
3522                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3523
3524         return rc;
3525 }
3526
3527 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3528                               void *encaped, size_t ec_size)
3529 {
3530         int rc = 0;
3531         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3532         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3533
3534         if (ec_size > sizeof(req.encap_request))
3535                 return -1;
3536
3537         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3538
3539         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3540         memcpy(req.encap_request, encaped, ec_size);
3541
3542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3543
3544         HWRM_CHECK_RESULT();
3545         HWRM_UNLOCK();
3546
3547         return rc;
3548 }
3549
3550 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3551                                        struct rte_ether_addr *mac)
3552 {
3553         struct hwrm_func_qcfg_input req = {0};
3554         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3555         int rc;
3556
3557         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3558
3559         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3561
3562         HWRM_CHECK_RESULT();
3563
3564         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3565
3566         HWRM_UNLOCK();
3567
3568         return rc;
3569 }
3570
3571 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3572                             void *encaped, size_t ec_size)
3573 {
3574         int rc = 0;
3575         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3576         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3577
3578         if (ec_size > sizeof(req.encap_request))
3579                 return -1;
3580
3581         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3582
3583         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3584         memcpy(req.encap_request, encaped, ec_size);
3585
3586         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3587
3588         HWRM_CHECK_RESULT();
3589         HWRM_UNLOCK();
3590
3591         return rc;
3592 }
3593
3594 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3595                          struct rte_eth_stats *stats, uint8_t rx)
3596 {
3597         int rc = 0;
3598         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3599         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3600
3601         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3602
3603         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3604
3605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3606
3607         HWRM_CHECK_RESULT();
3608
3609         if (rx) {
3610                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3611                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3612                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3613                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3614                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3615                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3616                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3617                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3618         } else {
3619                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3620                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3621                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3622                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3623                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3624                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3625         }
3626
3627         HWRM_UNLOCK();
3628
3629         return rc;
3630 }
3631
3632 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3633 {
3634         struct hwrm_port_qstats_input req = {0};
3635         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3636         struct bnxt_pf_info *pf = &bp->pf;
3637         int rc;
3638
3639         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3640
3641         req.port_id = rte_cpu_to_le_16(pf->port_id);
3642         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3643         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3644         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3645
3646         HWRM_CHECK_RESULT();
3647         HWRM_UNLOCK();
3648
3649         return rc;
3650 }
3651
3652 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3653 {
3654         struct hwrm_port_clr_stats_input req = {0};
3655         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3656         struct bnxt_pf_info *pf = &bp->pf;
3657         int rc;
3658
3659         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3660         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3661             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3662                 return 0;
3663
3664         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3665
3666         req.port_id = rte_cpu_to_le_16(pf->port_id);
3667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3668
3669         HWRM_CHECK_RESULT();
3670         HWRM_UNLOCK();
3671
3672         return rc;
3673 }
3674
3675 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3676 {
3677         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3678         struct hwrm_port_led_qcaps_input req = {0};
3679         int rc;
3680
3681         if (BNXT_VF(bp))
3682                 return 0;
3683
3684         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3685         req.port_id = bp->pf.port_id;
3686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3687
3688         HWRM_CHECK_RESULT();
3689
3690         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3691                 unsigned int i;
3692
3693                 bp->num_leds = resp->num_leds;
3694                 memcpy(bp->leds, &resp->led0_id,
3695                         sizeof(bp->leds[0]) * bp->num_leds);
3696                 for (i = 0; i < bp->num_leds; i++) {
3697                         struct bnxt_led_info *led = &bp->leds[i];
3698
3699                         uint16_t caps = led->led_state_caps;
3700
3701                         if (!led->led_group_id ||
3702                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3703                                 bp->num_leds = 0;
3704                                 break;
3705                         }
3706                 }
3707         }
3708
3709         HWRM_UNLOCK();
3710
3711         return rc;
3712 }
3713
3714 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3715 {
3716         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3717         struct hwrm_port_led_cfg_input req = {0};
3718         struct bnxt_led_cfg *led_cfg;
3719         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3720         uint16_t duration = 0;
3721         int rc, i;
3722
3723         if (!bp->num_leds || BNXT_VF(bp))
3724                 return -EOPNOTSUPP;
3725
3726         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3727
3728         if (led_on) {
3729                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3730                 duration = rte_cpu_to_le_16(500);
3731         }
3732         req.port_id = bp->pf.port_id;
3733         req.num_leds = bp->num_leds;
3734         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3735         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3736                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3737                 led_cfg->led_id = bp->leds[i].led_id;
3738                 led_cfg->led_state = led_state;
3739                 led_cfg->led_blink_on = duration;
3740                 led_cfg->led_blink_off = duration;
3741                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3742         }
3743
3744         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3745
3746         HWRM_CHECK_RESULT();
3747         HWRM_UNLOCK();
3748
3749         return rc;
3750 }
3751
3752 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3753                                uint32_t *length)
3754 {
3755         int rc;
3756         struct hwrm_nvm_get_dir_info_input req = {0};
3757         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3758
3759         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3760
3761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3762
3763         HWRM_CHECK_RESULT();
3764
3765         *entries = rte_le_to_cpu_32(resp->entries);
3766         *length = rte_le_to_cpu_32(resp->entry_length);
3767
3768         HWRM_UNLOCK();
3769         return rc;
3770 }
3771
3772 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3773 {
3774         int rc;
3775         uint32_t dir_entries;
3776         uint32_t entry_length;
3777         uint8_t *buf;
3778         size_t buflen;
3779         rte_iova_t dma_handle;
3780         struct hwrm_nvm_get_dir_entries_input req = {0};
3781         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3782
3783         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3784         if (rc != 0)
3785                 return rc;
3786
3787         *data++ = dir_entries;
3788         *data++ = entry_length;
3789         len -= 2;
3790         memset(data, 0xff, len);
3791
3792         buflen = dir_entries * entry_length;
3793         buf = rte_malloc("nvm_dir", buflen, 0);
3794         rte_mem_lock_page(buf);
3795         if (buf == NULL)
3796                 return -ENOMEM;
3797         dma_handle = rte_mem_virt2iova(buf);
3798         if (dma_handle == RTE_BAD_IOVA) {
3799                 PMD_DRV_LOG(ERR,
3800                         "unable to map response address to physical memory\n");
3801                 return -ENOMEM;
3802         }
3803         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3804         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3806
3807         if (rc == 0)
3808                 memcpy(data, buf, len > buflen ? buflen : len);
3809
3810         rte_free(buf);
3811         HWRM_CHECK_RESULT();
3812         HWRM_UNLOCK();
3813
3814         return rc;
3815 }
3816
3817 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3818                              uint32_t offset, uint32_t length,
3819                              uint8_t *data)
3820 {
3821         int rc;
3822         uint8_t *buf;
3823         rte_iova_t dma_handle;
3824         struct hwrm_nvm_read_input req = {0};
3825         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3826
3827         buf = rte_malloc("nvm_item", length, 0);
3828         rte_mem_lock_page(buf);
3829         if (!buf)
3830                 return -ENOMEM;
3831
3832         dma_handle = rte_mem_virt2iova(buf);
3833         if (dma_handle == RTE_BAD_IOVA) {
3834                 PMD_DRV_LOG(ERR,
3835                         "unable to map response address to physical memory\n");
3836                 return -ENOMEM;
3837         }
3838         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3839         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3840         req.dir_idx = rte_cpu_to_le_16(index);
3841         req.offset = rte_cpu_to_le_32(offset);
3842         req.len = rte_cpu_to_le_32(length);
3843         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3844         if (rc == 0)
3845                 memcpy(data, buf, length);
3846
3847         rte_free(buf);
3848         HWRM_CHECK_RESULT();
3849         HWRM_UNLOCK();
3850
3851         return rc;
3852 }
3853
3854 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3855 {
3856         int rc;
3857         struct hwrm_nvm_erase_dir_entry_input req = {0};
3858         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3859
3860         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3861         req.dir_idx = rte_cpu_to_le_16(index);
3862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3863         HWRM_CHECK_RESULT();
3864         HWRM_UNLOCK();
3865
3866         return rc;
3867 }
3868
3869
3870 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3871                           uint16_t dir_ordinal, uint16_t dir_ext,
3872                           uint16_t dir_attr, const uint8_t *data,
3873                           size_t data_len)
3874 {
3875         int rc;
3876         struct hwrm_nvm_write_input req = {0};
3877         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3878         rte_iova_t dma_handle;
3879         uint8_t *buf;
3880
3881         buf = rte_malloc("nvm_write", data_len, 0);
3882         rte_mem_lock_page(buf);
3883         if (!buf)
3884                 return -ENOMEM;
3885
3886         dma_handle = rte_mem_virt2iova(buf);
3887         if (dma_handle == RTE_BAD_IOVA) {
3888                 PMD_DRV_LOG(ERR,
3889                         "unable to map response address to physical memory\n");
3890                 return -ENOMEM;
3891         }
3892         memcpy(buf, data, data_len);
3893
3894         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3895
3896         req.dir_type = rte_cpu_to_le_16(dir_type);
3897         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3898         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3899         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3900         req.dir_data_length = rte_cpu_to_le_32(data_len);
3901         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3902
3903         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3904
3905         rte_free(buf);
3906         HWRM_CHECK_RESULT();
3907         HWRM_UNLOCK();
3908
3909         return rc;
3910 }
3911
3912 static void
3913 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3914 {
3915         uint32_t *count = cbdata;
3916
3917         *count = *count + 1;
3918 }
3919
3920 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3921                                      struct bnxt_vnic_info *vnic __rte_unused)
3922 {
3923         return 0;
3924 }
3925
3926 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3927 {
3928         uint32_t count = 0;
3929
3930         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3931             &count, bnxt_vnic_count_hwrm_stub);
3932
3933         return count;
3934 }
3935
3936 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3937                                         uint16_t *vnic_ids)
3938 {
3939         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3940         struct hwrm_func_vf_vnic_ids_query_output *resp =
3941                                                 bp->hwrm_cmd_resp_addr;
3942         int rc;
3943
3944         /* First query all VNIC ids */
3945         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3946
3947         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3948         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3949         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3950
3951         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3952                 HWRM_UNLOCK();
3953                 PMD_DRV_LOG(ERR,
3954                 "unable to map VNIC ID table address to physical memory\n");
3955                 return -ENOMEM;
3956         }
3957         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3958         HWRM_CHECK_RESULT();
3959         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3960
3961         HWRM_UNLOCK();
3962
3963         return rc;
3964 }
3965
3966 /*
3967  * This function queries the VNIC IDs  for a specified VF. It then calls
3968  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3969  * Then it calls the hwrm_cb function to program this new vnic configuration.
3970  */
3971 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3972         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3973         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3974 {
3975         struct bnxt_vnic_info vnic;
3976         int rc = 0;
3977         int i, num_vnic_ids;
3978         uint16_t *vnic_ids;
3979         size_t vnic_id_sz;
3980         size_t sz;
3981
3982         /* First query all VNIC ids */
3983         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3984         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3985                         RTE_CACHE_LINE_SIZE);
3986         if (vnic_ids == NULL)
3987                 return -ENOMEM;
3988
3989         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3990                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3991
3992         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3993
3994         if (num_vnic_ids < 0)
3995                 return num_vnic_ids;
3996
3997         /* Retrieve VNIC, update bd_stall then update */
3998
3999         for (i = 0; i < num_vnic_ids; i++) {
4000                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4001                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4002                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4003                 if (rc)
4004                         break;
4005                 if (vnic.mru <= 4)      /* Indicates unallocated */
4006                         continue;
4007
4008                 vnic_cb(&vnic, cbdata);
4009
4010                 rc = hwrm_cb(bp, &vnic);
4011                 if (rc)
4012                         break;
4013         }
4014
4015         rte_free(vnic_ids);
4016
4017         return rc;
4018 }
4019
4020 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4021                                               bool on)
4022 {
4023         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4024         struct hwrm_func_cfg_input req = {0};
4025         int rc;
4026
4027         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4028
4029         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4030         req.enables |= rte_cpu_to_le_32(
4031                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4032         req.vlan_antispoof_mode = on ?
4033                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4034                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4036
4037         HWRM_CHECK_RESULT();
4038         HWRM_UNLOCK();
4039
4040         return rc;
4041 }
4042
4043 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4044 {
4045         struct bnxt_vnic_info vnic;
4046         uint16_t *vnic_ids;
4047         size_t vnic_id_sz;
4048         int num_vnic_ids, i;
4049         size_t sz;
4050         int rc;
4051
4052         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4053         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4054                         RTE_CACHE_LINE_SIZE);
4055         if (vnic_ids == NULL)
4056                 return -ENOMEM;
4057
4058         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4059                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4060
4061         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4062         if (rc <= 0)
4063                 goto exit;
4064         num_vnic_ids = rc;
4065
4066         /*
4067          * Loop through to find the default VNIC ID.
4068          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4069          * by sending the hwrm_func_qcfg command to the firmware.
4070          */
4071         for (i = 0; i < num_vnic_ids; i++) {
4072                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4073                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4074                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4075                                         bp->pf.first_vf_id + vf);
4076                 if (rc)
4077                         goto exit;
4078                 if (vnic.func_default) {
4079                         rte_free(vnic_ids);
4080                         return vnic.fw_vnic_id;
4081                 }
4082         }
4083         /* Could not find a default VNIC. */
4084         PMD_DRV_LOG(ERR, "No default VNIC\n");
4085 exit:
4086         rte_free(vnic_ids);
4087         return rc;
4088 }
4089
4090 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4091                          uint16_t dst_id,
4092                          struct bnxt_filter_info *filter)
4093 {
4094         int rc = 0;
4095         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4096         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4097         uint32_t enables = 0;
4098
4099         if (filter->fw_em_filter_id != UINT64_MAX)
4100                 bnxt_hwrm_clear_em_filter(bp, filter);
4101
4102         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4103
4104         req.flags = rte_cpu_to_le_32(filter->flags);
4105
4106         enables = filter->enables |
4107               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4108         req.dst_id = rte_cpu_to_le_16(dst_id);
4109
4110         if (filter->ip_addr_type) {
4111                 req.ip_addr_type = filter->ip_addr_type;
4112                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4113         }
4114         if (enables &
4115             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4116                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4117         if (enables &
4118             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4119                 memcpy(req.src_macaddr, filter->src_macaddr,
4120                        RTE_ETHER_ADDR_LEN);
4121         if (enables &
4122             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4123                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4124                        RTE_ETHER_ADDR_LEN);
4125         if (enables &
4126             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4127                 req.ovlan_vid = filter->l2_ovlan;
4128         if (enables &
4129             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4130                 req.ivlan_vid = filter->l2_ivlan;
4131         if (enables &
4132             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4133                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4134         if (enables &
4135             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4136                 req.ip_protocol = filter->ip_protocol;
4137         if (enables &
4138             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4139                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4140         if (enables &
4141             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4142                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4143         if (enables &
4144             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4145                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4146         if (enables &
4147             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4148                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4149         if (enables &
4150             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4151                 req.mirror_vnic_id = filter->mirror_vnic_id;
4152
4153         req.enables = rte_cpu_to_le_32(enables);
4154
4155         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4156
4157         HWRM_CHECK_RESULT();
4158
4159         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4160         HWRM_UNLOCK();
4161
4162         return rc;
4163 }
4164
4165 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4166 {
4167         int rc = 0;
4168         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4169         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4170
4171         if (filter->fw_em_filter_id == UINT64_MAX)
4172                 return 0;
4173
4174         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4175         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4176
4177         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4178
4179         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4180
4181         HWRM_CHECK_RESULT();
4182         HWRM_UNLOCK();
4183
4184         filter->fw_em_filter_id = UINT64_MAX;
4185         filter->fw_l2_filter_id = UINT64_MAX;
4186
4187         return 0;
4188 }
4189
4190 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4191                          uint16_t dst_id,
4192                          struct bnxt_filter_info *filter)
4193 {
4194         int rc = 0;
4195         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4196         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4197                                                 bp->hwrm_cmd_resp_addr;
4198         uint32_t enables = 0;
4199
4200         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4201                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4202
4203         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4204
4205         req.flags = rte_cpu_to_le_32(filter->flags);
4206
4207         enables = filter->enables |
4208               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4209         req.dst_id = rte_cpu_to_le_16(dst_id);
4210
4211         if (filter->ip_addr_type) {
4212                 req.ip_addr_type = filter->ip_addr_type;
4213                 enables |=
4214                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4215         }
4216         if (enables &
4217             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4218                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4219         if (enables &
4220             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4221                 memcpy(req.src_macaddr, filter->src_macaddr,
4222                        RTE_ETHER_ADDR_LEN);
4223         if (enables &
4224             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4225                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4226         if (enables &
4227             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4228                 req.ip_protocol = filter->ip_protocol;
4229         if (enables &
4230             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4231                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4232         if (enables &
4233             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4234                 req.src_ipaddr_mask[0] =
4235                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4236         if (enables &
4237             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4238                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4239         if (enables &
4240             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4241                 req.dst_ipaddr_mask[0] =
4242                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4243         if (enables &
4244             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4245                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4246         if (enables &
4247             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4248                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4249         if (enables &
4250             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4251                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4252         if (enables &
4253             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4254                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4255         if (enables &
4256             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4257                 req.mirror_vnic_id = filter->mirror_vnic_id;
4258
4259         req.enables = rte_cpu_to_le_32(enables);
4260
4261         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4262
4263         HWRM_CHECK_RESULT();
4264
4265         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4266         HWRM_UNLOCK();
4267
4268         return rc;
4269 }
4270
4271 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4272                                 struct bnxt_filter_info *filter)
4273 {
4274         int rc = 0;
4275         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4276         struct hwrm_cfa_ntuple_filter_free_output *resp =
4277                                                 bp->hwrm_cmd_resp_addr;
4278
4279         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4280                 return 0;
4281
4282         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4283
4284         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4285
4286         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4287
4288         HWRM_CHECK_RESULT();
4289         HWRM_UNLOCK();
4290
4291         filter->fw_ntuple_filter_id = UINT64_MAX;
4292
4293         return 0;
4294 }
4295
4296 static int
4297 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4298 {
4299         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4300         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4301         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4302         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4303         uint16_t *ring_tbl = vnic->rss_table;
4304         int nr_ctxs = vnic->num_lb_ctxts;
4305         int max_rings = bp->rx_nr_rings;
4306         int i, j, k, cnt;
4307         int rc = 0;
4308
4309         for (i = 0, k = 0; i < nr_ctxs; i++) {
4310                 struct bnxt_rx_ring_info *rxr;
4311                 struct bnxt_cp_ring_info *cpr;
4312
4313                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4314
4315                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4316                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4317                 req.hash_mode_flags = vnic->hash_mode;
4318
4319                 req.ring_grp_tbl_addr =
4320                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4321                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4322                                      2 * sizeof(*ring_tbl));
4323                 req.hash_key_tbl_addr =
4324                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4325
4326                 req.ring_table_pair_index = i;
4327                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4328
4329                 for (j = 0; j < 64; j++) {
4330                         uint16_t ring_id;
4331
4332                         /* Find next active ring. */
4333                         for (cnt = 0; cnt < max_rings; cnt++) {
4334                                 if (rx_queue_state[k] !=
4335                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4336                                         break;
4337                                 if (++k == max_rings)
4338                                         k = 0;
4339                         }
4340
4341                         /* Return if no rings are active. */
4342                         if (cnt == max_rings)
4343                                 return 0;
4344
4345                         /* Add rx/cp ring pair to RSS table. */
4346                         rxr = rxqs[k]->rx_ring;
4347                         cpr = rxqs[k]->cp_ring;
4348
4349                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4350                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4351                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4352                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4353
4354                         if (++k == max_rings)
4355                                 k = 0;
4356                 }
4357                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4358                                             BNXT_USE_CHIMP_MB);
4359
4360                 HWRM_CHECK_RESULT();
4361                 HWRM_UNLOCK();
4362         }
4363
4364         return rc;
4365 }
4366
4367 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4368 {
4369         unsigned int rss_idx, fw_idx, i;
4370
4371         if (!(vnic->rss_table && vnic->hash_type))
4372                 return 0;
4373
4374         if (BNXT_CHIP_THOR(bp))
4375                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4376
4377         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4378                 return 0;
4379
4380         if (vnic->rss_table && vnic->hash_type) {
4381                 /*
4382                  * Fill the RSS hash & redirection table with
4383                  * ring group ids for all VNICs
4384                  */
4385                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4386                         rss_idx++, fw_idx++) {
4387                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4388                                 fw_idx %= bp->rx_cp_nr_rings;
4389                                 if (vnic->fw_grp_ids[fw_idx] !=
4390                                     INVALID_HW_RING_ID)
4391                                         break;
4392                                 fw_idx++;
4393                         }
4394                         if (i == bp->rx_cp_nr_rings)
4395                                 return 0;
4396                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4397                 }
4398                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4399         }
4400
4401         return 0;
4402 }
4403
4404 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4405         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4406 {
4407         uint16_t flags;
4408
4409         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4410
4411         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4412         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4413
4414         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4415         req->num_cmpl_dma_aggr_during_int =
4416                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4417
4418         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4419
4420         /* min timer set to 1/2 of interrupt timer */
4421         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4422
4423         /* buf timer set to 1/4 of interrupt timer */
4424         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4425
4426         req->cmpl_aggr_dma_tmr_during_int =
4427                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4428
4429         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4430                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4431         req->flags = rte_cpu_to_le_16(flags);
4432 }
4433
4434 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4435                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4436 {
4437         struct hwrm_ring_aggint_qcaps_input req = {0};
4438         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4439         uint32_t enables;
4440         uint16_t flags;
4441         int rc;
4442
4443         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4445         HWRM_CHECK_RESULT();
4446
4447         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4448         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4449
4450         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4451                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4452         agg_req->flags = rte_cpu_to_le_16(flags);
4453         enables =
4454          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4455          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4456         agg_req->enables = rte_cpu_to_le_32(enables);
4457
4458         HWRM_UNLOCK();
4459         return rc;
4460 }
4461
4462 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4463                         struct bnxt_coal *coal, uint16_t ring_id)
4464 {
4465         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4466         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4467                                                 bp->hwrm_cmd_resp_addr;
4468         int rc;
4469
4470         /* Set ring coalesce parameters only for 100G NICs */
4471         if (BNXT_CHIP_THOR(bp)) {
4472                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4473                         return -1;
4474         } else if (bnxt_stratus_device(bp)) {
4475                 bnxt_hwrm_set_coal_params(coal, &req);
4476         } else {
4477                 return 0;
4478         }
4479
4480         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4481         req.ring_id = rte_cpu_to_le_16(ring_id);
4482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4483         HWRM_CHECK_RESULT();
4484         HWRM_UNLOCK();
4485         return 0;
4486 }
4487
4488 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4489 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4490 {
4491         struct hwrm_func_backing_store_qcaps_input req = {0};
4492         struct hwrm_func_backing_store_qcaps_output *resp =
4493                 bp->hwrm_cmd_resp_addr;
4494         struct bnxt_ctx_pg_info *ctx_pg;
4495         struct bnxt_ctx_mem_info *ctx;
4496         int total_alloc_len;
4497         int rc, i;
4498
4499         if (!BNXT_CHIP_THOR(bp) ||
4500             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4501             BNXT_VF(bp) ||
4502             bp->ctx)
4503                 return 0;
4504
4505         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4507         HWRM_CHECK_RESULT_SILENT();
4508
4509         total_alloc_len = sizeof(*ctx);
4510         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4511                           RTE_CACHE_LINE_SIZE);
4512         if (!ctx) {
4513                 rc = -ENOMEM;
4514                 goto ctx_err;
4515         }
4516
4517         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4518                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4519                             RTE_CACHE_LINE_SIZE);
4520         if (!ctx_pg) {
4521                 rc = -ENOMEM;
4522                 goto ctx_err;
4523         }
4524         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4525                 ctx->tqm_mem[i] = ctx_pg;
4526
4527         bp->ctx = ctx;
4528         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4529         ctx->qp_min_qp1_entries =
4530                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4531         ctx->qp_max_l2_entries =
4532                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4533         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4534         ctx->srq_max_l2_entries =
4535                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4536         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4537         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4538         ctx->cq_max_l2_entries =
4539                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4540         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4541         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4542         ctx->vnic_max_vnic_entries =
4543                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4544         ctx->vnic_max_ring_table_entries =
4545                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4546         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4547         ctx->stat_max_entries =
4548                 rte_le_to_cpu_32(resp->stat_max_entries);
4549         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4550         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4551         ctx->tqm_min_entries_per_ring =
4552                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4553         ctx->tqm_max_entries_per_ring =
4554                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4555         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4556         if (!ctx->tqm_entries_multiple)
4557                 ctx->tqm_entries_multiple = 1;
4558         ctx->mrav_max_entries =
4559                 rte_le_to_cpu_32(resp->mrav_max_entries);
4560         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4561         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4562         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4563 ctx_err:
4564         HWRM_UNLOCK();
4565         return rc;
4566 }
4567
4568 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4569 {
4570         struct hwrm_func_backing_store_cfg_input req = {0};
4571         struct hwrm_func_backing_store_cfg_output *resp =
4572                 bp->hwrm_cmd_resp_addr;
4573         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4574         struct bnxt_ctx_pg_info *ctx_pg;
4575         uint32_t *num_entries;
4576         uint64_t *pg_dir;
4577         uint8_t *pg_attr;
4578         uint32_t ena;
4579         int i, rc;
4580
4581         if (!ctx)
4582                 return 0;
4583
4584         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4585         req.enables = rte_cpu_to_le_32(enables);
4586
4587         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4588                 ctx_pg = &ctx->qp_mem;
4589                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4590                 req.qp_num_qp1_entries =
4591                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4592                 req.qp_num_l2_entries =
4593                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4594                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4595                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4596                                       &req.qpc_pg_size_qpc_lvl,
4597                                       &req.qpc_page_dir);
4598         }
4599
4600         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4601                 ctx_pg = &ctx->srq_mem;
4602                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4603                 req.srq_num_l2_entries =
4604                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4605                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4606                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4607                                       &req.srq_pg_size_srq_lvl,
4608                                       &req.srq_page_dir);
4609         }
4610
4611         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4612                 ctx_pg = &ctx->cq_mem;
4613                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4614                 req.cq_num_l2_entries =
4615                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4616                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4617                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4618                                       &req.cq_pg_size_cq_lvl,
4619                                       &req.cq_page_dir);
4620         }
4621
4622         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4623                 ctx_pg = &ctx->vnic_mem;
4624                 req.vnic_num_vnic_entries =
4625                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4626                 req.vnic_num_ring_table_entries =
4627                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4628                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4629                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4630                                       &req.vnic_pg_size_vnic_lvl,
4631                                       &req.vnic_page_dir);
4632         }
4633
4634         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4635                 ctx_pg = &ctx->stat_mem;
4636                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4637                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4638                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4639                                       &req.stat_pg_size_stat_lvl,
4640                                       &req.stat_page_dir);
4641         }
4642
4643         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4644         num_entries = &req.tqm_sp_num_entries;
4645         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4646         pg_dir = &req.tqm_sp_page_dir;
4647         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4648         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4649                 if (!(enables & ena))
4650                         continue;
4651
4652                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4653
4654                 ctx_pg = ctx->tqm_mem[i];
4655                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4656                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4657         }
4658
4659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4660         HWRM_CHECK_RESULT();
4661         HWRM_UNLOCK();
4662
4663         return rc;
4664 }
4665
4666 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4667 {
4668         struct hwrm_port_qstats_ext_input req = {0};
4669         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4670         struct bnxt_pf_info *pf = &bp->pf;
4671         int rc;
4672
4673         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4674               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4675                 return 0;
4676
4677         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4678
4679         req.port_id = rte_cpu_to_le_16(pf->port_id);
4680         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4681                 req.tx_stat_host_addr =
4682                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4683                 req.tx_stat_size =
4684                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4685         }
4686         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4687                 req.rx_stat_host_addr =
4688                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4689                 req.rx_stat_size =
4690                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4691         }
4692         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4693
4694         if (rc) {
4695                 bp->fw_rx_port_stats_ext_size = 0;
4696                 bp->fw_tx_port_stats_ext_size = 0;
4697         } else {
4698                 bp->fw_rx_port_stats_ext_size =
4699                         rte_le_to_cpu_16(resp->rx_stat_size);
4700                 bp->fw_tx_port_stats_ext_size =
4701                         rte_le_to_cpu_16(resp->tx_stat_size);
4702         }
4703
4704         HWRM_CHECK_RESULT();
4705         HWRM_UNLOCK();
4706
4707         return rc;
4708 }
4709
4710 int
4711 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4712 {
4713         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4714         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4715                 bp->hwrm_cmd_resp_addr;
4716         int rc = 0;
4717
4718         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4719         req.tunnel_type = type;
4720         req.dest_fid = bp->fw_fid;
4721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4722         HWRM_CHECK_RESULT();
4723
4724         HWRM_UNLOCK();
4725
4726         return rc;
4727 }
4728
4729 int
4730 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4731 {
4732         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4733         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4734                 bp->hwrm_cmd_resp_addr;
4735         int rc = 0;
4736
4737         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4738         req.tunnel_type = type;
4739         req.dest_fid = bp->fw_fid;
4740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4741         HWRM_CHECK_RESULT();
4742
4743         HWRM_UNLOCK();
4744
4745         return rc;
4746 }
4747
4748 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4749 {
4750         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4751         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4752                 bp->hwrm_cmd_resp_addr;
4753         int rc = 0;
4754
4755         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4756         req.src_fid = bp->fw_fid;
4757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4758         HWRM_CHECK_RESULT();
4759
4760         if (type)
4761                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4762
4763         HWRM_UNLOCK();
4764
4765         return rc;
4766 }
4767
4768 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4769                                    uint16_t *dst_fid)
4770 {
4771         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4772         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4773                 bp->hwrm_cmd_resp_addr;
4774         int rc = 0;
4775
4776         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4777         req.src_fid = bp->fw_fid;
4778         req.tunnel_type = tun_type;
4779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4780         HWRM_CHECK_RESULT();
4781
4782         if (dst_fid)
4783                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4784
4785         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4786
4787         HWRM_UNLOCK();
4788
4789         return rc;
4790 }
4791
4792 int bnxt_hwrm_set_mac(struct bnxt *bp)
4793 {
4794         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4795         struct hwrm_func_vf_cfg_input req = {0};
4796         int rc = 0;
4797
4798         if (!BNXT_VF(bp))
4799                 return 0;
4800
4801         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4802
4803         req.enables =
4804                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4805         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4806
4807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4808
4809         HWRM_CHECK_RESULT();
4810
4811         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4812         HWRM_UNLOCK();
4813
4814         return rc;
4815 }
4816
4817 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4818 {
4819         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4820         struct hwrm_func_drv_if_change_input req = {0};
4821         uint32_t flags;
4822         int rc;
4823
4824         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4825                 return 0;
4826
4827         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4828          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4829          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4830          */
4831         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4832                 return 0;
4833
4834         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4835
4836         if (up)
4837                 req.flags =
4838                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4839
4840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4841
4842         HWRM_CHECK_RESULT();
4843         flags = rte_le_to_cpu_32(resp->flags);
4844         HWRM_UNLOCK();
4845
4846         if (!up)
4847                 return 0;
4848
4849         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4850                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4851                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4852         }
4853
4854         return 0;
4855 }
4856
4857 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4858 {
4859         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4860         struct bnxt_error_recovery_info *info = bp->recovery_info;
4861         struct hwrm_error_recovery_qcfg_input req = {0};
4862         uint32_t flags = 0;
4863         unsigned int i;
4864         int rc;
4865
4866         /* Older FW does not have error recovery support */
4867         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4868                 return 0;
4869
4870         if (!info) {
4871                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4872                                    sizeof(*info), 0);
4873                 bp->recovery_info = info;
4874                 if (info == NULL)
4875                         return -ENOMEM;
4876         } else {
4877                 memset(info, 0, sizeof(*info));
4878         }
4879
4880         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4881
4882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4883
4884         HWRM_CHECK_RESULT();
4885
4886         flags = rte_le_to_cpu_32(resp->flags);
4887         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4888                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4889         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4890                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4891
4892         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4893             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4894                 rc = -EINVAL;
4895                 goto err;
4896         }
4897
4898         /* FW returned values are in units of 100msec */
4899         info->driver_polling_freq =
4900                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4901         info->master_func_wait_period =
4902                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4903         info->normal_func_wait_period =
4904                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4905         info->master_func_wait_period_after_reset =
4906                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4907         info->max_bailout_time_after_reset =
4908                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4909         info->status_regs[BNXT_FW_STATUS_REG] =
4910                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4911         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4912                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4913         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4914                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4915         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4916                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4917         info->reg_array_cnt =
4918                 rte_le_to_cpu_32(resp->reg_array_cnt);
4919
4920         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4921                 rc = -EINVAL;
4922                 goto err;
4923         }
4924
4925         for (i = 0; i < info->reg_array_cnt; i++) {
4926                 info->reset_reg[i] =
4927                         rte_le_to_cpu_32(resp->reset_reg[i]);
4928                 info->reset_reg_val[i] =
4929                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4930                 info->delay_after_reset[i] =
4931                         resp->delay_after_reset[i];
4932         }
4933 err:
4934         HWRM_UNLOCK();
4935
4936         /* Map the FW status registers */
4937         if (!rc)
4938                 rc = bnxt_map_fw_health_status_regs(bp);
4939
4940         if (rc) {
4941                 rte_free(bp->recovery_info);
4942                 bp->recovery_info = NULL;
4943         }
4944         return rc;
4945 }
4946
4947 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4948 {
4949         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4950         struct hwrm_fw_reset_input req = {0};
4951         int rc;
4952
4953         if (!BNXT_PF(bp))
4954                 return -EOPNOTSUPP;
4955
4956         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4957
4958         req.embedded_proc_type =
4959                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4960         req.selfrst_status =
4961                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4962         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4963
4964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4965                                     BNXT_USE_KONG(bp));
4966
4967         HWRM_CHECK_RESULT();
4968         HWRM_UNLOCK();
4969
4970         return rc;
4971 }
4972
4973 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4974 {
4975         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4976         struct hwrm_port_ts_query_input req = {0};
4977         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4978         uint32_t flags = 0;
4979         int rc;
4980
4981         if (!ptp)
4982                 return 0;
4983
4984         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4985
4986         switch (path) {
4987         case BNXT_PTP_FLAGS_PATH_TX:
4988                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4989                 break;
4990         case BNXT_PTP_FLAGS_PATH_RX:
4991                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4992                 break;
4993         case BNXT_PTP_FLAGS_CURRENT_TIME:
4994                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4995                 break;
4996         }
4997
4998         req.flags = rte_cpu_to_le_32(flags);
4999         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5000
5001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5002
5003         HWRM_CHECK_RESULT();
5004
5005         if (timestamp) {
5006                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5007                 *timestamp |=
5008                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5009         }
5010         HWRM_UNLOCK();
5011
5012         return rc;
5013 }
5014
5015 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5016 {
5017         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5018                                         bp->hwrm_cmd_resp_addr;
5019         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5020         uint32_t flags = 0;
5021         int rc = 0;
5022
5023         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5024                 return rc;
5025
5026         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5027                 PMD_DRV_LOG(DEBUG,
5028                             "Not a PF or trusted VF. Command not supported\n");
5029                 return 0;
5030         }
5031
5032         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5034
5035         HWRM_CHECK_RESULT();
5036         flags = rte_le_to_cpu_32(resp->flags);
5037         HWRM_UNLOCK();
5038
5039         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5040                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5041                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5042         }
5043
5044         return rc;
5045 }