drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 /* Sync memory write before updating doorbell */
 131                 rte_wmb();
 132
 133                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 134         }
 135
 136         /* Write request msg to hwrm channel */
 137         for (i = 0; i < msg_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(*data, bar);
 140                 data++;
 141         }
 142
 143         /* Zero the rest of the request space */
 144         for (; i < max_req_len; i += 4) {
 145                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 146                 rte_write32(0, bar);
 147         }
 148
 149         /* Ring channel doorbell */
 150         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 151         rte_write32(1, bar);
 152
 153         /* Poll for the valid bit */
 154         for (i = 0; i < timeout; i++) {
 155                 /* Sanity check on the resp->resp_len */
 156                 rte_rmb();
 157                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 158                         /* Last byte of resp contains the valid key */
 159                         valid = (uint8_t *)resp + resp->resp_len - 1;
 160                         if (*valid == HWRM_RESP_VALID_KEY)
 161                                 break;
 162                 }
 163                 rte_delay_us(1);
 164         }
 165
 166         if (i >= timeout) {
 167                 /* Suppress VER_GET timeout messages during reset recovery */
 168                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 169                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 170                         return -ETIMEDOUT;
 171
 172                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 173                             req->req_type);
 174                 return -ETIMEDOUT;
 175         }
 176         return 0;
 177 }
 178
 179 /*
 180  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 181  * spinlock, and does initial processing.
 182  *
 183  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 184  * releases the spinlock only if it returns.  If the regular int return codes
 185  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 186  * directly, rather it should be copied and modified to suit the function.
 187  *
 188  * HWRM_UNLOCK() must be called after all response processing is completed.
 189  */
 190 #define HWRM_PREP(req, type, kong) do { \
 191         rte_spinlock_lock(&bp->hwrm_lock); \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 194         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 195         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 197         req.target_id = rte_cpu_to_le_16(0xffff); \
 198         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc > 0) \
 220                         rc = -EINVAL; \
 221                 return rc; \
 222         } \
 223         if (resp->error_code) { \
 224                 rc = rte_le_to_cpu_16(resp->error_code); \
 225                 if (resp->resp_len >= 16) { \
 226                         struct hwrm_err_output *tmp_hwrm_err_op = \
 227                                                 (void *)resp; \
 228                         PMD_DRV_LOG(ERR, \
 229                                 "error %d:%d:%08x:%04x\n", \
 230                                 rc, tmp_hwrm_err_op->cmd_err, \
 231                                 rte_le_to_cpu_32(\
 232                                         tmp_hwrm_err_op->opaque_0), \
 233                                 rte_le_to_cpu_16(\
 234                                         tmp_hwrm_err_op->opaque_1)); \
 235                 } else { \
 236                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 237                 } \
 238                 rte_spinlock_unlock(&bp->hwrm_lock); \
 239                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 240                         rc = -EACCES; \
 241                 else if (rc > 0) \
 242                         rc = -EINVAL; \
 243                 return rc; \
 244         } \
 245 } while (0)
 246
 247 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 248
 249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 250 {
 251         int rc = 0;
 252         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 253         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 254
 255         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 257         req.mask = 0;
 258
 259         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 260
 261         HWRM_CHECK_RESULT();
 262         HWRM_UNLOCK();
 263
 264         return rc;
 265 }
 266
 267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 268                                  struct bnxt_vnic_info *vnic,
 269                                  uint16_t vlan_count,
 270                                  struct bnxt_vlan_table_entry *vlan_table)
 271 {
 272         int rc = 0;
 273         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 274         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 275         uint32_t mask = 0;
 276
 277         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 278                 return rc;
 279
 280         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 281         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 282
 283         /* FIXME add multicast flag, when multicast adding options is supported
 284          * by ethtool.
 285          */
 286         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 287                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 288         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 289                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 290         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 291                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 292         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 293                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 294         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 296         if (vnic->mc_addr_cnt) {
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 298                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 299                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 300         }
 301         if (vlan_table) {
 302                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 303                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 304                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 305                          rte_mem_virt2iova(vlan_table));
 306                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 307         }
 308         req.mask = rte_cpu_to_le_32(mask);
 309
 310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 311
 312         HWRM_CHECK_RESULT();
 313         HWRM_UNLOCK();
 314
 315         return rc;
 316 }
 317
 318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 319                         uint16_t vlan_count,
 320                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 321 {
 322         int rc = 0;
 323         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 324         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 325                                                 bp->hwrm_cmd_resp_addr;
 326
 327         /*
 328          * Older HWRM versions did not support this command, and the set_rx_mask
 329          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 330          * removed from set_rx_mask call, and this command was added.
 331          *
 332          * This command is also present from 1.7.8.11 and higher,
 333          * as well as 1.7.8.0
 334          */
 335         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 336                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 337                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 338                                         (11)))
 339                                 return 0;
 340                 }
 341         }
 342         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 343         req.fid = rte_cpu_to_le_16(fid);
 344
 345         req.vlan_tag_mask_tbl_addr =
 346                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 347         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 348
 349         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 350
 351         HWRM_CHECK_RESULT();
 352         HWRM_UNLOCK();
 353
 354         return rc;
 355 }
 356
 357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 358                            struct bnxt_filter_info *filter)
 359 {
 360         int rc = 0;
 361         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 362         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 363
 364         if (filter->fw_l2_filter_id == UINT64_MAX)
 365                 return 0;
 366
 367         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 368
 369         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 370
 371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 372
 373         HWRM_CHECK_RESULT();
 374         HWRM_UNLOCK();
 375
 376         filter->fw_l2_filter_id = UINT64_MAX;
 377
 378         return 0;
 379 }
 380
 381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 382                          uint16_t dst_id,
 383                          struct bnxt_filter_info *filter)
 384 {
 385         int rc = 0;
 386         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 387         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 388         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 389         const struct rte_eth_vmdq_rx_conf *conf =
 390                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 391         uint32_t enables = 0;
 392         uint16_t j = dst_id - 1;
 393
 394         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 395         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 396             conf->pool_map[j].pools & (1UL << j)) {
 397                 PMD_DRV_LOG(DEBUG,
 398                         "Add vlan %u to vmdq pool %u\n",
 399                         conf->pool_map[j].vlan_id, j);
 400
 401                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 402                 filter->enables |=
 403                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 404                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 405         }
 406
 407         if (filter->fw_l2_filter_id != UINT64_MAX)
 408                 bnxt_hwrm_clear_l2_filter(bp, filter);
 409
 410         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 411
 412         req.flags = rte_cpu_to_le_32(filter->flags);
 413         req.flags |=
 414         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 415
 416         enables = filter->enables |
 417               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 418         req.dst_id = rte_cpu_to_le_16(dst_id);
 419
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 422                 memcpy(req.l2_addr, filter->l2_addr,
 423                        RTE_ETHER_ADDR_LEN);
 424         if (enables &
 425             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 426                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 427                        RTE_ETHER_ADDR_LEN);
 428         if (enables &
 429             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 430                 req.l2_ovlan = filter->l2_ovlan;
 431         if (enables &
 432             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 433                 req.l2_ivlan = filter->l2_ivlan;
 434         if (enables &
 435             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 436                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 437         if (enables &
 438             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 439                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 440         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 441                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 442         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 443                 req.src_type = filter->src_type;
 444
 445         req.enables = rte_cpu_to_le_32(enables);
 446
 447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 448
 449         HWRM_CHECK_RESULT();
 450
 451         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 452         HWRM_UNLOCK();
 453
 454         return rc;
 455 }
 456
 457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 458 {
 459         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 460         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 461         uint32_t flags = 0;
 462         int rc;
 463
 464         if (!ptp)
 465                 return 0;
 466
 467         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 468
 469         if (ptp->rx_filter)
 470                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 471         else
 472                 flags |=
 473                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 474         if (ptp->tx_tstamp_en)
 475                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 476         else
 477                 flags |=
 478                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 479         req.flags = rte_cpu_to_le_32(flags);
 480         req.enables = rte_cpu_to_le_32
 481                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 482         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485         HWRM_UNLOCK();
 486
 487         return rc;
 488 }
 489
 490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 491 {
 492         int rc = 0;
 493         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 494         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 495         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 496
 497 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 498         if (ptp)
 499                 return 0;
 500
 501         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 502
 503         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 504
 505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 506
 507         HWRM_CHECK_RESULT();
 508
 509         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 510                 return 0;
 511
 512         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 513         if (!ptp)
 514                 return -ENOMEM;
 515
 516         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 517                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 518         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 519                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 520         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 521                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 522         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 523                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 524         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 525                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 526         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 527                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 528         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 529                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 530         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 531                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 532         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 533                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 534
 535         ptp->bp = bp;
 536         bp->ptp_cfg = ptp;
 537
 538         return 0;
 539 }
 540
 541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 542 {
 543         int rc = 0;
 544         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 545         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 546         uint16_t new_max_vfs;
 547         uint32_t flags;
 548         int i;
 549
 550         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 551
 552         req.fid = rte_cpu_to_le_16(0xffff);
 553
 554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 555
 556         HWRM_CHECK_RESULT();
 557
 558         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 559         flags = rte_le_to_cpu_32(resp->flags);
 560         if (BNXT_PF(bp)) {
 561                 bp->pf.port_id = resp->port_id;
 562                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 563                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 564                 new_max_vfs = bp->pdev->max_vfs;
 565                 if (new_max_vfs != bp->pf.max_vfs) {
 566                         if (bp->pf.vf_info)
 567                                 rte_free(bp->pf.vf_info);
 568                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 569                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 570                         bp->pf.max_vfs = new_max_vfs;
 571                         for (i = 0; i < new_max_vfs; i++) {
 572                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 573                                 bp->pf.vf_info[i].vlan_table =
 574                                         rte_zmalloc("VF VLAN table",
 575                                                     getpagesize(),
 576                                                     getpagesize());
 577                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 578                                         PMD_DRV_LOG(ERR,
 579                                         "Fail to alloc VLAN table for VF %d\n",
 580                                         i);
 581                                 else
 582                                         rte_mem_lock_page(
 583                                                 bp->pf.vf_info[i].vlan_table);
 584                                 bp->pf.vf_info[i].vlan_as_table =
 585                                         rte_zmalloc("VF VLAN AS table",
 586                                                     getpagesize(),
 587                                                     getpagesize());
 588                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 589                                         PMD_DRV_LOG(ERR,
 590                                         "Alloc VLAN AS table for VF %d fail\n",
 591                                         i);
 592                                 else
 593                                         rte_mem_lock_page(
 594                                                bp->pf.vf_info[i].vlan_as_table);
 595                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 596                         }
 597                 }
 598         }
 599
 600         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 601         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 602         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 603         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 604         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 605         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 606         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 607         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 608         bp->max_l2_ctx =
 609                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 610         /* TODO: For now, do not support VMDq/RFS on VFs. */
 611         if (BNXT_PF(bp)) {
 612                 if (bp->pf.max_vfs)
 613                         bp->max_vnics = 1;
 614                 else
 615                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 616         } else {
 617                 bp->max_vnics = 1;
 618         }
 619         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 620         if (BNXT_PF(bp)) {
 621                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 622                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 623                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 624                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 625                         HWRM_UNLOCK();
 626                         bnxt_hwrm_ptp_qcfg(bp);
 627                 }
 628         }
 629
 630         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 631                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 632
 633         HWRM_UNLOCK();
 634
 635         return rc;
 636 }
 637
 638 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 639 {
 640         int rc;
 641
 642         rc = __bnxt_hwrm_func_qcaps(bp);
 643         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 644                 rc = bnxt_alloc_ctx_mem(bp);
 645                 if (rc)
 646                         return rc;
 647
 648                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 649                 if (!rc)
 650                         bp->flags |= BNXT_FLAG_NEW_RM;
 651         }
 652
 653         return rc;
 654 }
 655
 656 int bnxt_hwrm_func_reset(struct bnxt *bp)
 657 {
 658         int rc = 0;
 659         struct hwrm_func_reset_input req = {.req_type = 0 };
 660         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 661
 662         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 663
 664         req.enables = rte_cpu_to_le_32(0);
 665
 666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 667
 668         HWRM_CHECK_RESULT();
 669         HWRM_UNLOCK();
 670
 671         return rc;
 672 }
 673
 674 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 675 {
 676         int rc;
 677         uint32_t flags = 0;
 678         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 679         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 680
 681         if (bp->flags & BNXT_FLAG_REGISTERED)
 682                 return 0;
 683
 684         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 685
 686         /* PFs and trusted VFs should indicate the support of the
 687          * Master capability on non Stingray platform
 688          */
 689         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 690                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 691
 692         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 693         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 694                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 695         req.ver_maj = RTE_VER_YEAR;
 696         req.ver_min = RTE_VER_MONTH;
 697         req.ver_upd = RTE_VER_MINOR;
 698
 699         if (BNXT_PF(bp)) {
 700                 req.enables |= rte_cpu_to_le_32(
 701                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 702                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 703                        RTE_MIN(sizeof(req.vf_req_fwd),
 704                                sizeof(bp->pf.vf_req_fwd)));
 705
 706                 /*
 707                  * PF can sniff HWRM API issued by VF. This can be set up by
 708                  * linux driver and inherited by the DPDK PF driver. Clear
 709                  * this HWRM sniffer list in FW because DPDK PF driver does
 710                  * not support this.
 711                  */
 712                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 713         }
 714
 715         req.flags = rte_cpu_to_le_32(flags);
 716
 717         req.async_event_fwd[0] |=
 718                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 719                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 720                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 721                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 722         req.async_event_fwd[1] |=
 723                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 724                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 725
 726         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 727
 728         HWRM_CHECK_RESULT();
 729
 730         flags = rte_le_to_cpu_32(resp->flags);
 731         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 732                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 733
 734         HWRM_UNLOCK();
 735
 736         bp->flags |= BNXT_FLAG_REGISTERED;
 737
 738         return rc;
 739 }
 740
 741 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 742 {
 743         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 744                 return 0;
 745
 746         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 747 }
 748
 749 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 750 {
 751         int rc;
 752         uint32_t flags = 0;
 753         uint32_t enables;
 754         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 755         struct hwrm_func_vf_cfg_input req = {0};
 756
 757         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 758
 759         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 760                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 761                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 762                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 763                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 764
 765         if (BNXT_HAS_RING_GRPS(bp)) {
 766                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 767                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 768         }
 769
 770         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 771         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 772                                             AGG_RING_MULTIPLIER);
 773         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 774                                              bp->tx_nr_rings +
 775                                              BNXT_NUM_ASYNC_CPR(bp));
 776         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 777                                               bp->tx_nr_rings +
 778                                               BNXT_NUM_ASYNC_CPR(bp));
 779         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 780         if (bp->vf_resv_strategy ==
 781             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 782                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 783                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 784                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 785                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 786                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 787                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 788         }
 789
 790         if (test)
 791                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 792                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 793                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 794                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 795                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 796                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 797
 798         if (test && BNXT_HAS_RING_GRPS(bp))
 799                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 800
 801         req.flags = rte_cpu_to_le_32(flags);
 802         req.enables |= rte_cpu_to_le_32(enables);
 803
 804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 805
 806         if (test)
 807                 HWRM_CHECK_RESULT_SILENT();
 808         else
 809                 HWRM_CHECK_RESULT();
 810
 811         HWRM_UNLOCK();
 812         return rc;
 813 }
 814
 815 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 816 {
 817         int rc;
 818         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 819         struct hwrm_func_resource_qcaps_input req = {0};
 820
 821         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 822         req.fid = rte_cpu_to_le_16(0xffff);
 823
 824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 825
 826         HWRM_CHECK_RESULT();
 827
 828         if (BNXT_VF(bp)) {
 829                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 830                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 831                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 832                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 833                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 834                 /* func_resource_qcaps does not return max_rx_em_flows.
 835                  * So use the value provided by func_qcaps.
 836                  */
 837                 bp->max_l2_ctx =
 838                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 839                         bp->max_rx_em_flows;
 840                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 841                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 842         }
 843         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 844         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 845         if (bp->vf_resv_strategy >
 846             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 847                 bp->vf_resv_strategy =
 848                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 849
 850         HWRM_UNLOCK();
 851         return rc;
 852 }
 853
 854 int bnxt_hwrm_ver_get(struct bnxt *bp)
 855 {
 856         int rc = 0;
 857         struct hwrm_ver_get_input req = {.req_type = 0 };
 858         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 859         uint32_t fw_version;
 860         uint16_t max_resp_len;
 861         char type[RTE_MEMZONE_NAMESIZE];
 862         uint32_t dev_caps_cfg;
 863
 864         bp->max_req_len = HWRM_MAX_REQ_LEN;
 865         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 866
 867         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 868         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 869         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 870
 871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 872
 873         if (bp->flags & BNXT_FLAG_FW_RESET)
 874                 HWRM_CHECK_RESULT_SILENT();
 875         else
 876                 HWRM_CHECK_RESULT();
 877
 878         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 879                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 880                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 881                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 882         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 883                      (resp->hwrm_fw_min_8b << 16) |
 884                      (resp->hwrm_fw_bld_8b << 8) |
 885                      resp->hwrm_fw_rsvd_8b;
 886         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 887                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 888
 889         fw_version = resp->hwrm_intf_maj_8b << 16;
 890         fw_version |= resp->hwrm_intf_min_8b << 8;
 891         fw_version |= resp->hwrm_intf_upd_8b;
 892         bp->hwrm_spec_code = fw_version;
 893
 894         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 895                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 896                 rc = -EINVAL;
 897                 goto error;
 898         }
 899
 900         if (bp->max_req_len > resp->max_req_win_len) {
 901                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 902                 rc = -EINVAL;
 903         }
 904         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 905         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 906         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 907                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 908
 909         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 910         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 911
 912         if (bp->max_resp_len != max_resp_len) {
 913                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 914                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 915                         bp->pdev->addr.devid, bp->pdev->addr.function);
 916
 917                 rte_free(bp->hwrm_cmd_resp_addr);
 918
 919                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 920                 if (bp->hwrm_cmd_resp_addr == NULL) {
 921                         rc = -ENOMEM;
 922                         goto error;
 923                 }
 924                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 925                 bp->hwrm_cmd_resp_dma_addr =
 926                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 927                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 928                         PMD_DRV_LOG(ERR,
 929                         "Unable to map response buffer to physical memory.\n");
 930                         rc = -ENOMEM;
 931                         goto error;
 932                 }
 933                 bp->max_resp_len = max_resp_len;
 934         }
 935
 936         if ((dev_caps_cfg &
 937                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 938             (dev_caps_cfg &
 939              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 940                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 941                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 942         }
 943
 944         if (((dev_caps_cfg &
 945               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 946              (dev_caps_cfg &
 947               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 948             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 949                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 950                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 951                         bp->pdev->addr.devid, bp->pdev->addr.function);
 952
 953                 rte_free(bp->hwrm_short_cmd_req_addr);
 954
 955                 bp->hwrm_short_cmd_req_addr =
 956                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 957                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 958                         rc = -ENOMEM;
 959                         goto error;
 960                 }
 961                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 962                 bp->hwrm_short_cmd_req_dma_addr =
 963                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 964                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 965                         rte_free(bp->hwrm_short_cmd_req_addr);
 966                         PMD_DRV_LOG(ERR,
 967                                 "Unable to map buffer to physical memory.\n");
 968                         rc = -ENOMEM;
 969                         goto error;
 970                 }
 971         }
 972         if (dev_caps_cfg &
 973             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 974                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 975                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 976         }
 977         if (dev_caps_cfg &
 978             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 979                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 980
 981 error:
 982         HWRM_UNLOCK();
 983         return rc;
 984 }
 985
 986 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 987 {
 988         int rc;
 989         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 990         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 991
 992         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 993                 return 0;
 994
 995         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 996         req.flags = flags;
 997
 998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 999
1000         HWRM_CHECK_RESULT();
1001         HWRM_UNLOCK();
1002
1003         return rc;
1004 }
1005
1006 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1007 {
1008         int rc = 0;
1009         struct hwrm_port_phy_cfg_input req = {0};
1010         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1011         uint32_t enables = 0;
1012
1013         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1014
1015         if (conf->link_up) {
1016                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1017                 if (bp->link_info.auto_mode && conf->link_speed) {
1018                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1019                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1020                 }
1021
1022                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1023                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1024                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1025                 /*
1026                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1027                  * any auto mode, even "none".
1028                  */
1029                 if (!conf->link_speed) {
1030                         /* No speeds specified. Enable AutoNeg - all speeds */
1031                         req.auto_mode =
1032                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1033                 }
1034                 /* AutoNeg - Advertise speeds specified. */
1035                 if (conf->auto_link_speed_mask &&
1036                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1037                         req.auto_mode =
1038                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1039                         req.auto_link_speed_mask =
1040                                 conf->auto_link_speed_mask;
1041                         enables |=
1042                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1043                 }
1044
1045                 req.auto_duplex = conf->duplex;
1046                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1047                 req.auto_pause = conf->auto_pause;
1048                 req.force_pause = conf->force_pause;
1049                 /* Set force_pause if there is no auto or if there is a force */
1050                 if (req.auto_pause && !req.force_pause)
1051                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1052                 else
1053                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1054
1055                 req.enables = rte_cpu_to_le_32(enables);
1056         } else {
1057                 req.flags =
1058                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1059                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1060         }
1061
1062         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1063
1064         HWRM_CHECK_RESULT();
1065         HWRM_UNLOCK();
1066
1067         return rc;
1068 }
1069
1070 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1071                                    struct bnxt_link_info *link_info)
1072 {
1073         int rc = 0;
1074         struct hwrm_port_phy_qcfg_input req = {0};
1075         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1076
1077         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1078
1079         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1080
1081         HWRM_CHECK_RESULT();
1082
1083         link_info->phy_link_status = resp->link;
1084         link_info->link_up =
1085                 (link_info->phy_link_status ==
1086                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1087         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1088         link_info->duplex = resp->duplex_cfg;
1089         link_info->pause = resp->pause;
1090         link_info->auto_pause = resp->auto_pause;
1091         link_info->force_pause = resp->force_pause;
1092         link_info->auto_mode = resp->auto_mode;
1093         link_info->phy_type = resp->phy_type;
1094         link_info->media_type = resp->media_type;
1095
1096         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1097         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1098         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1099         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1100         link_info->phy_ver[0] = resp->phy_maj;
1101         link_info->phy_ver[1] = resp->phy_min;
1102         link_info->phy_ver[2] = resp->phy_bld;
1103
1104         HWRM_UNLOCK();
1105
1106         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1107         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1108         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1109         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1110         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1111                     link_info->auto_link_speed_mask);
1112         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1113                     link_info->force_link_speed);
1114
1115         return rc;
1116 }
1117
1118 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1119 {
1120         int rc = 0;
1121         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1122         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1123         int i;
1124
1125         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1126
1127         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1128         /* HWRM Version >= 1.9.1 */
1129         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1130                 req.drv_qmap_cap =
1131                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1132         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1133
1134         HWRM_CHECK_RESULT();
1135
1136 #define GET_QUEUE_INFO(x) \
1137         bp->cos_queue[x].id = resp->queue_id##x; \
1138         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1139
1140         GET_QUEUE_INFO(0);
1141         GET_QUEUE_INFO(1);
1142         GET_QUEUE_INFO(2);
1143         GET_QUEUE_INFO(3);
1144         GET_QUEUE_INFO(4);
1145         GET_QUEUE_INFO(5);
1146         GET_QUEUE_INFO(6);
1147         GET_QUEUE_INFO(7);
1148
1149         HWRM_UNLOCK();
1150
1151         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1152                 bp->tx_cosq_id = bp->cos_queue[0].id;
1153         } else {
1154                 /* iterate and find the COSq profile to use for Tx */
1155                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1156                         if (bp->cos_queue[i].profile ==
1157                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1158                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1159                                 break;
1160                         }
1161                 }
1162         }
1163
1164         bp->max_tc = resp->max_configurable_queues;
1165         bp->max_lltc = resp->max_configurable_lossless_queues;
1166         if (bp->max_tc > BNXT_MAX_QUEUE)
1167                 bp->max_tc = BNXT_MAX_QUEUE;
1168         bp->max_q = bp->max_tc;
1169
1170         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1171
1172         return rc;
1173 }
1174
1175 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1176                          struct bnxt_ring *ring,
1177                          uint32_t ring_type, uint32_t map_index,
1178                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1179 {
1180         int rc = 0;
1181         uint32_t enables = 0;
1182         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1183         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1184         struct rte_mempool *mb_pool;
1185         uint16_t rx_buf_size;
1186
1187         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1188
1189         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1190         req.fbo = rte_cpu_to_le_32(0);
1191         /* Association of ring index with doorbell index */
1192         req.logical_id = rte_cpu_to_le_16(map_index);
1193         req.length = rte_cpu_to_le_32(ring->ring_size);
1194
1195         switch (ring_type) {
1196         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1197                 req.ring_type = ring_type;
1198                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1199                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1200                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1201                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1202                         enables |=
1203                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1204                 break;
1205         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1206                 req.ring_type = ring_type;
1207                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1208                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1209                 if (BNXT_CHIP_THOR(bp)) {
1210                         mb_pool = bp->rx_queues[0]->mb_pool;
1211                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1212                                       RTE_PKTMBUF_HEADROOM;
1213                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1214                         enables |=
1215                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1216                 }
1217                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1218                         enables |=
1219                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1220                 break;
1221         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1222                 req.ring_type = ring_type;
1223                 if (BNXT_HAS_NQ(bp)) {
1224                         /* Association of cp ring with nq */
1225                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1226                         enables |=
1227                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1228                 }
1229                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1230                 break;
1231         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1232                 req.ring_type = ring_type;
1233                 req.page_size = BNXT_PAGE_SHFT;
1234                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1235                 break;
1236         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1237                 req.ring_type = ring_type;
1238                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1239
1240                 mb_pool = bp->rx_queues[0]->mb_pool;
1241                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1242                               RTE_PKTMBUF_HEADROOM;
1243                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1244
1245                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1246                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1247                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1248                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1249                 break;
1250         default:
1251                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1252                         ring_type);
1253                 HWRM_UNLOCK();
1254                 return -EINVAL;
1255         }
1256         req.enables = rte_cpu_to_le_32(enables);
1257
1258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1259
1260         if (rc || resp->error_code) {
1261                 if (rc == 0 && resp->error_code)
1262                         rc = rte_le_to_cpu_16(resp->error_code);
1263                 switch (ring_type) {
1264                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1265                         PMD_DRV_LOG(ERR,
1266                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1267                         HWRM_UNLOCK();
1268                         return rc;
1269                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1270                         PMD_DRV_LOG(ERR,
1271                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1272                         HWRM_UNLOCK();
1273                         return rc;
1274                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1275                         PMD_DRV_LOG(ERR,
1276                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1277                                     rc);
1278                         HWRM_UNLOCK();
1279                         return rc;
1280                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1281                         PMD_DRV_LOG(ERR,
1282                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1283                         HWRM_UNLOCK();
1284                         return rc;
1285                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1286                         PMD_DRV_LOG(ERR,
1287                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1288                         HWRM_UNLOCK();
1289                         return rc;
1290                 default:
1291                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1292                         HWRM_UNLOCK();
1293                         return rc;
1294                 }
1295         }
1296
1297         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1298         HWRM_UNLOCK();
1299         return rc;
1300 }
1301
1302 int bnxt_hwrm_ring_free(struct bnxt *bp,
1303                         struct bnxt_ring *ring, uint32_t ring_type)
1304 {
1305         int rc;
1306         struct hwrm_ring_free_input req = {.req_type = 0 };
1307         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1308
1309         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1310
1311         req.ring_type = ring_type;
1312         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1313
1314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1315
1316         if (rc || resp->error_code) {
1317                 if (rc == 0 && resp->error_code)
1318                         rc = rte_le_to_cpu_16(resp->error_code);
1319                 HWRM_UNLOCK();
1320
1321                 switch (ring_type) {
1322                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1323                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1324                                 rc);
1325                         return rc;
1326                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1327                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1328                                 rc);
1329                         return rc;
1330                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1331                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1332                                 rc);
1333                         return rc;
1334                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1335                         PMD_DRV_LOG(ERR,
1336                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1337                         return rc;
1338                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1339                         PMD_DRV_LOG(ERR,
1340                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1341                         return rc;
1342                 default:
1343                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1344                         return rc;
1345                 }
1346         }
1347         HWRM_UNLOCK();
1348         return 0;
1349 }
1350
1351 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1352 {
1353         int rc = 0;
1354         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1355         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1356
1357         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1358
1359         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1360         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1361         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1362         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1363
1364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1365
1366         HWRM_CHECK_RESULT();
1367
1368         bp->grp_info[idx].fw_grp_id =
1369             rte_le_to_cpu_16(resp->ring_group_id);
1370
1371         HWRM_UNLOCK();
1372
1373         return rc;
1374 }
1375
1376 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1377 {
1378         int rc;
1379         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1380         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1381
1382         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1383
1384         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1385
1386         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1387
1388         HWRM_CHECK_RESULT();
1389         HWRM_UNLOCK();
1390
1391         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1392         return rc;
1393 }
1394
1395 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1396 {
1397         int rc = 0;
1398         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1399         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1400
1401         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1402                 return rc;
1403
1404         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1405
1406         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1407
1408         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1409
1410         HWRM_CHECK_RESULT();
1411         HWRM_UNLOCK();
1412
1413         return rc;
1414 }
1415
1416 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1417                                 unsigned int idx __rte_unused)
1418 {
1419         int rc;
1420         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1421         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1422
1423         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1424
1425         req.update_period_ms = rte_cpu_to_le_32(0);
1426
1427         req.stats_dma_addr =
1428             rte_cpu_to_le_64(cpr->hw_stats_map);
1429
1430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1431
1432         HWRM_CHECK_RESULT();
1433
1434         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1435
1436         HWRM_UNLOCK();
1437
1438         return rc;
1439 }
1440
1441 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1442                                 unsigned int idx __rte_unused)
1443 {
1444         int rc;
1445         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1446         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1447
1448         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1449
1450         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1451
1452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1453
1454         HWRM_CHECK_RESULT();
1455         HWRM_UNLOCK();
1456
1457         return rc;
1458 }
1459
1460 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1461 {
1462         int rc = 0, i, j;
1463         struct hwrm_vnic_alloc_input req = { 0 };
1464         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1465
1466         if (!BNXT_HAS_RING_GRPS(bp))
1467                 goto skip_ring_grps;
1468
1469         /* map ring groups to this vnic */
1470         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1471                 vnic->start_grp_id, vnic->end_grp_id);
1472         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1473                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1474
1475         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1476         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1477         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1478         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1479
1480 skip_ring_grps:
1481         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1482                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1483         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1484
1485         if (vnic->func_default)
1486                 req.flags =
1487                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1489
1490         HWRM_CHECK_RESULT();
1491
1492         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1493         HWRM_UNLOCK();
1494         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1495         return rc;
1496 }
1497
1498 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1499                                         struct bnxt_vnic_info *vnic,
1500                                         struct bnxt_plcmodes_cfg *pmode)
1501 {
1502         int rc = 0;
1503         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1504         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1505
1506         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1507
1508         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1509
1510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1511
1512         HWRM_CHECK_RESULT();
1513
1514         pmode->flags = rte_le_to_cpu_32(resp->flags);
1515         /* dflt_vnic bit doesn't exist in the _cfg command */
1516         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1517         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1518         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1519         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1520
1521         HWRM_UNLOCK();
1522
1523         return rc;
1524 }
1525
1526 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1527                                        struct bnxt_vnic_info *vnic,
1528                                        struct bnxt_plcmodes_cfg *pmode)
1529 {
1530         int rc = 0;
1531         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1532         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1533
1534         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1535                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1536                 return rc;
1537         }
1538
1539         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1540
1541         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1542         req.flags = rte_cpu_to_le_32(pmode->flags);
1543         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1544         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1545         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1546         req.enables = rte_cpu_to_le_32(
1547             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1548             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1549             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1550         );
1551
1552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1553
1554         HWRM_CHECK_RESULT();
1555         HWRM_UNLOCK();
1556
1557         return rc;
1558 }
1559
1560 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1561 {
1562         int rc = 0;
1563         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1564         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1565         struct bnxt_plcmodes_cfg pmodes = { 0 };
1566         uint32_t ctx_enable_flag = 0;
1567         uint32_t enables = 0;
1568
1569         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1570                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1571                 return rc;
1572         }
1573
1574         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1575         if (rc)
1576                 return rc;
1577
1578         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1579
1580         if (BNXT_CHIP_THOR(bp)) {
1581                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1582                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1583                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1584
1585                 req.default_rx_ring_id =
1586                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1587                 req.default_cmpl_ring_id =
1588                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1589                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1590                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1591                 goto config_mru;
1592         }
1593
1594         /* Only RSS support for now TBD: COS & LB */
1595         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1596         if (vnic->lb_rule != 0xffff)
1597                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1598         if (vnic->cos_rule != 0xffff)
1599                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1600         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1601                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1602                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1603         }
1604         enables |= ctx_enable_flag;
1605         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1606         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1607         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1608         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1609
1610 config_mru:
1611         req.enables = rte_cpu_to_le_32(enables);
1612         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1613         req.mru = rte_cpu_to_le_16(vnic->mru);
1614         /* Configure default VNIC only once. */
1615         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1616                 req.flags |=
1617                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1618                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1619         }
1620         if (vnic->vlan_strip)
1621                 req.flags |=
1622                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1623         if (vnic->bd_stall)
1624                 req.flags |=
1625                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1626         if (vnic->roce_dual)
1627                 req.flags |= rte_cpu_to_le_32(
1628                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1629         if (vnic->roce_only)
1630                 req.flags |= rte_cpu_to_le_32(
1631                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1632         if (vnic->rss_dflt_cr)
1633                 req.flags |= rte_cpu_to_le_32(
1634                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1635
1636         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1637
1638         HWRM_CHECK_RESULT();
1639         HWRM_UNLOCK();
1640
1641         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1642
1643         return rc;
1644 }
1645
1646 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1647                 int16_t fw_vf_id)
1648 {
1649         int rc = 0;
1650         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1651         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1652
1653         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1654                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1655                 return rc;
1656         }
1657         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1658
1659         req.enables =
1660                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1661         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1662         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1663
1664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1665
1666         HWRM_CHECK_RESULT();
1667
1668         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1669         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1670         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1671         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1672         vnic->mru = rte_le_to_cpu_16(resp->mru);
1673         vnic->func_default = rte_le_to_cpu_32(
1674                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1675         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1676                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1677         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1678                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1679         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1680                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1681         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1682                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1683         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1684                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1685
1686         HWRM_UNLOCK();
1687
1688         return rc;
1689 }
1690
1691 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1692                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1693 {
1694         int rc = 0;
1695         uint16_t ctx_id;
1696         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1697         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1698                                                 bp->hwrm_cmd_resp_addr;
1699
1700         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1701
1702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703         HWRM_CHECK_RESULT();
1704
1705         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1706         if (!BNXT_HAS_RING_GRPS(bp))
1707                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1708         else if (ctx_idx == 0)
1709                 vnic->rss_rule = ctx_id;
1710
1711         HWRM_UNLOCK();
1712
1713         return rc;
1714 }
1715
1716 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1717                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1718 {
1719         int rc = 0;
1720         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1721         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1722                                                 bp->hwrm_cmd_resp_addr;
1723
1724         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1725                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1726                 return rc;
1727         }
1728         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1729
1730         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1731
1732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1733
1734         HWRM_CHECK_RESULT();
1735         HWRM_UNLOCK();
1736
1737         return rc;
1738 }
1739
1740 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1741 {
1742         int rc = 0;
1743         struct hwrm_vnic_free_input req = {.req_type = 0 };
1744         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1745
1746         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1747                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1748                 return rc;
1749         }
1750
1751         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1752
1753         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1754
1755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1756
1757         HWRM_CHECK_RESULT();
1758         HWRM_UNLOCK();
1759
1760         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1761         /* Configure default VNIC again if necessary. */
1762         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1763                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1764
1765         return rc;
1766 }
1767
1768 static int
1769 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1770 {
1771         int i;
1772         int rc = 0;
1773         int nr_ctxs = vnic->num_lb_ctxts;
1774         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1775         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1776
1777         for (i = 0; i < nr_ctxs; i++) {
1778                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1779
1780                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1782                 req.hash_mode_flags = vnic->hash_mode;
1783
1784                 req.hash_key_tbl_addr =
1785                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1786
1787                 req.ring_grp_tbl_addr =
1788                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1789                                          i * HW_HASH_INDEX_SIZE);
1790                 req.ring_table_pair_index = i;
1791                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1792
1793                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1794                                             BNXT_USE_CHIMP_MB);
1795
1796                 HWRM_CHECK_RESULT();
1797                 HWRM_UNLOCK();
1798         }
1799
1800         return rc;
1801 }
1802
1803 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1804                            struct bnxt_vnic_info *vnic)
1805 {
1806         int rc = 0;
1807         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1808         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1809
1810         if (!vnic->rss_table)
1811                 return 0;
1812
1813         if (BNXT_CHIP_THOR(bp))
1814                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1815
1816         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1817
1818         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1819         req.hash_mode_flags = vnic->hash_mode;
1820
1821         req.ring_grp_tbl_addr =
1822             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1823         req.hash_key_tbl_addr =
1824             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1825         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1826         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1827
1828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1829
1830         HWRM_CHECK_RESULT();
1831         HWRM_UNLOCK();
1832
1833         return rc;
1834 }
1835
1836 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1837                         struct bnxt_vnic_info *vnic)
1838 {
1839         int rc = 0;
1840         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1841         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1842         uint16_t size;
1843
1844         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1845                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1846                 return rc;
1847         }
1848
1849         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1850
1851         req.flags = rte_cpu_to_le_32(
1852                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1853
1854         req.enables = rte_cpu_to_le_32(
1855                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1856
1857         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1858         size -= RTE_PKTMBUF_HEADROOM;
1859
1860         req.jumbo_thresh = rte_cpu_to_le_16(size);
1861         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1862
1863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1864
1865         HWRM_CHECK_RESULT();
1866         HWRM_UNLOCK();
1867
1868         return rc;
1869 }
1870
1871 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1872                         struct bnxt_vnic_info *vnic, bool enable)
1873 {
1874         int rc = 0;
1875         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1876         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1877
1878         if (BNXT_CHIP_THOR(bp))
1879                 return 0;
1880
1881         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1882
1883         if (enable) {
1884                 req.enables = rte_cpu_to_le_32(
1885                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1886                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1887                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1888                 req.flags = rte_cpu_to_le_32(
1889                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1890                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1891                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1892                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1893                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1894                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1895                 req.max_agg_segs = rte_cpu_to_le_16(5);
1896                 req.max_aggs =
1897                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1898                 req.min_agg_len = rte_cpu_to_le_32(512);
1899         }
1900         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1901
1902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1903
1904         HWRM_CHECK_RESULT();
1905         HWRM_UNLOCK();
1906
1907         return rc;
1908 }
1909
1910 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1911 {
1912         struct hwrm_func_cfg_input req = {0};
1913         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1914         int rc;
1915
1916         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1917         req.enables = rte_cpu_to_le_32(
1918                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1919         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1920         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1921
1922         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1923
1924         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1925         HWRM_CHECK_RESULT();
1926         HWRM_UNLOCK();
1927
1928         bp->pf.vf_info[vf].random_mac = false;
1929
1930         return rc;
1931 }
1932
1933 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1934                                   uint64_t *dropped)
1935 {
1936         int rc = 0;
1937         struct hwrm_func_qstats_input req = {.req_type = 0};
1938         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1939
1940         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1941
1942         req.fid = rte_cpu_to_le_16(fid);
1943
1944         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1945
1946         HWRM_CHECK_RESULT();
1947
1948         if (dropped)
1949                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1950
1951         HWRM_UNLOCK();
1952
1953         return rc;
1954 }
1955
1956 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1957                           struct rte_eth_stats *stats)
1958 {
1959         int rc = 0;
1960         struct hwrm_func_qstats_input req = {.req_type = 0};
1961         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1962
1963         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1964
1965         req.fid = rte_cpu_to_le_16(fid);
1966
1967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968
1969         HWRM_CHECK_RESULT();
1970
1971         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1972         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1973         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1974         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1975         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1976         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1977
1978         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1979         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1980         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1981         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1982         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1983         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1984
1985         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1986         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1987         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1988
1989         HWRM_UNLOCK();
1990
1991         return rc;
1992 }
1993
1994 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1995 {
1996         int rc = 0;
1997         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1998         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1999
2000         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2001
2002         req.fid = rte_cpu_to_le_16(fid);
2003
2004         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2005
2006         HWRM_CHECK_RESULT();
2007         HWRM_UNLOCK();
2008
2009         return rc;
2010 }
2011
2012 /*
2013  * HWRM utility functions
2014  */
2015
2016 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2017 {
2018         unsigned int i;
2019         int rc = 0;
2020
2021         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2022                 struct bnxt_tx_queue *txq;
2023                 struct bnxt_rx_queue *rxq;
2024                 struct bnxt_cp_ring_info *cpr;
2025
2026                 if (i >= bp->rx_cp_nr_rings) {
2027                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2028                         cpr = txq->cp_ring;
2029                 } else {
2030                         rxq = bp->rx_queues[i];
2031                         cpr = rxq->cp_ring;
2032                 }
2033
2034                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2035                 if (rc)
2036                         return rc;
2037         }
2038         return 0;
2039 }
2040
2041 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2042 {
2043         int rc;
2044         unsigned int i;
2045         struct bnxt_cp_ring_info *cpr;
2046
2047         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2048
2049                 if (i >= bp->rx_cp_nr_rings) {
2050                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2051                 } else {
2052                         cpr = bp->rx_queues[i]->cp_ring;
2053                         if (BNXT_HAS_RING_GRPS(bp))
2054                                 bp->grp_info[i].fw_stats_ctx = -1;
2055                 }
2056                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2057                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2058                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2059                         if (rc)
2060                                 return rc;
2061                 }
2062         }
2063         return 0;
2064 }
2065
2066 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2067 {
2068         unsigned int i;
2069         int rc = 0;
2070
2071         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2072                 struct bnxt_tx_queue *txq;
2073                 struct bnxt_rx_queue *rxq;
2074                 struct bnxt_cp_ring_info *cpr;
2075
2076                 if (i >= bp->rx_cp_nr_rings) {
2077                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2078                         cpr = txq->cp_ring;
2079                 } else {
2080                         rxq = bp->rx_queues[i];
2081                         cpr = rxq->cp_ring;
2082                 }
2083
2084                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2085
2086                 if (rc)
2087                         return rc;
2088         }
2089         return rc;
2090 }
2091
2092 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2093 {
2094         uint16_t idx;
2095         uint32_t rc = 0;
2096
2097         if (!BNXT_HAS_RING_GRPS(bp))
2098                 return 0;
2099
2100         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2101
2102                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2103                         continue;
2104
2105                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2106
2107                 if (rc)
2108                         return rc;
2109         }
2110         return rc;
2111 }
2112
2113 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2114 {
2115         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2116
2117         bnxt_hwrm_ring_free(bp, cp_ring,
2118                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2119         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2120         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2121                                      sizeof(*cpr->cp_desc_ring));
2122         cpr->cp_raw_cons = 0;
2123         cpr->valid = 0;
2124 }
2125
2126 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2127 {
2128         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2129
2130         bnxt_hwrm_ring_free(bp, cp_ring,
2131                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2132         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2133         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2134                         sizeof(*cpr->cp_desc_ring));
2135         cpr->cp_raw_cons = 0;
2136         cpr->valid = 0;
2137 }
2138
2139 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2140 {
2141         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2142         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2143         struct bnxt_ring *ring = rxr->rx_ring_struct;
2144         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2145
2146         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2147                 bnxt_hwrm_ring_free(bp, ring,
2148                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2149                 ring->fw_ring_id = INVALID_HW_RING_ID;
2150                 if (BNXT_HAS_RING_GRPS(bp))
2151                         bp->grp_info[queue_index].rx_fw_ring_id =
2152                                                         INVALID_HW_RING_ID;
2153                 memset(rxr->rx_desc_ring, 0,
2154                        rxr->rx_ring_struct->ring_size *
2155                        sizeof(*rxr->rx_desc_ring));
2156                 memset(rxr->rx_buf_ring, 0,
2157                        rxr->rx_ring_struct->ring_size *
2158                        sizeof(*rxr->rx_buf_ring));
2159                 rxr->rx_prod = 0;
2160         }
2161         ring = rxr->ag_ring_struct;
2162         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2163                 bnxt_hwrm_ring_free(bp, ring,
2164                                     BNXT_CHIP_THOR(bp) ?
2165                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2166                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2167                 ring->fw_ring_id = INVALID_HW_RING_ID;
2168                 memset(rxr->ag_buf_ring, 0,
2169                        rxr->ag_ring_struct->ring_size *
2170                        sizeof(*rxr->ag_buf_ring));
2171                 rxr->ag_prod = 0;
2172                 if (BNXT_HAS_RING_GRPS(bp))
2173                         bp->grp_info[queue_index].ag_fw_ring_id =
2174                                                         INVALID_HW_RING_ID;
2175         }
2176         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2177                 bnxt_free_cp_ring(bp, cpr);
2178                 if (rxq->nq_ring)
2179                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2180         }
2181
2182         if (BNXT_HAS_RING_GRPS(bp))
2183                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2184 }
2185
2186 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2187 {
2188         unsigned int i;
2189
2190         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2191                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2192                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2193                 struct bnxt_ring *ring = txr->tx_ring_struct;
2194                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2195
2196                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2197                         bnxt_hwrm_ring_free(bp, ring,
2198                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2199                         ring->fw_ring_id = INVALID_HW_RING_ID;
2200                         memset(txr->tx_desc_ring, 0,
2201                                         txr->tx_ring_struct->ring_size *
2202                                         sizeof(*txr->tx_desc_ring));
2203                         memset(txr->tx_buf_ring, 0,
2204                                         txr->tx_ring_struct->ring_size *
2205                                         sizeof(*txr->tx_buf_ring));
2206                         txr->tx_prod = 0;
2207                         txr->tx_cons = 0;
2208                 }
2209                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2210                         bnxt_free_cp_ring(bp, cpr);
2211                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2212                         if (txq->nq_ring)
2213                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2214                 }
2215         }
2216
2217         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2218                 bnxt_free_hwrm_rx_ring(bp, i);
2219
2220         return 0;
2221 }
2222
2223 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2224 {
2225         uint16_t i;
2226         uint32_t rc = 0;
2227
2228         if (!BNXT_HAS_RING_GRPS(bp))
2229                 return 0;
2230
2231         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2232                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2233                 if (rc)
2234                         return rc;
2235         }
2236         return rc;
2237 }
2238
2239 void bnxt_free_hwrm_resources(struct bnxt *bp)
2240 {
2241         /* Release memzone */
2242         rte_free(bp->hwrm_cmd_resp_addr);
2243         rte_free(bp->hwrm_short_cmd_req_addr);
2244         bp->hwrm_cmd_resp_addr = NULL;
2245         bp->hwrm_short_cmd_req_addr = NULL;
2246         bp->hwrm_cmd_resp_dma_addr = 0;
2247         bp->hwrm_short_cmd_req_dma_addr = 0;
2248 }
2249
2250 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2251 {
2252         struct rte_pci_device *pdev = bp->pdev;
2253         char type[RTE_MEMZONE_NAMESIZE];
2254
2255         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2256                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2257         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2258         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2259         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2260         if (bp->hwrm_cmd_resp_addr == NULL)
2261                 return -ENOMEM;
2262         bp->hwrm_cmd_resp_dma_addr =
2263                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2264         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2265                 PMD_DRV_LOG(ERR,
2266                         "unable to map response address to physical memory\n");
2267                 return -ENOMEM;
2268         }
2269         rte_spinlock_init(&bp->hwrm_lock);
2270
2271         return 0;
2272 }
2273
2274 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2275 {
2276         struct bnxt_filter_info *filter;
2277         int rc = 0;
2278
2279         STAILQ_FOREACH(filter, &vnic->filter, next) {
2280                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2281                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2282                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2283                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2284                 else
2285                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2286                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2287                 //if (rc)
2288                         //break;
2289         }
2290         return rc;
2291 }
2292
2293 static int
2294 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2295 {
2296         struct bnxt_filter_info *filter;
2297         struct rte_flow *flow;
2298         int rc = 0;
2299
2300         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2301                 filter = flow->filter;
2302                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2303                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2304                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2305                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2306                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2307                 else
2308                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2309
2310                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2311                 rte_free(flow);
2312                 //if (rc)
2313                         //break;
2314         }
2315         return rc;
2316 }
2317
2318 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2319 {
2320         struct bnxt_filter_info *filter;
2321         int rc = 0;
2322
2323         STAILQ_FOREACH(filter, &vnic->filter, next) {
2324                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2325                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2326                                                      filter);
2327                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2328                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2329                                                          filter);
2330                 else
2331                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2332                                                      filter);
2333                 if (rc)
2334                         break;
2335         }
2336         return rc;
2337 }
2338
2339 void bnxt_free_tunnel_ports(struct bnxt *bp)
2340 {
2341         if (bp->vxlan_port_cnt)
2342                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2343                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2344         bp->vxlan_port = 0;
2345         if (bp->geneve_port_cnt)
2346                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2347                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2348         bp->geneve_port = 0;
2349 }
2350
2351 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2352 {
2353         int i, j;
2354
2355         if (bp->vnic_info == NULL)
2356                 return;
2357
2358         /*
2359          * Cleanup VNICs in reverse order, to make sure the L2 filter
2360          * from vnic0 is last to be cleaned up.
2361          */
2362         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2363                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2364
2365                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2366                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2367                         return;
2368                 }
2369
2370                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2371
2372                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2373
2374                 if (BNXT_CHIP_THOR(bp)) {
2375                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2376                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2377                                                         vnic->fw_grp_ids[j]);
2378                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2379                         }
2380                         vnic->num_lb_ctxts = 0;
2381                 } else {
2382                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2383                         vnic->rss_rule = INVALID_HW_RING_ID;
2384                 }
2385
2386                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2387
2388                 bnxt_hwrm_vnic_free(bp, vnic);
2389
2390                 rte_free(vnic->fw_grp_ids);
2391         }
2392         /* Ring resources */
2393         bnxt_free_all_hwrm_rings(bp);
2394         bnxt_free_all_hwrm_ring_grps(bp);
2395         bnxt_free_all_hwrm_stat_ctxs(bp);
2396         bnxt_free_tunnel_ports(bp);
2397 }
2398
2399 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2400 {
2401         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2402
2403         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2404                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2405
2406         switch (conf_link_speed) {
2407         case ETH_LINK_SPEED_10M_HD:
2408         case ETH_LINK_SPEED_100M_HD:
2409                 /* FALLTHROUGH */
2410                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2411         }
2412         return hw_link_duplex;
2413 }
2414
2415 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2416 {
2417         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2418 }
2419
2420 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2421 {
2422         uint16_t eth_link_speed = 0;
2423
2424         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2425                 return ETH_LINK_SPEED_AUTONEG;
2426
2427         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2428         case ETH_LINK_SPEED_100M:
2429         case ETH_LINK_SPEED_100M_HD:
2430                 /* FALLTHROUGH */
2431                 eth_link_speed =
2432                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2433                 break;
2434         case ETH_LINK_SPEED_1G:
2435                 eth_link_speed =
2436                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2437                 break;
2438         case ETH_LINK_SPEED_2_5G:
2439                 eth_link_speed =
2440                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2441                 break;
2442         case ETH_LINK_SPEED_10G:
2443                 eth_link_speed =
2444                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2445                 break;
2446         case ETH_LINK_SPEED_20G:
2447                 eth_link_speed =
2448                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2449                 break;
2450         case ETH_LINK_SPEED_25G:
2451                 eth_link_speed =
2452                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2453                 break;
2454         case ETH_LINK_SPEED_40G:
2455                 eth_link_speed =
2456                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2457                 break;
2458         case ETH_LINK_SPEED_50G:
2459                 eth_link_speed =
2460                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2461                 break;
2462         case ETH_LINK_SPEED_100G:
2463                 eth_link_speed =
2464                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2465                 break;
2466         default:
2467                 PMD_DRV_LOG(ERR,
2468                         "Unsupported link speed %d; default to AUTO\n",
2469                         conf_link_speed);
2470                 break;
2471         }
2472         return eth_link_speed;
2473 }
2474
2475 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2476                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2477                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2478                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2479
2480 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2481 {
2482         uint32_t one_speed;
2483
2484         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2485                 return 0;
2486
2487         if (link_speed & ETH_LINK_SPEED_FIXED) {
2488                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2489
2490                 if (one_speed & (one_speed - 1)) {
2491                         PMD_DRV_LOG(ERR,
2492                                 "Invalid advertised speeds (%u) for port %u\n",
2493                                 link_speed, port_id);
2494                         return -EINVAL;
2495                 }
2496                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2497                         PMD_DRV_LOG(ERR,
2498                                 "Unsupported advertised speed (%u) for port %u\n",
2499                                 link_speed, port_id);
2500                         return -EINVAL;
2501                 }
2502         } else {
2503                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2504                         PMD_DRV_LOG(ERR,
2505                                 "Unsupported advertised speeds (%u) for port %u\n",
2506                                 link_speed, port_id);
2507                         return -EINVAL;
2508                 }
2509         }
2510         return 0;
2511 }
2512
2513 static uint16_t
2514 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2515 {
2516         uint16_t ret = 0;
2517
2518         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2519                 if (bp->link_info.support_speeds)
2520                         return bp->link_info.support_speeds;
2521                 link_speed = BNXT_SUPPORTED_SPEEDS;
2522         }
2523
2524         if (link_speed & ETH_LINK_SPEED_100M)
2525                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2526         if (link_speed & ETH_LINK_SPEED_100M_HD)
2527                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2528         if (link_speed & ETH_LINK_SPEED_1G)
2529                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2530         if (link_speed & ETH_LINK_SPEED_2_5G)
2531                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2532         if (link_speed & ETH_LINK_SPEED_10G)
2533                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2534         if (link_speed & ETH_LINK_SPEED_20G)
2535                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2536         if (link_speed & ETH_LINK_SPEED_25G)
2537                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2538         if (link_speed & ETH_LINK_SPEED_40G)
2539                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2540         if (link_speed & ETH_LINK_SPEED_50G)
2541                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2542         if (link_speed & ETH_LINK_SPEED_100G)
2543                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2544         return ret;
2545 }
2546
2547 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2548 {
2549         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2550
2551         switch (hw_link_speed) {
2552         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2553                 eth_link_speed = ETH_SPEED_NUM_100M;
2554                 break;
2555         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2556                 eth_link_speed = ETH_SPEED_NUM_1G;
2557                 break;
2558         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2559                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2560                 break;
2561         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2562                 eth_link_speed = ETH_SPEED_NUM_10G;
2563                 break;
2564         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2565                 eth_link_speed = ETH_SPEED_NUM_20G;
2566                 break;
2567         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2568                 eth_link_speed = ETH_SPEED_NUM_25G;
2569                 break;
2570         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2571                 eth_link_speed = ETH_SPEED_NUM_40G;
2572                 break;
2573         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2574                 eth_link_speed = ETH_SPEED_NUM_50G;
2575                 break;
2576         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2577                 eth_link_speed = ETH_SPEED_NUM_100G;
2578                 break;
2579         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2580         default:
2581                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2582                         hw_link_speed);
2583                 break;
2584         }
2585         return eth_link_speed;
2586 }
2587
2588 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2589 {
2590         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2591
2592         switch (hw_link_duplex) {
2593         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2594         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2595                 /* FALLTHROUGH */
2596                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2597                 break;
2598         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2599                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2600                 break;
2601         default:
2602                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2603                         hw_link_duplex);
2604                 break;
2605         }
2606         return eth_link_duplex;
2607 }
2608
2609 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2610 {
2611         int rc = 0;
2612         struct bnxt_link_info *link_info = &bp->link_info;
2613
2614         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2615         if (rc) {
2616                 PMD_DRV_LOG(ERR,
2617                         "Get link config failed with rc %d\n", rc);
2618                 goto exit;
2619         }
2620         if (link_info->link_speed)
2621                 link->link_speed =
2622                         bnxt_parse_hw_link_speed(link_info->link_speed);
2623         else
2624                 link->link_speed = ETH_SPEED_NUM_NONE;
2625         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2626         link->link_status = link_info->link_up;
2627         link->link_autoneg = link_info->auto_mode ==
2628                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2629                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2630 exit:
2631         return rc;
2632 }
2633
2634 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2635 {
2636         int rc = 0;
2637         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2638         struct bnxt_link_info link_req;
2639         uint16_t speed, autoneg;
2640
2641         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2642                 return 0;
2643
2644         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2645                         bp->eth_dev->data->port_id);
2646         if (rc)
2647                 goto error;
2648
2649         memset(&link_req, 0, sizeof(link_req));
2650         link_req.link_up = link_up;
2651         if (!link_up)
2652                 goto port_phy_cfg;
2653
2654         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2655         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2656         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2657         /* Autoneg can be done only when the FW allows */
2658         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2659                                 bp->link_info.force_link_speed)) {
2660                 link_req.phy_flags |=
2661                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2662                 link_req.auto_link_speed_mask =
2663                         bnxt_parse_eth_link_speed_mask(bp,
2664                                                        dev_conf->link_speeds);
2665         } else {
2666                 if (bp->link_info.phy_type ==
2667                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2668                     bp->link_info.phy_type ==
2669                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2670                     bp->link_info.media_type ==
2671                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2672                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2673                         return -EINVAL;
2674                 }
2675
2676                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2677                 /* If user wants a particular speed try that first. */
2678                 if (speed)
2679                         link_req.link_speed = speed;
2680                 else if (bp->link_info.force_link_speed)
2681                         link_req.link_speed = bp->link_info.force_link_speed;
2682                 else
2683                         link_req.link_speed = bp->link_info.auto_link_speed;
2684         }
2685         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2686         link_req.auto_pause = bp->link_info.auto_pause;
2687         link_req.force_pause = bp->link_info.force_pause;
2688
2689 port_phy_cfg:
2690         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2691         if (rc) {
2692                 PMD_DRV_LOG(ERR,
2693                         "Set link config failed with rc %d\n", rc);
2694         }
2695
2696 error:
2697         return rc;
2698 }
2699
2700 /* JIRA 22088 */
2701 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2702 {
2703         struct hwrm_func_qcfg_input req = {0};
2704         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2705         uint16_t flags;
2706         int rc = 0;
2707
2708         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2709         req.fid = rte_cpu_to_le_16(0xffff);
2710
2711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2712
2713         HWRM_CHECK_RESULT();
2714
2715         /* Hard Coded.. 0xfff VLAN ID mask */
2716         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2717         flags = rte_le_to_cpu_16(resp->flags);
2718         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2719                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2720
2721         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2722                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2723                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2724         } else if (BNXT_VF(bp) &&
2725                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2726                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2727                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2728         }
2729
2730         if (mtu)
2731                 *mtu = resp->mtu;
2732
2733         switch (resp->port_partition_type) {
2734         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2735         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2736         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2737                 /* FALLTHROUGH */
2738                 bp->port_partition_type = resp->port_partition_type;
2739                 break;
2740         default:
2741                 bp->port_partition_type = 0;
2742                 break;
2743         }
2744
2745         HWRM_UNLOCK();
2746
2747         return rc;
2748 }
2749
2750 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2751                                    struct hwrm_func_qcaps_output *qcaps)
2752 {
2753         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2754         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2755                sizeof(qcaps->mac_address));
2756         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2757         qcaps->max_rx_rings = fcfg->num_rx_rings;
2758         qcaps->max_tx_rings = fcfg->num_tx_rings;
2759         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2760         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2761         qcaps->max_vfs = 0;
2762         qcaps->first_vf_id = 0;
2763         qcaps->max_vnics = fcfg->num_vnics;
2764         qcaps->max_decap_records = 0;
2765         qcaps->max_encap_records = 0;
2766         qcaps->max_tx_wm_flows = 0;
2767         qcaps->max_tx_em_flows = 0;
2768         qcaps->max_rx_wm_flows = 0;
2769         qcaps->max_rx_em_flows = 0;
2770         qcaps->max_flow_id = 0;
2771         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2772         qcaps->max_sp_tx_rings = 0;
2773         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2774 }
2775
2776 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2777 {
2778         struct hwrm_func_cfg_input req = {0};
2779         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2780         uint32_t enables;
2781         int rc;
2782
2783         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2784                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2785                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2786                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2787                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2788                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2789                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2790                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2791                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2792
2793         if (BNXT_HAS_RING_GRPS(bp)) {
2794                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2795                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2796         } else if (BNXT_HAS_NQ(bp)) {
2797                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2798                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2799         }
2800
2801         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2802         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2803         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2804                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2805                                    BNXT_NUM_VLANS);
2806         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2807         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2808         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2809         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2810         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2811         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2812         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2813         req.fid = rte_cpu_to_le_16(0xffff);
2814         req.enables = rte_cpu_to_le_32(enables);
2815
2816         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2817
2818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2819
2820         HWRM_CHECK_RESULT();
2821         HWRM_UNLOCK();
2822
2823         return rc;
2824 }
2825
2826 static void populate_vf_func_cfg_req(struct bnxt *bp,
2827                                      struct hwrm_func_cfg_input *req,
2828                                      int num_vfs)
2829 {
2830         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2831                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2832                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2833                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2834                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2835                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2836                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2837                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2838                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2839                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2840
2841         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2842                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2843                                     BNXT_NUM_VLANS);
2844         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2845                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2846                                     BNXT_NUM_VLANS);
2847         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2848                                                 (num_vfs + 1));
2849         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2850         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2851                                                (num_vfs + 1));
2852         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2853         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2854         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2855         /* TODO: For now, do not support VMDq/RFS on VFs. */
2856         req->num_vnics = rte_cpu_to_le_16(1);
2857         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2858                                                  (num_vfs + 1));
2859 }
2860
2861 static void add_random_mac_if_needed(struct bnxt *bp,
2862                                      struct hwrm_func_cfg_input *cfg_req,
2863                                      int vf)
2864 {
2865         struct rte_ether_addr mac;
2866
2867         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2868                 return;
2869
2870         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2871                 cfg_req->enables |=
2872                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2873                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2874                 bp->pf.vf_info[vf].random_mac = true;
2875         } else {
2876                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2877                         RTE_ETHER_ADDR_LEN);
2878         }
2879 }
2880
2881 static void reserve_resources_from_vf(struct bnxt *bp,
2882                                       struct hwrm_func_cfg_input *cfg_req,
2883                                       int vf)
2884 {
2885         struct hwrm_func_qcaps_input req = {0};
2886         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2887         int rc;
2888
2889         /* Get the actual allocated values now */
2890         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2891         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2893
2894         if (rc) {
2895                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2896                 copy_func_cfg_to_qcaps(cfg_req, resp);
2897         } else if (resp->error_code) {
2898                 rc = rte_le_to_cpu_16(resp->error_code);
2899                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2900                 copy_func_cfg_to_qcaps(cfg_req, resp);
2901         }
2902
2903         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2904         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2905         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2906         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2907         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2908         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2909         /*
2910          * TODO: While not supporting VMDq with VFs, max_vnics is always
2911          * forced to 1 in this case
2912          */
2913         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2914         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2915
2916         HWRM_UNLOCK();
2917 }
2918
2919 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2920 {
2921         struct hwrm_func_qcfg_input req = {0};
2922         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2923         int rc;
2924
2925         /* Check for zero MAC address */
2926         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2927         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2928         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2929         HWRM_CHECK_RESULT();
2930         rc = rte_le_to_cpu_16(resp->vlan);
2931
2932         HWRM_UNLOCK();
2933
2934         return rc;
2935 }
2936
2937 static int update_pf_resource_max(struct bnxt *bp)
2938 {
2939         struct hwrm_func_qcfg_input req = {0};
2940         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2941         int rc;
2942
2943         /* And copy the allocated numbers into the pf struct */
2944         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2945         req.fid = rte_cpu_to_le_16(0xffff);
2946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2947         HWRM_CHECK_RESULT();
2948
2949         /* Only TX ring value reflects actual allocation? TODO */
2950         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2951         bp->pf.evb_mode = resp->evb_mode;
2952
2953         HWRM_UNLOCK();
2954
2955         return rc;
2956 }
2957
2958 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2959 {
2960         int rc;
2961
2962         if (!BNXT_PF(bp)) {
2963                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2964                 return -EINVAL;
2965         }
2966
2967         rc = bnxt_hwrm_func_qcaps(bp);
2968         if (rc)
2969                 return rc;
2970
2971         bp->pf.func_cfg_flags &=
2972                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2973                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2974         bp->pf.func_cfg_flags |=
2975                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2976         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2977         rc = __bnxt_hwrm_func_qcaps(bp);
2978         return rc;
2979 }
2980
2981 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2982 {
2983         struct hwrm_func_cfg_input req = {0};
2984         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2985         int i;
2986         size_t sz;
2987         int rc = 0;
2988         size_t req_buf_sz;
2989
2990         if (!BNXT_PF(bp)) {
2991                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2992                 return -EINVAL;
2993         }
2994
2995         rc = bnxt_hwrm_func_qcaps(bp);
2996
2997         if (rc)
2998                 return rc;
2999
3000         bp->pf.active_vfs = num_vfs;
3001
3002         /*
3003          * First, configure the PF to only use one TX ring.  This ensures that
3004          * there are enough rings for all VFs.
3005          *
3006          * If we don't do this, when we call func_alloc() later, we will lock
3007          * extra rings to the PF that won't be available during func_cfg() of
3008          * the VFs.
3009          *
3010          * This has been fixed with firmware versions above 20.6.54
3011          */
3012         bp->pf.func_cfg_flags &=
3013                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3014                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3015         bp->pf.func_cfg_flags |=
3016                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3017         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3018         if (rc)
3019                 return rc;
3020
3021         /*
3022          * Now, create and register a buffer to hold forwarded VF requests
3023          */
3024         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3025         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3026                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3027         if (bp->pf.vf_req_buf == NULL) {
3028                 rc = -ENOMEM;
3029                 goto error_free;
3030         }
3031         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3032                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3033         for (i = 0; i < num_vfs; i++)
3034                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3035                                         (i * HWRM_MAX_REQ_LEN);
3036
3037         rc = bnxt_hwrm_func_buf_rgtr(bp);
3038         if (rc)
3039                 goto error_free;
3040
3041         populate_vf_func_cfg_req(bp, &req, num_vfs);
3042
3043         bp->pf.active_vfs = 0;
3044         for (i = 0; i < num_vfs; i++) {
3045                 add_random_mac_if_needed(bp, &req, i);
3046
3047                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3048                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3049                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3050                 rc = bnxt_hwrm_send_message(bp,
3051                                             &req,
3052                                             sizeof(req),
3053                                             BNXT_USE_CHIMP_MB);
3054
3055                 /* Clear enable flag for next pass */
3056                 req.enables &= ~rte_cpu_to_le_32(
3057                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3058
3059                 if (rc || resp->error_code) {
3060                         PMD_DRV_LOG(ERR,
3061                                 "Failed to initizlie VF %d\n", i);
3062                         PMD_DRV_LOG(ERR,
3063                                 "Not all VFs available. (%d, %d)\n",
3064                                 rc, resp->error_code);
3065                         HWRM_UNLOCK();
3066                         break;
3067                 }
3068
3069                 HWRM_UNLOCK();
3070
3071                 reserve_resources_from_vf(bp, &req, i);
3072                 bp->pf.active_vfs++;
3073                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3074         }
3075
3076         /*
3077          * Now configure the PF to use "the rest" of the resources
3078          * We're using STD_TX_RING_MODE here though which will limit the TX
3079          * rings.  This will allow QoS to function properly.  Not setting this
3080          * will cause PF rings to break bandwidth settings.
3081          */
3082         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3083         if (rc)
3084                 goto error_free;
3085
3086         rc = update_pf_resource_max(bp);
3087         if (rc)
3088                 goto error_free;
3089
3090         return rc;
3091
3092 error_free:
3093         bnxt_hwrm_func_buf_unrgtr(bp);
3094         return rc;
3095 }
3096
3097 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3098 {
3099         struct hwrm_func_cfg_input req = {0};
3100         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3101         int rc;
3102
3103         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3104
3105         req.fid = rte_cpu_to_le_16(0xffff);
3106         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3107         req.evb_mode = bp->pf.evb_mode;
3108
3109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110         HWRM_CHECK_RESULT();
3111         HWRM_UNLOCK();
3112
3113         return rc;
3114 }
3115
3116 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3117                                 uint8_t tunnel_type)
3118 {
3119         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3120         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3121         int rc = 0;
3122
3123         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3124         req.tunnel_type = tunnel_type;
3125         req.tunnel_dst_port_val = port;
3126         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3127         HWRM_CHECK_RESULT();
3128
3129         switch (tunnel_type) {
3130         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3131                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3132                 bp->vxlan_port = port;
3133                 break;
3134         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3135                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3136                 bp->geneve_port = port;
3137                 break;
3138         default:
3139                 break;
3140         }
3141
3142         HWRM_UNLOCK();
3143
3144         return rc;
3145 }
3146
3147 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3148                                 uint8_t tunnel_type)
3149 {
3150         struct hwrm_tunnel_dst_port_free_input req = {0};
3151         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3152         int rc = 0;
3153
3154         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3155
3156         req.tunnel_type = tunnel_type;
3157         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3159
3160         HWRM_CHECK_RESULT();
3161         HWRM_UNLOCK();
3162
3163         return rc;
3164 }
3165
3166 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3167                                         uint32_t flags)
3168 {
3169         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3170         struct hwrm_func_cfg_input req = {0};
3171         int rc;
3172
3173         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3174
3175         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3176         req.flags = rte_cpu_to_le_32(flags);
3177         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3178
3179         HWRM_CHECK_RESULT();
3180         HWRM_UNLOCK();
3181
3182         return rc;
3183 }
3184
3185 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3186 {
3187         uint32_t *flag = flagp;
3188
3189         vnic->flags = *flag;
3190 }
3191
3192 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3193 {
3194         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3195 }
3196
3197 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3198 {
3199         int rc = 0;
3200         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3201         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3202
3203         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3204
3205         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3206         req.req_buf_page_size = rte_cpu_to_le_16(
3207                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3208         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3209         req.req_buf_page_addr0 =
3210                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3211         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3212                 PMD_DRV_LOG(ERR,
3213                         "unable to map buffer address to physical memory\n");
3214                 return -ENOMEM;
3215         }
3216
3217         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3218
3219         HWRM_CHECK_RESULT();
3220         HWRM_UNLOCK();
3221
3222         return rc;
3223 }
3224
3225 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3226 {
3227         int rc = 0;
3228         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3229         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3230
3231         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3232                 return 0;
3233
3234         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3235
3236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3237
3238         HWRM_CHECK_RESULT();
3239         HWRM_UNLOCK();
3240
3241         return rc;
3242 }
3243
3244 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3245 {
3246         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3247         struct hwrm_func_cfg_input req = {0};
3248         int rc;
3249
3250         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3251
3252         req.fid = rte_cpu_to_le_16(0xffff);
3253         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3254         req.enables = rte_cpu_to_le_32(
3255                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3256         req.async_event_cr = rte_cpu_to_le_16(
3257                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3259
3260         HWRM_CHECK_RESULT();
3261         HWRM_UNLOCK();
3262
3263         return rc;
3264 }
3265
3266 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3267 {
3268         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3269         struct hwrm_func_vf_cfg_input req = {0};
3270         int rc;
3271
3272         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3273
3274         req.enables = rte_cpu_to_le_32(
3275                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3276         req.async_event_cr = rte_cpu_to_le_16(
3277                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3279
3280         HWRM_CHECK_RESULT();
3281         HWRM_UNLOCK();
3282
3283         return rc;
3284 }
3285
3286 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3287 {
3288         struct hwrm_func_cfg_input req = {0};
3289         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3290         uint16_t dflt_vlan, fid;
3291         uint32_t func_cfg_flags;
3292         int rc = 0;
3293
3294         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3295
3296         if (is_vf) {
3297                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3298                 fid = bp->pf.vf_info[vf].fid;
3299                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3300         } else {
3301                 fid = rte_cpu_to_le_16(0xffff);
3302                 func_cfg_flags = bp->pf.func_cfg_flags;
3303                 dflt_vlan = bp->vlan;
3304         }
3305
3306         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3307         req.fid = rte_cpu_to_le_16(fid);
3308         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3309         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3310
3311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3312
3313         HWRM_CHECK_RESULT();
3314         HWRM_UNLOCK();
3315
3316         return rc;
3317 }
3318
3319 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3320                         uint16_t max_bw, uint16_t enables)
3321 {
3322         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3323         struct hwrm_func_cfg_input req = {0};
3324         int rc;
3325
3326         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3327
3328         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3329         req.enables |= rte_cpu_to_le_32(enables);
3330         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3331         req.max_bw = rte_cpu_to_le_32(max_bw);
3332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3333
3334         HWRM_CHECK_RESULT();
3335         HWRM_UNLOCK();
3336
3337         return rc;
3338 }
3339
3340 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3341 {
3342         struct hwrm_func_cfg_input req = {0};
3343         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3344         int rc = 0;
3345
3346         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3347
3348         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3349         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3350         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3351         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3352
3353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3354
3355         HWRM_CHECK_RESULT();
3356         HWRM_UNLOCK();
3357
3358         return rc;
3359 }
3360
3361 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3362 {
3363         int rc;
3364
3365         if (BNXT_PF(bp))
3366                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3367         else
3368                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3369
3370         return rc;
3371 }
3372
3373 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3374                               void *encaped, size_t ec_size)
3375 {
3376         int rc = 0;
3377         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3378         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3379
3380         if (ec_size > sizeof(req.encap_request))
3381                 return -1;
3382
3383         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3384
3385         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3386         memcpy(req.encap_request, encaped, ec_size);
3387
3388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389
3390         HWRM_CHECK_RESULT();
3391         HWRM_UNLOCK();
3392
3393         return rc;
3394 }
3395
3396 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3397                                        struct rte_ether_addr *mac)
3398 {
3399         struct hwrm_func_qcfg_input req = {0};
3400         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3401         int rc;
3402
3403         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3404
3405         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3407
3408         HWRM_CHECK_RESULT();
3409
3410         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3411
3412         HWRM_UNLOCK();
3413
3414         return rc;
3415 }
3416
3417 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3418                             void *encaped, size_t ec_size)
3419 {
3420         int rc = 0;
3421         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3422         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3423
3424         if (ec_size > sizeof(req.encap_request))
3425                 return -1;
3426
3427         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3428
3429         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3430         memcpy(req.encap_request, encaped, ec_size);
3431
3432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3433
3434         HWRM_CHECK_RESULT();
3435         HWRM_UNLOCK();
3436
3437         return rc;
3438 }
3439
3440 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3441                          struct rte_eth_stats *stats, uint8_t rx)
3442 {
3443         int rc = 0;
3444         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3445         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3446
3447         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3448
3449         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3450
3451         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3452
3453         HWRM_CHECK_RESULT();
3454
3455         if (rx) {
3456                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3457                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3458                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3459                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3460                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3461                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3462                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3463                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3464         } else {
3465                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3466                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3467                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3468                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3469                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3470                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3471         }
3472
3473
3474         HWRM_UNLOCK();
3475
3476         return rc;
3477 }
3478
3479 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3480 {
3481         struct hwrm_port_qstats_input req = {0};
3482         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3483         struct bnxt_pf_info *pf = &bp->pf;
3484         int rc;
3485
3486         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3487
3488         req.port_id = rte_cpu_to_le_16(pf->port_id);
3489         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3490         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492
3493         HWRM_CHECK_RESULT();
3494         HWRM_UNLOCK();
3495
3496         return rc;
3497 }
3498
3499 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3500 {
3501         struct hwrm_port_clr_stats_input req = {0};
3502         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3503         struct bnxt_pf_info *pf = &bp->pf;
3504         int rc;
3505
3506         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3507         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3508             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3509                 return 0;
3510
3511         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3512
3513         req.port_id = rte_cpu_to_le_16(pf->port_id);
3514         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3515
3516         HWRM_CHECK_RESULT();
3517         HWRM_UNLOCK();
3518
3519         return rc;
3520 }
3521
3522 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3523 {
3524         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3525         struct hwrm_port_led_qcaps_input req = {0};
3526         int rc;
3527
3528         if (BNXT_VF(bp))
3529                 return 0;
3530
3531         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3532         req.port_id = bp->pf.port_id;
3533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3534
3535         HWRM_CHECK_RESULT();
3536
3537         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3538                 unsigned int i;
3539
3540                 bp->num_leds = resp->num_leds;
3541                 memcpy(bp->leds, &resp->led0_id,
3542                         sizeof(bp->leds[0]) * bp->num_leds);
3543                 for (i = 0; i < bp->num_leds; i++) {
3544                         struct bnxt_led_info *led = &bp->leds[i];
3545
3546                         uint16_t caps = led->led_state_caps;
3547
3548                         if (!led->led_group_id ||
3549                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3550                                 bp->num_leds = 0;
3551                                 break;
3552                         }
3553                 }
3554         }
3555
3556         HWRM_UNLOCK();
3557
3558         return rc;
3559 }
3560
3561 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3562 {
3563         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3564         struct hwrm_port_led_cfg_input req = {0};
3565         struct bnxt_led_cfg *led_cfg;
3566         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3567         uint16_t duration = 0;
3568         int rc, i;
3569
3570         if (!bp->num_leds || BNXT_VF(bp))
3571                 return -EOPNOTSUPP;
3572
3573         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3574
3575         if (led_on) {
3576                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3577                 duration = rte_cpu_to_le_16(500);
3578         }
3579         req.port_id = bp->pf.port_id;
3580         req.num_leds = bp->num_leds;
3581         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3582         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3583                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3584                 led_cfg->led_id = bp->leds[i].led_id;
3585                 led_cfg->led_state = led_state;
3586                 led_cfg->led_blink_on = duration;
3587                 led_cfg->led_blink_off = duration;
3588                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3589         }
3590
3591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592
3593         HWRM_CHECK_RESULT();
3594         HWRM_UNLOCK();
3595
3596         return rc;
3597 }
3598
3599 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3600                                uint32_t *length)
3601 {
3602         int rc;
3603         struct hwrm_nvm_get_dir_info_input req = {0};
3604         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3605
3606         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3607
3608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3609
3610         HWRM_CHECK_RESULT();
3611
3612         *entries = rte_le_to_cpu_32(resp->entries);
3613         *length = rte_le_to_cpu_32(resp->entry_length);
3614
3615         HWRM_UNLOCK();
3616         return rc;
3617 }
3618
3619 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3620 {
3621         int rc;
3622         uint32_t dir_entries;
3623         uint32_t entry_length;
3624         uint8_t *buf;
3625         size_t buflen;
3626         rte_iova_t dma_handle;
3627         struct hwrm_nvm_get_dir_entries_input req = {0};
3628         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3629
3630         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3631         if (rc != 0)
3632                 return rc;
3633
3634         *data++ = dir_entries;
3635         *data++ = entry_length;
3636         len -= 2;
3637         memset(data, 0xff, len);
3638
3639         buflen = dir_entries * entry_length;
3640         buf = rte_malloc("nvm_dir", buflen, 0);
3641         rte_mem_lock_page(buf);
3642         if (buf == NULL)
3643                 return -ENOMEM;
3644         dma_handle = rte_mem_virt2iova(buf);
3645         if (dma_handle == RTE_BAD_IOVA) {
3646                 PMD_DRV_LOG(ERR,
3647                         "unable to map response address to physical memory\n");
3648                 return -ENOMEM;
3649         }
3650         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3651         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3653
3654         if (rc == 0)
3655                 memcpy(data, buf, len > buflen ? buflen : len);
3656
3657         rte_free(buf);
3658         HWRM_CHECK_RESULT();
3659         HWRM_UNLOCK();
3660
3661         return rc;
3662 }
3663
3664 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3665                              uint32_t offset, uint32_t length,
3666                              uint8_t *data)
3667 {
3668         int rc;
3669         uint8_t *buf;
3670         rte_iova_t dma_handle;
3671         struct hwrm_nvm_read_input req = {0};
3672         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3673
3674         buf = rte_malloc("nvm_item", length, 0);
3675         rte_mem_lock_page(buf);
3676         if (!buf)
3677                 return -ENOMEM;
3678
3679         dma_handle = rte_mem_virt2iova(buf);
3680         if (dma_handle == RTE_BAD_IOVA) {
3681                 PMD_DRV_LOG(ERR,
3682                         "unable to map response address to physical memory\n");
3683                 return -ENOMEM;
3684         }
3685         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3686         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3687         req.dir_idx = rte_cpu_to_le_16(index);
3688         req.offset = rte_cpu_to_le_32(offset);
3689         req.len = rte_cpu_to_le_32(length);
3690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3691         if (rc == 0)
3692                 memcpy(data, buf, length);
3693
3694         rte_free(buf);
3695         HWRM_CHECK_RESULT();
3696         HWRM_UNLOCK();
3697
3698         return rc;
3699 }
3700
3701 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3702 {
3703         int rc;
3704         struct hwrm_nvm_erase_dir_entry_input req = {0};
3705         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3706
3707         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3708         req.dir_idx = rte_cpu_to_le_16(index);
3709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3710         HWRM_CHECK_RESULT();
3711         HWRM_UNLOCK();
3712
3713         return rc;
3714 }
3715
3716
3717 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3718                           uint16_t dir_ordinal, uint16_t dir_ext,
3719                           uint16_t dir_attr, const uint8_t *data,
3720                           size_t data_len)
3721 {
3722         int rc;
3723         struct hwrm_nvm_write_input req = {0};
3724         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3725         rte_iova_t dma_handle;
3726         uint8_t *buf;
3727
3728         buf = rte_malloc("nvm_write", data_len, 0);
3729         rte_mem_lock_page(buf);
3730         if (!buf)
3731                 return -ENOMEM;
3732
3733         dma_handle = rte_mem_virt2iova(buf);
3734         if (dma_handle == RTE_BAD_IOVA) {
3735                 PMD_DRV_LOG(ERR,
3736                         "unable to map response address to physical memory\n");
3737                 return -ENOMEM;
3738         }
3739         memcpy(buf, data, data_len);
3740
3741         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3742
3743         req.dir_type = rte_cpu_to_le_16(dir_type);
3744         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3745         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3746         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3747         req.dir_data_length = rte_cpu_to_le_32(data_len);
3748         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3749
3750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3751
3752         rte_free(buf);
3753         HWRM_CHECK_RESULT();
3754         HWRM_UNLOCK();
3755
3756         return rc;
3757 }
3758
3759 static void
3760 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3761 {
3762         uint32_t *count = cbdata;
3763
3764         *count = *count + 1;
3765 }
3766
3767 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3768                                      struct bnxt_vnic_info *vnic __rte_unused)
3769 {
3770         return 0;
3771 }
3772
3773 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3774 {
3775         uint32_t count = 0;
3776
3777         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3778             &count, bnxt_vnic_count_hwrm_stub);
3779
3780         return count;
3781 }
3782
3783 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3784                                         uint16_t *vnic_ids)
3785 {
3786         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3787         struct hwrm_func_vf_vnic_ids_query_output *resp =
3788                                                 bp->hwrm_cmd_resp_addr;
3789         int rc;
3790
3791         /* First query all VNIC ids */
3792         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3793
3794         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3795         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3796         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3797
3798         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3799                 HWRM_UNLOCK();
3800                 PMD_DRV_LOG(ERR,
3801                 "unable to map VNIC ID table address to physical memory\n");
3802                 return -ENOMEM;
3803         }
3804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3805         HWRM_CHECK_RESULT();
3806         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3807
3808         HWRM_UNLOCK();
3809
3810         return rc;
3811 }
3812
3813 /*
3814  * This function queries the VNIC IDs  for a specified VF. It then calls
3815  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3816  * Then it calls the hwrm_cb function to program this new vnic configuration.
3817  */
3818 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3819         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3820         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3821 {
3822         struct bnxt_vnic_info vnic;
3823         int rc = 0;
3824         int i, num_vnic_ids;
3825         uint16_t *vnic_ids;
3826         size_t vnic_id_sz;
3827         size_t sz;
3828
3829         /* First query all VNIC ids */
3830         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3831         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3832                         RTE_CACHE_LINE_SIZE);
3833         if (vnic_ids == NULL)
3834                 return -ENOMEM;
3835
3836         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3837                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3838
3839         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3840
3841         if (num_vnic_ids < 0)
3842                 return num_vnic_ids;
3843
3844         /* Retrieve VNIC, update bd_stall then update */
3845
3846         for (i = 0; i < num_vnic_ids; i++) {
3847                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3848                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3849                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3850                 if (rc)
3851                         break;
3852                 if (vnic.mru <= 4)      /* Indicates unallocated */
3853                         continue;
3854
3855                 vnic_cb(&vnic, cbdata);
3856
3857                 rc = hwrm_cb(bp, &vnic);
3858                 if (rc)
3859                         break;
3860         }
3861
3862         rte_free(vnic_ids);
3863
3864         return rc;
3865 }
3866
3867 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3868                                               bool on)
3869 {
3870         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3871         struct hwrm_func_cfg_input req = {0};
3872         int rc;
3873
3874         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3875
3876         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3877         req.enables |= rte_cpu_to_le_32(
3878                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3879         req.vlan_antispoof_mode = on ?
3880                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3881                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3883
3884         HWRM_CHECK_RESULT();
3885         HWRM_UNLOCK();
3886
3887         return rc;
3888 }
3889
3890 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3891 {
3892         struct bnxt_vnic_info vnic;
3893         uint16_t *vnic_ids;
3894         size_t vnic_id_sz;
3895         int num_vnic_ids, i;
3896         size_t sz;
3897         int rc;
3898
3899         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3900         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3901                         RTE_CACHE_LINE_SIZE);
3902         if (vnic_ids == NULL)
3903                 return -ENOMEM;
3904
3905         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3906                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3907
3908         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3909         if (rc <= 0)
3910                 goto exit;
3911         num_vnic_ids = rc;
3912
3913         /*
3914          * Loop through to find the default VNIC ID.
3915          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3916          * by sending the hwrm_func_qcfg command to the firmware.
3917          */
3918         for (i = 0; i < num_vnic_ids; i++) {
3919                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3920                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3921                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3922                                         bp->pf.first_vf_id + vf);
3923                 if (rc)
3924                         goto exit;
3925                 if (vnic.func_default) {
3926                         rte_free(vnic_ids);
3927                         return vnic.fw_vnic_id;
3928                 }
3929         }
3930         /* Could not find a default VNIC. */
3931         PMD_DRV_LOG(ERR, "No default VNIC\n");
3932 exit:
3933         rte_free(vnic_ids);
3934         return rc;
3935 }
3936
3937 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3938                          uint16_t dst_id,
3939                          struct bnxt_filter_info *filter)
3940 {
3941         int rc = 0;
3942         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3943         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3944         uint32_t enables = 0;
3945
3946         if (filter->fw_em_filter_id != UINT64_MAX)
3947                 bnxt_hwrm_clear_em_filter(bp, filter);
3948
3949         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3950
3951         req.flags = rte_cpu_to_le_32(filter->flags);
3952
3953         enables = filter->enables |
3954               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3955         req.dst_id = rte_cpu_to_le_16(dst_id);
3956
3957         if (filter->ip_addr_type) {
3958                 req.ip_addr_type = filter->ip_addr_type;
3959                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3960         }
3961         if (enables &
3962             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3963                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3964         if (enables &
3965             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3966                 memcpy(req.src_macaddr, filter->src_macaddr,
3967                        RTE_ETHER_ADDR_LEN);
3968         if (enables &
3969             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3970                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3971                        RTE_ETHER_ADDR_LEN);
3972         if (enables &
3973             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3974                 req.ovlan_vid = filter->l2_ovlan;
3975         if (enables &
3976             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3977                 req.ivlan_vid = filter->l2_ivlan;
3978         if (enables &
3979             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3980                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3981         if (enables &
3982             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3983                 req.ip_protocol = filter->ip_protocol;
3984         if (enables &
3985             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3986                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3987         if (enables &
3988             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3989                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3990         if (enables &
3991             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3992                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3993         if (enables &
3994             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3995                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3996         if (enables &
3997             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3998                 req.mirror_vnic_id = filter->mirror_vnic_id;
3999
4000         req.enables = rte_cpu_to_le_32(enables);
4001
4002         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4003
4004         HWRM_CHECK_RESULT();
4005
4006         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4007         HWRM_UNLOCK();
4008
4009         return rc;
4010 }
4011
4012 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4013 {
4014         int rc = 0;
4015         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4016         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4017
4018         if (filter->fw_em_filter_id == UINT64_MAX)
4019                 return 0;
4020
4021         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4022         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4023
4024         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4025
4026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4027
4028         HWRM_CHECK_RESULT();
4029         HWRM_UNLOCK();
4030
4031         filter->fw_em_filter_id = UINT64_MAX;
4032         filter->fw_l2_filter_id = UINT64_MAX;
4033
4034         return 0;
4035 }
4036
4037 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4038                          uint16_t dst_id,
4039                          struct bnxt_filter_info *filter)
4040 {
4041         int rc = 0;
4042         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4043         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4044                                                 bp->hwrm_cmd_resp_addr;
4045         uint32_t enables = 0;
4046
4047         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4048                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4049
4050         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4051
4052         req.flags = rte_cpu_to_le_32(filter->flags);
4053
4054         enables = filter->enables |
4055               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4056         req.dst_id = rte_cpu_to_le_16(dst_id);
4057
4058
4059         if (filter->ip_addr_type) {
4060                 req.ip_addr_type = filter->ip_addr_type;
4061                 enables |=
4062                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4063         }
4064         if (enables &
4065             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4066                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4067         if (enables &
4068             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4069                 memcpy(req.src_macaddr, filter->src_macaddr,
4070                        RTE_ETHER_ADDR_LEN);
4071         //if (enables &
4072             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4073                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4074                        //RTE_ETHER_ADDR_LEN);
4075         if (enables &
4076             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4077                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4078         if (enables &
4079             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4080                 req.ip_protocol = filter->ip_protocol;
4081         if (enables &
4082             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4083                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4084         if (enables &
4085             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4086                 req.src_ipaddr_mask[0] =
4087                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4088         if (enables &
4089             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4090                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4091         if (enables &
4092             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4093                 req.dst_ipaddr_mask[0] =
4094                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4095         if (enables &
4096             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4097                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4098         if (enables &
4099             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4100                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4101         if (enables &
4102             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4103                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4104         if (enables &
4105             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4106                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4107         if (enables &
4108             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4109                 req.mirror_vnic_id = filter->mirror_vnic_id;
4110
4111         req.enables = rte_cpu_to_le_32(enables);
4112
4113         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4114
4115         HWRM_CHECK_RESULT();
4116
4117         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4118         HWRM_UNLOCK();
4119
4120         return rc;
4121 }
4122
4123 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4124                                 struct bnxt_filter_info *filter)
4125 {
4126         int rc = 0;
4127         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4128         struct hwrm_cfa_ntuple_filter_free_output *resp =
4129                                                 bp->hwrm_cmd_resp_addr;
4130
4131         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4132                 return 0;
4133
4134         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4135
4136         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4137
4138         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4139
4140         HWRM_CHECK_RESULT();
4141         HWRM_UNLOCK();
4142
4143         filter->fw_ntuple_filter_id = UINT64_MAX;
4144
4145         return 0;
4146 }
4147
4148 static int
4149 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4150 {
4151         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4152         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4153         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4154         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4155         uint16_t *ring_tbl = vnic->rss_table;
4156         int nr_ctxs = vnic->num_lb_ctxts;
4157         int max_rings = bp->rx_nr_rings;
4158         int i, j, k, cnt;
4159         int rc = 0;
4160
4161         for (i = 0, k = 0; i < nr_ctxs; i++) {
4162                 struct bnxt_rx_ring_info *rxr;
4163                 struct bnxt_cp_ring_info *cpr;
4164
4165                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4166
4167                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4168                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4169                 req.hash_mode_flags = vnic->hash_mode;
4170
4171                 req.ring_grp_tbl_addr =
4172                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4173                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4174                                      2 * sizeof(*ring_tbl));
4175                 req.hash_key_tbl_addr =
4176                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4177
4178                 req.ring_table_pair_index = i;
4179                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4180
4181                 for (j = 0; j < 64; j++) {
4182                         uint16_t ring_id;
4183
4184                         /* Find next active ring. */
4185                         for (cnt = 0; cnt < max_rings; cnt++) {
4186                                 if (rx_queue_state[k] !=
4187                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4188                                         break;
4189                                 if (++k == max_rings)
4190                                         k = 0;
4191                         }
4192
4193                         /* Return if no rings are active. */
4194                         if (cnt == max_rings)
4195                                 return 0;
4196
4197                         /* Add rx/cp ring pair to RSS table. */
4198                         rxr = rxqs[k]->rx_ring;
4199                         cpr = rxqs[k]->cp_ring;
4200
4201                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4202                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4203                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4204                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4205
4206                         if (++k == max_rings)
4207                                 k = 0;
4208                 }
4209                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4210                                             BNXT_USE_CHIMP_MB);
4211
4212                 HWRM_CHECK_RESULT();
4213                 HWRM_UNLOCK();
4214         }
4215
4216         return rc;
4217 }
4218
4219 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4220 {
4221         unsigned int rss_idx, fw_idx, i;
4222
4223         if (!(vnic->rss_table && vnic->hash_type))
4224                 return 0;
4225
4226         if (BNXT_CHIP_THOR(bp))
4227                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4228
4229         /*
4230          * Fill the RSS hash & redirection table with
4231          * ring group ids for all VNICs
4232          */
4233         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4234                 rss_idx++, fw_idx++) {
4235                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4236                         fw_idx %= bp->rx_cp_nr_rings;
4237                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4238                                 break;
4239                         fw_idx++;
4240                 }
4241                 if (i == bp->rx_cp_nr_rings)
4242                         return 0;
4243                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4244         }
4245         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4246 }
4247
4248 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4249         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4250 {
4251         uint16_t flags;
4252
4253         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4254
4255         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4256         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4257
4258         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4259         req->num_cmpl_dma_aggr_during_int =
4260                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4261
4262         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4263
4264         /* min timer set to 1/2 of interrupt timer */
4265         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4266
4267         /* buf timer set to 1/4 of interrupt timer */
4268         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4269
4270         req->cmpl_aggr_dma_tmr_during_int =
4271                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4272
4273         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4274                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4275         req->flags = rte_cpu_to_le_16(flags);
4276 }
4277
4278 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4279                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4280 {
4281         struct hwrm_ring_aggint_qcaps_input req = {0};
4282         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4283         uint32_t enables;
4284         uint16_t flags;
4285         int rc;
4286
4287         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4289         HWRM_CHECK_RESULT();
4290
4291         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4292         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4293
4294         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4295                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4296         agg_req->flags = rte_cpu_to_le_16(flags);
4297         enables =
4298          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4299          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4300         agg_req->enables = rte_cpu_to_le_32(enables);
4301
4302         HWRM_UNLOCK();
4303         return rc;
4304 }
4305
4306 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4307                         struct bnxt_coal *coal, uint16_t ring_id)
4308 {
4309         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4310         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4311                                                 bp->hwrm_cmd_resp_addr;
4312         int rc;
4313
4314         /* Set ring coalesce parameters only for 100G NICs */
4315         if (BNXT_CHIP_THOR(bp)) {
4316                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4317                         return -1;
4318         } else if (bnxt_stratus_device(bp)) {
4319                 bnxt_hwrm_set_coal_params(coal, &req);
4320         } else {
4321                 return 0;
4322         }
4323
4324         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4325         req.ring_id = rte_cpu_to_le_16(ring_id);
4326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4327         HWRM_CHECK_RESULT();
4328         HWRM_UNLOCK();
4329         return 0;
4330 }
4331
4332 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4333 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4334 {
4335         struct hwrm_func_backing_store_qcaps_input req = {0};
4336         struct hwrm_func_backing_store_qcaps_output *resp =
4337                 bp->hwrm_cmd_resp_addr;
4338         int rc;
4339
4340         if (!BNXT_CHIP_THOR(bp) ||
4341             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4342             BNXT_VF(bp) ||
4343             bp->ctx)
4344                 return 0;
4345
4346         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4347         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4348         HWRM_CHECK_RESULT_SILENT();
4349
4350         if (!rc) {
4351                 struct bnxt_ctx_pg_info *ctx_pg;
4352                 struct bnxt_ctx_mem_info *ctx;
4353                 int total_alloc_len;
4354                 int i;
4355
4356                 total_alloc_len = sizeof(*ctx);
4357                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4358                                  RTE_CACHE_LINE_SIZE);
4359                 if (!ctx) {
4360                         rc = -ENOMEM;
4361                         goto ctx_err;
4362                 }
4363                 memset(ctx, 0, total_alloc_len);
4364
4365                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4366                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4367                                     RTE_CACHE_LINE_SIZE);
4368                 if (!ctx_pg) {
4369                         rc = -ENOMEM;
4370                         goto ctx_err;
4371                 }
4372                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4373                         ctx->tqm_mem[i] = ctx_pg;
4374
4375                 bp->ctx = ctx;
4376                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4377                 ctx->qp_min_qp1_entries =
4378                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4379                 ctx->qp_max_l2_entries =
4380                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4381                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4382                 ctx->srq_max_l2_entries =
4383                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4384                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4385                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4386                 ctx->cq_max_l2_entries =
4387                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4388                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4389                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4390                 ctx->vnic_max_vnic_entries =
4391                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4392                 ctx->vnic_max_ring_table_entries =
4393                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4394                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4395                 ctx->stat_max_entries =
4396                         rte_le_to_cpu_32(resp->stat_max_entries);
4397                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4398                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4399                 ctx->tqm_min_entries_per_ring =
4400                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4401                 ctx->tqm_max_entries_per_ring =
4402                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4403                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4404                 if (!ctx->tqm_entries_multiple)
4405                         ctx->tqm_entries_multiple = 1;
4406                 ctx->mrav_max_entries =
4407                         rte_le_to_cpu_32(resp->mrav_max_entries);
4408                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4409                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4410                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4411         } else {
4412                 rc = 0;
4413         }
4414 ctx_err:
4415         HWRM_UNLOCK();
4416         return rc;
4417 }
4418
4419 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4420 {
4421         struct hwrm_func_backing_store_cfg_input req = {0};
4422         struct hwrm_func_backing_store_cfg_output *resp =
4423                 bp->hwrm_cmd_resp_addr;
4424         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4425         struct bnxt_ctx_pg_info *ctx_pg;
4426         uint32_t *num_entries;
4427         uint64_t *pg_dir;
4428         uint8_t *pg_attr;
4429         uint32_t ena;
4430         int i, rc;
4431
4432         if (!ctx)
4433                 return 0;
4434
4435         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4436         req.enables = rte_cpu_to_le_32(enables);
4437
4438         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4439                 ctx_pg = &ctx->qp_mem;
4440                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4441                 req.qp_num_qp1_entries =
4442                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4443                 req.qp_num_l2_entries =
4444                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4445                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4446                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4447                                       &req.qpc_pg_size_qpc_lvl,
4448                                       &req.qpc_page_dir);
4449         }
4450
4451         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4452                 ctx_pg = &ctx->srq_mem;
4453                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4454                 req.srq_num_l2_entries =
4455                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4456                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4457                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4458                                       &req.srq_pg_size_srq_lvl,
4459                                       &req.srq_page_dir);
4460         }
4461
4462         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4463                 ctx_pg = &ctx->cq_mem;
4464                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4465                 req.cq_num_l2_entries =
4466                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4467                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4468                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4469                                       &req.cq_pg_size_cq_lvl,
4470                                       &req.cq_page_dir);
4471         }
4472
4473         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4474                 ctx_pg = &ctx->vnic_mem;
4475                 req.vnic_num_vnic_entries =
4476                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4477                 req.vnic_num_ring_table_entries =
4478                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4479                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4480                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4481                                       &req.vnic_pg_size_vnic_lvl,
4482                                       &req.vnic_page_dir);
4483         }
4484
4485         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4486                 ctx_pg = &ctx->stat_mem;
4487                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4488                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4489                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4490                                       &req.stat_pg_size_stat_lvl,
4491                                       &req.stat_page_dir);
4492         }
4493
4494         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4495         num_entries = &req.tqm_sp_num_entries;
4496         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4497         pg_dir = &req.tqm_sp_page_dir;
4498         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4499         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4500                 if (!(enables & ena))
4501                         continue;
4502
4503                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4504
4505                 ctx_pg = ctx->tqm_mem[i];
4506                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4507                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4508         }
4509
4510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4511         HWRM_CHECK_RESULT();
4512         HWRM_UNLOCK();
4513
4514         return rc;
4515 }
4516
4517 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4518 {
4519         struct hwrm_port_qstats_ext_input req = {0};
4520         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4521         struct bnxt_pf_info *pf = &bp->pf;
4522         int rc;
4523
4524         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4525               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4526                 return 0;
4527
4528         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4529
4530         req.port_id = rte_cpu_to_le_16(pf->port_id);
4531         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4532                 req.tx_stat_host_addr =
4533                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4534                 req.tx_stat_size =
4535                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4536         }
4537         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4538                 req.rx_stat_host_addr =
4539                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4540                 req.rx_stat_size =
4541                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4542         }
4543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4544
4545         if (rc) {
4546                 bp->fw_rx_port_stats_ext_size = 0;
4547                 bp->fw_tx_port_stats_ext_size = 0;
4548         } else {
4549                 bp->fw_rx_port_stats_ext_size =
4550                         rte_le_to_cpu_16(resp->rx_stat_size);
4551                 bp->fw_tx_port_stats_ext_size =
4552                         rte_le_to_cpu_16(resp->tx_stat_size);
4553         }
4554
4555         HWRM_CHECK_RESULT();
4556         HWRM_UNLOCK();
4557
4558         return rc;
4559 }
4560
4561 int
4562 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4563 {
4564         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4565         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4566                 bp->hwrm_cmd_resp_addr;
4567         int rc = 0;
4568
4569         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4570         req.tunnel_type = type;
4571         req.dest_fid = bp->fw_fid;
4572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4573         HWRM_CHECK_RESULT();
4574
4575         HWRM_UNLOCK();
4576
4577         return rc;
4578 }
4579
4580 int
4581 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4582 {
4583         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4584         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4585                 bp->hwrm_cmd_resp_addr;
4586         int rc = 0;
4587
4588         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4589         req.tunnel_type = type;
4590         req.dest_fid = bp->fw_fid;
4591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4592         HWRM_CHECK_RESULT();
4593
4594         HWRM_UNLOCK();
4595
4596         return rc;
4597 }
4598
4599 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4600 {
4601         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4602         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4603                 bp->hwrm_cmd_resp_addr;
4604         int rc = 0;
4605
4606         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4607         req.src_fid = bp->fw_fid;
4608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4609         HWRM_CHECK_RESULT();
4610
4611         if (type)
4612                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4613
4614         HWRM_UNLOCK();
4615
4616         return rc;
4617 }
4618
4619 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4620                                    uint16_t *dst_fid)
4621 {
4622         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4623         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4624                 bp->hwrm_cmd_resp_addr;
4625         int rc = 0;
4626
4627         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4628         req.src_fid = bp->fw_fid;
4629         req.tunnel_type = tun_type;
4630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4631         HWRM_CHECK_RESULT();
4632
4633         if (dst_fid)
4634                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4635
4636         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4637
4638         HWRM_UNLOCK();
4639
4640         return rc;
4641 }
4642
4643 int bnxt_hwrm_set_mac(struct bnxt *bp)
4644 {
4645         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4646         struct hwrm_func_vf_cfg_input req = {0};
4647         int rc = 0;
4648
4649         if (!BNXT_VF(bp))
4650                 return 0;
4651
4652         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4653
4654         req.enables =
4655                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4656         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4657
4658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4659
4660         HWRM_CHECK_RESULT();
4661
4662         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4663         HWRM_UNLOCK();
4664
4665         return rc;
4666 }
4667
4668 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4669 {
4670         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4671         struct hwrm_func_drv_if_change_input req = {0};
4672         uint32_t flags;
4673         int rc;
4674
4675         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4676                 return 0;
4677
4678         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4679          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4680          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4681          */
4682         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4683                 return 0;
4684
4685         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4686
4687         if (up)
4688                 req.flags =
4689                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4690
4691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4692
4693         HWRM_CHECK_RESULT();
4694         flags = rte_le_to_cpu_32(resp->flags);
4695         HWRM_UNLOCK();
4696
4697         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4698                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4699                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4700         }
4701
4702         return 0;
4703 }