drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         } else {
 667                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 668         }
 669
 670         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 671                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 672         else
 673                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 674
 675         HWRM_UNLOCK();
 676
 677         return rc;
 678 }
 679
 680 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 681 {
 682         int rc;
 683
 684         rc = __bnxt_hwrm_func_qcaps(bp);
 685         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 686                 rc = bnxt_alloc_ctx_mem(bp);
 687                 if (rc)
 688                         return rc;
 689
 690                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 691                 if (!rc)
 692                         bp->flags |= BNXT_FLAG_NEW_RM;
 693         }
 694
 695         return rc;
 696 }
 697
 698 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 699 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 700 {
 701         int rc = 0;
 702         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 703         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 704
 705         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 706
 707         req.target_id = rte_cpu_to_le_16(0xffff);
 708
 709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 710
 711         HWRM_CHECK_RESULT();
 712
 713         if (rte_le_to_cpu_32(resp->flags) &
 714             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 715                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 716                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 717         }
 718
 719         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 720
 721         HWRM_UNLOCK();
 722
 723         return rc;
 724 }
 725
 726 int bnxt_hwrm_func_reset(struct bnxt *bp)
 727 {
 728         int rc = 0;
 729         struct hwrm_func_reset_input req = {.req_type = 0 };
 730         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 731
 732         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 733
 734         req.enables = rte_cpu_to_le_32(0);
 735
 736         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 737
 738         HWRM_CHECK_RESULT();
 739         HWRM_UNLOCK();
 740
 741         return rc;
 742 }
 743
 744 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 745 {
 746         int rc;
 747         uint32_t flags = 0;
 748         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 749         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         if (bp->flags & BNXT_FLAG_REGISTERED)
 752                 return 0;
 753
 754         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 755         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 756                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 757
 758         /* PFs and trusted VFs should indicate the support of the
 759          * Master capability on non Stingray platform
 760          */
 761         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 762                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 763
 764         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 765         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 766                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 767         req.ver_maj = RTE_VER_YEAR;
 768         req.ver_min = RTE_VER_MONTH;
 769         req.ver_upd = RTE_VER_MINOR;
 770
 771         if (BNXT_PF(bp)) {
 772                 req.enables |= rte_cpu_to_le_32(
 773                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 774                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 775                        RTE_MIN(sizeof(req.vf_req_fwd),
 776                                sizeof(bp->pf.vf_req_fwd)));
 777
 778                 /*
 779                  * PF can sniff HWRM API issued by VF. This can be set up by
 780                  * linux driver and inherited by the DPDK PF driver. Clear
 781                  * this HWRM sniffer list in FW because DPDK PF driver does
 782                  * not support this.
 783                  */
 784                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 785         }
 786
 787         req.flags = rte_cpu_to_le_32(flags);
 788
 789         req.async_event_fwd[0] |=
 790                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 791                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 792                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 793                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 794                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 795         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 796                 req.async_event_fwd[0] |=
 797                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 798         req.async_event_fwd[1] |=
 799                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 800                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 801
 802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 803
 804         HWRM_CHECK_RESULT();
 805
 806         flags = rte_le_to_cpu_32(resp->flags);
 807         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 808                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 809
 810         HWRM_UNLOCK();
 811
 812         bp->flags |= BNXT_FLAG_REGISTERED;
 813
 814         return rc;
 815 }
 816
 817 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 818 {
 819         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 820                 return 0;
 821
 822         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 823 }
 824
 825 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 826 {
 827         int rc;
 828         uint32_t flags = 0;
 829         uint32_t enables;
 830         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 831         struct hwrm_func_vf_cfg_input req = {0};
 832
 833         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 834
 835         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 836                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 838                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 839                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 840
 841         if (BNXT_HAS_RING_GRPS(bp)) {
 842                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 843                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 844         }
 845
 846         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 847         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 848                                             AGG_RING_MULTIPLIER);
 849         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 850         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 851                                               bp->tx_nr_rings +
 852                                               BNXT_NUM_ASYNC_CPR(bp));
 853         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 854         if (bp->vf_resv_strategy ==
 855             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 856                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 857                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 859                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 860                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 861                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 862         } else if (bp->vf_resv_strategy ==
 863                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 864                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 865                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 866         }
 867
 868         if (test)
 869                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 871                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 872                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 873                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 874                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 875
 876         if (test && BNXT_HAS_RING_GRPS(bp))
 877                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 878
 879         req.flags = rte_cpu_to_le_32(flags);
 880         req.enables |= rte_cpu_to_le_32(enables);
 881
 882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 883
 884         if (test)
 885                 HWRM_CHECK_RESULT_SILENT();
 886         else
 887                 HWRM_CHECK_RESULT();
 888
 889         HWRM_UNLOCK();
 890         return rc;
 891 }
 892
 893 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 894 {
 895         int rc;
 896         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 897         struct hwrm_func_resource_qcaps_input req = {0};
 898
 899         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 900         req.fid = rte_cpu_to_le_16(0xffff);
 901
 902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 903
 904         HWRM_CHECK_RESULT();
 905
 906         if (BNXT_VF(bp)) {
 907                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 908                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 909                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 910                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 911                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 912                 /* func_resource_qcaps does not return max_rx_em_flows.
 913                  * So use the value provided by func_qcaps.
 914                  */
 915                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 916                 if (!BNXT_CHIP_THOR(bp))
 917                         bp->max_l2_ctx += bp->max_rx_em_flows;
 918                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 919                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 920         }
 921         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 922         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 923         if (bp->vf_resv_strategy >
 924             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 925                 bp->vf_resv_strategy =
 926                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 927
 928         HWRM_UNLOCK();
 929         return rc;
 930 }
 931
 932 int bnxt_hwrm_ver_get(struct bnxt *bp)
 933 {
 934         int rc = 0;
 935         struct hwrm_ver_get_input req = {.req_type = 0 };
 936         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 937         uint32_t fw_version;
 938         uint16_t max_resp_len;
 939         char type[RTE_MEMZONE_NAMESIZE];
 940         uint32_t dev_caps_cfg;
 941
 942         bp->max_req_len = HWRM_MAX_REQ_LEN;
 943         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 944
 945         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 946         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 947         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 948
 949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 950
 951         if (bp->flags & BNXT_FLAG_FW_RESET)
 952                 HWRM_CHECK_RESULT_SILENT();
 953         else
 954                 HWRM_CHECK_RESULT();
 955
 956         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 957                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 958                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 959                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 960         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 961                      (resp->hwrm_fw_min_8b << 16) |
 962                      (resp->hwrm_fw_bld_8b << 8) |
 963                      resp->hwrm_fw_rsvd_8b;
 964         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 965                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 966
 967         fw_version = resp->hwrm_intf_maj_8b << 16;
 968         fw_version |= resp->hwrm_intf_min_8b << 8;
 969         fw_version |= resp->hwrm_intf_upd_8b;
 970         bp->hwrm_spec_code = fw_version;
 971
 972         /* def_req_timeout value is in milliseconds */
 973         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 974         /* convert timeout to usec */
 975         bp->hwrm_cmd_timeout *= 1000;
 976         if (!bp->hwrm_cmd_timeout)
 977                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 978
 979         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 980                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 981                 rc = -EINVAL;
 982                 goto error;
 983         }
 984
 985         if (bp->max_req_len > resp->max_req_win_len) {
 986                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 987                 rc = -EINVAL;
 988         }
 989         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 990         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 991         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 992                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 993
 994         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 995         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 996
 997         if (bp->max_resp_len != max_resp_len) {
 998                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 999                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1000                         bp->pdev->addr.devid, bp->pdev->addr.function);
1001
1002                 rte_free(bp->hwrm_cmd_resp_addr);
1003
1004                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1005                 if (bp->hwrm_cmd_resp_addr == NULL) {
1006                         rc = -ENOMEM;
1007                         goto error;
1008                 }
1009                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1010                 bp->hwrm_cmd_resp_dma_addr =
1011                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1012                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1013                         PMD_DRV_LOG(ERR,
1014                         "Unable to map response buffer to physical memory.\n");
1015                         rc = -ENOMEM;
1016                         goto error;
1017                 }
1018                 bp->max_resp_len = max_resp_len;
1019         }
1020
1021         if ((dev_caps_cfg &
1022                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1023             (dev_caps_cfg &
1024              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1025                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1026                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1027         }
1028
1029         if (((dev_caps_cfg &
1030               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1031              (dev_caps_cfg &
1032               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1033             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1034                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1035                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1036                         bp->pdev->addr.devid, bp->pdev->addr.function);
1037
1038                 rte_free(bp->hwrm_short_cmd_req_addr);
1039
1040                 bp->hwrm_short_cmd_req_addr =
1041                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1042                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1043                         rc = -ENOMEM;
1044                         goto error;
1045                 }
1046                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1047                 bp->hwrm_short_cmd_req_dma_addr =
1048                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1049                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1050                         rte_free(bp->hwrm_short_cmd_req_addr);
1051                         PMD_DRV_LOG(ERR,
1052                                 "Unable to map buffer to physical memory.\n");
1053                         rc = -ENOMEM;
1054                         goto error;
1055                 }
1056         }
1057         if (dev_caps_cfg &
1058             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1059                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1060                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1061         }
1062         if (dev_caps_cfg &
1063             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1064                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1065         if (dev_caps_cfg &
1066             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1067                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1068                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1069         }
1070
1071 error:
1072         HWRM_UNLOCK();
1073         return rc;
1074 }
1075
1076 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1077 {
1078         int rc;
1079         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1080         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1081
1082         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1083                 return 0;
1084
1085         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1086         req.flags = flags;
1087
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089
1090         HWRM_CHECK_RESULT();
1091         HWRM_UNLOCK();
1092
1093         return rc;
1094 }
1095
1096 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1097 {
1098         int rc = 0;
1099         struct hwrm_port_phy_cfg_input req = {0};
1100         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1101         uint32_t enables = 0;
1102
1103         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1104
1105         if (conf->link_up) {
1106                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1107                 if (bp->link_info.auto_mode && conf->link_speed) {
1108                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1109                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1110                 }
1111
1112                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1113                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1114                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1115                 /*
1116                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1117                  * any auto mode, even "none".
1118                  */
1119                 if (!conf->link_speed) {
1120                         /* No speeds specified. Enable AutoNeg - all speeds */
1121                         req.auto_mode =
1122                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1123                 }
1124                 /* AutoNeg - Advertise speeds specified. */
1125                 if (conf->auto_link_speed_mask &&
1126                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1127                         req.auto_mode =
1128                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1129                         req.auto_link_speed_mask =
1130                                 conf->auto_link_speed_mask;
1131                         enables |=
1132                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1133                 }
1134
1135                 req.auto_duplex = conf->duplex;
1136                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1137                 req.auto_pause = conf->auto_pause;
1138                 req.force_pause = conf->force_pause;
1139                 /* Set force_pause if there is no auto or if there is a force */
1140                 if (req.auto_pause && !req.force_pause)
1141                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1142                 else
1143                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1144
1145                 req.enables = rte_cpu_to_le_32(enables);
1146         } else {
1147                 req.flags =
1148                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1149                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1150         }
1151
1152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1153
1154         HWRM_CHECK_RESULT();
1155         HWRM_UNLOCK();
1156
1157         return rc;
1158 }
1159
1160 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1161                                    struct bnxt_link_info *link_info)
1162 {
1163         int rc = 0;
1164         struct hwrm_port_phy_qcfg_input req = {0};
1165         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1166
1167         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1168
1169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1170
1171         HWRM_CHECK_RESULT();
1172
1173         link_info->phy_link_status = resp->link;
1174         link_info->link_up =
1175                 (link_info->phy_link_status ==
1176                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1177         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1178         link_info->duplex = resp->duplex_cfg;
1179         link_info->pause = resp->pause;
1180         link_info->auto_pause = resp->auto_pause;
1181         link_info->force_pause = resp->force_pause;
1182         link_info->auto_mode = resp->auto_mode;
1183         link_info->phy_type = resp->phy_type;
1184         link_info->media_type = resp->media_type;
1185
1186         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1187         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1188         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1189         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1190         link_info->phy_ver[0] = resp->phy_maj;
1191         link_info->phy_ver[1] = resp->phy_min;
1192         link_info->phy_ver[2] = resp->phy_bld;
1193
1194         HWRM_UNLOCK();
1195
1196         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1197         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1198         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1199         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1200         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1201                     link_info->auto_link_speed_mask);
1202         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1203                     link_info->force_link_speed);
1204
1205         return rc;
1206 }
1207
1208 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1209 {
1210         int rc = 0;
1211         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1212         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1213         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1214         int i;
1215
1216 get_rx_info:
1217         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1218
1219         req.flags = rte_cpu_to_le_32(dir);
1220         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1221         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1222             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1223                 req.drv_qmap_cap =
1224                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1226
1227         HWRM_CHECK_RESULT();
1228
1229         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1230                 GET_TX_QUEUE_INFO(0);
1231                 GET_TX_QUEUE_INFO(1);
1232                 GET_TX_QUEUE_INFO(2);
1233                 GET_TX_QUEUE_INFO(3);
1234                 GET_TX_QUEUE_INFO(4);
1235                 GET_TX_QUEUE_INFO(5);
1236                 GET_TX_QUEUE_INFO(6);
1237                 GET_TX_QUEUE_INFO(7);
1238         } else  {
1239                 GET_RX_QUEUE_INFO(0);
1240                 GET_RX_QUEUE_INFO(1);
1241                 GET_RX_QUEUE_INFO(2);
1242                 GET_RX_QUEUE_INFO(3);
1243                 GET_RX_QUEUE_INFO(4);
1244                 GET_RX_QUEUE_INFO(5);
1245                 GET_RX_QUEUE_INFO(6);
1246                 GET_RX_QUEUE_INFO(7);
1247         }
1248
1249         HWRM_UNLOCK();
1250
1251         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1252                 goto done;
1253
1254         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1255                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1256         } else {
1257                 int j;
1258
1259                 /* iterate and find the COSq profile to use for Tx */
1260                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1261                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1262                                 if (bp->tx_cos_queue[i].id != 0xff)
1263                                         bp->tx_cosq_id[j++] =
1264                                                 bp->tx_cos_queue[i].id;
1265                         }
1266                 } else {
1267                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1268                                 if (bp->tx_cos_queue[i].profile ==
1269                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1270                                         bp->tx_cosq_id[0] =
1271                                                 bp->tx_cos_queue[i].id;
1272                                         break;
1273                                 }
1274                         }
1275                 }
1276         }
1277
1278         bp->max_tc = resp->max_configurable_queues;
1279         bp->max_lltc = resp->max_configurable_lossless_queues;
1280         if (bp->max_tc > BNXT_MAX_QUEUE)
1281                 bp->max_tc = BNXT_MAX_QUEUE;
1282         bp->max_q = bp->max_tc;
1283
1284         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1285                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1286                 goto get_rx_info;
1287         }
1288
1289 done:
1290         return rc;
1291 }
1292
1293 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1294                          struct bnxt_ring *ring,
1295                          uint32_t ring_type, uint32_t map_index,
1296                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1297                          uint16_t tx_cosq_id)
1298 {
1299         int rc = 0;
1300         uint32_t enables = 0;
1301         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1302         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1303         struct rte_mempool *mb_pool;
1304         uint16_t rx_buf_size;
1305
1306         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1307
1308         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1309         req.fbo = rte_cpu_to_le_32(0);
1310         /* Association of ring index with doorbell index */
1311         req.logical_id = rte_cpu_to_le_16(map_index);
1312         req.length = rte_cpu_to_le_32(ring->ring_size);
1313
1314         switch (ring_type) {
1315         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1316                 req.ring_type = ring_type;
1317                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1318                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1319                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1320                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1321                         enables |=
1322                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1323                 break;
1324         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1325                 req.ring_type = ring_type;
1326                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1327                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1328                 if (BNXT_CHIP_THOR(bp)) {
1329                         mb_pool = bp->rx_queues[0]->mb_pool;
1330                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1331                                       RTE_PKTMBUF_HEADROOM;
1332                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1333                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1334                         enables |=
1335                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1336                 }
1337                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1338                         enables |=
1339                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1340                 break;
1341         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1342                 req.ring_type = ring_type;
1343                 if (BNXT_HAS_NQ(bp)) {
1344                         /* Association of cp ring with nq */
1345                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1346                         enables |=
1347                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1348                 }
1349                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1350                 break;
1351         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1352                 req.ring_type = ring_type;
1353                 req.page_size = BNXT_PAGE_SHFT;
1354                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1355                 break;
1356         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1357                 req.ring_type = ring_type;
1358                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1359
1360                 mb_pool = bp->rx_queues[0]->mb_pool;
1361                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1362                               RTE_PKTMBUF_HEADROOM;
1363                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1364                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1365
1366                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1367                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1368                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1369                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1370                 break;
1371         default:
1372                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1373                         ring_type);
1374                 HWRM_UNLOCK();
1375                 return -EINVAL;
1376         }
1377         req.enables = rte_cpu_to_le_32(enables);
1378
1379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380
1381         if (rc || resp->error_code) {
1382                 if (rc == 0 && resp->error_code)
1383                         rc = rte_le_to_cpu_16(resp->error_code);
1384                 switch (ring_type) {
1385                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1386                         PMD_DRV_LOG(ERR,
1387                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1388                         HWRM_UNLOCK();
1389                         return rc;
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1391                         PMD_DRV_LOG(ERR,
1392                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1393                         HWRM_UNLOCK();
1394                         return rc;
1395                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1396                         PMD_DRV_LOG(ERR,
1397                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1398                                     rc);
1399                         HWRM_UNLOCK();
1400                         return rc;
1401                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1407                         PMD_DRV_LOG(ERR,
1408                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1409                         HWRM_UNLOCK();
1410                         return rc;
1411                 default:
1412                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1413                         HWRM_UNLOCK();
1414                         return rc;
1415                 }
1416         }
1417
1418         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1419         HWRM_UNLOCK();
1420         return rc;
1421 }
1422
1423 int bnxt_hwrm_ring_free(struct bnxt *bp,
1424                         struct bnxt_ring *ring, uint32_t ring_type)
1425 {
1426         int rc;
1427         struct hwrm_ring_free_input req = {.req_type = 0 };
1428         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1429
1430         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1431
1432         req.ring_type = ring_type;
1433         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1434
1435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1436
1437         if (rc || resp->error_code) {
1438                 if (rc == 0 && resp->error_code)
1439                         rc = rte_le_to_cpu_16(resp->error_code);
1440                 HWRM_UNLOCK();
1441
1442                 switch (ring_type) {
1443                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1444                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1445                                 rc);
1446                         return rc;
1447                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1448                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1449                                 rc);
1450                         return rc;
1451                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1452                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1453                                 rc);
1454                         return rc;
1455                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1456                         PMD_DRV_LOG(ERR,
1457                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1458                         return rc;
1459                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1460                         PMD_DRV_LOG(ERR,
1461                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1462                         return rc;
1463                 default:
1464                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1465                         return rc;
1466                 }
1467         }
1468         HWRM_UNLOCK();
1469         return 0;
1470 }
1471
1472 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1473 {
1474         int rc = 0;
1475         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1476         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1479
1480         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1481         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1482         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1483         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1484
1485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1486
1487         HWRM_CHECK_RESULT();
1488
1489         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1490
1491         HWRM_UNLOCK();
1492
1493         return rc;
1494 }
1495
1496 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1497 {
1498         int rc;
1499         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1500         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1501
1502         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1503
1504         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1505
1506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507
1508         HWRM_CHECK_RESULT();
1509         HWRM_UNLOCK();
1510
1511         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1512         return rc;
1513 }
1514
1515 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1516 {
1517         int rc = 0;
1518         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1519         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1520
1521         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1522                 return rc;
1523
1524         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1525
1526         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1527
1528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1529
1530         HWRM_CHECK_RESULT();
1531         HWRM_UNLOCK();
1532
1533         return rc;
1534 }
1535
1536 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1537                                 unsigned int idx __rte_unused)
1538 {
1539         int rc;
1540         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1541         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1542
1543         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1544
1545         req.update_period_ms = rte_cpu_to_le_32(0);
1546
1547         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1548
1549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1550
1551         HWRM_CHECK_RESULT();
1552
1553         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1554
1555         HWRM_UNLOCK();
1556
1557         return rc;
1558 }
1559
1560 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1561                                 unsigned int idx __rte_unused)
1562 {
1563         int rc;
1564         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1565         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1566
1567         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1568
1569         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1570
1571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1572
1573         HWRM_CHECK_RESULT();
1574         HWRM_UNLOCK();
1575
1576         return rc;
1577 }
1578
1579 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1580 {
1581         int rc = 0, i, j;
1582         struct hwrm_vnic_alloc_input req = { 0 };
1583         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1584
1585         if (!BNXT_HAS_RING_GRPS(bp))
1586                 goto skip_ring_grps;
1587
1588         /* map ring groups to this vnic */
1589         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1590                 vnic->start_grp_id, vnic->end_grp_id);
1591         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1592                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1593
1594         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1595         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1596         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1597         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1598
1599 skip_ring_grps:
1600         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1601         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1602
1603         if (vnic->func_default)
1604                 req.flags =
1605                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1607
1608         HWRM_CHECK_RESULT();
1609
1610         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1611         HWRM_UNLOCK();
1612         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1613         return rc;
1614 }
1615
1616 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1617                                         struct bnxt_vnic_info *vnic,
1618                                         struct bnxt_plcmodes_cfg *pmode)
1619 {
1620         int rc = 0;
1621         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1622         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1623
1624         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1625
1626         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1627
1628         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1629
1630         HWRM_CHECK_RESULT();
1631
1632         pmode->flags = rte_le_to_cpu_32(resp->flags);
1633         /* dflt_vnic bit doesn't exist in the _cfg command */
1634         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1635         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1636         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1637         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1638
1639         HWRM_UNLOCK();
1640
1641         return rc;
1642 }
1643
1644 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1645                                        struct bnxt_vnic_info *vnic,
1646                                        struct bnxt_plcmodes_cfg *pmode)
1647 {
1648         int rc = 0;
1649         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1650         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1651
1652         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1653                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1654                 return rc;
1655         }
1656
1657         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1658
1659         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1660         req.flags = rte_cpu_to_le_32(pmode->flags);
1661         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1662         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1663         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1664         req.enables = rte_cpu_to_le_32(
1665             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1666             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1667             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1668         );
1669
1670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1671
1672         HWRM_CHECK_RESULT();
1673         HWRM_UNLOCK();
1674
1675         return rc;
1676 }
1677
1678 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1679 {
1680         int rc = 0;
1681         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1682         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1683         struct bnxt_plcmodes_cfg pmodes = { 0 };
1684         uint32_t ctx_enable_flag = 0;
1685         uint32_t enables = 0;
1686
1687         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1688                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1689                 return rc;
1690         }
1691
1692         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1693         if (rc)
1694                 return rc;
1695
1696         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1697
1698         if (BNXT_CHIP_THOR(bp)) {
1699                 int dflt_rxq = vnic->start_grp_id;
1700                 struct bnxt_rx_ring_info *rxr;
1701                 struct bnxt_cp_ring_info *cpr;
1702                 struct bnxt_rx_queue *rxq;
1703                 int i;
1704
1705                 /*
1706                  * The first active receive ring is used as the VNIC
1707                  * default receive ring. If there are no active receive
1708                  * rings (all corresponding receive queues are stopped),
1709                  * the first receive ring is used.
1710                  */
1711                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1712                         rxq = bp->eth_dev->data->rx_queues[i];
1713                         if (rxq->rx_started) {
1714                                 dflt_rxq = i;
1715                                 break;
1716                         }
1717                 }
1718
1719                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1720                 rxr = rxq->rx_ring;
1721                 cpr = rxq->cp_ring;
1722
1723                 req.default_rx_ring_id =
1724                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1725                 req.default_cmpl_ring_id =
1726                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1727                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1728                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1729                 goto config_mru;
1730         }
1731
1732         /* Only RSS support for now TBD: COS & LB */
1733         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1734         if (vnic->lb_rule != 0xffff)
1735                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1736         if (vnic->cos_rule != 0xffff)
1737                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1738         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1739                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1740                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1741         }
1742         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1743                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1744                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1745         }
1746
1747         enables |= ctx_enable_flag;
1748         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1749         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1750         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1751         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1752
1753 config_mru:
1754         req.enables = rte_cpu_to_le_32(enables);
1755         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1756         req.mru = rte_cpu_to_le_16(vnic->mru);
1757         /* Configure default VNIC only once. */
1758         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1759                 req.flags |=
1760                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1761                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1762         }
1763         if (vnic->vlan_strip)
1764                 req.flags |=
1765                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1766         if (vnic->bd_stall)
1767                 req.flags |=
1768                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1769         if (vnic->roce_dual)
1770                 req.flags |= rte_cpu_to_le_32(
1771                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1772         if (vnic->roce_only)
1773                 req.flags |= rte_cpu_to_le_32(
1774                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1775         if (vnic->rss_dflt_cr)
1776                 req.flags |= rte_cpu_to_le_32(
1777                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1778
1779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1780
1781         HWRM_CHECK_RESULT();
1782         HWRM_UNLOCK();
1783
1784         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1785
1786         return rc;
1787 }
1788
1789 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1790                 int16_t fw_vf_id)
1791 {
1792         int rc = 0;
1793         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1794         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1795
1796         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1797                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1798                 return rc;
1799         }
1800         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1801
1802         req.enables =
1803                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1804         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1805         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1806
1807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1808
1809         HWRM_CHECK_RESULT();
1810
1811         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1812         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1813         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1814         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1815         vnic->mru = rte_le_to_cpu_16(resp->mru);
1816         vnic->func_default = rte_le_to_cpu_32(
1817                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1818         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1819                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1820         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1821                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1822         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1823                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1824         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1825                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1826         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1827                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1828
1829         HWRM_UNLOCK();
1830
1831         return rc;
1832 }
1833
1834 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1835                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1836 {
1837         int rc = 0;
1838         uint16_t ctx_id;
1839         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1840         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1841                                                 bp->hwrm_cmd_resp_addr;
1842
1843         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1844
1845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1846         HWRM_CHECK_RESULT();
1847
1848         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1849         if (!BNXT_HAS_RING_GRPS(bp))
1850                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1851         else if (ctx_idx == 0)
1852                 vnic->rss_rule = ctx_id;
1853
1854         HWRM_UNLOCK();
1855
1856         return rc;
1857 }
1858
1859 static
1860 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1861                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1862 {
1863         int rc = 0;
1864         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1865         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1866                                                 bp->hwrm_cmd_resp_addr;
1867
1868         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1869                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1870                 return rc;
1871         }
1872         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1873
1874         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1875
1876         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1877
1878         HWRM_CHECK_RESULT();
1879         HWRM_UNLOCK();
1880
1881         return rc;
1882 }
1883
1884 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1885 {
1886         int rc = 0;
1887
1888         if (BNXT_CHIP_THOR(bp)) {
1889                 int j;
1890
1891                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1892                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1893                                                       vnic,
1894                                                       vnic->fw_grp_ids[j]);
1895                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1896                 }
1897                 vnic->num_lb_ctxts = 0;
1898         } else {
1899                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1900                 vnic->rss_rule = INVALID_HW_RING_ID;
1901         }
1902
1903         return rc;
1904 }
1905
1906 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1907 {
1908         int rc = 0;
1909         struct hwrm_vnic_free_input req = {.req_type = 0 };
1910         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1911
1912         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1913                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1914                 return rc;
1915         }
1916
1917         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1918
1919         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1920
1921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922
1923         HWRM_CHECK_RESULT();
1924         HWRM_UNLOCK();
1925
1926         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1927         /* Configure default VNIC again if necessary. */
1928         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1929                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1930
1931         return rc;
1932 }
1933
1934 static int
1935 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1936 {
1937         int i;
1938         int rc = 0;
1939         int nr_ctxs = vnic->num_lb_ctxts;
1940         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1941         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1942
1943         for (i = 0; i < nr_ctxs; i++) {
1944                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1945
1946                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1947                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1948                 req.hash_mode_flags = vnic->hash_mode;
1949
1950                 req.hash_key_tbl_addr =
1951                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1952
1953                 req.ring_grp_tbl_addr =
1954                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1955                                          i * HW_HASH_INDEX_SIZE);
1956                 req.ring_table_pair_index = i;
1957                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1958
1959                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1960                                             BNXT_USE_CHIMP_MB);
1961
1962                 HWRM_CHECK_RESULT();
1963                 HWRM_UNLOCK();
1964         }
1965
1966         return rc;
1967 }
1968
1969 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1970                            struct bnxt_vnic_info *vnic)
1971 {
1972         int rc = 0;
1973         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1974         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1975
1976         if (!vnic->rss_table)
1977                 return 0;
1978
1979         if (BNXT_CHIP_THOR(bp))
1980                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1981
1982         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1983
1984         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1985         req.hash_mode_flags = vnic->hash_mode;
1986
1987         req.ring_grp_tbl_addr =
1988             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1989         req.hash_key_tbl_addr =
1990             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1991         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1992         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993
1994         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1995
1996         HWRM_CHECK_RESULT();
1997         HWRM_UNLOCK();
1998
1999         return rc;
2000 }
2001
2002 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2003                         struct bnxt_vnic_info *vnic)
2004 {
2005         int rc = 0;
2006         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2007         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2008         uint16_t size;
2009
2010         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2011                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2012                 return rc;
2013         }
2014
2015         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2016
2017         req.flags = rte_cpu_to_le_32(
2018                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2019
2020         req.enables = rte_cpu_to_le_32(
2021                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2022
2023         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2024         size -= RTE_PKTMBUF_HEADROOM;
2025         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2026
2027         req.jumbo_thresh = rte_cpu_to_le_16(size);
2028         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2029
2030         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2031
2032         HWRM_CHECK_RESULT();
2033         HWRM_UNLOCK();
2034
2035         return rc;
2036 }
2037
2038 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2039                         struct bnxt_vnic_info *vnic, bool enable)
2040 {
2041         int rc = 0;
2042         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2043         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2044
2045         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2046                 if (enable)
2047                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2048                 return -ENOTSUP;
2049         }
2050
2051         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2052                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2053                 return 0;
2054         }
2055
2056         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2057
2058         if (enable) {
2059                 req.enables = rte_cpu_to_le_32(
2060                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2061                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2062                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2063                 req.flags = rte_cpu_to_le_32(
2064                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2065                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2066                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2067                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2068                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2069                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2070                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2071                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2072                 req.min_agg_len = rte_cpu_to_le_32(512);
2073         }
2074         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077
2078         HWRM_CHECK_RESULT();
2079         HWRM_UNLOCK();
2080
2081         return rc;
2082 }
2083
2084 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2085 {
2086         struct hwrm_func_cfg_input req = {0};
2087         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2088         int rc;
2089
2090         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2091         req.enables = rte_cpu_to_le_32(
2092                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2093         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2094         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2095
2096         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2097
2098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2099         HWRM_CHECK_RESULT();
2100         HWRM_UNLOCK();
2101
2102         bp->pf.vf_info[vf].random_mac = false;
2103
2104         return rc;
2105 }
2106
2107 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2108                                   uint64_t *dropped)
2109 {
2110         int rc = 0;
2111         struct hwrm_func_qstats_input req = {.req_type = 0};
2112         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2113
2114         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2115
2116         req.fid = rte_cpu_to_le_16(fid);
2117
2118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2119
2120         HWRM_CHECK_RESULT();
2121
2122         if (dropped)
2123                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2124
2125         HWRM_UNLOCK();
2126
2127         return rc;
2128 }
2129
2130 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2131                           struct rte_eth_stats *stats)
2132 {
2133         int rc = 0;
2134         struct hwrm_func_qstats_input req = {.req_type = 0};
2135         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2136
2137         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2138
2139         req.fid = rte_cpu_to_le_16(fid);
2140
2141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2142
2143         HWRM_CHECK_RESULT();
2144
2145         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2146         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2147         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2148         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2149         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2150         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2151
2152         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2153         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2154         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2155         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2156         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2157         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2158
2159         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2160         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2161         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2162
2163         HWRM_UNLOCK();
2164
2165         return rc;
2166 }
2167
2168 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2169 {
2170         int rc = 0;
2171         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2172         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2173
2174         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2175
2176         req.fid = rte_cpu_to_le_16(fid);
2177
2178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2179
2180         HWRM_CHECK_RESULT();
2181         HWRM_UNLOCK();
2182
2183         return rc;
2184 }
2185
2186 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2187 {
2188         unsigned int i;
2189         int rc = 0;
2190
2191         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2192                 struct bnxt_tx_queue *txq;
2193                 struct bnxt_rx_queue *rxq;
2194                 struct bnxt_cp_ring_info *cpr;
2195
2196                 if (i >= bp->rx_cp_nr_rings) {
2197                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2198                         cpr = txq->cp_ring;
2199                 } else {
2200                         rxq = bp->rx_queues[i];
2201                         cpr = rxq->cp_ring;
2202                 }
2203
2204                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2205                 if (rc)
2206                         return rc;
2207         }
2208         return 0;
2209 }
2210
2211 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2212 {
2213         int rc;
2214         unsigned int i;
2215         struct bnxt_cp_ring_info *cpr;
2216
2217         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2218
2219                 if (i >= bp->rx_cp_nr_rings) {
2220                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2221                 } else {
2222                         cpr = bp->rx_queues[i]->cp_ring;
2223                         if (BNXT_HAS_RING_GRPS(bp))
2224                                 bp->grp_info[i].fw_stats_ctx = -1;
2225                 }
2226                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2227                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2228                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2229                         if (rc)
2230                                 return rc;
2231                 }
2232         }
2233         return 0;
2234 }
2235
2236 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2237 {
2238         unsigned int i;
2239         int rc = 0;
2240
2241         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2242                 struct bnxt_tx_queue *txq;
2243                 struct bnxt_rx_queue *rxq;
2244                 struct bnxt_cp_ring_info *cpr;
2245
2246                 if (i >= bp->rx_cp_nr_rings) {
2247                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2248                         cpr = txq->cp_ring;
2249                 } else {
2250                         rxq = bp->rx_queues[i];
2251                         cpr = rxq->cp_ring;
2252                 }
2253
2254                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2255
2256                 if (rc)
2257                         return rc;
2258         }
2259         return rc;
2260 }
2261
2262 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2263 {
2264         uint16_t idx;
2265         uint32_t rc = 0;
2266
2267         if (!BNXT_HAS_RING_GRPS(bp))
2268                 return 0;
2269
2270         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2271
2272                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2273                         continue;
2274
2275                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2276
2277                 if (rc)
2278                         return rc;
2279         }
2280         return rc;
2281 }
2282
2283 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2284 {
2285         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2286
2287         bnxt_hwrm_ring_free(bp, cp_ring,
2288                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2289         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2290         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2291                                      sizeof(*cpr->cp_desc_ring));
2292         cpr->cp_raw_cons = 0;
2293         cpr->valid = 0;
2294 }
2295
2296 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2297 {
2298         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2299
2300         bnxt_hwrm_ring_free(bp, cp_ring,
2301                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2302         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2303         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2304                         sizeof(*cpr->cp_desc_ring));
2305         cpr->cp_raw_cons = 0;
2306         cpr->valid = 0;
2307 }
2308
2309 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2310 {
2311         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2312         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2313         struct bnxt_ring *ring = rxr->rx_ring_struct;
2314         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2315
2316         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2317                 bnxt_hwrm_ring_free(bp, ring,
2318                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2319                 ring->fw_ring_id = INVALID_HW_RING_ID;
2320                 if (BNXT_HAS_RING_GRPS(bp))
2321                         bp->grp_info[queue_index].rx_fw_ring_id =
2322                                                         INVALID_HW_RING_ID;
2323                 memset(rxr->rx_desc_ring, 0,
2324                        rxr->rx_ring_struct->ring_size *
2325                        sizeof(*rxr->rx_desc_ring));
2326                 memset(rxr->rx_buf_ring, 0,
2327                        rxr->rx_ring_struct->ring_size *
2328                        sizeof(*rxr->rx_buf_ring));
2329                 rxr->rx_prod = 0;
2330         }
2331         ring = rxr->ag_ring_struct;
2332         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2333                 bnxt_hwrm_ring_free(bp, ring,
2334                                     BNXT_CHIP_THOR(bp) ?
2335                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2336                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2337                 ring->fw_ring_id = INVALID_HW_RING_ID;
2338                 memset(rxr->ag_buf_ring, 0,
2339                        rxr->ag_ring_struct->ring_size *
2340                        sizeof(*rxr->ag_buf_ring));
2341                 rxr->ag_prod = 0;
2342                 if (BNXT_HAS_RING_GRPS(bp))
2343                         bp->grp_info[queue_index].ag_fw_ring_id =
2344                                                         INVALID_HW_RING_ID;
2345         }
2346         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2347                 bnxt_free_cp_ring(bp, cpr);
2348
2349         if (BNXT_HAS_RING_GRPS(bp))
2350                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2351 }
2352
2353 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2354 {
2355         unsigned int i;
2356
2357         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2358                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2359                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2360                 struct bnxt_ring *ring = txr->tx_ring_struct;
2361                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2362
2363                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2364                         bnxt_hwrm_ring_free(bp, ring,
2365                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2366                         ring->fw_ring_id = INVALID_HW_RING_ID;
2367                         memset(txr->tx_desc_ring, 0,
2368                                         txr->tx_ring_struct->ring_size *
2369                                         sizeof(*txr->tx_desc_ring));
2370                         memset(txr->tx_buf_ring, 0,
2371                                         txr->tx_ring_struct->ring_size *
2372                                         sizeof(*txr->tx_buf_ring));
2373                         txr->tx_prod = 0;
2374                         txr->tx_cons = 0;
2375                 }
2376                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2377                         bnxt_free_cp_ring(bp, cpr);
2378                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2379                 }
2380         }
2381
2382         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2383                 bnxt_free_hwrm_rx_ring(bp, i);
2384
2385         return 0;
2386 }
2387
2388 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2389 {
2390         uint16_t i;
2391         uint32_t rc = 0;
2392
2393         if (!BNXT_HAS_RING_GRPS(bp))
2394                 return 0;
2395
2396         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2397                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2398                 if (rc)
2399                         return rc;
2400         }
2401         return rc;
2402 }
2403
2404 /*
2405  * HWRM utility functions
2406  */
2407
2408 void bnxt_free_hwrm_resources(struct bnxt *bp)
2409 {
2410         /* Release memzone */
2411         rte_free(bp->hwrm_cmd_resp_addr);
2412         rte_free(bp->hwrm_short_cmd_req_addr);
2413         bp->hwrm_cmd_resp_addr = NULL;
2414         bp->hwrm_short_cmd_req_addr = NULL;
2415         bp->hwrm_cmd_resp_dma_addr = 0;
2416         bp->hwrm_short_cmd_req_dma_addr = 0;
2417 }
2418
2419 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2420 {
2421         struct rte_pci_device *pdev = bp->pdev;
2422         char type[RTE_MEMZONE_NAMESIZE];
2423
2424         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2425                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2426         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2427         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2428         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2429         if (bp->hwrm_cmd_resp_addr == NULL)
2430                 return -ENOMEM;
2431         bp->hwrm_cmd_resp_dma_addr =
2432                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2433         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2434                 PMD_DRV_LOG(ERR,
2435                         "unable to map response address to physical memory\n");
2436                 return -ENOMEM;
2437         }
2438         rte_spinlock_init(&bp->hwrm_lock);
2439
2440         return 0;
2441 }
2442
2443 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2444 {
2445         struct bnxt_filter_info *filter;
2446         int rc = 0;
2447
2448         STAILQ_FOREACH(filter, &vnic->filter, next) {
2449                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2450                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2451                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2452                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2453                 else
2454                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2455                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2456                 bnxt_free_filter(bp, filter);
2457         }
2458         return rc;
2459 }
2460
2461 static int
2462 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2463 {
2464         struct bnxt_filter_info *filter;
2465         struct rte_flow *flow;
2466         int rc = 0;
2467
2468         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2469                 flow = STAILQ_FIRST(&vnic->flow_list);
2470                 filter = flow->filter;
2471                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2472                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2473                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2474                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2475                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2476                 else
2477                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2478
2479                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2480                 rte_free(flow);
2481         }
2482         return rc;
2483 }
2484
2485 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2486 {
2487         struct bnxt_filter_info *filter;
2488         int rc = 0;
2489
2490         STAILQ_FOREACH(filter, &vnic->filter, next) {
2491                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2492                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2493                                                      filter);
2494                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2495                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2496                                                          filter);
2497                 else
2498                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2499                                                      filter);
2500                 if (rc)
2501                         break;
2502         }
2503         return rc;
2504 }
2505
2506 void bnxt_free_tunnel_ports(struct bnxt *bp)
2507 {
2508         if (bp->vxlan_port_cnt)
2509                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2510                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2511         bp->vxlan_port = 0;
2512         if (bp->geneve_port_cnt)
2513                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2514                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2515         bp->geneve_port = 0;
2516 }
2517
2518 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2519 {
2520         int i;
2521
2522         if (bp->vnic_info == NULL)
2523                 return;
2524
2525         /*
2526          * Cleanup VNICs in reverse order, to make sure the L2 filter
2527          * from vnic0 is last to be cleaned up.
2528          */
2529         for (i = bp->max_vnics - 1; i >= 0; i--) {
2530                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2531
2532                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2533                         continue;
2534
2535                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2536
2537                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2538
2539                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2540
2541                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2542
2543                 bnxt_hwrm_vnic_free(bp, vnic);
2544
2545                 rte_free(vnic->fw_grp_ids);
2546         }
2547         /* Ring resources */
2548         bnxt_free_all_hwrm_rings(bp);
2549         bnxt_free_all_hwrm_ring_grps(bp);
2550         bnxt_free_all_hwrm_stat_ctxs(bp);
2551         bnxt_free_tunnel_ports(bp);
2552 }
2553
2554 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2555 {
2556         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2557
2558         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2559                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2560
2561         switch (conf_link_speed) {
2562         case ETH_LINK_SPEED_10M_HD:
2563         case ETH_LINK_SPEED_100M_HD:
2564                 /* FALLTHROUGH */
2565                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2566         }
2567         return hw_link_duplex;
2568 }
2569
2570 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2571 {
2572         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2573 }
2574
2575 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2576 {
2577         uint16_t eth_link_speed = 0;
2578
2579         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2580                 return ETH_LINK_SPEED_AUTONEG;
2581
2582         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2583         case ETH_LINK_SPEED_100M:
2584         case ETH_LINK_SPEED_100M_HD:
2585                 /* FALLTHROUGH */
2586                 eth_link_speed =
2587                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2588                 break;
2589         case ETH_LINK_SPEED_1G:
2590                 eth_link_speed =
2591                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2592                 break;
2593         case ETH_LINK_SPEED_2_5G:
2594                 eth_link_speed =
2595                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2596                 break;
2597         case ETH_LINK_SPEED_10G:
2598                 eth_link_speed =
2599                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2600                 break;
2601         case ETH_LINK_SPEED_20G:
2602                 eth_link_speed =
2603                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2604                 break;
2605         case ETH_LINK_SPEED_25G:
2606                 eth_link_speed =
2607                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2608                 break;
2609         case ETH_LINK_SPEED_40G:
2610                 eth_link_speed =
2611                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2612                 break;
2613         case ETH_LINK_SPEED_50G:
2614                 eth_link_speed =
2615                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2616                 break;
2617         case ETH_LINK_SPEED_100G:
2618                 eth_link_speed =
2619                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2620                 break;
2621         default:
2622                 PMD_DRV_LOG(ERR,
2623                         "Unsupported link speed %d; default to AUTO\n",
2624                         conf_link_speed);
2625                 break;
2626         }
2627         return eth_link_speed;
2628 }
2629
2630 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2631                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2632                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2633                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2634
2635 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2636 {
2637         uint32_t one_speed;
2638
2639         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2640                 return 0;
2641
2642         if (link_speed & ETH_LINK_SPEED_FIXED) {
2643                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2644
2645                 if (one_speed & (one_speed - 1)) {
2646                         PMD_DRV_LOG(ERR,
2647                                 "Invalid advertised speeds (%u) for port %u\n",
2648                                 link_speed, port_id);
2649                         return -EINVAL;
2650                 }
2651                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2652                         PMD_DRV_LOG(ERR,
2653                                 "Unsupported advertised speed (%u) for port %u\n",
2654                                 link_speed, port_id);
2655                         return -EINVAL;
2656                 }
2657         } else {
2658                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2659                         PMD_DRV_LOG(ERR,
2660                                 "Unsupported advertised speeds (%u) for port %u\n",
2661                                 link_speed, port_id);
2662                         return -EINVAL;
2663                 }
2664         }
2665         return 0;
2666 }
2667
2668 static uint16_t
2669 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2670 {
2671         uint16_t ret = 0;
2672
2673         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2674                 if (bp->link_info.support_speeds)
2675                         return bp->link_info.support_speeds;
2676                 link_speed = BNXT_SUPPORTED_SPEEDS;
2677         }
2678
2679         if (link_speed & ETH_LINK_SPEED_100M)
2680                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2681         if (link_speed & ETH_LINK_SPEED_100M_HD)
2682                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2683         if (link_speed & ETH_LINK_SPEED_1G)
2684                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2685         if (link_speed & ETH_LINK_SPEED_2_5G)
2686                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2687         if (link_speed & ETH_LINK_SPEED_10G)
2688                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2689         if (link_speed & ETH_LINK_SPEED_20G)
2690                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2691         if (link_speed & ETH_LINK_SPEED_25G)
2692                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2693         if (link_speed & ETH_LINK_SPEED_40G)
2694                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2695         if (link_speed & ETH_LINK_SPEED_50G)
2696                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2697         if (link_speed & ETH_LINK_SPEED_100G)
2698                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2699         return ret;
2700 }
2701
2702 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2703 {
2704         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2705
2706         switch (hw_link_speed) {
2707         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2708                 eth_link_speed = ETH_SPEED_NUM_100M;
2709                 break;
2710         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2711                 eth_link_speed = ETH_SPEED_NUM_1G;
2712                 break;
2713         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2714                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2715                 break;
2716         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2717                 eth_link_speed = ETH_SPEED_NUM_10G;
2718                 break;
2719         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2720                 eth_link_speed = ETH_SPEED_NUM_20G;
2721                 break;
2722         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2723                 eth_link_speed = ETH_SPEED_NUM_25G;
2724                 break;
2725         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2726                 eth_link_speed = ETH_SPEED_NUM_40G;
2727                 break;
2728         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2729                 eth_link_speed = ETH_SPEED_NUM_50G;
2730                 break;
2731         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2732                 eth_link_speed = ETH_SPEED_NUM_100G;
2733                 break;
2734         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2735         default:
2736                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2737                         hw_link_speed);
2738                 break;
2739         }
2740         return eth_link_speed;
2741 }
2742
2743 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2744 {
2745         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2746
2747         switch (hw_link_duplex) {
2748         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2749         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2750                 /* FALLTHROUGH */
2751                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2752                 break;
2753         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2754                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2755                 break;
2756         default:
2757                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2758                         hw_link_duplex);
2759                 break;
2760         }
2761         return eth_link_duplex;
2762 }
2763
2764 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2765 {
2766         int rc = 0;
2767         struct bnxt_link_info *link_info = &bp->link_info;
2768
2769         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2770         if (rc) {
2771                 PMD_DRV_LOG(ERR,
2772                         "Get link config failed with rc %d\n", rc);
2773                 goto exit;
2774         }
2775         if (link_info->link_speed)
2776                 link->link_speed =
2777                         bnxt_parse_hw_link_speed(link_info->link_speed);
2778         else
2779                 link->link_speed = ETH_SPEED_NUM_NONE;
2780         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2781         link->link_status = link_info->link_up;
2782         link->link_autoneg = link_info->auto_mode ==
2783                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2784                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2785 exit:
2786         return rc;
2787 }
2788
2789 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2790 {
2791         int rc = 0;
2792         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2793         struct bnxt_link_info link_req;
2794         uint16_t speed, autoneg;
2795
2796         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2797                 return 0;
2798
2799         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2800                         bp->eth_dev->data->port_id);
2801         if (rc)
2802                 goto error;
2803
2804         memset(&link_req, 0, sizeof(link_req));
2805         link_req.link_up = link_up;
2806         if (!link_up)
2807                 goto port_phy_cfg;
2808
2809         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2810         if (BNXT_CHIP_THOR(bp) &&
2811             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2812                 /* 40G is not supported as part of media auto detect.
2813                  * The speed should be forced and autoneg disabled
2814                  * to configure 40G speed.
2815                  */
2816                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2817                 autoneg = 0;
2818         }
2819
2820         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2821         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2822         /* Autoneg can be done only when the FW allows.
2823          * When user configures fixed speed of 40G and later changes to
2824          * any other speed, auto_link_speed/force_link_speed is still set
2825          * to 40G until link comes up at new speed.
2826          */
2827         if (autoneg == 1 &&
2828             !(!BNXT_CHIP_THOR(bp) &&
2829               (bp->link_info.auto_link_speed ||
2830                bp->link_info.force_link_speed))) {
2831                 link_req.phy_flags |=
2832                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2833                 link_req.auto_link_speed_mask =
2834                         bnxt_parse_eth_link_speed_mask(bp,
2835                                                        dev_conf->link_speeds);
2836         } else {
2837                 if (bp->link_info.phy_type ==
2838                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2839                     bp->link_info.phy_type ==
2840                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2841                     bp->link_info.media_type ==
2842                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2843                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2844                         return -EINVAL;
2845                 }
2846
2847                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2848                 /* If user wants a particular speed try that first. */
2849                 if (speed)
2850                         link_req.link_speed = speed;
2851                 else if (bp->link_info.force_link_speed)
2852                         link_req.link_speed = bp->link_info.force_link_speed;
2853                 else
2854                         link_req.link_speed = bp->link_info.auto_link_speed;
2855         }
2856         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2857         link_req.auto_pause = bp->link_info.auto_pause;
2858         link_req.force_pause = bp->link_info.force_pause;
2859
2860 port_phy_cfg:
2861         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2862         if (rc) {
2863                 PMD_DRV_LOG(ERR,
2864                         "Set link config failed with rc %d\n", rc);
2865         }
2866
2867 error:
2868         return rc;
2869 }
2870
2871 /* JIRA 22088 */
2872 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2873 {
2874         struct hwrm_func_qcfg_input req = {0};
2875         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2876         uint16_t flags;
2877         int rc = 0;
2878
2879         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2880         req.fid = rte_cpu_to_le_16(0xffff);
2881
2882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2883
2884         HWRM_CHECK_RESULT();
2885
2886         /* Hard Coded.. 0xfff VLAN ID mask */
2887         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2888         flags = rte_le_to_cpu_16(resp->flags);
2889         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2890                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2891
2892         if (BNXT_VF(bp) &&
2893             !BNXT_VF_IS_TRUSTED(bp) &&
2894             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2895                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2896                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2897         } else if (BNXT_VF(bp) &&
2898                    BNXT_VF_IS_TRUSTED(bp) &&
2899                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2900                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2901                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2902         }
2903
2904         if (mtu)
2905                 *mtu = rte_le_to_cpu_16(resp->mtu);
2906
2907         switch (resp->port_partition_type) {
2908         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2909         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2910         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2911                 /* FALLTHROUGH */
2912                 bp->port_partition_type = resp->port_partition_type;
2913                 break;
2914         default:
2915                 bp->port_partition_type = 0;
2916                 break;
2917         }
2918
2919         HWRM_UNLOCK();
2920
2921         return rc;
2922 }
2923
2924 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2925                                    struct hwrm_func_qcaps_output *qcaps)
2926 {
2927         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2928         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2929                sizeof(qcaps->mac_address));
2930         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2931         qcaps->max_rx_rings = fcfg->num_rx_rings;
2932         qcaps->max_tx_rings = fcfg->num_tx_rings;
2933         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2934         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2935         qcaps->max_vfs = 0;
2936         qcaps->first_vf_id = 0;
2937         qcaps->max_vnics = fcfg->num_vnics;
2938         qcaps->max_decap_records = 0;
2939         qcaps->max_encap_records = 0;
2940         qcaps->max_tx_wm_flows = 0;
2941         qcaps->max_tx_em_flows = 0;
2942         qcaps->max_rx_wm_flows = 0;
2943         qcaps->max_rx_em_flows = 0;
2944         qcaps->max_flow_id = 0;
2945         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2946         qcaps->max_sp_tx_rings = 0;
2947         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2948 }
2949
2950 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2951 {
2952         struct hwrm_func_cfg_input req = {0};
2953         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2954         uint32_t enables;
2955         int rc;
2956
2957         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2958                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2959                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2960                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2961                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2962                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2963                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2964                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2965                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2966
2967         if (BNXT_HAS_RING_GRPS(bp)) {
2968                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2969                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2970         } else if (BNXT_HAS_NQ(bp)) {
2971                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2972                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2973         }
2974
2975         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2976         req.mtu = rte_cpu_to_le_16(RTE_MIN(bp->eth_dev->data->mtu,
2977                                            BNXT_MAX_MTU)); //FW adds hdr sizes
2978         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2979         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2980         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2981         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2982         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2983         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2984         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2985         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2986         req.fid = rte_cpu_to_le_16(0xffff);
2987         req.enables = rte_cpu_to_le_32(enables);
2988
2989         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2990
2991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2992
2993         HWRM_CHECK_RESULT();
2994         HWRM_UNLOCK();
2995
2996         return rc;
2997 }
2998
2999 static void populate_vf_func_cfg_req(struct bnxt *bp,
3000                                      struct hwrm_func_cfg_input *req,
3001                                      int num_vfs)
3002 {
3003         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3004                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3005                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3006                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3007                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3008                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3009                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3010                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3011                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3012                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3013
3014         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3015                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3016                                     BNXT_NUM_VLANS);
3017         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3018         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3019                                                 (num_vfs + 1));
3020         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3021         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3022                                                (num_vfs + 1));
3023         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3024         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3025         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3026         /* TODO: For now, do not support VMDq/RFS on VFs. */
3027         req->num_vnics = rte_cpu_to_le_16(1);
3028         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3029                                                  (num_vfs + 1));
3030 }
3031
3032 static void add_random_mac_if_needed(struct bnxt *bp,
3033                                      struct hwrm_func_cfg_input *cfg_req,
3034                                      int vf)
3035 {
3036         struct rte_ether_addr mac;
3037
3038         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3039                 return;
3040
3041         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3042                 cfg_req->enables |=
3043                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3044                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3045                 bp->pf.vf_info[vf].random_mac = true;
3046         } else {
3047                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3048                         RTE_ETHER_ADDR_LEN);
3049         }
3050 }
3051
3052 static void reserve_resources_from_vf(struct bnxt *bp,
3053                                       struct hwrm_func_cfg_input *cfg_req,
3054                                       int vf)
3055 {
3056         struct hwrm_func_qcaps_input req = {0};
3057         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3058         int rc;
3059
3060         /* Get the actual allocated values now */
3061         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3062         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3064
3065         if (rc) {
3066                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3067                 copy_func_cfg_to_qcaps(cfg_req, resp);
3068         } else if (resp->error_code) {
3069                 rc = rte_le_to_cpu_16(resp->error_code);
3070                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3071                 copy_func_cfg_to_qcaps(cfg_req, resp);
3072         }
3073
3074         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3075         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3076         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3077         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3078         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3079         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3080         /*
3081          * TODO: While not supporting VMDq with VFs, max_vnics is always
3082          * forced to 1 in this case
3083          */
3084         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3085         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3086
3087         HWRM_UNLOCK();
3088 }
3089
3090 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3091 {
3092         struct hwrm_func_qcfg_input req = {0};
3093         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3094         int rc;
3095
3096         /* Check for zero MAC address */
3097         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3098         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3100         HWRM_CHECK_RESULT();
3101         rc = rte_le_to_cpu_16(resp->vlan);
3102
3103         HWRM_UNLOCK();
3104
3105         return rc;
3106 }
3107
3108 static int update_pf_resource_max(struct bnxt *bp)
3109 {
3110         struct hwrm_func_qcfg_input req = {0};
3111         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3112         int rc;
3113
3114         /* And copy the allocated numbers into the pf struct */
3115         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3116         req.fid = rte_cpu_to_le_16(0xffff);
3117         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3118         HWRM_CHECK_RESULT();
3119
3120         /* Only TX ring value reflects actual allocation? TODO */
3121         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3122         bp->pf.evb_mode = resp->evb_mode;
3123
3124         HWRM_UNLOCK();
3125
3126         return rc;
3127 }
3128
3129 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3130 {
3131         int rc;
3132
3133         if (!BNXT_PF(bp)) {
3134                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3135                 return -EINVAL;
3136         }
3137
3138         rc = bnxt_hwrm_func_qcaps(bp);
3139         if (rc)
3140                 return rc;
3141
3142         bp->pf.func_cfg_flags &=
3143                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3144                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3145         bp->pf.func_cfg_flags |=
3146                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3147         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3148         rc = __bnxt_hwrm_func_qcaps(bp);
3149         return rc;
3150 }
3151
3152 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3153 {
3154         struct hwrm_func_cfg_input req = {0};
3155         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3156         int i;
3157         size_t sz;
3158         int rc = 0;
3159         size_t req_buf_sz;
3160
3161         if (!BNXT_PF(bp)) {
3162                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3163                 return -EINVAL;
3164         }
3165
3166         rc = bnxt_hwrm_func_qcaps(bp);
3167
3168         if (rc)
3169                 return rc;
3170
3171         bp->pf.active_vfs = num_vfs;
3172
3173         /*
3174          * First, configure the PF to only use one TX ring.  This ensures that
3175          * there are enough rings for all VFs.
3176          *
3177          * If we don't do this, when we call func_alloc() later, we will lock
3178          * extra rings to the PF that won't be available during func_cfg() of
3179          * the VFs.
3180          *
3181          * This has been fixed with firmware versions above 20.6.54
3182          */
3183         bp->pf.func_cfg_flags &=
3184                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3185                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3186         bp->pf.func_cfg_flags |=
3187                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3188         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3189         if (rc)
3190                 return rc;
3191
3192         /*
3193          * Now, create and register a buffer to hold forwarded VF requests
3194          */
3195         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3196         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3197                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3198         if (bp->pf.vf_req_buf == NULL) {
3199                 rc = -ENOMEM;
3200                 goto error_free;
3201         }
3202         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3203                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3204         for (i = 0; i < num_vfs; i++)
3205                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3206                                         (i * HWRM_MAX_REQ_LEN);
3207
3208         rc = bnxt_hwrm_func_buf_rgtr(bp);
3209         if (rc)
3210                 goto error_free;
3211
3212         populate_vf_func_cfg_req(bp, &req, num_vfs);
3213
3214         bp->pf.active_vfs = 0;
3215         for (i = 0; i < num_vfs; i++) {
3216                 add_random_mac_if_needed(bp, &req, i);
3217
3218                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3219                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3220                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3221                 rc = bnxt_hwrm_send_message(bp,
3222                                             &req,
3223                                             sizeof(req),
3224                                             BNXT_USE_CHIMP_MB);
3225
3226                 /* Clear enable flag for next pass */
3227                 req.enables &= ~rte_cpu_to_le_32(
3228                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3229
3230                 if (rc || resp->error_code) {
3231                         PMD_DRV_LOG(ERR,
3232                                 "Failed to initizlie VF %d\n", i);
3233                         PMD_DRV_LOG(ERR,
3234                                 "Not all VFs available. (%d, %d)\n",
3235                                 rc, resp->error_code);
3236                         HWRM_UNLOCK();
3237                         break;
3238                 }
3239
3240                 HWRM_UNLOCK();
3241
3242                 reserve_resources_from_vf(bp, &req, i);
3243                 bp->pf.active_vfs++;
3244                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3245         }
3246
3247         /*
3248          * Now configure the PF to use "the rest" of the resources
3249          * We're using STD_TX_RING_MODE here though which will limit the TX
3250          * rings.  This will allow QoS to function properly.  Not setting this
3251          * will cause PF rings to break bandwidth settings.
3252          */
3253         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3254         if (rc)
3255                 goto error_free;
3256
3257         rc = update_pf_resource_max(bp);
3258         if (rc)
3259                 goto error_free;
3260
3261         return rc;
3262
3263 error_free:
3264         bnxt_hwrm_func_buf_unrgtr(bp);
3265         return rc;
3266 }
3267
3268 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3269 {
3270         struct hwrm_func_cfg_input req = {0};
3271         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3272         int rc;
3273
3274         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3275
3276         req.fid = rte_cpu_to_le_16(0xffff);
3277         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3278         req.evb_mode = bp->pf.evb_mode;
3279
3280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3281         HWRM_CHECK_RESULT();
3282         HWRM_UNLOCK();
3283
3284         return rc;
3285 }
3286
3287 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3288                                 uint8_t tunnel_type)
3289 {
3290         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3291         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3292         int rc = 0;
3293
3294         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3295         req.tunnel_type = tunnel_type;
3296         req.tunnel_dst_port_val = port;
3297         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3298         HWRM_CHECK_RESULT();
3299
3300         switch (tunnel_type) {
3301         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3302                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3303                 bp->vxlan_port = port;
3304                 break;
3305         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3306                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3307                 bp->geneve_port = port;
3308                 break;
3309         default:
3310                 break;
3311         }
3312
3313         HWRM_UNLOCK();
3314
3315         return rc;
3316 }
3317
3318 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3319                                 uint8_t tunnel_type)
3320 {
3321         struct hwrm_tunnel_dst_port_free_input req = {0};
3322         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3323         int rc = 0;
3324
3325         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3326
3327         req.tunnel_type = tunnel_type;
3328         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3329         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330
3331         HWRM_CHECK_RESULT();
3332         HWRM_UNLOCK();
3333
3334         return rc;
3335 }
3336
3337 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3338                                         uint32_t flags)
3339 {
3340         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3341         struct hwrm_func_cfg_input req = {0};
3342         int rc;
3343
3344         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3345
3346         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3347         req.flags = rte_cpu_to_le_32(flags);
3348         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3349
3350         HWRM_CHECK_RESULT();
3351         HWRM_UNLOCK();
3352
3353         return rc;
3354 }
3355
3356 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3357 {
3358         uint32_t *flag = flagp;
3359
3360         vnic->flags = *flag;
3361 }
3362
3363 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3364 {
3365         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3366 }
3367
3368 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3369 {
3370         int rc = 0;
3371         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3372         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3373
3374         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3375
3376         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3377         req.req_buf_page_size = rte_cpu_to_le_16(
3378                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3379         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3380         req.req_buf_page_addr0 =
3381                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3382         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3383                 PMD_DRV_LOG(ERR,
3384                         "unable to map buffer address to physical memory\n");
3385                 return -ENOMEM;
3386         }
3387
3388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389
3390         HWRM_CHECK_RESULT();
3391         HWRM_UNLOCK();
3392
3393         return rc;
3394 }
3395
3396 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3397 {
3398         int rc = 0;
3399         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3400         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3401
3402         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3403                 return 0;
3404
3405         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3406
3407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3408
3409         HWRM_CHECK_RESULT();
3410         HWRM_UNLOCK();
3411
3412         return rc;
3413 }
3414
3415 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3416 {
3417         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3418         struct hwrm_func_cfg_input req = {0};
3419         int rc;
3420
3421         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3422
3423         req.fid = rte_cpu_to_le_16(0xffff);
3424         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3425         req.enables = rte_cpu_to_le_32(
3426                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3427         req.async_event_cr = rte_cpu_to_le_16(
3428                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3430
3431         HWRM_CHECK_RESULT();
3432         HWRM_UNLOCK();
3433
3434         return rc;
3435 }
3436
3437 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3438 {
3439         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3440         struct hwrm_func_vf_cfg_input req = {0};
3441         int rc;
3442
3443         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3444
3445         req.enables = rte_cpu_to_le_32(
3446                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3447         req.async_event_cr = rte_cpu_to_le_16(
3448                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3450
3451         HWRM_CHECK_RESULT();
3452         HWRM_UNLOCK();
3453
3454         return rc;
3455 }
3456
3457 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3458 {
3459         struct hwrm_func_cfg_input req = {0};
3460         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3461         uint16_t dflt_vlan, fid;
3462         uint32_t func_cfg_flags;
3463         int rc = 0;
3464
3465         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3466
3467         if (is_vf) {
3468                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3469                 fid = bp->pf.vf_info[vf].fid;
3470                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3471         } else {
3472                 fid = rte_cpu_to_le_16(0xffff);
3473                 func_cfg_flags = bp->pf.func_cfg_flags;
3474                 dflt_vlan = bp->vlan;
3475         }
3476
3477         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3478         req.fid = rte_cpu_to_le_16(fid);
3479         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3480         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3481
3482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3483
3484         HWRM_CHECK_RESULT();
3485         HWRM_UNLOCK();
3486
3487         return rc;
3488 }
3489
3490 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3491                         uint16_t max_bw, uint16_t enables)
3492 {
3493         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3494         struct hwrm_func_cfg_input req = {0};
3495         int rc;
3496
3497         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3498
3499         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3500         req.enables |= rte_cpu_to_le_32(enables);
3501         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3502         req.max_bw = rte_cpu_to_le_32(max_bw);
3503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3504
3505         HWRM_CHECK_RESULT();
3506         HWRM_UNLOCK();
3507
3508         return rc;
3509 }
3510
3511 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3512 {
3513         struct hwrm_func_cfg_input req = {0};
3514         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3515         int rc = 0;
3516
3517         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3518
3519         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3520         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3521         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3522         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3523
3524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3525
3526         HWRM_CHECK_RESULT();
3527         HWRM_UNLOCK();
3528
3529         return rc;
3530 }
3531
3532 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3533 {
3534         int rc;
3535
3536         if (BNXT_PF(bp))
3537                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3538         else
3539                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3540
3541         return rc;
3542 }
3543
3544 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3545                               void *encaped, size_t ec_size)
3546 {
3547         int rc = 0;
3548         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3549         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3550
3551         if (ec_size > sizeof(req.encap_request))
3552                 return -1;
3553
3554         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3555
3556         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3557         memcpy(req.encap_request, encaped, ec_size);
3558
3559         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3560
3561         HWRM_CHECK_RESULT();
3562         HWRM_UNLOCK();
3563
3564         return rc;
3565 }
3566
3567 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3568                                        struct rte_ether_addr *mac)
3569 {
3570         struct hwrm_func_qcfg_input req = {0};
3571         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3572         int rc;
3573
3574         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3575
3576         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3578
3579         HWRM_CHECK_RESULT();
3580
3581         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3582
3583         HWRM_UNLOCK();
3584
3585         return rc;
3586 }
3587
3588 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3589                             void *encaped, size_t ec_size)
3590 {
3591         int rc = 0;
3592         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3593         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3594
3595         if (ec_size > sizeof(req.encap_request))
3596                 return -1;
3597
3598         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3599
3600         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3601         memcpy(req.encap_request, encaped, ec_size);
3602
3603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3604
3605         HWRM_CHECK_RESULT();
3606         HWRM_UNLOCK();
3607
3608         return rc;
3609 }
3610
3611 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3612                          struct rte_eth_stats *stats, uint8_t rx)
3613 {
3614         int rc = 0;
3615         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3616         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3617
3618         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3619
3620         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3621
3622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3623
3624         HWRM_CHECK_RESULT();
3625
3626         if (rx) {
3627                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3628                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3629                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3630                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3631                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3632                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3633                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3634                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3635         } else {
3636                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3637                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3638                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3639                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3640                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3641                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3642         }
3643
3644         HWRM_UNLOCK();
3645
3646         return rc;
3647 }
3648
3649 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3650 {
3651         struct hwrm_port_qstats_input req = {0};
3652         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3653         struct bnxt_pf_info *pf = &bp->pf;
3654         int rc;
3655
3656         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3657
3658         req.port_id = rte_cpu_to_le_16(pf->port_id);
3659         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3660         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662
3663         HWRM_CHECK_RESULT();
3664         HWRM_UNLOCK();
3665
3666         return rc;
3667 }
3668
3669 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3670 {
3671         struct hwrm_port_clr_stats_input req = {0};
3672         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3673         struct bnxt_pf_info *pf = &bp->pf;
3674         int rc;
3675
3676         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3677         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3678             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3679                 return 0;
3680
3681         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3682
3683         req.port_id = rte_cpu_to_le_16(pf->port_id);
3684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3685
3686         HWRM_CHECK_RESULT();
3687         HWRM_UNLOCK();
3688
3689         return rc;
3690 }
3691
3692 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3693 {
3694         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3695         struct hwrm_port_led_qcaps_input req = {0};
3696         int rc;
3697
3698         if (BNXT_VF(bp))
3699                 return 0;
3700
3701         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3702         req.port_id = bp->pf.port_id;
3703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3704
3705         HWRM_CHECK_RESULT();
3706
3707         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3708                 unsigned int i;
3709
3710                 bp->num_leds = resp->num_leds;
3711                 memcpy(bp->leds, &resp->led0_id,
3712                         sizeof(bp->leds[0]) * bp->num_leds);
3713                 for (i = 0; i < bp->num_leds; i++) {
3714                         struct bnxt_led_info *led = &bp->leds[i];
3715
3716                         uint16_t caps = led->led_state_caps;
3717
3718                         if (!led->led_group_id ||
3719                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3720                                 bp->num_leds = 0;
3721                                 break;
3722                         }
3723                 }
3724         }
3725
3726         HWRM_UNLOCK();
3727
3728         return rc;
3729 }
3730
3731 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3732 {
3733         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3734         struct hwrm_port_led_cfg_input req = {0};
3735         struct bnxt_led_cfg *led_cfg;
3736         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3737         uint16_t duration = 0;
3738         int rc, i;
3739
3740         if (!bp->num_leds || BNXT_VF(bp))
3741                 return -EOPNOTSUPP;
3742
3743         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3744
3745         if (led_on) {
3746                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3747                 duration = rte_cpu_to_le_16(500);
3748         }
3749         req.port_id = bp->pf.port_id;
3750         req.num_leds = bp->num_leds;
3751         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3752         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3753                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3754                 led_cfg->led_id = bp->leds[i].led_id;
3755                 led_cfg->led_state = led_state;
3756                 led_cfg->led_blink_on = duration;
3757                 led_cfg->led_blink_off = duration;
3758                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3759         }
3760
3761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3762
3763         HWRM_CHECK_RESULT();
3764         HWRM_UNLOCK();
3765
3766         return rc;
3767 }
3768
3769 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3770                                uint32_t *length)
3771 {
3772         int rc;
3773         struct hwrm_nvm_get_dir_info_input req = {0};
3774         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3775
3776         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3777
3778         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3779
3780         HWRM_CHECK_RESULT();
3781
3782         *entries = rte_le_to_cpu_32(resp->entries);
3783         *length = rte_le_to_cpu_32(resp->entry_length);
3784
3785         HWRM_UNLOCK();
3786         return rc;
3787 }
3788
3789 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3790 {
3791         int rc;
3792         uint32_t dir_entries;
3793         uint32_t entry_length;
3794         uint8_t *buf;
3795         size_t buflen;
3796         rte_iova_t dma_handle;
3797         struct hwrm_nvm_get_dir_entries_input req = {0};
3798         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3799
3800         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3801         if (rc != 0)
3802                 return rc;
3803
3804         *data++ = dir_entries;
3805         *data++ = entry_length;
3806         len -= 2;
3807         memset(data, 0xff, len);
3808
3809         buflen = dir_entries * entry_length;
3810         buf = rte_malloc("nvm_dir", buflen, 0);
3811         rte_mem_lock_page(buf);
3812         if (buf == NULL)
3813                 return -ENOMEM;
3814         dma_handle = rte_mem_virt2iova(buf);
3815         if (dma_handle == RTE_BAD_IOVA) {
3816                 PMD_DRV_LOG(ERR,
3817                         "unable to map response address to physical memory\n");
3818                 return -ENOMEM;
3819         }
3820         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3821         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3823
3824         if (rc == 0)
3825                 memcpy(data, buf, len > buflen ? buflen : len);
3826
3827         rte_free(buf);
3828         HWRM_CHECK_RESULT();
3829         HWRM_UNLOCK();
3830
3831         return rc;
3832 }
3833
3834 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3835                              uint32_t offset, uint32_t length,
3836                              uint8_t *data)
3837 {
3838         int rc;
3839         uint8_t *buf;
3840         rte_iova_t dma_handle;
3841         struct hwrm_nvm_read_input req = {0};
3842         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3843
3844         buf = rte_malloc("nvm_item", length, 0);
3845         rte_mem_lock_page(buf);
3846         if (!buf)
3847                 return -ENOMEM;
3848
3849         dma_handle = rte_mem_virt2iova(buf);
3850         if (dma_handle == RTE_BAD_IOVA) {
3851                 PMD_DRV_LOG(ERR,
3852                         "unable to map response address to physical memory\n");
3853                 return -ENOMEM;
3854         }
3855         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3856         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3857         req.dir_idx = rte_cpu_to_le_16(index);
3858         req.offset = rte_cpu_to_le_32(offset);
3859         req.len = rte_cpu_to_le_32(length);
3860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3861         if (rc == 0)
3862                 memcpy(data, buf, length);
3863
3864         rte_free(buf);
3865         HWRM_CHECK_RESULT();
3866         HWRM_UNLOCK();
3867
3868         return rc;
3869 }
3870
3871 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3872 {
3873         int rc;
3874         struct hwrm_nvm_erase_dir_entry_input req = {0};
3875         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3876
3877         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3878         req.dir_idx = rte_cpu_to_le_16(index);
3879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3880         HWRM_CHECK_RESULT();
3881         HWRM_UNLOCK();
3882
3883         return rc;
3884 }
3885
3886
3887 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3888                           uint16_t dir_ordinal, uint16_t dir_ext,
3889                           uint16_t dir_attr, const uint8_t *data,
3890                           size_t data_len)
3891 {
3892         int rc;
3893         struct hwrm_nvm_write_input req = {0};
3894         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3895         rte_iova_t dma_handle;
3896         uint8_t *buf;
3897
3898         buf = rte_malloc("nvm_write", data_len, 0);
3899         rte_mem_lock_page(buf);
3900         if (!buf)
3901                 return -ENOMEM;
3902
3903         dma_handle = rte_mem_virt2iova(buf);
3904         if (dma_handle == RTE_BAD_IOVA) {
3905                 PMD_DRV_LOG(ERR,
3906                         "unable to map response address to physical memory\n");
3907                 return -ENOMEM;
3908         }
3909         memcpy(buf, data, data_len);
3910
3911         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3912
3913         req.dir_type = rte_cpu_to_le_16(dir_type);
3914         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3915         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3916         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3917         req.dir_data_length = rte_cpu_to_le_32(data_len);
3918         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3919
3920         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3921
3922         rte_free(buf);
3923         HWRM_CHECK_RESULT();
3924         HWRM_UNLOCK();
3925
3926         return rc;
3927 }
3928
3929 static void
3930 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3931 {
3932         uint32_t *count = cbdata;
3933
3934         *count = *count + 1;
3935 }
3936
3937 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3938                                      struct bnxt_vnic_info *vnic __rte_unused)
3939 {
3940         return 0;
3941 }
3942
3943 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3944 {
3945         uint32_t count = 0;
3946
3947         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3948             &count, bnxt_vnic_count_hwrm_stub);
3949
3950         return count;
3951 }
3952
3953 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3954                                         uint16_t *vnic_ids)
3955 {
3956         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3957         struct hwrm_func_vf_vnic_ids_query_output *resp =
3958                                                 bp->hwrm_cmd_resp_addr;
3959         int rc;
3960
3961         /* First query all VNIC ids */
3962         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3963
3964         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3965         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3966         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3967
3968         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3969                 HWRM_UNLOCK();
3970                 PMD_DRV_LOG(ERR,
3971                 "unable to map VNIC ID table address to physical memory\n");
3972                 return -ENOMEM;
3973         }
3974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3975         HWRM_CHECK_RESULT();
3976         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3977
3978         HWRM_UNLOCK();
3979
3980         return rc;
3981 }
3982
3983 /*
3984  * This function queries the VNIC IDs  for a specified VF. It then calls
3985  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3986  * Then it calls the hwrm_cb function to program this new vnic configuration.
3987  */
3988 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3989         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3990         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3991 {
3992         struct bnxt_vnic_info vnic;
3993         int rc = 0;
3994         int i, num_vnic_ids;
3995         uint16_t *vnic_ids;
3996         size_t vnic_id_sz;
3997         size_t sz;
3998
3999         /* First query all VNIC ids */
4000         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4001         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4002                         RTE_CACHE_LINE_SIZE);
4003         if (vnic_ids == NULL)
4004                 return -ENOMEM;
4005
4006         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4007                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4008
4009         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4010
4011         if (num_vnic_ids < 0)
4012                 return num_vnic_ids;
4013
4014         /* Retrieve VNIC, update bd_stall then update */
4015
4016         for (i = 0; i < num_vnic_ids; i++) {
4017                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4018                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4019                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4020                 if (rc)
4021                         break;
4022                 if (vnic.mru <= 4)      /* Indicates unallocated */
4023                         continue;
4024
4025                 vnic_cb(&vnic, cbdata);
4026
4027                 rc = hwrm_cb(bp, &vnic);
4028                 if (rc)
4029                         break;
4030         }
4031
4032         rte_free(vnic_ids);
4033
4034         return rc;
4035 }
4036
4037 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4038                                               bool on)
4039 {
4040         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4041         struct hwrm_func_cfg_input req = {0};
4042         int rc;
4043
4044         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4045
4046         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4047         req.enables |= rte_cpu_to_le_32(
4048                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4049         req.vlan_antispoof_mode = on ?
4050                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4051                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4053
4054         HWRM_CHECK_RESULT();
4055         HWRM_UNLOCK();
4056
4057         return rc;
4058 }
4059
4060 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4061 {
4062         struct bnxt_vnic_info vnic;
4063         uint16_t *vnic_ids;
4064         size_t vnic_id_sz;
4065         int num_vnic_ids, i;
4066         size_t sz;
4067         int rc;
4068
4069         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4070         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4071                         RTE_CACHE_LINE_SIZE);
4072         if (vnic_ids == NULL)
4073                 return -ENOMEM;
4074
4075         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4076                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4077
4078         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4079         if (rc <= 0)
4080                 goto exit;
4081         num_vnic_ids = rc;
4082
4083         /*
4084          * Loop through to find the default VNIC ID.
4085          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4086          * by sending the hwrm_func_qcfg command to the firmware.
4087          */
4088         for (i = 0; i < num_vnic_ids; i++) {
4089                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4090                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4091                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4092                                         bp->pf.first_vf_id + vf);
4093                 if (rc)
4094                         goto exit;
4095                 if (vnic.func_default) {
4096                         rte_free(vnic_ids);
4097                         return vnic.fw_vnic_id;
4098                 }
4099         }
4100         /* Could not find a default VNIC. */
4101         PMD_DRV_LOG(ERR, "No default VNIC\n");
4102 exit:
4103         rte_free(vnic_ids);
4104         return rc;
4105 }
4106
4107 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4108                          uint16_t dst_id,
4109                          struct bnxt_filter_info *filter)
4110 {
4111         int rc = 0;
4112         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4113         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4114         uint32_t enables = 0;
4115
4116         if (filter->fw_em_filter_id != UINT64_MAX)
4117                 bnxt_hwrm_clear_em_filter(bp, filter);
4118
4119         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4120
4121         req.flags = rte_cpu_to_le_32(filter->flags);
4122
4123         enables = filter->enables |
4124               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4125         req.dst_id = rte_cpu_to_le_16(dst_id);
4126
4127         if (filter->ip_addr_type) {
4128                 req.ip_addr_type = filter->ip_addr_type;
4129                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4130         }
4131         if (enables &
4132             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4133                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4134         if (enables &
4135             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4136                 memcpy(req.src_macaddr, filter->src_macaddr,
4137                        RTE_ETHER_ADDR_LEN);
4138         if (enables &
4139             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4140                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4141                        RTE_ETHER_ADDR_LEN);
4142         if (enables &
4143             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4144                 req.ovlan_vid = filter->l2_ovlan;
4145         if (enables &
4146             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4147                 req.ivlan_vid = filter->l2_ivlan;
4148         if (enables &
4149             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4150                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4151         if (enables &
4152             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4153                 req.ip_protocol = filter->ip_protocol;
4154         if (enables &
4155             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4156                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4157         if (enables &
4158             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4159                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4160         if (enables &
4161             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4162                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4163         if (enables &
4164             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4165                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4166         if (enables &
4167             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4168                 req.mirror_vnic_id = filter->mirror_vnic_id;
4169
4170         req.enables = rte_cpu_to_le_32(enables);
4171
4172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4173
4174         HWRM_CHECK_RESULT();
4175
4176         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4177         HWRM_UNLOCK();
4178
4179         return rc;
4180 }
4181
4182 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4183 {
4184         int rc = 0;
4185         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4186         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4187
4188         if (filter->fw_em_filter_id == UINT64_MAX)
4189                 return 0;
4190
4191         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4192         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4193
4194         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4195
4196         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4197
4198         HWRM_CHECK_RESULT();
4199         HWRM_UNLOCK();
4200
4201         filter->fw_em_filter_id = UINT64_MAX;
4202         filter->fw_l2_filter_id = UINT64_MAX;
4203
4204         return 0;
4205 }
4206
4207 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4208                          uint16_t dst_id,
4209                          struct bnxt_filter_info *filter)
4210 {
4211         int rc = 0;
4212         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4213         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4214                                                 bp->hwrm_cmd_resp_addr;
4215         uint32_t enables = 0;
4216
4217         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4218                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4219
4220         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4221
4222         req.flags = rte_cpu_to_le_32(filter->flags);
4223
4224         enables = filter->enables |
4225               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4226         req.dst_id = rte_cpu_to_le_16(dst_id);
4227
4228         if (filter->ip_addr_type) {
4229                 req.ip_addr_type = filter->ip_addr_type;
4230                 enables |=
4231                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4232         }
4233         if (enables &
4234             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4235                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4236         if (enables &
4237             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4238                 memcpy(req.src_macaddr, filter->src_macaddr,
4239                        RTE_ETHER_ADDR_LEN);
4240         if (enables &
4241             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4242                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4243         if (enables &
4244             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4245                 req.ip_protocol = filter->ip_protocol;
4246         if (enables &
4247             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4248                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4249         if (enables &
4250             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4251                 req.src_ipaddr_mask[0] =
4252                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4253         if (enables &
4254             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4255                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4256         if (enables &
4257             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4258                 req.dst_ipaddr_mask[0] =
4259                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4260         if (enables &
4261             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4262                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4263         if (enables &
4264             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4265                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4266         if (enables &
4267             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4268                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4269         if (enables &
4270             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4271                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4272         if (enables &
4273             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4274                 req.mirror_vnic_id = filter->mirror_vnic_id;
4275
4276         req.enables = rte_cpu_to_le_32(enables);
4277
4278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4279
4280         HWRM_CHECK_RESULT();
4281
4282         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4283         HWRM_UNLOCK();
4284
4285         return rc;
4286 }
4287
4288 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4289                                 struct bnxt_filter_info *filter)
4290 {
4291         int rc = 0;
4292         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4293         struct hwrm_cfa_ntuple_filter_free_output *resp =
4294                                                 bp->hwrm_cmd_resp_addr;
4295
4296         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4297                 return 0;
4298
4299         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4300
4301         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4302
4303         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4304
4305         HWRM_CHECK_RESULT();
4306         HWRM_UNLOCK();
4307
4308         filter->fw_ntuple_filter_id = UINT64_MAX;
4309
4310         return 0;
4311 }
4312
4313 static int
4314 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4315 {
4316         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4317         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4318         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4319         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4320         uint16_t *ring_tbl = vnic->rss_table;
4321         int nr_ctxs = vnic->num_lb_ctxts;
4322         int max_rings = bp->rx_nr_rings;
4323         int i, j, k, cnt;
4324         int rc = 0;
4325
4326         for (i = 0, k = 0; i < nr_ctxs; i++) {
4327                 struct bnxt_rx_ring_info *rxr;
4328                 struct bnxt_cp_ring_info *cpr;
4329
4330                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4331
4332                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4333                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4334                 req.hash_mode_flags = vnic->hash_mode;
4335
4336                 req.ring_grp_tbl_addr =
4337                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4338                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4339                                      2 * sizeof(*ring_tbl));
4340                 req.hash_key_tbl_addr =
4341                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4342
4343                 req.ring_table_pair_index = i;
4344                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4345
4346                 for (j = 0; j < 64; j++) {
4347                         uint16_t ring_id;
4348
4349                         /* Find next active ring. */
4350                         for (cnt = 0; cnt < max_rings; cnt++) {
4351                                 if (rx_queue_state[k] !=
4352                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4353                                         break;
4354                                 if (++k == max_rings)
4355                                         k = 0;
4356                         }
4357
4358                         /* Return if no rings are active. */
4359                         if (cnt == max_rings) {
4360                                 HWRM_UNLOCK();
4361                                 return 0;
4362                         }
4363
4364                         /* Add rx/cp ring pair to RSS table. */
4365                         rxr = rxqs[k]->rx_ring;
4366                         cpr = rxqs[k]->cp_ring;
4367
4368                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4369                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4370                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4371                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4372
4373                         if (++k == max_rings)
4374                                 k = 0;
4375                 }
4376                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4377                                             BNXT_USE_CHIMP_MB);
4378
4379                 HWRM_CHECK_RESULT();
4380                 HWRM_UNLOCK();
4381         }
4382
4383         return rc;
4384 }
4385
4386 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4387 {
4388         unsigned int rss_idx, fw_idx, i;
4389
4390         if (!(vnic->rss_table && vnic->hash_type))
4391                 return 0;
4392
4393         if (BNXT_CHIP_THOR(bp))
4394                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4395
4396         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4397                 return 0;
4398
4399         if (vnic->rss_table && vnic->hash_type) {
4400                 /*
4401                  * Fill the RSS hash & redirection table with
4402                  * ring group ids for all VNICs
4403                  */
4404                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4405                         rss_idx++, fw_idx++) {
4406                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4407                                 fw_idx %= bp->rx_cp_nr_rings;
4408                                 if (vnic->fw_grp_ids[fw_idx] !=
4409                                     INVALID_HW_RING_ID)
4410                                         break;
4411                                 fw_idx++;
4412                         }
4413                         if (i == bp->rx_cp_nr_rings)
4414                                 return 0;
4415                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4416                 }
4417                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4418         }
4419
4420         return 0;
4421 }
4422
4423 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4424         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4425 {
4426         uint16_t flags;
4427
4428         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4429
4430         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4431         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4432
4433         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4434         req->num_cmpl_dma_aggr_during_int =
4435                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4436
4437         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4438
4439         /* min timer set to 1/2 of interrupt timer */
4440         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4441
4442         /* buf timer set to 1/4 of interrupt timer */
4443         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4444
4445         req->cmpl_aggr_dma_tmr_during_int =
4446                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4447
4448         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4449                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4450         req->flags = rte_cpu_to_le_16(flags);
4451 }
4452
4453 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4454                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4455 {
4456         struct hwrm_ring_aggint_qcaps_input req = {0};
4457         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4458         uint32_t enables;
4459         uint16_t flags;
4460         int rc;
4461
4462         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4463         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4464         HWRM_CHECK_RESULT();
4465
4466         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4467         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4468
4469         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4470                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4471         agg_req->flags = rte_cpu_to_le_16(flags);
4472         enables =
4473          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4474          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4475         agg_req->enables = rte_cpu_to_le_32(enables);
4476
4477         HWRM_UNLOCK();
4478         return rc;
4479 }
4480
4481 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4482                         struct bnxt_coal *coal, uint16_t ring_id)
4483 {
4484         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4485         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4486                                                 bp->hwrm_cmd_resp_addr;
4487         int rc;
4488
4489         /* Set ring coalesce parameters only for 100G NICs */
4490         if (BNXT_CHIP_THOR(bp)) {
4491                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4492                         return -1;
4493         } else if (bnxt_stratus_device(bp)) {
4494                 bnxt_hwrm_set_coal_params(coal, &req);
4495         } else {
4496                 return 0;
4497         }
4498
4499         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4500         req.ring_id = rte_cpu_to_le_16(ring_id);
4501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4502         HWRM_CHECK_RESULT();
4503         HWRM_UNLOCK();
4504         return 0;
4505 }
4506
4507 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4508 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4509 {
4510         struct hwrm_func_backing_store_qcaps_input req = {0};
4511         struct hwrm_func_backing_store_qcaps_output *resp =
4512                 bp->hwrm_cmd_resp_addr;
4513         struct bnxt_ctx_pg_info *ctx_pg;
4514         struct bnxt_ctx_mem_info *ctx;
4515         int total_alloc_len;
4516         int rc, i;
4517
4518         if (!BNXT_CHIP_THOR(bp) ||
4519             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4520             BNXT_VF(bp) ||
4521             bp->ctx)
4522                 return 0;
4523
4524         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4525         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4526         HWRM_CHECK_RESULT_SILENT();
4527
4528         total_alloc_len = sizeof(*ctx);
4529         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4530                           RTE_CACHE_LINE_SIZE);
4531         if (!ctx) {
4532                 rc = -ENOMEM;
4533                 goto ctx_err;
4534         }
4535
4536         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4537                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4538                             RTE_CACHE_LINE_SIZE);
4539         if (!ctx_pg) {
4540                 rc = -ENOMEM;
4541                 goto ctx_err;
4542         }
4543         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4544                 ctx->tqm_mem[i] = ctx_pg;
4545
4546         bp->ctx = ctx;
4547         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4548         ctx->qp_min_qp1_entries =
4549                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4550         ctx->qp_max_l2_entries =
4551                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4552         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4553         ctx->srq_max_l2_entries =
4554                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4555         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4556         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4557         ctx->cq_max_l2_entries =
4558                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4559         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4560         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4561         ctx->vnic_max_vnic_entries =
4562                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4563         ctx->vnic_max_ring_table_entries =
4564                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4565         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4566         ctx->stat_max_entries =
4567                 rte_le_to_cpu_32(resp->stat_max_entries);
4568         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4569         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4570         ctx->tqm_min_entries_per_ring =
4571                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4572         ctx->tqm_max_entries_per_ring =
4573                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4574         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4575         if (!ctx->tqm_entries_multiple)
4576                 ctx->tqm_entries_multiple = 1;
4577         ctx->mrav_max_entries =
4578                 rte_le_to_cpu_32(resp->mrav_max_entries);
4579         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4580         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4581         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4582 ctx_err:
4583         HWRM_UNLOCK();
4584         return rc;
4585 }
4586
4587 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4588 {
4589         struct hwrm_func_backing_store_cfg_input req = {0};
4590         struct hwrm_func_backing_store_cfg_output *resp =
4591                 bp->hwrm_cmd_resp_addr;
4592         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4593         struct bnxt_ctx_pg_info *ctx_pg;
4594         uint32_t *num_entries;
4595         uint64_t *pg_dir;
4596         uint8_t *pg_attr;
4597         uint32_t ena;
4598         int i, rc;
4599
4600         if (!ctx)
4601                 return 0;
4602
4603         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4604         req.enables = rte_cpu_to_le_32(enables);
4605
4606         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4607                 ctx_pg = &ctx->qp_mem;
4608                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4609                 req.qp_num_qp1_entries =
4610                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4611                 req.qp_num_l2_entries =
4612                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4613                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4614                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4615                                       &req.qpc_pg_size_qpc_lvl,
4616                                       &req.qpc_page_dir);
4617         }
4618
4619         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4620                 ctx_pg = &ctx->srq_mem;
4621                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4622                 req.srq_num_l2_entries =
4623                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4624                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4625                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4626                                       &req.srq_pg_size_srq_lvl,
4627                                       &req.srq_page_dir);
4628         }
4629
4630         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4631                 ctx_pg = &ctx->cq_mem;
4632                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4633                 req.cq_num_l2_entries =
4634                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4635                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4636                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4637                                       &req.cq_pg_size_cq_lvl,
4638                                       &req.cq_page_dir);
4639         }
4640
4641         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4642                 ctx_pg = &ctx->vnic_mem;
4643                 req.vnic_num_vnic_entries =
4644                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4645                 req.vnic_num_ring_table_entries =
4646                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4647                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4648                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4649                                       &req.vnic_pg_size_vnic_lvl,
4650                                       &req.vnic_page_dir);
4651         }
4652
4653         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4654                 ctx_pg = &ctx->stat_mem;
4655                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4656                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4657                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4658                                       &req.stat_pg_size_stat_lvl,
4659                                       &req.stat_page_dir);
4660         }
4661
4662         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4663         num_entries = &req.tqm_sp_num_entries;
4664         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4665         pg_dir = &req.tqm_sp_page_dir;
4666         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4667         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4668                 if (!(enables & ena))
4669                         continue;
4670
4671                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4672
4673                 ctx_pg = ctx->tqm_mem[i];
4674                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4675                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4676         }
4677
4678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4679         HWRM_CHECK_RESULT();
4680         HWRM_UNLOCK();
4681
4682         return rc;
4683 }
4684
4685 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4686 {
4687         struct hwrm_port_qstats_ext_input req = {0};
4688         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4689         struct bnxt_pf_info *pf = &bp->pf;
4690         int rc;
4691
4692         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4693               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4694                 return 0;
4695
4696         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4697
4698         req.port_id = rte_cpu_to_le_16(pf->port_id);
4699         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4700                 req.tx_stat_host_addr =
4701                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4702                 req.tx_stat_size =
4703                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4704         }
4705         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4706                 req.rx_stat_host_addr =
4707                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4708                 req.rx_stat_size =
4709                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4710         }
4711         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4712
4713         if (rc) {
4714                 bp->fw_rx_port_stats_ext_size = 0;
4715                 bp->fw_tx_port_stats_ext_size = 0;
4716         } else {
4717                 bp->fw_rx_port_stats_ext_size =
4718                         rte_le_to_cpu_16(resp->rx_stat_size);
4719                 bp->fw_tx_port_stats_ext_size =
4720                         rte_le_to_cpu_16(resp->tx_stat_size);
4721         }
4722
4723         HWRM_CHECK_RESULT();
4724         HWRM_UNLOCK();
4725
4726         return rc;
4727 }
4728
4729 int
4730 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4731 {
4732         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4733         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4734                 bp->hwrm_cmd_resp_addr;
4735         int rc = 0;
4736
4737         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4738         req.tunnel_type = type;
4739         req.dest_fid = bp->fw_fid;
4740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4741         HWRM_CHECK_RESULT();
4742
4743         HWRM_UNLOCK();
4744
4745         return rc;
4746 }
4747
4748 int
4749 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4750 {
4751         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4752         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4753                 bp->hwrm_cmd_resp_addr;
4754         int rc = 0;
4755
4756         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4757         req.tunnel_type = type;
4758         req.dest_fid = bp->fw_fid;
4759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4760         HWRM_CHECK_RESULT();
4761
4762         HWRM_UNLOCK();
4763
4764         return rc;
4765 }
4766
4767 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4768 {
4769         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4770         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4771                 bp->hwrm_cmd_resp_addr;
4772         int rc = 0;
4773
4774         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4775         req.src_fid = bp->fw_fid;
4776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4777         HWRM_CHECK_RESULT();
4778
4779         if (type)
4780                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4781
4782         HWRM_UNLOCK();
4783
4784         return rc;
4785 }
4786
4787 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4788                                    uint16_t *dst_fid)
4789 {
4790         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4791         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4792                 bp->hwrm_cmd_resp_addr;
4793         int rc = 0;
4794
4795         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4796         req.src_fid = bp->fw_fid;
4797         req.tunnel_type = tun_type;
4798         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4799         HWRM_CHECK_RESULT();
4800
4801         if (dst_fid)
4802                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4803
4804         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4805
4806         HWRM_UNLOCK();
4807
4808         return rc;
4809 }
4810
4811 int bnxt_hwrm_set_mac(struct bnxt *bp)
4812 {
4813         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4814         struct hwrm_func_vf_cfg_input req = {0};
4815         int rc = 0;
4816
4817         if (!BNXT_VF(bp))
4818                 return 0;
4819
4820         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4821
4822         req.enables =
4823                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4824         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4825
4826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4827
4828         HWRM_CHECK_RESULT();
4829
4830         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4831         HWRM_UNLOCK();
4832
4833         return rc;
4834 }
4835
4836 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4837 {
4838         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4839         struct hwrm_func_drv_if_change_input req = {0};
4840         uint32_t flags;
4841         int rc;
4842
4843         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4844                 return 0;
4845
4846         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4847          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4848          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4849          */
4850         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4851                 return 0;
4852
4853         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4854
4855         if (up)
4856                 req.flags =
4857                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4858
4859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4860
4861         HWRM_CHECK_RESULT();
4862         flags = rte_le_to_cpu_32(resp->flags);
4863         HWRM_UNLOCK();
4864
4865         if (!up)
4866                 return 0;
4867
4868         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4869                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4870                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4871         }
4872
4873         return 0;
4874 }
4875
4876 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4877 {
4878         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4879         struct bnxt_error_recovery_info *info = bp->recovery_info;
4880         struct hwrm_error_recovery_qcfg_input req = {0};
4881         uint32_t flags = 0;
4882         unsigned int i;
4883         int rc;
4884
4885         /* Older FW does not have error recovery support */
4886         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4887                 return 0;
4888
4889         if (!info) {
4890                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4891                                    sizeof(*info), 0);
4892                 bp->recovery_info = info;
4893                 if (info == NULL)
4894                         return -ENOMEM;
4895         } else {
4896                 memset(info, 0, sizeof(*info));
4897         }
4898
4899         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4900
4901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4902
4903         HWRM_CHECK_RESULT();
4904
4905         flags = rte_le_to_cpu_32(resp->flags);
4906         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4907                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4908         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4909                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4910
4911         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4912             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4913                 rc = -EINVAL;
4914                 goto err;
4915         }
4916
4917         /* FW returned values are in units of 100msec */
4918         info->driver_polling_freq =
4919                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4920         info->master_func_wait_period =
4921                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4922         info->normal_func_wait_period =
4923                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4924         info->master_func_wait_period_after_reset =
4925                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4926         info->max_bailout_time_after_reset =
4927                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4928         info->status_regs[BNXT_FW_STATUS_REG] =
4929                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4930         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4931                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4932         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4933                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4934         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4935                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4936         info->reg_array_cnt =
4937                 rte_le_to_cpu_32(resp->reg_array_cnt);
4938
4939         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4940                 rc = -EINVAL;
4941                 goto err;
4942         }
4943
4944         for (i = 0; i < info->reg_array_cnt; i++) {
4945                 info->reset_reg[i] =
4946                         rte_le_to_cpu_32(resp->reset_reg[i]);
4947                 info->reset_reg_val[i] =
4948                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4949                 info->delay_after_reset[i] =
4950                         resp->delay_after_reset[i];
4951         }
4952 err:
4953         HWRM_UNLOCK();
4954
4955         /* Map the FW status registers */
4956         if (!rc)
4957                 rc = bnxt_map_fw_health_status_regs(bp);
4958
4959         if (rc) {
4960                 rte_free(bp->recovery_info);
4961                 bp->recovery_info = NULL;
4962         }
4963         return rc;
4964 }
4965
4966 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4967 {
4968         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4969         struct hwrm_fw_reset_input req = {0};
4970         int rc;
4971
4972         if (!BNXT_PF(bp))
4973                 return -EOPNOTSUPP;
4974
4975         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4976
4977         req.embedded_proc_type =
4978                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4979         req.selfrst_status =
4980                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4981         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4982
4983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4984                                     BNXT_USE_KONG(bp));
4985
4986         HWRM_CHECK_RESULT();
4987         HWRM_UNLOCK();
4988
4989         return rc;
4990 }
4991
4992 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4993 {
4994         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4995         struct hwrm_port_ts_query_input req = {0};
4996         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4997         uint32_t flags = 0;
4998         int rc;
4999
5000         if (!ptp)
5001                 return 0;
5002
5003         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5004
5005         switch (path) {
5006         case BNXT_PTP_FLAGS_PATH_TX:
5007                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5008                 break;
5009         case BNXT_PTP_FLAGS_PATH_RX:
5010                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5011                 break;
5012         case BNXT_PTP_FLAGS_CURRENT_TIME:
5013                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5014                 break;
5015         }
5016
5017         req.flags = rte_cpu_to_le_32(flags);
5018         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5019
5020         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5021
5022         HWRM_CHECK_RESULT();
5023
5024         if (timestamp) {
5025                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5026                 *timestamp |=
5027                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5028         }
5029         HWRM_UNLOCK();
5030
5031         return rc;
5032 }
5033
5034 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5035 {
5036         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5037                                         bp->hwrm_cmd_resp_addr;
5038         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5039         uint32_t flags = 0;
5040         int rc = 0;
5041
5042         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5043                 return rc;
5044
5045         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5046                 PMD_DRV_LOG(DEBUG,
5047                             "Not a PF or trusted VF. Command not supported\n");
5048                 return 0;
5049         }
5050
5051         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5053
5054         HWRM_CHECK_RESULT();
5055         flags = rte_le_to_cpu_32(resp->flags);
5056         HWRM_UNLOCK();
5057
5058         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5059                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5060                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5061         }
5062
5063         return rc;
5064 }