drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr =
 313                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                              struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct bnxt_vnic_info *vnic = NULL;
 371         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 372         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 373
 374         if (filter->fw_l2_filter_id == UINT64_MAX)
 375                 return 0;
 376
 377         if (filter->matching_l2_fltr_ptr)
 378                 l2_filter = filter->matching_l2_fltr_ptr;
 379
 380         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 381                     filter, l2_filter, l2_filter->l2_ref_cnt);
 382
 383         if (l2_filter->l2_ref_cnt == 0)
 384                 return 0;
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402         if (l2_filter->l2_ref_cnt == 0) {
 403                 vnic = l2_filter->vnic;
 404                 if (vnic) {
 405                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 406                                       bnxt_filter_info, next);
 407                         bnxt_free_filter(bp, l2_filter);
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 415                          uint16_t dst_id,
 416                          struct bnxt_filter_info *filter)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 420         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 421         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 422         const struct rte_eth_vmdq_rx_conf *conf =
 423                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 424         uint32_t enables = 0;
 425         uint16_t j = dst_id - 1;
 426
 427         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 428         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 429             conf->pool_map[j].pools & (1UL << j)) {
 430                 PMD_DRV_LOG(DEBUG,
 431                         "Add vlan %u to vmdq pool %u\n",
 432                         conf->pool_map[j].vlan_id, j);
 433
 434                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 435                 filter->enables |=
 436                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 437                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 438         }
 439
 440         if (filter->fw_l2_filter_id != UINT64_MAX)
 441                 bnxt_hwrm_clear_l2_filter(bp, filter);
 442
 443         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 444
 445         req.flags = rte_cpu_to_le_32(filter->flags);
 446
 447         enables = filter->enables |
 448               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 449         req.dst_id = rte_cpu_to_le_16(dst_id);
 450
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 453                 memcpy(req.l2_addr, filter->l2_addr,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 457                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 458                        RTE_ETHER_ADDR_LEN);
 459         if (enables &
 460             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 461                 req.l2_ovlan = filter->l2_ovlan;
 462         if (enables &
 463             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 464                 req.l2_ivlan = filter->l2_ivlan;
 465         if (enables &
 466             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 467                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 468         if (enables &
 469             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 470                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 471         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 472                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 473         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 474                 req.src_type = filter->src_type;
 475         if (filter->pri_hint) {
 476                 req.pri_hint = filter->pri_hint;
 477                 req.l2_filter_id_hint =
 478                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 479         }
 480
 481         req.enables = rte_cpu_to_le_32(enables);
 482
 483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 484
 485         HWRM_CHECK_RESULT();
 486
 487         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 488         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 489         HWRM_UNLOCK();
 490
 491         return rc;
 492 }
 493
 494 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 495 {
 496         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 497         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 498         uint32_t flags = 0;
 499         int rc;
 500
 501         if (!ptp)
 502                 return 0;
 503
 504         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 505
 506         if (ptp->rx_filter)
 507                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 508         else
 509                 flags |=
 510                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 511         if (ptp->tx_tstamp_en)
 512                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 513         else
 514                 flags |=
 515                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 516         req.flags = rte_cpu_to_le_32(flags);
 517         req.enables = rte_cpu_to_le_32
 518                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 519         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522         HWRM_UNLOCK();
 523
 524         return rc;
 525 }
 526
 527 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 531         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 532         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 533
 534         if (ptp)
 535                 return 0;
 536
 537         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 538
 539         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 540
 541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 542
 543         HWRM_CHECK_RESULT();
 544
 545         if (!BNXT_CHIP_THOR(bp) &&
 546             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 547                 return 0;
 548
 549         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 550                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 551
 552         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 553         if (!ptp)
 554                 return -ENOMEM;
 555
 556         if (!BNXT_CHIP_THOR(bp)) {
 557                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 559                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 560                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 561                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 562                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 563                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 564                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 565                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 566                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 567                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 568                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 569                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 570                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 571                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 572                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 573                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 574                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 575         }
 576
 577         ptp->bp = bp;
 578         bp->ptp_cfg = ptp;
 579
 580         return 0;
 581 }
 582
 583 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 584 {
 585         int rc = 0;
 586         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 587         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 588         uint16_t new_max_vfs;
 589         uint32_t flags;
 590         int i;
 591
 592         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 593
 594         req.fid = rte_cpu_to_le_16(0xffff);
 595
 596         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 597
 598         HWRM_CHECK_RESULT();
 599
 600         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 601         flags = rte_le_to_cpu_32(resp->flags);
 602         if (BNXT_PF(bp)) {
 603                 bp->pf.port_id = resp->port_id;
 604                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 605                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 606                 new_max_vfs = bp->pdev->max_vfs;
 607                 if (new_max_vfs != bp->pf.max_vfs) {
 608                         if (bp->pf.vf_info)
 609                                 rte_free(bp->pf.vf_info);
 610                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 611                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 612                         bp->pf.max_vfs = new_max_vfs;
 613                         for (i = 0; i < new_max_vfs; i++) {
 614                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 615                                 bp->pf.vf_info[i].vlan_table =
 616                                         rte_zmalloc("VF VLAN table",
 617                                                     getpagesize(),
 618                                                     getpagesize());
 619                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 620                                         PMD_DRV_LOG(ERR,
 621                                         "Fail to alloc VLAN table for VF %d\n",
 622                                         i);
 623                                 else
 624                                         rte_mem_lock_page(
 625                                                 bp->pf.vf_info[i].vlan_table);
 626                                 bp->pf.vf_info[i].vlan_as_table =
 627                                         rte_zmalloc("VF VLAN AS table",
 628                                                     getpagesize(),
 629                                                     getpagesize());
 630                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 631                                         PMD_DRV_LOG(ERR,
 632                                         "Alloc VLAN AS table for VF %d fail\n",
 633                                         i);
 634                                 else
 635                                         rte_mem_lock_page(
 636                                                bp->pf.vf_info[i].vlan_as_table);
 637                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 638                         }
 639                 }
 640         }
 641
 642         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 643         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 644         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 645         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 646         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 647         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 648         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 649         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 650         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 651         if (!BNXT_CHIP_THOR(bp))
 652                 bp->max_l2_ctx += bp->max_rx_em_flows;
 653         /* TODO: For now, do not support VMDq/RFS on VFs. */
 654         if (BNXT_PF(bp)) {
 655                 if (bp->pf.max_vfs)
 656                         bp->max_vnics = 1;
 657                 else
 658                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 659         } else {
 660                 bp->max_vnics = 1;
 661         }
 662         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 663         if (BNXT_PF(bp)) {
 664                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 665                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 666                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 667                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 668                         HWRM_UNLOCK();
 669                         bnxt_hwrm_ptp_qcfg(bp);
 670                 }
 671         }
 672
 673         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 674                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 675
 676         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 677                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 678                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 679         }
 680
 681         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 682                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 683
 684         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 685                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 686
 687         HWRM_UNLOCK();
 688
 689         return rc;
 690 }
 691
 692 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 693 {
 694         int rc;
 695
 696         rc = __bnxt_hwrm_func_qcaps(bp);
 697         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 698                 rc = bnxt_alloc_ctx_mem(bp);
 699                 if (rc)
 700                         return rc;
 701
 702                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 703                 if (!rc)
 704                         bp->flags |= BNXT_FLAG_NEW_RM;
 705         }
 706
 707         /* On older FW,
 708          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 709          * But the error can be ignored. Return success.
 710          */
 711
 712         return 0;
 713 }
 714
 715 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 716 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 717 {
 718         int rc = 0;
 719         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 720         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 721
 722         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 723
 724         req.target_id = rte_cpu_to_le_16(0xffff);
 725
 726         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 727
 728         HWRM_CHECK_RESULT();
 729
 730         if (rte_le_to_cpu_32(resp->flags) &
 731             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 732                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 733                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 734         }
 735
 736         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 737
 738         HWRM_UNLOCK();
 739
 740         return rc;
 741 }
 742
 743 int bnxt_hwrm_func_reset(struct bnxt *bp)
 744 {
 745         int rc = 0;
 746         struct hwrm_func_reset_input req = {.req_type = 0 };
 747         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 748
 749         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 750
 751         req.enables = rte_cpu_to_le_32(0);
 752
 753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 754
 755         HWRM_CHECK_RESULT();
 756         HWRM_UNLOCK();
 757
 758         return rc;
 759 }
 760
 761 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 762 {
 763         int rc;
 764         uint32_t flags = 0;
 765         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 766         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 767
 768         if (bp->flags & BNXT_FLAG_REGISTERED)
 769                 return 0;
 770
 771         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 772                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 773         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 774                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 775
 776         /* PFs and trusted VFs should indicate the support of the
 777          * Master capability on non Stingray platform
 778          */
 779         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 780                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 781
 782         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 783         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 784                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 785         req.ver_maj = RTE_VER_YEAR;
 786         req.ver_min = RTE_VER_MONTH;
 787         req.ver_upd = RTE_VER_MINOR;
 788
 789         if (BNXT_PF(bp)) {
 790                 req.enables |= rte_cpu_to_le_32(
 791                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 792                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 793                        RTE_MIN(sizeof(req.vf_req_fwd),
 794                                sizeof(bp->pf.vf_req_fwd)));
 795
 796                 /*
 797                  * PF can sniff HWRM API issued by VF. This can be set up by
 798                  * linux driver and inherited by the DPDK PF driver. Clear
 799                  * this HWRM sniffer list in FW because DPDK PF driver does
 800                  * not support this.
 801                  */
 802                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 803         }
 804
 805         req.flags = rte_cpu_to_le_32(flags);
 806
 807         req.async_event_fwd[0] |=
 808                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 809                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 810                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 811                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 812                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 813         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 814                 req.async_event_fwd[0] |=
 815                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 816         req.async_event_fwd[1] |=
 817                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 818                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 819
 820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 821
 822         HWRM_CHECK_RESULT();
 823
 824         flags = rte_le_to_cpu_32(resp->flags);
 825         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 826                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 827
 828         HWRM_UNLOCK();
 829
 830         bp->flags |= BNXT_FLAG_REGISTERED;
 831
 832         return rc;
 833 }
 834
 835 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 836 {
 837         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 838                 return 0;
 839
 840         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 841 }
 842
 843 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 844 {
 845         int rc;
 846         uint32_t flags = 0;
 847         uint32_t enables;
 848         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 849         struct hwrm_func_vf_cfg_input req = {0};
 850
 851         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 852
 853         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 854                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 855                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 856                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 857                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 858
 859         if (BNXT_HAS_RING_GRPS(bp)) {
 860                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 861                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 862         }
 863
 864         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 865         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 866                                             AGG_RING_MULTIPLIER);
 867         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 868         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 869                                               bp->tx_nr_rings +
 870                                               BNXT_NUM_ASYNC_CPR(bp));
 871         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 872         if (bp->vf_resv_strategy ==
 873             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 874                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 875                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 876                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 877                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 878                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 879                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 880         } else if (bp->vf_resv_strategy ==
 881                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 882                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 883                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 884         }
 885
 886         if (test)
 887                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 888                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 889                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 890                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 891                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 892                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 893
 894         if (test && BNXT_HAS_RING_GRPS(bp))
 895                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 896
 897         req.flags = rte_cpu_to_le_32(flags);
 898         req.enables |= rte_cpu_to_le_32(enables);
 899
 900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 901
 902         if (test)
 903                 HWRM_CHECK_RESULT_SILENT();
 904         else
 905                 HWRM_CHECK_RESULT();
 906
 907         HWRM_UNLOCK();
 908         return rc;
 909 }
 910
 911 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 912 {
 913         int rc;
 914         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 915         struct hwrm_func_resource_qcaps_input req = {0};
 916
 917         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 918         req.fid = rte_cpu_to_le_16(0xffff);
 919
 920         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 921
 922         HWRM_CHECK_RESULT_SILENT();
 923
 924         if (BNXT_VF(bp)) {
 925                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 926                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 927                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 928                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 929                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 930                 /* func_resource_qcaps does not return max_rx_em_flows.
 931                  * So use the value provided by func_qcaps.
 932                  */
 933                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 934                 if (!BNXT_CHIP_THOR(bp))
 935                         bp->max_l2_ctx += bp->max_rx_em_flows;
 936                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 937                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 938         }
 939         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 940         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 941         if (bp->vf_resv_strategy >
 942             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 943                 bp->vf_resv_strategy =
 944                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 945
 946         HWRM_UNLOCK();
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_ver_get(struct bnxt *bp)
 951 {
 952         int rc = 0;
 953         struct hwrm_ver_get_input req = {.req_type = 0 };
 954         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 955         uint32_t fw_version;
 956         uint16_t max_resp_len;
 957         char type[RTE_MEMZONE_NAMESIZE];
 958         uint32_t dev_caps_cfg;
 959
 960         bp->max_req_len = HWRM_MAX_REQ_LEN;
 961         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 962
 963         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 964         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 965         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 966
 967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 968
 969         if (bp->flags & BNXT_FLAG_FW_RESET)
 970                 HWRM_CHECK_RESULT_SILENT();
 971         else
 972                 HWRM_CHECK_RESULT();
 973
 974         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 975                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 976                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 977                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 978         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 979                      (resp->hwrm_fw_min_8b << 16) |
 980                      (resp->hwrm_fw_bld_8b << 8) |
 981                      resp->hwrm_fw_rsvd_8b;
 982         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 983                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 984
 985         fw_version = resp->hwrm_intf_maj_8b << 16;
 986         fw_version |= resp->hwrm_intf_min_8b << 8;
 987         fw_version |= resp->hwrm_intf_upd_8b;
 988         bp->hwrm_spec_code = fw_version;
 989
 990         /* def_req_timeout value is in milliseconds */
 991         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 992         /* convert timeout to usec */
 993         bp->hwrm_cmd_timeout *= 1000;
 994         if (!bp->hwrm_cmd_timeout)
 995                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 996
 997         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 998                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 999                 rc = -EINVAL;
1000                 goto error;
1001         }
1002
1003         if (bp->max_req_len > resp->max_req_win_len) {
1004                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1005                 rc = -EINVAL;
1006         }
1007         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1008         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1009         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1010                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1011
1012         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1013         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1014
1015         if (bp->max_resp_len != max_resp_len) {
1016                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1017                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1018                         bp->pdev->addr.devid, bp->pdev->addr.function);
1019
1020                 rte_free(bp->hwrm_cmd_resp_addr);
1021
1022                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1023                 if (bp->hwrm_cmd_resp_addr == NULL) {
1024                         rc = -ENOMEM;
1025                         goto error;
1026                 }
1027                 bp->hwrm_cmd_resp_dma_addr =
1028                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1029                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1030                         PMD_DRV_LOG(ERR,
1031                         "Unable to map response buffer to physical memory.\n");
1032                         rc = -ENOMEM;
1033                         goto error;
1034                 }
1035                 bp->max_resp_len = max_resp_len;
1036         }
1037
1038         if ((dev_caps_cfg &
1039                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1040             (dev_caps_cfg &
1041              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1042                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1043                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1044         }
1045
1046         if (((dev_caps_cfg &
1047               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1048              (dev_caps_cfg &
1049               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1050             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1051                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1052                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1053                         bp->pdev->addr.devid, bp->pdev->addr.function);
1054
1055                 rte_free(bp->hwrm_short_cmd_req_addr);
1056
1057                 bp->hwrm_short_cmd_req_addr =
1058                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1059                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1060                         rc = -ENOMEM;
1061                         goto error;
1062                 }
1063                 bp->hwrm_short_cmd_req_dma_addr =
1064                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1065                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1066                         rte_free(bp->hwrm_short_cmd_req_addr);
1067                         PMD_DRV_LOG(ERR,
1068                                 "Unable to map buffer to physical memory.\n");
1069                         rc = -ENOMEM;
1070                         goto error;
1071                 }
1072         }
1073         if (dev_caps_cfg &
1074             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1075                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1076                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1077         }
1078         if (dev_caps_cfg &
1079             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1080                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1081         if (dev_caps_cfg &
1082             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1083                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1084                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1085         }
1086
1087 error:
1088         HWRM_UNLOCK();
1089         return rc;
1090 }
1091
1092 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1093 {
1094         int rc;
1095         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1096         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1097
1098         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1099                 return 0;
1100
1101         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1102         req.flags = flags;
1103
1104         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1105
1106         HWRM_CHECK_RESULT();
1107         HWRM_UNLOCK();
1108
1109         return rc;
1110 }
1111
1112 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1113 {
1114         int rc = 0;
1115         struct hwrm_port_phy_cfg_input req = {0};
1116         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1117         uint32_t enables = 0;
1118
1119         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1120
1121         if (conf->link_up) {
1122                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1123                 if (bp->link_info.auto_mode && conf->link_speed) {
1124                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1125                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1126                 }
1127
1128                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1129                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1130                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1131                 /*
1132                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1133                  * any auto mode, even "none".
1134                  */
1135                 if (!conf->link_speed) {
1136                         /* No speeds specified. Enable AutoNeg - all speeds */
1137                         req.auto_mode =
1138                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1139                 }
1140                 /* AutoNeg - Advertise speeds specified. */
1141                 if (conf->auto_link_speed_mask &&
1142                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1143                         req.auto_mode =
1144                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1145                         req.auto_link_speed_mask =
1146                                 conf->auto_link_speed_mask;
1147                         enables |=
1148                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1149                 }
1150
1151                 req.auto_duplex = conf->duplex;
1152                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1153                 req.auto_pause = conf->auto_pause;
1154                 req.force_pause = conf->force_pause;
1155                 /* Set force_pause if there is no auto or if there is a force */
1156                 if (req.auto_pause && !req.force_pause)
1157                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1158                 else
1159                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1160
1161                 req.enables = rte_cpu_to_le_32(enables);
1162         } else {
1163                 req.flags =
1164                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1165                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1166         }
1167
1168         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1169
1170         HWRM_CHECK_RESULT();
1171         HWRM_UNLOCK();
1172
1173         return rc;
1174 }
1175
1176 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1177                                    struct bnxt_link_info *link_info)
1178 {
1179         int rc = 0;
1180         struct hwrm_port_phy_qcfg_input req = {0};
1181         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1182
1183         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1184
1185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1186
1187         HWRM_CHECK_RESULT();
1188
1189         link_info->phy_link_status = resp->link;
1190         link_info->link_up =
1191                 (link_info->phy_link_status ==
1192                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1193         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1194         link_info->duplex = resp->duplex_cfg;
1195         link_info->pause = resp->pause;
1196         link_info->auto_pause = resp->auto_pause;
1197         link_info->force_pause = resp->force_pause;
1198         link_info->auto_mode = resp->auto_mode;
1199         link_info->phy_type = resp->phy_type;
1200         link_info->media_type = resp->media_type;
1201
1202         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1203         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1204         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1205         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1206         link_info->phy_ver[0] = resp->phy_maj;
1207         link_info->phy_ver[1] = resp->phy_min;
1208         link_info->phy_ver[2] = resp->phy_bld;
1209
1210         HWRM_UNLOCK();
1211
1212         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1213         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1214         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1215         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1216         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1217                     link_info->auto_link_speed_mask);
1218         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1219                     link_info->force_link_speed);
1220
1221         return rc;
1222 }
1223
1224 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1225 {
1226         int i = 0;
1227
1228         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1229                 if (bp->tx_cos_queue[i].profile ==
1230                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1231                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1232                         return true;
1233                 }
1234         }
1235         return false;
1236 }
1237
1238 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1239 {
1240         int i = 0;
1241
1242         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1243                 if (bp->tx_cos_queue[i].profile !=
1244                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1245                     bp->tx_cos_queue[i].id !=
1246                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1247                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1248                         break;
1249                 }
1250         }
1251 }
1252
1253 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1254 {
1255         int rc = 0;
1256         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1257         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1258         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1259         int i;
1260
1261 get_rx_info:
1262         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1263
1264         req.flags = rte_cpu_to_le_32(dir);
1265         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1266         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1267             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1268                 req.drv_qmap_cap =
1269                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1271
1272         HWRM_CHECK_RESULT();
1273
1274         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1275                 GET_TX_QUEUE_INFO(0);
1276                 GET_TX_QUEUE_INFO(1);
1277                 GET_TX_QUEUE_INFO(2);
1278                 GET_TX_QUEUE_INFO(3);
1279                 GET_TX_QUEUE_INFO(4);
1280                 GET_TX_QUEUE_INFO(5);
1281                 GET_TX_QUEUE_INFO(6);
1282                 GET_TX_QUEUE_INFO(7);
1283         } else  {
1284                 GET_RX_QUEUE_INFO(0);
1285                 GET_RX_QUEUE_INFO(1);
1286                 GET_RX_QUEUE_INFO(2);
1287                 GET_RX_QUEUE_INFO(3);
1288                 GET_RX_QUEUE_INFO(4);
1289                 GET_RX_QUEUE_INFO(5);
1290                 GET_RX_QUEUE_INFO(6);
1291                 GET_RX_QUEUE_INFO(7);
1292         }
1293
1294         HWRM_UNLOCK();
1295
1296         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1297                 goto done;
1298
1299         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1300                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1301         } else {
1302                 int j;
1303
1304                 /* iterate and find the COSq profile to use for Tx */
1305                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1306                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1307                                 if (bp->tx_cos_queue[i].id != 0xff)
1308                                         bp->tx_cosq_id[j++] =
1309                                                 bp->tx_cos_queue[i].id;
1310                         }
1311                 } else {
1312                         /* When CoS classification is disabled, for normal NIC
1313                          * operations, ideally we should look to use LOSSY.
1314                          * If not found, fallback to the first valid profile
1315                          */
1316                         if (!bnxt_find_lossy_profile(bp))
1317                                 bnxt_find_first_valid_profile(bp);
1318
1319                 }
1320         }
1321
1322         bp->max_tc = resp->max_configurable_queues;
1323         bp->max_lltc = resp->max_configurable_lossless_queues;
1324         if (bp->max_tc > BNXT_MAX_QUEUE)
1325                 bp->max_tc = BNXT_MAX_QUEUE;
1326         bp->max_q = bp->max_tc;
1327
1328         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1329                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1330                 goto get_rx_info;
1331         }
1332
1333 done:
1334         return rc;
1335 }
1336
1337 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1338                          struct bnxt_ring *ring,
1339                          uint32_t ring_type, uint32_t map_index,
1340                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1341                          uint16_t tx_cosq_id)
1342 {
1343         int rc = 0;
1344         uint32_t enables = 0;
1345         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1346         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1347         struct rte_mempool *mb_pool;
1348         uint16_t rx_buf_size;
1349
1350         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1351
1352         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1353         req.fbo = rte_cpu_to_le_32(0);
1354         /* Association of ring index with doorbell index */
1355         req.logical_id = rte_cpu_to_le_16(map_index);
1356         req.length = rte_cpu_to_le_32(ring->ring_size);
1357
1358         switch (ring_type) {
1359         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1360                 req.ring_type = ring_type;
1361                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1362                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1363                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1364                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1365                         enables |=
1366                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1367                 break;
1368         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1369                 req.ring_type = ring_type;
1370                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1371                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1372                 if (BNXT_CHIP_THOR(bp)) {
1373                         mb_pool = bp->rx_queues[0]->mb_pool;
1374                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1375                                       RTE_PKTMBUF_HEADROOM;
1376                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1377                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1378                         enables |=
1379                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1380                 }
1381                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1382                         enables |=
1383                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1384                 break;
1385         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1386                 req.ring_type = ring_type;
1387                 if (BNXT_HAS_NQ(bp)) {
1388                         /* Association of cp ring with nq */
1389                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1390                         enables |=
1391                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1392                 }
1393                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1394                 break;
1395         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1396                 req.ring_type = ring_type;
1397                 req.page_size = BNXT_PAGE_SHFT;
1398                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1399                 break;
1400         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1401                 req.ring_type = ring_type;
1402                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1403
1404                 mb_pool = bp->rx_queues[0]->mb_pool;
1405                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1406                               RTE_PKTMBUF_HEADROOM;
1407                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1408                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1409
1410                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1411                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1412                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1413                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1414                 break;
1415         default:
1416                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1417                         ring_type);
1418                 HWRM_UNLOCK();
1419                 return -EINVAL;
1420         }
1421         req.enables = rte_cpu_to_le_32(enables);
1422
1423         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1424
1425         if (rc || resp->error_code) {
1426                 if (rc == 0 && resp->error_code)
1427                         rc = rte_le_to_cpu_16(resp->error_code);
1428                 switch (ring_type) {
1429                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1430                         PMD_DRV_LOG(ERR,
1431                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1432                         HWRM_UNLOCK();
1433                         return rc;
1434                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1435                         PMD_DRV_LOG(ERR,
1436                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1437                         HWRM_UNLOCK();
1438                         return rc;
1439                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1440                         PMD_DRV_LOG(ERR,
1441                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1442                                     rc);
1443                         HWRM_UNLOCK();
1444                         return rc;
1445                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1446                         PMD_DRV_LOG(ERR,
1447                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1448                         HWRM_UNLOCK();
1449                         return rc;
1450                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1451                         PMD_DRV_LOG(ERR,
1452                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1453                         HWRM_UNLOCK();
1454                         return rc;
1455                 default:
1456                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1457                         HWRM_UNLOCK();
1458                         return rc;
1459                 }
1460         }
1461
1462         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1463         HWRM_UNLOCK();
1464         return rc;
1465 }
1466
1467 int bnxt_hwrm_ring_free(struct bnxt *bp,
1468                         struct bnxt_ring *ring, uint32_t ring_type)
1469 {
1470         int rc;
1471         struct hwrm_ring_free_input req = {.req_type = 0 };
1472         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1473
1474         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1475
1476         req.ring_type = ring_type;
1477         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1478
1479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1480
1481         if (rc || resp->error_code) {
1482                 if (rc == 0 && resp->error_code)
1483                         rc = rte_le_to_cpu_16(resp->error_code);
1484                 HWRM_UNLOCK();
1485
1486                 switch (ring_type) {
1487                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1488                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1489                                 rc);
1490                         return rc;
1491                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1492                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1493                                 rc);
1494                         return rc;
1495                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1496                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1497                                 rc);
1498                         return rc;
1499                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1500                         PMD_DRV_LOG(ERR,
1501                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1502                         return rc;
1503                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1504                         PMD_DRV_LOG(ERR,
1505                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1506                         return rc;
1507                 default:
1508                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1509                         return rc;
1510                 }
1511         }
1512         HWRM_UNLOCK();
1513         return 0;
1514 }
1515
1516 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1517 {
1518         int rc = 0;
1519         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1520         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1521
1522         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1523
1524         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1525         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1526         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1527         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1528
1529         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1530
1531         HWRM_CHECK_RESULT();
1532
1533         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1534
1535         HWRM_UNLOCK();
1536
1537         return rc;
1538 }
1539
1540 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1541 {
1542         int rc;
1543         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1544         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1545
1546         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1547
1548         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1549
1550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1551
1552         HWRM_CHECK_RESULT();
1553         HWRM_UNLOCK();
1554
1555         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1556         return rc;
1557 }
1558
1559 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1560 {
1561         int rc = 0;
1562         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1563         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1564
1565         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1566                 return rc;
1567
1568         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1569
1570         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1571
1572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1573
1574         HWRM_CHECK_RESULT();
1575         HWRM_UNLOCK();
1576
1577         return rc;
1578 }
1579
1580 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1581                                 unsigned int idx __rte_unused)
1582 {
1583         int rc;
1584         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1585         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1586
1587         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1588
1589         req.update_period_ms = rte_cpu_to_le_32(0);
1590
1591         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1592
1593         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1594
1595         HWRM_CHECK_RESULT();
1596
1597         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1598
1599         HWRM_UNLOCK();
1600
1601         return rc;
1602 }
1603
1604 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1605                                 unsigned int idx __rte_unused)
1606 {
1607         int rc;
1608         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1609         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1610
1611         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1612
1613         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1614
1615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616
1617         HWRM_CHECK_RESULT();
1618         HWRM_UNLOCK();
1619
1620         return rc;
1621 }
1622
1623 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1624 {
1625         int rc = 0, i, j;
1626         struct hwrm_vnic_alloc_input req = { 0 };
1627         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1628
1629         if (!BNXT_HAS_RING_GRPS(bp))
1630                 goto skip_ring_grps;
1631
1632         /* map ring groups to this vnic */
1633         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1634                 vnic->start_grp_id, vnic->end_grp_id);
1635         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1636                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1637
1638         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1639         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1640         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1641         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642
1643 skip_ring_grps:
1644         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1645         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1646
1647         if (vnic->func_default)
1648                 req.flags =
1649                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1651
1652         HWRM_CHECK_RESULT();
1653
1654         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1655         HWRM_UNLOCK();
1656         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1657         return rc;
1658 }
1659
1660 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1661                                         struct bnxt_vnic_info *vnic,
1662                                         struct bnxt_plcmodes_cfg *pmode)
1663 {
1664         int rc = 0;
1665         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1666         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1667
1668         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1669
1670         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1671
1672         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1673
1674         HWRM_CHECK_RESULT();
1675
1676         pmode->flags = rte_le_to_cpu_32(resp->flags);
1677         /* dflt_vnic bit doesn't exist in the _cfg command */
1678         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1679         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1680         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1681         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1682
1683         HWRM_UNLOCK();
1684
1685         return rc;
1686 }
1687
1688 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1689                                        struct bnxt_vnic_info *vnic,
1690                                        struct bnxt_plcmodes_cfg *pmode)
1691 {
1692         int rc = 0;
1693         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1694         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1695
1696         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1697                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1698                 return rc;
1699         }
1700
1701         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1702
1703         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1704         req.flags = rte_cpu_to_le_32(pmode->flags);
1705         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1706         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1707         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1708         req.enables = rte_cpu_to_le_32(
1709             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1710             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1711             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1712         );
1713
1714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1715
1716         HWRM_CHECK_RESULT();
1717         HWRM_UNLOCK();
1718
1719         return rc;
1720 }
1721
1722 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1723 {
1724         int rc = 0;
1725         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1726         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1727         struct bnxt_plcmodes_cfg pmodes = { 0 };
1728         uint32_t ctx_enable_flag = 0;
1729         uint32_t enables = 0;
1730
1731         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1732                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1733                 return rc;
1734         }
1735
1736         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1737         if (rc)
1738                 return rc;
1739
1740         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1741
1742         if (BNXT_CHIP_THOR(bp)) {
1743                 int dflt_rxq = vnic->start_grp_id;
1744                 struct bnxt_rx_ring_info *rxr;
1745                 struct bnxt_cp_ring_info *cpr;
1746                 struct bnxt_rx_queue *rxq;
1747                 int i;
1748
1749                 /*
1750                  * The first active receive ring is used as the VNIC
1751                  * default receive ring. If there are no active receive
1752                  * rings (all corresponding receive queues are stopped),
1753                  * the first receive ring is used.
1754                  */
1755                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1756                         rxq = bp->eth_dev->data->rx_queues[i];
1757                         if (rxq->rx_started) {
1758                                 dflt_rxq = i;
1759                                 break;
1760                         }
1761                 }
1762
1763                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1764                 rxr = rxq->rx_ring;
1765                 cpr = rxq->cp_ring;
1766
1767                 req.default_rx_ring_id =
1768                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1769                 req.default_cmpl_ring_id =
1770                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1771                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1772                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1773                 goto config_mru;
1774         }
1775
1776         /* Only RSS support for now TBD: COS & LB */
1777         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1778         if (vnic->lb_rule != 0xffff)
1779                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1780         if (vnic->cos_rule != 0xffff)
1781                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1782         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1783                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1784                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1785         }
1786         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1787                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1788                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1789         }
1790
1791         enables |= ctx_enable_flag;
1792         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1793         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1794         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1795         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1796
1797 config_mru:
1798         req.enables = rte_cpu_to_le_32(enables);
1799         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1800         req.mru = rte_cpu_to_le_16(vnic->mru);
1801         /* Configure default VNIC only once. */
1802         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1803                 req.flags |=
1804                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1805                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1806         }
1807         if (vnic->vlan_strip)
1808                 req.flags |=
1809                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1810         if (vnic->bd_stall)
1811                 req.flags |=
1812                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1813         if (vnic->roce_dual)
1814                 req.flags |= rte_cpu_to_le_32(
1815                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1816         if (vnic->roce_only)
1817                 req.flags |= rte_cpu_to_le_32(
1818                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1819         if (vnic->rss_dflt_cr)
1820                 req.flags |= rte_cpu_to_le_32(
1821                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824
1825         HWRM_CHECK_RESULT();
1826         HWRM_UNLOCK();
1827
1828         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1829
1830         return rc;
1831 }
1832
1833 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1834                 int16_t fw_vf_id)
1835 {
1836         int rc = 0;
1837         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1838         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1839
1840         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1841                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1842                 return rc;
1843         }
1844         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1845
1846         req.enables =
1847                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1848         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1849         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1850
1851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1852
1853         HWRM_CHECK_RESULT();
1854
1855         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1856         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1857         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1858         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1859         vnic->mru = rte_le_to_cpu_16(resp->mru);
1860         vnic->func_default = rte_le_to_cpu_32(
1861                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1862         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1863                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1864         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1865                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1866         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1867                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1868         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1869                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1870         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1871                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1872
1873         HWRM_UNLOCK();
1874
1875         return rc;
1876 }
1877
1878 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1879                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1880 {
1881         int rc = 0;
1882         uint16_t ctx_id;
1883         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1884         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1885                                                 bp->hwrm_cmd_resp_addr;
1886
1887         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1888
1889         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1890         HWRM_CHECK_RESULT();
1891
1892         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1893         if (!BNXT_HAS_RING_GRPS(bp))
1894                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1895         else if (ctx_idx == 0)
1896                 vnic->rss_rule = ctx_id;
1897
1898         HWRM_UNLOCK();
1899
1900         return rc;
1901 }
1902
1903 static
1904 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1905                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1906 {
1907         int rc = 0;
1908         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1909         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1910                                                 bp->hwrm_cmd_resp_addr;
1911
1912         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1913                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1914                 return rc;
1915         }
1916         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1917
1918         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1919
1920         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1921
1922         HWRM_CHECK_RESULT();
1923         HWRM_UNLOCK();
1924
1925         return rc;
1926 }
1927
1928 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1929 {
1930         int rc = 0;
1931
1932         if (BNXT_CHIP_THOR(bp)) {
1933                 int j;
1934
1935                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1936                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1937                                                       vnic,
1938                                                       vnic->fw_grp_ids[j]);
1939                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1940                 }
1941                 vnic->num_lb_ctxts = 0;
1942         } else {
1943                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1944                 vnic->rss_rule = INVALID_HW_RING_ID;
1945         }
1946
1947         return rc;
1948 }
1949
1950 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1951 {
1952         int rc = 0;
1953         struct hwrm_vnic_free_input req = {.req_type = 0 };
1954         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1955
1956         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1957                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1958                 return rc;
1959         }
1960
1961         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1962
1963         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1964
1965         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1966
1967         HWRM_CHECK_RESULT();
1968         HWRM_UNLOCK();
1969
1970         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1971         /* Configure default VNIC again if necessary. */
1972         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1973                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1974
1975         return rc;
1976 }
1977
1978 static int
1979 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1980 {
1981         int i;
1982         int rc = 0;
1983         int nr_ctxs = vnic->num_lb_ctxts;
1984         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1985         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986
1987         for (i = 0; i < nr_ctxs; i++) {
1988                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1989
1990                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1991                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1992                 req.hash_mode_flags = vnic->hash_mode;
1993
1994                 req.hash_key_tbl_addr =
1995                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1996
1997                 req.ring_grp_tbl_addr =
1998                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1999                                          i * HW_HASH_INDEX_SIZE);
2000                 req.ring_table_pair_index = i;
2001                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2002
2003                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2004                                             BNXT_USE_CHIMP_MB);
2005
2006                 HWRM_CHECK_RESULT();
2007                 HWRM_UNLOCK();
2008         }
2009
2010         return rc;
2011 }
2012
2013 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2014                            struct bnxt_vnic_info *vnic)
2015 {
2016         int rc = 0;
2017         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2018         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2019
2020         if (!vnic->rss_table)
2021                 return 0;
2022
2023         if (BNXT_CHIP_THOR(bp))
2024                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2025
2026         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2027
2028         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2029         req.hash_mode_flags = vnic->hash_mode;
2030
2031         req.ring_grp_tbl_addr =
2032             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2033         req.hash_key_tbl_addr =
2034             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2035         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2036         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2037
2038         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2039
2040         HWRM_CHECK_RESULT();
2041         HWRM_UNLOCK();
2042
2043         return rc;
2044 }
2045
2046 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2047                         struct bnxt_vnic_info *vnic)
2048 {
2049         int rc = 0;
2050         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2051         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2052         uint16_t size;
2053
2054         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2055                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2056                 return rc;
2057         }
2058
2059         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2060
2061         req.flags = rte_cpu_to_le_32(
2062                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2063
2064         req.enables = rte_cpu_to_le_32(
2065                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2066
2067         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2068         size -= RTE_PKTMBUF_HEADROOM;
2069         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2070
2071         req.jumbo_thresh = rte_cpu_to_le_16(size);
2072         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2073
2074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075
2076         HWRM_CHECK_RESULT();
2077         HWRM_UNLOCK();
2078
2079         return rc;
2080 }
2081
2082 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2083                         struct bnxt_vnic_info *vnic, bool enable)
2084 {
2085         int rc = 0;
2086         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2087         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2088
2089         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2090                 if (enable)
2091                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2092                 return -ENOTSUP;
2093         }
2094
2095         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2096                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2097                 return 0;
2098         }
2099
2100         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2101
2102         if (enable) {
2103                 req.enables = rte_cpu_to_le_32(
2104                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2105                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2106                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2107                 req.flags = rte_cpu_to_le_32(
2108                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2109                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2110                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2112                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2113                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2114                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2115                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2116                 req.min_agg_len = rte_cpu_to_le_32(512);
2117         }
2118         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2119
2120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2121
2122         HWRM_CHECK_RESULT();
2123         HWRM_UNLOCK();
2124
2125         return rc;
2126 }
2127
2128 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2129 {
2130         struct hwrm_func_cfg_input req = {0};
2131         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2132         int rc;
2133
2134         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2135         req.enables = rte_cpu_to_le_32(
2136                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2137         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2138         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2139
2140         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2141
2142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2143         HWRM_CHECK_RESULT();
2144         HWRM_UNLOCK();
2145
2146         bp->pf.vf_info[vf].random_mac = false;
2147
2148         return rc;
2149 }
2150
2151 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2152                                   uint64_t *dropped)
2153 {
2154         int rc = 0;
2155         struct hwrm_func_qstats_input req = {.req_type = 0};
2156         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2157
2158         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2159
2160         req.fid = rte_cpu_to_le_16(fid);
2161
2162         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2163
2164         HWRM_CHECK_RESULT();
2165
2166         if (dropped)
2167                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2168
2169         HWRM_UNLOCK();
2170
2171         return rc;
2172 }
2173
2174 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2175                           struct rte_eth_stats *stats)
2176 {
2177         int rc = 0;
2178         struct hwrm_func_qstats_input req = {.req_type = 0};
2179         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2180
2181         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2182
2183         req.fid = rte_cpu_to_le_16(fid);
2184
2185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2186
2187         HWRM_CHECK_RESULT();
2188
2189         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2190         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2191         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2192         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2193         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2194         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2195
2196         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2197         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2198         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2199         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2200         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2201         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2202
2203         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2204         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2205         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2206
2207         HWRM_UNLOCK();
2208
2209         return rc;
2210 }
2211
2212 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2213 {
2214         int rc = 0;
2215         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2216         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2217
2218         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2219
2220         req.fid = rte_cpu_to_le_16(fid);
2221
2222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2223
2224         HWRM_CHECK_RESULT();
2225         HWRM_UNLOCK();
2226
2227         return rc;
2228 }
2229
2230 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2231 {
2232         unsigned int i;
2233         int rc = 0;
2234
2235         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2236                 struct bnxt_tx_queue *txq;
2237                 struct bnxt_rx_queue *rxq;
2238                 struct bnxt_cp_ring_info *cpr;
2239
2240                 if (i >= bp->rx_cp_nr_rings) {
2241                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2242                         cpr = txq->cp_ring;
2243                 } else {
2244                         rxq = bp->rx_queues[i];
2245                         cpr = rxq->cp_ring;
2246                 }
2247
2248                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2249                 if (rc)
2250                         return rc;
2251         }
2252         return 0;
2253 }
2254
2255 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2256 {
2257         int rc;
2258         unsigned int i;
2259         struct bnxt_cp_ring_info *cpr;
2260
2261         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2262
2263                 if (i >= bp->rx_cp_nr_rings) {
2264                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2265                 } else {
2266                         cpr = bp->rx_queues[i]->cp_ring;
2267                         if (BNXT_HAS_RING_GRPS(bp))
2268                                 bp->grp_info[i].fw_stats_ctx = -1;
2269                 }
2270                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2271                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2272                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2273                         if (rc)
2274                                 return rc;
2275                 }
2276         }
2277         return 0;
2278 }
2279
2280 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2281 {
2282         unsigned int i;
2283         int rc = 0;
2284
2285         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2286                 struct bnxt_tx_queue *txq;
2287                 struct bnxt_rx_queue *rxq;
2288                 struct bnxt_cp_ring_info *cpr;
2289
2290                 if (i >= bp->rx_cp_nr_rings) {
2291                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2292                         cpr = txq->cp_ring;
2293                 } else {
2294                         rxq = bp->rx_queues[i];
2295                         cpr = rxq->cp_ring;
2296                 }
2297
2298                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2299
2300                 if (rc)
2301                         return rc;
2302         }
2303         return rc;
2304 }
2305
2306 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2307 {
2308         uint16_t idx;
2309         uint32_t rc = 0;
2310
2311         if (!BNXT_HAS_RING_GRPS(bp))
2312                 return 0;
2313
2314         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2315
2316                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2317                         continue;
2318
2319                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2320
2321                 if (rc)
2322                         return rc;
2323         }
2324         return rc;
2325 }
2326
2327 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2328 {
2329         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2330
2331         bnxt_hwrm_ring_free(bp, cp_ring,
2332                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2333         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2334         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2335                                      sizeof(*cpr->cp_desc_ring));
2336         cpr->cp_raw_cons = 0;
2337         cpr->valid = 0;
2338 }
2339
2340 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2341 {
2342         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2343
2344         bnxt_hwrm_ring_free(bp, cp_ring,
2345                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2346         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2347         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2348                         sizeof(*cpr->cp_desc_ring));
2349         cpr->cp_raw_cons = 0;
2350         cpr->valid = 0;
2351 }
2352
2353 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2354 {
2355         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2356         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2357         struct bnxt_ring *ring = rxr->rx_ring_struct;
2358         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2359
2360         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2361                 bnxt_hwrm_ring_free(bp, ring,
2362                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2363                 ring->fw_ring_id = INVALID_HW_RING_ID;
2364                 if (BNXT_HAS_RING_GRPS(bp))
2365                         bp->grp_info[queue_index].rx_fw_ring_id =
2366                                                         INVALID_HW_RING_ID;
2367                 memset(rxr->rx_desc_ring, 0,
2368                        rxr->rx_ring_struct->ring_size *
2369                        sizeof(*rxr->rx_desc_ring));
2370                 memset(rxr->rx_buf_ring, 0,
2371                        rxr->rx_ring_struct->ring_size *
2372                        sizeof(*rxr->rx_buf_ring));
2373                 rxr->rx_prod = 0;
2374         }
2375         ring = rxr->ag_ring_struct;
2376         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2377                 bnxt_hwrm_ring_free(bp, ring,
2378                                     BNXT_CHIP_THOR(bp) ?
2379                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2380                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2381                 ring->fw_ring_id = INVALID_HW_RING_ID;
2382                 memset(rxr->ag_buf_ring, 0,
2383                        rxr->ag_ring_struct->ring_size *
2384                        sizeof(*rxr->ag_buf_ring));
2385                 rxr->ag_prod = 0;
2386                 if (BNXT_HAS_RING_GRPS(bp))
2387                         bp->grp_info[queue_index].ag_fw_ring_id =
2388                                                         INVALID_HW_RING_ID;
2389         }
2390         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2391                 bnxt_free_cp_ring(bp, cpr);
2392
2393         if (BNXT_HAS_RING_GRPS(bp))
2394                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2395 }
2396
2397 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2398 {
2399         unsigned int i;
2400
2401         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2402                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2403                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2404                 struct bnxt_ring *ring = txr->tx_ring_struct;
2405                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2406
2407                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2408                         bnxt_hwrm_ring_free(bp, ring,
2409                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2410                         ring->fw_ring_id = INVALID_HW_RING_ID;
2411                         memset(txr->tx_desc_ring, 0,
2412                                         txr->tx_ring_struct->ring_size *
2413                                         sizeof(*txr->tx_desc_ring));
2414                         memset(txr->tx_buf_ring, 0,
2415                                         txr->tx_ring_struct->ring_size *
2416                                         sizeof(*txr->tx_buf_ring));
2417                         txr->tx_prod = 0;
2418                         txr->tx_cons = 0;
2419                 }
2420                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2421                         bnxt_free_cp_ring(bp, cpr);
2422                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2423                 }
2424         }
2425
2426         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2427                 bnxt_free_hwrm_rx_ring(bp, i);
2428
2429         return 0;
2430 }
2431
2432 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2433 {
2434         uint16_t i;
2435         uint32_t rc = 0;
2436
2437         if (!BNXT_HAS_RING_GRPS(bp))
2438                 return 0;
2439
2440         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2441                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2442                 if (rc)
2443                         return rc;
2444         }
2445         return rc;
2446 }
2447
2448 /*
2449  * HWRM utility functions
2450  */
2451
2452 void bnxt_free_hwrm_resources(struct bnxt *bp)
2453 {
2454         /* Release memzone */
2455         rte_free(bp->hwrm_cmd_resp_addr);
2456         rte_free(bp->hwrm_short_cmd_req_addr);
2457         bp->hwrm_cmd_resp_addr = NULL;
2458         bp->hwrm_short_cmd_req_addr = NULL;
2459         bp->hwrm_cmd_resp_dma_addr = 0;
2460         bp->hwrm_short_cmd_req_dma_addr = 0;
2461 }
2462
2463 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2464 {
2465         struct rte_pci_device *pdev = bp->pdev;
2466         char type[RTE_MEMZONE_NAMESIZE];
2467
2468         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2469                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2470         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2471         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2472         if (bp->hwrm_cmd_resp_addr == NULL)
2473                 return -ENOMEM;
2474         bp->hwrm_cmd_resp_dma_addr =
2475                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2476         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2477                 PMD_DRV_LOG(ERR,
2478                         "unable to map response address to physical memory\n");
2479                 return -ENOMEM;
2480         }
2481         rte_spinlock_init(&bp->hwrm_lock);
2482
2483         return 0;
2484 }
2485
2486 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2487 {
2488         struct bnxt_filter_info *filter;
2489         int rc = 0;
2490
2491         STAILQ_FOREACH(filter, &vnic->filter, next) {
2492                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2493                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2494                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2495                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2496                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2497                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2498                 bnxt_free_filter(bp, filter);
2499         }
2500         return rc;
2501 }
2502
2503 static int
2504 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2505 {
2506         struct bnxt_filter_info *filter;
2507         struct rte_flow *flow;
2508         int rc = 0;
2509
2510         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2511                 flow = STAILQ_FIRST(&vnic->flow_list);
2512                 filter = flow->filter;
2513                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2514                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2515                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2516                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2517                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2518                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2519
2520                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2521                 rte_free(flow);
2522         }
2523         return rc;
2524 }
2525
2526 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2527 {
2528         struct bnxt_filter_info *filter;
2529         int rc = 0;
2530
2531         STAILQ_FOREACH(filter, &vnic->filter, next) {
2532                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2533                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2534                                                      filter);
2535                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2536                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2537                                                          filter);
2538                 else
2539                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2540                                                      filter);
2541                 if (rc)
2542                         break;
2543         }
2544         return rc;
2545 }
2546
2547 void bnxt_free_tunnel_ports(struct bnxt *bp)
2548 {
2549         if (bp->vxlan_port_cnt)
2550                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2551                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2552         bp->vxlan_port = 0;
2553         if (bp->geneve_port_cnt)
2554                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2555                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2556         bp->geneve_port = 0;
2557 }
2558
2559 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2560 {
2561         int i;
2562
2563         if (bp->vnic_info == NULL)
2564                 return;
2565
2566         /*
2567          * Cleanup VNICs in reverse order, to make sure the L2 filter
2568          * from vnic0 is last to be cleaned up.
2569          */
2570         for (i = bp->max_vnics - 1; i >= 0; i--) {
2571                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2572
2573                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2574                         continue;
2575
2576                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2577
2578                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2579
2580                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2581
2582                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2583
2584                 bnxt_hwrm_vnic_free(bp, vnic);
2585
2586                 rte_free(vnic->fw_grp_ids);
2587         }
2588         /* Ring resources */
2589         bnxt_free_all_hwrm_rings(bp);
2590         bnxt_free_all_hwrm_ring_grps(bp);
2591         bnxt_free_all_hwrm_stat_ctxs(bp);
2592         bnxt_free_tunnel_ports(bp);
2593 }
2594
2595 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2596 {
2597         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2598
2599         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2600                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2601
2602         switch (conf_link_speed) {
2603         case ETH_LINK_SPEED_10M_HD:
2604         case ETH_LINK_SPEED_100M_HD:
2605                 /* FALLTHROUGH */
2606                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2607         }
2608         return hw_link_duplex;
2609 }
2610
2611 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2612 {
2613         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2614 }
2615
2616 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2617 {
2618         uint16_t eth_link_speed = 0;
2619
2620         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2621                 return ETH_LINK_SPEED_AUTONEG;
2622
2623         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2624         case ETH_LINK_SPEED_100M:
2625         case ETH_LINK_SPEED_100M_HD:
2626                 /* FALLTHROUGH */
2627                 eth_link_speed =
2628                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2629                 break;
2630         case ETH_LINK_SPEED_1G:
2631                 eth_link_speed =
2632                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2633                 break;
2634         case ETH_LINK_SPEED_2_5G:
2635                 eth_link_speed =
2636                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2637                 break;
2638         case ETH_LINK_SPEED_10G:
2639                 eth_link_speed =
2640                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2641                 break;
2642         case ETH_LINK_SPEED_20G:
2643                 eth_link_speed =
2644                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2645                 break;
2646         case ETH_LINK_SPEED_25G:
2647                 eth_link_speed =
2648                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2649                 break;
2650         case ETH_LINK_SPEED_40G:
2651                 eth_link_speed =
2652                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2653                 break;
2654         case ETH_LINK_SPEED_50G:
2655                 eth_link_speed =
2656                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2657                 break;
2658         case ETH_LINK_SPEED_100G:
2659                 eth_link_speed =
2660                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2661                 break;
2662         default:
2663                 PMD_DRV_LOG(ERR,
2664                         "Unsupported link speed %d; default to AUTO\n",
2665                         conf_link_speed);
2666                 break;
2667         }
2668         return eth_link_speed;
2669 }
2670
2671 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2672                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2673                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2674                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2675
2676 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2677 {
2678         uint32_t one_speed;
2679
2680         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2681                 return 0;
2682
2683         if (link_speed & ETH_LINK_SPEED_FIXED) {
2684                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2685
2686                 if (one_speed & (one_speed - 1)) {
2687                         PMD_DRV_LOG(ERR,
2688                                 "Invalid advertised speeds (%u) for port %u\n",
2689                                 link_speed, port_id);
2690                         return -EINVAL;
2691                 }
2692                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2693                         PMD_DRV_LOG(ERR,
2694                                 "Unsupported advertised speed (%u) for port %u\n",
2695                                 link_speed, port_id);
2696                         return -EINVAL;
2697                 }
2698         } else {
2699                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2700                         PMD_DRV_LOG(ERR,
2701                                 "Unsupported advertised speeds (%u) for port %u\n",
2702                                 link_speed, port_id);
2703                         return -EINVAL;
2704                 }
2705         }
2706         return 0;
2707 }
2708
2709 static uint16_t
2710 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2711 {
2712         uint16_t ret = 0;
2713
2714         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2715                 if (bp->link_info.support_speeds)
2716                         return bp->link_info.support_speeds;
2717                 link_speed = BNXT_SUPPORTED_SPEEDS;
2718         }
2719
2720         if (link_speed & ETH_LINK_SPEED_100M)
2721                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2722         if (link_speed & ETH_LINK_SPEED_100M_HD)
2723                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2724         if (link_speed & ETH_LINK_SPEED_1G)
2725                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2726         if (link_speed & ETH_LINK_SPEED_2_5G)
2727                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2728         if (link_speed & ETH_LINK_SPEED_10G)
2729                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2730         if (link_speed & ETH_LINK_SPEED_20G)
2731                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2732         if (link_speed & ETH_LINK_SPEED_25G)
2733                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2734         if (link_speed & ETH_LINK_SPEED_40G)
2735                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2736         if (link_speed & ETH_LINK_SPEED_50G)
2737                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2738         if (link_speed & ETH_LINK_SPEED_100G)
2739                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2740         return ret;
2741 }
2742
2743 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2744 {
2745         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2746
2747         switch (hw_link_speed) {
2748         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2749                 eth_link_speed = ETH_SPEED_NUM_100M;
2750                 break;
2751         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2752                 eth_link_speed = ETH_SPEED_NUM_1G;
2753                 break;
2754         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2755                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2756                 break;
2757         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2758                 eth_link_speed = ETH_SPEED_NUM_10G;
2759                 break;
2760         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2761                 eth_link_speed = ETH_SPEED_NUM_20G;
2762                 break;
2763         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2764                 eth_link_speed = ETH_SPEED_NUM_25G;
2765                 break;
2766         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2767                 eth_link_speed = ETH_SPEED_NUM_40G;
2768                 break;
2769         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2770                 eth_link_speed = ETH_SPEED_NUM_50G;
2771                 break;
2772         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2773                 eth_link_speed = ETH_SPEED_NUM_100G;
2774                 break;
2775         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2776         default:
2777                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2778                         hw_link_speed);
2779                 break;
2780         }
2781         return eth_link_speed;
2782 }
2783
2784 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2785 {
2786         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2787
2788         switch (hw_link_duplex) {
2789         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2790         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2791                 /* FALLTHROUGH */
2792                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2793                 break;
2794         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2795                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2796                 break;
2797         default:
2798                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2799                         hw_link_duplex);
2800                 break;
2801         }
2802         return eth_link_duplex;
2803 }
2804
2805 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2806 {
2807         int rc = 0;
2808         struct bnxt_link_info *link_info = &bp->link_info;
2809
2810         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2811         if (rc) {
2812                 PMD_DRV_LOG(ERR,
2813                         "Get link config failed with rc %d\n", rc);
2814                 goto exit;
2815         }
2816         if (link_info->link_speed)
2817                 link->link_speed =
2818                         bnxt_parse_hw_link_speed(link_info->link_speed);
2819         else
2820                 link->link_speed = ETH_SPEED_NUM_NONE;
2821         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2822         link->link_status = link_info->link_up;
2823         link->link_autoneg = link_info->auto_mode ==
2824                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2825                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2826 exit:
2827         return rc;
2828 }
2829
2830 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2831 {
2832         int rc = 0;
2833         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2834         struct bnxt_link_info link_req;
2835         uint16_t speed, autoneg;
2836
2837         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2838                 return 0;
2839
2840         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2841                         bp->eth_dev->data->port_id);
2842         if (rc)
2843                 goto error;
2844
2845         memset(&link_req, 0, sizeof(link_req));
2846         link_req.link_up = link_up;
2847         if (!link_up)
2848                 goto port_phy_cfg;
2849
2850         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2851         if (BNXT_CHIP_THOR(bp) &&
2852             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2853                 /* 40G is not supported as part of media auto detect.
2854                  * The speed should be forced and autoneg disabled
2855                  * to configure 40G speed.
2856                  */
2857                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2858                 autoneg = 0;
2859         }
2860
2861         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2862         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2863         /* Autoneg can be done only when the FW allows.
2864          * When user configures fixed speed of 40G and later changes to
2865          * any other speed, auto_link_speed/force_link_speed is still set
2866          * to 40G until link comes up at new speed.
2867          */
2868         if (autoneg == 1 &&
2869             !(!BNXT_CHIP_THOR(bp) &&
2870               (bp->link_info.auto_link_speed ||
2871                bp->link_info.force_link_speed))) {
2872                 link_req.phy_flags |=
2873                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2874                 link_req.auto_link_speed_mask =
2875                         bnxt_parse_eth_link_speed_mask(bp,
2876                                                        dev_conf->link_speeds);
2877         } else {
2878                 if (bp->link_info.phy_type ==
2879                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2880                     bp->link_info.phy_type ==
2881                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2882                     bp->link_info.media_type ==
2883                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2884                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2885                         return -EINVAL;
2886                 }
2887
2888                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2889                 /* If user wants a particular speed try that first. */
2890                 if (speed)
2891                         link_req.link_speed = speed;
2892                 else if (bp->link_info.force_link_speed)
2893                         link_req.link_speed = bp->link_info.force_link_speed;
2894                 else
2895                         link_req.link_speed = bp->link_info.auto_link_speed;
2896         }
2897         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2898         link_req.auto_pause = bp->link_info.auto_pause;
2899         link_req.force_pause = bp->link_info.force_pause;
2900
2901 port_phy_cfg:
2902         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2903         if (rc) {
2904                 PMD_DRV_LOG(ERR,
2905                         "Set link config failed with rc %d\n", rc);
2906         }
2907
2908 error:
2909         return rc;
2910 }
2911
2912 /* JIRA 22088 */
2913 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2914 {
2915         struct hwrm_func_qcfg_input req = {0};
2916         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2917         uint16_t flags;
2918         int rc = 0;
2919
2920         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2921         req.fid = rte_cpu_to_le_16(0xffff);
2922
2923         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2924
2925         HWRM_CHECK_RESULT();
2926
2927         /* Hard Coded.. 0xfff VLAN ID mask */
2928         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2929         flags = rte_le_to_cpu_16(resp->flags);
2930         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2931                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2932
2933         if (BNXT_VF(bp) &&
2934             !BNXT_VF_IS_TRUSTED(bp) &&
2935             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2936                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2937                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2938         } else if (BNXT_VF(bp) &&
2939                    BNXT_VF_IS_TRUSTED(bp) &&
2940                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2941                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2942                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2943         }
2944
2945         if (mtu)
2946                 *mtu = rte_le_to_cpu_16(resp->mtu);
2947
2948         switch (resp->port_partition_type) {
2949         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2950         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2951         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2952                 /* FALLTHROUGH */
2953                 bp->port_partition_type = resp->port_partition_type;
2954                 break;
2955         default:
2956                 bp->port_partition_type = 0;
2957                 break;
2958         }
2959
2960         HWRM_UNLOCK();
2961
2962         return rc;
2963 }
2964
2965 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2966                                    struct hwrm_func_qcaps_output *qcaps)
2967 {
2968         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2969         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2970                sizeof(qcaps->mac_address));
2971         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2972         qcaps->max_rx_rings = fcfg->num_rx_rings;
2973         qcaps->max_tx_rings = fcfg->num_tx_rings;
2974         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2975         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2976         qcaps->max_vfs = 0;
2977         qcaps->first_vf_id = 0;
2978         qcaps->max_vnics = fcfg->num_vnics;
2979         qcaps->max_decap_records = 0;
2980         qcaps->max_encap_records = 0;
2981         qcaps->max_tx_wm_flows = 0;
2982         qcaps->max_tx_em_flows = 0;
2983         qcaps->max_rx_wm_flows = 0;
2984         qcaps->max_rx_em_flows = 0;
2985         qcaps->max_flow_id = 0;
2986         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2987         qcaps->max_sp_tx_rings = 0;
2988         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2989 }
2990
2991 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2992 {
2993         struct hwrm_func_cfg_input req = {0};
2994         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2995         uint32_t enables;
2996         int rc;
2997
2998         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2999                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3000                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3001                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3002                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3003                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3004                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3005                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3006                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3007
3008         if (BNXT_HAS_RING_GRPS(bp)) {
3009                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3010                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3011         } else if (BNXT_HAS_NQ(bp)) {
3012                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3013                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3014         }
3015
3016         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3017         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3018         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3019         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3020         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3021         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3022         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3023         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3024         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3025         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3026         req.fid = rte_cpu_to_le_16(0xffff);
3027         req.enables = rte_cpu_to_le_32(enables);
3028
3029         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3030
3031         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3032
3033         HWRM_CHECK_RESULT();
3034         HWRM_UNLOCK();
3035
3036         return rc;
3037 }
3038
3039 static void populate_vf_func_cfg_req(struct bnxt *bp,
3040                                      struct hwrm_func_cfg_input *req,
3041                                      int num_vfs)
3042 {
3043         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3044                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3045                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3046                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3047                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3048                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3049                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3050                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3051                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3052                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3053
3054         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3055                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3056                                     BNXT_NUM_VLANS);
3057         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3058         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3059                                                 (num_vfs + 1));
3060         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3061         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3062                                                (num_vfs + 1));
3063         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3064         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3065         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3066         /* TODO: For now, do not support VMDq/RFS on VFs. */
3067         req->num_vnics = rte_cpu_to_le_16(1);
3068         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3069                                                  (num_vfs + 1));
3070 }
3071
3072 static void add_random_mac_if_needed(struct bnxt *bp,
3073                                      struct hwrm_func_cfg_input *cfg_req,
3074                                      int vf)
3075 {
3076         struct rte_ether_addr mac;
3077
3078         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3079                 return;
3080
3081         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3082                 cfg_req->enables |=
3083                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3084                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3085                 bp->pf.vf_info[vf].random_mac = true;
3086         } else {
3087                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3088                         RTE_ETHER_ADDR_LEN);
3089         }
3090 }
3091
3092 static void reserve_resources_from_vf(struct bnxt *bp,
3093                                       struct hwrm_func_cfg_input *cfg_req,
3094                                       int vf)
3095 {
3096         struct hwrm_func_qcaps_input req = {0};
3097         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3098         int rc;
3099
3100         /* Get the actual allocated values now */
3101         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3102         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3104
3105         if (rc) {
3106                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3107                 copy_func_cfg_to_qcaps(cfg_req, resp);
3108         } else if (resp->error_code) {
3109                 rc = rte_le_to_cpu_16(resp->error_code);
3110                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3111                 copy_func_cfg_to_qcaps(cfg_req, resp);
3112         }
3113
3114         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3115         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3116         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3117         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3118         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3119         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3120         /*
3121          * TODO: While not supporting VMDq with VFs, max_vnics is always
3122          * forced to 1 in this case
3123          */
3124         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3125         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3126
3127         HWRM_UNLOCK();
3128 }
3129
3130 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3131 {
3132         struct hwrm_func_qcfg_input req = {0};
3133         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3134         int rc;
3135
3136         /* Check for zero MAC address */
3137         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3138         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3139         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3140         HWRM_CHECK_RESULT();
3141         rc = rte_le_to_cpu_16(resp->vlan);
3142
3143         HWRM_UNLOCK();
3144
3145         return rc;
3146 }
3147
3148 static int update_pf_resource_max(struct bnxt *bp)
3149 {
3150         struct hwrm_func_qcfg_input req = {0};
3151         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3152         int rc;
3153
3154         /* And copy the allocated numbers into the pf struct */
3155         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3156         req.fid = rte_cpu_to_le_16(0xffff);
3157         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3158         HWRM_CHECK_RESULT();
3159
3160         /* Only TX ring value reflects actual allocation? TODO */
3161         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3162         bp->pf.evb_mode = resp->evb_mode;
3163
3164         HWRM_UNLOCK();
3165
3166         return rc;
3167 }
3168
3169 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3170 {
3171         int rc;
3172
3173         if (!BNXT_PF(bp)) {
3174                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3175                 return -EINVAL;
3176         }
3177
3178         rc = bnxt_hwrm_func_qcaps(bp);
3179         if (rc)
3180                 return rc;
3181
3182         bp->pf.func_cfg_flags &=
3183                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3184                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3185         bp->pf.func_cfg_flags |=
3186                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3187         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3188         rc = __bnxt_hwrm_func_qcaps(bp);
3189         return rc;
3190 }
3191
3192 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3193 {
3194         struct hwrm_func_cfg_input req = {0};
3195         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3196         int i;
3197         size_t sz;
3198         int rc = 0;
3199         size_t req_buf_sz;
3200
3201         if (!BNXT_PF(bp)) {
3202                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3203                 return -EINVAL;
3204         }
3205
3206         rc = bnxt_hwrm_func_qcaps(bp);
3207
3208         if (rc)
3209                 return rc;
3210
3211         bp->pf.active_vfs = num_vfs;
3212
3213         /*
3214          * First, configure the PF to only use one TX ring.  This ensures that
3215          * there are enough rings for all VFs.
3216          *
3217          * If we don't do this, when we call func_alloc() later, we will lock
3218          * extra rings to the PF that won't be available during func_cfg() of
3219          * the VFs.
3220          *
3221          * This has been fixed with firmware versions above 20.6.54
3222          */
3223         bp->pf.func_cfg_flags &=
3224                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3225                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3226         bp->pf.func_cfg_flags |=
3227                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3228         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3229         if (rc)
3230                 return rc;
3231
3232         /*
3233          * Now, create and register a buffer to hold forwarded VF requests
3234          */
3235         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3236         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3237                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3238         if (bp->pf.vf_req_buf == NULL) {
3239                 rc = -ENOMEM;
3240                 goto error_free;
3241         }
3242         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3243                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3244         for (i = 0; i < num_vfs; i++)
3245                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3246                                         (i * HWRM_MAX_REQ_LEN);
3247
3248         rc = bnxt_hwrm_func_buf_rgtr(bp);
3249         if (rc)
3250                 goto error_free;
3251
3252         populate_vf_func_cfg_req(bp, &req, num_vfs);
3253
3254         bp->pf.active_vfs = 0;
3255         for (i = 0; i < num_vfs; i++) {
3256                 add_random_mac_if_needed(bp, &req, i);
3257
3258                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3259                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3260                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3261                 rc = bnxt_hwrm_send_message(bp,
3262                                             &req,
3263                                             sizeof(req),
3264                                             BNXT_USE_CHIMP_MB);
3265
3266                 /* Clear enable flag for next pass */
3267                 req.enables &= ~rte_cpu_to_le_32(
3268                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3269
3270                 if (rc || resp->error_code) {
3271                         PMD_DRV_LOG(ERR,
3272                                 "Failed to initizlie VF %d\n", i);
3273                         PMD_DRV_LOG(ERR,
3274                                 "Not all VFs available. (%d, %d)\n",
3275                                 rc, resp->error_code);
3276                         HWRM_UNLOCK();
3277                         break;
3278                 }
3279
3280                 HWRM_UNLOCK();
3281
3282                 reserve_resources_from_vf(bp, &req, i);
3283                 bp->pf.active_vfs++;
3284                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3285         }
3286
3287         /*
3288          * Now configure the PF to use "the rest" of the resources
3289          * We're using STD_TX_RING_MODE here though which will limit the TX
3290          * rings.  This will allow QoS to function properly.  Not setting this
3291          * will cause PF rings to break bandwidth settings.
3292          */
3293         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3294         if (rc)
3295                 goto error_free;
3296
3297         rc = update_pf_resource_max(bp);
3298         if (rc)
3299                 goto error_free;
3300
3301         return rc;
3302
3303 error_free:
3304         bnxt_hwrm_func_buf_unrgtr(bp);
3305         return rc;
3306 }
3307
3308 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3309 {
3310         struct hwrm_func_cfg_input req = {0};
3311         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3312         int rc;
3313
3314         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3315
3316         req.fid = rte_cpu_to_le_16(0xffff);
3317         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3318         req.evb_mode = bp->pf.evb_mode;
3319
3320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3321         HWRM_CHECK_RESULT();
3322         HWRM_UNLOCK();
3323
3324         return rc;
3325 }
3326
3327 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3328                                 uint8_t tunnel_type)
3329 {
3330         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3331         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3332         int rc = 0;
3333
3334         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3335         req.tunnel_type = tunnel_type;
3336         req.tunnel_dst_port_val = port;
3337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3338         HWRM_CHECK_RESULT();
3339
3340         switch (tunnel_type) {
3341         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3342                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3343                 bp->vxlan_port = port;
3344                 break;
3345         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3346                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3347                 bp->geneve_port = port;
3348                 break;
3349         default:
3350                 break;
3351         }
3352
3353         HWRM_UNLOCK();
3354
3355         return rc;
3356 }
3357
3358 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3359                                 uint8_t tunnel_type)
3360 {
3361         struct hwrm_tunnel_dst_port_free_input req = {0};
3362         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3363         int rc = 0;
3364
3365         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3366
3367         req.tunnel_type = tunnel_type;
3368         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3369         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3370
3371         HWRM_CHECK_RESULT();
3372         HWRM_UNLOCK();
3373
3374         return rc;
3375 }
3376
3377 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3378                                         uint32_t flags)
3379 {
3380         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3381         struct hwrm_func_cfg_input req = {0};
3382         int rc;
3383
3384         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3385
3386         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3387         req.flags = rte_cpu_to_le_32(flags);
3388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3389
3390         HWRM_CHECK_RESULT();
3391         HWRM_UNLOCK();
3392
3393         return rc;
3394 }
3395
3396 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3397 {
3398         uint32_t *flag = flagp;
3399
3400         vnic->flags = *flag;
3401 }
3402
3403 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3404 {
3405         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3406 }
3407
3408 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3409 {
3410         int rc = 0;
3411         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3412         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3413
3414         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3415
3416         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3417         req.req_buf_page_size = rte_cpu_to_le_16(
3418                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3419         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3420         req.req_buf_page_addr0 =
3421                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3422         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3423                 PMD_DRV_LOG(ERR,
3424                         "unable to map buffer address to physical memory\n");
3425                 return -ENOMEM;
3426         }
3427
3428         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3429
3430         HWRM_CHECK_RESULT();
3431         HWRM_UNLOCK();
3432
3433         return rc;
3434 }
3435
3436 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3437 {
3438         int rc = 0;
3439         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3440         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3441
3442         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3443                 return 0;
3444
3445         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3446
3447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3448
3449         HWRM_CHECK_RESULT();
3450         HWRM_UNLOCK();
3451
3452         return rc;
3453 }
3454
3455 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3456 {
3457         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3458         struct hwrm_func_cfg_input req = {0};
3459         int rc;
3460
3461         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3462
3463         req.fid = rte_cpu_to_le_16(0xffff);
3464         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3465         req.enables = rte_cpu_to_le_32(
3466                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3467         req.async_event_cr = rte_cpu_to_le_16(
3468                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3470
3471         HWRM_CHECK_RESULT();
3472         HWRM_UNLOCK();
3473
3474         return rc;
3475 }
3476
3477 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3478 {
3479         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3480         struct hwrm_func_vf_cfg_input req = {0};
3481         int rc;
3482
3483         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3484
3485         req.enables = rte_cpu_to_le_32(
3486                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3487         req.async_event_cr = rte_cpu_to_le_16(
3488                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3490
3491         HWRM_CHECK_RESULT();
3492         HWRM_UNLOCK();
3493
3494         return rc;
3495 }
3496
3497 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3498 {
3499         struct hwrm_func_cfg_input req = {0};
3500         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3501         uint16_t dflt_vlan, fid;
3502         uint32_t func_cfg_flags;
3503         int rc = 0;
3504
3505         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3506
3507         if (is_vf) {
3508                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3509                 fid = bp->pf.vf_info[vf].fid;
3510                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3511         } else {
3512                 fid = rte_cpu_to_le_16(0xffff);
3513                 func_cfg_flags = bp->pf.func_cfg_flags;
3514                 dflt_vlan = bp->vlan;
3515         }
3516
3517         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3518         req.fid = rte_cpu_to_le_16(fid);
3519         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3520         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3521
3522         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3523
3524         HWRM_CHECK_RESULT();
3525         HWRM_UNLOCK();
3526
3527         return rc;
3528 }
3529
3530 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3531                         uint16_t max_bw, uint16_t enables)
3532 {
3533         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3534         struct hwrm_func_cfg_input req = {0};
3535         int rc;
3536
3537         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3538
3539         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3540         req.enables |= rte_cpu_to_le_32(enables);
3541         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3542         req.max_bw = rte_cpu_to_le_32(max_bw);
3543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3544
3545         HWRM_CHECK_RESULT();
3546         HWRM_UNLOCK();
3547
3548         return rc;
3549 }
3550
3551 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3552 {
3553         struct hwrm_func_cfg_input req = {0};
3554         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3555         int rc = 0;
3556
3557         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3558
3559         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3560         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3561         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3562         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3563
3564         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3565
3566         HWRM_CHECK_RESULT();
3567         HWRM_UNLOCK();
3568
3569         return rc;
3570 }
3571
3572 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3573 {
3574         int rc;
3575
3576         if (BNXT_PF(bp))
3577                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3578         else
3579                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3580
3581         return rc;
3582 }
3583
3584 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3585                               void *encaped, size_t ec_size)
3586 {
3587         int rc = 0;
3588         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3589         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3590
3591         if (ec_size > sizeof(req.encap_request))
3592                 return -1;
3593
3594         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3595
3596         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3597         memcpy(req.encap_request, encaped, ec_size);
3598
3599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3600
3601         HWRM_CHECK_RESULT();
3602         HWRM_UNLOCK();
3603
3604         return rc;
3605 }
3606
3607 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3608                                        struct rte_ether_addr *mac)
3609 {
3610         struct hwrm_func_qcfg_input req = {0};
3611         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3612         int rc;
3613
3614         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3615
3616         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3618
3619         HWRM_CHECK_RESULT();
3620
3621         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3622
3623         HWRM_UNLOCK();
3624
3625         return rc;
3626 }
3627
3628 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3629                             void *encaped, size_t ec_size)
3630 {
3631         int rc = 0;
3632         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3633         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3634
3635         if (ec_size > sizeof(req.encap_request))
3636                 return -1;
3637
3638         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3639
3640         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3641         memcpy(req.encap_request, encaped, ec_size);
3642
3643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3644
3645         HWRM_CHECK_RESULT();
3646         HWRM_UNLOCK();
3647
3648         return rc;
3649 }
3650
3651 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3652                          struct rte_eth_stats *stats, uint8_t rx)
3653 {
3654         int rc = 0;
3655         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3656         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3657
3658         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3659
3660         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3661
3662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3663
3664         HWRM_CHECK_RESULT();
3665
3666         if (rx) {
3667                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3668                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3669                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3670                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3671                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3672                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3673                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3674                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3675         } else {
3676                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3677                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3678                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3679                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3680                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3681                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3682         }
3683
3684         HWRM_UNLOCK();
3685
3686         return rc;
3687 }
3688
3689 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3690 {
3691         struct hwrm_port_qstats_input req = {0};
3692         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3693         struct bnxt_pf_info *pf = &bp->pf;
3694         int rc;
3695
3696         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3697
3698         req.port_id = rte_cpu_to_le_16(pf->port_id);
3699         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3700         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3702
3703         HWRM_CHECK_RESULT();
3704         HWRM_UNLOCK();
3705
3706         return rc;
3707 }
3708
3709 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3710 {
3711         struct hwrm_port_clr_stats_input req = {0};
3712         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3713         struct bnxt_pf_info *pf = &bp->pf;
3714         int rc;
3715
3716         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3717         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3718             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3719                 return 0;
3720
3721         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3722
3723         req.port_id = rte_cpu_to_le_16(pf->port_id);
3724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3725
3726         HWRM_CHECK_RESULT();
3727         HWRM_UNLOCK();
3728
3729         return rc;
3730 }
3731
3732 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3733 {
3734         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3735         struct hwrm_port_led_qcaps_input req = {0};
3736         int rc;
3737
3738         if (BNXT_VF(bp))
3739                 return 0;
3740
3741         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3742         req.port_id = bp->pf.port_id;
3743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3744
3745         HWRM_CHECK_RESULT();
3746
3747         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3748                 unsigned int i;
3749
3750                 bp->num_leds = resp->num_leds;
3751                 memcpy(bp->leds, &resp->led0_id,
3752                         sizeof(bp->leds[0]) * bp->num_leds);
3753                 for (i = 0; i < bp->num_leds; i++) {
3754                         struct bnxt_led_info *led = &bp->leds[i];
3755
3756                         uint16_t caps = led->led_state_caps;
3757
3758                         if (!led->led_group_id ||
3759                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3760                                 bp->num_leds = 0;
3761                                 break;
3762                         }
3763                 }
3764         }
3765
3766         HWRM_UNLOCK();
3767
3768         return rc;
3769 }
3770
3771 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3772 {
3773         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3774         struct hwrm_port_led_cfg_input req = {0};
3775         struct bnxt_led_cfg *led_cfg;
3776         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3777         uint16_t duration = 0;
3778         int rc, i;
3779
3780         if (!bp->num_leds || BNXT_VF(bp))
3781                 return -EOPNOTSUPP;
3782
3783         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3784
3785         if (led_on) {
3786                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3787                 duration = rte_cpu_to_le_16(500);
3788         }
3789         req.port_id = bp->pf.port_id;
3790         req.num_leds = bp->num_leds;
3791         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3792         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3793                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3794                 led_cfg->led_id = bp->leds[i].led_id;
3795                 led_cfg->led_state = led_state;
3796                 led_cfg->led_blink_on = duration;
3797                 led_cfg->led_blink_off = duration;
3798                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3799         }
3800
3801         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3802
3803         HWRM_CHECK_RESULT();
3804         HWRM_UNLOCK();
3805
3806         return rc;
3807 }
3808
3809 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3810                                uint32_t *length)
3811 {
3812         int rc;
3813         struct hwrm_nvm_get_dir_info_input req = {0};
3814         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3815
3816         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3817
3818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3819
3820         HWRM_CHECK_RESULT();
3821
3822         *entries = rte_le_to_cpu_32(resp->entries);
3823         *length = rte_le_to_cpu_32(resp->entry_length);
3824
3825         HWRM_UNLOCK();
3826         return rc;
3827 }
3828
3829 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3830 {
3831         int rc;
3832         uint32_t dir_entries;
3833         uint32_t entry_length;
3834         uint8_t *buf;
3835         size_t buflen;
3836         rte_iova_t dma_handle;
3837         struct hwrm_nvm_get_dir_entries_input req = {0};
3838         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3839
3840         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3841         if (rc != 0)
3842                 return rc;
3843
3844         *data++ = dir_entries;
3845         *data++ = entry_length;
3846         len -= 2;
3847         memset(data, 0xff, len);
3848
3849         buflen = dir_entries * entry_length;
3850         buf = rte_malloc("nvm_dir", buflen, 0);
3851         if (buf == NULL)
3852                 return -ENOMEM;
3853         dma_handle = rte_malloc_virt2iova(buf);
3854         if (dma_handle == RTE_BAD_IOVA) {
3855                 PMD_DRV_LOG(ERR,
3856                         "unable to map response address to physical memory\n");
3857                 return -ENOMEM;
3858         }
3859         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3860         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3861         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3862
3863         if (rc == 0)
3864                 memcpy(data, buf, len > buflen ? buflen : len);
3865
3866         rte_free(buf);
3867         HWRM_CHECK_RESULT();
3868         HWRM_UNLOCK();
3869
3870         return rc;
3871 }
3872
3873 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3874                              uint32_t offset, uint32_t length,
3875                              uint8_t *data)
3876 {
3877         int rc;
3878         uint8_t *buf;
3879         rte_iova_t dma_handle;
3880         struct hwrm_nvm_read_input req = {0};
3881         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3882
3883         buf = rte_malloc("nvm_item", length, 0);
3884         if (!buf)
3885                 return -ENOMEM;
3886
3887         dma_handle = rte_malloc_virt2iova(buf);
3888         if (dma_handle == RTE_BAD_IOVA) {
3889                 PMD_DRV_LOG(ERR,
3890                         "unable to map response address to physical memory\n");
3891                 return -ENOMEM;
3892         }
3893         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3894         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3895         req.dir_idx = rte_cpu_to_le_16(index);
3896         req.offset = rte_cpu_to_le_32(offset);
3897         req.len = rte_cpu_to_le_32(length);
3898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3899         if (rc == 0)
3900                 memcpy(data, buf, length);
3901
3902         rte_free(buf);
3903         HWRM_CHECK_RESULT();
3904         HWRM_UNLOCK();
3905
3906         return rc;
3907 }
3908
3909 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3910 {
3911         int rc;
3912         struct hwrm_nvm_erase_dir_entry_input req = {0};
3913         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3914
3915         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3916         req.dir_idx = rte_cpu_to_le_16(index);
3917         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3918         HWRM_CHECK_RESULT();
3919         HWRM_UNLOCK();
3920
3921         return rc;
3922 }
3923
3924
3925 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3926                           uint16_t dir_ordinal, uint16_t dir_ext,
3927                           uint16_t dir_attr, const uint8_t *data,
3928                           size_t data_len)
3929 {
3930         int rc;
3931         struct hwrm_nvm_write_input req = {0};
3932         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3933         rte_iova_t dma_handle;
3934         uint8_t *buf;
3935
3936         buf = rte_malloc("nvm_write", data_len, 0);
3937         if (!buf)
3938                 return -ENOMEM;
3939
3940         dma_handle = rte_malloc_virt2iova(buf);
3941         if (dma_handle == RTE_BAD_IOVA) {
3942                 PMD_DRV_LOG(ERR,
3943                         "unable to map response address to physical memory\n");
3944                 return -ENOMEM;
3945         }
3946         memcpy(buf, data, data_len);
3947
3948         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3949
3950         req.dir_type = rte_cpu_to_le_16(dir_type);
3951         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3952         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3953         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3954         req.dir_data_length = rte_cpu_to_le_32(data_len);
3955         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3956
3957         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3958
3959         rte_free(buf);
3960         HWRM_CHECK_RESULT();
3961         HWRM_UNLOCK();
3962
3963         return rc;
3964 }
3965
3966 static void
3967 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3968 {
3969         uint32_t *count = cbdata;
3970
3971         *count = *count + 1;
3972 }
3973
3974 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3975                                      struct bnxt_vnic_info *vnic __rte_unused)
3976 {
3977         return 0;
3978 }
3979
3980 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3981 {
3982         uint32_t count = 0;
3983
3984         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3985             &count, bnxt_vnic_count_hwrm_stub);
3986
3987         return count;
3988 }
3989
3990 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3991                                         uint16_t *vnic_ids)
3992 {
3993         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3994         struct hwrm_func_vf_vnic_ids_query_output *resp =
3995                                                 bp->hwrm_cmd_resp_addr;
3996         int rc;
3997
3998         /* First query all VNIC ids */
3999         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4000
4001         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4002         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4003         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4004
4005         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4006                 HWRM_UNLOCK();
4007                 PMD_DRV_LOG(ERR,
4008                 "unable to map VNIC ID table address to physical memory\n");
4009                 return -ENOMEM;
4010         }
4011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4012         HWRM_CHECK_RESULT();
4013         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4014
4015         HWRM_UNLOCK();
4016
4017         return rc;
4018 }
4019
4020 /*
4021  * This function queries the VNIC IDs  for a specified VF. It then calls
4022  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4023  * Then it calls the hwrm_cb function to program this new vnic configuration.
4024  */
4025 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4026         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4027         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4028 {
4029         struct bnxt_vnic_info vnic;
4030         int rc = 0;
4031         int i, num_vnic_ids;
4032         uint16_t *vnic_ids;
4033         size_t vnic_id_sz;
4034         size_t sz;
4035
4036         /* First query all VNIC ids */
4037         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4038         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4039                         RTE_CACHE_LINE_SIZE);
4040         if (vnic_ids == NULL)
4041                 return -ENOMEM;
4042
4043         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4044                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4045
4046         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4047
4048         if (num_vnic_ids < 0)
4049                 return num_vnic_ids;
4050
4051         /* Retrieve VNIC, update bd_stall then update */
4052
4053         for (i = 0; i < num_vnic_ids; i++) {
4054                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4055                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4056                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4057                 if (rc)
4058                         break;
4059                 if (vnic.mru <= 4)      /* Indicates unallocated */
4060                         continue;
4061
4062                 vnic_cb(&vnic, cbdata);
4063
4064                 rc = hwrm_cb(bp, &vnic);
4065                 if (rc)
4066                         break;
4067         }
4068
4069         rte_free(vnic_ids);
4070
4071         return rc;
4072 }
4073
4074 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4075                                               bool on)
4076 {
4077         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4078         struct hwrm_func_cfg_input req = {0};
4079         int rc;
4080
4081         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4082
4083         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4084         req.enables |= rte_cpu_to_le_32(
4085                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4086         req.vlan_antispoof_mode = on ?
4087                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4088                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4089         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4090
4091         HWRM_CHECK_RESULT();
4092         HWRM_UNLOCK();
4093
4094         return rc;
4095 }
4096
4097 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4098 {
4099         struct bnxt_vnic_info vnic;
4100         uint16_t *vnic_ids;
4101         size_t vnic_id_sz;
4102         int num_vnic_ids, i;
4103         size_t sz;
4104         int rc;
4105
4106         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4107         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4108                         RTE_CACHE_LINE_SIZE);
4109         if (vnic_ids == NULL)
4110                 return -ENOMEM;
4111
4112         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4113                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4114
4115         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4116         if (rc <= 0)
4117                 goto exit;
4118         num_vnic_ids = rc;
4119
4120         /*
4121          * Loop through to find the default VNIC ID.
4122          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4123          * by sending the hwrm_func_qcfg command to the firmware.
4124          */
4125         for (i = 0; i < num_vnic_ids; i++) {
4126                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4127                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4128                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4129                                         bp->pf.first_vf_id + vf);
4130                 if (rc)
4131                         goto exit;
4132                 if (vnic.func_default) {
4133                         rte_free(vnic_ids);
4134                         return vnic.fw_vnic_id;
4135                 }
4136         }
4137         /* Could not find a default VNIC. */
4138         PMD_DRV_LOG(ERR, "No default VNIC\n");
4139 exit:
4140         rte_free(vnic_ids);
4141         return rc;
4142 }
4143
4144 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4145                          uint16_t dst_id,
4146                          struct bnxt_filter_info *filter)
4147 {
4148         int rc = 0;
4149         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4150         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4151         uint32_t enables = 0;
4152
4153         if (filter->fw_em_filter_id != UINT64_MAX)
4154                 bnxt_hwrm_clear_em_filter(bp, filter);
4155
4156         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4157
4158         req.flags = rte_cpu_to_le_32(filter->flags);
4159
4160         enables = filter->enables |
4161               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4162         req.dst_id = rte_cpu_to_le_16(dst_id);
4163
4164         if (filter->ip_addr_type) {
4165                 req.ip_addr_type = filter->ip_addr_type;
4166                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4167         }
4168         if (enables &
4169             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4170                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4171         if (enables &
4172             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4173                 memcpy(req.src_macaddr, filter->src_macaddr,
4174                        RTE_ETHER_ADDR_LEN);
4175         if (enables &
4176             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4177                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4178                        RTE_ETHER_ADDR_LEN);
4179         if (enables &
4180             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4181                 req.ovlan_vid = filter->l2_ovlan;
4182         if (enables &
4183             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4184                 req.ivlan_vid = filter->l2_ivlan;
4185         if (enables &
4186             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4187                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4188         if (enables &
4189             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4190                 req.ip_protocol = filter->ip_protocol;
4191         if (enables &
4192             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4193                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4194         if (enables &
4195             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4196                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4197         if (enables &
4198             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4199                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4200         if (enables &
4201             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4202                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4203         if (enables &
4204             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4205                 req.mirror_vnic_id = filter->mirror_vnic_id;
4206
4207         req.enables = rte_cpu_to_le_32(enables);
4208
4209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4210
4211         HWRM_CHECK_RESULT();
4212
4213         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4214         HWRM_UNLOCK();
4215
4216         return rc;
4217 }
4218
4219 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4220 {
4221         int rc = 0;
4222         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4223         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4224
4225         if (filter->fw_em_filter_id == UINT64_MAX)
4226                 return 0;
4227
4228         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4229
4230         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4231
4232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4233
4234         HWRM_CHECK_RESULT();
4235         HWRM_UNLOCK();
4236
4237         filter->fw_em_filter_id = UINT64_MAX;
4238         filter->fw_l2_filter_id = UINT64_MAX;
4239
4240         return 0;
4241 }
4242
4243 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4244                          uint16_t dst_id,
4245                          struct bnxt_filter_info *filter)
4246 {
4247         int rc = 0;
4248         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4249         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4250                                                 bp->hwrm_cmd_resp_addr;
4251         uint32_t enables = 0;
4252
4253         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4254                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4255
4256         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4257
4258         req.flags = rte_cpu_to_le_32(filter->flags);
4259
4260         enables = filter->enables |
4261               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4262         req.dst_id = rte_cpu_to_le_16(dst_id);
4263
4264         if (filter->ip_addr_type) {
4265                 req.ip_addr_type = filter->ip_addr_type;
4266                 enables |=
4267                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4268         }
4269         if (enables &
4270             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4271                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4272         if (enables &
4273             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4274                 memcpy(req.src_macaddr, filter->src_macaddr,
4275                        RTE_ETHER_ADDR_LEN);
4276         if (enables &
4277             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4278                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4279         if (enables &
4280             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4281                 req.ip_protocol = filter->ip_protocol;
4282         if (enables &
4283             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4284                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4285         if (enables &
4286             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4287                 req.src_ipaddr_mask[0] =
4288                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4289         if (enables &
4290             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4291                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4292         if (enables &
4293             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4294                 req.dst_ipaddr_mask[0] =
4295                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4296         if (enables &
4297             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4298                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4299         if (enables &
4300             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4301                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4302         if (enables &
4303             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4304                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4305         if (enables &
4306             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4307                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4308         if (enables &
4309             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4310                 req.mirror_vnic_id = filter->mirror_vnic_id;
4311
4312         req.enables = rte_cpu_to_le_32(enables);
4313
4314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4315
4316         HWRM_CHECK_RESULT();
4317
4318         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4319         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4320         HWRM_UNLOCK();
4321
4322         return rc;
4323 }
4324
4325 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4326                                 struct bnxt_filter_info *filter)
4327 {
4328         int rc = 0;
4329         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4330         struct hwrm_cfa_ntuple_filter_free_output *resp =
4331                                                 bp->hwrm_cmd_resp_addr;
4332
4333         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4334                 return 0;
4335
4336         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4337
4338         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4339
4340         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4341
4342         HWRM_CHECK_RESULT();
4343         HWRM_UNLOCK();
4344
4345         filter->fw_ntuple_filter_id = UINT64_MAX;
4346
4347         return 0;
4348 }
4349
4350 static int
4351 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4352 {
4353         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4354         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4355         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4356         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4357         uint16_t *ring_tbl = vnic->rss_table;
4358         int nr_ctxs = vnic->num_lb_ctxts;
4359         int max_rings = bp->rx_nr_rings;
4360         int i, j, k, cnt;
4361         int rc = 0;
4362
4363         for (i = 0, k = 0; i < nr_ctxs; i++) {
4364                 struct bnxt_rx_ring_info *rxr;
4365                 struct bnxt_cp_ring_info *cpr;
4366
4367                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4368
4369                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4370                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4371                 req.hash_mode_flags = vnic->hash_mode;
4372
4373                 req.ring_grp_tbl_addr =
4374                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4375                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4376                                      2 * sizeof(*ring_tbl));
4377                 req.hash_key_tbl_addr =
4378                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4379
4380                 req.ring_table_pair_index = i;
4381                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4382
4383                 for (j = 0; j < 64; j++) {
4384                         uint16_t ring_id;
4385
4386                         /* Find next active ring. */
4387                         for (cnt = 0; cnt < max_rings; cnt++) {
4388                                 if (rx_queue_state[k] !=
4389                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4390                                         break;
4391                                 if (++k == max_rings)
4392                                         k = 0;
4393                         }
4394
4395                         /* Return if no rings are active. */
4396                         if (cnt == max_rings) {
4397                                 HWRM_UNLOCK();
4398                                 return 0;
4399                         }
4400
4401                         /* Add rx/cp ring pair to RSS table. */
4402                         rxr = rxqs[k]->rx_ring;
4403                         cpr = rxqs[k]->cp_ring;
4404
4405                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4406                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4407                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4408                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4409
4410                         if (++k == max_rings)
4411                                 k = 0;
4412                 }
4413                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4414                                             BNXT_USE_CHIMP_MB);
4415
4416                 HWRM_CHECK_RESULT();
4417                 HWRM_UNLOCK();
4418         }
4419
4420         return rc;
4421 }
4422
4423 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4424 {
4425         unsigned int rss_idx, fw_idx, i;
4426
4427         if (!(vnic->rss_table && vnic->hash_type))
4428                 return 0;
4429
4430         if (BNXT_CHIP_THOR(bp))
4431                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4432
4433         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4434                 return 0;
4435
4436         if (vnic->rss_table && vnic->hash_type) {
4437                 /*
4438                  * Fill the RSS hash & redirection table with
4439                  * ring group ids for all VNICs
4440                  */
4441                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4442                         rss_idx++, fw_idx++) {
4443                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4444                                 fw_idx %= bp->rx_cp_nr_rings;
4445                                 if (vnic->fw_grp_ids[fw_idx] !=
4446                                     INVALID_HW_RING_ID)
4447                                         break;
4448                                 fw_idx++;
4449                         }
4450                         if (i == bp->rx_cp_nr_rings)
4451                                 return 0;
4452                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4453                 }
4454                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4455         }
4456
4457         return 0;
4458 }
4459
4460 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4461         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4462 {
4463         uint16_t flags;
4464
4465         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4466
4467         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4468         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4469
4470         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4471         req->num_cmpl_dma_aggr_during_int =
4472                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4473
4474         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4475
4476         /* min timer set to 1/2 of interrupt timer */
4477         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4478
4479         /* buf timer set to 1/4 of interrupt timer */
4480         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4481
4482         req->cmpl_aggr_dma_tmr_during_int =
4483                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4484
4485         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4486                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4487         req->flags = rte_cpu_to_le_16(flags);
4488 }
4489
4490 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4491                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4492 {
4493         struct hwrm_ring_aggint_qcaps_input req = {0};
4494         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4495         uint32_t enables;
4496         uint16_t flags;
4497         int rc;
4498
4499         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4500         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4501         HWRM_CHECK_RESULT();
4502
4503         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4504         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4505
4506         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4507                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4508         agg_req->flags = rte_cpu_to_le_16(flags);
4509         enables =
4510          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4511          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4512         agg_req->enables = rte_cpu_to_le_32(enables);
4513
4514         HWRM_UNLOCK();
4515         return rc;
4516 }
4517
4518 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4519                         struct bnxt_coal *coal, uint16_t ring_id)
4520 {
4521         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4522         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4523                                                 bp->hwrm_cmd_resp_addr;
4524         int rc;
4525
4526         /* Set ring coalesce parameters only for 100G NICs */
4527         if (BNXT_CHIP_THOR(bp)) {
4528                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4529                         return -1;
4530         } else if (bnxt_stratus_device(bp)) {
4531                 bnxt_hwrm_set_coal_params(coal, &req);
4532         } else {
4533                 return 0;
4534         }
4535
4536         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4537         req.ring_id = rte_cpu_to_le_16(ring_id);
4538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4539         HWRM_CHECK_RESULT();
4540         HWRM_UNLOCK();
4541         return 0;
4542 }
4543
4544 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4545 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4546 {
4547         struct hwrm_func_backing_store_qcaps_input req = {0};
4548         struct hwrm_func_backing_store_qcaps_output *resp =
4549                 bp->hwrm_cmd_resp_addr;
4550         struct bnxt_ctx_pg_info *ctx_pg;
4551         struct bnxt_ctx_mem_info *ctx;
4552         int total_alloc_len;
4553         int rc, i;
4554
4555         if (!BNXT_CHIP_THOR(bp) ||
4556             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4557             BNXT_VF(bp) ||
4558             bp->ctx)
4559                 return 0;
4560
4561         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4562         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4563         HWRM_CHECK_RESULT_SILENT();
4564
4565         total_alloc_len = sizeof(*ctx);
4566         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4567                           RTE_CACHE_LINE_SIZE);
4568         if (!ctx) {
4569                 rc = -ENOMEM;
4570                 goto ctx_err;
4571         }
4572
4573         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4574                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4575                             RTE_CACHE_LINE_SIZE);
4576         if (!ctx_pg) {
4577                 rc = -ENOMEM;
4578                 goto ctx_err;
4579         }
4580         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4581                 ctx->tqm_mem[i] = ctx_pg;
4582
4583         bp->ctx = ctx;
4584         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4585         ctx->qp_min_qp1_entries =
4586                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4587         ctx->qp_max_l2_entries =
4588                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4589         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4590         ctx->srq_max_l2_entries =
4591                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4592         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4593         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4594         ctx->cq_max_l2_entries =
4595                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4596         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4597         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4598         ctx->vnic_max_vnic_entries =
4599                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4600         ctx->vnic_max_ring_table_entries =
4601                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4602         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4603         ctx->stat_max_entries =
4604                 rte_le_to_cpu_32(resp->stat_max_entries);
4605         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4606         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4607         ctx->tqm_min_entries_per_ring =
4608                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4609         ctx->tqm_max_entries_per_ring =
4610                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4611         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4612         if (!ctx->tqm_entries_multiple)
4613                 ctx->tqm_entries_multiple = 1;
4614         ctx->mrav_max_entries =
4615                 rte_le_to_cpu_32(resp->mrav_max_entries);
4616         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4617         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4618         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4619 ctx_err:
4620         HWRM_UNLOCK();
4621         return rc;
4622 }
4623
4624 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4625 {
4626         struct hwrm_func_backing_store_cfg_input req = {0};
4627         struct hwrm_func_backing_store_cfg_output *resp =
4628                 bp->hwrm_cmd_resp_addr;
4629         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4630         struct bnxt_ctx_pg_info *ctx_pg;
4631         uint32_t *num_entries;
4632         uint64_t *pg_dir;
4633         uint8_t *pg_attr;
4634         uint32_t ena;
4635         int i, rc;
4636
4637         if (!ctx)
4638                 return 0;
4639
4640         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4641         req.enables = rte_cpu_to_le_32(enables);
4642
4643         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4644                 ctx_pg = &ctx->qp_mem;
4645                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4646                 req.qp_num_qp1_entries =
4647                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4648                 req.qp_num_l2_entries =
4649                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4650                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4651                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4652                                       &req.qpc_pg_size_qpc_lvl,
4653                                       &req.qpc_page_dir);
4654         }
4655
4656         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4657                 ctx_pg = &ctx->srq_mem;
4658                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4659                 req.srq_num_l2_entries =
4660                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4661                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4662                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4663                                       &req.srq_pg_size_srq_lvl,
4664                                       &req.srq_page_dir);
4665         }
4666
4667         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4668                 ctx_pg = &ctx->cq_mem;
4669                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4670                 req.cq_num_l2_entries =
4671                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4672                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4673                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4674                                       &req.cq_pg_size_cq_lvl,
4675                                       &req.cq_page_dir);
4676         }
4677
4678         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4679                 ctx_pg = &ctx->vnic_mem;
4680                 req.vnic_num_vnic_entries =
4681                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4682                 req.vnic_num_ring_table_entries =
4683                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4684                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4685                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4686                                       &req.vnic_pg_size_vnic_lvl,
4687                                       &req.vnic_page_dir);
4688         }
4689
4690         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4691                 ctx_pg = &ctx->stat_mem;
4692                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4693                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4694                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4695                                       &req.stat_pg_size_stat_lvl,
4696                                       &req.stat_page_dir);
4697         }
4698
4699         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4700         num_entries = &req.tqm_sp_num_entries;
4701         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4702         pg_dir = &req.tqm_sp_page_dir;
4703         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4704         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4705                 if (!(enables & ena))
4706                         continue;
4707
4708                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4709
4710                 ctx_pg = ctx->tqm_mem[i];
4711                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4712                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4713         }
4714
4715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4716         HWRM_CHECK_RESULT();
4717         HWRM_UNLOCK();
4718
4719         return rc;
4720 }
4721
4722 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4723 {
4724         struct hwrm_port_qstats_ext_input req = {0};
4725         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4726         struct bnxt_pf_info *pf = &bp->pf;
4727         int rc;
4728
4729         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4730               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4731                 return 0;
4732
4733         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4734
4735         req.port_id = rte_cpu_to_le_16(pf->port_id);
4736         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4737                 req.tx_stat_host_addr =
4738                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4739                 req.tx_stat_size =
4740                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4741         }
4742         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4743                 req.rx_stat_host_addr =
4744                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4745                 req.rx_stat_size =
4746                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4747         }
4748         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4749
4750         if (rc) {
4751                 bp->fw_rx_port_stats_ext_size = 0;
4752                 bp->fw_tx_port_stats_ext_size = 0;
4753         } else {
4754                 bp->fw_rx_port_stats_ext_size =
4755                         rte_le_to_cpu_16(resp->rx_stat_size);
4756                 bp->fw_tx_port_stats_ext_size =
4757                         rte_le_to_cpu_16(resp->tx_stat_size);
4758         }
4759
4760         HWRM_CHECK_RESULT();
4761         HWRM_UNLOCK();
4762
4763         return rc;
4764 }
4765
4766 int
4767 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4768 {
4769         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4770         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4771                 bp->hwrm_cmd_resp_addr;
4772         int rc = 0;
4773
4774         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4775         req.tunnel_type = type;
4776         req.dest_fid = bp->fw_fid;
4777         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4778         HWRM_CHECK_RESULT();
4779
4780         HWRM_UNLOCK();
4781
4782         return rc;
4783 }
4784
4785 int
4786 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4787 {
4788         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4789         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4790                 bp->hwrm_cmd_resp_addr;
4791         int rc = 0;
4792
4793         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4794         req.tunnel_type = type;
4795         req.dest_fid = bp->fw_fid;
4796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4797         HWRM_CHECK_RESULT();
4798
4799         HWRM_UNLOCK();
4800
4801         return rc;
4802 }
4803
4804 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4805 {
4806         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4807         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4808                 bp->hwrm_cmd_resp_addr;
4809         int rc = 0;
4810
4811         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4812         req.src_fid = bp->fw_fid;
4813         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4814         HWRM_CHECK_RESULT();
4815
4816         if (type)
4817                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4818
4819         HWRM_UNLOCK();
4820
4821         return rc;
4822 }
4823
4824 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4825                                    uint16_t *dst_fid)
4826 {
4827         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4828         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4829                 bp->hwrm_cmd_resp_addr;
4830         int rc = 0;
4831
4832         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4833         req.src_fid = bp->fw_fid;
4834         req.tunnel_type = tun_type;
4835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4836         HWRM_CHECK_RESULT();
4837
4838         if (dst_fid)
4839                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4840
4841         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4842
4843         HWRM_UNLOCK();
4844
4845         return rc;
4846 }
4847
4848 int bnxt_hwrm_set_mac(struct bnxt *bp)
4849 {
4850         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4851         struct hwrm_func_vf_cfg_input req = {0};
4852         int rc = 0;
4853
4854         if (!BNXT_VF(bp))
4855                 return 0;
4856
4857         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4858
4859         req.enables =
4860                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4861         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4862
4863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4864
4865         HWRM_CHECK_RESULT();
4866
4867         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4868         HWRM_UNLOCK();
4869
4870         return rc;
4871 }
4872
4873 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4874 {
4875         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4876         struct hwrm_func_drv_if_change_input req = {0};
4877         uint32_t flags;
4878         int rc;
4879
4880         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4881                 return 0;
4882
4883         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4884          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4885          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4886          */
4887         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4888                 return 0;
4889
4890         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4891
4892         if (up)
4893                 req.flags =
4894                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4895
4896         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4897
4898         HWRM_CHECK_RESULT();
4899         flags = rte_le_to_cpu_32(resp->flags);
4900         HWRM_UNLOCK();
4901
4902         if (!up)
4903                 return 0;
4904
4905         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4906                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4907                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4908         }
4909
4910         return 0;
4911 }
4912
4913 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4914 {
4915         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4916         struct bnxt_error_recovery_info *info = bp->recovery_info;
4917         struct hwrm_error_recovery_qcfg_input req = {0};
4918         uint32_t flags = 0;
4919         unsigned int i;
4920         int rc;
4921
4922         /* Older FW does not have error recovery support */
4923         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4924                 return 0;
4925
4926         if (!info) {
4927                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4928                                    sizeof(*info), 0);
4929                 bp->recovery_info = info;
4930                 if (info == NULL)
4931                         return -ENOMEM;
4932         } else {
4933                 memset(info, 0, sizeof(*info));
4934         }
4935
4936         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4937
4938         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4939
4940         HWRM_CHECK_RESULT();
4941
4942         flags = rte_le_to_cpu_32(resp->flags);
4943         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4944                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4945         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4946                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4947
4948         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4949             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4950                 rc = -EINVAL;
4951                 goto err;
4952         }
4953
4954         /* FW returned values are in units of 100msec */
4955         info->driver_polling_freq =
4956                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4957         info->master_func_wait_period =
4958                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4959         info->normal_func_wait_period =
4960                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4961         info->master_func_wait_period_after_reset =
4962                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4963         info->max_bailout_time_after_reset =
4964                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4965         info->status_regs[BNXT_FW_STATUS_REG] =
4966                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4967         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4968                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4969         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4970                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4971         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4972                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4973         info->reg_array_cnt =
4974                 rte_le_to_cpu_32(resp->reg_array_cnt);
4975
4976         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4977                 rc = -EINVAL;
4978                 goto err;
4979         }
4980
4981         for (i = 0; i < info->reg_array_cnt; i++) {
4982                 info->reset_reg[i] =
4983                         rte_le_to_cpu_32(resp->reset_reg[i]);
4984                 info->reset_reg_val[i] =
4985                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4986                 info->delay_after_reset[i] =
4987                         resp->delay_after_reset[i];
4988         }
4989 err:
4990         HWRM_UNLOCK();
4991
4992         /* Map the FW status registers */
4993         if (!rc)
4994                 rc = bnxt_map_fw_health_status_regs(bp);
4995
4996         if (rc) {
4997                 rte_free(bp->recovery_info);
4998                 bp->recovery_info = NULL;
4999         }
5000         return rc;
5001 }
5002
5003 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5004 {
5005         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5006         struct hwrm_fw_reset_input req = {0};
5007         int rc;
5008
5009         if (!BNXT_PF(bp))
5010                 return -EOPNOTSUPP;
5011
5012         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5013
5014         req.embedded_proc_type =
5015                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5016         req.selfrst_status =
5017                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5018         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5019
5020         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5021                                     BNXT_USE_KONG(bp));
5022
5023         HWRM_CHECK_RESULT();
5024         HWRM_UNLOCK();
5025
5026         return rc;
5027 }
5028
5029 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5030 {
5031         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5032         struct hwrm_port_ts_query_input req = {0};
5033         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5034         uint32_t flags = 0;
5035         int rc;
5036
5037         if (!ptp)
5038                 return 0;
5039
5040         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5041
5042         switch (path) {
5043         case BNXT_PTP_FLAGS_PATH_TX:
5044                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5045                 break;
5046         case BNXT_PTP_FLAGS_PATH_RX:
5047                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5048                 break;
5049         case BNXT_PTP_FLAGS_CURRENT_TIME:
5050                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5051                 break;
5052         }
5053
5054         req.flags = rte_cpu_to_le_32(flags);
5055         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5056
5057         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5058
5059         HWRM_CHECK_RESULT();
5060
5061         if (timestamp) {
5062                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5063                 *timestamp |=
5064                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5065         }
5066         HWRM_UNLOCK();
5067
5068         return rc;
5069 }
5070
5071 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5072 {
5073         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5074                                         bp->hwrm_cmd_resp_addr;
5075         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5076         uint32_t flags = 0;
5077         int rc = 0;
5078
5079         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5080                 return rc;
5081
5082         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5083                 PMD_DRV_LOG(DEBUG,
5084                             "Not a PF or trusted VF. Command not supported\n");
5085                 return 0;
5086         }
5087
5088         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5089         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5090
5091         HWRM_CHECK_RESULT();
5092         flags = rte_le_to_cpu_32(resp->flags);
5093         HWRM_UNLOCK();
5094
5095         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5096                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5097                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5098         }
5099
5100         return rc;
5101 }