drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 674 {
 675         int rc = 0;
 676         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 677         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 678         uint16_t new_max_vfs;
 679         uint32_t flags;
 680         int i;
 681
 682         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 683
 684         req.fid = rte_cpu_to_le_16(0xffff);
 685
 686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 687
 688         HWRM_CHECK_RESULT();
 689
 690         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 691         flags = rte_le_to_cpu_32(resp->flags);
 692         if (BNXT_PF(bp)) {
 693                 bp->pf.port_id = resp->port_id;
 694                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 695                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 696                 new_max_vfs = bp->pdev->max_vfs;
 697                 if (new_max_vfs != bp->pf.max_vfs) {
 698                         if (bp->pf.vf_info)
 699                                 rte_free(bp->pf.vf_info);
 700                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 701                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 702                         bp->pf.max_vfs = new_max_vfs;
 703                         for (i = 0; i < new_max_vfs; i++) {
 704                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 705                                 bp->pf.vf_info[i].vlan_table =
 706                                         rte_zmalloc("VF VLAN table",
 707                                                     getpagesize(),
 708                                                     getpagesize());
 709                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 710                                         PMD_DRV_LOG(ERR,
 711                                         "Fail to alloc VLAN table for VF %d\n",
 712                                         i);
 713                                 else
 714                                         rte_mem_lock_page(
 715                                                 bp->pf.vf_info[i].vlan_table);
 716                                 bp->pf.vf_info[i].vlan_as_table =
 717                                         rte_zmalloc("VF VLAN AS table",
 718                                                     getpagesize(),
 719                                                     getpagesize());
 720                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 721                                         PMD_DRV_LOG(ERR,
 722                                         "Alloc VLAN AS table for VF %d fail\n",
 723                                         i);
 724                                 else
 725                                         rte_mem_lock_page(
 726                                                bp->pf.vf_info[i].vlan_as_table);
 727                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 728                         }
 729                 }
 730         }
 731
 732         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 733         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 734         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 735         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 736         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 737         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 738         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 739         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 740         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 741         if (!BNXT_CHIP_THOR(bp))
 742                 bp->max_l2_ctx += bp->max_rx_em_flows;
 743         /* TODO: For now, do not support VMDq/RFS on VFs. */
 744         if (BNXT_PF(bp)) {
 745                 if (bp->pf.max_vfs)
 746                         bp->max_vnics = 1;
 747                 else
 748                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 749         } else {
 750                 bp->max_vnics = 1;
 751         }
 752         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 753                     bp->max_l2_ctx, bp->max_vnics);
 754         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 755         if (BNXT_PF(bp)) {
 756                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 757                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 758                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 759                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 760                         HWRM_UNLOCK();
 761                         bnxt_hwrm_ptp_qcfg(bp);
 762                 }
 763         }
 764
 765         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 766                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 767
 768         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 769                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 770                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 771         }
 772
 773         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 774                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 775
 776         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 777                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 778
 779         HWRM_UNLOCK();
 780
 781         return rc;
 782 }
 783
 784 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 785 {
 786         int rc;
 787
 788         rc = __bnxt_hwrm_func_qcaps(bp);
 789         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 790                 rc = bnxt_alloc_ctx_mem(bp);
 791                 if (rc)
 792                         return rc;
 793
 794                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 795                 if (!rc)
 796                         bp->flags |= BNXT_FLAG_NEW_RM;
 797         }
 798
 799         /* On older FW,
 800          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 801          * But the error can be ignored. Return success.
 802          */
 803
 804         return 0;
 805 }
 806
 807 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 808 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 809 {
 810         int rc = 0;
 811         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 812         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 813
 814         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 815
 816         req.target_id = rte_cpu_to_le_16(0xffff);
 817
 818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 819
 820         HWRM_CHECK_RESULT();
 821
 822         if (rte_le_to_cpu_32(resp->flags) &
 823             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 824                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 825                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 826         }
 827
 828         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 829
 830         HWRM_UNLOCK();
 831
 832         return rc;
 833 }
 834
 835 int bnxt_hwrm_func_reset(struct bnxt *bp)
 836 {
 837         int rc = 0;
 838         struct hwrm_func_reset_input req = {.req_type = 0 };
 839         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 840
 841         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 842
 843         req.enables = rte_cpu_to_le_32(0);
 844
 845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 846
 847         HWRM_CHECK_RESULT();
 848         HWRM_UNLOCK();
 849
 850         return rc;
 851 }
 852
 853 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 854 {
 855         int rc;
 856         uint32_t flags = 0;
 857         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 858         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 859
 860         if (bp->flags & BNXT_FLAG_REGISTERED)
 861                 return 0;
 862
 863         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 864                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 865         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 866                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 867
 868         /* PFs and trusted VFs should indicate the support of the
 869          * Master capability on non Stingray platform
 870          */
 871         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 872                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 873
 874         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 875         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 876                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 877         req.ver_maj = RTE_VER_YEAR;
 878         req.ver_min = RTE_VER_MONTH;
 879         req.ver_upd = RTE_VER_MINOR;
 880
 881         if (BNXT_PF(bp)) {
 882                 req.enables |= rte_cpu_to_le_32(
 883                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 884                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 885                        RTE_MIN(sizeof(req.vf_req_fwd),
 886                                sizeof(bp->pf.vf_req_fwd)));
 887
 888                 /*
 889                  * PF can sniff HWRM API issued by VF. This can be set up by
 890                  * linux driver and inherited by the DPDK PF driver. Clear
 891                  * this HWRM sniffer list in FW because DPDK PF driver does
 892                  * not support this.
 893                  */
 894                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 895         }
 896
 897         req.flags = rte_cpu_to_le_32(flags);
 898
 899         req.async_event_fwd[0] |=
 900                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 901                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 902                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 903                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 904                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 905         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 906                 req.async_event_fwd[0] |=
 907                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 908         req.async_event_fwd[1] |=
 909                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 910                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 911         if (BNXT_PF(bp))
 912                 req.async_event_fwd[1] |=
 913                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 914
 915         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 916
 917         HWRM_CHECK_RESULT();
 918
 919         flags = rte_le_to_cpu_32(resp->flags);
 920         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 921                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 922
 923         HWRM_UNLOCK();
 924
 925         bp->flags |= BNXT_FLAG_REGISTERED;
 926
 927         return rc;
 928 }
 929
 930 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 931 {
 932         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 933                 return 0;
 934
 935         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 936 }
 937
 938 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 939 {
 940         int rc;
 941         uint32_t flags = 0;
 942         uint32_t enables;
 943         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 944         struct hwrm_func_vf_cfg_input req = {0};
 945
 946         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 947
 948         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 949                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 950                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 951                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 952                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 953
 954         if (BNXT_HAS_RING_GRPS(bp)) {
 955                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 956                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 957         }
 958
 959         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 960         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 961                                             AGG_RING_MULTIPLIER);
 962         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 963         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 964                                               bp->tx_nr_rings +
 965                                               BNXT_NUM_ASYNC_CPR(bp));
 966         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 967         if (bp->vf_resv_strategy ==
 968             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 969                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 970                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 971                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 972                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 973                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 974                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 975         } else if (bp->vf_resv_strategy ==
 976                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 977                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 978                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 979         }
 980
 981         if (test)
 982                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 983                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 984                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 985                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 986                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 987                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 988
 989         if (test && BNXT_HAS_RING_GRPS(bp))
 990                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 991
 992         req.flags = rte_cpu_to_le_32(flags);
 993         req.enables |= rte_cpu_to_le_32(enables);
 994
 995         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 996
 997         if (test)
 998                 HWRM_CHECK_RESULT_SILENT();
 999         else
1000                 HWRM_CHECK_RESULT();
1001
1002         HWRM_UNLOCK();
1003         return rc;
1004 }
1005
1006 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1007 {
1008         int rc;
1009         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1010         struct hwrm_func_resource_qcaps_input req = {0};
1011
1012         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1013         req.fid = rte_cpu_to_le_16(0xffff);
1014
1015         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1016
1017         HWRM_CHECK_RESULT_SILENT();
1018
1019         if (BNXT_VF(bp)) {
1020                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1021                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1022                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1023                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1024                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1025                 /* func_resource_qcaps does not return max_rx_em_flows.
1026                  * So use the value provided by func_qcaps.
1027                  */
1028                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1029                 if (!BNXT_CHIP_THOR(bp))
1030                         bp->max_l2_ctx += bp->max_rx_em_flows;
1031                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1032                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1033         }
1034         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1035         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1036         if (bp->vf_resv_strategy >
1037             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1038                 bp->vf_resv_strategy =
1039                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1040
1041         HWRM_UNLOCK();
1042         return rc;
1043 }
1044
1045 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1046 {
1047         int rc = 0;
1048         struct hwrm_ver_get_input req = {.req_type = 0 };
1049         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1050         uint32_t fw_version;
1051         uint16_t max_resp_len;
1052         char type[RTE_MEMZONE_NAMESIZE];
1053         uint32_t dev_caps_cfg;
1054
1055         bp->max_req_len = HWRM_MAX_REQ_LEN;
1056         bp->hwrm_cmd_timeout = timeout;
1057         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1058
1059         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1060         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1061         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1062
1063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1064
1065         if (bp->flags & BNXT_FLAG_FW_RESET)
1066                 HWRM_CHECK_RESULT_SILENT();
1067         else
1068                 HWRM_CHECK_RESULT();
1069
1070         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1071                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1072                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1073                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1074         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1075                      (resp->hwrm_fw_min_8b << 16) |
1076                      (resp->hwrm_fw_bld_8b << 8) |
1077                      resp->hwrm_fw_rsvd_8b;
1078         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1079                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1080
1081         fw_version = resp->hwrm_intf_maj_8b << 16;
1082         fw_version |= resp->hwrm_intf_min_8b << 8;
1083         fw_version |= resp->hwrm_intf_upd_8b;
1084         bp->hwrm_spec_code = fw_version;
1085
1086         /* def_req_timeout value is in milliseconds */
1087         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1088         /* convert timeout to usec */
1089         bp->hwrm_cmd_timeout *= 1000;
1090         if (!bp->hwrm_cmd_timeout)
1091                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1092
1093         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1094                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1095                 rc = -EINVAL;
1096                 goto error;
1097         }
1098
1099         if (bp->max_req_len > resp->max_req_win_len) {
1100                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1101                 rc = -EINVAL;
1102         }
1103         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1104         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1105         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1106                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1107
1108         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1109         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1110
1111         if (bp->max_resp_len != max_resp_len) {
1112                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1113                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1114                         bp->pdev->addr.devid, bp->pdev->addr.function);
1115
1116                 rte_free(bp->hwrm_cmd_resp_addr);
1117
1118                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1119                 if (bp->hwrm_cmd_resp_addr == NULL) {
1120                         rc = -ENOMEM;
1121                         goto error;
1122                 }
1123                 bp->hwrm_cmd_resp_dma_addr =
1124                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1125                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1126                         PMD_DRV_LOG(ERR,
1127                         "Unable to map response buffer to physical memory.\n");
1128                         rc = -ENOMEM;
1129                         goto error;
1130                 }
1131                 bp->max_resp_len = max_resp_len;
1132         }
1133
1134         if ((dev_caps_cfg &
1135                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1136             (dev_caps_cfg &
1137              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1138                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1139                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1140         }
1141
1142         if (((dev_caps_cfg &
1143               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1144              (dev_caps_cfg &
1145               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1146             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1147                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1148                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1149                         bp->pdev->addr.devid, bp->pdev->addr.function);
1150
1151                 rte_free(bp->hwrm_short_cmd_req_addr);
1152
1153                 bp->hwrm_short_cmd_req_addr =
1154                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1155                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1156                         rc = -ENOMEM;
1157                         goto error;
1158                 }
1159                 bp->hwrm_short_cmd_req_dma_addr =
1160                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1161                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1162                         rte_free(bp->hwrm_short_cmd_req_addr);
1163                         PMD_DRV_LOG(ERR,
1164                                 "Unable to map buffer to physical memory.\n");
1165                         rc = -ENOMEM;
1166                         goto error;
1167                 }
1168         }
1169         if (dev_caps_cfg &
1170             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1171                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1172                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1173         }
1174         if (dev_caps_cfg &
1175             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1176                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1177         if (dev_caps_cfg &
1178             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1179                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1180                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1181         }
1182
1183         if (dev_caps_cfg &
1184             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1185                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1186                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1187         }
1188
1189
1190 error:
1191         HWRM_UNLOCK();
1192         return rc;
1193 }
1194
1195 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1196 {
1197         int rc;
1198         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1199         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1200
1201         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1202                 return 0;
1203
1204         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1205         req.flags = flags;
1206
1207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1208
1209         HWRM_CHECK_RESULT();
1210         HWRM_UNLOCK();
1211
1212         return rc;
1213 }
1214
1215 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1216 {
1217         int rc = 0;
1218         struct hwrm_port_phy_cfg_input req = {0};
1219         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1220         uint32_t enables = 0;
1221
1222         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1223
1224         if (conf->link_up) {
1225                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1226                 if (bp->link_info.auto_mode && conf->link_speed) {
1227                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1228                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1229                 }
1230
1231                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1232                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1233                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1234                 /*
1235                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1236                  * any auto mode, even "none".
1237                  */
1238                 if (!conf->link_speed) {
1239                         /* No speeds specified. Enable AutoNeg - all speeds */
1240                         req.auto_mode =
1241                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1242                 }
1243                 /* AutoNeg - Advertise speeds specified. */
1244                 if (conf->auto_link_speed_mask &&
1245                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1246                         req.auto_mode =
1247                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1248                         req.auto_link_speed_mask =
1249                                 conf->auto_link_speed_mask;
1250                         enables |=
1251                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1252                 }
1253
1254                 req.auto_duplex = conf->duplex;
1255                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1256                 req.auto_pause = conf->auto_pause;
1257                 req.force_pause = conf->force_pause;
1258                 /* Set force_pause if there is no auto or if there is a force */
1259                 if (req.auto_pause && !req.force_pause)
1260                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1261                 else
1262                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1263
1264                 req.enables = rte_cpu_to_le_32(enables);
1265         } else {
1266                 req.flags =
1267                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1268                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1269         }
1270
1271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1272
1273         HWRM_CHECK_RESULT();
1274         HWRM_UNLOCK();
1275
1276         return rc;
1277 }
1278
1279 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1280                                    struct bnxt_link_info *link_info)
1281 {
1282         int rc = 0;
1283         struct hwrm_port_phy_qcfg_input req = {0};
1284         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1285
1286         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1287
1288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1289
1290         HWRM_CHECK_RESULT();
1291
1292         link_info->phy_link_status = resp->link;
1293         link_info->link_up =
1294                 (link_info->phy_link_status ==
1295                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1296         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1297         link_info->duplex = resp->duplex_cfg;
1298         link_info->pause = resp->pause;
1299         link_info->auto_pause = resp->auto_pause;
1300         link_info->force_pause = resp->force_pause;
1301         link_info->auto_mode = resp->auto_mode;
1302         link_info->phy_type = resp->phy_type;
1303         link_info->media_type = resp->media_type;
1304
1305         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1306         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1307         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1308         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1309         link_info->phy_ver[0] = resp->phy_maj;
1310         link_info->phy_ver[1] = resp->phy_min;
1311         link_info->phy_ver[2] = resp->phy_bld;
1312
1313         HWRM_UNLOCK();
1314
1315         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1316         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1317         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1318         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1319         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1320                     link_info->auto_link_speed_mask);
1321         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1322                     link_info->force_link_speed);
1323
1324         return rc;
1325 }
1326
1327 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1328 {
1329         int i = 0;
1330
1331         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1332                 if (bp->tx_cos_queue[i].profile ==
1333                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1334                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1335                         return true;
1336                 }
1337         }
1338         return false;
1339 }
1340
1341 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1342 {
1343         int i = 0;
1344
1345         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1346                 if (bp->tx_cos_queue[i].profile !=
1347                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1348                     bp->tx_cos_queue[i].id !=
1349                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1350                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1351                         break;
1352                 }
1353         }
1354 }
1355
1356 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1357 {
1358         int rc = 0;
1359         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1360         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1361         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1362         int i;
1363
1364 get_rx_info:
1365         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1366
1367         req.flags = rte_cpu_to_le_32(dir);
1368         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1369         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1370             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1371                 req.drv_qmap_cap =
1372                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1373         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1374
1375         HWRM_CHECK_RESULT();
1376
1377         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1378                 GET_TX_QUEUE_INFO(0);
1379                 GET_TX_QUEUE_INFO(1);
1380                 GET_TX_QUEUE_INFO(2);
1381                 GET_TX_QUEUE_INFO(3);
1382                 GET_TX_QUEUE_INFO(4);
1383                 GET_TX_QUEUE_INFO(5);
1384                 GET_TX_QUEUE_INFO(6);
1385                 GET_TX_QUEUE_INFO(7);
1386         } else  {
1387                 GET_RX_QUEUE_INFO(0);
1388                 GET_RX_QUEUE_INFO(1);
1389                 GET_RX_QUEUE_INFO(2);
1390                 GET_RX_QUEUE_INFO(3);
1391                 GET_RX_QUEUE_INFO(4);
1392                 GET_RX_QUEUE_INFO(5);
1393                 GET_RX_QUEUE_INFO(6);
1394                 GET_RX_QUEUE_INFO(7);
1395         }
1396
1397         HWRM_UNLOCK();
1398
1399         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1400                 goto done;
1401
1402         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1403                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1404         } else {
1405                 int j;
1406
1407                 /* iterate and find the COSq profile to use for Tx */
1408                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1409                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1410                                 if (bp->tx_cos_queue[i].id != 0xff)
1411                                         bp->tx_cosq_id[j++] =
1412                                                 bp->tx_cos_queue[i].id;
1413                         }
1414                 } else {
1415                         /* When CoS classification is disabled, for normal NIC
1416                          * operations, ideally we should look to use LOSSY.
1417                          * If not found, fallback to the first valid profile
1418                          */
1419                         if (!bnxt_find_lossy_profile(bp))
1420                                 bnxt_find_first_valid_profile(bp);
1421
1422                 }
1423         }
1424
1425         bp->max_tc = resp->max_configurable_queues;
1426         bp->max_lltc = resp->max_configurable_lossless_queues;
1427         if (bp->max_tc > BNXT_MAX_QUEUE)
1428                 bp->max_tc = BNXT_MAX_QUEUE;
1429         bp->max_q = bp->max_tc;
1430
1431         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1432                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1433                 goto get_rx_info;
1434         }
1435
1436 done:
1437         return rc;
1438 }
1439
1440 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1441                          struct bnxt_ring *ring,
1442                          uint32_t ring_type, uint32_t map_index,
1443                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1444                          uint16_t tx_cosq_id)
1445 {
1446         int rc = 0;
1447         uint32_t enables = 0;
1448         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1449         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1450         struct rte_mempool *mb_pool;
1451         uint16_t rx_buf_size;
1452
1453         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1454
1455         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1456         req.fbo = rte_cpu_to_le_32(0);
1457         /* Association of ring index with doorbell index */
1458         req.logical_id = rte_cpu_to_le_16(map_index);
1459         req.length = rte_cpu_to_le_32(ring->ring_size);
1460
1461         switch (ring_type) {
1462         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1463                 req.ring_type = ring_type;
1464                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1465                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1466                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1467                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1468                         enables |=
1469                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1470                 break;
1471         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1472                 req.ring_type = ring_type;
1473                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1474                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1475                 if (BNXT_CHIP_THOR(bp)) {
1476                         mb_pool = bp->rx_queues[0]->mb_pool;
1477                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1478                                       RTE_PKTMBUF_HEADROOM;
1479                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1480                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1481                         enables |=
1482                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1483                 }
1484                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1485                         enables |=
1486                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1487                 break;
1488         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1489                 req.ring_type = ring_type;
1490                 if (BNXT_HAS_NQ(bp)) {
1491                         /* Association of cp ring with nq */
1492                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1493                         enables |=
1494                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1495                 }
1496                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1497                 break;
1498         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1499                 req.ring_type = ring_type;
1500                 req.page_size = BNXT_PAGE_SHFT;
1501                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1502                 break;
1503         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1504                 req.ring_type = ring_type;
1505                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1506
1507                 mb_pool = bp->rx_queues[0]->mb_pool;
1508                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1509                               RTE_PKTMBUF_HEADROOM;
1510                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1511                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1512
1513                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1514                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1515                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1516                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1517                 break;
1518         default:
1519                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1520                         ring_type);
1521                 HWRM_UNLOCK();
1522                 return -EINVAL;
1523         }
1524         req.enables = rte_cpu_to_le_32(enables);
1525
1526         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1527
1528         if (rc || resp->error_code) {
1529                 if (rc == 0 && resp->error_code)
1530                         rc = rte_le_to_cpu_16(resp->error_code);
1531                 switch (ring_type) {
1532                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1533                         PMD_DRV_LOG(ERR,
1534                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1535                         HWRM_UNLOCK();
1536                         return rc;
1537                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1538                         PMD_DRV_LOG(ERR,
1539                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1540                         HWRM_UNLOCK();
1541                         return rc;
1542                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1543                         PMD_DRV_LOG(ERR,
1544                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1545                                     rc);
1546                         HWRM_UNLOCK();
1547                         return rc;
1548                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1549                         PMD_DRV_LOG(ERR,
1550                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1551                         HWRM_UNLOCK();
1552                         return rc;
1553                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1554                         PMD_DRV_LOG(ERR,
1555                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1556                         HWRM_UNLOCK();
1557                         return rc;
1558                 default:
1559                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1560                         HWRM_UNLOCK();
1561                         return rc;
1562                 }
1563         }
1564
1565         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1566         HWRM_UNLOCK();
1567         return rc;
1568 }
1569
1570 int bnxt_hwrm_ring_free(struct bnxt *bp,
1571                         struct bnxt_ring *ring, uint32_t ring_type)
1572 {
1573         int rc;
1574         struct hwrm_ring_free_input req = {.req_type = 0 };
1575         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1576
1577         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1578
1579         req.ring_type = ring_type;
1580         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1581
1582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1583
1584         if (rc || resp->error_code) {
1585                 if (rc == 0 && resp->error_code)
1586                         rc = rte_le_to_cpu_16(resp->error_code);
1587                 HWRM_UNLOCK();
1588
1589                 switch (ring_type) {
1590                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1591                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1592                                 rc);
1593                         return rc;
1594                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1595                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1596                                 rc);
1597                         return rc;
1598                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1599                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1600                                 rc);
1601                         return rc;
1602                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1603                         PMD_DRV_LOG(ERR,
1604                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1605                         return rc;
1606                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1607                         PMD_DRV_LOG(ERR,
1608                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1609                         return rc;
1610                 default:
1611                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1612                         return rc;
1613                 }
1614         }
1615         HWRM_UNLOCK();
1616         return 0;
1617 }
1618
1619 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1620 {
1621         int rc = 0;
1622         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1623         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1624
1625         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1626
1627         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1628         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1629         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1630         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1631
1632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1633
1634         HWRM_CHECK_RESULT();
1635
1636         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1637
1638         HWRM_UNLOCK();
1639
1640         return rc;
1641 }
1642
1643 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1644 {
1645         int rc;
1646         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1647         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1648
1649         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1650
1651         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1652
1653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1654
1655         HWRM_CHECK_RESULT();
1656         HWRM_UNLOCK();
1657
1658         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1659         return rc;
1660 }
1661
1662 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1663 {
1664         int rc = 0;
1665         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1666         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1667
1668         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1669                 return rc;
1670
1671         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1672
1673         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1674
1675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1676
1677         HWRM_CHECK_RESULT();
1678         HWRM_UNLOCK();
1679
1680         return rc;
1681 }
1682
1683 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1684                                 unsigned int idx __rte_unused)
1685 {
1686         int rc;
1687         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1688         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1689
1690         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1691
1692         req.update_period_ms = rte_cpu_to_le_32(0);
1693
1694         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1695
1696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1697
1698         HWRM_CHECK_RESULT();
1699
1700         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1701
1702         HWRM_UNLOCK();
1703
1704         return rc;
1705 }
1706
1707 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1708                                 unsigned int idx __rte_unused)
1709 {
1710         int rc;
1711         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1712         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1713
1714         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1715
1716         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1717
1718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1719
1720         HWRM_CHECK_RESULT();
1721         HWRM_UNLOCK();
1722
1723         return rc;
1724 }
1725
1726 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1727 {
1728         int rc = 0, i, j;
1729         struct hwrm_vnic_alloc_input req = { 0 };
1730         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1731
1732         if (!BNXT_HAS_RING_GRPS(bp))
1733                 goto skip_ring_grps;
1734
1735         /* map ring groups to this vnic */
1736         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1737                 vnic->start_grp_id, vnic->end_grp_id);
1738         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1739                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1740
1741         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1742         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1743         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1744         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1745
1746 skip_ring_grps:
1747         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1748         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1749
1750         if (vnic->func_default)
1751                 req.flags =
1752                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1754
1755         HWRM_CHECK_RESULT();
1756
1757         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1758         HWRM_UNLOCK();
1759         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1760         return rc;
1761 }
1762
1763 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1764                                         struct bnxt_vnic_info *vnic,
1765                                         struct bnxt_plcmodes_cfg *pmode)
1766 {
1767         int rc = 0;
1768         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1769         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1770
1771         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1772
1773         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1774
1775         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1776
1777         HWRM_CHECK_RESULT();
1778
1779         pmode->flags = rte_le_to_cpu_32(resp->flags);
1780         /* dflt_vnic bit doesn't exist in the _cfg command */
1781         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1782         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1783         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1784         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1785
1786         HWRM_UNLOCK();
1787
1788         return rc;
1789 }
1790
1791 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1792                                        struct bnxt_vnic_info *vnic,
1793                                        struct bnxt_plcmodes_cfg *pmode)
1794 {
1795         int rc = 0;
1796         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1797         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1798
1799         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1800                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1801                 return rc;
1802         }
1803
1804         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1805
1806         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1807         req.flags = rte_cpu_to_le_32(pmode->flags);
1808         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1809         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1810         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1811         req.enables = rte_cpu_to_le_32(
1812             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1813             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1814             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1815         );
1816
1817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1818
1819         HWRM_CHECK_RESULT();
1820         HWRM_UNLOCK();
1821
1822         return rc;
1823 }
1824
1825 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1826 {
1827         int rc = 0;
1828         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1829         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1830         struct bnxt_plcmodes_cfg pmodes = { 0 };
1831         uint32_t ctx_enable_flag = 0;
1832         uint32_t enables = 0;
1833
1834         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1835                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1836                 return rc;
1837         }
1838
1839         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1840         if (rc)
1841                 return rc;
1842
1843         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1844
1845         if (BNXT_CHIP_THOR(bp)) {
1846                 int dflt_rxq = vnic->start_grp_id;
1847                 struct bnxt_rx_ring_info *rxr;
1848                 struct bnxt_cp_ring_info *cpr;
1849                 struct bnxt_rx_queue *rxq;
1850                 int i;
1851
1852                 /*
1853                  * The first active receive ring is used as the VNIC
1854                  * default receive ring. If there are no active receive
1855                  * rings (all corresponding receive queues are stopped),
1856                  * the first receive ring is used.
1857                  */
1858                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1859                         rxq = bp->eth_dev->data->rx_queues[i];
1860                         if (rxq->rx_started) {
1861                                 dflt_rxq = i;
1862                                 break;
1863                         }
1864                 }
1865
1866                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1867                 rxr = rxq->rx_ring;
1868                 cpr = rxq->cp_ring;
1869
1870                 req.default_rx_ring_id =
1871                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1872                 req.default_cmpl_ring_id =
1873                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1874                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1875                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1876                 goto config_mru;
1877         }
1878
1879         /* Only RSS support for now TBD: COS & LB */
1880         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1881         if (vnic->lb_rule != 0xffff)
1882                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1883         if (vnic->cos_rule != 0xffff)
1884                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1885         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1886                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1887                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1888         }
1889         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1890                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1891                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1892         }
1893
1894         enables |= ctx_enable_flag;
1895         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1896         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1897         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1898         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1899
1900 config_mru:
1901         req.enables = rte_cpu_to_le_32(enables);
1902         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1903         req.mru = rte_cpu_to_le_16(vnic->mru);
1904         /* Configure default VNIC only once. */
1905         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1906                 req.flags |=
1907                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1908                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1909         }
1910         if (vnic->vlan_strip)
1911                 req.flags |=
1912                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1913         if (vnic->bd_stall)
1914                 req.flags |=
1915                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1916         if (vnic->roce_dual)
1917                 req.flags |= rte_cpu_to_le_32(
1918                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1919         if (vnic->roce_only)
1920                 req.flags |= rte_cpu_to_le_32(
1921                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1922         if (vnic->rss_dflt_cr)
1923                 req.flags |= rte_cpu_to_le_32(
1924                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1925
1926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1927
1928         HWRM_CHECK_RESULT();
1929         HWRM_UNLOCK();
1930
1931         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1932
1933         return rc;
1934 }
1935
1936 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1937                 int16_t fw_vf_id)
1938 {
1939         int rc = 0;
1940         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1941         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1942
1943         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1944                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1945                 return rc;
1946         }
1947         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1948
1949         req.enables =
1950                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1951         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1952         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1953
1954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1955
1956         HWRM_CHECK_RESULT();
1957
1958         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1959         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1960         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1961         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1962         vnic->mru = rte_le_to_cpu_16(resp->mru);
1963         vnic->func_default = rte_le_to_cpu_32(
1964                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1965         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1966                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1967         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1968                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1969         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1970                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1971         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1972                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1973         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1974                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1975
1976         HWRM_UNLOCK();
1977
1978         return rc;
1979 }
1980
1981 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1982                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1983 {
1984         int rc = 0;
1985         uint16_t ctx_id;
1986         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1987         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1988                                                 bp->hwrm_cmd_resp_addr;
1989
1990         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1991
1992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1993         HWRM_CHECK_RESULT();
1994
1995         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1996         if (!BNXT_HAS_RING_GRPS(bp))
1997                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1998         else if (ctx_idx == 0)
1999                 vnic->rss_rule = ctx_id;
2000
2001         HWRM_UNLOCK();
2002
2003         return rc;
2004 }
2005
2006 static
2007 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2008                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2009 {
2010         int rc = 0;
2011         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2012         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2013                                                 bp->hwrm_cmd_resp_addr;
2014
2015         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2016                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2017                 return rc;
2018         }
2019         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2020
2021         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2022
2023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2024
2025         HWRM_CHECK_RESULT();
2026         HWRM_UNLOCK();
2027
2028         return rc;
2029 }
2030
2031 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2032 {
2033         int rc = 0;
2034
2035         if (BNXT_CHIP_THOR(bp)) {
2036                 int j;
2037
2038                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2039                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2040                                                       vnic,
2041                                                       vnic->fw_grp_ids[j]);
2042                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2043                 }
2044                 vnic->num_lb_ctxts = 0;
2045         } else {
2046                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2047                 vnic->rss_rule = INVALID_HW_RING_ID;
2048         }
2049
2050         return rc;
2051 }
2052
2053 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2054 {
2055         int rc = 0;
2056         struct hwrm_vnic_free_input req = {.req_type = 0 };
2057         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2058
2059         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2060                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2061                 return rc;
2062         }
2063
2064         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2065
2066         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2067
2068         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2069
2070         HWRM_CHECK_RESULT();
2071         HWRM_UNLOCK();
2072
2073         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2074         /* Configure default VNIC again if necessary. */
2075         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2076                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2077
2078         return rc;
2079 }
2080
2081 static int
2082 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2083 {
2084         int i;
2085         int rc = 0;
2086         int nr_ctxs = vnic->num_lb_ctxts;
2087         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2088         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2089
2090         for (i = 0; i < nr_ctxs; i++) {
2091                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2092
2093                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2094                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2095                 req.hash_mode_flags = vnic->hash_mode;
2096
2097                 req.hash_key_tbl_addr =
2098                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2099
2100                 req.ring_grp_tbl_addr =
2101                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2102                                          i * HW_HASH_INDEX_SIZE);
2103                 req.ring_table_pair_index = i;
2104                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2105
2106                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2107                                             BNXT_USE_CHIMP_MB);
2108
2109                 HWRM_CHECK_RESULT();
2110                 HWRM_UNLOCK();
2111         }
2112
2113         return rc;
2114 }
2115
2116 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2117                            struct bnxt_vnic_info *vnic)
2118 {
2119         int rc = 0;
2120         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2121         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2122
2123         if (!vnic->rss_table)
2124                 return 0;
2125
2126         if (BNXT_CHIP_THOR(bp))
2127                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2128
2129         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2130
2131         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2132         req.hash_mode_flags = vnic->hash_mode;
2133
2134         req.ring_grp_tbl_addr =
2135             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2136         req.hash_key_tbl_addr =
2137             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2138         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2139         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2140
2141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2142
2143         HWRM_CHECK_RESULT();
2144         HWRM_UNLOCK();
2145
2146         return rc;
2147 }
2148
2149 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2150                         struct bnxt_vnic_info *vnic)
2151 {
2152         int rc = 0;
2153         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2154         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2155         uint16_t size;
2156
2157         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2158                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2159                 return rc;
2160         }
2161
2162         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2163
2164         req.flags = rte_cpu_to_le_32(
2165                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2166
2167         req.enables = rte_cpu_to_le_32(
2168                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2169
2170         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2171         size -= RTE_PKTMBUF_HEADROOM;
2172         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2173
2174         req.jumbo_thresh = rte_cpu_to_le_16(size);
2175         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2176
2177         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2178
2179         HWRM_CHECK_RESULT();
2180         HWRM_UNLOCK();
2181
2182         return rc;
2183 }
2184
2185 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2186                         struct bnxt_vnic_info *vnic, bool enable)
2187 {
2188         int rc = 0;
2189         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2190         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2191
2192         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2193                 if (enable)
2194                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2195                 return -ENOTSUP;
2196         }
2197
2198         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2199                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2200                 return 0;
2201         }
2202
2203         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2204
2205         if (enable) {
2206                 req.enables = rte_cpu_to_le_32(
2207                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2208                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2209                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2210                 req.flags = rte_cpu_to_le_32(
2211                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2212                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2213                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2214                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2215                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2216                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2217                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2218                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2219                 req.min_agg_len = rte_cpu_to_le_32(512);
2220         }
2221         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2222
2223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2224
2225         HWRM_CHECK_RESULT();
2226         HWRM_UNLOCK();
2227
2228         return rc;
2229 }
2230
2231 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2232 {
2233         struct hwrm_func_cfg_input req = {0};
2234         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2235         int rc;
2236
2237         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2238         req.enables = rte_cpu_to_le_32(
2239                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2240         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2241         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2242
2243         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2244
2245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2246         HWRM_CHECK_RESULT();
2247         HWRM_UNLOCK();
2248
2249         bp->pf.vf_info[vf].random_mac = false;
2250
2251         return rc;
2252 }
2253
2254 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2255                                   uint64_t *dropped)
2256 {
2257         int rc = 0;
2258         struct hwrm_func_qstats_input req = {.req_type = 0};
2259         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2260
2261         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2262
2263         req.fid = rte_cpu_to_le_16(fid);
2264
2265         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2266
2267         HWRM_CHECK_RESULT();
2268
2269         if (dropped)
2270                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2271
2272         HWRM_UNLOCK();
2273
2274         return rc;
2275 }
2276
2277 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2278                           struct rte_eth_stats *stats,
2279                           struct hwrm_func_qstats_output *func_qstats)
2280 {
2281         int rc = 0;
2282         struct hwrm_func_qstats_input req = {.req_type = 0};
2283         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2284
2285         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2286
2287         req.fid = rte_cpu_to_le_16(fid);
2288
2289         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2290
2291         HWRM_CHECK_RESULT();
2292         if (func_qstats)
2293                 memcpy(func_qstats, resp,
2294                        sizeof(struct hwrm_func_qstats_output));
2295
2296         if (!stats)
2297                 goto exit;
2298
2299         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2300         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2301         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2302         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2303         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2304         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2305
2306         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2307         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2308         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2309         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2310         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2311         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2312
2313         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2314         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2315         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2316
2317 exit:
2318         HWRM_UNLOCK();
2319
2320         return rc;
2321 }
2322
2323 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2324 {
2325         int rc = 0;
2326         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2327         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2328
2329         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2330
2331         req.fid = rte_cpu_to_le_16(fid);
2332
2333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2334
2335         HWRM_CHECK_RESULT();
2336         HWRM_UNLOCK();
2337
2338         return rc;
2339 }
2340
2341 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2342 {
2343         unsigned int i;
2344         int rc = 0;
2345
2346         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2347                 struct bnxt_tx_queue *txq;
2348                 struct bnxt_rx_queue *rxq;
2349                 struct bnxt_cp_ring_info *cpr;
2350
2351                 if (i >= bp->rx_cp_nr_rings) {
2352                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2353                         cpr = txq->cp_ring;
2354                 } else {
2355                         rxq = bp->rx_queues[i];
2356                         cpr = rxq->cp_ring;
2357                 }
2358
2359                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2360                 if (rc)
2361                         return rc;
2362         }
2363         return 0;
2364 }
2365
2366 static int
2367 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2368 {
2369         int rc;
2370         unsigned int i;
2371         struct bnxt_cp_ring_info *cpr;
2372
2373         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2374
2375                 if (i >= bp->rx_cp_nr_rings) {
2376                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2377                 } else {
2378                         cpr = bp->rx_queues[i]->cp_ring;
2379                         if (BNXT_HAS_RING_GRPS(bp))
2380                                 bp->grp_info[i].fw_stats_ctx = -1;
2381                 }
2382                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2383                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2384                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2385                         if (rc)
2386                                 return rc;
2387                 }
2388         }
2389         return 0;
2390 }
2391
2392 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2393 {
2394         unsigned int i;
2395         int rc = 0;
2396
2397         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2398                 struct bnxt_tx_queue *txq;
2399                 struct bnxt_rx_queue *rxq;
2400                 struct bnxt_cp_ring_info *cpr;
2401
2402                 if (i >= bp->rx_cp_nr_rings) {
2403                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2404                         cpr = txq->cp_ring;
2405                 } else {
2406                         rxq = bp->rx_queues[i];
2407                         cpr = rxq->cp_ring;
2408                 }
2409
2410                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2411
2412                 if (rc)
2413                         return rc;
2414         }
2415         return rc;
2416 }
2417
2418 static int
2419 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2420 {
2421         uint16_t idx;
2422         uint32_t rc = 0;
2423
2424         if (!BNXT_HAS_RING_GRPS(bp))
2425                 return 0;
2426
2427         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2428
2429                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2430                         continue;
2431
2432                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2433
2434                 if (rc)
2435                         return rc;
2436         }
2437         return rc;
2438 }
2439
2440 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2441 {
2442         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2443
2444         bnxt_hwrm_ring_free(bp, cp_ring,
2445                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2446         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2447         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2448                                      sizeof(*cpr->cp_desc_ring));
2449         cpr->cp_raw_cons = 0;
2450         cpr->valid = 0;
2451 }
2452
2453 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2454 {
2455         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2456
2457         bnxt_hwrm_ring_free(bp, cp_ring,
2458                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2459         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2460         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2461                         sizeof(*cpr->cp_desc_ring));
2462         cpr->cp_raw_cons = 0;
2463         cpr->valid = 0;
2464 }
2465
2466 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2467 {
2468         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2469         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2470         struct bnxt_ring *ring = rxr->rx_ring_struct;
2471         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2472
2473         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2474                 bnxt_hwrm_ring_free(bp, ring,
2475                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2476                 ring->fw_ring_id = INVALID_HW_RING_ID;
2477                 if (BNXT_HAS_RING_GRPS(bp))
2478                         bp->grp_info[queue_index].rx_fw_ring_id =
2479                                                         INVALID_HW_RING_ID;
2480         }
2481         ring = rxr->ag_ring_struct;
2482         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2483                 bnxt_hwrm_ring_free(bp, ring,
2484                                     BNXT_CHIP_THOR(bp) ?
2485                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2486                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2487                 if (BNXT_HAS_RING_GRPS(bp))
2488                         bp->grp_info[queue_index].ag_fw_ring_id =
2489                                                         INVALID_HW_RING_ID;
2490         }
2491         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2492                 bnxt_free_cp_ring(bp, cpr);
2493
2494         if (BNXT_HAS_RING_GRPS(bp))
2495                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2496 }
2497
2498 static int
2499 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2500 {
2501         unsigned int i;
2502
2503         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2504                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2505                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2506                 struct bnxt_ring *ring = txr->tx_ring_struct;
2507                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2508
2509                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2510                         bnxt_hwrm_ring_free(bp, ring,
2511                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2512                         ring->fw_ring_id = INVALID_HW_RING_ID;
2513                         memset(txr->tx_desc_ring, 0,
2514                                         txr->tx_ring_struct->ring_size *
2515                                         sizeof(*txr->tx_desc_ring));
2516                         memset(txr->tx_buf_ring, 0,
2517                                         txr->tx_ring_struct->ring_size *
2518                                         sizeof(*txr->tx_buf_ring));
2519                         txr->tx_prod = 0;
2520                         txr->tx_cons = 0;
2521                 }
2522                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2523                         bnxt_free_cp_ring(bp, cpr);
2524                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2525                 }
2526         }
2527
2528         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2529                 bnxt_free_hwrm_rx_ring(bp, i);
2530
2531         return 0;
2532 }
2533
2534 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2535 {
2536         uint16_t i;
2537         uint32_t rc = 0;
2538
2539         if (!BNXT_HAS_RING_GRPS(bp))
2540                 return 0;
2541
2542         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2543                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2544                 if (rc)
2545                         return rc;
2546         }
2547         return rc;
2548 }
2549
2550 /*
2551  * HWRM utility functions
2552  */
2553
2554 void bnxt_free_hwrm_resources(struct bnxt *bp)
2555 {
2556         /* Release memzone */
2557         rte_free(bp->hwrm_cmd_resp_addr);
2558         rte_free(bp->hwrm_short_cmd_req_addr);
2559         bp->hwrm_cmd_resp_addr = NULL;
2560         bp->hwrm_short_cmd_req_addr = NULL;
2561         bp->hwrm_cmd_resp_dma_addr = 0;
2562         bp->hwrm_short_cmd_req_dma_addr = 0;
2563 }
2564
2565 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2566 {
2567         struct rte_pci_device *pdev = bp->pdev;
2568         char type[RTE_MEMZONE_NAMESIZE];
2569
2570         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2571                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2572         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2573         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2574         if (bp->hwrm_cmd_resp_addr == NULL)
2575                 return -ENOMEM;
2576         bp->hwrm_cmd_resp_dma_addr =
2577                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2578         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2579                 PMD_DRV_LOG(ERR,
2580                         "unable to map response address to physical memory\n");
2581                 return -ENOMEM;
2582         }
2583         rte_spinlock_init(&bp->hwrm_lock);
2584
2585         return 0;
2586 }
2587
2588 static int
2589 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2590 {
2591         struct bnxt_filter_info *filter;
2592         int rc = 0;
2593
2594         STAILQ_FOREACH(filter, &vnic->filter, next) {
2595                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2596                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2597                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2598                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2599                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2600                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2601                 bnxt_free_filter(bp, filter);
2602         }
2603         return rc;
2604 }
2605
2606 static int
2607 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2608 {
2609         struct bnxt_filter_info *filter;
2610         struct rte_flow *flow;
2611         int rc = 0;
2612
2613         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2614                 flow = STAILQ_FIRST(&vnic->flow_list);
2615                 filter = flow->filter;
2616                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2617                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2618                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2619                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2620                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2621                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2622
2623                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2624                 rte_free(flow);
2625         }
2626         return rc;
2627 }
2628
2629 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2630 {
2631         struct bnxt_filter_info *filter;
2632         int rc = 0;
2633
2634         STAILQ_FOREACH(filter, &vnic->filter, next) {
2635                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2636                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2637                                                      filter);
2638                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2639                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2640                                                          filter);
2641                 else
2642                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2643                                                      filter);
2644                 if (rc)
2645                         break;
2646         }
2647         return rc;
2648 }
2649
2650 static void
2651 bnxt_free_tunnel_ports(struct bnxt *bp)
2652 {
2653         if (bp->vxlan_port_cnt)
2654                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2655                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2656         bp->vxlan_port = 0;
2657         if (bp->geneve_port_cnt)
2658                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2659                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2660         bp->geneve_port = 0;
2661 }
2662
2663 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2664 {
2665         int i;
2666
2667         if (bp->vnic_info == NULL)
2668                 return;
2669
2670         /*
2671          * Cleanup VNICs in reverse order, to make sure the L2 filter
2672          * from vnic0 is last to be cleaned up.
2673          */
2674         for (i = bp->max_vnics - 1; i >= 0; i--) {
2675                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2676
2677                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2678                         continue;
2679
2680                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2681
2682                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2683
2684                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2685
2686                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2687
2688                 bnxt_hwrm_vnic_free(bp, vnic);
2689
2690                 rte_free(vnic->fw_grp_ids);
2691         }
2692         /* Ring resources */
2693         bnxt_free_all_hwrm_rings(bp);
2694         bnxt_free_all_hwrm_ring_grps(bp);
2695         bnxt_free_all_hwrm_stat_ctxs(bp);
2696         bnxt_free_tunnel_ports(bp);
2697 }
2698
2699 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2700 {
2701         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2702
2703         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2704                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2705
2706         switch (conf_link_speed) {
2707         case ETH_LINK_SPEED_10M_HD:
2708         case ETH_LINK_SPEED_100M_HD:
2709                 /* FALLTHROUGH */
2710                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2711         }
2712         return hw_link_duplex;
2713 }
2714
2715 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2716 {
2717         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2718 }
2719
2720 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2721 {
2722         uint16_t eth_link_speed = 0;
2723
2724         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2725                 return ETH_LINK_SPEED_AUTONEG;
2726
2727         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2728         case ETH_LINK_SPEED_100M:
2729         case ETH_LINK_SPEED_100M_HD:
2730                 /* FALLTHROUGH */
2731                 eth_link_speed =
2732                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2733                 break;
2734         case ETH_LINK_SPEED_1G:
2735                 eth_link_speed =
2736                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2737                 break;
2738         case ETH_LINK_SPEED_2_5G:
2739                 eth_link_speed =
2740                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2741                 break;
2742         case ETH_LINK_SPEED_10G:
2743                 eth_link_speed =
2744                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2745                 break;
2746         case ETH_LINK_SPEED_20G:
2747                 eth_link_speed =
2748                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2749                 break;
2750         case ETH_LINK_SPEED_25G:
2751                 eth_link_speed =
2752                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2753                 break;
2754         case ETH_LINK_SPEED_40G:
2755                 eth_link_speed =
2756                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2757                 break;
2758         case ETH_LINK_SPEED_50G:
2759                 eth_link_speed =
2760                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2761                 break;
2762         case ETH_LINK_SPEED_100G:
2763                 eth_link_speed =
2764                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2765                 break;
2766         case ETH_LINK_SPEED_200G:
2767                 eth_link_speed =
2768                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2769                 break;
2770         default:
2771                 PMD_DRV_LOG(ERR,
2772                         "Unsupported link speed %d; default to AUTO\n",
2773                         conf_link_speed);
2774                 break;
2775         }
2776         return eth_link_speed;
2777 }
2778
2779 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2780                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2781                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2782                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2783                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2784
2785 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2786 {
2787         uint32_t one_speed;
2788
2789         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2790                 return 0;
2791
2792         if (link_speed & ETH_LINK_SPEED_FIXED) {
2793                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2794
2795                 if (one_speed & (one_speed - 1)) {
2796                         PMD_DRV_LOG(ERR,
2797                                 "Invalid advertised speeds (%u) for port %u\n",
2798                                 link_speed, port_id);
2799                         return -EINVAL;
2800                 }
2801                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2802                         PMD_DRV_LOG(ERR,
2803                                 "Unsupported advertised speed (%u) for port %u\n",
2804                                 link_speed, port_id);
2805                         return -EINVAL;
2806                 }
2807         } else {
2808                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2809                         PMD_DRV_LOG(ERR,
2810                                 "Unsupported advertised speeds (%u) for port %u\n",
2811                                 link_speed, port_id);
2812                         return -EINVAL;
2813                 }
2814         }
2815         return 0;
2816 }
2817
2818 static uint16_t
2819 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2820 {
2821         uint16_t ret = 0;
2822
2823         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2824                 if (bp->link_info.support_speeds)
2825                         return bp->link_info.support_speeds;
2826                 link_speed = BNXT_SUPPORTED_SPEEDS;
2827         }
2828
2829         if (link_speed & ETH_LINK_SPEED_100M)
2830                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2831         if (link_speed & ETH_LINK_SPEED_100M_HD)
2832                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2833         if (link_speed & ETH_LINK_SPEED_1G)
2834                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2835         if (link_speed & ETH_LINK_SPEED_2_5G)
2836                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2837         if (link_speed & ETH_LINK_SPEED_10G)
2838                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2839         if (link_speed & ETH_LINK_SPEED_20G)
2840                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2841         if (link_speed & ETH_LINK_SPEED_25G)
2842                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2843         if (link_speed & ETH_LINK_SPEED_40G)
2844                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2845         if (link_speed & ETH_LINK_SPEED_50G)
2846                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2847         if (link_speed & ETH_LINK_SPEED_100G)
2848                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2849         if (link_speed & ETH_LINK_SPEED_200G)
2850                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2851         return ret;
2852 }
2853
2854 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2855 {
2856         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2857
2858         switch (hw_link_speed) {
2859         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2860                 eth_link_speed = ETH_SPEED_NUM_100M;
2861                 break;
2862         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2863                 eth_link_speed = ETH_SPEED_NUM_1G;
2864                 break;
2865         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2866                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2867                 break;
2868         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2869                 eth_link_speed = ETH_SPEED_NUM_10G;
2870                 break;
2871         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2872                 eth_link_speed = ETH_SPEED_NUM_20G;
2873                 break;
2874         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2875                 eth_link_speed = ETH_SPEED_NUM_25G;
2876                 break;
2877         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2878                 eth_link_speed = ETH_SPEED_NUM_40G;
2879                 break;
2880         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2881                 eth_link_speed = ETH_SPEED_NUM_50G;
2882                 break;
2883         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2884                 eth_link_speed = ETH_SPEED_NUM_100G;
2885                 break;
2886         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2887                 eth_link_speed = ETH_SPEED_NUM_200G;
2888                 break;
2889         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2890         default:
2891                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2892                         hw_link_speed);
2893                 break;
2894         }
2895         return eth_link_speed;
2896 }
2897
2898 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2899 {
2900         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2901
2902         switch (hw_link_duplex) {
2903         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2904         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2905                 /* FALLTHROUGH */
2906                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2907                 break;
2908         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2909                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2910                 break;
2911         default:
2912                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2913                         hw_link_duplex);
2914                 break;
2915         }
2916         return eth_link_duplex;
2917 }
2918
2919 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2920 {
2921         int rc = 0;
2922         struct bnxt_link_info *link_info = &bp->link_info;
2923
2924         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2925         if (rc) {
2926                 PMD_DRV_LOG(ERR,
2927                         "Get link config failed with rc %d\n", rc);
2928                 goto exit;
2929         }
2930         if (link_info->link_speed)
2931                 link->link_speed =
2932                         bnxt_parse_hw_link_speed(link_info->link_speed);
2933         else
2934                 link->link_speed = ETH_SPEED_NUM_NONE;
2935         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2936         link->link_status = link_info->link_up;
2937         link->link_autoneg = link_info->auto_mode ==
2938                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2939                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2940 exit:
2941         return rc;
2942 }
2943
2944 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2945 {
2946         int rc = 0;
2947         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2948         struct bnxt_link_info link_req;
2949         uint16_t speed, autoneg;
2950
2951         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2952                 return 0;
2953
2954         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2955                         bp->eth_dev->data->port_id);
2956         if (rc)
2957                 goto error;
2958
2959         memset(&link_req, 0, sizeof(link_req));
2960         link_req.link_up = link_up;
2961         if (!link_up)
2962                 goto port_phy_cfg;
2963
2964         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2965         if (BNXT_CHIP_THOR(bp) &&
2966             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2967                 /* 40G is not supported as part of media auto detect.
2968                  * The speed should be forced and autoneg disabled
2969                  * to configure 40G speed.
2970                  */
2971                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2972                 autoneg = 0;
2973         }
2974
2975         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2976         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2977         /* Autoneg can be done only when the FW allows.
2978          * When user configures fixed speed of 40G and later changes to
2979          * any other speed, auto_link_speed/force_link_speed is still set
2980          * to 40G until link comes up at new speed.
2981          */
2982         if (autoneg == 1 &&
2983             !(!BNXT_CHIP_THOR(bp) &&
2984               (bp->link_info.auto_link_speed ||
2985                bp->link_info.force_link_speed))) {
2986                 link_req.phy_flags |=
2987                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2988                 link_req.auto_link_speed_mask =
2989                         bnxt_parse_eth_link_speed_mask(bp,
2990                                                        dev_conf->link_speeds);
2991         } else {
2992                 if (bp->link_info.phy_type ==
2993                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2994                     bp->link_info.phy_type ==
2995                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2996                     bp->link_info.media_type ==
2997                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2998                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2999                         return -EINVAL;
3000                 }
3001
3002                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3003                 /* If user wants a particular speed try that first. */
3004                 if (speed)
3005                         link_req.link_speed = speed;
3006                 else if (bp->link_info.force_link_speed)
3007                         link_req.link_speed = bp->link_info.force_link_speed;
3008                 else
3009                         link_req.link_speed = bp->link_info.auto_link_speed;
3010         }
3011         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3012         link_req.auto_pause = bp->link_info.auto_pause;
3013         link_req.force_pause = bp->link_info.force_pause;
3014
3015 port_phy_cfg:
3016         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3017         if (rc) {
3018                 PMD_DRV_LOG(ERR,
3019                         "Set link config failed with rc %d\n", rc);
3020         }
3021
3022 error:
3023         return rc;
3024 }
3025
3026 /* JIRA 22088 */
3027 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3028 {
3029         struct hwrm_func_qcfg_input req = {0};
3030         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3031         uint16_t flags;
3032         int rc = 0;
3033         bp->func_svif = BNXT_SVIF_INVALID;
3034         uint16_t svif_info;
3035
3036         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3037         req.fid = rte_cpu_to_le_16(0xffff);
3038
3039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3040
3041         HWRM_CHECK_RESULT();
3042
3043         /* Hard Coded.. 0xfff VLAN ID mask */
3044         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3045
3046         svif_info = rte_le_to_cpu_16(resp->svif_info);
3047         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3048                 bp->func_svif = svif_info &
3049                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3050
3051         flags = rte_le_to_cpu_16(resp->flags);
3052         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3053                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3054
3055         if (BNXT_VF(bp) &&
3056             !BNXT_VF_IS_TRUSTED(bp) &&
3057             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3058                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3059                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3060         } else if (BNXT_VF(bp) &&
3061                    BNXT_VF_IS_TRUSTED(bp) &&
3062                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3063                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3064                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3065         }
3066
3067         if (mtu)
3068                 *mtu = rte_le_to_cpu_16(resp->mtu);
3069
3070         switch (resp->port_partition_type) {
3071         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3072         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3073         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3074                 /* FALLTHROUGH */
3075                 bp->flags |= BNXT_FLAG_NPAR_PF;
3076                 break;
3077         default:
3078                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3079                 break;
3080         }
3081
3082         HWRM_UNLOCK();
3083
3084         return rc;
3085 }
3086
3087 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3088 {
3089         struct hwrm_port_mac_qcfg_input req = {0};
3090         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3091         uint16_t port_svif_info;
3092         int rc;
3093
3094         bp->port_svif = BNXT_SVIF_INVALID;
3095
3096         if (!BNXT_PF(bp))
3097                 return 0;
3098
3099         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3100
3101         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3102
3103         HWRM_CHECK_RESULT();
3104
3105         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3106         if (port_svif_info &
3107             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3108                 bp->port_svif = port_svif_info &
3109                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3110
3111         HWRM_UNLOCK();
3112
3113         return 0;
3114 }
3115
3116 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3117                                    struct hwrm_func_qcaps_output *qcaps)
3118 {
3119         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3120         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3121                sizeof(qcaps->mac_address));
3122         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3123         qcaps->max_rx_rings = fcfg->num_rx_rings;
3124         qcaps->max_tx_rings = fcfg->num_tx_rings;
3125         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3126         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3127         qcaps->max_vfs = 0;
3128         qcaps->first_vf_id = 0;
3129         qcaps->max_vnics = fcfg->num_vnics;
3130         qcaps->max_decap_records = 0;
3131         qcaps->max_encap_records = 0;
3132         qcaps->max_tx_wm_flows = 0;
3133         qcaps->max_tx_em_flows = 0;
3134         qcaps->max_rx_wm_flows = 0;
3135         qcaps->max_rx_em_flows = 0;
3136         qcaps->max_flow_id = 0;
3137         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3138         qcaps->max_sp_tx_rings = 0;
3139         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3140 }
3141
3142 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3143 {
3144         struct hwrm_func_cfg_input req = {0};
3145         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3146         uint32_t enables;
3147         int rc;
3148
3149         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3150                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3151                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3152                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3153                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3154                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3155                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3156                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3157                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3158
3159         if (BNXT_HAS_RING_GRPS(bp)) {
3160                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3161                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3162         } else if (BNXT_HAS_NQ(bp)) {
3163                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3164                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3165         }
3166
3167         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3168         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3169         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3170         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3171         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3172         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3173         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3174         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3175         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3176         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3177         req.fid = rte_cpu_to_le_16(0xffff);
3178         req.enables = rte_cpu_to_le_32(enables);
3179
3180         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3181
3182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3183
3184         HWRM_CHECK_RESULT();
3185         HWRM_UNLOCK();
3186
3187         return rc;
3188 }
3189
3190 static void populate_vf_func_cfg_req(struct bnxt *bp,
3191                                      struct hwrm_func_cfg_input *req,
3192                                      int num_vfs)
3193 {
3194         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3195                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3196                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3197                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3198                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3199                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3200                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3201                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3202                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3203                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3204
3205         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3206                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3207                                     BNXT_NUM_VLANS);
3208         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3209         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3210                                                 (num_vfs + 1));
3211         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3212         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3213                                                (num_vfs + 1));
3214         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3215         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3216         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3217         /* TODO: For now, do not support VMDq/RFS on VFs. */
3218         req->num_vnics = rte_cpu_to_le_16(1);
3219         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3220                                                  (num_vfs + 1));
3221 }
3222
3223 static void add_random_mac_if_needed(struct bnxt *bp,
3224                                      struct hwrm_func_cfg_input *cfg_req,
3225                                      int vf)
3226 {
3227         struct rte_ether_addr mac;
3228
3229         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3230                 return;
3231
3232         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3233                 cfg_req->enables |=
3234                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3235                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3236                 bp->pf.vf_info[vf].random_mac = true;
3237         } else {
3238                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3239                         RTE_ETHER_ADDR_LEN);
3240         }
3241 }
3242
3243 static int reserve_resources_from_vf(struct bnxt *bp,
3244                                      struct hwrm_func_cfg_input *cfg_req,
3245                                      int vf)
3246 {
3247         struct hwrm_func_qcaps_input req = {0};
3248         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3249         int rc;
3250
3251         /* Get the actual allocated values now */
3252         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3253         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3254         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3255
3256         if (rc) {
3257                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3258                 copy_func_cfg_to_qcaps(cfg_req, resp);
3259         } else if (resp->error_code) {
3260                 rc = rte_le_to_cpu_16(resp->error_code);
3261                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3262                 copy_func_cfg_to_qcaps(cfg_req, resp);
3263         }
3264
3265         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3266         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3267         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3268         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3269         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3270         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3271         /*
3272          * TODO: While not supporting VMDq with VFs, max_vnics is always
3273          * forced to 1 in this case
3274          */
3275         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3276         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3277
3278         HWRM_UNLOCK();
3279
3280         return 0;
3281 }
3282
3283 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3284 {
3285         struct hwrm_func_qcfg_input req = {0};
3286         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3287         int rc;
3288
3289         /* Check for zero MAC address */
3290         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3291         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3292         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3293         HWRM_CHECK_RESULT();
3294         rc = rte_le_to_cpu_16(resp->vlan);
3295
3296         HWRM_UNLOCK();
3297
3298         return rc;
3299 }
3300
3301 static int update_pf_resource_max(struct bnxt *bp)
3302 {
3303         struct hwrm_func_qcfg_input req = {0};
3304         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3305         int rc;
3306
3307         /* And copy the allocated numbers into the pf struct */
3308         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3309         req.fid = rte_cpu_to_le_16(0xffff);
3310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3311         HWRM_CHECK_RESULT();
3312
3313         /* Only TX ring value reflects actual allocation? TODO */
3314         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3315         bp->pf.evb_mode = resp->evb_mode;
3316
3317         HWRM_UNLOCK();
3318
3319         return rc;
3320 }
3321
3322 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3323 {
3324         int rc;
3325
3326         if (!BNXT_PF(bp)) {
3327                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3328                 return -EINVAL;
3329         }
3330
3331         rc = bnxt_hwrm_func_qcaps(bp);
3332         if (rc)
3333                 return rc;
3334
3335         bp->pf.func_cfg_flags &=
3336                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3337                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3338         bp->pf.func_cfg_flags |=
3339                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3340         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3341         rc = __bnxt_hwrm_func_qcaps(bp);
3342         return rc;
3343 }
3344
3345 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3346 {
3347         struct hwrm_func_cfg_input req = {0};
3348         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3349         int i;
3350         size_t sz;
3351         int rc = 0;
3352         size_t req_buf_sz;
3353
3354         if (!BNXT_PF(bp)) {
3355                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3356                 return -EINVAL;
3357         }
3358
3359         rc = bnxt_hwrm_func_qcaps(bp);
3360
3361         if (rc)
3362                 return rc;
3363
3364         bp->pf.active_vfs = num_vfs;
3365
3366         /*
3367          * First, configure the PF to only use one TX ring.  This ensures that
3368          * there are enough rings for all VFs.
3369          *
3370          * If we don't do this, when we call func_alloc() later, we will lock
3371          * extra rings to the PF that won't be available during func_cfg() of
3372          * the VFs.
3373          *
3374          * This has been fixed with firmware versions above 20.6.54
3375          */
3376         bp->pf.func_cfg_flags &=
3377                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3378                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3379         bp->pf.func_cfg_flags |=
3380                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3381         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3382         if (rc)
3383                 return rc;
3384
3385         /*
3386          * Now, create and register a buffer to hold forwarded VF requests
3387          */
3388         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3389         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3390                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3391         if (bp->pf.vf_req_buf == NULL) {
3392                 rc = -ENOMEM;
3393                 goto error_free;
3394         }
3395         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3396                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3397         for (i = 0; i < num_vfs; i++)
3398                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3399                                         (i * HWRM_MAX_REQ_LEN);
3400
3401         rc = bnxt_hwrm_func_buf_rgtr(bp);
3402         if (rc)
3403                 goto error_free;
3404
3405         populate_vf_func_cfg_req(bp, &req, num_vfs);
3406
3407         bp->pf.active_vfs = 0;
3408         for (i = 0; i < num_vfs; i++) {
3409                 add_random_mac_if_needed(bp, &req, i);
3410
3411                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3412                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3413                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3414                 rc = bnxt_hwrm_send_message(bp,
3415                                             &req,
3416                                             sizeof(req),
3417                                             BNXT_USE_CHIMP_MB);
3418
3419                 /* Clear enable flag for next pass */
3420                 req.enables &= ~rte_cpu_to_le_32(
3421                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3422
3423                 if (rc || resp->error_code) {
3424                         PMD_DRV_LOG(ERR,
3425                                 "Failed to initizlie VF %d\n", i);
3426                         PMD_DRV_LOG(ERR,
3427                                 "Not all VFs available. (%d, %d)\n",
3428                                 rc, resp->error_code);
3429                         HWRM_UNLOCK();
3430                         break;
3431                 }
3432
3433                 HWRM_UNLOCK();
3434
3435                 reserve_resources_from_vf(bp, &req, i);
3436                 bp->pf.active_vfs++;
3437                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3438         }
3439
3440         /*
3441          * Now configure the PF to use "the rest" of the resources
3442          * We're using STD_TX_RING_MODE here though which will limit the TX
3443          * rings.  This will allow QoS to function properly.  Not setting this
3444          * will cause PF rings to break bandwidth settings.
3445          */
3446         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3447         if (rc)
3448                 goto error_free;
3449
3450         rc = update_pf_resource_max(bp);
3451         if (rc)
3452                 goto error_free;
3453
3454         return rc;
3455
3456 error_free:
3457         bnxt_hwrm_func_buf_unrgtr(bp);
3458         return rc;
3459 }
3460
3461 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3462 {
3463         struct hwrm_func_cfg_input req = {0};
3464         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3465         int rc;
3466
3467         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3468
3469         req.fid = rte_cpu_to_le_16(0xffff);
3470         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3471         req.evb_mode = bp->pf.evb_mode;
3472
3473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3474         HWRM_CHECK_RESULT();
3475         HWRM_UNLOCK();
3476
3477         return rc;
3478 }
3479
3480 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3481                                 uint8_t tunnel_type)
3482 {
3483         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3484         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3485         int rc = 0;
3486
3487         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3488         req.tunnel_type = tunnel_type;
3489         req.tunnel_dst_port_val = port;
3490         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3491         HWRM_CHECK_RESULT();
3492
3493         switch (tunnel_type) {
3494         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3495                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3496                 bp->vxlan_port = port;
3497                 break;
3498         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3499                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3500                 bp->geneve_port = port;
3501                 break;
3502         default:
3503                 break;
3504         }
3505
3506         HWRM_UNLOCK();
3507
3508         return rc;
3509 }
3510
3511 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3512                                 uint8_t tunnel_type)
3513 {
3514         struct hwrm_tunnel_dst_port_free_input req = {0};
3515         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3516         int rc = 0;
3517
3518         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3519
3520         req.tunnel_type = tunnel_type;
3521         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3522         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3523
3524         HWRM_CHECK_RESULT();
3525         HWRM_UNLOCK();
3526
3527         return rc;
3528 }
3529
3530 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3531                                         uint32_t flags)
3532 {
3533         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3534         struct hwrm_func_cfg_input req = {0};
3535         int rc;
3536
3537         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3538
3539         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3540         req.flags = rte_cpu_to_le_32(flags);
3541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3542
3543         HWRM_CHECK_RESULT();
3544         HWRM_UNLOCK();
3545
3546         return rc;
3547 }
3548
3549 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3550 {
3551         uint32_t *flag = flagp;
3552
3553         vnic->flags = *flag;
3554 }
3555
3556 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3557 {
3558         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3559 }
3560
3561 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3562 {
3563         int rc = 0;
3564         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3565         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3566
3567         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3568
3569         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3570         req.req_buf_page_size = rte_cpu_to_le_16(
3571                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3572         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3573         req.req_buf_page_addr0 =
3574                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3575         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3576                 PMD_DRV_LOG(ERR,
3577                         "unable to map buffer address to physical memory\n");
3578                 return -ENOMEM;
3579         }
3580
3581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3582
3583         HWRM_CHECK_RESULT();
3584         HWRM_UNLOCK();
3585
3586         return rc;
3587 }
3588
3589 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3590 {
3591         int rc = 0;
3592         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3593         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3594
3595         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3596                 return 0;
3597
3598         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3599
3600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3601
3602         HWRM_CHECK_RESULT();
3603         HWRM_UNLOCK();
3604
3605         return rc;
3606 }
3607
3608 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3609 {
3610         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3611         struct hwrm_func_cfg_input req = {0};
3612         int rc;
3613
3614         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3615
3616         req.fid = rte_cpu_to_le_16(0xffff);
3617         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3618         req.enables = rte_cpu_to_le_32(
3619                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3620         req.async_event_cr = rte_cpu_to_le_16(
3621                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3623
3624         HWRM_CHECK_RESULT();
3625         HWRM_UNLOCK();
3626
3627         return rc;
3628 }
3629
3630 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3631 {
3632         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3633         struct hwrm_func_vf_cfg_input req = {0};
3634         int rc;
3635
3636         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3637
3638         req.enables = rte_cpu_to_le_32(
3639                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3640         req.async_event_cr = rte_cpu_to_le_16(
3641                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3643
3644         HWRM_CHECK_RESULT();
3645         HWRM_UNLOCK();
3646
3647         return rc;
3648 }
3649
3650 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3651 {
3652         struct hwrm_func_cfg_input req = {0};
3653         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3654         uint16_t dflt_vlan, fid;
3655         uint32_t func_cfg_flags;
3656         int rc = 0;
3657
3658         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3659
3660         if (is_vf) {
3661                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3662                 fid = bp->pf.vf_info[vf].fid;
3663                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3664         } else {
3665                 fid = rte_cpu_to_le_16(0xffff);
3666                 func_cfg_flags = bp->pf.func_cfg_flags;
3667                 dflt_vlan = bp->vlan;
3668         }
3669
3670         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3671         req.fid = rte_cpu_to_le_16(fid);
3672         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3673         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3674
3675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3676
3677         HWRM_CHECK_RESULT();
3678         HWRM_UNLOCK();
3679
3680         return rc;
3681 }
3682
3683 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3684                         uint16_t max_bw, uint16_t enables)
3685 {
3686         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3687         struct hwrm_func_cfg_input req = {0};
3688         int rc;
3689
3690         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3691
3692         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3693         req.enables |= rte_cpu_to_le_32(enables);
3694         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3695         req.max_bw = rte_cpu_to_le_32(max_bw);
3696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3697
3698         HWRM_CHECK_RESULT();
3699         HWRM_UNLOCK();
3700
3701         return rc;
3702 }
3703
3704 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3705 {
3706         struct hwrm_func_cfg_input req = {0};
3707         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3708         int rc = 0;
3709
3710         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3711
3712         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3713         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3714         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3715         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3716
3717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3718
3719         HWRM_CHECK_RESULT();
3720         HWRM_UNLOCK();
3721
3722         return rc;
3723 }
3724
3725 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3726 {
3727         int rc;
3728
3729         if (BNXT_PF(bp))
3730                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3731         else
3732                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3733
3734         return rc;
3735 }
3736
3737 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3738                               void *encaped, size_t ec_size)
3739 {
3740         int rc = 0;
3741         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3742         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3743
3744         if (ec_size > sizeof(req.encap_request))
3745                 return -1;
3746
3747         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3748
3749         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3750         memcpy(req.encap_request, encaped, ec_size);
3751
3752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3753
3754         HWRM_CHECK_RESULT();
3755         HWRM_UNLOCK();
3756
3757         return rc;
3758 }
3759
3760 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3761                                        struct rte_ether_addr *mac)
3762 {
3763         struct hwrm_func_qcfg_input req = {0};
3764         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3765         int rc;
3766
3767         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3768
3769         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3770         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3771
3772         HWRM_CHECK_RESULT();
3773
3774         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3775
3776         HWRM_UNLOCK();
3777
3778         return rc;
3779 }
3780
3781 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3782                             void *encaped, size_t ec_size)
3783 {
3784         int rc = 0;
3785         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3786         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3787
3788         if (ec_size > sizeof(req.encap_request))
3789                 return -1;
3790
3791         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3792
3793         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3794         memcpy(req.encap_request, encaped, ec_size);
3795
3796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3797
3798         HWRM_CHECK_RESULT();
3799         HWRM_UNLOCK();
3800
3801         return rc;
3802 }
3803
3804 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3805                          struct rte_eth_stats *stats, uint8_t rx)
3806 {
3807         int rc = 0;
3808         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3809         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3810
3811         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3812
3813         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3814
3815         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3816
3817         HWRM_CHECK_RESULT();
3818
3819         if (rx) {
3820                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3821                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3822                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3823                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3824                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3825                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3826                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3827                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3828         } else {
3829                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3830                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3831                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3832                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3833                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3834                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3835         }
3836
3837         HWRM_UNLOCK();
3838
3839         return rc;
3840 }
3841
3842 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3843 {
3844         struct hwrm_port_qstats_input req = {0};
3845         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3846         struct bnxt_pf_info *pf = &bp->pf;
3847         int rc;
3848
3849         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3850
3851         req.port_id = rte_cpu_to_le_16(pf->port_id);
3852         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3853         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3855
3856         HWRM_CHECK_RESULT();
3857         HWRM_UNLOCK();
3858
3859         return rc;
3860 }
3861
3862 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3863 {
3864         struct hwrm_port_clr_stats_input req = {0};
3865         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3866         struct bnxt_pf_info *pf = &bp->pf;
3867         int rc;
3868
3869         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3870         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3871             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3872                 return 0;
3873
3874         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3875
3876         req.port_id = rte_cpu_to_le_16(pf->port_id);
3877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3878
3879         HWRM_CHECK_RESULT();
3880         HWRM_UNLOCK();
3881
3882         return rc;
3883 }
3884
3885 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3886 {
3887         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3888         struct hwrm_port_led_qcaps_input req = {0};
3889         int rc;
3890
3891         if (BNXT_VF(bp))
3892                 return 0;
3893
3894         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3895         req.port_id = bp->pf.port_id;
3896         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3897
3898         HWRM_CHECK_RESULT();
3899
3900         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3901                 unsigned int i;
3902
3903                 bp->leds->num_leds = resp->num_leds;
3904                 memcpy(bp->leds, &resp->led0_id,
3905                         sizeof(bp->leds[0]) * bp->leds->num_leds);
3906                 for (i = 0; i < bp->leds->num_leds; i++) {
3907                         struct bnxt_led_info *led = &bp->leds[i];
3908
3909                         uint16_t caps = led->led_state_caps;
3910
3911                         if (!led->led_group_id ||
3912                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3913                                 bp->leds->num_leds = 0;
3914                                 break;
3915                         }
3916                 }
3917         }
3918
3919         HWRM_UNLOCK();
3920
3921         return rc;
3922 }
3923
3924 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3925 {
3926         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3927         struct hwrm_port_led_cfg_input req = {0};
3928         struct bnxt_led_cfg *led_cfg;
3929         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3930         uint16_t duration = 0;
3931         int rc, i;
3932
3933         if (!bp->leds->num_leds || BNXT_VF(bp))
3934                 return -EOPNOTSUPP;
3935
3936         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3937
3938         if (led_on) {
3939                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3940                 duration = rte_cpu_to_le_16(500);
3941         }
3942         req.port_id = bp->pf.port_id;
3943         req.num_leds = bp->leds->num_leds;
3944         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3945         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
3946                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3947                 led_cfg->led_id = bp->leds[i].led_id;
3948                 led_cfg->led_state = led_state;
3949                 led_cfg->led_blink_on = duration;
3950                 led_cfg->led_blink_off = duration;
3951                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3952         }
3953
3954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3955
3956         HWRM_CHECK_RESULT();
3957         HWRM_UNLOCK();
3958
3959         return rc;
3960 }
3961
3962 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3963                                uint32_t *length)
3964 {
3965         int rc;
3966         struct hwrm_nvm_get_dir_info_input req = {0};
3967         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3968
3969         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3970
3971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3972
3973         HWRM_CHECK_RESULT();
3974
3975         *entries = rte_le_to_cpu_32(resp->entries);
3976         *length = rte_le_to_cpu_32(resp->entry_length);
3977
3978         HWRM_UNLOCK();
3979         return rc;
3980 }
3981
3982 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3983 {
3984         int rc;
3985         uint32_t dir_entries;
3986         uint32_t entry_length;
3987         uint8_t *buf;
3988         size_t buflen;
3989         rte_iova_t dma_handle;
3990         struct hwrm_nvm_get_dir_entries_input req = {0};
3991         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3992
3993         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3994         if (rc != 0)
3995                 return rc;
3996
3997         *data++ = dir_entries;
3998         *data++ = entry_length;
3999         len -= 2;
4000         memset(data, 0xff, len);
4001
4002         buflen = dir_entries * entry_length;
4003         buf = rte_malloc("nvm_dir", buflen, 0);
4004         if (buf == NULL)
4005                 return -ENOMEM;
4006         dma_handle = rte_malloc_virt2iova(buf);
4007         if (dma_handle == RTE_BAD_IOVA) {
4008                 PMD_DRV_LOG(ERR,
4009                         "unable to map response address to physical memory\n");
4010                 return -ENOMEM;
4011         }
4012         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4013         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4015
4016         if (rc == 0)
4017                 memcpy(data, buf, len > buflen ? buflen : len);
4018
4019         rte_free(buf);
4020         HWRM_CHECK_RESULT();
4021         HWRM_UNLOCK();
4022
4023         return rc;
4024 }
4025
4026 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4027                              uint32_t offset, uint32_t length,
4028                              uint8_t *data)
4029 {
4030         int rc;
4031         uint8_t *buf;
4032         rte_iova_t dma_handle;
4033         struct hwrm_nvm_read_input req = {0};
4034         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4035
4036         buf = rte_malloc("nvm_item", length, 0);
4037         if (!buf)
4038                 return -ENOMEM;
4039
4040         dma_handle = rte_malloc_virt2iova(buf);
4041         if (dma_handle == RTE_BAD_IOVA) {
4042                 PMD_DRV_LOG(ERR,
4043                         "unable to map response address to physical memory\n");
4044                 return -ENOMEM;
4045         }
4046         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4047         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4048         req.dir_idx = rte_cpu_to_le_16(index);
4049         req.offset = rte_cpu_to_le_32(offset);
4050         req.len = rte_cpu_to_le_32(length);
4051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4052         if (rc == 0)
4053                 memcpy(data, buf, length);
4054
4055         rte_free(buf);
4056         HWRM_CHECK_RESULT();
4057         HWRM_UNLOCK();
4058
4059         return rc;
4060 }
4061
4062 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4063 {
4064         int rc;
4065         struct hwrm_nvm_erase_dir_entry_input req = {0};
4066         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4067
4068         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4069         req.dir_idx = rte_cpu_to_le_16(index);
4070         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4071         HWRM_CHECK_RESULT();
4072         HWRM_UNLOCK();
4073
4074         return rc;
4075 }
4076
4077
4078 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4079                           uint16_t dir_ordinal, uint16_t dir_ext,
4080                           uint16_t dir_attr, const uint8_t *data,
4081                           size_t data_len)
4082 {
4083         int rc;
4084         struct hwrm_nvm_write_input req = {0};
4085         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4086         rte_iova_t dma_handle;
4087         uint8_t *buf;
4088
4089         buf = rte_malloc("nvm_write", data_len, 0);
4090         if (!buf)
4091                 return -ENOMEM;
4092
4093         dma_handle = rte_malloc_virt2iova(buf);
4094         if (dma_handle == RTE_BAD_IOVA) {
4095                 PMD_DRV_LOG(ERR,
4096                         "unable to map response address to physical memory\n");
4097                 return -ENOMEM;
4098         }
4099         memcpy(buf, data, data_len);
4100
4101         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4102
4103         req.dir_type = rte_cpu_to_le_16(dir_type);
4104         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4105         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4106         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4107         req.dir_data_length = rte_cpu_to_le_32(data_len);
4108         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4109
4110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4111
4112         rte_free(buf);
4113         HWRM_CHECK_RESULT();
4114         HWRM_UNLOCK();
4115
4116         return rc;
4117 }
4118
4119 static void
4120 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4121 {
4122         uint32_t *count = cbdata;
4123
4124         *count = *count + 1;
4125 }
4126
4127 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4128                                      struct bnxt_vnic_info *vnic __rte_unused)
4129 {
4130         return 0;
4131 }
4132
4133 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4134 {
4135         uint32_t count = 0;
4136
4137         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4138             &count, bnxt_vnic_count_hwrm_stub);
4139
4140         return count;
4141 }
4142
4143 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4144                                         uint16_t *vnic_ids)
4145 {
4146         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4147         struct hwrm_func_vf_vnic_ids_query_output *resp =
4148                                                 bp->hwrm_cmd_resp_addr;
4149         int rc;
4150
4151         /* First query all VNIC ids */
4152         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4153
4154         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4155         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4156         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4157
4158         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4159                 HWRM_UNLOCK();
4160                 PMD_DRV_LOG(ERR,
4161                 "unable to map VNIC ID table address to physical memory\n");
4162                 return -ENOMEM;
4163         }
4164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4165         HWRM_CHECK_RESULT();
4166         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4167
4168         HWRM_UNLOCK();
4169
4170         return rc;
4171 }
4172
4173 /*
4174  * This function queries the VNIC IDs  for a specified VF. It then calls
4175  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4176  * Then it calls the hwrm_cb function to program this new vnic configuration.
4177  */
4178 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4179         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4180         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4181 {
4182         struct bnxt_vnic_info vnic;
4183         int rc = 0;
4184         int i, num_vnic_ids;
4185         uint16_t *vnic_ids;
4186         size_t vnic_id_sz;
4187         size_t sz;
4188
4189         /* First query all VNIC ids */
4190         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4191         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4192                         RTE_CACHE_LINE_SIZE);
4193         if (vnic_ids == NULL)
4194                 return -ENOMEM;
4195
4196         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4197                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4198
4199         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4200
4201         if (num_vnic_ids < 0)
4202                 return num_vnic_ids;
4203
4204         /* Retrieve VNIC, update bd_stall then update */
4205
4206         for (i = 0; i < num_vnic_ids; i++) {
4207                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4208                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4209                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4210                 if (rc)
4211                         break;
4212                 if (vnic.mru <= 4)      /* Indicates unallocated */
4213                         continue;
4214
4215                 vnic_cb(&vnic, cbdata);
4216
4217                 rc = hwrm_cb(bp, &vnic);
4218                 if (rc)
4219                         break;
4220         }
4221
4222         rte_free(vnic_ids);
4223
4224         return rc;
4225 }
4226
4227 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4228                                               bool on)
4229 {
4230         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4231         struct hwrm_func_cfg_input req = {0};
4232         int rc;
4233
4234         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4235
4236         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4237         req.enables |= rte_cpu_to_le_32(
4238                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4239         req.vlan_antispoof_mode = on ?
4240                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4241                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4243
4244         HWRM_CHECK_RESULT();
4245         HWRM_UNLOCK();
4246
4247         return rc;
4248 }
4249
4250 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4251 {
4252         struct bnxt_vnic_info vnic;
4253         uint16_t *vnic_ids;
4254         size_t vnic_id_sz;
4255         int num_vnic_ids, i;
4256         size_t sz;
4257         int rc;
4258
4259         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4260         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4261                         RTE_CACHE_LINE_SIZE);
4262         if (vnic_ids == NULL)
4263                 return -ENOMEM;
4264
4265         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4266                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4267
4268         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4269         if (rc <= 0)
4270                 goto exit;
4271         num_vnic_ids = rc;
4272
4273         /*
4274          * Loop through to find the default VNIC ID.
4275          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4276          * by sending the hwrm_func_qcfg command to the firmware.
4277          */
4278         for (i = 0; i < num_vnic_ids; i++) {
4279                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4280                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4281                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4282                                         bp->pf.first_vf_id + vf);
4283                 if (rc)
4284                         goto exit;
4285                 if (vnic.func_default) {
4286                         rte_free(vnic_ids);
4287                         return vnic.fw_vnic_id;
4288                 }
4289         }
4290         /* Could not find a default VNIC. */
4291         PMD_DRV_LOG(ERR, "No default VNIC\n");
4292 exit:
4293         rte_free(vnic_ids);
4294         return rc;
4295 }
4296
4297 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4298                          uint16_t dst_id,
4299                          struct bnxt_filter_info *filter)
4300 {
4301         int rc = 0;
4302         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4303         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4304         uint32_t enables = 0;
4305
4306         if (filter->fw_em_filter_id != UINT64_MAX)
4307                 bnxt_hwrm_clear_em_filter(bp, filter);
4308
4309         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4310
4311         req.flags = rte_cpu_to_le_32(filter->flags);
4312
4313         enables = filter->enables |
4314               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4315         req.dst_id = rte_cpu_to_le_16(dst_id);
4316
4317         if (filter->ip_addr_type) {
4318                 req.ip_addr_type = filter->ip_addr_type;
4319                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4320         }
4321         if (enables &
4322             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4323                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4324         if (enables &
4325             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4326                 memcpy(req.src_macaddr, filter->src_macaddr,
4327                        RTE_ETHER_ADDR_LEN);
4328         if (enables &
4329             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4330                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4331                        RTE_ETHER_ADDR_LEN);
4332         if (enables &
4333             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4334                 req.ovlan_vid = filter->l2_ovlan;
4335         if (enables &
4336             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4337                 req.ivlan_vid = filter->l2_ivlan;
4338         if (enables &
4339             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4340                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4341         if (enables &
4342             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4343                 req.ip_protocol = filter->ip_protocol;
4344         if (enables &
4345             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4346                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4347         if (enables &
4348             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4349                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4350         if (enables &
4351             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4352                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4353         if (enables &
4354             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4355                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4356         if (enables &
4357             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4358                 req.mirror_vnic_id = filter->mirror_vnic_id;
4359
4360         req.enables = rte_cpu_to_le_32(enables);
4361
4362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4363
4364         HWRM_CHECK_RESULT();
4365
4366         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4367         HWRM_UNLOCK();
4368
4369         return rc;
4370 }
4371
4372 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4373 {
4374         int rc = 0;
4375         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4376         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4377
4378         if (filter->fw_em_filter_id == UINT64_MAX)
4379                 return 0;
4380
4381         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4382
4383         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4384
4385         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4386
4387         HWRM_CHECK_RESULT();
4388         HWRM_UNLOCK();
4389
4390         filter->fw_em_filter_id = UINT64_MAX;
4391         filter->fw_l2_filter_id = UINT64_MAX;
4392
4393         return 0;
4394 }
4395
4396 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4397                          uint16_t dst_id,
4398                          struct bnxt_filter_info *filter)
4399 {
4400         int rc = 0;
4401         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4402         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4403                                                 bp->hwrm_cmd_resp_addr;
4404         uint32_t enables = 0;
4405
4406         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4407                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4408
4409         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4410
4411         req.flags = rte_cpu_to_le_32(filter->flags);
4412
4413         enables = filter->enables |
4414               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4415         req.dst_id = rte_cpu_to_le_16(dst_id);
4416
4417         if (filter->ip_addr_type) {
4418                 req.ip_addr_type = filter->ip_addr_type;
4419                 enables |=
4420                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4421         }
4422         if (enables &
4423             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4424                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4425         if (enables &
4426             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4427                 memcpy(req.src_macaddr, filter->src_macaddr,
4428                        RTE_ETHER_ADDR_LEN);
4429         if (enables &
4430             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4431                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4432         if (enables &
4433             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4434                 req.ip_protocol = filter->ip_protocol;
4435         if (enables &
4436             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4437                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4438         if (enables &
4439             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4440                 req.src_ipaddr_mask[0] =
4441                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4442         if (enables &
4443             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4444                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4445         if (enables &
4446             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4447                 req.dst_ipaddr_mask[0] =
4448                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4449         if (enables &
4450             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4451                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4452         if (enables &
4453             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4454                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4455         if (enables &
4456             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4457                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4458         if (enables &
4459             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4460                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4461         if (enables &
4462             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4463                 req.mirror_vnic_id = filter->mirror_vnic_id;
4464
4465         req.enables = rte_cpu_to_le_32(enables);
4466
4467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4468
4469         HWRM_CHECK_RESULT();
4470
4471         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4472         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4473         HWRM_UNLOCK();
4474
4475         return rc;
4476 }
4477
4478 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4479                                 struct bnxt_filter_info *filter)
4480 {
4481         int rc = 0;
4482         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4483         struct hwrm_cfa_ntuple_filter_free_output *resp =
4484                                                 bp->hwrm_cmd_resp_addr;
4485
4486         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4487                 return 0;
4488
4489         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4490
4491         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4492
4493         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4494
4495         HWRM_CHECK_RESULT();
4496         HWRM_UNLOCK();
4497
4498         filter->fw_ntuple_filter_id = UINT64_MAX;
4499
4500         return 0;
4501 }
4502
4503 static int
4504 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4505 {
4506         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4507         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4508         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4509         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4510         uint16_t *ring_tbl = vnic->rss_table;
4511         int nr_ctxs = vnic->num_lb_ctxts;
4512         int max_rings = bp->rx_nr_rings;
4513         int i, j, k, cnt;
4514         int rc = 0;
4515
4516         for (i = 0, k = 0; i < nr_ctxs; i++) {
4517                 struct bnxt_rx_ring_info *rxr;
4518                 struct bnxt_cp_ring_info *cpr;
4519
4520                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4521
4522                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4523                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4524                 req.hash_mode_flags = vnic->hash_mode;
4525
4526                 req.ring_grp_tbl_addr =
4527                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4528                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4529                                      2 * sizeof(*ring_tbl));
4530                 req.hash_key_tbl_addr =
4531                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4532
4533                 req.ring_table_pair_index = i;
4534                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4535
4536                 for (j = 0; j < 64; j++) {
4537                         uint16_t ring_id;
4538
4539                         /* Find next active ring. */
4540                         for (cnt = 0; cnt < max_rings; cnt++) {
4541                                 if (rx_queue_state[k] !=
4542                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4543                                         break;
4544                                 if (++k == max_rings)
4545                                         k = 0;
4546                         }
4547
4548                         /* Return if no rings are active. */
4549                         if (cnt == max_rings) {
4550                                 HWRM_UNLOCK();
4551                                 return 0;
4552                         }
4553
4554                         /* Add rx/cp ring pair to RSS table. */
4555                         rxr = rxqs[k]->rx_ring;
4556                         cpr = rxqs[k]->cp_ring;
4557
4558                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4559                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4560                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4561                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4562
4563                         if (++k == max_rings)
4564                                 k = 0;
4565                 }
4566                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4567                                             BNXT_USE_CHIMP_MB);
4568
4569                 HWRM_CHECK_RESULT();
4570                 HWRM_UNLOCK();
4571         }
4572
4573         return rc;
4574 }
4575
4576 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4577 {
4578         unsigned int rss_idx, fw_idx, i;
4579
4580         if (!(vnic->rss_table && vnic->hash_type))
4581                 return 0;
4582
4583         if (BNXT_CHIP_THOR(bp))
4584                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4585
4586         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4587                 return 0;
4588
4589         if (vnic->rss_table && vnic->hash_type) {
4590                 /*
4591                  * Fill the RSS hash & redirection table with
4592                  * ring group ids for all VNICs
4593                  */
4594                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4595                         rss_idx++, fw_idx++) {
4596                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4597                                 fw_idx %= bp->rx_cp_nr_rings;
4598                                 if (vnic->fw_grp_ids[fw_idx] !=
4599                                     INVALID_HW_RING_ID)
4600                                         break;
4601                                 fw_idx++;
4602                         }
4603                         if (i == bp->rx_cp_nr_rings)
4604                                 return 0;
4605                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4606                 }
4607                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4608         }
4609
4610         return 0;
4611 }
4612
4613 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4614         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4615 {
4616         uint16_t flags;
4617
4618         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4619
4620         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4621         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4622
4623         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4624         req->num_cmpl_dma_aggr_during_int =
4625                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4626
4627         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4628
4629         /* min timer set to 1/2 of interrupt timer */
4630         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4631
4632         /* buf timer set to 1/4 of interrupt timer */
4633         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4634
4635         req->cmpl_aggr_dma_tmr_during_int =
4636                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4637
4638         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4639                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4640         req->flags = rte_cpu_to_le_16(flags);
4641 }
4642
4643 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4644                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4645 {
4646         struct hwrm_ring_aggint_qcaps_input req = {0};
4647         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4648         uint32_t enables;
4649         uint16_t flags;
4650         int rc;
4651
4652         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4654         HWRM_CHECK_RESULT();
4655
4656         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4657         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4658
4659         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4660                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4661         agg_req->flags = rte_cpu_to_le_16(flags);
4662         enables =
4663          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4664          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4665         agg_req->enables = rte_cpu_to_le_32(enables);
4666
4667         HWRM_UNLOCK();
4668         return rc;
4669 }
4670
4671 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4672                         struct bnxt_coal *coal, uint16_t ring_id)
4673 {
4674         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4675         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4676                                                 bp->hwrm_cmd_resp_addr;
4677         int rc;
4678
4679         /* Set ring coalesce parameters only for 100G NICs */
4680         if (BNXT_CHIP_THOR(bp)) {
4681                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4682                         return -1;
4683         } else if (bnxt_stratus_device(bp)) {
4684                 bnxt_hwrm_set_coal_params(coal, &req);
4685         } else {
4686                 return 0;
4687         }
4688
4689         HWRM_PREP(&req,
4690                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4691                   BNXT_USE_CHIMP_MB);
4692         req.ring_id = rte_cpu_to_le_16(ring_id);
4693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4694         HWRM_CHECK_RESULT();
4695         HWRM_UNLOCK();
4696         return 0;
4697 }
4698
4699 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4700 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4701 {
4702         struct hwrm_func_backing_store_qcaps_input req = {0};
4703         struct hwrm_func_backing_store_qcaps_output *resp =
4704                 bp->hwrm_cmd_resp_addr;
4705         struct bnxt_ctx_pg_info *ctx_pg;
4706         struct bnxt_ctx_mem_info *ctx;
4707         int total_alloc_len;
4708         int rc, i, tqm_rings;
4709
4710         if (!BNXT_CHIP_THOR(bp) ||
4711             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4712             BNXT_VF(bp) ||
4713             bp->ctx)
4714                 return 0;
4715
4716         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4718         HWRM_CHECK_RESULT_SILENT();
4719
4720         total_alloc_len = sizeof(*ctx);
4721         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4722                           RTE_CACHE_LINE_SIZE);
4723         if (!ctx) {
4724                 rc = -ENOMEM;
4725                 goto ctx_err;
4726         }
4727
4728         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4729         ctx->qp_min_qp1_entries =
4730                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4731         ctx->qp_max_l2_entries =
4732                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4733         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4734         ctx->srq_max_l2_entries =
4735                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4736         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4737         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4738         ctx->cq_max_l2_entries =
4739                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4740         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4741         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4742         ctx->vnic_max_vnic_entries =
4743                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4744         ctx->vnic_max_ring_table_entries =
4745                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4746         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4747         ctx->stat_max_entries =
4748                 rte_le_to_cpu_32(resp->stat_max_entries);
4749         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4750         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4751         ctx->tqm_min_entries_per_ring =
4752                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4753         ctx->tqm_max_entries_per_ring =
4754                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4755         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4756         if (!ctx->tqm_entries_multiple)
4757                 ctx->tqm_entries_multiple = 1;
4758         ctx->mrav_max_entries =
4759                 rte_le_to_cpu_32(resp->mrav_max_entries);
4760         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4761         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4762         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4763         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4764
4765         if (!ctx->tqm_fp_rings_count)
4766                 ctx->tqm_fp_rings_count = bp->max_q;
4767
4768         tqm_rings = ctx->tqm_fp_rings_count + 1;
4769
4770         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4771                             sizeof(*ctx_pg) * tqm_rings,
4772                             RTE_CACHE_LINE_SIZE);
4773         if (!ctx_pg) {
4774                 rc = -ENOMEM;
4775                 goto ctx_err;
4776         }
4777         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4778                 ctx->tqm_mem[i] = ctx_pg;
4779
4780         bp->ctx = ctx;
4781 ctx_err:
4782         HWRM_UNLOCK();
4783         return rc;
4784 }
4785
4786 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4787 {
4788         struct hwrm_func_backing_store_cfg_input req = {0};
4789         struct hwrm_func_backing_store_cfg_output *resp =
4790                 bp->hwrm_cmd_resp_addr;
4791         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4792         struct bnxt_ctx_pg_info *ctx_pg;
4793         uint32_t *num_entries;
4794         uint64_t *pg_dir;
4795         uint8_t *pg_attr;
4796         uint32_t ena;
4797         int i, rc;
4798
4799         if (!ctx)
4800                 return 0;
4801
4802         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4803         req.enables = rte_cpu_to_le_32(enables);
4804
4805         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4806                 ctx_pg = &ctx->qp_mem;
4807                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4808                 req.qp_num_qp1_entries =
4809                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4810                 req.qp_num_l2_entries =
4811                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4812                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4813                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4814                                       &req.qpc_pg_size_qpc_lvl,
4815                                       &req.qpc_page_dir);
4816         }
4817
4818         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4819                 ctx_pg = &ctx->srq_mem;
4820                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4821                 req.srq_num_l2_entries =
4822                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4823                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4824                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4825                                       &req.srq_pg_size_srq_lvl,
4826                                       &req.srq_page_dir);
4827         }
4828
4829         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4830                 ctx_pg = &ctx->cq_mem;
4831                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4832                 req.cq_num_l2_entries =
4833                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4834                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4835                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4836                                       &req.cq_pg_size_cq_lvl,
4837                                       &req.cq_page_dir);
4838         }
4839
4840         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4841                 ctx_pg = &ctx->vnic_mem;
4842                 req.vnic_num_vnic_entries =
4843                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4844                 req.vnic_num_ring_table_entries =
4845                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4846                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4847                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4848                                       &req.vnic_pg_size_vnic_lvl,
4849                                       &req.vnic_page_dir);
4850         }
4851
4852         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4853                 ctx_pg = &ctx->stat_mem;
4854                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4855                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4856                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4857                                       &req.stat_pg_size_stat_lvl,
4858                                       &req.stat_page_dir);
4859         }
4860
4861         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4862         num_entries = &req.tqm_sp_num_entries;
4863         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4864         pg_dir = &req.tqm_sp_page_dir;
4865         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4866         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4867                 if (!(enables & ena))
4868                         continue;
4869
4870                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4871
4872                 ctx_pg = ctx->tqm_mem[i];
4873                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4874                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4875         }
4876
4877         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4878         HWRM_CHECK_RESULT();
4879         HWRM_UNLOCK();
4880
4881         return rc;
4882 }
4883
4884 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4885 {
4886         struct hwrm_port_qstats_ext_input req = {0};
4887         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4888         struct bnxt_pf_info *pf = &bp->pf;
4889         int rc;
4890
4891         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4892               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4893                 return 0;
4894
4895         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4896
4897         req.port_id = rte_cpu_to_le_16(pf->port_id);
4898         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4899                 req.tx_stat_host_addr =
4900                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4901                 req.tx_stat_size =
4902                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4903         }
4904         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4905                 req.rx_stat_host_addr =
4906                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4907                 req.rx_stat_size =
4908                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4909         }
4910         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4911
4912         if (rc) {
4913                 bp->fw_rx_port_stats_ext_size = 0;
4914                 bp->fw_tx_port_stats_ext_size = 0;
4915         } else {
4916                 bp->fw_rx_port_stats_ext_size =
4917                         rte_le_to_cpu_16(resp->rx_stat_size);
4918                 bp->fw_tx_port_stats_ext_size =
4919                         rte_le_to_cpu_16(resp->tx_stat_size);
4920         }
4921
4922         HWRM_CHECK_RESULT();
4923         HWRM_UNLOCK();
4924
4925         return rc;
4926 }
4927
4928 int
4929 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4930 {
4931         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4932         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4933                 bp->hwrm_cmd_resp_addr;
4934         int rc = 0;
4935
4936         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4937         req.tunnel_type = type;
4938         req.dest_fid = bp->fw_fid;
4939         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4940         HWRM_CHECK_RESULT();
4941
4942         HWRM_UNLOCK();
4943
4944         return rc;
4945 }
4946
4947 int
4948 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4949 {
4950         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4951         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4952                 bp->hwrm_cmd_resp_addr;
4953         int rc = 0;
4954
4955         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4956         req.tunnel_type = type;
4957         req.dest_fid = bp->fw_fid;
4958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4959         HWRM_CHECK_RESULT();
4960
4961         HWRM_UNLOCK();
4962
4963         return rc;
4964 }
4965
4966 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4967 {
4968         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4969         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4970                 bp->hwrm_cmd_resp_addr;
4971         int rc = 0;
4972
4973         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4974         req.src_fid = bp->fw_fid;
4975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4976         HWRM_CHECK_RESULT();
4977
4978         if (type)
4979                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4980
4981         HWRM_UNLOCK();
4982
4983         return rc;
4984 }
4985
4986 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4987                                    uint16_t *dst_fid)
4988 {
4989         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4990         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4991                 bp->hwrm_cmd_resp_addr;
4992         int rc = 0;
4993
4994         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4995         req.src_fid = bp->fw_fid;
4996         req.tunnel_type = tun_type;
4997         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4998         HWRM_CHECK_RESULT();
4999
5000         if (dst_fid)
5001                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5002
5003         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5004
5005         HWRM_UNLOCK();
5006
5007         return rc;
5008 }
5009
5010 int bnxt_hwrm_set_mac(struct bnxt *bp)
5011 {
5012         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5013         struct hwrm_func_vf_cfg_input req = {0};
5014         int rc = 0;
5015
5016         if (!BNXT_VF(bp))
5017                 return 0;
5018
5019         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5020
5021         req.enables =
5022                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5023         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5024
5025         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5026
5027         HWRM_CHECK_RESULT();
5028
5029         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5030         HWRM_UNLOCK();
5031
5032         return rc;
5033 }
5034
5035 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5036 {
5037         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5038         struct hwrm_func_drv_if_change_input req = {0};
5039         uint32_t flags;
5040         int rc;
5041
5042         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5043                 return 0;
5044
5045         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5046          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5047          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5048          */
5049         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5050                 return 0;
5051
5052         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5053
5054         if (up)
5055                 req.flags =
5056                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5057
5058         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5059
5060         HWRM_CHECK_RESULT();
5061         flags = rte_le_to_cpu_32(resp->flags);
5062         HWRM_UNLOCK();
5063
5064         if (!up)
5065                 return 0;
5066
5067         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5068                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5069                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5070         }
5071
5072         return 0;
5073 }
5074
5075 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5076 {
5077         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5078         struct bnxt_error_recovery_info *info = bp->recovery_info;
5079         struct hwrm_error_recovery_qcfg_input req = {0};
5080         uint32_t flags = 0;
5081         unsigned int i;
5082         int rc;
5083
5084         /* Older FW does not have error recovery support */
5085         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5086                 return 0;
5087
5088         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5089
5090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5091
5092         HWRM_CHECK_RESULT();
5093
5094         flags = rte_le_to_cpu_32(resp->flags);
5095         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5096                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5097         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5098                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5099
5100         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5101             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5102                 rc = -EINVAL;
5103                 goto err;
5104         }
5105
5106         /* FW returned values are in units of 100msec */
5107         info->driver_polling_freq =
5108                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5109         info->master_func_wait_period =
5110                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5111         info->normal_func_wait_period =
5112                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5113         info->master_func_wait_period_after_reset =
5114                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5115         info->max_bailout_time_after_reset =
5116                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5117         info->status_regs[BNXT_FW_STATUS_REG] =
5118                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5119         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5120                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5121         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5122                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5123         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5124                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5125         info->reg_array_cnt =
5126                 rte_le_to_cpu_32(resp->reg_array_cnt);
5127
5128         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5129                 rc = -EINVAL;
5130                 goto err;
5131         }
5132
5133         for (i = 0; i < info->reg_array_cnt; i++) {
5134                 info->reset_reg[i] =
5135                         rte_le_to_cpu_32(resp->reset_reg[i]);
5136                 info->reset_reg_val[i] =
5137                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5138                 info->delay_after_reset[i] =
5139                         resp->delay_after_reset[i];
5140         }
5141 err:
5142         HWRM_UNLOCK();
5143
5144         /* Map the FW status registers */
5145         if (!rc)
5146                 rc = bnxt_map_fw_health_status_regs(bp);
5147
5148         if (rc) {
5149                 rte_free(bp->recovery_info);
5150                 bp->recovery_info = NULL;
5151         }
5152         return rc;
5153 }
5154
5155 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5156 {
5157         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5158         struct hwrm_fw_reset_input req = {0};
5159         int rc;
5160
5161         if (!BNXT_PF(bp))
5162                 return -EOPNOTSUPP;
5163
5164         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5165
5166         req.embedded_proc_type =
5167                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5168         req.selfrst_status =
5169                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5170         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5171
5172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5173                                     BNXT_USE_KONG(bp));
5174
5175         HWRM_CHECK_RESULT();
5176         HWRM_UNLOCK();
5177
5178         return rc;
5179 }
5180
5181 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5182 {
5183         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5184         struct hwrm_port_ts_query_input req = {0};
5185         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5186         uint32_t flags = 0;
5187         int rc;
5188
5189         if (!ptp)
5190                 return 0;
5191
5192         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5193
5194         switch (path) {
5195         case BNXT_PTP_FLAGS_PATH_TX:
5196                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5197                 break;
5198         case BNXT_PTP_FLAGS_PATH_RX:
5199                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5200                 break;
5201         case BNXT_PTP_FLAGS_CURRENT_TIME:
5202                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5203                 break;
5204         }
5205
5206         req.flags = rte_cpu_to_le_32(flags);
5207         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5208
5209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5210
5211         HWRM_CHECK_RESULT();
5212
5213         if (timestamp) {
5214                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5215                 *timestamp |=
5216                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5217         }
5218         HWRM_UNLOCK();
5219
5220         return rc;
5221 }
5222
5223 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5224 {
5225         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5226                                         bp->hwrm_cmd_resp_addr;
5227         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5228         uint32_t flags = 0;
5229         int rc = 0;
5230
5231         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5232                 return rc;
5233
5234         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5235                 PMD_DRV_LOG(DEBUG,
5236                             "Not a PF or trusted VF. Command not supported\n");
5237                 return 0;
5238         }
5239
5240         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5241         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5242
5243         HWRM_CHECK_RESULT();
5244         flags = rte_le_to_cpu_32(resp->flags);
5245         HWRM_UNLOCK();
5246
5247         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5248                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5249                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5250         }
5251
5252         return rc;
5253 }
5254
5255 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5256 {
5257         int rc = 0;
5258
5259         struct hwrm_cfa_counter_qcaps_input req = {0};
5260         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5261
5262         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5263                 PMD_DRV_LOG(DEBUG,
5264                             "Not a PF or trusted VF. Command not supported\n");
5265                 return 0;
5266         }
5267
5268         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5269         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5271
5272         HWRM_CHECK_RESULT();
5273         if (max_fc)
5274                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5275         HWRM_UNLOCK();
5276
5277         return 0;
5278 }
5279
5280 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5281 {
5282         int rc = 0;
5283         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5284         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5285
5286         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5287                 PMD_DRV_LOG(DEBUG,
5288                             "Not a PF or trusted VF. Command not supported\n");
5289                 return 0;
5290         }
5291
5292         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5293
5294         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5295         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5296         req.page_dir = rte_cpu_to_le_64(dma_addr);
5297
5298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5299
5300         HWRM_CHECK_RESULT();
5301         if (ctx_id) {
5302                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5303                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5304         }
5305         HWRM_UNLOCK();
5306
5307         return 0;
5308 }
5309
5310 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5311 {
5312         int rc = 0;
5313         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5314         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5315
5316         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5317                 PMD_DRV_LOG(DEBUG,
5318                             "Not a PF or trusted VF. Command not supported\n");
5319                 return 0;
5320         }
5321
5322         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5323
5324         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5325
5326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5327
5328         HWRM_CHECK_RESULT();
5329         HWRM_UNLOCK();
5330
5331         return rc;
5332 }
5333
5334 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5335                               uint16_t cntr, uint16_t ctx_id,
5336                               uint32_t num_entries, bool enable)
5337 {
5338         struct hwrm_cfa_counter_cfg_input req = {0};
5339         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5340         uint16_t flags = 0;
5341         int rc;
5342
5343         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5344                 PMD_DRV_LOG(DEBUG,
5345                             "Not a PF or trusted VF. Command not supported\n");
5346                 return 0;
5347         }
5348
5349         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5350
5351         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5352         req.counter_type = rte_cpu_to_le_16(cntr);
5353         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5354                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5355         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5356         if (dir == BNXT_DIR_RX)
5357                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5358         else if (dir == BNXT_DIR_TX)
5359                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5360         req.flags = rte_cpu_to_le_16(flags);
5361         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5362         req.num_entries = rte_cpu_to_le_32(num_entries);
5363
5364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5365         HWRM_CHECK_RESULT();
5366         HWRM_UNLOCK();
5367
5368         return 0;
5369 }
5370
5371 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5372                                  enum bnxt_flow_dir dir,
5373                                  uint16_t cntr,
5374                                  uint16_t num_entries)
5375 {
5376         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5377         struct hwrm_cfa_counter_qstats_input req = {0};
5378         uint16_t flow_ctx_id = 0;
5379         uint16_t flags = 0;
5380         int rc = 0;
5381
5382         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5383                 PMD_DRV_LOG(DEBUG,
5384                             "Not a PF or trusted VF. Command not supported\n");
5385                 return 0;
5386         }
5387
5388         if (dir == BNXT_DIR_RX) {
5389                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5390                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5391         } else if (dir == BNXT_DIR_TX) {
5392                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5393                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5394         }
5395
5396         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5397         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5398         req.counter_type = rte_cpu_to_le_16(cntr);
5399         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5400         req.num_entries = rte_cpu_to_le_16(num_entries);
5401         req.flags = rte_cpu_to_le_16(flags);
5402         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5403
5404         HWRM_CHECK_RESULT();
5405         HWRM_UNLOCK();
5406
5407         return 0;
5408 }