drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr =
 313                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                              struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct bnxt_vnic_info *vnic = NULL;
 371         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 372         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 373
 374         if (filter->fw_l2_filter_id == UINT64_MAX)
 375                 return 0;
 376
 377         if (filter->matching_l2_fltr_ptr)
 378                 l2_filter = filter->matching_l2_fltr_ptr;
 379
 380         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 381                     filter, l2_filter, l2_filter->l2_ref_cnt);
 382
 383         if (l2_filter->l2_ref_cnt == 0)
 384                 return 0;
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402         if (l2_filter->l2_ref_cnt == 0) {
 403                 vnic = l2_filter->vnic;
 404                 if (vnic) {
 405                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 406                                       bnxt_filter_info, next);
 407                         bnxt_free_filter(bp, l2_filter);
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 415                          uint16_t dst_id,
 416                          struct bnxt_filter_info *filter)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 420         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 421         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 422         const struct rte_eth_vmdq_rx_conf *conf =
 423                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 424         uint32_t enables = 0;
 425         uint16_t j = dst_id - 1;
 426
 427         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 428         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 429             conf->pool_map[j].pools & (1UL << j)) {
 430                 PMD_DRV_LOG(DEBUG,
 431                         "Add vlan %u to vmdq pool %u\n",
 432                         conf->pool_map[j].vlan_id, j);
 433
 434                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 435                 filter->enables |=
 436                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 437                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 438         }
 439
 440         if (filter->fw_l2_filter_id != UINT64_MAX)
 441                 bnxt_hwrm_clear_l2_filter(bp, filter);
 442
 443         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 444
 445         req.flags = rte_cpu_to_le_32(filter->flags);
 446
 447         enables = filter->enables |
 448               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 449         req.dst_id = rte_cpu_to_le_16(dst_id);
 450
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 453                 memcpy(req.l2_addr, filter->l2_addr,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 457                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 458                        RTE_ETHER_ADDR_LEN);
 459         if (enables &
 460             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 461                 req.l2_ovlan = filter->l2_ovlan;
 462         if (enables &
 463             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 464                 req.l2_ivlan = filter->l2_ivlan;
 465         if (enables &
 466             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 467                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 468         if (enables &
 469             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 470                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 471         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 472                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 473         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 474                 req.src_type = filter->src_type;
 475         if (filter->pri_hint) {
 476                 req.pri_hint = filter->pri_hint;
 477                 req.l2_filter_id_hint =
 478                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 479         }
 480
 481         req.enables = rte_cpu_to_le_32(enables);
 482
 483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 484
 485         HWRM_CHECK_RESULT();
 486
 487         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 488         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 489         HWRM_UNLOCK();
 490
 491         filter->l2_ref_cnt++;
 492
 493         return rc;
 494 }
 495
 496 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 497 {
 498         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 499         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 500         uint32_t flags = 0;
 501         int rc;
 502
 503         if (!ptp)
 504                 return 0;
 505
 506         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 507
 508         if (ptp->rx_filter)
 509                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 510         else
 511                 flags |=
 512                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 513         if (ptp->tx_tstamp_en)
 514                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 515         else
 516                 flags |=
 517                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 518         req.flags = rte_cpu_to_le_32(flags);
 519         req.enables = rte_cpu_to_le_32
 520                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 521         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 522
 523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 530 {
 531         int rc = 0;
 532         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 533         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 534         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 535
 536         if (ptp)
 537                 return 0;
 538
 539         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 540
 541         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 542
 543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 544
 545         HWRM_CHECK_RESULT();
 546
 547         if (!BNXT_CHIP_THOR(bp) &&
 548             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 549                 return 0;
 550
 551         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 552                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 553
 554         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 555         if (!ptp)
 556                 return -ENOMEM;
 557
 558         if (!BNXT_CHIP_THOR(bp)) {
 559                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 560                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 561                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 562                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 563                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 564                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 565                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 566                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 567                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 568                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 569                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 570                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 571                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 572                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 573                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 574                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 575                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 576                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 577         }
 578
 579         ptp->bp = bp;
 580         bp->ptp_cfg = ptp;
 581
 582         return 0;
 583 }
 584
 585 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 586 {
 587         int rc = 0;
 588         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 589         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 590         uint16_t new_max_vfs;
 591         uint32_t flags;
 592         int i;
 593
 594         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 595
 596         req.fid = rte_cpu_to_le_16(0xffff);
 597
 598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 599
 600         HWRM_CHECK_RESULT();
 601
 602         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 603         flags = rte_le_to_cpu_32(resp->flags);
 604         if (BNXT_PF(bp)) {
 605                 bp->pf.port_id = resp->port_id;
 606                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 607                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 608                 new_max_vfs = bp->pdev->max_vfs;
 609                 if (new_max_vfs != bp->pf.max_vfs) {
 610                         if (bp->pf.vf_info)
 611                                 rte_free(bp->pf.vf_info);
 612                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 613                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 614                         bp->pf.max_vfs = new_max_vfs;
 615                         for (i = 0; i < new_max_vfs; i++) {
 616                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 617                                 bp->pf.vf_info[i].vlan_table =
 618                                         rte_zmalloc("VF VLAN table",
 619                                                     getpagesize(),
 620                                                     getpagesize());
 621                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 622                                         PMD_DRV_LOG(ERR,
 623                                         "Fail to alloc VLAN table for VF %d\n",
 624                                         i);
 625                                 else
 626                                         rte_mem_lock_page(
 627                                                 bp->pf.vf_info[i].vlan_table);
 628                                 bp->pf.vf_info[i].vlan_as_table =
 629                                         rte_zmalloc("VF VLAN AS table",
 630                                                     getpagesize(),
 631                                                     getpagesize());
 632                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 633                                         PMD_DRV_LOG(ERR,
 634                                         "Alloc VLAN AS table for VF %d fail\n",
 635                                         i);
 636                                 else
 637                                         rte_mem_lock_page(
 638                                                bp->pf.vf_info[i].vlan_as_table);
 639                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 640                         }
 641                 }
 642         }
 643
 644         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 645         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 646         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 647         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 648         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 649         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 650         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 651         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 652         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 653         if (!BNXT_CHIP_THOR(bp))
 654                 bp->max_l2_ctx += bp->max_rx_em_flows;
 655         /* TODO: For now, do not support VMDq/RFS on VFs. */
 656         if (BNXT_PF(bp)) {
 657                 if (bp->pf.max_vfs)
 658                         bp->max_vnics = 1;
 659                 else
 660                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 661         } else {
 662                 bp->max_vnics = 1;
 663         }
 664         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 665         if (BNXT_PF(bp)) {
 666                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 667                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 668                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 669                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 670                         HWRM_UNLOCK();
 671                         bnxt_hwrm_ptp_qcfg(bp);
 672                 }
 673         }
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 676                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 677
 678         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 679                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 680                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 681         }
 682
 683         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 684                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 685
 686         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 687                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 688
 689         HWRM_UNLOCK();
 690
 691         return rc;
 692 }
 693
 694 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 695 {
 696         int rc;
 697
 698         rc = __bnxt_hwrm_func_qcaps(bp);
 699         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 700                 rc = bnxt_alloc_ctx_mem(bp);
 701                 if (rc)
 702                         return rc;
 703
 704                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 705                 if (!rc)
 706                         bp->flags |= BNXT_FLAG_NEW_RM;
 707         }
 708
 709         /* On older FW,
 710          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 711          * But the error can be ignored. Return success.
 712          */
 713
 714         return 0;
 715 }
 716
 717 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 718 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 719 {
 720         int rc = 0;
 721         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 722         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 723
 724         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 725
 726         req.target_id = rte_cpu_to_le_16(0xffff);
 727
 728         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 729
 730         HWRM_CHECK_RESULT();
 731
 732         if (rte_le_to_cpu_32(resp->flags) &
 733             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 734                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 735                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 736         }
 737
 738         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 739
 740         HWRM_UNLOCK();
 741
 742         return rc;
 743 }
 744
 745 int bnxt_hwrm_func_reset(struct bnxt *bp)
 746 {
 747         int rc = 0;
 748         struct hwrm_func_reset_input req = {.req_type = 0 };
 749         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 752
 753         req.enables = rte_cpu_to_le_32(0);
 754
 755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 756
 757         HWRM_CHECK_RESULT();
 758         HWRM_UNLOCK();
 759
 760         return rc;
 761 }
 762
 763 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 764 {
 765         int rc;
 766         uint32_t flags = 0;
 767         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 768         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 769
 770         if (bp->flags & BNXT_FLAG_REGISTERED)
 771                 return 0;
 772
 773         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 774                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 775         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 776                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 777
 778         /* PFs and trusted VFs should indicate the support of the
 779          * Master capability on non Stingray platform
 780          */
 781         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 782                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 783
 784         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 785         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 786                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 787         req.ver_maj = RTE_VER_YEAR;
 788         req.ver_min = RTE_VER_MONTH;
 789         req.ver_upd = RTE_VER_MINOR;
 790
 791         if (BNXT_PF(bp)) {
 792                 req.enables |= rte_cpu_to_le_32(
 793                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 794                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 795                        RTE_MIN(sizeof(req.vf_req_fwd),
 796                                sizeof(bp->pf.vf_req_fwd)));
 797
 798                 /*
 799                  * PF can sniff HWRM API issued by VF. This can be set up by
 800                  * linux driver and inherited by the DPDK PF driver. Clear
 801                  * this HWRM sniffer list in FW because DPDK PF driver does
 802                  * not support this.
 803                  */
 804                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 805         }
 806
 807         req.flags = rte_cpu_to_le_32(flags);
 808
 809         req.async_event_fwd[0] |=
 810                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 811                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 812                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 813                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 814                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 815         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 816                 req.async_event_fwd[0] |=
 817                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 818         req.async_event_fwd[1] |=
 819                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 820                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 821
 822         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 823
 824         HWRM_CHECK_RESULT();
 825
 826         flags = rte_le_to_cpu_32(resp->flags);
 827         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 828                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 829
 830         HWRM_UNLOCK();
 831
 832         bp->flags |= BNXT_FLAG_REGISTERED;
 833
 834         return rc;
 835 }
 836
 837 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 838 {
 839         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 840                 return 0;
 841
 842         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 843 }
 844
 845 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 846 {
 847         int rc;
 848         uint32_t flags = 0;
 849         uint32_t enables;
 850         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 851         struct hwrm_func_vf_cfg_input req = {0};
 852
 853         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 854
 855         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 856                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 857                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 858                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 859                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 860
 861         if (BNXT_HAS_RING_GRPS(bp)) {
 862                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 863                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 864         }
 865
 866         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 867         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 868                                             AGG_RING_MULTIPLIER);
 869         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 870         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 871                                               bp->tx_nr_rings +
 872                                               BNXT_NUM_ASYNC_CPR(bp));
 873         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 874         if (bp->vf_resv_strategy ==
 875             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 876                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 877                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 878                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 879                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 880                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 881                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 882         } else if (bp->vf_resv_strategy ==
 883                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 884                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 885                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 886         }
 887
 888         if (test)
 889                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 890                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 891                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 892                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 893                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 894                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 895
 896         if (test && BNXT_HAS_RING_GRPS(bp))
 897                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 898
 899         req.flags = rte_cpu_to_le_32(flags);
 900         req.enables |= rte_cpu_to_le_32(enables);
 901
 902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 903
 904         if (test)
 905                 HWRM_CHECK_RESULT_SILENT();
 906         else
 907                 HWRM_CHECK_RESULT();
 908
 909         HWRM_UNLOCK();
 910         return rc;
 911 }
 912
 913 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 914 {
 915         int rc;
 916         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 917         struct hwrm_func_resource_qcaps_input req = {0};
 918
 919         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 920         req.fid = rte_cpu_to_le_16(0xffff);
 921
 922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 923
 924         HWRM_CHECK_RESULT_SILENT();
 925
 926         if (BNXT_VF(bp)) {
 927                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 928                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 929                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 930                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 931                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 932                 /* func_resource_qcaps does not return max_rx_em_flows.
 933                  * So use the value provided by func_qcaps.
 934                  */
 935                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 936                 if (!BNXT_CHIP_THOR(bp))
 937                         bp->max_l2_ctx += bp->max_rx_em_flows;
 938                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 939                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 940         }
 941         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 942         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 943         if (bp->vf_resv_strategy >
 944             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 945                 bp->vf_resv_strategy =
 946                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 947
 948         HWRM_UNLOCK();
 949         return rc;
 950 }
 951
 952 int bnxt_hwrm_ver_get(struct bnxt *bp)
 953 {
 954         int rc = 0;
 955         struct hwrm_ver_get_input req = {.req_type = 0 };
 956         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 957         uint32_t fw_version;
 958         uint16_t max_resp_len;
 959         char type[RTE_MEMZONE_NAMESIZE];
 960         uint32_t dev_caps_cfg;
 961
 962         bp->max_req_len = HWRM_MAX_REQ_LEN;
 963         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 964
 965         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 966         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 967         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 968
 969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 970
 971         if (bp->flags & BNXT_FLAG_FW_RESET)
 972                 HWRM_CHECK_RESULT_SILENT();
 973         else
 974                 HWRM_CHECK_RESULT();
 975
 976         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 977                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 978                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 979                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 980         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 981                      (resp->hwrm_fw_min_8b << 16) |
 982                      (resp->hwrm_fw_bld_8b << 8) |
 983                      resp->hwrm_fw_rsvd_8b;
 984         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 985                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 986
 987         fw_version = resp->hwrm_intf_maj_8b << 16;
 988         fw_version |= resp->hwrm_intf_min_8b << 8;
 989         fw_version |= resp->hwrm_intf_upd_8b;
 990         bp->hwrm_spec_code = fw_version;
 991
 992         /* def_req_timeout value is in milliseconds */
 993         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 994         /* convert timeout to usec */
 995         bp->hwrm_cmd_timeout *= 1000;
 996         if (!bp->hwrm_cmd_timeout)
 997                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 998
 999         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1000                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1001                 rc = -EINVAL;
1002                 goto error;
1003         }
1004
1005         if (bp->max_req_len > resp->max_req_win_len) {
1006                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1007                 rc = -EINVAL;
1008         }
1009         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1010         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1011         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1012                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1013
1014         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1015         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1016
1017         if (bp->max_resp_len != max_resp_len) {
1018                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1019                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1020                         bp->pdev->addr.devid, bp->pdev->addr.function);
1021
1022                 rte_free(bp->hwrm_cmd_resp_addr);
1023
1024                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1025                 if (bp->hwrm_cmd_resp_addr == NULL) {
1026                         rc = -ENOMEM;
1027                         goto error;
1028                 }
1029                 bp->hwrm_cmd_resp_dma_addr =
1030                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1031                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1032                         PMD_DRV_LOG(ERR,
1033                         "Unable to map response buffer to physical memory.\n");
1034                         rc = -ENOMEM;
1035                         goto error;
1036                 }
1037                 bp->max_resp_len = max_resp_len;
1038         }
1039
1040         if ((dev_caps_cfg &
1041                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1042             (dev_caps_cfg &
1043              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1044                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1045                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1046         }
1047
1048         if (((dev_caps_cfg &
1049               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1050              (dev_caps_cfg &
1051               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1052             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1053                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1054                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1055                         bp->pdev->addr.devid, bp->pdev->addr.function);
1056
1057                 rte_free(bp->hwrm_short_cmd_req_addr);
1058
1059                 bp->hwrm_short_cmd_req_addr =
1060                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1061                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1062                         rc = -ENOMEM;
1063                         goto error;
1064                 }
1065                 bp->hwrm_short_cmd_req_dma_addr =
1066                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1067                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1068                         rte_free(bp->hwrm_short_cmd_req_addr);
1069                         PMD_DRV_LOG(ERR,
1070                                 "Unable to map buffer to physical memory.\n");
1071                         rc = -ENOMEM;
1072                         goto error;
1073                 }
1074         }
1075         if (dev_caps_cfg &
1076             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1077                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1078                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1079         }
1080         if (dev_caps_cfg &
1081             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1082                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1083         if (dev_caps_cfg &
1084             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1085                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1086                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1087         }
1088
1089 error:
1090         HWRM_UNLOCK();
1091         return rc;
1092 }
1093
1094 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1095 {
1096         int rc;
1097         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1098         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1099
1100         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1101                 return 0;
1102
1103         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1104         req.flags = flags;
1105
1106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107
1108         HWRM_CHECK_RESULT();
1109         HWRM_UNLOCK();
1110
1111         return rc;
1112 }
1113
1114 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1115 {
1116         int rc = 0;
1117         struct hwrm_port_phy_cfg_input req = {0};
1118         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         uint32_t enables = 0;
1120
1121         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1122
1123         if (conf->link_up) {
1124                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1125                 if (bp->link_info.auto_mode && conf->link_speed) {
1126                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1127                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1128                 }
1129
1130                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1131                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1133                 /*
1134                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1135                  * any auto mode, even "none".
1136                  */
1137                 if (!conf->link_speed) {
1138                         /* No speeds specified. Enable AutoNeg - all speeds */
1139                         req.auto_mode =
1140                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1141                 }
1142                 /* AutoNeg - Advertise speeds specified. */
1143                 if (conf->auto_link_speed_mask &&
1144                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1145                         req.auto_mode =
1146                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1147                         req.auto_link_speed_mask =
1148                                 conf->auto_link_speed_mask;
1149                         enables |=
1150                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1151                 }
1152
1153                 req.auto_duplex = conf->duplex;
1154                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1155                 req.auto_pause = conf->auto_pause;
1156                 req.force_pause = conf->force_pause;
1157                 /* Set force_pause if there is no auto or if there is a force */
1158                 if (req.auto_pause && !req.force_pause)
1159                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1160                 else
1161                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1162
1163                 req.enables = rte_cpu_to_le_32(enables);
1164         } else {
1165                 req.flags =
1166                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1167                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1168         }
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         HWRM_CHECK_RESULT();
1173         HWRM_UNLOCK();
1174
1175         return rc;
1176 }
1177
1178 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1179                                    struct bnxt_link_info *link_info)
1180 {
1181         int rc = 0;
1182         struct hwrm_port_phy_qcfg_input req = {0};
1183         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184
1185         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1186
1187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1188
1189         HWRM_CHECK_RESULT();
1190
1191         link_info->phy_link_status = resp->link;
1192         link_info->link_up =
1193                 (link_info->phy_link_status ==
1194                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1195         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1196         link_info->duplex = resp->duplex_cfg;
1197         link_info->pause = resp->pause;
1198         link_info->auto_pause = resp->auto_pause;
1199         link_info->force_pause = resp->force_pause;
1200         link_info->auto_mode = resp->auto_mode;
1201         link_info->phy_type = resp->phy_type;
1202         link_info->media_type = resp->media_type;
1203
1204         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1205         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1206         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1207         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1208         link_info->phy_ver[0] = resp->phy_maj;
1209         link_info->phy_ver[1] = resp->phy_min;
1210         link_info->phy_ver[2] = resp->phy_bld;
1211
1212         HWRM_UNLOCK();
1213
1214         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1215         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1216         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1217         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1218         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1219                     link_info->auto_link_speed_mask);
1220         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1221                     link_info->force_link_speed);
1222
1223         return rc;
1224 }
1225
1226 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1227 {
1228         int i = 0;
1229
1230         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1231                 if (bp->tx_cos_queue[i].profile ==
1232                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1233                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1234                         return true;
1235                 }
1236         }
1237         return false;
1238 }
1239
1240 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1241 {
1242         int i = 0;
1243
1244         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1245                 if (bp->tx_cos_queue[i].profile !=
1246                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1247                     bp->tx_cos_queue[i].id !=
1248                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1249                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1250                         break;
1251                 }
1252         }
1253 }
1254
1255 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1256 {
1257         int rc = 0;
1258         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1259         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1260         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1261         int i;
1262
1263 get_rx_info:
1264         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1265
1266         req.flags = rte_cpu_to_le_32(dir);
1267         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1268         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1269             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1270                 req.drv_qmap_cap =
1271                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1273
1274         HWRM_CHECK_RESULT();
1275
1276         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1277                 GET_TX_QUEUE_INFO(0);
1278                 GET_TX_QUEUE_INFO(1);
1279                 GET_TX_QUEUE_INFO(2);
1280                 GET_TX_QUEUE_INFO(3);
1281                 GET_TX_QUEUE_INFO(4);
1282                 GET_TX_QUEUE_INFO(5);
1283                 GET_TX_QUEUE_INFO(6);
1284                 GET_TX_QUEUE_INFO(7);
1285         } else  {
1286                 GET_RX_QUEUE_INFO(0);
1287                 GET_RX_QUEUE_INFO(1);
1288                 GET_RX_QUEUE_INFO(2);
1289                 GET_RX_QUEUE_INFO(3);
1290                 GET_RX_QUEUE_INFO(4);
1291                 GET_RX_QUEUE_INFO(5);
1292                 GET_RX_QUEUE_INFO(6);
1293                 GET_RX_QUEUE_INFO(7);
1294         }
1295
1296         HWRM_UNLOCK();
1297
1298         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1299                 goto done;
1300
1301         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1302                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1303         } else {
1304                 int j;
1305
1306                 /* iterate and find the COSq profile to use for Tx */
1307                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1308                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1309                                 if (bp->tx_cos_queue[i].id != 0xff)
1310                                         bp->tx_cosq_id[j++] =
1311                                                 bp->tx_cos_queue[i].id;
1312                         }
1313                 } else {
1314                         /* When CoS classification is disabled, for normal NIC
1315                          * operations, ideally we should look to use LOSSY.
1316                          * If not found, fallback to the first valid profile
1317                          */
1318                         if (!bnxt_find_lossy_profile(bp))
1319                                 bnxt_find_first_valid_profile(bp);
1320
1321                 }
1322         }
1323
1324         bp->max_tc = resp->max_configurable_queues;
1325         bp->max_lltc = resp->max_configurable_lossless_queues;
1326         if (bp->max_tc > BNXT_MAX_QUEUE)
1327                 bp->max_tc = BNXT_MAX_QUEUE;
1328         bp->max_q = bp->max_tc;
1329
1330         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1331                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1332                 goto get_rx_info;
1333         }
1334
1335 done:
1336         return rc;
1337 }
1338
1339 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1340                          struct bnxt_ring *ring,
1341                          uint32_t ring_type, uint32_t map_index,
1342                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1343                          uint16_t tx_cosq_id)
1344 {
1345         int rc = 0;
1346         uint32_t enables = 0;
1347         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1348         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1349         struct rte_mempool *mb_pool;
1350         uint16_t rx_buf_size;
1351
1352         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1353
1354         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1355         req.fbo = rte_cpu_to_le_32(0);
1356         /* Association of ring index with doorbell index */
1357         req.logical_id = rte_cpu_to_le_16(map_index);
1358         req.length = rte_cpu_to_le_32(ring->ring_size);
1359
1360         switch (ring_type) {
1361         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1362                 req.ring_type = ring_type;
1363                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1364                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1365                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1366                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1367                         enables |=
1368                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1369                 break;
1370         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1371                 req.ring_type = ring_type;
1372                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1373                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1374                 if (BNXT_CHIP_THOR(bp)) {
1375                         mb_pool = bp->rx_queues[0]->mb_pool;
1376                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1377                                       RTE_PKTMBUF_HEADROOM;
1378                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1379                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1380                         enables |=
1381                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1382                 }
1383                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1384                         enables |=
1385                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1386                 break;
1387         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1388                 req.ring_type = ring_type;
1389                 if (BNXT_HAS_NQ(bp)) {
1390                         /* Association of cp ring with nq */
1391                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1392                         enables |=
1393                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1394                 }
1395                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1396                 break;
1397         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1398                 req.ring_type = ring_type;
1399                 req.page_size = BNXT_PAGE_SHFT;
1400                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1401                 break;
1402         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1403                 req.ring_type = ring_type;
1404                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1405
1406                 mb_pool = bp->rx_queues[0]->mb_pool;
1407                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1408                               RTE_PKTMBUF_HEADROOM;
1409                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1410                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1411
1412                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1413                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1414                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1415                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1416                 break;
1417         default:
1418                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1419                         ring_type);
1420                 HWRM_UNLOCK();
1421                 return -EINVAL;
1422         }
1423         req.enables = rte_cpu_to_le_32(enables);
1424
1425         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1426
1427         if (rc || resp->error_code) {
1428                 if (rc == 0 && resp->error_code)
1429                         rc = rte_le_to_cpu_16(resp->error_code);
1430                 switch (ring_type) {
1431                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1432                         PMD_DRV_LOG(ERR,
1433                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1434                         HWRM_UNLOCK();
1435                         return rc;
1436                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1437                         PMD_DRV_LOG(ERR,
1438                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1439                         HWRM_UNLOCK();
1440                         return rc;
1441                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1442                         PMD_DRV_LOG(ERR,
1443                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1444                                     rc);
1445                         HWRM_UNLOCK();
1446                         return rc;
1447                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1448                         PMD_DRV_LOG(ERR,
1449                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1450                         HWRM_UNLOCK();
1451                         return rc;
1452                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1453                         PMD_DRV_LOG(ERR,
1454                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1455                         HWRM_UNLOCK();
1456                         return rc;
1457                 default:
1458                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1459                         HWRM_UNLOCK();
1460                         return rc;
1461                 }
1462         }
1463
1464         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1465         HWRM_UNLOCK();
1466         return rc;
1467 }
1468
1469 int bnxt_hwrm_ring_free(struct bnxt *bp,
1470                         struct bnxt_ring *ring, uint32_t ring_type)
1471 {
1472         int rc;
1473         struct hwrm_ring_free_input req = {.req_type = 0 };
1474         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1475
1476         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1477
1478         req.ring_type = ring_type;
1479         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1480
1481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482
1483         if (rc || resp->error_code) {
1484                 if (rc == 0 && resp->error_code)
1485                         rc = rte_le_to_cpu_16(resp->error_code);
1486                 HWRM_UNLOCK();
1487
1488                 switch (ring_type) {
1489                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1490                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1491                                 rc);
1492                         return rc;
1493                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1494                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1495                                 rc);
1496                         return rc;
1497                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1498                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1499                                 rc);
1500                         return rc;
1501                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1502                         PMD_DRV_LOG(ERR,
1503                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1504                         return rc;
1505                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1506                         PMD_DRV_LOG(ERR,
1507                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1508                         return rc;
1509                 default:
1510                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1511                         return rc;
1512                 }
1513         }
1514         HWRM_UNLOCK();
1515         return 0;
1516 }
1517
1518 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1519 {
1520         int rc = 0;
1521         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1522         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1523
1524         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1525
1526         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1527         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1528         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1529         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1530
1531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1532
1533         HWRM_CHECK_RESULT();
1534
1535         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1536
1537         HWRM_UNLOCK();
1538
1539         return rc;
1540 }
1541
1542 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1543 {
1544         int rc;
1545         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1546         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1547
1548         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1549
1550         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1551
1552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1553
1554         HWRM_CHECK_RESULT();
1555         HWRM_UNLOCK();
1556
1557         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1558         return rc;
1559 }
1560
1561 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1562 {
1563         int rc = 0;
1564         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1565         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1566
1567         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1568                 return rc;
1569
1570         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1571
1572         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1573
1574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1575
1576         HWRM_CHECK_RESULT();
1577         HWRM_UNLOCK();
1578
1579         return rc;
1580 }
1581
1582 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1583                                 unsigned int idx __rte_unused)
1584 {
1585         int rc;
1586         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1587         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1588
1589         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1590
1591         req.update_period_ms = rte_cpu_to_le_32(0);
1592
1593         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1594
1595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1596
1597         HWRM_CHECK_RESULT();
1598
1599         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1600
1601         HWRM_UNLOCK();
1602
1603         return rc;
1604 }
1605
1606 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1607                                 unsigned int idx __rte_unused)
1608 {
1609         int rc;
1610         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1611         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1612
1613         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1614
1615         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1616
1617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618
1619         HWRM_CHECK_RESULT();
1620         HWRM_UNLOCK();
1621
1622         return rc;
1623 }
1624
1625 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1626 {
1627         int rc = 0, i, j;
1628         struct hwrm_vnic_alloc_input req = { 0 };
1629         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630
1631         if (!BNXT_HAS_RING_GRPS(bp))
1632                 goto skip_ring_grps;
1633
1634         /* map ring groups to this vnic */
1635         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1636                 vnic->start_grp_id, vnic->end_grp_id);
1637         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1638                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1639
1640         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1641         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1643         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1644
1645 skip_ring_grps:
1646         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1647         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1648
1649         if (vnic->func_default)
1650                 req.flags =
1651                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1653
1654         HWRM_CHECK_RESULT();
1655
1656         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1657         HWRM_UNLOCK();
1658         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1659         return rc;
1660 }
1661
1662 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1663                                         struct bnxt_vnic_info *vnic,
1664                                         struct bnxt_plcmodes_cfg *pmode)
1665 {
1666         int rc = 0;
1667         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1668         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1669
1670         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1671
1672         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1673
1674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1675
1676         HWRM_CHECK_RESULT();
1677
1678         pmode->flags = rte_le_to_cpu_32(resp->flags);
1679         /* dflt_vnic bit doesn't exist in the _cfg command */
1680         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1681         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1682         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1683         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1684
1685         HWRM_UNLOCK();
1686
1687         return rc;
1688 }
1689
1690 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1691                                        struct bnxt_vnic_info *vnic,
1692                                        struct bnxt_plcmodes_cfg *pmode)
1693 {
1694         int rc = 0;
1695         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1696         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1697
1698         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1699                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1700                 return rc;
1701         }
1702
1703         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1704
1705         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1706         req.flags = rte_cpu_to_le_32(pmode->flags);
1707         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1708         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1709         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1710         req.enables = rte_cpu_to_le_32(
1711             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1712             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1713             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1714         );
1715
1716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1717
1718         HWRM_CHECK_RESULT();
1719         HWRM_UNLOCK();
1720
1721         return rc;
1722 }
1723
1724 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1725 {
1726         int rc = 0;
1727         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1728         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1729         struct bnxt_plcmodes_cfg pmodes = { 0 };
1730         uint32_t ctx_enable_flag = 0;
1731         uint32_t enables = 0;
1732
1733         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1734                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1735                 return rc;
1736         }
1737
1738         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1739         if (rc)
1740                 return rc;
1741
1742         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1743
1744         if (BNXT_CHIP_THOR(bp)) {
1745                 int dflt_rxq = vnic->start_grp_id;
1746                 struct bnxt_rx_ring_info *rxr;
1747                 struct bnxt_cp_ring_info *cpr;
1748                 struct bnxt_rx_queue *rxq;
1749                 int i;
1750
1751                 /*
1752                  * The first active receive ring is used as the VNIC
1753                  * default receive ring. If there are no active receive
1754                  * rings (all corresponding receive queues are stopped),
1755                  * the first receive ring is used.
1756                  */
1757                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1758                         rxq = bp->eth_dev->data->rx_queues[i];
1759                         if (rxq->rx_started) {
1760                                 dflt_rxq = i;
1761                                 break;
1762                         }
1763                 }
1764
1765                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1766                 rxr = rxq->rx_ring;
1767                 cpr = rxq->cp_ring;
1768
1769                 req.default_rx_ring_id =
1770                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1771                 req.default_cmpl_ring_id =
1772                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1773                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1774                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1775                 goto config_mru;
1776         }
1777
1778         /* Only RSS support for now TBD: COS & LB */
1779         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1780         if (vnic->lb_rule != 0xffff)
1781                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1782         if (vnic->cos_rule != 0xffff)
1783                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1784         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1785                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1786                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1787         }
1788         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1789                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1790                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1791         }
1792
1793         enables |= ctx_enable_flag;
1794         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1795         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1796         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1797         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1798
1799 config_mru:
1800         req.enables = rte_cpu_to_le_32(enables);
1801         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1802         req.mru = rte_cpu_to_le_16(vnic->mru);
1803         /* Configure default VNIC only once. */
1804         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1805                 req.flags |=
1806                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1807                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1808         }
1809         if (vnic->vlan_strip)
1810                 req.flags |=
1811                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1812         if (vnic->bd_stall)
1813                 req.flags |=
1814                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1815         if (vnic->roce_dual)
1816                 req.flags |= rte_cpu_to_le_32(
1817                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1818         if (vnic->roce_only)
1819                 req.flags |= rte_cpu_to_le_32(
1820                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1821         if (vnic->rss_dflt_cr)
1822                 req.flags |= rte_cpu_to_le_32(
1823                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1824
1825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826
1827         HWRM_CHECK_RESULT();
1828         HWRM_UNLOCK();
1829
1830         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1831
1832         return rc;
1833 }
1834
1835 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1836                 int16_t fw_vf_id)
1837 {
1838         int rc = 0;
1839         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1840         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1841
1842         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1843                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1844                 return rc;
1845         }
1846         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1847
1848         req.enables =
1849                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1850         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1851         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1852
1853         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854
1855         HWRM_CHECK_RESULT();
1856
1857         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1858         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1859         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1860         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1861         vnic->mru = rte_le_to_cpu_16(resp->mru);
1862         vnic->func_default = rte_le_to_cpu_32(
1863                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1864         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1865                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1866         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1867                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1868         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1869                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1870         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1871                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1872         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1873                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1874
1875         HWRM_UNLOCK();
1876
1877         return rc;
1878 }
1879
1880 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1881                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1882 {
1883         int rc = 0;
1884         uint16_t ctx_id;
1885         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1886         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1887                                                 bp->hwrm_cmd_resp_addr;
1888
1889         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1890
1891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892         HWRM_CHECK_RESULT();
1893
1894         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1895         if (!BNXT_HAS_RING_GRPS(bp))
1896                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1897         else if (ctx_idx == 0)
1898                 vnic->rss_rule = ctx_id;
1899
1900         HWRM_UNLOCK();
1901
1902         return rc;
1903 }
1904
1905 static
1906 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1907                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1908 {
1909         int rc = 0;
1910         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1911         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1912                                                 bp->hwrm_cmd_resp_addr;
1913
1914         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1915                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1916                 return rc;
1917         }
1918         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1919
1920         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1921
1922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1923
1924         HWRM_CHECK_RESULT();
1925         HWRM_UNLOCK();
1926
1927         return rc;
1928 }
1929
1930 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1931 {
1932         int rc = 0;
1933
1934         if (BNXT_CHIP_THOR(bp)) {
1935                 int j;
1936
1937                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1938                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1939                                                       vnic,
1940                                                       vnic->fw_grp_ids[j]);
1941                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1942                 }
1943                 vnic->num_lb_ctxts = 0;
1944         } else {
1945                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1946                 vnic->rss_rule = INVALID_HW_RING_ID;
1947         }
1948
1949         return rc;
1950 }
1951
1952 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1953 {
1954         int rc = 0;
1955         struct hwrm_vnic_free_input req = {.req_type = 0 };
1956         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1957
1958         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1959                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1960                 return rc;
1961         }
1962
1963         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1964
1965         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1966
1967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968
1969         HWRM_CHECK_RESULT();
1970         HWRM_UNLOCK();
1971
1972         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1973         /* Configure default VNIC again if necessary. */
1974         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1975                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1976
1977         return rc;
1978 }
1979
1980 static int
1981 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1982 {
1983         int i;
1984         int rc = 0;
1985         int nr_ctxs = vnic->num_lb_ctxts;
1986         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1987         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1988
1989         for (i = 0; i < nr_ctxs; i++) {
1990                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1991
1992                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1994                 req.hash_mode_flags = vnic->hash_mode;
1995
1996                 req.hash_key_tbl_addr =
1997                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1998
1999                 req.ring_grp_tbl_addr =
2000                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2001                                          i * HW_HASH_INDEX_SIZE);
2002                 req.ring_table_pair_index = i;
2003                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2004
2005                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2006                                             BNXT_USE_CHIMP_MB);
2007
2008                 HWRM_CHECK_RESULT();
2009                 HWRM_UNLOCK();
2010         }
2011
2012         return rc;
2013 }
2014
2015 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2016                            struct bnxt_vnic_info *vnic)
2017 {
2018         int rc = 0;
2019         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2020         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021
2022         if (!vnic->rss_table)
2023                 return 0;
2024
2025         if (BNXT_CHIP_THOR(bp))
2026                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2027
2028         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2029
2030         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2031         req.hash_mode_flags = vnic->hash_mode;
2032
2033         req.ring_grp_tbl_addr =
2034             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2035         req.hash_key_tbl_addr =
2036             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2037         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2038         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2039
2040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2041
2042         HWRM_CHECK_RESULT();
2043         HWRM_UNLOCK();
2044
2045         return rc;
2046 }
2047
2048 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2049                         struct bnxt_vnic_info *vnic)
2050 {
2051         int rc = 0;
2052         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2053         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2054         uint16_t size;
2055
2056         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2058                 return rc;
2059         }
2060
2061         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2062
2063         req.flags = rte_cpu_to_le_32(
2064                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2065
2066         req.enables = rte_cpu_to_le_32(
2067                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2068
2069         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2070         size -= RTE_PKTMBUF_HEADROOM;
2071         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2072
2073         req.jumbo_thresh = rte_cpu_to_le_16(size);
2074         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077
2078         HWRM_CHECK_RESULT();
2079         HWRM_UNLOCK();
2080
2081         return rc;
2082 }
2083
2084 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2085                         struct bnxt_vnic_info *vnic, bool enable)
2086 {
2087         int rc = 0;
2088         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2089         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2090
2091         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2092                 if (enable)
2093                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2094                 return -ENOTSUP;
2095         }
2096
2097         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2099                 return 0;
2100         }
2101
2102         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2103
2104         if (enable) {
2105                 req.enables = rte_cpu_to_le_32(
2106                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2107                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2108                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2109                 req.flags = rte_cpu_to_le_32(
2110                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2112                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2113                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2114                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2115                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2116                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2117                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2118                 req.min_agg_len = rte_cpu_to_le_32(512);
2119         }
2120         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2121
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123
2124         HWRM_CHECK_RESULT();
2125         HWRM_UNLOCK();
2126
2127         return rc;
2128 }
2129
2130 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2131 {
2132         struct hwrm_func_cfg_input req = {0};
2133         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2134         int rc;
2135
2136         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2137         req.enables = rte_cpu_to_le_32(
2138                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2139         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2140         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2141
2142         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2143
2144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2145         HWRM_CHECK_RESULT();
2146         HWRM_UNLOCK();
2147
2148         bp->pf.vf_info[vf].random_mac = false;
2149
2150         return rc;
2151 }
2152
2153 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2154                                   uint64_t *dropped)
2155 {
2156         int rc = 0;
2157         struct hwrm_func_qstats_input req = {.req_type = 0};
2158         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2159
2160         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2161
2162         req.fid = rte_cpu_to_le_16(fid);
2163
2164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2165
2166         HWRM_CHECK_RESULT();
2167
2168         if (dropped)
2169                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2170
2171         HWRM_UNLOCK();
2172
2173         return rc;
2174 }
2175
2176 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2177                           struct rte_eth_stats *stats)
2178 {
2179         int rc = 0;
2180         struct hwrm_func_qstats_input req = {.req_type = 0};
2181         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2182
2183         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2184
2185         req.fid = rte_cpu_to_le_16(fid);
2186
2187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2188
2189         HWRM_CHECK_RESULT();
2190
2191         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2192         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2193         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2194         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2195         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2196         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2197
2198         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2199         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2200         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2201         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2202         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2203         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2204
2205         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2206         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2207         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2208
2209         HWRM_UNLOCK();
2210
2211         return rc;
2212 }
2213
2214 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2215 {
2216         int rc = 0;
2217         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2218         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2219
2220         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2221
2222         req.fid = rte_cpu_to_le_16(fid);
2223
2224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2225
2226         HWRM_CHECK_RESULT();
2227         HWRM_UNLOCK();
2228
2229         return rc;
2230 }
2231
2232 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2233 {
2234         unsigned int i;
2235         int rc = 0;
2236
2237         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2238                 struct bnxt_tx_queue *txq;
2239                 struct bnxt_rx_queue *rxq;
2240                 struct bnxt_cp_ring_info *cpr;
2241
2242                 if (i >= bp->rx_cp_nr_rings) {
2243                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2244                         cpr = txq->cp_ring;
2245                 } else {
2246                         rxq = bp->rx_queues[i];
2247                         cpr = rxq->cp_ring;
2248                 }
2249
2250                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2251                 if (rc)
2252                         return rc;
2253         }
2254         return 0;
2255 }
2256
2257 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2258 {
2259         int rc;
2260         unsigned int i;
2261         struct bnxt_cp_ring_info *cpr;
2262
2263         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2264
2265                 if (i >= bp->rx_cp_nr_rings) {
2266                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2267                 } else {
2268                         cpr = bp->rx_queues[i]->cp_ring;
2269                         if (BNXT_HAS_RING_GRPS(bp))
2270                                 bp->grp_info[i].fw_stats_ctx = -1;
2271                 }
2272                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2273                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2274                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2275                         if (rc)
2276                                 return rc;
2277                 }
2278         }
2279         return 0;
2280 }
2281
2282 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2283 {
2284         unsigned int i;
2285         int rc = 0;
2286
2287         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2288                 struct bnxt_tx_queue *txq;
2289                 struct bnxt_rx_queue *rxq;
2290                 struct bnxt_cp_ring_info *cpr;
2291
2292                 if (i >= bp->rx_cp_nr_rings) {
2293                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2294                         cpr = txq->cp_ring;
2295                 } else {
2296                         rxq = bp->rx_queues[i];
2297                         cpr = rxq->cp_ring;
2298                 }
2299
2300                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2301
2302                 if (rc)
2303                         return rc;
2304         }
2305         return rc;
2306 }
2307
2308 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2309 {
2310         uint16_t idx;
2311         uint32_t rc = 0;
2312
2313         if (!BNXT_HAS_RING_GRPS(bp))
2314                 return 0;
2315
2316         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2317
2318                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2319                         continue;
2320
2321                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2322
2323                 if (rc)
2324                         return rc;
2325         }
2326         return rc;
2327 }
2328
2329 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2330 {
2331         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2332
2333         bnxt_hwrm_ring_free(bp, cp_ring,
2334                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2335         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2336         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2337                                      sizeof(*cpr->cp_desc_ring));
2338         cpr->cp_raw_cons = 0;
2339         cpr->valid = 0;
2340 }
2341
2342 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2343 {
2344         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2345
2346         bnxt_hwrm_ring_free(bp, cp_ring,
2347                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2348         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2349         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2350                         sizeof(*cpr->cp_desc_ring));
2351         cpr->cp_raw_cons = 0;
2352         cpr->valid = 0;
2353 }
2354
2355 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2356 {
2357         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2358         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2359         struct bnxt_ring *ring = rxr->rx_ring_struct;
2360         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2361
2362         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2363                 bnxt_hwrm_ring_free(bp, ring,
2364                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2365                 ring->fw_ring_id = INVALID_HW_RING_ID;
2366                 if (BNXT_HAS_RING_GRPS(bp))
2367                         bp->grp_info[queue_index].rx_fw_ring_id =
2368                                                         INVALID_HW_RING_ID;
2369                 memset(rxr->rx_desc_ring, 0,
2370                        rxr->rx_ring_struct->ring_size *
2371                        sizeof(*rxr->rx_desc_ring));
2372                 memset(rxr->rx_buf_ring, 0,
2373                        rxr->rx_ring_struct->ring_size *
2374                        sizeof(*rxr->rx_buf_ring));
2375                 rxr->rx_prod = 0;
2376         }
2377         ring = rxr->ag_ring_struct;
2378         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2379                 bnxt_hwrm_ring_free(bp, ring,
2380                                     BNXT_CHIP_THOR(bp) ?
2381                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2382                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2383                 ring->fw_ring_id = INVALID_HW_RING_ID;
2384                 memset(rxr->ag_buf_ring, 0,
2385                        rxr->ag_ring_struct->ring_size *
2386                        sizeof(*rxr->ag_buf_ring));
2387                 rxr->ag_prod = 0;
2388                 if (BNXT_HAS_RING_GRPS(bp))
2389                         bp->grp_info[queue_index].ag_fw_ring_id =
2390                                                         INVALID_HW_RING_ID;
2391         }
2392         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2393                 bnxt_free_cp_ring(bp, cpr);
2394
2395         if (BNXT_HAS_RING_GRPS(bp))
2396                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2397 }
2398
2399 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2400 {
2401         unsigned int i;
2402
2403         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2404                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2405                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2406                 struct bnxt_ring *ring = txr->tx_ring_struct;
2407                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2408
2409                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2410                         bnxt_hwrm_ring_free(bp, ring,
2411                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2412                         ring->fw_ring_id = INVALID_HW_RING_ID;
2413                         memset(txr->tx_desc_ring, 0,
2414                                         txr->tx_ring_struct->ring_size *
2415                                         sizeof(*txr->tx_desc_ring));
2416                         memset(txr->tx_buf_ring, 0,
2417                                         txr->tx_ring_struct->ring_size *
2418                                         sizeof(*txr->tx_buf_ring));
2419                         txr->tx_prod = 0;
2420                         txr->tx_cons = 0;
2421                 }
2422                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2423                         bnxt_free_cp_ring(bp, cpr);
2424                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2425                 }
2426         }
2427
2428         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2429                 bnxt_free_hwrm_rx_ring(bp, i);
2430
2431         return 0;
2432 }
2433
2434 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2435 {
2436         uint16_t i;
2437         uint32_t rc = 0;
2438
2439         if (!BNXT_HAS_RING_GRPS(bp))
2440                 return 0;
2441
2442         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2443                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2444                 if (rc)
2445                         return rc;
2446         }
2447         return rc;
2448 }
2449
2450 /*
2451  * HWRM utility functions
2452  */
2453
2454 void bnxt_free_hwrm_resources(struct bnxt *bp)
2455 {
2456         /* Release memzone */
2457         rte_free(bp->hwrm_cmd_resp_addr);
2458         rte_free(bp->hwrm_short_cmd_req_addr);
2459         bp->hwrm_cmd_resp_addr = NULL;
2460         bp->hwrm_short_cmd_req_addr = NULL;
2461         bp->hwrm_cmd_resp_dma_addr = 0;
2462         bp->hwrm_short_cmd_req_dma_addr = 0;
2463 }
2464
2465 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2466 {
2467         struct rte_pci_device *pdev = bp->pdev;
2468         char type[RTE_MEMZONE_NAMESIZE];
2469
2470         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2471                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2472         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2473         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2474         if (bp->hwrm_cmd_resp_addr == NULL)
2475                 return -ENOMEM;
2476         bp->hwrm_cmd_resp_dma_addr =
2477                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2478         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2479                 PMD_DRV_LOG(ERR,
2480                         "unable to map response address to physical memory\n");
2481                 return -ENOMEM;
2482         }
2483         rte_spinlock_init(&bp->hwrm_lock);
2484
2485         return 0;
2486 }
2487
2488 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2489 {
2490         struct bnxt_filter_info *filter;
2491         int rc = 0;
2492
2493         STAILQ_FOREACH(filter, &vnic->filter, next) {
2494                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2495                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2496                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2497                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2498                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2499                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2500                 bnxt_free_filter(bp, filter);
2501         }
2502         return rc;
2503 }
2504
2505 static int
2506 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2507 {
2508         struct bnxt_filter_info *filter;
2509         struct rte_flow *flow;
2510         int rc = 0;
2511
2512         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2513                 flow = STAILQ_FIRST(&vnic->flow_list);
2514                 filter = flow->filter;
2515                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2516                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2517                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2518                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2519                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2520                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2521
2522                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2523                 rte_free(flow);
2524         }
2525         return rc;
2526 }
2527
2528 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2529 {
2530         struct bnxt_filter_info *filter;
2531         int rc = 0;
2532
2533         STAILQ_FOREACH(filter, &vnic->filter, next) {
2534                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2535                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2536                                                      filter);
2537                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2538                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2539                                                          filter);
2540                 else
2541                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2542                                                      filter);
2543                 if (rc)
2544                         break;
2545         }
2546         return rc;
2547 }
2548
2549 void bnxt_free_tunnel_ports(struct bnxt *bp)
2550 {
2551         if (bp->vxlan_port_cnt)
2552                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2553                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2554         bp->vxlan_port = 0;
2555         if (bp->geneve_port_cnt)
2556                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2557                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2558         bp->geneve_port = 0;
2559 }
2560
2561 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2562 {
2563         int i;
2564
2565         if (bp->vnic_info == NULL)
2566                 return;
2567
2568         /*
2569          * Cleanup VNICs in reverse order, to make sure the L2 filter
2570          * from vnic0 is last to be cleaned up.
2571          */
2572         for (i = bp->max_vnics - 1; i >= 0; i--) {
2573                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2574
2575                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2576                         continue;
2577
2578                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2579
2580                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2581
2582                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2583
2584                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2585
2586                 bnxt_hwrm_vnic_free(bp, vnic);
2587
2588                 rte_free(vnic->fw_grp_ids);
2589         }
2590         /* Ring resources */
2591         bnxt_free_all_hwrm_rings(bp);
2592         bnxt_free_all_hwrm_ring_grps(bp);
2593         bnxt_free_all_hwrm_stat_ctxs(bp);
2594         bnxt_free_tunnel_ports(bp);
2595 }
2596
2597 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2598 {
2599         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2600
2601         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2602                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2603
2604         switch (conf_link_speed) {
2605         case ETH_LINK_SPEED_10M_HD:
2606         case ETH_LINK_SPEED_100M_HD:
2607                 /* FALLTHROUGH */
2608                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2609         }
2610         return hw_link_duplex;
2611 }
2612
2613 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2614 {
2615         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2616 }
2617
2618 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2619 {
2620         uint16_t eth_link_speed = 0;
2621
2622         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2623                 return ETH_LINK_SPEED_AUTONEG;
2624
2625         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2626         case ETH_LINK_SPEED_100M:
2627         case ETH_LINK_SPEED_100M_HD:
2628                 /* FALLTHROUGH */
2629                 eth_link_speed =
2630                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2631                 break;
2632         case ETH_LINK_SPEED_1G:
2633                 eth_link_speed =
2634                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2635                 break;
2636         case ETH_LINK_SPEED_2_5G:
2637                 eth_link_speed =
2638                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2639                 break;
2640         case ETH_LINK_SPEED_10G:
2641                 eth_link_speed =
2642                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2643                 break;
2644         case ETH_LINK_SPEED_20G:
2645                 eth_link_speed =
2646                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2647                 break;
2648         case ETH_LINK_SPEED_25G:
2649                 eth_link_speed =
2650                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2651                 break;
2652         case ETH_LINK_SPEED_40G:
2653                 eth_link_speed =
2654                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2655                 break;
2656         case ETH_LINK_SPEED_50G:
2657                 eth_link_speed =
2658                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2659                 break;
2660         case ETH_LINK_SPEED_100G:
2661                 eth_link_speed =
2662                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2663                 break;
2664         default:
2665                 PMD_DRV_LOG(ERR,
2666                         "Unsupported link speed %d; default to AUTO\n",
2667                         conf_link_speed);
2668                 break;
2669         }
2670         return eth_link_speed;
2671 }
2672
2673 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2674                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2675                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2676                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2677
2678 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2679 {
2680         uint32_t one_speed;
2681
2682         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2683                 return 0;
2684
2685         if (link_speed & ETH_LINK_SPEED_FIXED) {
2686                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2687
2688                 if (one_speed & (one_speed - 1)) {
2689                         PMD_DRV_LOG(ERR,
2690                                 "Invalid advertised speeds (%u) for port %u\n",
2691                                 link_speed, port_id);
2692                         return -EINVAL;
2693                 }
2694                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2695                         PMD_DRV_LOG(ERR,
2696                                 "Unsupported advertised speed (%u) for port %u\n",
2697                                 link_speed, port_id);
2698                         return -EINVAL;
2699                 }
2700         } else {
2701                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2702                         PMD_DRV_LOG(ERR,
2703                                 "Unsupported advertised speeds (%u) for port %u\n",
2704                                 link_speed, port_id);
2705                         return -EINVAL;
2706                 }
2707         }
2708         return 0;
2709 }
2710
2711 static uint16_t
2712 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2713 {
2714         uint16_t ret = 0;
2715
2716         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2717                 if (bp->link_info.support_speeds)
2718                         return bp->link_info.support_speeds;
2719                 link_speed = BNXT_SUPPORTED_SPEEDS;
2720         }
2721
2722         if (link_speed & ETH_LINK_SPEED_100M)
2723                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2724         if (link_speed & ETH_LINK_SPEED_100M_HD)
2725                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2726         if (link_speed & ETH_LINK_SPEED_1G)
2727                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2728         if (link_speed & ETH_LINK_SPEED_2_5G)
2729                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2730         if (link_speed & ETH_LINK_SPEED_10G)
2731                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2732         if (link_speed & ETH_LINK_SPEED_20G)
2733                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2734         if (link_speed & ETH_LINK_SPEED_25G)
2735                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2736         if (link_speed & ETH_LINK_SPEED_40G)
2737                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2738         if (link_speed & ETH_LINK_SPEED_50G)
2739                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2740         if (link_speed & ETH_LINK_SPEED_100G)
2741                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2742         return ret;
2743 }
2744
2745 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2746 {
2747         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2748
2749         switch (hw_link_speed) {
2750         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2751                 eth_link_speed = ETH_SPEED_NUM_100M;
2752                 break;
2753         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2754                 eth_link_speed = ETH_SPEED_NUM_1G;
2755                 break;
2756         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2757                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2758                 break;
2759         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2760                 eth_link_speed = ETH_SPEED_NUM_10G;
2761                 break;
2762         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2763                 eth_link_speed = ETH_SPEED_NUM_20G;
2764                 break;
2765         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2766                 eth_link_speed = ETH_SPEED_NUM_25G;
2767                 break;
2768         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2769                 eth_link_speed = ETH_SPEED_NUM_40G;
2770                 break;
2771         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2772                 eth_link_speed = ETH_SPEED_NUM_50G;
2773                 break;
2774         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2775                 eth_link_speed = ETH_SPEED_NUM_100G;
2776                 break;
2777         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2778         default:
2779                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2780                         hw_link_speed);
2781                 break;
2782         }
2783         return eth_link_speed;
2784 }
2785
2786 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2787 {
2788         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2789
2790         switch (hw_link_duplex) {
2791         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2792         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2793                 /* FALLTHROUGH */
2794                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2795                 break;
2796         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2797                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2798                 break;
2799         default:
2800                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2801                         hw_link_duplex);
2802                 break;
2803         }
2804         return eth_link_duplex;
2805 }
2806
2807 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2808 {
2809         int rc = 0;
2810         struct bnxt_link_info *link_info = &bp->link_info;
2811
2812         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2813         if (rc) {
2814                 PMD_DRV_LOG(ERR,
2815                         "Get link config failed with rc %d\n", rc);
2816                 goto exit;
2817         }
2818         if (link_info->link_speed)
2819                 link->link_speed =
2820                         bnxt_parse_hw_link_speed(link_info->link_speed);
2821         else
2822                 link->link_speed = ETH_SPEED_NUM_NONE;
2823         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2824         link->link_status = link_info->link_up;
2825         link->link_autoneg = link_info->auto_mode ==
2826                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2827                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2828 exit:
2829         return rc;
2830 }
2831
2832 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2833 {
2834         int rc = 0;
2835         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2836         struct bnxt_link_info link_req;
2837         uint16_t speed, autoneg;
2838
2839         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2840                 return 0;
2841
2842         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2843                         bp->eth_dev->data->port_id);
2844         if (rc)
2845                 goto error;
2846
2847         memset(&link_req, 0, sizeof(link_req));
2848         link_req.link_up = link_up;
2849         if (!link_up)
2850                 goto port_phy_cfg;
2851
2852         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2853         if (BNXT_CHIP_THOR(bp) &&
2854             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2855                 /* 40G is not supported as part of media auto detect.
2856                  * The speed should be forced and autoneg disabled
2857                  * to configure 40G speed.
2858                  */
2859                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2860                 autoneg = 0;
2861         }
2862
2863         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2864         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2865         /* Autoneg can be done only when the FW allows.
2866          * When user configures fixed speed of 40G and later changes to
2867          * any other speed, auto_link_speed/force_link_speed is still set
2868          * to 40G until link comes up at new speed.
2869          */
2870         if (autoneg == 1 &&
2871             !(!BNXT_CHIP_THOR(bp) &&
2872               (bp->link_info.auto_link_speed ||
2873                bp->link_info.force_link_speed))) {
2874                 link_req.phy_flags |=
2875                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2876                 link_req.auto_link_speed_mask =
2877                         bnxt_parse_eth_link_speed_mask(bp,
2878                                                        dev_conf->link_speeds);
2879         } else {
2880                 if (bp->link_info.phy_type ==
2881                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2882                     bp->link_info.phy_type ==
2883                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2884                     bp->link_info.media_type ==
2885                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2886                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2887                         return -EINVAL;
2888                 }
2889
2890                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2891                 /* If user wants a particular speed try that first. */
2892                 if (speed)
2893                         link_req.link_speed = speed;
2894                 else if (bp->link_info.force_link_speed)
2895                         link_req.link_speed = bp->link_info.force_link_speed;
2896                 else
2897                         link_req.link_speed = bp->link_info.auto_link_speed;
2898         }
2899         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2900         link_req.auto_pause = bp->link_info.auto_pause;
2901         link_req.force_pause = bp->link_info.force_pause;
2902
2903 port_phy_cfg:
2904         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2905         if (rc) {
2906                 PMD_DRV_LOG(ERR,
2907                         "Set link config failed with rc %d\n", rc);
2908         }
2909
2910 error:
2911         return rc;
2912 }
2913
2914 /* JIRA 22088 */
2915 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2916 {
2917         struct hwrm_func_qcfg_input req = {0};
2918         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2919         uint16_t flags;
2920         int rc = 0;
2921
2922         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2923         req.fid = rte_cpu_to_le_16(0xffff);
2924
2925         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2926
2927         HWRM_CHECK_RESULT();
2928
2929         /* Hard Coded.. 0xfff VLAN ID mask */
2930         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2931         flags = rte_le_to_cpu_16(resp->flags);
2932         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2933                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2934
2935         if (BNXT_VF(bp) &&
2936             !BNXT_VF_IS_TRUSTED(bp) &&
2937             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2938                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2939                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2940         } else if (BNXT_VF(bp) &&
2941                    BNXT_VF_IS_TRUSTED(bp) &&
2942                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2943                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2944                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2945         }
2946
2947         if (mtu)
2948                 *mtu = rte_le_to_cpu_16(resp->mtu);
2949
2950         switch (resp->port_partition_type) {
2951         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2952         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2953         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2954                 /* FALLTHROUGH */
2955                 bp->port_partition_type = resp->port_partition_type;
2956                 break;
2957         default:
2958                 bp->port_partition_type = 0;
2959                 break;
2960         }
2961
2962         HWRM_UNLOCK();
2963
2964         return rc;
2965 }
2966
2967 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2968                                    struct hwrm_func_qcaps_output *qcaps)
2969 {
2970         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2971         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2972                sizeof(qcaps->mac_address));
2973         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2974         qcaps->max_rx_rings = fcfg->num_rx_rings;
2975         qcaps->max_tx_rings = fcfg->num_tx_rings;
2976         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2977         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2978         qcaps->max_vfs = 0;
2979         qcaps->first_vf_id = 0;
2980         qcaps->max_vnics = fcfg->num_vnics;
2981         qcaps->max_decap_records = 0;
2982         qcaps->max_encap_records = 0;
2983         qcaps->max_tx_wm_flows = 0;
2984         qcaps->max_tx_em_flows = 0;
2985         qcaps->max_rx_wm_flows = 0;
2986         qcaps->max_rx_em_flows = 0;
2987         qcaps->max_flow_id = 0;
2988         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2989         qcaps->max_sp_tx_rings = 0;
2990         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2991 }
2992
2993 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2994 {
2995         struct hwrm_func_cfg_input req = {0};
2996         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2997         uint32_t enables;
2998         int rc;
2999
3000         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3001                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3002                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3003                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3004                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3005                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3006                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3007                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3008                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3009
3010         if (BNXT_HAS_RING_GRPS(bp)) {
3011                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3012                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3013         } else if (BNXT_HAS_NQ(bp)) {
3014                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3015                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3016         }
3017
3018         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3019         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3020         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3021         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3022         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3023         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3024         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3025         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3026         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3027         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3028         req.fid = rte_cpu_to_le_16(0xffff);
3029         req.enables = rte_cpu_to_le_32(enables);
3030
3031         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3032
3033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3034
3035         HWRM_CHECK_RESULT();
3036         HWRM_UNLOCK();
3037
3038         return rc;
3039 }
3040
3041 static void populate_vf_func_cfg_req(struct bnxt *bp,
3042                                      struct hwrm_func_cfg_input *req,
3043                                      int num_vfs)
3044 {
3045         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3046                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3047                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3048                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3049                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3050                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3051                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3052                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3053                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3054                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3055
3056         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3057                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3058                                     BNXT_NUM_VLANS);
3059         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3060         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3061                                                 (num_vfs + 1));
3062         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3063         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3064                                                (num_vfs + 1));
3065         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3066         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3067         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3068         /* TODO: For now, do not support VMDq/RFS on VFs. */
3069         req->num_vnics = rte_cpu_to_le_16(1);
3070         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3071                                                  (num_vfs + 1));
3072 }
3073
3074 static void add_random_mac_if_needed(struct bnxt *bp,
3075                                      struct hwrm_func_cfg_input *cfg_req,
3076                                      int vf)
3077 {
3078         struct rte_ether_addr mac;
3079
3080         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3081                 return;
3082
3083         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3084                 cfg_req->enables |=
3085                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3086                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3087                 bp->pf.vf_info[vf].random_mac = true;
3088         } else {
3089                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3090                         RTE_ETHER_ADDR_LEN);
3091         }
3092 }
3093
3094 static void reserve_resources_from_vf(struct bnxt *bp,
3095                                       struct hwrm_func_cfg_input *cfg_req,
3096                                       int vf)
3097 {
3098         struct hwrm_func_qcaps_input req = {0};
3099         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3100         int rc;
3101
3102         /* Get the actual allocated values now */
3103         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3104         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3106
3107         if (rc) {
3108                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3109                 copy_func_cfg_to_qcaps(cfg_req, resp);
3110         } else if (resp->error_code) {
3111                 rc = rte_le_to_cpu_16(resp->error_code);
3112                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3113                 copy_func_cfg_to_qcaps(cfg_req, resp);
3114         }
3115
3116         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3117         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3118         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3119         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3120         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3121         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3122         /*
3123          * TODO: While not supporting VMDq with VFs, max_vnics is always
3124          * forced to 1 in this case
3125          */
3126         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3127         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3128
3129         HWRM_UNLOCK();
3130 }
3131
3132 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3133 {
3134         struct hwrm_func_qcfg_input req = {0};
3135         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3136         int rc;
3137
3138         /* Check for zero MAC address */
3139         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3140         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3142         HWRM_CHECK_RESULT();
3143         rc = rte_le_to_cpu_16(resp->vlan);
3144
3145         HWRM_UNLOCK();
3146
3147         return rc;
3148 }
3149
3150 static int update_pf_resource_max(struct bnxt *bp)
3151 {
3152         struct hwrm_func_qcfg_input req = {0};
3153         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3154         int rc;
3155
3156         /* And copy the allocated numbers into the pf struct */
3157         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3158         req.fid = rte_cpu_to_le_16(0xffff);
3159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3160         HWRM_CHECK_RESULT();
3161
3162         /* Only TX ring value reflects actual allocation? TODO */
3163         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3164         bp->pf.evb_mode = resp->evb_mode;
3165
3166         HWRM_UNLOCK();
3167
3168         return rc;
3169 }
3170
3171 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3172 {
3173         int rc;
3174
3175         if (!BNXT_PF(bp)) {
3176                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3177                 return -EINVAL;
3178         }
3179
3180         rc = bnxt_hwrm_func_qcaps(bp);
3181         if (rc)
3182                 return rc;
3183
3184         bp->pf.func_cfg_flags &=
3185                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3186                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3187         bp->pf.func_cfg_flags |=
3188                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3189         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3190         rc = __bnxt_hwrm_func_qcaps(bp);
3191         return rc;
3192 }
3193
3194 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3195 {
3196         struct hwrm_func_cfg_input req = {0};
3197         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3198         int i;
3199         size_t sz;
3200         int rc = 0;
3201         size_t req_buf_sz;
3202
3203         if (!BNXT_PF(bp)) {
3204                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3205                 return -EINVAL;
3206         }
3207
3208         rc = bnxt_hwrm_func_qcaps(bp);
3209
3210         if (rc)
3211                 return rc;
3212
3213         bp->pf.active_vfs = num_vfs;
3214
3215         /*
3216          * First, configure the PF to only use one TX ring.  This ensures that
3217          * there are enough rings for all VFs.
3218          *
3219          * If we don't do this, when we call func_alloc() later, we will lock
3220          * extra rings to the PF that won't be available during func_cfg() of
3221          * the VFs.
3222          *
3223          * This has been fixed with firmware versions above 20.6.54
3224          */
3225         bp->pf.func_cfg_flags &=
3226                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3227                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3228         bp->pf.func_cfg_flags |=
3229                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3230         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3231         if (rc)
3232                 return rc;
3233
3234         /*
3235          * Now, create and register a buffer to hold forwarded VF requests
3236          */
3237         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3238         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3239                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3240         if (bp->pf.vf_req_buf == NULL) {
3241                 rc = -ENOMEM;
3242                 goto error_free;
3243         }
3244         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3245                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3246         for (i = 0; i < num_vfs; i++)
3247                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3248                                         (i * HWRM_MAX_REQ_LEN);
3249
3250         rc = bnxt_hwrm_func_buf_rgtr(bp);
3251         if (rc)
3252                 goto error_free;
3253
3254         populate_vf_func_cfg_req(bp, &req, num_vfs);
3255
3256         bp->pf.active_vfs = 0;
3257         for (i = 0; i < num_vfs; i++) {
3258                 add_random_mac_if_needed(bp, &req, i);
3259
3260                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3261                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3262                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3263                 rc = bnxt_hwrm_send_message(bp,
3264                                             &req,
3265                                             sizeof(req),
3266                                             BNXT_USE_CHIMP_MB);
3267
3268                 /* Clear enable flag for next pass */
3269                 req.enables &= ~rte_cpu_to_le_32(
3270                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3271
3272                 if (rc || resp->error_code) {
3273                         PMD_DRV_LOG(ERR,
3274                                 "Failed to initizlie VF %d\n", i);
3275                         PMD_DRV_LOG(ERR,
3276                                 "Not all VFs available. (%d, %d)\n",
3277                                 rc, resp->error_code);
3278                         HWRM_UNLOCK();
3279                         break;
3280                 }
3281
3282                 HWRM_UNLOCK();
3283
3284                 reserve_resources_from_vf(bp, &req, i);
3285                 bp->pf.active_vfs++;
3286                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3287         }
3288
3289         /*
3290          * Now configure the PF to use "the rest" of the resources
3291          * We're using STD_TX_RING_MODE here though which will limit the TX
3292          * rings.  This will allow QoS to function properly.  Not setting this
3293          * will cause PF rings to break bandwidth settings.
3294          */
3295         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3296         if (rc)
3297                 goto error_free;
3298
3299         rc = update_pf_resource_max(bp);
3300         if (rc)
3301                 goto error_free;
3302
3303         return rc;
3304
3305 error_free:
3306         bnxt_hwrm_func_buf_unrgtr(bp);
3307         return rc;
3308 }
3309
3310 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3311 {
3312         struct hwrm_func_cfg_input req = {0};
3313         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3314         int rc;
3315
3316         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3317
3318         req.fid = rte_cpu_to_le_16(0xffff);
3319         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3320         req.evb_mode = bp->pf.evb_mode;
3321
3322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3323         HWRM_CHECK_RESULT();
3324         HWRM_UNLOCK();
3325
3326         return rc;
3327 }
3328
3329 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3330                                 uint8_t tunnel_type)
3331 {
3332         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3333         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3334         int rc = 0;
3335
3336         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3337         req.tunnel_type = tunnel_type;
3338         req.tunnel_dst_port_val = port;
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340         HWRM_CHECK_RESULT();
3341
3342         switch (tunnel_type) {
3343         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3344                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3345                 bp->vxlan_port = port;
3346                 break;
3347         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3348                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3349                 bp->geneve_port = port;
3350                 break;
3351         default:
3352                 break;
3353         }
3354
3355         HWRM_UNLOCK();
3356
3357         return rc;
3358 }
3359
3360 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3361                                 uint8_t tunnel_type)
3362 {
3363         struct hwrm_tunnel_dst_port_free_input req = {0};
3364         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3365         int rc = 0;
3366
3367         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3368
3369         req.tunnel_type = tunnel_type;
3370         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372
3373         HWRM_CHECK_RESULT();
3374         HWRM_UNLOCK();
3375
3376         return rc;
3377 }
3378
3379 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3380                                         uint32_t flags)
3381 {
3382         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3383         struct hwrm_func_cfg_input req = {0};
3384         int rc;
3385
3386         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3387
3388         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3389         req.flags = rte_cpu_to_le_32(flags);
3390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3391
3392         HWRM_CHECK_RESULT();
3393         HWRM_UNLOCK();
3394
3395         return rc;
3396 }
3397
3398 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3399 {
3400         uint32_t *flag = flagp;
3401
3402         vnic->flags = *flag;
3403 }
3404
3405 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3406 {
3407         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3408 }
3409
3410 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3411 {
3412         int rc = 0;
3413         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3414         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3415
3416         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3417
3418         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3419         req.req_buf_page_size = rte_cpu_to_le_16(
3420                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3421         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3422         req.req_buf_page_addr0 =
3423                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3424         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3425                 PMD_DRV_LOG(ERR,
3426                         "unable to map buffer address to physical memory\n");
3427                 return -ENOMEM;
3428         }
3429
3430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3431
3432         HWRM_CHECK_RESULT();
3433         HWRM_UNLOCK();
3434
3435         return rc;
3436 }
3437
3438 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3439 {
3440         int rc = 0;
3441         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3442         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3443
3444         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3445                 return 0;
3446
3447         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3448
3449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3450
3451         HWRM_CHECK_RESULT();
3452         HWRM_UNLOCK();
3453
3454         return rc;
3455 }
3456
3457 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3458 {
3459         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3460         struct hwrm_func_cfg_input req = {0};
3461         int rc;
3462
3463         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3464
3465         req.fid = rte_cpu_to_le_16(0xffff);
3466         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3467         req.enables = rte_cpu_to_le_32(
3468                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3469         req.async_event_cr = rte_cpu_to_le_16(
3470                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472
3473         HWRM_CHECK_RESULT();
3474         HWRM_UNLOCK();
3475
3476         return rc;
3477 }
3478
3479 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3480 {
3481         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3482         struct hwrm_func_vf_cfg_input req = {0};
3483         int rc;
3484
3485         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3486
3487         req.enables = rte_cpu_to_le_32(
3488                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3489         req.async_event_cr = rte_cpu_to_le_16(
3490                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492
3493         HWRM_CHECK_RESULT();
3494         HWRM_UNLOCK();
3495
3496         return rc;
3497 }
3498
3499 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3500 {
3501         struct hwrm_func_cfg_input req = {0};
3502         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3503         uint16_t dflt_vlan, fid;
3504         uint32_t func_cfg_flags;
3505         int rc = 0;
3506
3507         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3508
3509         if (is_vf) {
3510                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3511                 fid = bp->pf.vf_info[vf].fid;
3512                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3513         } else {
3514                 fid = rte_cpu_to_le_16(0xffff);
3515                 func_cfg_flags = bp->pf.func_cfg_flags;
3516                 dflt_vlan = bp->vlan;
3517         }
3518
3519         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3520         req.fid = rte_cpu_to_le_16(fid);
3521         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3522         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3523
3524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3525
3526         HWRM_CHECK_RESULT();
3527         HWRM_UNLOCK();
3528
3529         return rc;
3530 }
3531
3532 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3533                         uint16_t max_bw, uint16_t enables)
3534 {
3535         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3536         struct hwrm_func_cfg_input req = {0};
3537         int rc;
3538
3539         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3540
3541         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3542         req.enables |= rte_cpu_to_le_32(enables);
3543         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3544         req.max_bw = rte_cpu_to_le_32(max_bw);
3545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3546
3547         HWRM_CHECK_RESULT();
3548         HWRM_UNLOCK();
3549
3550         return rc;
3551 }
3552
3553 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3554 {
3555         struct hwrm_func_cfg_input req = {0};
3556         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3557         int rc = 0;
3558
3559         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3560
3561         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3562         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3563         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3564         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3565
3566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3567
3568         HWRM_CHECK_RESULT();
3569         HWRM_UNLOCK();
3570
3571         return rc;
3572 }
3573
3574 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3575 {
3576         int rc;
3577
3578         if (BNXT_PF(bp))
3579                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3580         else
3581                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3582
3583         return rc;
3584 }
3585
3586 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3587                               void *encaped, size_t ec_size)
3588 {
3589         int rc = 0;
3590         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3591         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3592
3593         if (ec_size > sizeof(req.encap_request))
3594                 return -1;
3595
3596         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3597
3598         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3599         memcpy(req.encap_request, encaped, ec_size);
3600
3601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602
3603         HWRM_CHECK_RESULT();
3604         HWRM_UNLOCK();
3605
3606         return rc;
3607 }
3608
3609 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3610                                        struct rte_ether_addr *mac)
3611 {
3612         struct hwrm_func_qcfg_input req = {0};
3613         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3614         int rc;
3615
3616         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3617
3618         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3620
3621         HWRM_CHECK_RESULT();
3622
3623         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3624
3625         HWRM_UNLOCK();
3626
3627         return rc;
3628 }
3629
3630 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3631                             void *encaped, size_t ec_size)
3632 {
3633         int rc = 0;
3634         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3635         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3636
3637         if (ec_size > sizeof(req.encap_request))
3638                 return -1;
3639
3640         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3641
3642         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3643         memcpy(req.encap_request, encaped, ec_size);
3644
3645         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3646
3647         HWRM_CHECK_RESULT();
3648         HWRM_UNLOCK();
3649
3650         return rc;
3651 }
3652
3653 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3654                          struct rte_eth_stats *stats, uint8_t rx)
3655 {
3656         int rc = 0;
3657         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3658         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3659
3660         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3661
3662         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3663
3664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3665
3666         HWRM_CHECK_RESULT();
3667
3668         if (rx) {
3669                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3670                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3671                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3672                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3673                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3674                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3675                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3676                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3677         } else {
3678                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3679                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3680                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3681                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3682                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3683                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3684         }
3685
3686         HWRM_UNLOCK();
3687
3688         return rc;
3689 }
3690
3691 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3692 {
3693         struct hwrm_port_qstats_input req = {0};
3694         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3695         struct bnxt_pf_info *pf = &bp->pf;
3696         int rc;
3697
3698         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3699
3700         req.port_id = rte_cpu_to_le_16(pf->port_id);
3701         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3702         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3704
3705         HWRM_CHECK_RESULT();
3706         HWRM_UNLOCK();
3707
3708         return rc;
3709 }
3710
3711 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3712 {
3713         struct hwrm_port_clr_stats_input req = {0};
3714         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3715         struct bnxt_pf_info *pf = &bp->pf;
3716         int rc;
3717
3718         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3719         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3720             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3721                 return 0;
3722
3723         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3724
3725         req.port_id = rte_cpu_to_le_16(pf->port_id);
3726         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3727
3728         HWRM_CHECK_RESULT();
3729         HWRM_UNLOCK();
3730
3731         return rc;
3732 }
3733
3734 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3735 {
3736         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3737         struct hwrm_port_led_qcaps_input req = {0};
3738         int rc;
3739
3740         if (BNXT_VF(bp))
3741                 return 0;
3742
3743         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3744         req.port_id = bp->pf.port_id;
3745         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3746
3747         HWRM_CHECK_RESULT();
3748
3749         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3750                 unsigned int i;
3751
3752                 bp->num_leds = resp->num_leds;
3753                 memcpy(bp->leds, &resp->led0_id,
3754                         sizeof(bp->leds[0]) * bp->num_leds);
3755                 for (i = 0; i < bp->num_leds; i++) {
3756                         struct bnxt_led_info *led = &bp->leds[i];
3757
3758                         uint16_t caps = led->led_state_caps;
3759
3760                         if (!led->led_group_id ||
3761                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3762                                 bp->num_leds = 0;
3763                                 break;
3764                         }
3765                 }
3766         }
3767
3768         HWRM_UNLOCK();
3769
3770         return rc;
3771 }
3772
3773 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3774 {
3775         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3776         struct hwrm_port_led_cfg_input req = {0};
3777         struct bnxt_led_cfg *led_cfg;
3778         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3779         uint16_t duration = 0;
3780         int rc, i;
3781
3782         if (!bp->num_leds || BNXT_VF(bp))
3783                 return -EOPNOTSUPP;
3784
3785         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3786
3787         if (led_on) {
3788                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3789                 duration = rte_cpu_to_le_16(500);
3790         }
3791         req.port_id = bp->pf.port_id;
3792         req.num_leds = bp->num_leds;
3793         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3794         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3795                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3796                 led_cfg->led_id = bp->leds[i].led_id;
3797                 led_cfg->led_state = led_state;
3798                 led_cfg->led_blink_on = duration;
3799                 led_cfg->led_blink_off = duration;
3800                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3801         }
3802
3803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3804
3805         HWRM_CHECK_RESULT();
3806         HWRM_UNLOCK();
3807
3808         return rc;
3809 }
3810
3811 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3812                                uint32_t *length)
3813 {
3814         int rc;
3815         struct hwrm_nvm_get_dir_info_input req = {0};
3816         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3817
3818         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3819
3820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3821
3822         HWRM_CHECK_RESULT();
3823
3824         *entries = rte_le_to_cpu_32(resp->entries);
3825         *length = rte_le_to_cpu_32(resp->entry_length);
3826
3827         HWRM_UNLOCK();
3828         return rc;
3829 }
3830
3831 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3832 {
3833         int rc;
3834         uint32_t dir_entries;
3835         uint32_t entry_length;
3836         uint8_t *buf;
3837         size_t buflen;
3838         rte_iova_t dma_handle;
3839         struct hwrm_nvm_get_dir_entries_input req = {0};
3840         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3841
3842         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3843         if (rc != 0)
3844                 return rc;
3845
3846         *data++ = dir_entries;
3847         *data++ = entry_length;
3848         len -= 2;
3849         memset(data, 0xff, len);
3850
3851         buflen = dir_entries * entry_length;
3852         buf = rte_malloc("nvm_dir", buflen, 0);
3853         if (buf == NULL)
3854                 return -ENOMEM;
3855         dma_handle = rte_malloc_virt2iova(buf);
3856         if (dma_handle == RTE_BAD_IOVA) {
3857                 PMD_DRV_LOG(ERR,
3858                         "unable to map response address to physical memory\n");
3859                 return -ENOMEM;
3860         }
3861         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3862         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3864
3865         if (rc == 0)
3866                 memcpy(data, buf, len > buflen ? buflen : len);
3867
3868         rte_free(buf);
3869         HWRM_CHECK_RESULT();
3870         HWRM_UNLOCK();
3871
3872         return rc;
3873 }
3874
3875 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3876                              uint32_t offset, uint32_t length,
3877                              uint8_t *data)
3878 {
3879         int rc;
3880         uint8_t *buf;
3881         rte_iova_t dma_handle;
3882         struct hwrm_nvm_read_input req = {0};
3883         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3884
3885         buf = rte_malloc("nvm_item", length, 0);
3886         if (!buf)
3887                 return -ENOMEM;
3888
3889         dma_handle = rte_malloc_virt2iova(buf);
3890         if (dma_handle == RTE_BAD_IOVA) {
3891                 PMD_DRV_LOG(ERR,
3892                         "unable to map response address to physical memory\n");
3893                 return -ENOMEM;
3894         }
3895         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3896         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3897         req.dir_idx = rte_cpu_to_le_16(index);
3898         req.offset = rte_cpu_to_le_32(offset);
3899         req.len = rte_cpu_to_le_32(length);
3900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3901         if (rc == 0)
3902                 memcpy(data, buf, length);
3903
3904         rte_free(buf);
3905         HWRM_CHECK_RESULT();
3906         HWRM_UNLOCK();
3907
3908         return rc;
3909 }
3910
3911 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3912 {
3913         int rc;
3914         struct hwrm_nvm_erase_dir_entry_input req = {0};
3915         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3916
3917         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3918         req.dir_idx = rte_cpu_to_le_16(index);
3919         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3920         HWRM_CHECK_RESULT();
3921         HWRM_UNLOCK();
3922
3923         return rc;
3924 }
3925
3926
3927 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3928                           uint16_t dir_ordinal, uint16_t dir_ext,
3929                           uint16_t dir_attr, const uint8_t *data,
3930                           size_t data_len)
3931 {
3932         int rc;
3933         struct hwrm_nvm_write_input req = {0};
3934         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3935         rte_iova_t dma_handle;
3936         uint8_t *buf;
3937
3938         buf = rte_malloc("nvm_write", data_len, 0);
3939         if (!buf)
3940                 return -ENOMEM;
3941
3942         dma_handle = rte_malloc_virt2iova(buf);
3943         if (dma_handle == RTE_BAD_IOVA) {
3944                 PMD_DRV_LOG(ERR,
3945                         "unable to map response address to physical memory\n");
3946                 return -ENOMEM;
3947         }
3948         memcpy(buf, data, data_len);
3949
3950         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3951
3952         req.dir_type = rte_cpu_to_le_16(dir_type);
3953         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3954         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3955         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3956         req.dir_data_length = rte_cpu_to_le_32(data_len);
3957         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3958
3959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3960
3961         rte_free(buf);
3962         HWRM_CHECK_RESULT();
3963         HWRM_UNLOCK();
3964
3965         return rc;
3966 }
3967
3968 static void
3969 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3970 {
3971         uint32_t *count = cbdata;
3972
3973         *count = *count + 1;
3974 }
3975
3976 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3977                                      struct bnxt_vnic_info *vnic __rte_unused)
3978 {
3979         return 0;
3980 }
3981
3982 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3983 {
3984         uint32_t count = 0;
3985
3986         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3987             &count, bnxt_vnic_count_hwrm_stub);
3988
3989         return count;
3990 }
3991
3992 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3993                                         uint16_t *vnic_ids)
3994 {
3995         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3996         struct hwrm_func_vf_vnic_ids_query_output *resp =
3997                                                 bp->hwrm_cmd_resp_addr;
3998         int rc;
3999
4000         /* First query all VNIC ids */
4001         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4002
4003         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4004         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4005         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4006
4007         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4008                 HWRM_UNLOCK();
4009                 PMD_DRV_LOG(ERR,
4010                 "unable to map VNIC ID table address to physical memory\n");
4011                 return -ENOMEM;
4012         }
4013         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4014         HWRM_CHECK_RESULT();
4015         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4016
4017         HWRM_UNLOCK();
4018
4019         return rc;
4020 }
4021
4022 /*
4023  * This function queries the VNIC IDs  for a specified VF. It then calls
4024  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4025  * Then it calls the hwrm_cb function to program this new vnic configuration.
4026  */
4027 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4028         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4029         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4030 {
4031         struct bnxt_vnic_info vnic;
4032         int rc = 0;
4033         int i, num_vnic_ids;
4034         uint16_t *vnic_ids;
4035         size_t vnic_id_sz;
4036         size_t sz;
4037
4038         /* First query all VNIC ids */
4039         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4040         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4041                         RTE_CACHE_LINE_SIZE);
4042         if (vnic_ids == NULL)
4043                 return -ENOMEM;
4044
4045         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4046                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4047
4048         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4049
4050         if (num_vnic_ids < 0)
4051                 return num_vnic_ids;
4052
4053         /* Retrieve VNIC, update bd_stall then update */
4054
4055         for (i = 0; i < num_vnic_ids; i++) {
4056                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4057                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4058                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4059                 if (rc)
4060                         break;
4061                 if (vnic.mru <= 4)      /* Indicates unallocated */
4062                         continue;
4063
4064                 vnic_cb(&vnic, cbdata);
4065
4066                 rc = hwrm_cb(bp, &vnic);
4067                 if (rc)
4068                         break;
4069         }
4070
4071         rte_free(vnic_ids);
4072
4073         return rc;
4074 }
4075
4076 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4077                                               bool on)
4078 {
4079         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4080         struct hwrm_func_cfg_input req = {0};
4081         int rc;
4082
4083         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4084
4085         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4086         req.enables |= rte_cpu_to_le_32(
4087                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4088         req.vlan_antispoof_mode = on ?
4089                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4090                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4092
4093         HWRM_CHECK_RESULT();
4094         HWRM_UNLOCK();
4095
4096         return rc;
4097 }
4098
4099 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4100 {
4101         struct bnxt_vnic_info vnic;
4102         uint16_t *vnic_ids;
4103         size_t vnic_id_sz;
4104         int num_vnic_ids, i;
4105         size_t sz;
4106         int rc;
4107
4108         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4109         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4110                         RTE_CACHE_LINE_SIZE);
4111         if (vnic_ids == NULL)
4112                 return -ENOMEM;
4113
4114         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4115                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4116
4117         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4118         if (rc <= 0)
4119                 goto exit;
4120         num_vnic_ids = rc;
4121
4122         /*
4123          * Loop through to find the default VNIC ID.
4124          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4125          * by sending the hwrm_func_qcfg command to the firmware.
4126          */
4127         for (i = 0; i < num_vnic_ids; i++) {
4128                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4129                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4130                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4131                                         bp->pf.first_vf_id + vf);
4132                 if (rc)
4133                         goto exit;
4134                 if (vnic.func_default) {
4135                         rte_free(vnic_ids);
4136                         return vnic.fw_vnic_id;
4137                 }
4138         }
4139         /* Could not find a default VNIC. */
4140         PMD_DRV_LOG(ERR, "No default VNIC\n");
4141 exit:
4142         rte_free(vnic_ids);
4143         return rc;
4144 }
4145
4146 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4147                          uint16_t dst_id,
4148                          struct bnxt_filter_info *filter)
4149 {
4150         int rc = 0;
4151         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4152         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4153         uint32_t enables = 0;
4154
4155         if (filter->fw_em_filter_id != UINT64_MAX)
4156                 bnxt_hwrm_clear_em_filter(bp, filter);
4157
4158         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4159
4160         req.flags = rte_cpu_to_le_32(filter->flags);
4161
4162         enables = filter->enables |
4163               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4164         req.dst_id = rte_cpu_to_le_16(dst_id);
4165
4166         if (filter->ip_addr_type) {
4167                 req.ip_addr_type = filter->ip_addr_type;
4168                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4169         }
4170         if (enables &
4171             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4172                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4173         if (enables &
4174             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4175                 memcpy(req.src_macaddr, filter->src_macaddr,
4176                        RTE_ETHER_ADDR_LEN);
4177         if (enables &
4178             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4179                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4180                        RTE_ETHER_ADDR_LEN);
4181         if (enables &
4182             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4183                 req.ovlan_vid = filter->l2_ovlan;
4184         if (enables &
4185             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4186                 req.ivlan_vid = filter->l2_ivlan;
4187         if (enables &
4188             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4189                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4190         if (enables &
4191             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4192                 req.ip_protocol = filter->ip_protocol;
4193         if (enables &
4194             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4195                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4196         if (enables &
4197             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4198                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4199         if (enables &
4200             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4201                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4202         if (enables &
4203             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4204                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4205         if (enables &
4206             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4207                 req.mirror_vnic_id = filter->mirror_vnic_id;
4208
4209         req.enables = rte_cpu_to_le_32(enables);
4210
4211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4212
4213         HWRM_CHECK_RESULT();
4214
4215         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4216         HWRM_UNLOCK();
4217
4218         return rc;
4219 }
4220
4221 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4222 {
4223         int rc = 0;
4224         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4225         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4226
4227         if (filter->fw_em_filter_id == UINT64_MAX)
4228                 return 0;
4229
4230         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4231
4232         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4233
4234         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4235
4236         HWRM_CHECK_RESULT();
4237         HWRM_UNLOCK();
4238
4239         filter->fw_em_filter_id = UINT64_MAX;
4240         filter->fw_l2_filter_id = UINT64_MAX;
4241
4242         return 0;
4243 }
4244
4245 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4246                          uint16_t dst_id,
4247                          struct bnxt_filter_info *filter)
4248 {
4249         int rc = 0;
4250         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4251         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4252                                                 bp->hwrm_cmd_resp_addr;
4253         uint32_t enables = 0;
4254
4255         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4256                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4257
4258         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4259
4260         req.flags = rte_cpu_to_le_32(filter->flags);
4261
4262         enables = filter->enables |
4263               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4264         req.dst_id = rte_cpu_to_le_16(dst_id);
4265
4266         if (filter->ip_addr_type) {
4267                 req.ip_addr_type = filter->ip_addr_type;
4268                 enables |=
4269                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4270         }
4271         if (enables &
4272             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4273                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4274         if (enables &
4275             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4276                 memcpy(req.src_macaddr, filter->src_macaddr,
4277                        RTE_ETHER_ADDR_LEN);
4278         if (enables &
4279             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4280                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4281         if (enables &
4282             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4283                 req.ip_protocol = filter->ip_protocol;
4284         if (enables &
4285             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4286                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4287         if (enables &
4288             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4289                 req.src_ipaddr_mask[0] =
4290                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4291         if (enables &
4292             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4293                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4294         if (enables &
4295             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4296                 req.dst_ipaddr_mask[0] =
4297                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4298         if (enables &
4299             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4300                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4301         if (enables &
4302             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4303                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4304         if (enables &
4305             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4306                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4307         if (enables &
4308             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4309                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4310         if (enables &
4311             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4312                 req.mirror_vnic_id = filter->mirror_vnic_id;
4313
4314         req.enables = rte_cpu_to_le_32(enables);
4315
4316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4317
4318         HWRM_CHECK_RESULT();
4319
4320         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4321         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4322         HWRM_UNLOCK();
4323
4324         return rc;
4325 }
4326
4327 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4328                                 struct bnxt_filter_info *filter)
4329 {
4330         int rc = 0;
4331         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4332         struct hwrm_cfa_ntuple_filter_free_output *resp =
4333                                                 bp->hwrm_cmd_resp_addr;
4334
4335         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4336                 return 0;
4337
4338         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4339
4340         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4341
4342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4343
4344         HWRM_CHECK_RESULT();
4345         HWRM_UNLOCK();
4346
4347         filter->fw_ntuple_filter_id = UINT64_MAX;
4348
4349         return 0;
4350 }
4351
4352 static int
4353 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4354 {
4355         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4356         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4357         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4358         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4359         uint16_t *ring_tbl = vnic->rss_table;
4360         int nr_ctxs = vnic->num_lb_ctxts;
4361         int max_rings = bp->rx_nr_rings;
4362         int i, j, k, cnt;
4363         int rc = 0;
4364
4365         for (i = 0, k = 0; i < nr_ctxs; i++) {
4366                 struct bnxt_rx_ring_info *rxr;
4367                 struct bnxt_cp_ring_info *cpr;
4368
4369                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4370
4371                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4372                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4373                 req.hash_mode_flags = vnic->hash_mode;
4374
4375                 req.ring_grp_tbl_addr =
4376                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4377                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4378                                      2 * sizeof(*ring_tbl));
4379                 req.hash_key_tbl_addr =
4380                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4381
4382                 req.ring_table_pair_index = i;
4383                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4384
4385                 for (j = 0; j < 64; j++) {
4386                         uint16_t ring_id;
4387
4388                         /* Find next active ring. */
4389                         for (cnt = 0; cnt < max_rings; cnt++) {
4390                                 if (rx_queue_state[k] !=
4391                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4392                                         break;
4393                                 if (++k == max_rings)
4394                                         k = 0;
4395                         }
4396
4397                         /* Return if no rings are active. */
4398                         if (cnt == max_rings) {
4399                                 HWRM_UNLOCK();
4400                                 return 0;
4401                         }
4402
4403                         /* Add rx/cp ring pair to RSS table. */
4404                         rxr = rxqs[k]->rx_ring;
4405                         cpr = rxqs[k]->cp_ring;
4406
4407                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4408                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4409                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4410                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4411
4412                         if (++k == max_rings)
4413                                 k = 0;
4414                 }
4415                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4416                                             BNXT_USE_CHIMP_MB);
4417
4418                 HWRM_CHECK_RESULT();
4419                 HWRM_UNLOCK();
4420         }
4421
4422         return rc;
4423 }
4424
4425 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4426 {
4427         unsigned int rss_idx, fw_idx, i;
4428
4429         if (!(vnic->rss_table && vnic->hash_type))
4430                 return 0;
4431
4432         if (BNXT_CHIP_THOR(bp))
4433                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4434
4435         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4436                 return 0;
4437
4438         if (vnic->rss_table && vnic->hash_type) {
4439                 /*
4440                  * Fill the RSS hash & redirection table with
4441                  * ring group ids for all VNICs
4442                  */
4443                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4444                         rss_idx++, fw_idx++) {
4445                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4446                                 fw_idx %= bp->rx_cp_nr_rings;
4447                                 if (vnic->fw_grp_ids[fw_idx] !=
4448                                     INVALID_HW_RING_ID)
4449                                         break;
4450                                 fw_idx++;
4451                         }
4452                         if (i == bp->rx_cp_nr_rings)
4453                                 return 0;
4454                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4455                 }
4456                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4457         }
4458
4459         return 0;
4460 }
4461
4462 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4463         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4464 {
4465         uint16_t flags;
4466
4467         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4468
4469         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4470         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4471
4472         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4473         req->num_cmpl_dma_aggr_during_int =
4474                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4475
4476         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4477
4478         /* min timer set to 1/2 of interrupt timer */
4479         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4480
4481         /* buf timer set to 1/4 of interrupt timer */
4482         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4483
4484         req->cmpl_aggr_dma_tmr_during_int =
4485                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4486
4487         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4488                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4489         req->flags = rte_cpu_to_le_16(flags);
4490 }
4491
4492 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4493                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4494 {
4495         struct hwrm_ring_aggint_qcaps_input req = {0};
4496         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4497         uint32_t enables;
4498         uint16_t flags;
4499         int rc;
4500
4501         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4503         HWRM_CHECK_RESULT();
4504
4505         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4506         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4507
4508         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4509                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4510         agg_req->flags = rte_cpu_to_le_16(flags);
4511         enables =
4512          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4513          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4514         agg_req->enables = rte_cpu_to_le_32(enables);
4515
4516         HWRM_UNLOCK();
4517         return rc;
4518 }
4519
4520 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4521                         struct bnxt_coal *coal, uint16_t ring_id)
4522 {
4523         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4524         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4525                                                 bp->hwrm_cmd_resp_addr;
4526         int rc;
4527
4528         /* Set ring coalesce parameters only for 100G NICs */
4529         if (BNXT_CHIP_THOR(bp)) {
4530                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4531                         return -1;
4532         } else if (bnxt_stratus_device(bp)) {
4533                 bnxt_hwrm_set_coal_params(coal, &req);
4534         } else {
4535                 return 0;
4536         }
4537
4538         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4539         req.ring_id = rte_cpu_to_le_16(ring_id);
4540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4541         HWRM_CHECK_RESULT();
4542         HWRM_UNLOCK();
4543         return 0;
4544 }
4545
4546 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4547 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4548 {
4549         struct hwrm_func_backing_store_qcaps_input req = {0};
4550         struct hwrm_func_backing_store_qcaps_output *resp =
4551                 bp->hwrm_cmd_resp_addr;
4552         struct bnxt_ctx_pg_info *ctx_pg;
4553         struct bnxt_ctx_mem_info *ctx;
4554         int total_alloc_len;
4555         int rc, i;
4556
4557         if (!BNXT_CHIP_THOR(bp) ||
4558             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4559             BNXT_VF(bp) ||
4560             bp->ctx)
4561                 return 0;
4562
4563         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4564         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4565         HWRM_CHECK_RESULT_SILENT();
4566
4567         total_alloc_len = sizeof(*ctx);
4568         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4569                           RTE_CACHE_LINE_SIZE);
4570         if (!ctx) {
4571                 rc = -ENOMEM;
4572                 goto ctx_err;
4573         }
4574
4575         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4576                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4577                             RTE_CACHE_LINE_SIZE);
4578         if (!ctx_pg) {
4579                 rc = -ENOMEM;
4580                 goto ctx_err;
4581         }
4582         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4583                 ctx->tqm_mem[i] = ctx_pg;
4584
4585         bp->ctx = ctx;
4586         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4587         ctx->qp_min_qp1_entries =
4588                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4589         ctx->qp_max_l2_entries =
4590                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4591         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4592         ctx->srq_max_l2_entries =
4593                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4594         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4595         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4596         ctx->cq_max_l2_entries =
4597                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4598         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4599         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4600         ctx->vnic_max_vnic_entries =
4601                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4602         ctx->vnic_max_ring_table_entries =
4603                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4604         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4605         ctx->stat_max_entries =
4606                 rte_le_to_cpu_32(resp->stat_max_entries);
4607         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4608         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4609         ctx->tqm_min_entries_per_ring =
4610                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4611         ctx->tqm_max_entries_per_ring =
4612                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4613         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4614         if (!ctx->tqm_entries_multiple)
4615                 ctx->tqm_entries_multiple = 1;
4616         ctx->mrav_max_entries =
4617                 rte_le_to_cpu_32(resp->mrav_max_entries);
4618         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4619         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4620         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4621 ctx_err:
4622         HWRM_UNLOCK();
4623         return rc;
4624 }
4625
4626 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4627 {
4628         struct hwrm_func_backing_store_cfg_input req = {0};
4629         struct hwrm_func_backing_store_cfg_output *resp =
4630                 bp->hwrm_cmd_resp_addr;
4631         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4632         struct bnxt_ctx_pg_info *ctx_pg;
4633         uint32_t *num_entries;
4634         uint64_t *pg_dir;
4635         uint8_t *pg_attr;
4636         uint32_t ena;
4637         int i, rc;
4638
4639         if (!ctx)
4640                 return 0;
4641
4642         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4643         req.enables = rte_cpu_to_le_32(enables);
4644
4645         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4646                 ctx_pg = &ctx->qp_mem;
4647                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4648                 req.qp_num_qp1_entries =
4649                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4650                 req.qp_num_l2_entries =
4651                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4652                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4653                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4654                                       &req.qpc_pg_size_qpc_lvl,
4655                                       &req.qpc_page_dir);
4656         }
4657
4658         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4659                 ctx_pg = &ctx->srq_mem;
4660                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4661                 req.srq_num_l2_entries =
4662                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4663                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4664                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4665                                       &req.srq_pg_size_srq_lvl,
4666                                       &req.srq_page_dir);
4667         }
4668
4669         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4670                 ctx_pg = &ctx->cq_mem;
4671                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4672                 req.cq_num_l2_entries =
4673                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4674                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4675                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4676                                       &req.cq_pg_size_cq_lvl,
4677                                       &req.cq_page_dir);
4678         }
4679
4680         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4681                 ctx_pg = &ctx->vnic_mem;
4682                 req.vnic_num_vnic_entries =
4683                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4684                 req.vnic_num_ring_table_entries =
4685                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4686                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4687                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4688                                       &req.vnic_pg_size_vnic_lvl,
4689                                       &req.vnic_page_dir);
4690         }
4691
4692         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4693                 ctx_pg = &ctx->stat_mem;
4694                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4695                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4696                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4697                                       &req.stat_pg_size_stat_lvl,
4698                                       &req.stat_page_dir);
4699         }
4700
4701         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4702         num_entries = &req.tqm_sp_num_entries;
4703         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4704         pg_dir = &req.tqm_sp_page_dir;
4705         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4706         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4707                 if (!(enables & ena))
4708                         continue;
4709
4710                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4711
4712                 ctx_pg = ctx->tqm_mem[i];
4713                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4714                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4715         }
4716
4717         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4718         HWRM_CHECK_RESULT();
4719         HWRM_UNLOCK();
4720
4721         return rc;
4722 }
4723
4724 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4725 {
4726         struct hwrm_port_qstats_ext_input req = {0};
4727         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4728         struct bnxt_pf_info *pf = &bp->pf;
4729         int rc;
4730
4731         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4732               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4733                 return 0;
4734
4735         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4736
4737         req.port_id = rte_cpu_to_le_16(pf->port_id);
4738         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4739                 req.tx_stat_host_addr =
4740                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4741                 req.tx_stat_size =
4742                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4743         }
4744         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4745                 req.rx_stat_host_addr =
4746                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4747                 req.rx_stat_size =
4748                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4749         }
4750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4751
4752         if (rc) {
4753                 bp->fw_rx_port_stats_ext_size = 0;
4754                 bp->fw_tx_port_stats_ext_size = 0;
4755         } else {
4756                 bp->fw_rx_port_stats_ext_size =
4757                         rte_le_to_cpu_16(resp->rx_stat_size);
4758                 bp->fw_tx_port_stats_ext_size =
4759                         rte_le_to_cpu_16(resp->tx_stat_size);
4760         }
4761
4762         HWRM_CHECK_RESULT();
4763         HWRM_UNLOCK();
4764
4765         return rc;
4766 }
4767
4768 int
4769 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4770 {
4771         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4772         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4773                 bp->hwrm_cmd_resp_addr;
4774         int rc = 0;
4775
4776         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4777         req.tunnel_type = type;
4778         req.dest_fid = bp->fw_fid;
4779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4780         HWRM_CHECK_RESULT();
4781
4782         HWRM_UNLOCK();
4783
4784         return rc;
4785 }
4786
4787 int
4788 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4789 {
4790         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4791         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4792                 bp->hwrm_cmd_resp_addr;
4793         int rc = 0;
4794
4795         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4796         req.tunnel_type = type;
4797         req.dest_fid = bp->fw_fid;
4798         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4799         HWRM_CHECK_RESULT();
4800
4801         HWRM_UNLOCK();
4802
4803         return rc;
4804 }
4805
4806 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4807 {
4808         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4809         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4810                 bp->hwrm_cmd_resp_addr;
4811         int rc = 0;
4812
4813         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4814         req.src_fid = bp->fw_fid;
4815         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4816         HWRM_CHECK_RESULT();
4817
4818         if (type)
4819                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4820
4821         HWRM_UNLOCK();
4822
4823         return rc;
4824 }
4825
4826 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4827                                    uint16_t *dst_fid)
4828 {
4829         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4830         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4831                 bp->hwrm_cmd_resp_addr;
4832         int rc = 0;
4833
4834         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4835         req.src_fid = bp->fw_fid;
4836         req.tunnel_type = tun_type;
4837         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4838         HWRM_CHECK_RESULT();
4839
4840         if (dst_fid)
4841                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4842
4843         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4844
4845         HWRM_UNLOCK();
4846
4847         return rc;
4848 }
4849
4850 int bnxt_hwrm_set_mac(struct bnxt *bp)
4851 {
4852         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4853         struct hwrm_func_vf_cfg_input req = {0};
4854         int rc = 0;
4855
4856         if (!BNXT_VF(bp))
4857                 return 0;
4858
4859         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4860
4861         req.enables =
4862                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4863         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4864
4865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4866
4867         HWRM_CHECK_RESULT();
4868
4869         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4870         HWRM_UNLOCK();
4871
4872         return rc;
4873 }
4874
4875 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4876 {
4877         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4878         struct hwrm_func_drv_if_change_input req = {0};
4879         uint32_t flags;
4880         int rc;
4881
4882         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4883                 return 0;
4884
4885         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4886          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4887          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4888          */
4889         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4890                 return 0;
4891
4892         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4893
4894         if (up)
4895                 req.flags =
4896                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4897
4898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4899
4900         HWRM_CHECK_RESULT();
4901         flags = rte_le_to_cpu_32(resp->flags);
4902         HWRM_UNLOCK();
4903
4904         if (!up)
4905                 return 0;
4906
4907         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4908                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4909                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4910         }
4911
4912         return 0;
4913 }
4914
4915 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4916 {
4917         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4918         struct bnxt_error_recovery_info *info = bp->recovery_info;
4919         struct hwrm_error_recovery_qcfg_input req = {0};
4920         uint32_t flags = 0;
4921         unsigned int i;
4922         int rc;
4923
4924         /* Older FW does not have error recovery support */
4925         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4926                 return 0;
4927
4928         if (!info) {
4929                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4930                                    sizeof(*info), 0);
4931                 bp->recovery_info = info;
4932                 if (info == NULL)
4933                         return -ENOMEM;
4934         } else {
4935                 memset(info, 0, sizeof(*info));
4936         }
4937
4938         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4939
4940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4941
4942         HWRM_CHECK_RESULT();
4943
4944         flags = rte_le_to_cpu_32(resp->flags);
4945         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4946                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4947         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4948                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4949
4950         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4951             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4952                 rc = -EINVAL;
4953                 goto err;
4954         }
4955
4956         /* FW returned values are in units of 100msec */
4957         info->driver_polling_freq =
4958                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4959         info->master_func_wait_period =
4960                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4961         info->normal_func_wait_period =
4962                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4963         info->master_func_wait_period_after_reset =
4964                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4965         info->max_bailout_time_after_reset =
4966                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4967         info->status_regs[BNXT_FW_STATUS_REG] =
4968                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4969         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4970                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4971         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4972                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4973         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4974                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4975         info->reg_array_cnt =
4976                 rte_le_to_cpu_32(resp->reg_array_cnt);
4977
4978         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4979                 rc = -EINVAL;
4980                 goto err;
4981         }
4982
4983         for (i = 0; i < info->reg_array_cnt; i++) {
4984                 info->reset_reg[i] =
4985                         rte_le_to_cpu_32(resp->reset_reg[i]);
4986                 info->reset_reg_val[i] =
4987                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4988                 info->delay_after_reset[i] =
4989                         resp->delay_after_reset[i];
4990         }
4991 err:
4992         HWRM_UNLOCK();
4993
4994         /* Map the FW status registers */
4995         if (!rc)
4996                 rc = bnxt_map_fw_health_status_regs(bp);
4997
4998         if (rc) {
4999                 rte_free(bp->recovery_info);
5000                 bp->recovery_info = NULL;
5001         }
5002         return rc;
5003 }
5004
5005 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5006 {
5007         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5008         struct hwrm_fw_reset_input req = {0};
5009         int rc;
5010
5011         if (!BNXT_PF(bp))
5012                 return -EOPNOTSUPP;
5013
5014         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5015
5016         req.embedded_proc_type =
5017                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5018         req.selfrst_status =
5019                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5020         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5021
5022         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5023                                     BNXT_USE_KONG(bp));
5024
5025         HWRM_CHECK_RESULT();
5026         HWRM_UNLOCK();
5027
5028         return rc;
5029 }
5030
5031 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5032 {
5033         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5034         struct hwrm_port_ts_query_input req = {0};
5035         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5036         uint32_t flags = 0;
5037         int rc;
5038
5039         if (!ptp)
5040                 return 0;
5041
5042         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5043
5044         switch (path) {
5045         case BNXT_PTP_FLAGS_PATH_TX:
5046                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5047                 break;
5048         case BNXT_PTP_FLAGS_PATH_RX:
5049                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5050                 break;
5051         case BNXT_PTP_FLAGS_CURRENT_TIME:
5052                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5053                 break;
5054         }
5055
5056         req.flags = rte_cpu_to_le_32(flags);
5057         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5058
5059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5060
5061         HWRM_CHECK_RESULT();
5062
5063         if (timestamp) {
5064                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5065                 *timestamp |=
5066                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5067         }
5068         HWRM_UNLOCK();
5069
5070         return rc;
5071 }
5072
5073 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5074 {
5075         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5076                                         bp->hwrm_cmd_resp_addr;
5077         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5078         uint32_t flags = 0;
5079         int rc = 0;
5080
5081         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5082                 return rc;
5083
5084         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5085                 PMD_DRV_LOG(DEBUG,
5086                             "Not a PF or trusted VF. Command not supported\n");
5087                 return 0;
5088         }
5089
5090         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5092
5093         HWRM_CHECK_RESULT();
5094         flags = rte_le_to_cpu_32(resp->flags);
5095         HWRM_UNLOCK();
5096
5097         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5098                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5099                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5100         }
5101
5102         return rc;
5103 }