drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                              struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct bnxt_vnic_info *vnic = NULL;
 371         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 372         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 373
 374         if (filter->fw_l2_filter_id == UINT64_MAX)
 375                 return 0;
 376
 377         if (filter->matching_l2_fltr_ptr)
 378                 l2_filter = filter->matching_l2_fltr_ptr;
 379
 380         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 381                     filter, l2_filter, l2_filter->l2_ref_cnt);
 382
 383         if (l2_filter->l2_ref_cnt == 0)
 384                 return 0;
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402         if (l2_filter->l2_ref_cnt == 0) {
 403                 vnic = l2_filter->vnic;
 404                 if (vnic) {
 405                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 406                                       bnxt_filter_info, next);
 407                         bnxt_free_filter(bp, l2_filter);
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 415                          uint16_t dst_id,
 416                          struct bnxt_filter_info *filter)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 420         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 421         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 422         const struct rte_eth_vmdq_rx_conf *conf =
 423                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 424         uint32_t enables = 0;
 425         uint16_t j = dst_id - 1;
 426
 427         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 428         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 429             conf->pool_map[j].pools & (1UL << j)) {
 430                 PMD_DRV_LOG(DEBUG,
 431                         "Add vlan %u to vmdq pool %u\n",
 432                         conf->pool_map[j].vlan_id, j);
 433
 434                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 435                 filter->enables |=
 436                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 437                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 438         }
 439
 440         if (filter->fw_l2_filter_id != UINT64_MAX)
 441                 bnxt_hwrm_clear_l2_filter(bp, filter);
 442
 443         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 444
 445         req.flags = rte_cpu_to_le_32(filter->flags);
 446
 447         enables = filter->enables |
 448               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 449         req.dst_id = rte_cpu_to_le_16(dst_id);
 450
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 453                 memcpy(req.l2_addr, filter->l2_addr,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 457                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 458                        RTE_ETHER_ADDR_LEN);
 459         if (enables &
 460             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 461                 req.l2_ovlan = filter->l2_ovlan;
 462         if (enables &
 463             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 464                 req.l2_ivlan = filter->l2_ivlan;
 465         if (enables &
 466             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 467                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 468         if (enables &
 469             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 470                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 471         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 472                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 473         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 474                 req.src_type = filter->src_type;
 475         if (filter->pri_hint) {
 476                 req.pri_hint = filter->pri_hint;
 477                 req.l2_filter_id_hint =
 478                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 479         }
 480
 481         req.enables = rte_cpu_to_le_32(enables);
 482
 483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 484
 485         HWRM_CHECK_RESULT();
 486
 487         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 488         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 489         HWRM_UNLOCK();
 490
 491         return rc;
 492 }
 493
 494 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 495 {
 496         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 497         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 498         uint32_t flags = 0;
 499         int rc;
 500
 501         if (!ptp)
 502                 return 0;
 503
 504         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 505
 506         if (ptp->rx_filter)
 507                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 508         else
 509                 flags |=
 510                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 511         if (ptp->tx_tstamp_en)
 512                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 513         else
 514                 flags |=
 515                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 516         req.flags = rte_cpu_to_le_32(flags);
 517         req.enables = rte_cpu_to_le_32
 518                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 519         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522         HWRM_UNLOCK();
 523
 524         return rc;
 525 }
 526
 527 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 531         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 532         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 533
 534         if (ptp)
 535                 return 0;
 536
 537         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 538
 539         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 540
 541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 542
 543         HWRM_CHECK_RESULT();
 544
 545         if (!BNXT_CHIP_THOR(bp) &&
 546             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 547                 return 0;
 548
 549         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 550                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 551
 552         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 553         if (!ptp)
 554                 return -ENOMEM;
 555
 556         if (!BNXT_CHIP_THOR(bp)) {
 557                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 559                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 560                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 561                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 562                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 563                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 564                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 565                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 566                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 567                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 568                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 569                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 570                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 571                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 572                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 573                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 574                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 575         }
 576
 577         ptp->bp = bp;
 578         bp->ptp_cfg = ptp;
 579
 580         return 0;
 581 }
 582
 583 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 584 {
 585         int rc = 0;
 586         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 587         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 588         uint16_t new_max_vfs;
 589         uint32_t flags;
 590         int i;
 591
 592         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 593
 594         req.fid = rte_cpu_to_le_16(0xffff);
 595
 596         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 597
 598         HWRM_CHECK_RESULT();
 599
 600         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 601         flags = rte_le_to_cpu_32(resp->flags);
 602         if (BNXT_PF(bp)) {
 603                 bp->pf.port_id = resp->port_id;
 604                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 605                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 606                 new_max_vfs = bp->pdev->max_vfs;
 607                 if (new_max_vfs != bp->pf.max_vfs) {
 608                         if (bp->pf.vf_info)
 609                                 rte_free(bp->pf.vf_info);
 610                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 611                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 612                         bp->pf.max_vfs = new_max_vfs;
 613                         for (i = 0; i < new_max_vfs; i++) {
 614                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 615                                 bp->pf.vf_info[i].vlan_table =
 616                                         rte_zmalloc("VF VLAN table",
 617                                                     getpagesize(),
 618                                                     getpagesize());
 619                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 620                                         PMD_DRV_LOG(ERR,
 621                                         "Fail to alloc VLAN table for VF %d\n",
 622                                         i);
 623                                 else
 624                                         rte_mem_lock_page(
 625                                                 bp->pf.vf_info[i].vlan_table);
 626                                 bp->pf.vf_info[i].vlan_as_table =
 627                                         rte_zmalloc("VF VLAN AS table",
 628                                                     getpagesize(),
 629                                                     getpagesize());
 630                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 631                                         PMD_DRV_LOG(ERR,
 632                                         "Alloc VLAN AS table for VF %d fail\n",
 633                                         i);
 634                                 else
 635                                         rte_mem_lock_page(
 636                                                bp->pf.vf_info[i].vlan_as_table);
 637                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 638                         }
 639                 }
 640         }
 641
 642         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 643         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 644         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 645         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 646         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 647         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 648         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 649         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 650         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 651         if (!BNXT_CHIP_THOR(bp))
 652                 bp->max_l2_ctx += bp->max_rx_em_flows;
 653         /* TODO: For now, do not support VMDq/RFS on VFs. */
 654         if (BNXT_PF(bp)) {
 655                 if (bp->pf.max_vfs)
 656                         bp->max_vnics = 1;
 657                 else
 658                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 659         } else {
 660                 bp->max_vnics = 1;
 661         }
 662         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 663         if (BNXT_PF(bp)) {
 664                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 665                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 666                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 667                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 668                         HWRM_UNLOCK();
 669                         bnxt_hwrm_ptp_qcfg(bp);
 670                 }
 671         }
 672
 673         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 674                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 675
 676         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 677                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 678                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 679         }
 680
 681         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 682                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 683
 684         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 685                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 686
 687         HWRM_UNLOCK();
 688
 689         return rc;
 690 }
 691
 692 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 693 {
 694         int rc;
 695
 696         rc = __bnxt_hwrm_func_qcaps(bp);
 697         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 698                 rc = bnxt_alloc_ctx_mem(bp);
 699                 if (rc)
 700                         return rc;
 701
 702                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 703                 if (!rc)
 704                         bp->flags |= BNXT_FLAG_NEW_RM;
 705         }
 706
 707         /* On older FW,
 708          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 709          * But the error can be ignored. Return success.
 710          */
 711
 712         return 0;
 713 }
 714
 715 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 716 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 717 {
 718         int rc = 0;
 719         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 720         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 721
 722         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 723
 724         req.target_id = rte_cpu_to_le_16(0xffff);
 725
 726         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 727
 728         HWRM_CHECK_RESULT();
 729
 730         if (rte_le_to_cpu_32(resp->flags) &
 731             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 732                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 733                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 734         }
 735
 736         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 737
 738         HWRM_UNLOCK();
 739
 740         return rc;
 741 }
 742
 743 int bnxt_hwrm_func_reset(struct bnxt *bp)
 744 {
 745         int rc = 0;
 746         struct hwrm_func_reset_input req = {.req_type = 0 };
 747         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 748
 749         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 750
 751         req.enables = rte_cpu_to_le_32(0);
 752
 753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 754
 755         HWRM_CHECK_RESULT();
 756         HWRM_UNLOCK();
 757
 758         return rc;
 759 }
 760
 761 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 762 {
 763         int rc;
 764         uint32_t flags = 0;
 765         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 766         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 767
 768         if (bp->flags & BNXT_FLAG_REGISTERED)
 769                 return 0;
 770
 771         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 772                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 773         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 774                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 775
 776         /* PFs and trusted VFs should indicate the support of the
 777          * Master capability on non Stingray platform
 778          */
 779         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 780                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 781
 782         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 783         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 784                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 785         req.ver_maj = RTE_VER_YEAR;
 786         req.ver_min = RTE_VER_MONTH;
 787         req.ver_upd = RTE_VER_MINOR;
 788
 789         if (BNXT_PF(bp)) {
 790                 req.enables |= rte_cpu_to_le_32(
 791                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 792                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 793                        RTE_MIN(sizeof(req.vf_req_fwd),
 794                                sizeof(bp->pf.vf_req_fwd)));
 795
 796                 /*
 797                  * PF can sniff HWRM API issued by VF. This can be set up by
 798                  * linux driver and inherited by the DPDK PF driver. Clear
 799                  * this HWRM sniffer list in FW because DPDK PF driver does
 800                  * not support this.
 801                  */
 802                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 803         }
 804
 805         req.flags = rte_cpu_to_le_32(flags);
 806
 807         req.async_event_fwd[0] |=
 808                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 809                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 810                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 811                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 812                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 813         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 814                 req.async_event_fwd[0] |=
 815                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 816         req.async_event_fwd[1] |=
 817                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 818                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 819
 820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 821
 822         HWRM_CHECK_RESULT();
 823
 824         flags = rte_le_to_cpu_32(resp->flags);
 825         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 826                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 827
 828         HWRM_UNLOCK();
 829
 830         bp->flags |= BNXT_FLAG_REGISTERED;
 831
 832         return rc;
 833 }
 834
 835 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 836 {
 837         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 838                 return 0;
 839
 840         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 841 }
 842
 843 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 844 {
 845         int rc;
 846         uint32_t flags = 0;
 847         uint32_t enables;
 848         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 849         struct hwrm_func_vf_cfg_input req = {0};
 850
 851         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 852
 853         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 854                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 855                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 856                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 857                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 858
 859         if (BNXT_HAS_RING_GRPS(bp)) {
 860                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 861                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 862         }
 863
 864         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 865         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 866                                             AGG_RING_MULTIPLIER);
 867         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 868         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 869                                               bp->tx_nr_rings +
 870                                               BNXT_NUM_ASYNC_CPR(bp));
 871         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 872         if (bp->vf_resv_strategy ==
 873             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 874                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 875                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 876                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 877                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 878                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 879                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 880         } else if (bp->vf_resv_strategy ==
 881                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 882                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 883                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 884         }
 885
 886         if (test)
 887                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 888                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 889                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 890                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 891                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 892                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 893
 894         if (test && BNXT_HAS_RING_GRPS(bp))
 895                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 896
 897         req.flags = rte_cpu_to_le_32(flags);
 898         req.enables |= rte_cpu_to_le_32(enables);
 899
 900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 901
 902         if (test)
 903                 HWRM_CHECK_RESULT_SILENT();
 904         else
 905                 HWRM_CHECK_RESULT();
 906
 907         HWRM_UNLOCK();
 908         return rc;
 909 }
 910
 911 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 912 {
 913         int rc;
 914         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 915         struct hwrm_func_resource_qcaps_input req = {0};
 916
 917         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 918         req.fid = rte_cpu_to_le_16(0xffff);
 919
 920         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 921
 922         HWRM_CHECK_RESULT_SILENT();
 923
 924         if (BNXT_VF(bp)) {
 925                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 926                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 927                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 928                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 929                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 930                 /* func_resource_qcaps does not return max_rx_em_flows.
 931                  * So use the value provided by func_qcaps.
 932                  */
 933                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 934                 if (!BNXT_CHIP_THOR(bp))
 935                         bp->max_l2_ctx += bp->max_rx_em_flows;
 936                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 937                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 938         }
 939         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 940         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 941         if (bp->vf_resv_strategy >
 942             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 943                 bp->vf_resv_strategy =
 944                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 945
 946         HWRM_UNLOCK();
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_ver_get(struct bnxt *bp)
 951 {
 952         int rc = 0;
 953         struct hwrm_ver_get_input req = {.req_type = 0 };
 954         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 955         uint32_t fw_version;
 956         uint16_t max_resp_len;
 957         char type[RTE_MEMZONE_NAMESIZE];
 958         uint32_t dev_caps_cfg;
 959
 960         bp->max_req_len = HWRM_MAX_REQ_LEN;
 961         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 962
 963         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 964         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 965         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 966
 967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 968
 969         if (bp->flags & BNXT_FLAG_FW_RESET)
 970                 HWRM_CHECK_RESULT_SILENT();
 971         else
 972                 HWRM_CHECK_RESULT();
 973
 974         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 975                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 976                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 977                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 978         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 979                      (resp->hwrm_fw_min_8b << 16) |
 980                      (resp->hwrm_fw_bld_8b << 8) |
 981                      resp->hwrm_fw_rsvd_8b;
 982         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 983                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 984
 985         fw_version = resp->hwrm_intf_maj_8b << 16;
 986         fw_version |= resp->hwrm_intf_min_8b << 8;
 987         fw_version |= resp->hwrm_intf_upd_8b;
 988         bp->hwrm_spec_code = fw_version;
 989
 990         /* def_req_timeout value is in milliseconds */
 991         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 992         /* convert timeout to usec */
 993         bp->hwrm_cmd_timeout *= 1000;
 994         if (!bp->hwrm_cmd_timeout)
 995                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 996
 997         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 998                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 999                 rc = -EINVAL;
1000                 goto error;
1001         }
1002
1003         if (bp->max_req_len > resp->max_req_win_len) {
1004                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1005                 rc = -EINVAL;
1006         }
1007         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1008         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1009         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1010                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1011
1012         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1013         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1014
1015         if (bp->max_resp_len != max_resp_len) {
1016                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1017                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1018                         bp->pdev->addr.devid, bp->pdev->addr.function);
1019
1020                 rte_free(bp->hwrm_cmd_resp_addr);
1021
1022                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1023                 if (bp->hwrm_cmd_resp_addr == NULL) {
1024                         rc = -ENOMEM;
1025                         goto error;
1026                 }
1027                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1028                 bp->hwrm_cmd_resp_dma_addr =
1029                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1030                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1031                         PMD_DRV_LOG(ERR,
1032                         "Unable to map response buffer to physical memory.\n");
1033                         rc = -ENOMEM;
1034                         goto error;
1035                 }
1036                 bp->max_resp_len = max_resp_len;
1037         }
1038
1039         if ((dev_caps_cfg &
1040                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1041             (dev_caps_cfg &
1042              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1043                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1044                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1045         }
1046
1047         if (((dev_caps_cfg &
1048               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1049              (dev_caps_cfg &
1050               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1051             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1052                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1053                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1054                         bp->pdev->addr.devid, bp->pdev->addr.function);
1055
1056                 rte_free(bp->hwrm_short_cmd_req_addr);
1057
1058                 bp->hwrm_short_cmd_req_addr =
1059                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1060                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1061                         rc = -ENOMEM;
1062                         goto error;
1063                 }
1064                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1065                 bp->hwrm_short_cmd_req_dma_addr =
1066                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1067                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1068                         rte_free(bp->hwrm_short_cmd_req_addr);
1069                         PMD_DRV_LOG(ERR,
1070                                 "Unable to map buffer to physical memory.\n");
1071                         rc = -ENOMEM;
1072                         goto error;
1073                 }
1074         }
1075         if (dev_caps_cfg &
1076             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1077                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1078                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1079         }
1080         if (dev_caps_cfg &
1081             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1082                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1083         if (dev_caps_cfg &
1084             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1085                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1086                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1087         }
1088
1089 error:
1090         HWRM_UNLOCK();
1091         return rc;
1092 }
1093
1094 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1095 {
1096         int rc;
1097         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1098         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1099
1100         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1101                 return 0;
1102
1103         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1104         req.flags = flags;
1105
1106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107
1108         HWRM_CHECK_RESULT();
1109         HWRM_UNLOCK();
1110
1111         return rc;
1112 }
1113
1114 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1115 {
1116         int rc = 0;
1117         struct hwrm_port_phy_cfg_input req = {0};
1118         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         uint32_t enables = 0;
1120
1121         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1122
1123         if (conf->link_up) {
1124                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1125                 if (bp->link_info.auto_mode && conf->link_speed) {
1126                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1127                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1128                 }
1129
1130                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1131                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1133                 /*
1134                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1135                  * any auto mode, even "none".
1136                  */
1137                 if (!conf->link_speed) {
1138                         /* No speeds specified. Enable AutoNeg - all speeds */
1139                         req.auto_mode =
1140                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1141                 }
1142                 /* AutoNeg - Advertise speeds specified. */
1143                 if (conf->auto_link_speed_mask &&
1144                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1145                         req.auto_mode =
1146                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1147                         req.auto_link_speed_mask =
1148                                 conf->auto_link_speed_mask;
1149                         enables |=
1150                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1151                 }
1152
1153                 req.auto_duplex = conf->duplex;
1154                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1155                 req.auto_pause = conf->auto_pause;
1156                 req.force_pause = conf->force_pause;
1157                 /* Set force_pause if there is no auto or if there is a force */
1158                 if (req.auto_pause && !req.force_pause)
1159                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1160                 else
1161                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1162
1163                 req.enables = rte_cpu_to_le_32(enables);
1164         } else {
1165                 req.flags =
1166                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1167                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1168         }
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         HWRM_CHECK_RESULT();
1173         HWRM_UNLOCK();
1174
1175         return rc;
1176 }
1177
1178 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1179                                    struct bnxt_link_info *link_info)
1180 {
1181         int rc = 0;
1182         struct hwrm_port_phy_qcfg_input req = {0};
1183         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184
1185         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1186
1187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1188
1189         HWRM_CHECK_RESULT();
1190
1191         link_info->phy_link_status = resp->link;
1192         link_info->link_up =
1193                 (link_info->phy_link_status ==
1194                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1195         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1196         link_info->duplex = resp->duplex_cfg;
1197         link_info->pause = resp->pause;
1198         link_info->auto_pause = resp->auto_pause;
1199         link_info->force_pause = resp->force_pause;
1200         link_info->auto_mode = resp->auto_mode;
1201         link_info->phy_type = resp->phy_type;
1202         link_info->media_type = resp->media_type;
1203
1204         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1205         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1206         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1207         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1208         link_info->phy_ver[0] = resp->phy_maj;
1209         link_info->phy_ver[1] = resp->phy_min;
1210         link_info->phy_ver[2] = resp->phy_bld;
1211
1212         HWRM_UNLOCK();
1213
1214         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1215         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1216         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1217         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1218         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1219                     link_info->auto_link_speed_mask);
1220         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1221                     link_info->force_link_speed);
1222
1223         return rc;
1224 }
1225
1226 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1227 {
1228         int i = 0;
1229
1230         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1231                 if (bp->tx_cos_queue[i].profile ==
1232                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1233                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1234                         return true;
1235                 }
1236         }
1237         return false;
1238 }
1239
1240 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1241 {
1242         int i = 0;
1243
1244         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1245                 if (bp->tx_cos_queue[i].profile !=
1246                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1247                     bp->tx_cos_queue[i].id !=
1248                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1249                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1250                         break;
1251                 }
1252         }
1253 }
1254
1255 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1256 {
1257         int rc = 0;
1258         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1259         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1260         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1261         int i;
1262
1263 get_rx_info:
1264         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1265
1266         req.flags = rte_cpu_to_le_32(dir);
1267         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1268         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1269             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1270                 req.drv_qmap_cap =
1271                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1273
1274         HWRM_CHECK_RESULT();
1275
1276         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1277                 GET_TX_QUEUE_INFO(0);
1278                 GET_TX_QUEUE_INFO(1);
1279                 GET_TX_QUEUE_INFO(2);
1280                 GET_TX_QUEUE_INFO(3);
1281                 GET_TX_QUEUE_INFO(4);
1282                 GET_TX_QUEUE_INFO(5);
1283                 GET_TX_QUEUE_INFO(6);
1284                 GET_TX_QUEUE_INFO(7);
1285         } else  {
1286                 GET_RX_QUEUE_INFO(0);
1287                 GET_RX_QUEUE_INFO(1);
1288                 GET_RX_QUEUE_INFO(2);
1289                 GET_RX_QUEUE_INFO(3);
1290                 GET_RX_QUEUE_INFO(4);
1291                 GET_RX_QUEUE_INFO(5);
1292                 GET_RX_QUEUE_INFO(6);
1293                 GET_RX_QUEUE_INFO(7);
1294         }
1295
1296         HWRM_UNLOCK();
1297
1298         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1299                 goto done;
1300
1301         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1302                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1303         } else {
1304                 int j;
1305
1306                 /* iterate and find the COSq profile to use for Tx */
1307                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1308                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1309                                 if (bp->tx_cos_queue[i].id != 0xff)
1310                                         bp->tx_cosq_id[j++] =
1311                                                 bp->tx_cos_queue[i].id;
1312                         }
1313                 } else {
1314                         /* When CoS classification is disabled, for normal NIC
1315                          * operations, ideally we should look to use LOSSY.
1316                          * If not found, fallback to the first valid profile
1317                          */
1318                         if (!bnxt_find_lossy_profile(bp))
1319                                 bnxt_find_first_valid_profile(bp);
1320
1321                 }
1322         }
1323
1324         bp->max_tc = resp->max_configurable_queues;
1325         bp->max_lltc = resp->max_configurable_lossless_queues;
1326         if (bp->max_tc > BNXT_MAX_QUEUE)
1327                 bp->max_tc = BNXT_MAX_QUEUE;
1328         bp->max_q = bp->max_tc;
1329
1330         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1331                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1332                 goto get_rx_info;
1333         }
1334
1335 done:
1336         return rc;
1337 }
1338
1339 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1340                          struct bnxt_ring *ring,
1341                          uint32_t ring_type, uint32_t map_index,
1342                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1343                          uint16_t tx_cosq_id)
1344 {
1345         int rc = 0;
1346         uint32_t enables = 0;
1347         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1348         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1349         struct rte_mempool *mb_pool;
1350         uint16_t rx_buf_size;
1351
1352         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1353
1354         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1355         req.fbo = rte_cpu_to_le_32(0);
1356         /* Association of ring index with doorbell index */
1357         req.logical_id = rte_cpu_to_le_16(map_index);
1358         req.length = rte_cpu_to_le_32(ring->ring_size);
1359
1360         switch (ring_type) {
1361         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1362                 req.ring_type = ring_type;
1363                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1364                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1365                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1366                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1367                         enables |=
1368                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1369                 break;
1370         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1371                 req.ring_type = ring_type;
1372                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1373                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1374                 if (BNXT_CHIP_THOR(bp)) {
1375                         mb_pool = bp->rx_queues[0]->mb_pool;
1376                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1377                                       RTE_PKTMBUF_HEADROOM;
1378                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1379                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1380                         enables |=
1381                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1382                 }
1383                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1384                         enables |=
1385                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1386                 break;
1387         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1388                 req.ring_type = ring_type;
1389                 if (BNXT_HAS_NQ(bp)) {
1390                         /* Association of cp ring with nq */
1391                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1392                         enables |=
1393                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1394                 }
1395                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1396                 break;
1397         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1398                 req.ring_type = ring_type;
1399                 req.page_size = BNXT_PAGE_SHFT;
1400                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1401                 break;
1402         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1403                 req.ring_type = ring_type;
1404                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1405
1406                 mb_pool = bp->rx_queues[0]->mb_pool;
1407                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1408                               RTE_PKTMBUF_HEADROOM;
1409                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1410                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1411
1412                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1413                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1414                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1415                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1416                 break;
1417         default:
1418                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1419                         ring_type);
1420                 HWRM_UNLOCK();
1421                 return -EINVAL;
1422         }
1423         req.enables = rte_cpu_to_le_32(enables);
1424
1425         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1426
1427         if (rc || resp->error_code) {
1428                 if (rc == 0 && resp->error_code)
1429                         rc = rte_le_to_cpu_16(resp->error_code);
1430                 switch (ring_type) {
1431                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1432                         PMD_DRV_LOG(ERR,
1433                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1434                         HWRM_UNLOCK();
1435                         return rc;
1436                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1437                         PMD_DRV_LOG(ERR,
1438                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1439                         HWRM_UNLOCK();
1440                         return rc;
1441                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1442                         PMD_DRV_LOG(ERR,
1443                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1444                                     rc);
1445                         HWRM_UNLOCK();
1446                         return rc;
1447                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1448                         PMD_DRV_LOG(ERR,
1449                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1450                         HWRM_UNLOCK();
1451                         return rc;
1452                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1453                         PMD_DRV_LOG(ERR,
1454                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1455                         HWRM_UNLOCK();
1456                         return rc;
1457                 default:
1458                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1459                         HWRM_UNLOCK();
1460                         return rc;
1461                 }
1462         }
1463
1464         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1465         HWRM_UNLOCK();
1466         return rc;
1467 }
1468
1469 int bnxt_hwrm_ring_free(struct bnxt *bp,
1470                         struct bnxt_ring *ring, uint32_t ring_type)
1471 {
1472         int rc;
1473         struct hwrm_ring_free_input req = {.req_type = 0 };
1474         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1475
1476         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1477
1478         req.ring_type = ring_type;
1479         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1480
1481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482
1483         if (rc || resp->error_code) {
1484                 if (rc == 0 && resp->error_code)
1485                         rc = rte_le_to_cpu_16(resp->error_code);
1486                 HWRM_UNLOCK();
1487
1488                 switch (ring_type) {
1489                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1490                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1491                                 rc);
1492                         return rc;
1493                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1494                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1495                                 rc);
1496                         return rc;
1497                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1498                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1499                                 rc);
1500                         return rc;
1501                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1502                         PMD_DRV_LOG(ERR,
1503                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1504                         return rc;
1505                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1506                         PMD_DRV_LOG(ERR,
1507                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1508                         return rc;
1509                 default:
1510                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1511                         return rc;
1512                 }
1513         }
1514         HWRM_UNLOCK();
1515         return 0;
1516 }
1517
1518 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1519 {
1520         int rc = 0;
1521         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1522         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1523
1524         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1525
1526         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1527         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1528         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1529         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1530
1531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1532
1533         HWRM_CHECK_RESULT();
1534
1535         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1536
1537         HWRM_UNLOCK();
1538
1539         return rc;
1540 }
1541
1542 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1543 {
1544         int rc;
1545         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1546         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1547
1548         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1549
1550         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1551
1552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1553
1554         HWRM_CHECK_RESULT();
1555         HWRM_UNLOCK();
1556
1557         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1558         return rc;
1559 }
1560
1561 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1562 {
1563         int rc = 0;
1564         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1565         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1566
1567         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1568                 return rc;
1569
1570         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1571
1572         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1573
1574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1575
1576         HWRM_CHECK_RESULT();
1577         HWRM_UNLOCK();
1578
1579         return rc;
1580 }
1581
1582 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1583                                 unsigned int idx __rte_unused)
1584 {
1585         int rc;
1586         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1587         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1588
1589         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1590
1591         req.update_period_ms = rte_cpu_to_le_32(0);
1592
1593         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1594
1595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1596
1597         HWRM_CHECK_RESULT();
1598
1599         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1600
1601         HWRM_UNLOCK();
1602
1603         return rc;
1604 }
1605
1606 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1607                                 unsigned int idx __rte_unused)
1608 {
1609         int rc;
1610         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1611         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1612
1613         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1614
1615         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1616
1617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618
1619         HWRM_CHECK_RESULT();
1620         HWRM_UNLOCK();
1621
1622         return rc;
1623 }
1624
1625 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1626 {
1627         int rc = 0, i, j;
1628         struct hwrm_vnic_alloc_input req = { 0 };
1629         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630
1631         if (!BNXT_HAS_RING_GRPS(bp))
1632                 goto skip_ring_grps;
1633
1634         /* map ring groups to this vnic */
1635         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1636                 vnic->start_grp_id, vnic->end_grp_id);
1637         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1638                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1639
1640         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1641         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1643         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1644
1645 skip_ring_grps:
1646         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1647         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1648
1649         if (vnic->func_default)
1650                 req.flags =
1651                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1653
1654         HWRM_CHECK_RESULT();
1655
1656         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1657         HWRM_UNLOCK();
1658         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1659         return rc;
1660 }
1661
1662 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1663                                         struct bnxt_vnic_info *vnic,
1664                                         struct bnxt_plcmodes_cfg *pmode)
1665 {
1666         int rc = 0;
1667         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1668         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1669
1670         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1671
1672         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1673
1674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1675
1676         HWRM_CHECK_RESULT();
1677
1678         pmode->flags = rte_le_to_cpu_32(resp->flags);
1679         /* dflt_vnic bit doesn't exist in the _cfg command */
1680         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1681         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1682         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1683         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1684
1685         HWRM_UNLOCK();
1686
1687         return rc;
1688 }
1689
1690 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1691                                        struct bnxt_vnic_info *vnic,
1692                                        struct bnxt_plcmodes_cfg *pmode)
1693 {
1694         int rc = 0;
1695         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1696         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1697
1698         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1699                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1700                 return rc;
1701         }
1702
1703         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1704
1705         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1706         req.flags = rte_cpu_to_le_32(pmode->flags);
1707         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1708         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1709         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1710         req.enables = rte_cpu_to_le_32(
1711             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1712             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1713             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1714         );
1715
1716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1717
1718         HWRM_CHECK_RESULT();
1719         HWRM_UNLOCK();
1720
1721         return rc;
1722 }
1723
1724 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1725 {
1726         int rc = 0;
1727         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1728         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1729         struct bnxt_plcmodes_cfg pmodes = { 0 };
1730         uint32_t ctx_enable_flag = 0;
1731         uint32_t enables = 0;
1732
1733         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1734                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1735                 return rc;
1736         }
1737
1738         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1739         if (rc)
1740                 return rc;
1741
1742         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1743
1744         if (BNXT_CHIP_THOR(bp)) {
1745                 int dflt_rxq = vnic->start_grp_id;
1746                 struct bnxt_rx_ring_info *rxr;
1747                 struct bnxt_cp_ring_info *cpr;
1748                 struct bnxt_rx_queue *rxq;
1749                 int i;
1750
1751                 /*
1752                  * The first active receive ring is used as the VNIC
1753                  * default receive ring. If there are no active receive
1754                  * rings (all corresponding receive queues are stopped),
1755                  * the first receive ring is used.
1756                  */
1757                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1758                         rxq = bp->eth_dev->data->rx_queues[i];
1759                         if (rxq->rx_started) {
1760                                 dflt_rxq = i;
1761                                 break;
1762                         }
1763                 }
1764
1765                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1766                 rxr = rxq->rx_ring;
1767                 cpr = rxq->cp_ring;
1768
1769                 req.default_rx_ring_id =
1770                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1771                 req.default_cmpl_ring_id =
1772                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1773                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1774                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1775                 goto config_mru;
1776         }
1777
1778         /* Only RSS support for now TBD: COS & LB */
1779         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1780         if (vnic->lb_rule != 0xffff)
1781                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1782         if (vnic->cos_rule != 0xffff)
1783                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1784         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1785                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1786                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1787         }
1788         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1789                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1790                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1791         }
1792
1793         enables |= ctx_enable_flag;
1794         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1795         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1796         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1797         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1798
1799 config_mru:
1800         req.enables = rte_cpu_to_le_32(enables);
1801         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1802         req.mru = rte_cpu_to_le_16(vnic->mru);
1803         /* Configure default VNIC only once. */
1804         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1805                 req.flags |=
1806                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1807                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1808         }
1809         if (vnic->vlan_strip)
1810                 req.flags |=
1811                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1812         if (vnic->bd_stall)
1813                 req.flags |=
1814                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1815         if (vnic->roce_dual)
1816                 req.flags |= rte_cpu_to_le_32(
1817                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1818         if (vnic->roce_only)
1819                 req.flags |= rte_cpu_to_le_32(
1820                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1821         if (vnic->rss_dflt_cr)
1822                 req.flags |= rte_cpu_to_le_32(
1823                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1824
1825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826
1827         HWRM_CHECK_RESULT();
1828         HWRM_UNLOCK();
1829
1830         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1831
1832         return rc;
1833 }
1834
1835 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1836                 int16_t fw_vf_id)
1837 {
1838         int rc = 0;
1839         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1840         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1841
1842         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1843                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1844                 return rc;
1845         }
1846         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1847
1848         req.enables =
1849                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1850         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1851         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1852
1853         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854
1855         HWRM_CHECK_RESULT();
1856
1857         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1858         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1859         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1860         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1861         vnic->mru = rte_le_to_cpu_16(resp->mru);
1862         vnic->func_default = rte_le_to_cpu_32(
1863                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1864         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1865                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1866         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1867                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1868         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1869                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1870         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1871                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1872         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1873                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1874
1875         HWRM_UNLOCK();
1876
1877         return rc;
1878 }
1879
1880 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1881                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1882 {
1883         int rc = 0;
1884         uint16_t ctx_id;
1885         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1886         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1887                                                 bp->hwrm_cmd_resp_addr;
1888
1889         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1890
1891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892         HWRM_CHECK_RESULT();
1893
1894         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1895         if (!BNXT_HAS_RING_GRPS(bp))
1896                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1897         else if (ctx_idx == 0)
1898                 vnic->rss_rule = ctx_id;
1899
1900         HWRM_UNLOCK();
1901
1902         return rc;
1903 }
1904
1905 static
1906 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1907                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1908 {
1909         int rc = 0;
1910         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1911         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1912                                                 bp->hwrm_cmd_resp_addr;
1913
1914         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1915                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1916                 return rc;
1917         }
1918         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1919
1920         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1921
1922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1923
1924         HWRM_CHECK_RESULT();
1925         HWRM_UNLOCK();
1926
1927         return rc;
1928 }
1929
1930 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1931 {
1932         int rc = 0;
1933
1934         if (BNXT_CHIP_THOR(bp)) {
1935                 int j;
1936
1937                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1938                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1939                                                       vnic,
1940                                                       vnic->fw_grp_ids[j]);
1941                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1942                 }
1943                 vnic->num_lb_ctxts = 0;
1944         } else {
1945                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1946                 vnic->rss_rule = INVALID_HW_RING_ID;
1947         }
1948
1949         return rc;
1950 }
1951
1952 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1953 {
1954         int rc = 0;
1955         struct hwrm_vnic_free_input req = {.req_type = 0 };
1956         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1957
1958         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1959                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1960                 return rc;
1961         }
1962
1963         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1964
1965         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1966
1967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968
1969         HWRM_CHECK_RESULT();
1970         HWRM_UNLOCK();
1971
1972         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1973         /* Configure default VNIC again if necessary. */
1974         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1975                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1976
1977         return rc;
1978 }
1979
1980 static int
1981 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1982 {
1983         int i;
1984         int rc = 0;
1985         int nr_ctxs = vnic->num_lb_ctxts;
1986         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1987         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1988
1989         for (i = 0; i < nr_ctxs; i++) {
1990                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1991
1992                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1994                 req.hash_mode_flags = vnic->hash_mode;
1995
1996                 req.hash_key_tbl_addr =
1997                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1998
1999                 req.ring_grp_tbl_addr =
2000                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2001                                          i * HW_HASH_INDEX_SIZE);
2002                 req.ring_table_pair_index = i;
2003                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2004
2005                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2006                                             BNXT_USE_CHIMP_MB);
2007
2008                 HWRM_CHECK_RESULT();
2009                 HWRM_UNLOCK();
2010         }
2011
2012         return rc;
2013 }
2014
2015 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2016                            struct bnxt_vnic_info *vnic)
2017 {
2018         int rc = 0;
2019         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2020         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021
2022         if (!vnic->rss_table)
2023                 return 0;
2024
2025         if (BNXT_CHIP_THOR(bp))
2026                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2027
2028         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2029
2030         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2031         req.hash_mode_flags = vnic->hash_mode;
2032
2033         req.ring_grp_tbl_addr =
2034             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2035         req.hash_key_tbl_addr =
2036             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2037         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2038         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2039
2040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2041
2042         HWRM_CHECK_RESULT();
2043         HWRM_UNLOCK();
2044
2045         return rc;
2046 }
2047
2048 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2049                         struct bnxt_vnic_info *vnic)
2050 {
2051         int rc = 0;
2052         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2053         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2054         uint16_t size;
2055
2056         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2058                 return rc;
2059         }
2060
2061         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2062
2063         req.flags = rte_cpu_to_le_32(
2064                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2065
2066         req.enables = rte_cpu_to_le_32(
2067                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2068
2069         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2070         size -= RTE_PKTMBUF_HEADROOM;
2071         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2072
2073         req.jumbo_thresh = rte_cpu_to_le_16(size);
2074         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077
2078         HWRM_CHECK_RESULT();
2079         HWRM_UNLOCK();
2080
2081         return rc;
2082 }
2083
2084 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2085                         struct bnxt_vnic_info *vnic, bool enable)
2086 {
2087         int rc = 0;
2088         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2089         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2090
2091         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2092                 if (enable)
2093                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2094                 return -ENOTSUP;
2095         }
2096
2097         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2099                 return 0;
2100         }
2101
2102         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2103
2104         if (enable) {
2105                 req.enables = rte_cpu_to_le_32(
2106                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2107                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2108                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2109                 req.flags = rte_cpu_to_le_32(
2110                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2112                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2113                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2114                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2115                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2116                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2117                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2118                 req.min_agg_len = rte_cpu_to_le_32(512);
2119         }
2120         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2121
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123
2124         HWRM_CHECK_RESULT();
2125         HWRM_UNLOCK();
2126
2127         return rc;
2128 }
2129
2130 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2131 {
2132         struct hwrm_func_cfg_input req = {0};
2133         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2134         int rc;
2135
2136         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2137         req.enables = rte_cpu_to_le_32(
2138                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2139         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2140         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2141
2142         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2143
2144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2145         HWRM_CHECK_RESULT();
2146         HWRM_UNLOCK();
2147
2148         bp->pf.vf_info[vf].random_mac = false;
2149
2150         return rc;
2151 }
2152
2153 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2154                                   uint64_t *dropped)
2155 {
2156         int rc = 0;
2157         struct hwrm_func_qstats_input req = {.req_type = 0};
2158         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2159
2160         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2161
2162         req.fid = rte_cpu_to_le_16(fid);
2163
2164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2165
2166         HWRM_CHECK_RESULT();
2167
2168         if (dropped)
2169                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2170
2171         HWRM_UNLOCK();
2172
2173         return rc;
2174 }
2175
2176 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2177                           struct rte_eth_stats *stats)
2178 {
2179         int rc = 0;
2180         struct hwrm_func_qstats_input req = {.req_type = 0};
2181         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2182
2183         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2184
2185         req.fid = rte_cpu_to_le_16(fid);
2186
2187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2188
2189         HWRM_CHECK_RESULT();
2190
2191         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2192         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2193         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2194         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2195         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2196         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2197
2198         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2199         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2200         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2201         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2202         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2203         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2204
2205         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2206         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2207         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2208
2209         HWRM_UNLOCK();
2210
2211         return rc;
2212 }
2213
2214 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2215 {
2216         int rc = 0;
2217         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2218         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2219
2220         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2221
2222         req.fid = rte_cpu_to_le_16(fid);
2223
2224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2225
2226         HWRM_CHECK_RESULT();
2227         HWRM_UNLOCK();
2228
2229         return rc;
2230 }
2231
2232 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2233 {
2234         unsigned int i;
2235         int rc = 0;
2236
2237         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2238                 struct bnxt_tx_queue *txq;
2239                 struct bnxt_rx_queue *rxq;
2240                 struct bnxt_cp_ring_info *cpr;
2241
2242                 if (i >= bp->rx_cp_nr_rings) {
2243                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2244                         cpr = txq->cp_ring;
2245                 } else {
2246                         rxq = bp->rx_queues[i];
2247                         cpr = rxq->cp_ring;
2248                 }
2249
2250                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2251                 if (rc)
2252                         return rc;
2253         }
2254         return 0;
2255 }
2256
2257 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2258 {
2259         int rc;
2260         unsigned int i;
2261         struct bnxt_cp_ring_info *cpr;
2262
2263         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2264
2265                 if (i >= bp->rx_cp_nr_rings) {
2266                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2267                 } else {
2268                         cpr = bp->rx_queues[i]->cp_ring;
2269                         if (BNXT_HAS_RING_GRPS(bp))
2270                                 bp->grp_info[i].fw_stats_ctx = -1;
2271                 }
2272                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2273                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2274                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2275                         if (rc)
2276                                 return rc;
2277                 }
2278         }
2279         return 0;
2280 }
2281
2282 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2283 {
2284         unsigned int i;
2285         int rc = 0;
2286
2287         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2288                 struct bnxt_tx_queue *txq;
2289                 struct bnxt_rx_queue *rxq;
2290                 struct bnxt_cp_ring_info *cpr;
2291
2292                 if (i >= bp->rx_cp_nr_rings) {
2293                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2294                         cpr = txq->cp_ring;
2295                 } else {
2296                         rxq = bp->rx_queues[i];
2297                         cpr = rxq->cp_ring;
2298                 }
2299
2300                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2301
2302                 if (rc)
2303                         return rc;
2304         }
2305         return rc;
2306 }
2307
2308 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2309 {
2310         uint16_t idx;
2311         uint32_t rc = 0;
2312
2313         if (!BNXT_HAS_RING_GRPS(bp))
2314                 return 0;
2315
2316         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2317
2318                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2319                         continue;
2320
2321                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2322
2323                 if (rc)
2324                         return rc;
2325         }
2326         return rc;
2327 }
2328
2329 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2330 {
2331         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2332
2333         bnxt_hwrm_ring_free(bp, cp_ring,
2334                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2335         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2336         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2337                                      sizeof(*cpr->cp_desc_ring));
2338         cpr->cp_raw_cons = 0;
2339         cpr->valid = 0;
2340 }
2341
2342 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2343 {
2344         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2345
2346         bnxt_hwrm_ring_free(bp, cp_ring,
2347                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2348         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2349         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2350                         sizeof(*cpr->cp_desc_ring));
2351         cpr->cp_raw_cons = 0;
2352         cpr->valid = 0;
2353 }
2354
2355 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2356 {
2357         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2358         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2359         struct bnxt_ring *ring = rxr->rx_ring_struct;
2360         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2361
2362         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2363                 bnxt_hwrm_ring_free(bp, ring,
2364                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2365                 ring->fw_ring_id = INVALID_HW_RING_ID;
2366                 if (BNXT_HAS_RING_GRPS(bp))
2367                         bp->grp_info[queue_index].rx_fw_ring_id =
2368                                                         INVALID_HW_RING_ID;
2369                 memset(rxr->rx_desc_ring, 0,
2370                        rxr->rx_ring_struct->ring_size *
2371                        sizeof(*rxr->rx_desc_ring));
2372                 memset(rxr->rx_buf_ring, 0,
2373                        rxr->rx_ring_struct->ring_size *
2374                        sizeof(*rxr->rx_buf_ring));
2375                 rxr->rx_prod = 0;
2376         }
2377         ring = rxr->ag_ring_struct;
2378         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2379                 bnxt_hwrm_ring_free(bp, ring,
2380                                     BNXT_CHIP_THOR(bp) ?
2381                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2382                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2383                 ring->fw_ring_id = INVALID_HW_RING_ID;
2384                 memset(rxr->ag_buf_ring, 0,
2385                        rxr->ag_ring_struct->ring_size *
2386                        sizeof(*rxr->ag_buf_ring));
2387                 rxr->ag_prod = 0;
2388                 if (BNXT_HAS_RING_GRPS(bp))
2389                         bp->grp_info[queue_index].ag_fw_ring_id =
2390                                                         INVALID_HW_RING_ID;
2391         }
2392         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2393                 bnxt_free_cp_ring(bp, cpr);
2394
2395         if (BNXT_HAS_RING_GRPS(bp))
2396                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2397 }
2398
2399 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2400 {
2401         unsigned int i;
2402
2403         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2404                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2405                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2406                 struct bnxt_ring *ring = txr->tx_ring_struct;
2407                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2408
2409                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2410                         bnxt_hwrm_ring_free(bp, ring,
2411                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2412                         ring->fw_ring_id = INVALID_HW_RING_ID;
2413                         memset(txr->tx_desc_ring, 0,
2414                                         txr->tx_ring_struct->ring_size *
2415                                         sizeof(*txr->tx_desc_ring));
2416                         memset(txr->tx_buf_ring, 0,
2417                                         txr->tx_ring_struct->ring_size *
2418                                         sizeof(*txr->tx_buf_ring));
2419                         txr->tx_prod = 0;
2420                         txr->tx_cons = 0;
2421                 }
2422                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2423                         bnxt_free_cp_ring(bp, cpr);
2424                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2425                 }
2426         }
2427
2428         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2429                 bnxt_free_hwrm_rx_ring(bp, i);
2430
2431         return 0;
2432 }
2433
2434 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2435 {
2436         uint16_t i;
2437         uint32_t rc = 0;
2438
2439         if (!BNXT_HAS_RING_GRPS(bp))
2440                 return 0;
2441
2442         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2443                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2444                 if (rc)
2445                         return rc;
2446         }
2447         return rc;
2448 }
2449
2450 /*
2451  * HWRM utility functions
2452  */
2453
2454 void bnxt_free_hwrm_resources(struct bnxt *bp)
2455 {
2456         /* Release memzone */
2457         rte_free(bp->hwrm_cmd_resp_addr);
2458         rte_free(bp->hwrm_short_cmd_req_addr);
2459         bp->hwrm_cmd_resp_addr = NULL;
2460         bp->hwrm_short_cmd_req_addr = NULL;
2461         bp->hwrm_cmd_resp_dma_addr = 0;
2462         bp->hwrm_short_cmd_req_dma_addr = 0;
2463 }
2464
2465 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2466 {
2467         struct rte_pci_device *pdev = bp->pdev;
2468         char type[RTE_MEMZONE_NAMESIZE];
2469
2470         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2471                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2472         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2473         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2474         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2475         if (bp->hwrm_cmd_resp_addr == NULL)
2476                 return -ENOMEM;
2477         bp->hwrm_cmd_resp_dma_addr =
2478                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2479         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2480                 PMD_DRV_LOG(ERR,
2481                         "unable to map response address to physical memory\n");
2482                 return -ENOMEM;
2483         }
2484         rte_spinlock_init(&bp->hwrm_lock);
2485
2486         return 0;
2487 }
2488
2489 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2490 {
2491         struct bnxt_filter_info *filter;
2492         int rc = 0;
2493
2494         STAILQ_FOREACH(filter, &vnic->filter, next) {
2495                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2496                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2497                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2498                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2499                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2500                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2501                 bnxt_free_filter(bp, filter);
2502         }
2503         return rc;
2504 }
2505
2506 static int
2507 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2508 {
2509         struct bnxt_filter_info *filter;
2510         struct rte_flow *flow;
2511         int rc = 0;
2512
2513         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2514                 flow = STAILQ_FIRST(&vnic->flow_list);
2515                 filter = flow->filter;
2516                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2517                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2518                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2519                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2520                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2521                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2522
2523                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2524                 rte_free(flow);
2525         }
2526         return rc;
2527 }
2528
2529 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2530 {
2531         struct bnxt_filter_info *filter;
2532         int rc = 0;
2533
2534         STAILQ_FOREACH(filter, &vnic->filter, next) {
2535                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2536                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2537                                                      filter);
2538                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2539                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2540                                                          filter);
2541                 else
2542                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2543                                                      filter);
2544                 if (rc)
2545                         break;
2546         }
2547         return rc;
2548 }
2549
2550 void bnxt_free_tunnel_ports(struct bnxt *bp)
2551 {
2552         if (bp->vxlan_port_cnt)
2553                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2554                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2555         bp->vxlan_port = 0;
2556         if (bp->geneve_port_cnt)
2557                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2558                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2559         bp->geneve_port = 0;
2560 }
2561
2562 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2563 {
2564         int i;
2565
2566         if (bp->vnic_info == NULL)
2567                 return;
2568
2569         /*
2570          * Cleanup VNICs in reverse order, to make sure the L2 filter
2571          * from vnic0 is last to be cleaned up.
2572          */
2573         for (i = bp->max_vnics - 1; i >= 0; i--) {
2574                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2575
2576                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2577                         continue;
2578
2579                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2580
2581                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2582
2583                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2584
2585                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2586
2587                 bnxt_hwrm_vnic_free(bp, vnic);
2588
2589                 rte_free(vnic->fw_grp_ids);
2590         }
2591         /* Ring resources */
2592         bnxt_free_all_hwrm_rings(bp);
2593         bnxt_free_all_hwrm_ring_grps(bp);
2594         bnxt_free_all_hwrm_stat_ctxs(bp);
2595         bnxt_free_tunnel_ports(bp);
2596 }
2597
2598 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2599 {
2600         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2601
2602         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2603                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2604
2605         switch (conf_link_speed) {
2606         case ETH_LINK_SPEED_10M_HD:
2607         case ETH_LINK_SPEED_100M_HD:
2608                 /* FALLTHROUGH */
2609                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2610         }
2611         return hw_link_duplex;
2612 }
2613
2614 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2615 {
2616         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2617 }
2618
2619 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2620 {
2621         uint16_t eth_link_speed = 0;
2622
2623         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2624                 return ETH_LINK_SPEED_AUTONEG;
2625
2626         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2627         case ETH_LINK_SPEED_100M:
2628         case ETH_LINK_SPEED_100M_HD:
2629                 /* FALLTHROUGH */
2630                 eth_link_speed =
2631                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2632                 break;
2633         case ETH_LINK_SPEED_1G:
2634                 eth_link_speed =
2635                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2636                 break;
2637         case ETH_LINK_SPEED_2_5G:
2638                 eth_link_speed =
2639                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2640                 break;
2641         case ETH_LINK_SPEED_10G:
2642                 eth_link_speed =
2643                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2644                 break;
2645         case ETH_LINK_SPEED_20G:
2646                 eth_link_speed =
2647                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2648                 break;
2649         case ETH_LINK_SPEED_25G:
2650                 eth_link_speed =
2651                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2652                 break;
2653         case ETH_LINK_SPEED_40G:
2654                 eth_link_speed =
2655                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2656                 break;
2657         case ETH_LINK_SPEED_50G:
2658                 eth_link_speed =
2659                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2660                 break;
2661         case ETH_LINK_SPEED_100G:
2662                 eth_link_speed =
2663                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2664                 break;
2665         default:
2666                 PMD_DRV_LOG(ERR,
2667                         "Unsupported link speed %d; default to AUTO\n",
2668                         conf_link_speed);
2669                 break;
2670         }
2671         return eth_link_speed;
2672 }
2673
2674 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2675                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2676                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2677                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2678
2679 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2680 {
2681         uint32_t one_speed;
2682
2683         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2684                 return 0;
2685
2686         if (link_speed & ETH_LINK_SPEED_FIXED) {
2687                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2688
2689                 if (one_speed & (one_speed - 1)) {
2690                         PMD_DRV_LOG(ERR,
2691                                 "Invalid advertised speeds (%u) for port %u\n",
2692                                 link_speed, port_id);
2693                         return -EINVAL;
2694                 }
2695                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2696                         PMD_DRV_LOG(ERR,
2697                                 "Unsupported advertised speed (%u) for port %u\n",
2698                                 link_speed, port_id);
2699                         return -EINVAL;
2700                 }
2701         } else {
2702                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2703                         PMD_DRV_LOG(ERR,
2704                                 "Unsupported advertised speeds (%u) for port %u\n",
2705                                 link_speed, port_id);
2706                         return -EINVAL;
2707                 }
2708         }
2709         return 0;
2710 }
2711
2712 static uint16_t
2713 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2714 {
2715         uint16_t ret = 0;
2716
2717         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2718                 if (bp->link_info.support_speeds)
2719                         return bp->link_info.support_speeds;
2720                 link_speed = BNXT_SUPPORTED_SPEEDS;
2721         }
2722
2723         if (link_speed & ETH_LINK_SPEED_100M)
2724                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2725         if (link_speed & ETH_LINK_SPEED_100M_HD)
2726                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2727         if (link_speed & ETH_LINK_SPEED_1G)
2728                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2729         if (link_speed & ETH_LINK_SPEED_2_5G)
2730                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2731         if (link_speed & ETH_LINK_SPEED_10G)
2732                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2733         if (link_speed & ETH_LINK_SPEED_20G)
2734                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2735         if (link_speed & ETH_LINK_SPEED_25G)
2736                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2737         if (link_speed & ETH_LINK_SPEED_40G)
2738                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2739         if (link_speed & ETH_LINK_SPEED_50G)
2740                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2741         if (link_speed & ETH_LINK_SPEED_100G)
2742                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2743         return ret;
2744 }
2745
2746 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2747 {
2748         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2749
2750         switch (hw_link_speed) {
2751         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2752                 eth_link_speed = ETH_SPEED_NUM_100M;
2753                 break;
2754         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2755                 eth_link_speed = ETH_SPEED_NUM_1G;
2756                 break;
2757         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2758                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2759                 break;
2760         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2761                 eth_link_speed = ETH_SPEED_NUM_10G;
2762                 break;
2763         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2764                 eth_link_speed = ETH_SPEED_NUM_20G;
2765                 break;
2766         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2767                 eth_link_speed = ETH_SPEED_NUM_25G;
2768                 break;
2769         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2770                 eth_link_speed = ETH_SPEED_NUM_40G;
2771                 break;
2772         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2773                 eth_link_speed = ETH_SPEED_NUM_50G;
2774                 break;
2775         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2776                 eth_link_speed = ETH_SPEED_NUM_100G;
2777                 break;
2778         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2779         default:
2780                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2781                         hw_link_speed);
2782                 break;
2783         }
2784         return eth_link_speed;
2785 }
2786
2787 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2788 {
2789         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2790
2791         switch (hw_link_duplex) {
2792         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2793         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2794                 /* FALLTHROUGH */
2795                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2796                 break;
2797         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2798                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2799                 break;
2800         default:
2801                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2802                         hw_link_duplex);
2803                 break;
2804         }
2805         return eth_link_duplex;
2806 }
2807
2808 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2809 {
2810         int rc = 0;
2811         struct bnxt_link_info *link_info = &bp->link_info;
2812
2813         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2814         if (rc) {
2815                 PMD_DRV_LOG(ERR,
2816                         "Get link config failed with rc %d\n", rc);
2817                 goto exit;
2818         }
2819         if (link_info->link_speed)
2820                 link->link_speed =
2821                         bnxt_parse_hw_link_speed(link_info->link_speed);
2822         else
2823                 link->link_speed = ETH_SPEED_NUM_NONE;
2824         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2825         link->link_status = link_info->link_up;
2826         link->link_autoneg = link_info->auto_mode ==
2827                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2828                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2829 exit:
2830         return rc;
2831 }
2832
2833 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2834 {
2835         int rc = 0;
2836         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2837         struct bnxt_link_info link_req;
2838         uint16_t speed, autoneg;
2839
2840         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2841                 return 0;
2842
2843         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2844                         bp->eth_dev->data->port_id);
2845         if (rc)
2846                 goto error;
2847
2848         memset(&link_req, 0, sizeof(link_req));
2849         link_req.link_up = link_up;
2850         if (!link_up)
2851                 goto port_phy_cfg;
2852
2853         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2854         if (BNXT_CHIP_THOR(bp) &&
2855             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2856                 /* 40G is not supported as part of media auto detect.
2857                  * The speed should be forced and autoneg disabled
2858                  * to configure 40G speed.
2859                  */
2860                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2861                 autoneg = 0;
2862         }
2863
2864         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2865         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2866         /* Autoneg can be done only when the FW allows.
2867          * When user configures fixed speed of 40G and later changes to
2868          * any other speed, auto_link_speed/force_link_speed is still set
2869          * to 40G until link comes up at new speed.
2870          */
2871         if (autoneg == 1 &&
2872             !(!BNXT_CHIP_THOR(bp) &&
2873               (bp->link_info.auto_link_speed ||
2874                bp->link_info.force_link_speed))) {
2875                 link_req.phy_flags |=
2876                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2877                 link_req.auto_link_speed_mask =
2878                         bnxt_parse_eth_link_speed_mask(bp,
2879                                                        dev_conf->link_speeds);
2880         } else {
2881                 if (bp->link_info.phy_type ==
2882                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2883                     bp->link_info.phy_type ==
2884                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2885                     bp->link_info.media_type ==
2886                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2887                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2888                         return -EINVAL;
2889                 }
2890
2891                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2892                 /* If user wants a particular speed try that first. */
2893                 if (speed)
2894                         link_req.link_speed = speed;
2895                 else if (bp->link_info.force_link_speed)
2896                         link_req.link_speed = bp->link_info.force_link_speed;
2897                 else
2898                         link_req.link_speed = bp->link_info.auto_link_speed;
2899         }
2900         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2901         link_req.auto_pause = bp->link_info.auto_pause;
2902         link_req.force_pause = bp->link_info.force_pause;
2903
2904 port_phy_cfg:
2905         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2906         if (rc) {
2907                 PMD_DRV_LOG(ERR,
2908                         "Set link config failed with rc %d\n", rc);
2909         }
2910
2911 error:
2912         return rc;
2913 }
2914
2915 /* JIRA 22088 */
2916 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2917 {
2918         struct hwrm_func_qcfg_input req = {0};
2919         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2920         uint16_t flags;
2921         int rc = 0;
2922
2923         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2924         req.fid = rte_cpu_to_le_16(0xffff);
2925
2926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2927
2928         HWRM_CHECK_RESULT();
2929
2930         /* Hard Coded.. 0xfff VLAN ID mask */
2931         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2932         flags = rte_le_to_cpu_16(resp->flags);
2933         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2934                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2935
2936         if (BNXT_VF(bp) &&
2937             !BNXT_VF_IS_TRUSTED(bp) &&
2938             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2939                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2940                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2941         } else if (BNXT_VF(bp) &&
2942                    BNXT_VF_IS_TRUSTED(bp) &&
2943                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2944                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2945                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2946         }
2947
2948         if (mtu)
2949                 *mtu = rte_le_to_cpu_16(resp->mtu);
2950
2951         switch (resp->port_partition_type) {
2952         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2953         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2954         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2955                 /* FALLTHROUGH */
2956                 bp->port_partition_type = resp->port_partition_type;
2957                 break;
2958         default:
2959                 bp->port_partition_type = 0;
2960                 break;
2961         }
2962
2963         HWRM_UNLOCK();
2964
2965         return rc;
2966 }
2967
2968 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2969                                    struct hwrm_func_qcaps_output *qcaps)
2970 {
2971         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2972         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2973                sizeof(qcaps->mac_address));
2974         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2975         qcaps->max_rx_rings = fcfg->num_rx_rings;
2976         qcaps->max_tx_rings = fcfg->num_tx_rings;
2977         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2978         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2979         qcaps->max_vfs = 0;
2980         qcaps->first_vf_id = 0;
2981         qcaps->max_vnics = fcfg->num_vnics;
2982         qcaps->max_decap_records = 0;
2983         qcaps->max_encap_records = 0;
2984         qcaps->max_tx_wm_flows = 0;
2985         qcaps->max_tx_em_flows = 0;
2986         qcaps->max_rx_wm_flows = 0;
2987         qcaps->max_rx_em_flows = 0;
2988         qcaps->max_flow_id = 0;
2989         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2990         qcaps->max_sp_tx_rings = 0;
2991         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2992 }
2993
2994 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2995 {
2996         struct hwrm_func_cfg_input req = {0};
2997         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2998         uint32_t enables;
2999         int rc;
3000
3001         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3002                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3003                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3004                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3005                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3006                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3007                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3008                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3009                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3010
3011         if (BNXT_HAS_RING_GRPS(bp)) {
3012                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3013                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3014         } else if (BNXT_HAS_NQ(bp)) {
3015                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3016                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3017         }
3018
3019         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3020         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3021         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3022         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3023         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3024         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3025         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3026         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3027         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3028         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3029         req.fid = rte_cpu_to_le_16(0xffff);
3030         req.enables = rte_cpu_to_le_32(enables);
3031
3032         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3033
3034         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3035
3036         HWRM_CHECK_RESULT();
3037         HWRM_UNLOCK();
3038
3039         return rc;
3040 }
3041
3042 static void populate_vf_func_cfg_req(struct bnxt *bp,
3043                                      struct hwrm_func_cfg_input *req,
3044                                      int num_vfs)
3045 {
3046         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3047                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3048                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3049                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3050                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3051                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3052                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3053                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3054                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3055                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3056
3057         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3058                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3059                                     BNXT_NUM_VLANS);
3060         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3061         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3062                                                 (num_vfs + 1));
3063         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3064         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3065                                                (num_vfs + 1));
3066         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3067         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3068         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3069         /* TODO: For now, do not support VMDq/RFS on VFs. */
3070         req->num_vnics = rte_cpu_to_le_16(1);
3071         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3072                                                  (num_vfs + 1));
3073 }
3074
3075 static void add_random_mac_if_needed(struct bnxt *bp,
3076                                      struct hwrm_func_cfg_input *cfg_req,
3077                                      int vf)
3078 {
3079         struct rte_ether_addr mac;
3080
3081         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3082                 return;
3083
3084         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3085                 cfg_req->enables |=
3086                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3087                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3088                 bp->pf.vf_info[vf].random_mac = true;
3089         } else {
3090                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3091                         RTE_ETHER_ADDR_LEN);
3092         }
3093 }
3094
3095 static void reserve_resources_from_vf(struct bnxt *bp,
3096                                       struct hwrm_func_cfg_input *cfg_req,
3097                                       int vf)
3098 {
3099         struct hwrm_func_qcaps_input req = {0};
3100         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3101         int rc;
3102
3103         /* Get the actual allocated values now */
3104         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3105         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3107
3108         if (rc) {
3109                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3110                 copy_func_cfg_to_qcaps(cfg_req, resp);
3111         } else if (resp->error_code) {
3112                 rc = rte_le_to_cpu_16(resp->error_code);
3113                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3114                 copy_func_cfg_to_qcaps(cfg_req, resp);
3115         }
3116
3117         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3118         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3119         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3120         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3121         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3122         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3123         /*
3124          * TODO: While not supporting VMDq with VFs, max_vnics is always
3125          * forced to 1 in this case
3126          */
3127         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3128         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3129
3130         HWRM_UNLOCK();
3131 }
3132
3133 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3134 {
3135         struct hwrm_func_qcfg_input req = {0};
3136         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3137         int rc;
3138
3139         /* Check for zero MAC address */
3140         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3141         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3143         HWRM_CHECK_RESULT();
3144         rc = rte_le_to_cpu_16(resp->vlan);
3145
3146         HWRM_UNLOCK();
3147
3148         return rc;
3149 }
3150
3151 static int update_pf_resource_max(struct bnxt *bp)
3152 {
3153         struct hwrm_func_qcfg_input req = {0};
3154         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3155         int rc;
3156
3157         /* And copy the allocated numbers into the pf struct */
3158         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3159         req.fid = rte_cpu_to_le_16(0xffff);
3160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3161         HWRM_CHECK_RESULT();
3162
3163         /* Only TX ring value reflects actual allocation? TODO */
3164         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3165         bp->pf.evb_mode = resp->evb_mode;
3166
3167         HWRM_UNLOCK();
3168
3169         return rc;
3170 }
3171
3172 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3173 {
3174         int rc;
3175
3176         if (!BNXT_PF(bp)) {
3177                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3178                 return -EINVAL;
3179         }
3180
3181         rc = bnxt_hwrm_func_qcaps(bp);
3182         if (rc)
3183                 return rc;
3184
3185         bp->pf.func_cfg_flags &=
3186                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3187                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3188         bp->pf.func_cfg_flags |=
3189                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3190         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3191         rc = __bnxt_hwrm_func_qcaps(bp);
3192         return rc;
3193 }
3194
3195 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3196 {
3197         struct hwrm_func_cfg_input req = {0};
3198         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3199         int i;
3200         size_t sz;
3201         int rc = 0;
3202         size_t req_buf_sz;
3203
3204         if (!BNXT_PF(bp)) {
3205                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3206                 return -EINVAL;
3207         }
3208
3209         rc = bnxt_hwrm_func_qcaps(bp);
3210
3211         if (rc)
3212                 return rc;
3213
3214         bp->pf.active_vfs = num_vfs;
3215
3216         /*
3217          * First, configure the PF to only use one TX ring.  This ensures that
3218          * there are enough rings for all VFs.
3219          *
3220          * If we don't do this, when we call func_alloc() later, we will lock
3221          * extra rings to the PF that won't be available during func_cfg() of
3222          * the VFs.
3223          *
3224          * This has been fixed with firmware versions above 20.6.54
3225          */
3226         bp->pf.func_cfg_flags &=
3227                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3228                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3229         bp->pf.func_cfg_flags |=
3230                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3231         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3232         if (rc)
3233                 return rc;
3234
3235         /*
3236          * Now, create and register a buffer to hold forwarded VF requests
3237          */
3238         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3239         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3240                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3241         if (bp->pf.vf_req_buf == NULL) {
3242                 rc = -ENOMEM;
3243                 goto error_free;
3244         }
3245         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3246                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3247         for (i = 0; i < num_vfs; i++)
3248                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3249                                         (i * HWRM_MAX_REQ_LEN);
3250
3251         rc = bnxt_hwrm_func_buf_rgtr(bp);
3252         if (rc)
3253                 goto error_free;
3254
3255         populate_vf_func_cfg_req(bp, &req, num_vfs);
3256
3257         bp->pf.active_vfs = 0;
3258         for (i = 0; i < num_vfs; i++) {
3259                 add_random_mac_if_needed(bp, &req, i);
3260
3261                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3262                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3263                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3264                 rc = bnxt_hwrm_send_message(bp,
3265                                             &req,
3266                                             sizeof(req),
3267                                             BNXT_USE_CHIMP_MB);
3268
3269                 /* Clear enable flag for next pass */
3270                 req.enables &= ~rte_cpu_to_le_32(
3271                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3272
3273                 if (rc || resp->error_code) {
3274                         PMD_DRV_LOG(ERR,
3275                                 "Failed to initizlie VF %d\n", i);
3276                         PMD_DRV_LOG(ERR,
3277                                 "Not all VFs available. (%d, %d)\n",
3278                                 rc, resp->error_code);
3279                         HWRM_UNLOCK();
3280                         break;
3281                 }
3282
3283                 HWRM_UNLOCK();
3284
3285                 reserve_resources_from_vf(bp, &req, i);
3286                 bp->pf.active_vfs++;
3287                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3288         }
3289
3290         /*
3291          * Now configure the PF to use "the rest" of the resources
3292          * We're using STD_TX_RING_MODE here though which will limit the TX
3293          * rings.  This will allow QoS to function properly.  Not setting this
3294          * will cause PF rings to break bandwidth settings.
3295          */
3296         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3297         if (rc)
3298                 goto error_free;
3299
3300         rc = update_pf_resource_max(bp);
3301         if (rc)
3302                 goto error_free;
3303
3304         return rc;
3305
3306 error_free:
3307         bnxt_hwrm_func_buf_unrgtr(bp);
3308         return rc;
3309 }
3310
3311 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3312 {
3313         struct hwrm_func_cfg_input req = {0};
3314         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3315         int rc;
3316
3317         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3318
3319         req.fid = rte_cpu_to_le_16(0xffff);
3320         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3321         req.evb_mode = bp->pf.evb_mode;
3322
3323         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3324         HWRM_CHECK_RESULT();
3325         HWRM_UNLOCK();
3326
3327         return rc;
3328 }
3329
3330 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3331                                 uint8_t tunnel_type)
3332 {
3333         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3334         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3335         int rc = 0;
3336
3337         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3338         req.tunnel_type = tunnel_type;
3339         req.tunnel_dst_port_val = port;
3340         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3341         HWRM_CHECK_RESULT();
3342
3343         switch (tunnel_type) {
3344         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3345                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3346                 bp->vxlan_port = port;
3347                 break;
3348         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3349                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3350                 bp->geneve_port = port;
3351                 break;
3352         default:
3353                 break;
3354         }
3355
3356         HWRM_UNLOCK();
3357
3358         return rc;
3359 }
3360
3361 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3362                                 uint8_t tunnel_type)
3363 {
3364         struct hwrm_tunnel_dst_port_free_input req = {0};
3365         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3366         int rc = 0;
3367
3368         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3369
3370         req.tunnel_type = tunnel_type;
3371         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373
3374         HWRM_CHECK_RESULT();
3375         HWRM_UNLOCK();
3376
3377         return rc;
3378 }
3379
3380 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3381                                         uint32_t flags)
3382 {
3383         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3384         struct hwrm_func_cfg_input req = {0};
3385         int rc;
3386
3387         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3388
3389         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3390         req.flags = rte_cpu_to_le_32(flags);
3391         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3392
3393         HWRM_CHECK_RESULT();
3394         HWRM_UNLOCK();
3395
3396         return rc;
3397 }
3398
3399 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3400 {
3401         uint32_t *flag = flagp;
3402
3403         vnic->flags = *flag;
3404 }
3405
3406 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3407 {
3408         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3409 }
3410
3411 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3412 {
3413         int rc = 0;
3414         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3415         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3416
3417         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3418
3419         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3420         req.req_buf_page_size = rte_cpu_to_le_16(
3421                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3422         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3423         req.req_buf_page_addr0 =
3424                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3425         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3426                 PMD_DRV_LOG(ERR,
3427                         "unable to map buffer address to physical memory\n");
3428                 return -ENOMEM;
3429         }
3430
3431         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3432
3433         HWRM_CHECK_RESULT();
3434         HWRM_UNLOCK();
3435
3436         return rc;
3437 }
3438
3439 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3440 {
3441         int rc = 0;
3442         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3443         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3444
3445         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3446                 return 0;
3447
3448         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3449
3450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3451
3452         HWRM_CHECK_RESULT();
3453         HWRM_UNLOCK();
3454
3455         return rc;
3456 }
3457
3458 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3459 {
3460         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3461         struct hwrm_func_cfg_input req = {0};
3462         int rc;
3463
3464         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3465
3466         req.fid = rte_cpu_to_le_16(0xffff);
3467         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3468         req.enables = rte_cpu_to_le_32(
3469                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3470         req.async_event_cr = rte_cpu_to_le_16(
3471                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3472         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3473
3474         HWRM_CHECK_RESULT();
3475         HWRM_UNLOCK();
3476
3477         return rc;
3478 }
3479
3480 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3481 {
3482         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3483         struct hwrm_func_vf_cfg_input req = {0};
3484         int rc;
3485
3486         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3487
3488         req.enables = rte_cpu_to_le_32(
3489                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3490         req.async_event_cr = rte_cpu_to_le_16(
3491                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493
3494         HWRM_CHECK_RESULT();
3495         HWRM_UNLOCK();
3496
3497         return rc;
3498 }
3499
3500 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3501 {
3502         struct hwrm_func_cfg_input req = {0};
3503         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3504         uint16_t dflt_vlan, fid;
3505         uint32_t func_cfg_flags;
3506         int rc = 0;
3507
3508         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3509
3510         if (is_vf) {
3511                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3512                 fid = bp->pf.vf_info[vf].fid;
3513                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3514         } else {
3515                 fid = rte_cpu_to_le_16(0xffff);
3516                 func_cfg_flags = bp->pf.func_cfg_flags;
3517                 dflt_vlan = bp->vlan;
3518         }
3519
3520         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3521         req.fid = rte_cpu_to_le_16(fid);
3522         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3523         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3524
3525         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3526
3527         HWRM_CHECK_RESULT();
3528         HWRM_UNLOCK();
3529
3530         return rc;
3531 }
3532
3533 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3534                         uint16_t max_bw, uint16_t enables)
3535 {
3536         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3537         struct hwrm_func_cfg_input req = {0};
3538         int rc;
3539
3540         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3541
3542         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3543         req.enables |= rte_cpu_to_le_32(enables);
3544         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3545         req.max_bw = rte_cpu_to_le_32(max_bw);
3546         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3547
3548         HWRM_CHECK_RESULT();
3549         HWRM_UNLOCK();
3550
3551         return rc;
3552 }
3553
3554 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3555 {
3556         struct hwrm_func_cfg_input req = {0};
3557         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3558         int rc = 0;
3559
3560         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3561
3562         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3563         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3564         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3565         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3566
3567         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3568
3569         HWRM_CHECK_RESULT();
3570         HWRM_UNLOCK();
3571
3572         return rc;
3573 }
3574
3575 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3576 {
3577         int rc;
3578
3579         if (BNXT_PF(bp))
3580                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3581         else
3582                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3583
3584         return rc;
3585 }
3586
3587 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3588                               void *encaped, size_t ec_size)
3589 {
3590         int rc = 0;
3591         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3592         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3593
3594         if (ec_size > sizeof(req.encap_request))
3595                 return -1;
3596
3597         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3598
3599         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3600         memcpy(req.encap_request, encaped, ec_size);
3601
3602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3603
3604         HWRM_CHECK_RESULT();
3605         HWRM_UNLOCK();
3606
3607         return rc;
3608 }
3609
3610 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3611                                        struct rte_ether_addr *mac)
3612 {
3613         struct hwrm_func_qcfg_input req = {0};
3614         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3615         int rc;
3616
3617         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3618
3619         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3621
3622         HWRM_CHECK_RESULT();
3623
3624         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3625
3626         HWRM_UNLOCK();
3627
3628         return rc;
3629 }
3630
3631 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3632                             void *encaped, size_t ec_size)
3633 {
3634         int rc = 0;
3635         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3636         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3637
3638         if (ec_size > sizeof(req.encap_request))
3639                 return -1;
3640
3641         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3642
3643         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3644         memcpy(req.encap_request, encaped, ec_size);
3645
3646         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3647
3648         HWRM_CHECK_RESULT();
3649         HWRM_UNLOCK();
3650
3651         return rc;
3652 }
3653
3654 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3655                          struct rte_eth_stats *stats, uint8_t rx)
3656 {
3657         int rc = 0;
3658         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3659         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3660
3661         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3662
3663         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3664
3665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3666
3667         HWRM_CHECK_RESULT();
3668
3669         if (rx) {
3670                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3671                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3672                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3673                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3674                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3675                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3676                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3677                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3678         } else {
3679                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3680                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3681                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3682                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3683                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3684                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3685         }
3686
3687         HWRM_UNLOCK();
3688
3689         return rc;
3690 }
3691
3692 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3693 {
3694         struct hwrm_port_qstats_input req = {0};
3695         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3696         struct bnxt_pf_info *pf = &bp->pf;
3697         int rc;
3698
3699         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3700
3701         req.port_id = rte_cpu_to_le_16(pf->port_id);
3702         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3703         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3704         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3705
3706         HWRM_CHECK_RESULT();
3707         HWRM_UNLOCK();
3708
3709         return rc;
3710 }
3711
3712 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3713 {
3714         struct hwrm_port_clr_stats_input req = {0};
3715         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3716         struct bnxt_pf_info *pf = &bp->pf;
3717         int rc;
3718
3719         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3720         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3721             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3722                 return 0;
3723
3724         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3725
3726         req.port_id = rte_cpu_to_le_16(pf->port_id);
3727         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3728
3729         HWRM_CHECK_RESULT();
3730         HWRM_UNLOCK();
3731
3732         return rc;
3733 }
3734
3735 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3736 {
3737         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3738         struct hwrm_port_led_qcaps_input req = {0};
3739         int rc;
3740
3741         if (BNXT_VF(bp))
3742                 return 0;
3743
3744         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3745         req.port_id = bp->pf.port_id;
3746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3747
3748         HWRM_CHECK_RESULT();
3749
3750         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3751                 unsigned int i;
3752
3753                 bp->num_leds = resp->num_leds;
3754                 memcpy(bp->leds, &resp->led0_id,
3755                         sizeof(bp->leds[0]) * bp->num_leds);
3756                 for (i = 0; i < bp->num_leds; i++) {
3757                         struct bnxt_led_info *led = &bp->leds[i];
3758
3759                         uint16_t caps = led->led_state_caps;
3760
3761                         if (!led->led_group_id ||
3762                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3763                                 bp->num_leds = 0;
3764                                 break;
3765                         }
3766                 }
3767         }
3768
3769         HWRM_UNLOCK();
3770
3771         return rc;
3772 }
3773
3774 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3775 {
3776         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3777         struct hwrm_port_led_cfg_input req = {0};
3778         struct bnxt_led_cfg *led_cfg;
3779         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3780         uint16_t duration = 0;
3781         int rc, i;
3782
3783         if (!bp->num_leds || BNXT_VF(bp))
3784                 return -EOPNOTSUPP;
3785
3786         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3787
3788         if (led_on) {
3789                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3790                 duration = rte_cpu_to_le_16(500);
3791         }
3792         req.port_id = bp->pf.port_id;
3793         req.num_leds = bp->num_leds;
3794         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3795         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3796                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3797                 led_cfg->led_id = bp->leds[i].led_id;
3798                 led_cfg->led_state = led_state;
3799                 led_cfg->led_blink_on = duration;
3800                 led_cfg->led_blink_off = duration;
3801                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3802         }
3803
3804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3805
3806         HWRM_CHECK_RESULT();
3807         HWRM_UNLOCK();
3808
3809         return rc;
3810 }
3811
3812 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3813                                uint32_t *length)
3814 {
3815         int rc;
3816         struct hwrm_nvm_get_dir_info_input req = {0};
3817         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3818
3819         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3820
3821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3822
3823         HWRM_CHECK_RESULT();
3824
3825         *entries = rte_le_to_cpu_32(resp->entries);
3826         *length = rte_le_to_cpu_32(resp->entry_length);
3827
3828         HWRM_UNLOCK();
3829         return rc;
3830 }
3831
3832 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3833 {
3834         int rc;
3835         uint32_t dir_entries;
3836         uint32_t entry_length;
3837         uint8_t *buf;
3838         size_t buflen;
3839         rte_iova_t dma_handle;
3840         struct hwrm_nvm_get_dir_entries_input req = {0};
3841         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3842
3843         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3844         if (rc != 0)
3845                 return rc;
3846
3847         *data++ = dir_entries;
3848         *data++ = entry_length;
3849         len -= 2;
3850         memset(data, 0xff, len);
3851
3852         buflen = dir_entries * entry_length;
3853         buf = rte_malloc("nvm_dir", buflen, 0);
3854         rte_mem_lock_page(buf);
3855         if (buf == NULL)
3856                 return -ENOMEM;
3857         dma_handle = rte_mem_virt2iova(buf);
3858         if (dma_handle == RTE_BAD_IOVA) {
3859                 PMD_DRV_LOG(ERR,
3860                         "unable to map response address to physical memory\n");
3861                 return -ENOMEM;
3862         }
3863         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3864         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3866
3867         if (rc == 0)
3868                 memcpy(data, buf, len > buflen ? buflen : len);
3869
3870         rte_free(buf);
3871         HWRM_CHECK_RESULT();
3872         HWRM_UNLOCK();
3873
3874         return rc;
3875 }
3876
3877 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3878                              uint32_t offset, uint32_t length,
3879                              uint8_t *data)
3880 {
3881         int rc;
3882         uint8_t *buf;
3883         rte_iova_t dma_handle;
3884         struct hwrm_nvm_read_input req = {0};
3885         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3886
3887         buf = rte_malloc("nvm_item", length, 0);
3888         rte_mem_lock_page(buf);
3889         if (!buf)
3890                 return -ENOMEM;
3891
3892         dma_handle = rte_mem_virt2iova(buf);
3893         if (dma_handle == RTE_BAD_IOVA) {
3894                 PMD_DRV_LOG(ERR,
3895                         "unable to map response address to physical memory\n");
3896                 return -ENOMEM;
3897         }
3898         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3899         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3900         req.dir_idx = rte_cpu_to_le_16(index);
3901         req.offset = rte_cpu_to_le_32(offset);
3902         req.len = rte_cpu_to_le_32(length);
3903         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3904         if (rc == 0)
3905                 memcpy(data, buf, length);
3906
3907         rte_free(buf);
3908         HWRM_CHECK_RESULT();
3909         HWRM_UNLOCK();
3910
3911         return rc;
3912 }
3913
3914 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3915 {
3916         int rc;
3917         struct hwrm_nvm_erase_dir_entry_input req = {0};
3918         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3919
3920         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3921         req.dir_idx = rte_cpu_to_le_16(index);
3922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3923         HWRM_CHECK_RESULT();
3924         HWRM_UNLOCK();
3925
3926         return rc;
3927 }
3928
3929
3930 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3931                           uint16_t dir_ordinal, uint16_t dir_ext,
3932                           uint16_t dir_attr, const uint8_t *data,
3933                           size_t data_len)
3934 {
3935         int rc;
3936         struct hwrm_nvm_write_input req = {0};
3937         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3938         rte_iova_t dma_handle;
3939         uint8_t *buf;
3940
3941         buf = rte_malloc("nvm_write", data_len, 0);
3942         rte_mem_lock_page(buf);
3943         if (!buf)
3944                 return -ENOMEM;
3945
3946         dma_handle = rte_mem_virt2iova(buf);
3947         if (dma_handle == RTE_BAD_IOVA) {
3948                 PMD_DRV_LOG(ERR,
3949                         "unable to map response address to physical memory\n");
3950                 return -ENOMEM;
3951         }
3952         memcpy(buf, data, data_len);
3953
3954         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3955
3956         req.dir_type = rte_cpu_to_le_16(dir_type);
3957         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3958         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3959         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3960         req.dir_data_length = rte_cpu_to_le_32(data_len);
3961         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3962
3963         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3964
3965         rte_free(buf);
3966         HWRM_CHECK_RESULT();
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 static void
3973 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3974 {
3975         uint32_t *count = cbdata;
3976
3977         *count = *count + 1;
3978 }
3979
3980 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3981                                      struct bnxt_vnic_info *vnic __rte_unused)
3982 {
3983         return 0;
3984 }
3985
3986 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3987 {
3988         uint32_t count = 0;
3989
3990         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3991             &count, bnxt_vnic_count_hwrm_stub);
3992
3993         return count;
3994 }
3995
3996 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3997                                         uint16_t *vnic_ids)
3998 {
3999         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4000         struct hwrm_func_vf_vnic_ids_query_output *resp =
4001                                                 bp->hwrm_cmd_resp_addr;
4002         int rc;
4003
4004         /* First query all VNIC ids */
4005         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4006
4007         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4008         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4009         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
4010
4011         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4012                 HWRM_UNLOCK();
4013                 PMD_DRV_LOG(ERR,
4014                 "unable to map VNIC ID table address to physical memory\n");
4015                 return -ENOMEM;
4016         }
4017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4018         HWRM_CHECK_RESULT();
4019         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4020
4021         HWRM_UNLOCK();
4022
4023         return rc;
4024 }
4025
4026 /*
4027  * This function queries the VNIC IDs  for a specified VF. It then calls
4028  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4029  * Then it calls the hwrm_cb function to program this new vnic configuration.
4030  */
4031 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4032         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4033         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4034 {
4035         struct bnxt_vnic_info vnic;
4036         int rc = 0;
4037         int i, num_vnic_ids;
4038         uint16_t *vnic_ids;
4039         size_t vnic_id_sz;
4040         size_t sz;
4041
4042         /* First query all VNIC ids */
4043         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4044         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4045                         RTE_CACHE_LINE_SIZE);
4046         if (vnic_ids == NULL)
4047                 return -ENOMEM;
4048
4049         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4050                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4051
4052         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4053
4054         if (num_vnic_ids < 0)
4055                 return num_vnic_ids;
4056
4057         /* Retrieve VNIC, update bd_stall then update */
4058
4059         for (i = 0; i < num_vnic_ids; i++) {
4060                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4061                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4062                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4063                 if (rc)
4064                         break;
4065                 if (vnic.mru <= 4)      /* Indicates unallocated */
4066                         continue;
4067
4068                 vnic_cb(&vnic, cbdata);
4069
4070                 rc = hwrm_cb(bp, &vnic);
4071                 if (rc)
4072                         break;
4073         }
4074
4075         rte_free(vnic_ids);
4076
4077         return rc;
4078 }
4079
4080 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4081                                               bool on)
4082 {
4083         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4084         struct hwrm_func_cfg_input req = {0};
4085         int rc;
4086
4087         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4088
4089         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4090         req.enables |= rte_cpu_to_le_32(
4091                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4092         req.vlan_antispoof_mode = on ?
4093                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4094                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096
4097         HWRM_CHECK_RESULT();
4098         HWRM_UNLOCK();
4099
4100         return rc;
4101 }
4102
4103 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4104 {
4105         struct bnxt_vnic_info vnic;
4106         uint16_t *vnic_ids;
4107         size_t vnic_id_sz;
4108         int num_vnic_ids, i;
4109         size_t sz;
4110         int rc;
4111
4112         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4113         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4114                         RTE_CACHE_LINE_SIZE);
4115         if (vnic_ids == NULL)
4116                 return -ENOMEM;
4117
4118         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4119                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4120
4121         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4122         if (rc <= 0)
4123                 goto exit;
4124         num_vnic_ids = rc;
4125
4126         /*
4127          * Loop through to find the default VNIC ID.
4128          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4129          * by sending the hwrm_func_qcfg command to the firmware.
4130          */
4131         for (i = 0; i < num_vnic_ids; i++) {
4132                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4133                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4134                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4135                                         bp->pf.first_vf_id + vf);
4136                 if (rc)
4137                         goto exit;
4138                 if (vnic.func_default) {
4139                         rte_free(vnic_ids);
4140                         return vnic.fw_vnic_id;
4141                 }
4142         }
4143         /* Could not find a default VNIC. */
4144         PMD_DRV_LOG(ERR, "No default VNIC\n");
4145 exit:
4146         rte_free(vnic_ids);
4147         return rc;
4148 }
4149
4150 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4151                          uint16_t dst_id,
4152                          struct bnxt_filter_info *filter)
4153 {
4154         int rc = 0;
4155         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4156         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4157         uint32_t enables = 0;
4158
4159         if (filter->fw_em_filter_id != UINT64_MAX)
4160                 bnxt_hwrm_clear_em_filter(bp, filter);
4161
4162         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4163
4164         req.flags = rte_cpu_to_le_32(filter->flags);
4165
4166         enables = filter->enables |
4167               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4168         req.dst_id = rte_cpu_to_le_16(dst_id);
4169
4170         if (filter->ip_addr_type) {
4171                 req.ip_addr_type = filter->ip_addr_type;
4172                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4173         }
4174         if (enables &
4175             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4176                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4177         if (enables &
4178             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4179                 memcpy(req.src_macaddr, filter->src_macaddr,
4180                        RTE_ETHER_ADDR_LEN);
4181         if (enables &
4182             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4183                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4184                        RTE_ETHER_ADDR_LEN);
4185         if (enables &
4186             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4187                 req.ovlan_vid = filter->l2_ovlan;
4188         if (enables &
4189             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4190                 req.ivlan_vid = filter->l2_ivlan;
4191         if (enables &
4192             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4193                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4194         if (enables &
4195             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4196                 req.ip_protocol = filter->ip_protocol;
4197         if (enables &
4198             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4199                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4200         if (enables &
4201             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4202                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4203         if (enables &
4204             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4205                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4206         if (enables &
4207             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4208                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4209         if (enables &
4210             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4211                 req.mirror_vnic_id = filter->mirror_vnic_id;
4212
4213         req.enables = rte_cpu_to_le_32(enables);
4214
4215         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4216
4217         HWRM_CHECK_RESULT();
4218
4219         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4220         HWRM_UNLOCK();
4221
4222         return rc;
4223 }
4224
4225 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4226 {
4227         int rc = 0;
4228         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4229         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4230
4231         if (filter->fw_em_filter_id == UINT64_MAX)
4232                 return 0;
4233
4234         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4235
4236         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4237
4238         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4239
4240         HWRM_CHECK_RESULT();
4241         HWRM_UNLOCK();
4242
4243         filter->fw_em_filter_id = UINT64_MAX;
4244         filter->fw_l2_filter_id = UINT64_MAX;
4245
4246         return 0;
4247 }
4248
4249 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4250                          uint16_t dst_id,
4251                          struct bnxt_filter_info *filter)
4252 {
4253         int rc = 0;
4254         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4255         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4256                                                 bp->hwrm_cmd_resp_addr;
4257         uint32_t enables = 0;
4258
4259         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4260                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4261
4262         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4263
4264         req.flags = rte_cpu_to_le_32(filter->flags);
4265
4266         enables = filter->enables |
4267               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4268         req.dst_id = rte_cpu_to_le_16(dst_id);
4269
4270         if (filter->ip_addr_type) {
4271                 req.ip_addr_type = filter->ip_addr_type;
4272                 enables |=
4273                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4274         }
4275         if (enables &
4276             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4277                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4278         if (enables &
4279             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4280                 memcpy(req.src_macaddr, filter->src_macaddr,
4281                        RTE_ETHER_ADDR_LEN);
4282         if (enables &
4283             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4284                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4285         if (enables &
4286             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4287                 req.ip_protocol = filter->ip_protocol;
4288         if (enables &
4289             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4290                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4291         if (enables &
4292             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4293                 req.src_ipaddr_mask[0] =
4294                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4295         if (enables &
4296             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4297                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4298         if (enables &
4299             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4300                 req.dst_ipaddr_mask[0] =
4301                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4302         if (enables &
4303             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4304                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4305         if (enables &
4306             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4307                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4308         if (enables &
4309             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4310                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4311         if (enables &
4312             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4313                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4314         if (enables &
4315             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4316                 req.mirror_vnic_id = filter->mirror_vnic_id;
4317
4318         req.enables = rte_cpu_to_le_32(enables);
4319
4320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4321
4322         HWRM_CHECK_RESULT();
4323
4324         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4325         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4326         HWRM_UNLOCK();
4327
4328         return rc;
4329 }
4330
4331 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4332                                 struct bnxt_filter_info *filter)
4333 {
4334         int rc = 0;
4335         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4336         struct hwrm_cfa_ntuple_filter_free_output *resp =
4337                                                 bp->hwrm_cmd_resp_addr;
4338
4339         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4340                 return 0;
4341
4342         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4343
4344         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4345
4346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4347
4348         HWRM_CHECK_RESULT();
4349         HWRM_UNLOCK();
4350
4351         filter->fw_ntuple_filter_id = UINT64_MAX;
4352
4353         return 0;
4354 }
4355
4356 static int
4357 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4358 {
4359         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4360         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4361         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4362         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4363         uint16_t *ring_tbl = vnic->rss_table;
4364         int nr_ctxs = vnic->num_lb_ctxts;
4365         int max_rings = bp->rx_nr_rings;
4366         int i, j, k, cnt;
4367         int rc = 0;
4368
4369         for (i = 0, k = 0; i < nr_ctxs; i++) {
4370                 struct bnxt_rx_ring_info *rxr;
4371                 struct bnxt_cp_ring_info *cpr;
4372
4373                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4374
4375                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4376                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4377                 req.hash_mode_flags = vnic->hash_mode;
4378
4379                 req.ring_grp_tbl_addr =
4380                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4381                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4382                                      2 * sizeof(*ring_tbl));
4383                 req.hash_key_tbl_addr =
4384                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4385
4386                 req.ring_table_pair_index = i;
4387                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4388
4389                 for (j = 0; j < 64; j++) {
4390                         uint16_t ring_id;
4391
4392                         /* Find next active ring. */
4393                         for (cnt = 0; cnt < max_rings; cnt++) {
4394                                 if (rx_queue_state[k] !=
4395                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4396                                         break;
4397                                 if (++k == max_rings)
4398                                         k = 0;
4399                         }
4400
4401                         /* Return if no rings are active. */
4402                         if (cnt == max_rings) {
4403                                 HWRM_UNLOCK();
4404                                 return 0;
4405                         }
4406
4407                         /* Add rx/cp ring pair to RSS table. */
4408                         rxr = rxqs[k]->rx_ring;
4409                         cpr = rxqs[k]->cp_ring;
4410
4411                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4412                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4413                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4414                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4415
4416                         if (++k == max_rings)
4417                                 k = 0;
4418                 }
4419                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4420                                             BNXT_USE_CHIMP_MB);
4421
4422                 HWRM_CHECK_RESULT();
4423                 HWRM_UNLOCK();
4424         }
4425
4426         return rc;
4427 }
4428
4429 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4430 {
4431         unsigned int rss_idx, fw_idx, i;
4432
4433         if (!(vnic->rss_table && vnic->hash_type))
4434                 return 0;
4435
4436         if (BNXT_CHIP_THOR(bp))
4437                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4438
4439         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4440                 return 0;
4441
4442         if (vnic->rss_table && vnic->hash_type) {
4443                 /*
4444                  * Fill the RSS hash & redirection table with
4445                  * ring group ids for all VNICs
4446                  */
4447                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4448                         rss_idx++, fw_idx++) {
4449                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4450                                 fw_idx %= bp->rx_cp_nr_rings;
4451                                 if (vnic->fw_grp_ids[fw_idx] !=
4452                                     INVALID_HW_RING_ID)
4453                                         break;
4454                                 fw_idx++;
4455                         }
4456                         if (i == bp->rx_cp_nr_rings)
4457                                 return 0;
4458                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4459                 }
4460                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4461         }
4462
4463         return 0;
4464 }
4465
4466 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4467         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4468 {
4469         uint16_t flags;
4470
4471         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4472
4473         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4474         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4475
4476         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4477         req->num_cmpl_dma_aggr_during_int =
4478                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4479
4480         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4481
4482         /* min timer set to 1/2 of interrupt timer */
4483         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4484
4485         /* buf timer set to 1/4 of interrupt timer */
4486         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4487
4488         req->cmpl_aggr_dma_tmr_during_int =
4489                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4490
4491         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4492                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4493         req->flags = rte_cpu_to_le_16(flags);
4494 }
4495
4496 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4497                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4498 {
4499         struct hwrm_ring_aggint_qcaps_input req = {0};
4500         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4501         uint32_t enables;
4502         uint16_t flags;
4503         int rc;
4504
4505         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4507         HWRM_CHECK_RESULT();
4508
4509         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4510         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4511
4512         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4513                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4514         agg_req->flags = rte_cpu_to_le_16(flags);
4515         enables =
4516          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4517          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4518         agg_req->enables = rte_cpu_to_le_32(enables);
4519
4520         HWRM_UNLOCK();
4521         return rc;
4522 }
4523
4524 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4525                         struct bnxt_coal *coal, uint16_t ring_id)
4526 {
4527         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4528         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4529                                                 bp->hwrm_cmd_resp_addr;
4530         int rc;
4531
4532         /* Set ring coalesce parameters only for 100G NICs */
4533         if (BNXT_CHIP_THOR(bp)) {
4534                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4535                         return -1;
4536         } else if (bnxt_stratus_device(bp)) {
4537                 bnxt_hwrm_set_coal_params(coal, &req);
4538         } else {
4539                 return 0;
4540         }
4541
4542         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4543         req.ring_id = rte_cpu_to_le_16(ring_id);
4544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4545         HWRM_CHECK_RESULT();
4546         HWRM_UNLOCK();
4547         return 0;
4548 }
4549
4550 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4551 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4552 {
4553         struct hwrm_func_backing_store_qcaps_input req = {0};
4554         struct hwrm_func_backing_store_qcaps_output *resp =
4555                 bp->hwrm_cmd_resp_addr;
4556         struct bnxt_ctx_pg_info *ctx_pg;
4557         struct bnxt_ctx_mem_info *ctx;
4558         int total_alloc_len;
4559         int rc, i;
4560
4561         if (!BNXT_CHIP_THOR(bp) ||
4562             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4563             BNXT_VF(bp) ||
4564             bp->ctx)
4565                 return 0;
4566
4567         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4569         HWRM_CHECK_RESULT_SILENT();
4570
4571         total_alloc_len = sizeof(*ctx);
4572         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4573                           RTE_CACHE_LINE_SIZE);
4574         if (!ctx) {
4575                 rc = -ENOMEM;
4576                 goto ctx_err;
4577         }
4578
4579         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4580                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4581                             RTE_CACHE_LINE_SIZE);
4582         if (!ctx_pg) {
4583                 rc = -ENOMEM;
4584                 goto ctx_err;
4585         }
4586         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4587                 ctx->tqm_mem[i] = ctx_pg;
4588
4589         bp->ctx = ctx;
4590         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4591         ctx->qp_min_qp1_entries =
4592                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4593         ctx->qp_max_l2_entries =
4594                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4595         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4596         ctx->srq_max_l2_entries =
4597                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4598         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4599         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4600         ctx->cq_max_l2_entries =
4601                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4602         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4603         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4604         ctx->vnic_max_vnic_entries =
4605                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4606         ctx->vnic_max_ring_table_entries =
4607                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4608         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4609         ctx->stat_max_entries =
4610                 rte_le_to_cpu_32(resp->stat_max_entries);
4611         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4612         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4613         ctx->tqm_min_entries_per_ring =
4614                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4615         ctx->tqm_max_entries_per_ring =
4616                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4617         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4618         if (!ctx->tqm_entries_multiple)
4619                 ctx->tqm_entries_multiple = 1;
4620         ctx->mrav_max_entries =
4621                 rte_le_to_cpu_32(resp->mrav_max_entries);
4622         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4623         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4624         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4625 ctx_err:
4626         HWRM_UNLOCK();
4627         return rc;
4628 }
4629
4630 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4631 {
4632         struct hwrm_func_backing_store_cfg_input req = {0};
4633         struct hwrm_func_backing_store_cfg_output *resp =
4634                 bp->hwrm_cmd_resp_addr;
4635         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4636         struct bnxt_ctx_pg_info *ctx_pg;
4637         uint32_t *num_entries;
4638         uint64_t *pg_dir;
4639         uint8_t *pg_attr;
4640         uint32_t ena;
4641         int i, rc;
4642
4643         if (!ctx)
4644                 return 0;
4645
4646         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4647         req.enables = rte_cpu_to_le_32(enables);
4648
4649         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4650                 ctx_pg = &ctx->qp_mem;
4651                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4652                 req.qp_num_qp1_entries =
4653                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4654                 req.qp_num_l2_entries =
4655                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4656                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4657                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4658                                       &req.qpc_pg_size_qpc_lvl,
4659                                       &req.qpc_page_dir);
4660         }
4661
4662         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4663                 ctx_pg = &ctx->srq_mem;
4664                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4665                 req.srq_num_l2_entries =
4666                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4667                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4668                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4669                                       &req.srq_pg_size_srq_lvl,
4670                                       &req.srq_page_dir);
4671         }
4672
4673         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4674                 ctx_pg = &ctx->cq_mem;
4675                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4676                 req.cq_num_l2_entries =
4677                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4678                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4679                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4680                                       &req.cq_pg_size_cq_lvl,
4681                                       &req.cq_page_dir);
4682         }
4683
4684         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4685                 ctx_pg = &ctx->vnic_mem;
4686                 req.vnic_num_vnic_entries =
4687                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4688                 req.vnic_num_ring_table_entries =
4689                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4690                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4691                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4692                                       &req.vnic_pg_size_vnic_lvl,
4693                                       &req.vnic_page_dir);
4694         }
4695
4696         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4697                 ctx_pg = &ctx->stat_mem;
4698                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4699                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4700                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4701                                       &req.stat_pg_size_stat_lvl,
4702                                       &req.stat_page_dir);
4703         }
4704
4705         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4706         num_entries = &req.tqm_sp_num_entries;
4707         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4708         pg_dir = &req.tqm_sp_page_dir;
4709         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4710         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4711                 if (!(enables & ena))
4712                         continue;
4713
4714                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4715
4716                 ctx_pg = ctx->tqm_mem[i];
4717                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4718                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4719         }
4720
4721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4722         HWRM_CHECK_RESULT();
4723         HWRM_UNLOCK();
4724
4725         return rc;
4726 }
4727
4728 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4729 {
4730         struct hwrm_port_qstats_ext_input req = {0};
4731         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4732         struct bnxt_pf_info *pf = &bp->pf;
4733         int rc;
4734
4735         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4736               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4737                 return 0;
4738
4739         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4740
4741         req.port_id = rte_cpu_to_le_16(pf->port_id);
4742         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4743                 req.tx_stat_host_addr =
4744                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4745                 req.tx_stat_size =
4746                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4747         }
4748         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4749                 req.rx_stat_host_addr =
4750                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4751                 req.rx_stat_size =
4752                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4753         }
4754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755
4756         if (rc) {
4757                 bp->fw_rx_port_stats_ext_size = 0;
4758                 bp->fw_tx_port_stats_ext_size = 0;
4759         } else {
4760                 bp->fw_rx_port_stats_ext_size =
4761                         rte_le_to_cpu_16(resp->rx_stat_size);
4762                 bp->fw_tx_port_stats_ext_size =
4763                         rte_le_to_cpu_16(resp->tx_stat_size);
4764         }
4765
4766         HWRM_CHECK_RESULT();
4767         HWRM_UNLOCK();
4768
4769         return rc;
4770 }
4771
4772 int
4773 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4774 {
4775         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4776         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4777                 bp->hwrm_cmd_resp_addr;
4778         int rc = 0;
4779
4780         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4781         req.tunnel_type = type;
4782         req.dest_fid = bp->fw_fid;
4783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4784         HWRM_CHECK_RESULT();
4785
4786         HWRM_UNLOCK();
4787
4788         return rc;
4789 }
4790
4791 int
4792 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4793 {
4794         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4795         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4796                 bp->hwrm_cmd_resp_addr;
4797         int rc = 0;
4798
4799         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4800         req.tunnel_type = type;
4801         req.dest_fid = bp->fw_fid;
4802         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4803         HWRM_CHECK_RESULT();
4804
4805         HWRM_UNLOCK();
4806
4807         return rc;
4808 }
4809
4810 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4811 {
4812         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4813         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4814                 bp->hwrm_cmd_resp_addr;
4815         int rc = 0;
4816
4817         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4818         req.src_fid = bp->fw_fid;
4819         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4820         HWRM_CHECK_RESULT();
4821
4822         if (type)
4823                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4824
4825         HWRM_UNLOCK();
4826
4827         return rc;
4828 }
4829
4830 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4831                                    uint16_t *dst_fid)
4832 {
4833         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4834         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4835                 bp->hwrm_cmd_resp_addr;
4836         int rc = 0;
4837
4838         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4839         req.src_fid = bp->fw_fid;
4840         req.tunnel_type = tun_type;
4841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4842         HWRM_CHECK_RESULT();
4843
4844         if (dst_fid)
4845                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4846
4847         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4848
4849         HWRM_UNLOCK();
4850
4851         return rc;
4852 }
4853
4854 int bnxt_hwrm_set_mac(struct bnxt *bp)
4855 {
4856         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4857         struct hwrm_func_vf_cfg_input req = {0};
4858         int rc = 0;
4859
4860         if (!BNXT_VF(bp))
4861                 return 0;
4862
4863         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4864
4865         req.enables =
4866                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4867         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4868
4869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4870
4871         HWRM_CHECK_RESULT();
4872
4873         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4874         HWRM_UNLOCK();
4875
4876         return rc;
4877 }
4878
4879 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4880 {
4881         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4882         struct hwrm_func_drv_if_change_input req = {0};
4883         uint32_t flags;
4884         int rc;
4885
4886         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4887                 return 0;
4888
4889         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4890          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4891          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4892          */
4893         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4894                 return 0;
4895
4896         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4897
4898         if (up)
4899                 req.flags =
4900                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4901
4902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4903
4904         HWRM_CHECK_RESULT();
4905         flags = rte_le_to_cpu_32(resp->flags);
4906         HWRM_UNLOCK();
4907
4908         if (!up)
4909                 return 0;
4910
4911         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4912                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4913                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4914         }
4915
4916         return 0;
4917 }
4918
4919 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4920 {
4921         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4922         struct bnxt_error_recovery_info *info = bp->recovery_info;
4923         struct hwrm_error_recovery_qcfg_input req = {0};
4924         uint32_t flags = 0;
4925         unsigned int i;
4926         int rc;
4927
4928         /* Older FW does not have error recovery support */
4929         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4930                 return 0;
4931
4932         if (!info) {
4933                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4934                                    sizeof(*info), 0);
4935                 bp->recovery_info = info;
4936                 if (info == NULL)
4937                         return -ENOMEM;
4938         } else {
4939                 memset(info, 0, sizeof(*info));
4940         }
4941
4942         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4943
4944         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4945
4946         HWRM_CHECK_RESULT();
4947
4948         flags = rte_le_to_cpu_32(resp->flags);
4949         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4950                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4951         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4952                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4953
4954         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4955             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4956                 rc = -EINVAL;
4957                 goto err;
4958         }
4959
4960         /* FW returned values are in units of 100msec */
4961         info->driver_polling_freq =
4962                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4963         info->master_func_wait_period =
4964                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4965         info->normal_func_wait_period =
4966                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4967         info->master_func_wait_period_after_reset =
4968                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4969         info->max_bailout_time_after_reset =
4970                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4971         info->status_regs[BNXT_FW_STATUS_REG] =
4972                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4973         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4974                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4975         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4976                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4977         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4978                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4979         info->reg_array_cnt =
4980                 rte_le_to_cpu_32(resp->reg_array_cnt);
4981
4982         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4983                 rc = -EINVAL;
4984                 goto err;
4985         }
4986
4987         for (i = 0; i < info->reg_array_cnt; i++) {
4988                 info->reset_reg[i] =
4989                         rte_le_to_cpu_32(resp->reset_reg[i]);
4990                 info->reset_reg_val[i] =
4991                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4992                 info->delay_after_reset[i] =
4993                         resp->delay_after_reset[i];
4994         }
4995 err:
4996         HWRM_UNLOCK();
4997
4998         /* Map the FW status registers */
4999         if (!rc)
5000                 rc = bnxt_map_fw_health_status_regs(bp);
5001
5002         if (rc) {
5003                 rte_free(bp->recovery_info);
5004                 bp->recovery_info = NULL;
5005         }
5006         return rc;
5007 }
5008
5009 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5010 {
5011         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5012         struct hwrm_fw_reset_input req = {0};
5013         int rc;
5014
5015         if (!BNXT_PF(bp))
5016                 return -EOPNOTSUPP;
5017
5018         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5019
5020         req.embedded_proc_type =
5021                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5022         req.selfrst_status =
5023                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5024         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5025
5026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5027                                     BNXT_USE_KONG(bp));
5028
5029         HWRM_CHECK_RESULT();
5030         HWRM_UNLOCK();
5031
5032         return rc;
5033 }
5034
5035 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5036 {
5037         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5038         struct hwrm_port_ts_query_input req = {0};
5039         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5040         uint32_t flags = 0;
5041         int rc;
5042
5043         if (!ptp)
5044                 return 0;
5045
5046         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5047
5048         switch (path) {
5049         case BNXT_PTP_FLAGS_PATH_TX:
5050                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5051                 break;
5052         case BNXT_PTP_FLAGS_PATH_RX:
5053                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5054                 break;
5055         case BNXT_PTP_FLAGS_CURRENT_TIME:
5056                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5057                 break;
5058         }
5059
5060         req.flags = rte_cpu_to_le_32(flags);
5061         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5062
5063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5064
5065         HWRM_CHECK_RESULT();
5066
5067         if (timestamp) {
5068                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5069                 *timestamp |=
5070                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5071         }
5072         HWRM_UNLOCK();
5073
5074         return rc;
5075 }
5076
5077 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5078 {
5079         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5080                                         bp->hwrm_cmd_resp_addr;
5081         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5082         uint32_t flags = 0;
5083         int rc = 0;
5084
5085         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5086                 return rc;
5087
5088         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5089                 PMD_DRV_LOG(DEBUG,
5090                             "Not a PF or trusted VF. Command not supported\n");
5091                 return 0;
5092         }
5093
5094         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5096
5097         HWRM_CHECK_RESULT();
5098         flags = rte_le_to_cpu_32(resp->flags);
5099         HWRM_UNLOCK();
5100
5101         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5102                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5103                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5104         }
5105
5106         return rc;
5107 }