drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 156                         req->req_type);
 157                 goto err_ret;
 158         }
 159         return 0;
 160
 161 err_ret:
 162         return -1;
 163 }
 164
 165 /*
 166  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 167  * spinlock, and does initial processing.
 168  *
 169  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 170  * releases the spinlock only if it returns.  If the regular int return codes
 171  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 172  * directly, rather it should be copied and modified to suit the function.
 173  *
 174  * HWRM_UNLOCK() must be called after all response processing is completed.
 175  */
 176 #define HWRM_PREP(req, type, kong) do { \
 177         rte_spinlock_lock(&bp->hwrm_lock); \
 178         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 179         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 180         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 181         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 182                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 183         req.target_id = rte_cpu_to_le_16(0xffff); \
 184         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 185 } while (0)
 186
 187 #define HWRM_CHECK_RESULT_SILENT() do {\
 188         if (rc) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192         if (resp->error_code) { \
 193                 rc = rte_le_to_cpu_16(resp->error_code); \
 194                 rte_spinlock_unlock(&bp->hwrm_lock); \
 195                 return rc; \
 196         } \
 197 } while (0)
 198
 199 #define HWRM_CHECK_RESULT() do {\
 200         if (rc) { \
 201                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 204                         rc = -EACCES; \
 205                 else if (rc > 0) \
 206                         rc = -EINVAL; \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 if (resp->resp_len >= 16) { \
 212                         struct hwrm_err_output *tmp_hwrm_err_op = \
 213                                                 (void *)resp; \
 214                         PMD_DRV_LOG(ERR, \
 215                                 "error %d:%d:%08x:%04x\n", \
 216                                 rc, tmp_hwrm_err_op->cmd_err, \
 217                                 rte_le_to_cpu_32(\
 218                                         tmp_hwrm_err_op->opaque_0), \
 219                                 rte_le_to_cpu_16(\
 220                                         tmp_hwrm_err_op->opaque_1)); \
 221                 } else { \
 222                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = UINT64_MAX;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 PMD_DRV_LOG(DEBUG,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399         req.flags |=
 400         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 401
 402         enables = filter->enables |
 403               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 404         req.dst_id = rte_cpu_to_le_16(dst_id);
 405
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 408                 memcpy(req.l2_addr, filter->l2_addr,
 409                        RTE_ETHER_ADDR_LEN);
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 412                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 413                        RTE_ETHER_ADDR_LEN);
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 416                 req.l2_ovlan = filter->l2_ovlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 419                 req.l2_ivlan = filter->l2_ivlan;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 422                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 425                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 427                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 428         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 429                 req.src_type = filter->src_type;
 430
 431         req.enables = rte_cpu_to_le_32(enables);
 432
 433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 434
 435         HWRM_CHECK_RESULT();
 436
 437         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 438         HWRM_UNLOCK();
 439
 440         return rc;
 441 }
 442
 443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 444 {
 445         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 447         uint32_t flags = 0;
 448         int rc;
 449
 450         if (!ptp)
 451                 return 0;
 452
 453         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 454
 455         if (ptp->rx_filter)
 456                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 457         else
 458                 flags |=
 459                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 460         if (ptp->tx_tstamp_en)
 461                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 462         else
 463                 flags |=
 464                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 465         req.flags = rte_cpu_to_le_32(flags);
 466         req.enables = rte_cpu_to_le_32
 467                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 468         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 471         HWRM_UNLOCK();
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 480         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 482
 483 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 484         if (ptp)
 485                 return 0;
 486
 487         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 488
 489         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 490
 491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 492
 493         HWRM_CHECK_RESULT();
 494
 495         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 496                 return 0;
 497
 498         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 499         if (!ptp)
 500                 return -ENOMEM;
 501
 502         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 503                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 504         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 505                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 506         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 507                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 508         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 509                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 510         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 511                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 512         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 513                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 514         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 515                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 516         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 517                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 518         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 519                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 520
 521         ptp->bp = bp;
 522         bp->ptp_cfg = ptp;
 523
 524         return 0;
 525 }
 526
 527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 531         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 532         uint16_t new_max_vfs;
 533         uint32_t flags;
 534         int i;
 535
 536         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 537
 538         req.fid = rte_cpu_to_le_16(0xffff);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 545         flags = rte_le_to_cpu_32(resp->flags);
 546         if (BNXT_PF(bp)) {
 547                 bp->pf.port_id = resp->port_id;
 548                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 549                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 550                 new_max_vfs = bp->pdev->max_vfs;
 551                 if (new_max_vfs != bp->pf.max_vfs) {
 552                         if (bp->pf.vf_info)
 553                                 rte_free(bp->pf.vf_info);
 554                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 555                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 556                         bp->pf.max_vfs = new_max_vfs;
 557                         for (i = 0; i < new_max_vfs; i++) {
 558                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 559                                 bp->pf.vf_info[i].vlan_table =
 560                                         rte_zmalloc("VF VLAN table",
 561                                                     getpagesize(),
 562                                                     getpagesize());
 563                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 564                                         PMD_DRV_LOG(ERR,
 565                                         "Fail to alloc VLAN table for VF %d\n",
 566                                         i);
 567                                 else
 568                                         rte_mem_lock_page(
 569                                                 bp->pf.vf_info[i].vlan_table);
 570                                 bp->pf.vf_info[i].vlan_as_table =
 571                                         rte_zmalloc("VF VLAN AS table",
 572                                                     getpagesize(),
 573                                                     getpagesize());
 574                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 575                                         PMD_DRV_LOG(ERR,
 576                                         "Alloc VLAN AS table for VF %d fail\n",
 577                                         i);
 578                                 else
 579                                         rte_mem_lock_page(
 580                                                bp->pf.vf_info[i].vlan_as_table);
 581                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 582                         }
 583                 }
 584         }
 585
 586         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 587         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 588         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 589         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 590         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 591         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 592         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 593         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 594         /* TODO: For now, do not support VMDq/RFS on VFs. */
 595         if (BNXT_PF(bp)) {
 596                 if (bp->pf.max_vfs)
 597                         bp->max_vnics = 1;
 598                 else
 599                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 600         } else {
 601                 bp->max_vnics = 1;
 602         }
 603         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 604         if (BNXT_PF(bp)) {
 605                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 606                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 607                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 608                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 609                         HWRM_UNLOCK();
 610                         bnxt_hwrm_ptp_qcfg(bp);
 611                 }
 612         }
 613
 614         HWRM_UNLOCK();
 615
 616         return rc;
 617 }
 618
 619 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 620 {
 621         int rc;
 622
 623         rc = __bnxt_hwrm_func_qcaps(bp);
 624         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 625                 rc = bnxt_alloc_ctx_mem(bp);
 626                 if (rc)
 627                         return rc;
 628
 629                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 630                 if (!rc)
 631                         bp->flags |= BNXT_FLAG_NEW_RM;
 632         }
 633
 634         return rc;
 635 }
 636
 637 int bnxt_hwrm_func_reset(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640         struct hwrm_func_reset_input req = {.req_type = 0 };
 641         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 642
 643         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 644
 645         req.enables = rte_cpu_to_le_32(0);
 646
 647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 648
 649         HWRM_CHECK_RESULT();
 650         HWRM_UNLOCK();
 651
 652         return rc;
 653 }
 654
 655 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 656 {
 657         int rc;
 658         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 659         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 660
 661         if (bp->flags & BNXT_FLAG_REGISTERED)
 662                 return 0;
 663
 664         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 665         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 666                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 667         req.ver_maj = RTE_VER_YEAR;
 668         req.ver_min = RTE_VER_MONTH;
 669         req.ver_upd = RTE_VER_MINOR;
 670
 671         if (BNXT_PF(bp)) {
 672                 req.enables |= rte_cpu_to_le_32(
 673                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 674                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 675                        RTE_MIN(sizeof(req.vf_req_fwd),
 676                                sizeof(bp->pf.vf_req_fwd)));
 677
 678                 /*
 679                  * PF can sniff HWRM API issued by VF. This can be set up by
 680                  * linux driver and inherited by the DPDK PF driver. Clear
 681                  * this HWRM sniffer list in FW because DPDK PF driver does
 682                  * not support this.
 683                  */
 684                 req.flags =
 685                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 686         }
 687
 688         req.async_event_fwd[0] |=
 689                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 690                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 691                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 692         req.async_event_fwd[1] |=
 693                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 694                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 695
 696         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 697
 698         HWRM_CHECK_RESULT();
 699         HWRM_UNLOCK();
 700
 701         bp->flags |= BNXT_FLAG_REGISTERED;
 702
 703         return rc;
 704 }
 705
 706 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 707 {
 708         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 709                 return 0;
 710
 711         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 712 }
 713
 714 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 715 {
 716         int rc;
 717         uint32_t flags = 0;
 718         uint32_t enables;
 719         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 720         struct hwrm_func_vf_cfg_input req = {0};
 721
 722         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 723
 724         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 725                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 726                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 727                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 728                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 729
 730         if (BNXT_HAS_RING_GRPS(bp)) {
 731                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 732                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 733         }
 734
 735         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 736         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 737                                             AGG_RING_MULTIPLIER);
 738         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 739         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 740                                               bp->tx_nr_rings);
 741         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 742         if (bp->vf_resv_strategy ==
 743             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 744                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 745                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 746                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 747                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 748                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 749                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 750         }
 751
 752         if (test)
 753                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 754                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 755                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 756                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 757                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 758                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 759
 760         if (test && BNXT_HAS_RING_GRPS(bp))
 761                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 762
 763         req.flags = rte_cpu_to_le_32(flags);
 764         req.enables |= rte_cpu_to_le_32(enables);
 765
 766         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 767
 768         if (test)
 769                 HWRM_CHECK_RESULT_SILENT();
 770         else
 771                 HWRM_CHECK_RESULT();
 772
 773         HWRM_UNLOCK();
 774         return rc;
 775 }
 776
 777 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 778 {
 779         int rc;
 780         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 781         struct hwrm_func_resource_qcaps_input req = {0};
 782
 783         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 784         req.fid = rte_cpu_to_le_16(0xffff);
 785
 786         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 787
 788         HWRM_CHECK_RESULT();
 789
 790         if (BNXT_VF(bp)) {
 791                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 792                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 793                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 794                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 795                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 796                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 797                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 798                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 799         }
 800         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 801         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 802         if (bp->vf_resv_strategy >
 803             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 804                 bp->vf_resv_strategy =
 805                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 806
 807         HWRM_UNLOCK();
 808         return rc;
 809 }
 810
 811 int bnxt_hwrm_ver_get(struct bnxt *bp)
 812 {
 813         int rc = 0;
 814         struct hwrm_ver_get_input req = {.req_type = 0 };
 815         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 816         uint32_t fw_version;
 817         uint16_t max_resp_len;
 818         char type[RTE_MEMZONE_NAMESIZE];
 819         uint32_t dev_caps_cfg;
 820
 821         bp->max_req_len = HWRM_MAX_REQ_LEN;
 822         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 823
 824         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 825         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 826         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 827
 828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 829
 830         HWRM_CHECK_RESULT();
 831
 832         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 833                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 834                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 835                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 836         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 837                      (resp->hwrm_fw_min_8b << 16) |
 838                      (resp->hwrm_fw_bld_8b << 8) |
 839                      resp->hwrm_fw_rsvd_8b;
 840         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 841                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 842
 843         fw_version = resp->hwrm_intf_maj_8b << 16;
 844         fw_version |= resp->hwrm_intf_min_8b << 8;
 845         fw_version |= resp->hwrm_intf_upd_8b;
 846         bp->hwrm_spec_code = fw_version;
 847
 848         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 849                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 850                 rc = -EINVAL;
 851                 goto error;
 852         }
 853
 854         if (bp->max_req_len > resp->max_req_win_len) {
 855                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 856                 rc = -EINVAL;
 857         }
 858         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 859         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 860         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 861                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 862
 863         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 864         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 865
 866         if (bp->max_resp_len != max_resp_len) {
 867                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 868                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 869                         bp->pdev->addr.devid, bp->pdev->addr.function);
 870
 871                 rte_free(bp->hwrm_cmd_resp_addr);
 872
 873                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 874                 if (bp->hwrm_cmd_resp_addr == NULL) {
 875                         rc = -ENOMEM;
 876                         goto error;
 877                 }
 878                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 879                 bp->hwrm_cmd_resp_dma_addr =
 880                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 881                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 882                         PMD_DRV_LOG(ERR,
 883                         "Unable to map response buffer to physical memory.\n");
 884                         rc = -ENOMEM;
 885                         goto error;
 886                 }
 887                 bp->max_resp_len = max_resp_len;
 888         }
 889
 890         if ((dev_caps_cfg &
 891                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 892             (dev_caps_cfg &
 893              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 894                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 895                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 896         }
 897
 898         if (((dev_caps_cfg &
 899               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 900              (dev_caps_cfg &
 901               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 902             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 903                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 904                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 905                         bp->pdev->addr.devid, bp->pdev->addr.function);
 906
 907                 rte_free(bp->hwrm_short_cmd_req_addr);
 908
 909                 bp->hwrm_short_cmd_req_addr =
 910                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 911                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 912                         rc = -ENOMEM;
 913                         goto error;
 914                 }
 915                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 916                 bp->hwrm_short_cmd_req_dma_addr =
 917                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 918                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 919                         rte_free(bp->hwrm_short_cmd_req_addr);
 920                         PMD_DRV_LOG(ERR,
 921                                 "Unable to map buffer to physical memory.\n");
 922                         rc = -ENOMEM;
 923                         goto error;
 924                 }
 925         }
 926         if (dev_caps_cfg &
 927             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 928                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 929                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 930         }
 931         if (dev_caps_cfg &
 932             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 933                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 934
 935 error:
 936         HWRM_UNLOCK();
 937         return rc;
 938 }
 939
 940 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 941 {
 942         int rc;
 943         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 944         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 945
 946         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 947                 return 0;
 948
 949         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 950         req.flags = flags;
 951
 952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 953
 954         HWRM_CHECK_RESULT();
 955         HWRM_UNLOCK();
 956
 957         bp->flags &= ~BNXT_FLAG_REGISTERED;
 958
 959         return rc;
 960 }
 961
 962 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 963 {
 964         int rc = 0;
 965         struct hwrm_port_phy_cfg_input req = {0};
 966         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 967         uint32_t enables = 0;
 968
 969         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 970
 971         if (conf->link_up) {
 972                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 973                 if (bp->link_info.auto_mode && conf->link_speed) {
 974                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 975                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 976                 }
 977
 978                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 979                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 980                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 981                 /*
 982                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 983                  * any auto mode, even "none".
 984                  */
 985                 if (!conf->link_speed) {
 986                         /* No speeds specified. Enable AutoNeg - all speeds */
 987                         req.auto_mode =
 988                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 989                 }
 990                 /* AutoNeg - Advertise speeds specified. */
 991                 if (conf->auto_link_speed_mask &&
 992                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 993                         req.auto_mode =
 994                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 995                         req.auto_link_speed_mask =
 996                                 conf->auto_link_speed_mask;
 997                         enables |=
 998                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 999                 }
1000
1001                 req.auto_duplex = conf->duplex;
1002                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1003                 req.auto_pause = conf->auto_pause;
1004                 req.force_pause = conf->force_pause;
1005                 /* Set force_pause if there is no auto or if there is a force */
1006                 if (req.auto_pause && !req.force_pause)
1007                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1008                 else
1009                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1010
1011                 req.enables = rte_cpu_to_le_32(enables);
1012         } else {
1013                 req.flags =
1014                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1015                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1016         }
1017
1018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1019
1020         HWRM_CHECK_RESULT();
1021         HWRM_UNLOCK();
1022
1023         return rc;
1024 }
1025
1026 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1027                                    struct bnxt_link_info *link_info)
1028 {
1029         int rc = 0;
1030         struct hwrm_port_phy_qcfg_input req = {0};
1031         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1032
1033         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1034
1035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1036
1037         HWRM_CHECK_RESULT();
1038
1039         link_info->phy_link_status = resp->link;
1040         link_info->link_up =
1041                 (link_info->phy_link_status ==
1042                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1043         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1044         link_info->duplex = resp->duplex_cfg;
1045         link_info->pause = resp->pause;
1046         link_info->auto_pause = resp->auto_pause;
1047         link_info->force_pause = resp->force_pause;
1048         link_info->auto_mode = resp->auto_mode;
1049         link_info->phy_type = resp->phy_type;
1050         link_info->media_type = resp->media_type;
1051
1052         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1053         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1054         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1055         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1056         link_info->phy_ver[0] = resp->phy_maj;
1057         link_info->phy_ver[1] = resp->phy_min;
1058         link_info->phy_ver[2] = resp->phy_bld;
1059
1060         HWRM_UNLOCK();
1061
1062         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1063         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1064         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1065         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1066         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1067                     link_info->auto_link_speed_mask);
1068         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1069                     link_info->force_link_speed);
1070
1071         return rc;
1072 }
1073
1074 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1075 {
1076         int rc = 0;
1077         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1078         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1079         int i;
1080
1081         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1082
1083         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1084         /* HWRM Version >= 1.9.1 */
1085         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1086                 req.drv_qmap_cap =
1087                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089
1090         HWRM_CHECK_RESULT();
1091
1092 #define GET_QUEUE_INFO(x) \
1093         bp->cos_queue[x].id = resp->queue_id##x; \
1094         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1095
1096         GET_QUEUE_INFO(0);
1097         GET_QUEUE_INFO(1);
1098         GET_QUEUE_INFO(2);
1099         GET_QUEUE_INFO(3);
1100         GET_QUEUE_INFO(4);
1101         GET_QUEUE_INFO(5);
1102         GET_QUEUE_INFO(6);
1103         GET_QUEUE_INFO(7);
1104
1105         HWRM_UNLOCK();
1106
1107         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1108                 bp->tx_cosq_id = bp->cos_queue[0].id;
1109         } else {
1110                 /* iterate and find the COSq profile to use for Tx */
1111                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1112                         if (bp->cos_queue[i].profile ==
1113                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1114                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1115                                 break;
1116                         }
1117                 }
1118         }
1119
1120         bp->max_tc = resp->max_configurable_queues;
1121         bp->max_lltc = resp->max_configurable_lossless_queues;
1122         if (bp->max_tc > BNXT_MAX_QUEUE)
1123                 bp->max_tc = BNXT_MAX_QUEUE;
1124         bp->max_q = bp->max_tc;
1125
1126         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1127
1128         return rc;
1129 }
1130
1131 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1132                          struct bnxt_ring *ring,
1133                          uint32_t ring_type, uint32_t map_index,
1134                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1135 {
1136         int rc = 0;
1137         uint32_t enables = 0;
1138         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1139         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1140         struct rte_mempool *mb_pool;
1141         uint16_t rx_buf_size;
1142
1143         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1144
1145         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1146         req.fbo = rte_cpu_to_le_32(0);
1147         /* Association of ring index with doorbell index */
1148         req.logical_id = rte_cpu_to_le_16(map_index);
1149         req.length = rte_cpu_to_le_32(ring->ring_size);
1150
1151         switch (ring_type) {
1152         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1153                 req.ring_type = ring_type;
1154                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1155                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1156                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1157                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1158                         enables |=
1159                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1160                 break;
1161         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1162                 req.ring_type = ring_type;
1163                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1164                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1165                 if (BNXT_CHIP_THOR(bp)) {
1166                         mb_pool = bp->rx_queues[0]->mb_pool;
1167                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1168                                       RTE_PKTMBUF_HEADROOM;
1169                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1170                         enables |=
1171                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1172                 }
1173                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1174                         enables |=
1175                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1176                 break;
1177         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1178                 req.ring_type = ring_type;
1179                 if (BNXT_HAS_NQ(bp)) {
1180                         /* Association of cp ring with nq */
1181                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1182                         enables |=
1183                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1184                 }
1185                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1186                 break;
1187         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1188                 req.ring_type = ring_type;
1189                 req.page_size = BNXT_PAGE_SHFT;
1190                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1191                 break;
1192         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1193                 req.ring_type = ring_type;
1194                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1195
1196                 mb_pool = bp->rx_queues[0]->mb_pool;
1197                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1198                               RTE_PKTMBUF_HEADROOM;
1199                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1200
1201                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1202                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1203                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1204                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1205                 break;
1206         default:
1207                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1208                         ring_type);
1209                 HWRM_UNLOCK();
1210                 return -1;
1211         }
1212         req.enables = rte_cpu_to_le_32(enables);
1213
1214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215
1216         if (rc || resp->error_code) {
1217                 if (rc == 0 && resp->error_code)
1218                         rc = rte_le_to_cpu_16(resp->error_code);
1219                 switch (ring_type) {
1220                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1221                         PMD_DRV_LOG(ERR,
1222                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1223                         HWRM_UNLOCK();
1224                         return rc;
1225                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1226                         PMD_DRV_LOG(ERR,
1227                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1228                         HWRM_UNLOCK();
1229                         return rc;
1230                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1231                         PMD_DRV_LOG(ERR,
1232                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1233                                     rc);
1234                         HWRM_UNLOCK();
1235                         return rc;
1236                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1237                         PMD_DRV_LOG(ERR,
1238                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1239                         HWRM_UNLOCK();
1240                         return rc;
1241                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1242                         PMD_DRV_LOG(ERR,
1243                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1244                         HWRM_UNLOCK();
1245                         return rc;
1246                 default:
1247                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1248                         HWRM_UNLOCK();
1249                         return rc;
1250                 }
1251         }
1252
1253         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1254         HWRM_UNLOCK();
1255         return rc;
1256 }
1257
1258 int bnxt_hwrm_ring_free(struct bnxt *bp,
1259                         struct bnxt_ring *ring, uint32_t ring_type)
1260 {
1261         int rc;
1262         struct hwrm_ring_free_input req = {.req_type = 0 };
1263         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1264
1265         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1266
1267         req.ring_type = ring_type;
1268         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1269
1270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1271
1272         if (rc || resp->error_code) {
1273                 if (rc == 0 && resp->error_code)
1274                         rc = rte_le_to_cpu_16(resp->error_code);
1275                 HWRM_UNLOCK();
1276
1277                 switch (ring_type) {
1278                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1279                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1280                                 rc);
1281                         return rc;
1282                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1283                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1284                                 rc);
1285                         return rc;
1286                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1287                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1288                                 rc);
1289                         return rc;
1290                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1291                         PMD_DRV_LOG(ERR,
1292                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1293                         return rc;
1294                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1295                         PMD_DRV_LOG(ERR,
1296                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1297                         return rc;
1298                 default:
1299                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1300                         return rc;
1301                 }
1302         }
1303         HWRM_UNLOCK();
1304         return 0;
1305 }
1306
1307 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1308 {
1309         int rc = 0;
1310         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1311         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1312
1313         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1314
1315         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1316         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1317         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1318         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1319
1320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1321
1322         HWRM_CHECK_RESULT();
1323
1324         bp->grp_info[idx].fw_grp_id =
1325             rte_le_to_cpu_16(resp->ring_group_id);
1326
1327         HWRM_UNLOCK();
1328
1329         return rc;
1330 }
1331
1332 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1333 {
1334         int rc;
1335         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1336         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1337
1338         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1339
1340         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1341
1342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1343
1344         HWRM_CHECK_RESULT();
1345         HWRM_UNLOCK();
1346
1347         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1348         return rc;
1349 }
1350
1351 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1352 {
1353         int rc = 0;
1354         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1355         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1356
1357         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1358                 return rc;
1359
1360         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1361
1362         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1363
1364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1365
1366         HWRM_CHECK_RESULT();
1367         HWRM_UNLOCK();
1368
1369         return rc;
1370 }
1371
1372 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1373                                 unsigned int idx __rte_unused)
1374 {
1375         int rc;
1376         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1377         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1378
1379         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1380
1381         req.update_period_ms = rte_cpu_to_le_32(0);
1382
1383         req.stats_dma_addr =
1384             rte_cpu_to_le_64(cpr->hw_stats_map);
1385
1386         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1387
1388         HWRM_CHECK_RESULT();
1389
1390         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1391
1392         HWRM_UNLOCK();
1393
1394         return rc;
1395 }
1396
1397 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1398                                 unsigned int idx __rte_unused)
1399 {
1400         int rc;
1401         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1402         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1403
1404         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1405
1406         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1407
1408         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1409
1410         HWRM_CHECK_RESULT();
1411         HWRM_UNLOCK();
1412
1413         return rc;
1414 }
1415
1416 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1417 {
1418         int rc = 0, i, j;
1419         struct hwrm_vnic_alloc_input req = { 0 };
1420         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1421
1422         if (!BNXT_HAS_RING_GRPS(bp))
1423                 goto skip_ring_grps;
1424
1425         /* map ring groups to this vnic */
1426         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1427                 vnic->start_grp_id, vnic->end_grp_id);
1428         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1429                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1430
1431         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1432         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1433         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1434         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1435
1436 skip_ring_grps:
1437         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1438                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1439         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1440
1441         if (vnic->func_default)
1442                 req.flags =
1443                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1445
1446         HWRM_CHECK_RESULT();
1447
1448         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1449         HWRM_UNLOCK();
1450         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1451         return rc;
1452 }
1453
1454 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1455                                         struct bnxt_vnic_info *vnic,
1456                                         struct bnxt_plcmodes_cfg *pmode)
1457 {
1458         int rc = 0;
1459         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1460         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1461
1462         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1463
1464         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1465
1466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467
1468         HWRM_CHECK_RESULT();
1469
1470         pmode->flags = rte_le_to_cpu_32(resp->flags);
1471         /* dflt_vnic bit doesn't exist in the _cfg command */
1472         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1473         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1474         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1475         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1476
1477         HWRM_UNLOCK();
1478
1479         return rc;
1480 }
1481
1482 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1483                                        struct bnxt_vnic_info *vnic,
1484                                        struct bnxt_plcmodes_cfg *pmode)
1485 {
1486         int rc = 0;
1487         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1488         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1489
1490         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1491
1492         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1493         req.flags = rte_cpu_to_le_32(pmode->flags);
1494         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1495         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1496         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1497         req.enables = rte_cpu_to_le_32(
1498             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1499             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1500             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1501         );
1502
1503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1504
1505         HWRM_CHECK_RESULT();
1506         HWRM_UNLOCK();
1507
1508         return rc;
1509 }
1510
1511 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1512 {
1513         int rc = 0;
1514         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1515         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1516         uint32_t ctx_enable_flag = 0;
1517         struct bnxt_plcmodes_cfg pmodes;
1518         uint32_t enables = 0;
1519
1520         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1521                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1522                 return rc;
1523         }
1524
1525         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1526         if (rc)
1527                 return rc;
1528
1529         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1530
1531         if (BNXT_CHIP_THOR(bp)) {
1532                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1533                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1534                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1535
1536                 req.default_rx_ring_id =
1537                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1538                 req.default_cmpl_ring_id =
1539                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1540                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1541                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1542                 goto config_mru;
1543         }
1544
1545         /* Only RSS support for now TBD: COS & LB */
1546         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1547         if (vnic->lb_rule != 0xffff)
1548                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1549         if (vnic->cos_rule != 0xffff)
1550                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1551         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1552                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1553                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1554         }
1555         enables |= ctx_enable_flag;
1556         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1557         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1558         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1559         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1560
1561 config_mru:
1562         req.enables = rte_cpu_to_le_32(enables);
1563         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1564         req.mru = rte_cpu_to_le_16(vnic->mru);
1565         /* Configure default VNIC only once. */
1566         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1567                 req.flags |=
1568                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1569                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1570         }
1571         if (vnic->vlan_strip)
1572                 req.flags |=
1573                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1574         if (vnic->bd_stall)
1575                 req.flags |=
1576                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1577         if (vnic->roce_dual)
1578                 req.flags |= rte_cpu_to_le_32(
1579                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1580         if (vnic->roce_only)
1581                 req.flags |= rte_cpu_to_le_32(
1582                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1583         if (vnic->rss_dflt_cr)
1584                 req.flags |= rte_cpu_to_le_32(
1585                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1586
1587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1588
1589         HWRM_CHECK_RESULT();
1590         HWRM_UNLOCK();
1591
1592         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1593
1594         return rc;
1595 }
1596
1597 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1598                 int16_t fw_vf_id)
1599 {
1600         int rc = 0;
1601         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1602         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1603
1604         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1605                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1606                 return rc;
1607         }
1608         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1609
1610         req.enables =
1611                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1612         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1613         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1614
1615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616
1617         HWRM_CHECK_RESULT();
1618
1619         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1620         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1621         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1622         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1623         vnic->mru = rte_le_to_cpu_16(resp->mru);
1624         vnic->func_default = rte_le_to_cpu_32(
1625                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1626         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1627                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1628         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1629                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1630         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1631                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1632         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1633                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1634         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1635                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1636
1637         HWRM_UNLOCK();
1638
1639         return rc;
1640 }
1641
1642 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1643                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1644 {
1645         int rc = 0;
1646         uint16_t ctx_id;
1647         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1648         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1649                                                 bp->hwrm_cmd_resp_addr;
1650
1651         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1652
1653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1654         HWRM_CHECK_RESULT();
1655
1656         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1657         if (!BNXT_HAS_RING_GRPS(bp))
1658                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1659         else if (ctx_idx == 0)
1660                 vnic->rss_rule = ctx_id;
1661
1662         HWRM_UNLOCK();
1663
1664         return rc;
1665 }
1666
1667 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1668                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1669 {
1670         int rc = 0;
1671         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1672         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1673                                                 bp->hwrm_cmd_resp_addr;
1674
1675         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1676                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1677                 return rc;
1678         }
1679         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1680
1681         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1682
1683         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1684
1685         HWRM_CHECK_RESULT();
1686         HWRM_UNLOCK();
1687
1688         return rc;
1689 }
1690
1691 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1692 {
1693         int rc = 0;
1694         struct hwrm_vnic_free_input req = {.req_type = 0 };
1695         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1696
1697         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1698                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1699                 return rc;
1700         }
1701
1702         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1703
1704         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1705
1706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1707
1708         HWRM_CHECK_RESULT();
1709         HWRM_UNLOCK();
1710
1711         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1712         /* Configure default VNIC again if necessary. */
1713         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1714                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1715
1716         return rc;
1717 }
1718
1719 static int
1720 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1721 {
1722         int i;
1723         int rc = 0;
1724         int nr_ctxs = bp->max_ring_grps;
1725         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1726         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1727
1728         if (!(vnic->rss_table && vnic->hash_type))
1729                 return 0;
1730
1731         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1732
1733         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1735         req.hash_mode_flags = vnic->hash_mode;
1736
1737         req.hash_key_tbl_addr =
1738             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1739
1740         for (i = 0; i < nr_ctxs; i++) {
1741                 req.ring_grp_tbl_addr =
1742                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1743                                          i * HW_HASH_INDEX_SIZE);
1744                 req.ring_table_pair_index = i;
1745                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1746
1747                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1748                                             BNXT_USE_CHIMP_MB);
1749
1750                 HWRM_CHECK_RESULT();
1751                 if (rc)
1752                         break;
1753         }
1754
1755         HWRM_UNLOCK();
1756
1757         return rc;
1758 }
1759
1760 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1761                            struct bnxt_vnic_info *vnic)
1762 {
1763         int rc = 0;
1764         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1765         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1766
1767         if (BNXT_CHIP_THOR(bp))
1768                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1769
1770         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1771
1772         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1773         req.hash_mode_flags = vnic->hash_mode;
1774
1775         req.ring_grp_tbl_addr =
1776             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1777         req.hash_key_tbl_addr =
1778             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1779         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1780         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781
1782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783
1784         HWRM_CHECK_RESULT();
1785         HWRM_UNLOCK();
1786
1787         return rc;
1788 }
1789
1790 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1791                         struct bnxt_vnic_info *vnic)
1792 {
1793         int rc = 0;
1794         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1795         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1796         uint16_t size;
1797
1798         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1799                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1800                 return rc;
1801         }
1802
1803         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1804
1805         req.flags = rte_cpu_to_le_32(
1806                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1807
1808         req.enables = rte_cpu_to_le_32(
1809                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1810
1811         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1812         size -= RTE_PKTMBUF_HEADROOM;
1813
1814         req.jumbo_thresh = rte_cpu_to_le_16(size);
1815         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1816
1817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1818
1819         HWRM_CHECK_RESULT();
1820         HWRM_UNLOCK();
1821
1822         return rc;
1823 }
1824
1825 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1826                         struct bnxt_vnic_info *vnic, bool enable)
1827 {
1828         int rc = 0;
1829         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1830         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1831
1832         if (BNXT_CHIP_THOR(bp))
1833                 return 0;
1834
1835         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1836
1837         if (enable) {
1838                 req.enables = rte_cpu_to_le_32(
1839                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1840                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1841                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1842                 req.flags = rte_cpu_to_le_32(
1843                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1844                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1845                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1846                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1847                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1848                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1849                 req.max_agg_segs = rte_cpu_to_le_16(5);
1850                 req.max_aggs =
1851                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1852                 req.min_agg_len = rte_cpu_to_le_32(512);
1853         }
1854         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855
1856         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857
1858         HWRM_CHECK_RESULT();
1859         HWRM_UNLOCK();
1860
1861         return rc;
1862 }
1863
1864 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1865 {
1866         struct hwrm_func_cfg_input req = {0};
1867         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1868         int rc;
1869
1870         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1871         req.enables = rte_cpu_to_le_32(
1872                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1873         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1874         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1875
1876         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1877
1878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1879         HWRM_CHECK_RESULT();
1880         HWRM_UNLOCK();
1881
1882         bp->pf.vf_info[vf].random_mac = false;
1883
1884         return rc;
1885 }
1886
1887 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1888                                   uint64_t *dropped)
1889 {
1890         int rc = 0;
1891         struct hwrm_func_qstats_input req = {.req_type = 0};
1892         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1893
1894         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1895
1896         req.fid = rte_cpu_to_le_16(fid);
1897
1898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1899
1900         HWRM_CHECK_RESULT();
1901
1902         if (dropped)
1903                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1904
1905         HWRM_UNLOCK();
1906
1907         return rc;
1908 }
1909
1910 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1911                           struct rte_eth_stats *stats)
1912 {
1913         int rc = 0;
1914         struct hwrm_func_qstats_input req = {.req_type = 0};
1915         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1916
1917         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1918
1919         req.fid = rte_cpu_to_le_16(fid);
1920
1921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922
1923         HWRM_CHECK_RESULT();
1924
1925         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1926         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1927         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1928         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1929         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1930         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1931
1932         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1933         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1934         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1935         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1936         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1937         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1938
1939         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1940         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1941         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1942
1943         HWRM_UNLOCK();
1944
1945         return rc;
1946 }
1947
1948 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1949 {
1950         int rc = 0;
1951         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1952         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1953
1954         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1955
1956         req.fid = rte_cpu_to_le_16(fid);
1957
1958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1959
1960         HWRM_CHECK_RESULT();
1961         HWRM_UNLOCK();
1962
1963         return rc;
1964 }
1965
1966 /*
1967  * HWRM utility functions
1968  */
1969
1970 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1971 {
1972         unsigned int i;
1973         int rc = 0;
1974
1975         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1976                 struct bnxt_tx_queue *txq;
1977                 struct bnxt_rx_queue *rxq;
1978                 struct bnxt_cp_ring_info *cpr;
1979
1980                 if (i >= bp->rx_cp_nr_rings) {
1981                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1982                         cpr = txq->cp_ring;
1983                 } else {
1984                         rxq = bp->rx_queues[i];
1985                         cpr = rxq->cp_ring;
1986                 }
1987
1988                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1989                 if (rc)
1990                         return rc;
1991         }
1992         return 0;
1993 }
1994
1995 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1996 {
1997         int rc;
1998         unsigned int i;
1999         struct bnxt_cp_ring_info *cpr;
2000
2001         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2002
2003                 if (i >= bp->rx_cp_nr_rings) {
2004                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2005                 } else {
2006                         cpr = bp->rx_queues[i]->cp_ring;
2007                         bp->grp_info[i].fw_stats_ctx = -1;
2008                 }
2009                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2010                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2011                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2012                         if (rc)
2013                                 return rc;
2014                 }
2015         }
2016         return 0;
2017 }
2018
2019 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2020 {
2021         unsigned int i;
2022         int rc = 0;
2023
2024         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2025                 struct bnxt_tx_queue *txq;
2026                 struct bnxt_rx_queue *rxq;
2027                 struct bnxt_cp_ring_info *cpr;
2028
2029                 if (i >= bp->rx_cp_nr_rings) {
2030                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2031                         cpr = txq->cp_ring;
2032                 } else {
2033                         rxq = bp->rx_queues[i];
2034                         cpr = rxq->cp_ring;
2035                 }
2036
2037                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2038
2039                 if (rc)
2040                         return rc;
2041         }
2042         return rc;
2043 }
2044
2045 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2046 {
2047         uint16_t idx;
2048         uint32_t rc = 0;
2049
2050         if (!BNXT_HAS_RING_GRPS(bp))
2051                 return 0;
2052
2053         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2054
2055                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2056                         continue;
2057
2058                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2059
2060                 if (rc)
2061                         return rc;
2062         }
2063         return rc;
2064 }
2065
2066 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2067 {
2068         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2069
2070         bnxt_hwrm_ring_free(bp, cp_ring,
2071                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2072         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2073         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2074                                      sizeof(*cpr->cp_desc_ring));
2075         cpr->cp_raw_cons = 0;
2076 }
2077
2078 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2079 {
2080         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2081
2082         bnxt_hwrm_ring_free(bp, cp_ring,
2083                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2084         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2085         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2086                         sizeof(*cpr->cp_desc_ring));
2087         cpr->cp_raw_cons = 0;
2088 }
2089
2090 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2091 {
2092         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2093         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2094         struct bnxt_ring *ring = rxr->rx_ring_struct;
2095         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2096
2097         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2098                 bnxt_hwrm_ring_free(bp, ring,
2099                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2100                 ring->fw_ring_id = INVALID_HW_RING_ID;
2101                 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2102                 memset(rxr->rx_desc_ring, 0,
2103                        rxr->rx_ring_struct->ring_size *
2104                        sizeof(*rxr->rx_desc_ring));
2105                 memset(rxr->rx_buf_ring, 0,
2106                        rxr->rx_ring_struct->ring_size *
2107                        sizeof(*rxr->rx_buf_ring));
2108                 rxr->rx_prod = 0;
2109         }
2110         ring = rxr->ag_ring_struct;
2111         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2112                 bnxt_hwrm_ring_free(bp, ring,
2113                                     BNXT_CHIP_THOR(bp) ?
2114                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2115                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2116                 ring->fw_ring_id = INVALID_HW_RING_ID;
2117                 memset(rxr->ag_buf_ring, 0,
2118                        rxr->ag_ring_struct->ring_size *
2119                        sizeof(*rxr->ag_buf_ring));
2120                 rxr->ag_prod = 0;
2121                 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2122         }
2123         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2124                 bnxt_free_cp_ring(bp, cpr);
2125                 if (rxq->nq_ring)
2126                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2127         }
2128
2129         bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2130 }
2131
2132 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2133 {
2134         unsigned int i;
2135
2136         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2137                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2138                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2139                 struct bnxt_ring *ring = txr->tx_ring_struct;
2140                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2141
2142                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2143                         bnxt_hwrm_ring_free(bp, ring,
2144                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2145                         ring->fw_ring_id = INVALID_HW_RING_ID;
2146                         memset(txr->tx_desc_ring, 0,
2147                                         txr->tx_ring_struct->ring_size *
2148                                         sizeof(*txr->tx_desc_ring));
2149                         memset(txr->tx_buf_ring, 0,
2150                                         txr->tx_ring_struct->ring_size *
2151                                         sizeof(*txr->tx_buf_ring));
2152                         txr->tx_prod = 0;
2153                         txr->tx_cons = 0;
2154                 }
2155                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2156                         bnxt_free_cp_ring(bp, cpr);
2157                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2158                         if (txq->nq_ring)
2159                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2160                 }
2161         }
2162
2163         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2164                 bnxt_free_hwrm_rx_ring(bp, i);
2165
2166         return 0;
2167 }
2168
2169 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2170 {
2171         uint16_t i;
2172         uint32_t rc = 0;
2173
2174         if (!BNXT_HAS_RING_GRPS(bp))
2175                 return 0;
2176
2177         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2178                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2179                 if (rc)
2180                         return rc;
2181         }
2182         return rc;
2183 }
2184
2185 void bnxt_free_hwrm_resources(struct bnxt *bp)
2186 {
2187         /* Release memzone */
2188         rte_free(bp->hwrm_cmd_resp_addr);
2189         rte_free(bp->hwrm_short_cmd_req_addr);
2190         bp->hwrm_cmd_resp_addr = NULL;
2191         bp->hwrm_short_cmd_req_addr = NULL;
2192         bp->hwrm_cmd_resp_dma_addr = 0;
2193         bp->hwrm_short_cmd_req_dma_addr = 0;
2194 }
2195
2196 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2197 {
2198         struct rte_pci_device *pdev = bp->pdev;
2199         char type[RTE_MEMZONE_NAMESIZE];
2200
2201         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2202                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2203         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2204         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2205         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2206         if (bp->hwrm_cmd_resp_addr == NULL)
2207                 return -ENOMEM;
2208         bp->hwrm_cmd_resp_dma_addr =
2209                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2210         if (bp->hwrm_cmd_resp_dma_addr == 0) {
2211                 PMD_DRV_LOG(ERR,
2212                         "unable to map response address to physical memory\n");
2213                 return -ENOMEM;
2214         }
2215         rte_spinlock_init(&bp->hwrm_lock);
2216
2217         return 0;
2218 }
2219
2220 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2221 {
2222         struct bnxt_filter_info *filter;
2223         int rc = 0;
2224
2225         STAILQ_FOREACH(filter, &vnic->filter, next) {
2226                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2227                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2228                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2229                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2230                 else
2231                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2232                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2233                 //if (rc)
2234                         //break;
2235         }
2236         return rc;
2237 }
2238
2239 static int
2240 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2241 {
2242         struct bnxt_filter_info *filter;
2243         struct rte_flow *flow;
2244         int rc = 0;
2245
2246         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2247                 filter = flow->filter;
2248                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2249                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2250                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2251                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2252                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2253                 else
2254                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2255
2256                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2257                 rte_free(flow);
2258                 //if (rc)
2259                         //break;
2260         }
2261         return rc;
2262 }
2263
2264 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2265 {
2266         struct bnxt_filter_info *filter;
2267         int rc = 0;
2268
2269         STAILQ_FOREACH(filter, &vnic->filter, next) {
2270                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2271                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2272                                                      filter);
2273                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2274                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2275                                                          filter);
2276                 else
2277                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2278                                                      filter);
2279                 if (rc)
2280                         break;
2281         }
2282         return rc;
2283 }
2284
2285 void bnxt_free_tunnel_ports(struct bnxt *bp)
2286 {
2287         if (bp->vxlan_port_cnt)
2288                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2289                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2290         bp->vxlan_port = 0;
2291         if (bp->geneve_port_cnt)
2292                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2293                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2294         bp->geneve_port = 0;
2295 }
2296
2297 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2298 {
2299         int i, j;
2300
2301         if (bp->vnic_info == NULL)
2302                 return;
2303
2304         /*
2305          * Cleanup VNICs in reverse order, to make sure the L2 filter
2306          * from vnic0 is last to be cleaned up.
2307          */
2308         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2309                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2310
2311                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2312
2313                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2314
2315                 if (!BNXT_CHIP_THOR(bp)) {
2316                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2317                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2318                                                         vnic->fw_grp_ids[j]);
2319                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2320                         }
2321                 } else {
2322                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2323                         vnic->rss_rule = INVALID_HW_RING_ID;
2324                 }
2325
2326                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2327
2328                 bnxt_hwrm_vnic_free(bp, vnic);
2329
2330                 rte_free(vnic->fw_grp_ids);
2331         }
2332         /* Ring resources */
2333         bnxt_free_all_hwrm_rings(bp);
2334         bnxt_free_all_hwrm_ring_grps(bp);
2335         bnxt_free_all_hwrm_stat_ctxs(bp);
2336         bnxt_free_tunnel_ports(bp);
2337 }
2338
2339 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2340 {
2341         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2342
2343         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2344                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2345
2346         switch (conf_link_speed) {
2347         case ETH_LINK_SPEED_10M_HD:
2348         case ETH_LINK_SPEED_100M_HD:
2349                 /* FALLTHROUGH */
2350                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2351         }
2352         return hw_link_duplex;
2353 }
2354
2355 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2356 {
2357         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2358 }
2359
2360 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2361 {
2362         uint16_t eth_link_speed = 0;
2363
2364         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2365                 return ETH_LINK_SPEED_AUTONEG;
2366
2367         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2368         case ETH_LINK_SPEED_100M:
2369         case ETH_LINK_SPEED_100M_HD:
2370                 /* FALLTHROUGH */
2371                 eth_link_speed =
2372                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2373                 break;
2374         case ETH_LINK_SPEED_1G:
2375                 eth_link_speed =
2376                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2377                 break;
2378         case ETH_LINK_SPEED_2_5G:
2379                 eth_link_speed =
2380                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2381                 break;
2382         case ETH_LINK_SPEED_10G:
2383                 eth_link_speed =
2384                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2385                 break;
2386         case ETH_LINK_SPEED_20G:
2387                 eth_link_speed =
2388                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2389                 break;
2390         case ETH_LINK_SPEED_25G:
2391                 eth_link_speed =
2392                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2393                 break;
2394         case ETH_LINK_SPEED_40G:
2395                 eth_link_speed =
2396                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2397                 break;
2398         case ETH_LINK_SPEED_50G:
2399                 eth_link_speed =
2400                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2401                 break;
2402         case ETH_LINK_SPEED_100G:
2403                 eth_link_speed =
2404                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2405                 break;
2406         default:
2407                 PMD_DRV_LOG(ERR,
2408                         "Unsupported link speed %d; default to AUTO\n",
2409                         conf_link_speed);
2410                 break;
2411         }
2412         return eth_link_speed;
2413 }
2414
2415 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2416                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2417                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2418                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2419
2420 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2421 {
2422         uint32_t one_speed;
2423
2424         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2425                 return 0;
2426
2427         if (link_speed & ETH_LINK_SPEED_FIXED) {
2428                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2429
2430                 if (one_speed & (one_speed - 1)) {
2431                         PMD_DRV_LOG(ERR,
2432                                 "Invalid advertised speeds (%u) for port %u\n",
2433                                 link_speed, port_id);
2434                         return -EINVAL;
2435                 }
2436                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2437                         PMD_DRV_LOG(ERR,
2438                                 "Unsupported advertised speed (%u) for port %u\n",
2439                                 link_speed, port_id);
2440                         return -EINVAL;
2441                 }
2442         } else {
2443                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2444                         PMD_DRV_LOG(ERR,
2445                                 "Unsupported advertised speeds (%u) for port %u\n",
2446                                 link_speed, port_id);
2447                         return -EINVAL;
2448                 }
2449         }
2450         return 0;
2451 }
2452
2453 static uint16_t
2454 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2455 {
2456         uint16_t ret = 0;
2457
2458         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2459                 if (bp->link_info.support_speeds)
2460                         return bp->link_info.support_speeds;
2461                 link_speed = BNXT_SUPPORTED_SPEEDS;
2462         }
2463
2464         if (link_speed & ETH_LINK_SPEED_100M)
2465                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2466         if (link_speed & ETH_LINK_SPEED_100M_HD)
2467                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2468         if (link_speed & ETH_LINK_SPEED_1G)
2469                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2470         if (link_speed & ETH_LINK_SPEED_2_5G)
2471                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2472         if (link_speed & ETH_LINK_SPEED_10G)
2473                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2474         if (link_speed & ETH_LINK_SPEED_20G)
2475                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2476         if (link_speed & ETH_LINK_SPEED_25G)
2477                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2478         if (link_speed & ETH_LINK_SPEED_40G)
2479                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2480         if (link_speed & ETH_LINK_SPEED_50G)
2481                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2482         if (link_speed & ETH_LINK_SPEED_100G)
2483                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2484         return ret;
2485 }
2486
2487 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2488 {
2489         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2490
2491         switch (hw_link_speed) {
2492         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2493                 eth_link_speed = ETH_SPEED_NUM_100M;
2494                 break;
2495         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2496                 eth_link_speed = ETH_SPEED_NUM_1G;
2497                 break;
2498         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2499                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2500                 break;
2501         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2502                 eth_link_speed = ETH_SPEED_NUM_10G;
2503                 break;
2504         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2505                 eth_link_speed = ETH_SPEED_NUM_20G;
2506                 break;
2507         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2508                 eth_link_speed = ETH_SPEED_NUM_25G;
2509                 break;
2510         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2511                 eth_link_speed = ETH_SPEED_NUM_40G;
2512                 break;
2513         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2514                 eth_link_speed = ETH_SPEED_NUM_50G;
2515                 break;
2516         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2517                 eth_link_speed = ETH_SPEED_NUM_100G;
2518                 break;
2519         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2520         default:
2521                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2522                         hw_link_speed);
2523                 break;
2524         }
2525         return eth_link_speed;
2526 }
2527
2528 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2529 {
2530         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2531
2532         switch (hw_link_duplex) {
2533         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2534         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2535                 /* FALLTHROUGH */
2536                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2537                 break;
2538         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2539                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2540                 break;
2541         default:
2542                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2543                         hw_link_duplex);
2544                 break;
2545         }
2546         return eth_link_duplex;
2547 }
2548
2549 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2550 {
2551         int rc = 0;
2552         struct bnxt_link_info *link_info = &bp->link_info;
2553
2554         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2555         if (rc) {
2556                 PMD_DRV_LOG(ERR,
2557                         "Get link config failed with rc %d\n", rc);
2558                 goto exit;
2559         }
2560         if (link_info->link_speed)
2561                 link->link_speed =
2562                         bnxt_parse_hw_link_speed(link_info->link_speed);
2563         else
2564                 link->link_speed = ETH_SPEED_NUM_NONE;
2565         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2566         link->link_status = link_info->link_up;
2567         link->link_autoneg = link_info->auto_mode ==
2568                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2569                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2570 exit:
2571         return rc;
2572 }
2573
2574 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2575 {
2576         int rc = 0;
2577         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2578         struct bnxt_link_info link_req;
2579         uint16_t speed, autoneg;
2580
2581         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2582                 return 0;
2583
2584         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2585                         bp->eth_dev->data->port_id);
2586         if (rc)
2587                 goto error;
2588
2589         memset(&link_req, 0, sizeof(link_req));
2590         link_req.link_up = link_up;
2591         if (!link_up)
2592                 goto port_phy_cfg;
2593
2594         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2595         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2596         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2597         /* Autoneg can be done only when the FW allows */
2598         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2599                                 bp->link_info.force_link_speed)) {
2600                 link_req.phy_flags |=
2601                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2602                 link_req.auto_link_speed_mask =
2603                         bnxt_parse_eth_link_speed_mask(bp,
2604                                                        dev_conf->link_speeds);
2605         } else {
2606                 if (bp->link_info.phy_type ==
2607                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2608                     bp->link_info.phy_type ==
2609                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2610                     bp->link_info.media_type ==
2611                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2612                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2613                         return -EINVAL;
2614                 }
2615
2616                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2617                 /* If user wants a particular speed try that first. */
2618                 if (speed)
2619                         link_req.link_speed = speed;
2620                 else if (bp->link_info.force_link_speed)
2621                         link_req.link_speed = bp->link_info.force_link_speed;
2622                 else
2623                         link_req.link_speed = bp->link_info.auto_link_speed;
2624         }
2625         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2626         link_req.auto_pause = bp->link_info.auto_pause;
2627         link_req.force_pause = bp->link_info.force_pause;
2628
2629 port_phy_cfg:
2630         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2631         if (rc) {
2632                 PMD_DRV_LOG(ERR,
2633                         "Set link config failed with rc %d\n", rc);
2634         }
2635
2636 error:
2637         return rc;
2638 }
2639
2640 /* JIRA 22088 */
2641 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2642 {
2643         struct hwrm_func_qcfg_input req = {0};
2644         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2645         uint16_t flags;
2646         int rc = 0;
2647
2648         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2649         req.fid = rte_cpu_to_le_16(0xffff);
2650
2651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2652
2653         HWRM_CHECK_RESULT();
2654
2655         /* Hard Coded.. 0xfff VLAN ID mask */
2656         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2657         flags = rte_le_to_cpu_16(resp->flags);
2658         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2659                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2660
2661         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2662                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2663                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2664         }
2665
2666         if (mtu)
2667                 *mtu = resp->mtu;
2668
2669         switch (resp->port_partition_type) {
2670         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2671         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2672         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2673                 /* FALLTHROUGH */
2674                 bp->port_partition_type = resp->port_partition_type;
2675                 break;
2676         default:
2677                 bp->port_partition_type = 0;
2678                 break;
2679         }
2680
2681         HWRM_UNLOCK();
2682
2683         return rc;
2684 }
2685
2686 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2687                                    struct hwrm_func_qcaps_output *qcaps)
2688 {
2689         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2690         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2691                sizeof(qcaps->mac_address));
2692         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2693         qcaps->max_rx_rings = fcfg->num_rx_rings;
2694         qcaps->max_tx_rings = fcfg->num_tx_rings;
2695         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2696         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2697         qcaps->max_vfs = 0;
2698         qcaps->first_vf_id = 0;
2699         qcaps->max_vnics = fcfg->num_vnics;
2700         qcaps->max_decap_records = 0;
2701         qcaps->max_encap_records = 0;
2702         qcaps->max_tx_wm_flows = 0;
2703         qcaps->max_tx_em_flows = 0;
2704         qcaps->max_rx_wm_flows = 0;
2705         qcaps->max_rx_em_flows = 0;
2706         qcaps->max_flow_id = 0;
2707         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2708         qcaps->max_sp_tx_rings = 0;
2709         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2710 }
2711
2712 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2713 {
2714         struct hwrm_func_cfg_input req = {0};
2715         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2716         uint32_t enables;
2717         int rc;
2718
2719         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2720                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2721                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2722                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2723                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2724                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2725                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2726                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2727                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2728
2729         if (BNXT_HAS_RING_GRPS(bp)) {
2730                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2731                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2732         } else if (BNXT_HAS_NQ(bp)) {
2733                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2734                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2735         }
2736
2737         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2738         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2739         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2740                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2741                                    BNXT_NUM_VLANS);
2742         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2743         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2744         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2745         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2746         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2747         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2748         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2749         req.fid = rte_cpu_to_le_16(0xffff);
2750         req.enables = rte_cpu_to_le_32(enables);
2751
2752         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2753
2754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2755
2756         HWRM_CHECK_RESULT();
2757         HWRM_UNLOCK();
2758
2759         return rc;
2760 }
2761
2762 static void populate_vf_func_cfg_req(struct bnxt *bp,
2763                                      struct hwrm_func_cfg_input *req,
2764                                      int num_vfs)
2765 {
2766         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2767                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2768                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2769                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2770                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2771                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2772                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2773                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2774                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2775                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2776
2777         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2778                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2779                                     BNXT_NUM_VLANS);
2780         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2781                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2782                                     BNXT_NUM_VLANS);
2783         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2784                                                 (num_vfs + 1));
2785         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2786         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2787                                                (num_vfs + 1));
2788         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2789         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2790         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2791         /* TODO: For now, do not support VMDq/RFS on VFs. */
2792         req->num_vnics = rte_cpu_to_le_16(1);
2793         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2794                                                  (num_vfs + 1));
2795 }
2796
2797 static void add_random_mac_if_needed(struct bnxt *bp,
2798                                      struct hwrm_func_cfg_input *cfg_req,
2799                                      int vf)
2800 {
2801         struct rte_ether_addr mac;
2802
2803         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2804                 return;
2805
2806         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2807                 cfg_req->enables |=
2808                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2809                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2810                 bp->pf.vf_info[vf].random_mac = true;
2811         } else {
2812                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2813                         RTE_ETHER_ADDR_LEN);
2814         }
2815 }
2816
2817 static void reserve_resources_from_vf(struct bnxt *bp,
2818                                       struct hwrm_func_cfg_input *cfg_req,
2819                                       int vf)
2820 {
2821         struct hwrm_func_qcaps_input req = {0};
2822         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2823         int rc;
2824
2825         /* Get the actual allocated values now */
2826         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2827         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2829
2830         if (rc) {
2831                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2832                 copy_func_cfg_to_qcaps(cfg_req, resp);
2833         } else if (resp->error_code) {
2834                 rc = rte_le_to_cpu_16(resp->error_code);
2835                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2836                 copy_func_cfg_to_qcaps(cfg_req, resp);
2837         }
2838
2839         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2840         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2841         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2842         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2843         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2844         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2845         /*
2846          * TODO: While not supporting VMDq with VFs, max_vnics is always
2847          * forced to 1 in this case
2848          */
2849         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2850         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2851
2852         HWRM_UNLOCK();
2853 }
2854
2855 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2856 {
2857         struct hwrm_func_qcfg_input req = {0};
2858         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2859         int rc;
2860
2861         /* Check for zero MAC address */
2862         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2863         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2865         if (rc) {
2866                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2867                 return -1;
2868         } else if (resp->error_code) {
2869                 rc = rte_le_to_cpu_16(resp->error_code);
2870                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2871                 return -1;
2872         }
2873         rc = rte_le_to_cpu_16(resp->vlan);
2874
2875         HWRM_UNLOCK();
2876
2877         return rc;
2878 }
2879
2880 static int update_pf_resource_max(struct bnxt *bp)
2881 {
2882         struct hwrm_func_qcfg_input req = {0};
2883         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2884         int rc;
2885
2886         /* And copy the allocated numbers into the pf struct */
2887         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2888         req.fid = rte_cpu_to_le_16(0xffff);
2889         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2890         HWRM_CHECK_RESULT();
2891
2892         /* Only TX ring value reflects actual allocation? TODO */
2893         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2894         bp->pf.evb_mode = resp->evb_mode;
2895
2896         HWRM_UNLOCK();
2897
2898         return rc;
2899 }
2900
2901 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2902 {
2903         int rc;
2904
2905         if (!BNXT_PF(bp)) {
2906                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2907                 return -1;
2908         }
2909
2910         rc = bnxt_hwrm_func_qcaps(bp);
2911         if (rc)
2912                 return rc;
2913
2914         bp->pf.func_cfg_flags &=
2915                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2916                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2917         bp->pf.func_cfg_flags |=
2918                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2919         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2920         rc = __bnxt_hwrm_func_qcaps(bp);
2921         return rc;
2922 }
2923
2924 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2925 {
2926         struct hwrm_func_cfg_input req = {0};
2927         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2928         int i;
2929         size_t sz;
2930         int rc = 0;
2931         size_t req_buf_sz;
2932
2933         if (!BNXT_PF(bp)) {
2934                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2935                 return -1;
2936         }
2937
2938         rc = bnxt_hwrm_func_qcaps(bp);
2939
2940         if (rc)
2941                 return rc;
2942
2943         bp->pf.active_vfs = num_vfs;
2944
2945         /*
2946          * First, configure the PF to only use one TX ring.  This ensures that
2947          * there are enough rings for all VFs.
2948          *
2949          * If we don't do this, when we call func_alloc() later, we will lock
2950          * extra rings to the PF that won't be available during func_cfg() of
2951          * the VFs.
2952          *
2953          * This has been fixed with firmware versions above 20.6.54
2954          */
2955         bp->pf.func_cfg_flags &=
2956                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2957                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2958         bp->pf.func_cfg_flags |=
2959                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2960         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2961         if (rc)
2962                 return rc;
2963
2964         /*
2965          * Now, create and register a buffer to hold forwarded VF requests
2966          */
2967         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2968         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2969                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2970         if (bp->pf.vf_req_buf == NULL) {
2971                 rc = -ENOMEM;
2972                 goto error_free;
2973         }
2974         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2975                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2976         for (i = 0; i < num_vfs; i++)
2977                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2978                                         (i * HWRM_MAX_REQ_LEN);
2979
2980         rc = bnxt_hwrm_func_buf_rgtr(bp);
2981         if (rc)
2982                 goto error_free;
2983
2984         populate_vf_func_cfg_req(bp, &req, num_vfs);
2985
2986         bp->pf.active_vfs = 0;
2987         for (i = 0; i < num_vfs; i++) {
2988                 add_random_mac_if_needed(bp, &req, i);
2989
2990                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2991                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2992                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2993                 rc = bnxt_hwrm_send_message(bp,
2994                                             &req,
2995                                             sizeof(req),
2996                                             BNXT_USE_CHIMP_MB);
2997
2998                 /* Clear enable flag for next pass */
2999                 req.enables &= ~rte_cpu_to_le_32(
3000                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3001
3002                 if (rc || resp->error_code) {
3003                         PMD_DRV_LOG(ERR,
3004                                 "Failed to initizlie VF %d\n", i);
3005                         PMD_DRV_LOG(ERR,
3006                                 "Not all VFs available. (%d, %d)\n",
3007                                 rc, resp->error_code);
3008                         HWRM_UNLOCK();
3009                         break;
3010                 }
3011
3012                 HWRM_UNLOCK();
3013
3014                 reserve_resources_from_vf(bp, &req, i);
3015                 bp->pf.active_vfs++;
3016                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3017         }
3018
3019         /*
3020          * Now configure the PF to use "the rest" of the resources
3021          * We're using STD_TX_RING_MODE here though which will limit the TX
3022          * rings.  This will allow QoS to function properly.  Not setting this
3023          * will cause PF rings to break bandwidth settings.
3024          */
3025         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3026         if (rc)
3027                 goto error_free;
3028
3029         rc = update_pf_resource_max(bp);
3030         if (rc)
3031                 goto error_free;
3032
3033         return rc;
3034
3035 error_free:
3036         bnxt_hwrm_func_buf_unrgtr(bp);
3037         return rc;
3038 }
3039
3040 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3041 {
3042         struct hwrm_func_cfg_input req = {0};
3043         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3044         int rc;
3045
3046         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3047
3048         req.fid = rte_cpu_to_le_16(0xffff);
3049         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3050         req.evb_mode = bp->pf.evb_mode;
3051
3052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3053         HWRM_CHECK_RESULT();
3054         HWRM_UNLOCK();
3055
3056         return rc;
3057 }
3058
3059 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3060                                 uint8_t tunnel_type)
3061 {
3062         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3063         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3064         int rc = 0;
3065
3066         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3067         req.tunnel_type = tunnel_type;
3068         req.tunnel_dst_port_val = port;
3069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3070         HWRM_CHECK_RESULT();
3071
3072         switch (tunnel_type) {
3073         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3074                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3075                 bp->vxlan_port = port;
3076                 break;
3077         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3078                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3079                 bp->geneve_port = port;
3080                 break;
3081         default:
3082                 break;
3083         }
3084
3085         HWRM_UNLOCK();
3086
3087         return rc;
3088 }
3089
3090 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3091                                 uint8_t tunnel_type)
3092 {
3093         struct hwrm_tunnel_dst_port_free_input req = {0};
3094         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3095         int rc = 0;
3096
3097         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3098
3099         req.tunnel_type = tunnel_type;
3100         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3101         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3102
3103         HWRM_CHECK_RESULT();
3104         HWRM_UNLOCK();
3105
3106         return rc;
3107 }
3108
3109 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3110                                         uint32_t flags)
3111 {
3112         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3113         struct hwrm_func_cfg_input req = {0};
3114         int rc;
3115
3116         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3117
3118         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3119         req.flags = rte_cpu_to_le_32(flags);
3120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3121
3122         HWRM_CHECK_RESULT();
3123         HWRM_UNLOCK();
3124
3125         return rc;
3126 }
3127
3128 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3129 {
3130         uint32_t *flag = flagp;
3131
3132         vnic->flags = *flag;
3133 }
3134
3135 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3136 {
3137         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3138 }
3139
3140 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3141 {
3142         int rc = 0;
3143         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3144         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3145
3146         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3147
3148         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3149         req.req_buf_page_size = rte_cpu_to_le_16(
3150                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3151         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3152         req.req_buf_page_addr0 =
3153                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3154         if (req.req_buf_page_addr0 == 0) {
3155                 PMD_DRV_LOG(ERR,
3156                         "unable to map buffer address to physical memory\n");
3157                 return -ENOMEM;
3158         }
3159
3160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3161
3162         HWRM_CHECK_RESULT();
3163         HWRM_UNLOCK();
3164
3165         return rc;
3166 }
3167
3168 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3169 {
3170         int rc = 0;
3171         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3172         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3173
3174         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3175
3176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3177
3178         HWRM_CHECK_RESULT();
3179         HWRM_UNLOCK();
3180
3181         return rc;
3182 }
3183
3184 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3185 {
3186         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3187         struct hwrm_func_cfg_input req = {0};
3188         int rc;
3189
3190         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3191
3192         req.fid = rte_cpu_to_le_16(0xffff);
3193         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3194         req.enables = rte_cpu_to_le_32(
3195                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3196         req.async_event_cr = rte_cpu_to_le_16(
3197                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3198         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3199
3200         HWRM_CHECK_RESULT();
3201         HWRM_UNLOCK();
3202
3203         return rc;
3204 }
3205
3206 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3207 {
3208         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3209         struct hwrm_func_vf_cfg_input req = {0};
3210         int rc;
3211
3212         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3213
3214         req.enables = rte_cpu_to_le_32(
3215                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3216         req.async_event_cr = rte_cpu_to_le_16(
3217                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3219
3220         HWRM_CHECK_RESULT();
3221         HWRM_UNLOCK();
3222
3223         return rc;
3224 }
3225
3226 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3227 {
3228         struct hwrm_func_cfg_input req = {0};
3229         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3230         uint16_t dflt_vlan, fid;
3231         uint32_t func_cfg_flags;
3232         int rc = 0;
3233
3234         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3235
3236         if (is_vf) {
3237                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3238                 fid = bp->pf.vf_info[vf].fid;
3239                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3240         } else {
3241                 fid = rte_cpu_to_le_16(0xffff);
3242                 func_cfg_flags = bp->pf.func_cfg_flags;
3243                 dflt_vlan = bp->vlan;
3244         }
3245
3246         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3247         req.fid = rte_cpu_to_le_16(fid);
3248         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3249         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3250
3251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3252
3253         HWRM_CHECK_RESULT();
3254         HWRM_UNLOCK();
3255
3256         return rc;
3257 }
3258
3259 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3260                         uint16_t max_bw, uint16_t enables)
3261 {
3262         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3263         struct hwrm_func_cfg_input req = {0};
3264         int rc;
3265
3266         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3267
3268         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3269         req.enables |= rte_cpu_to_le_32(enables);
3270         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3271         req.max_bw = rte_cpu_to_le_32(max_bw);
3272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3273
3274         HWRM_CHECK_RESULT();
3275         HWRM_UNLOCK();
3276
3277         return rc;
3278 }
3279
3280 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3281 {
3282         struct hwrm_func_cfg_input req = {0};
3283         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3284         int rc = 0;
3285
3286         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3287
3288         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3289         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3290         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3291         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3292
3293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3294
3295         HWRM_CHECK_RESULT();
3296         HWRM_UNLOCK();
3297
3298         return rc;
3299 }
3300
3301 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3302 {
3303         int rc;
3304
3305         if (BNXT_PF(bp))
3306                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3307         else
3308                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3309
3310         return rc;
3311 }
3312
3313 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3314                               void *encaped, size_t ec_size)
3315 {
3316         int rc = 0;
3317         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3318         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3319
3320         if (ec_size > sizeof(req.encap_request))
3321                 return -1;
3322
3323         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3324
3325         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3326         memcpy(req.encap_request, encaped, ec_size);
3327
3328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3329
3330         HWRM_CHECK_RESULT();
3331         HWRM_UNLOCK();
3332
3333         return rc;
3334 }
3335
3336 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3337                                        struct rte_ether_addr *mac)
3338 {
3339         struct hwrm_func_qcfg_input req = {0};
3340         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3341         int rc;
3342
3343         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3344
3345         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3347
3348         HWRM_CHECK_RESULT();
3349
3350         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3351
3352         HWRM_UNLOCK();
3353
3354         return rc;
3355 }
3356
3357 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3358                             void *encaped, size_t ec_size)
3359 {
3360         int rc = 0;
3361         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3362         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3363
3364         if (ec_size > sizeof(req.encap_request))
3365                 return -1;
3366
3367         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3368
3369         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3370         memcpy(req.encap_request, encaped, ec_size);
3371
3372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373
3374         HWRM_CHECK_RESULT();
3375         HWRM_UNLOCK();
3376
3377         return rc;
3378 }
3379
3380 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3381                          struct rte_eth_stats *stats, uint8_t rx)
3382 {
3383         int rc = 0;
3384         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3385         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3386
3387         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3388
3389         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3390
3391         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3392
3393         HWRM_CHECK_RESULT();
3394
3395         if (rx) {
3396                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3397                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3398                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3399                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3400                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3401                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3402                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3403                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3404         } else {
3405                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3406                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3407                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3408                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3409                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3410                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3411         }
3412
3413
3414         HWRM_UNLOCK();
3415
3416         return rc;
3417 }
3418
3419 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3420 {
3421         struct hwrm_port_qstats_input req = {0};
3422         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3423         struct bnxt_pf_info *pf = &bp->pf;
3424         int rc;
3425
3426         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3427
3428         req.port_id = rte_cpu_to_le_16(pf->port_id);
3429         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3430         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3431         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3432
3433         HWRM_CHECK_RESULT();
3434         HWRM_UNLOCK();
3435
3436         return rc;
3437 }
3438
3439 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3440 {
3441         struct hwrm_port_clr_stats_input req = {0};
3442         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3443         struct bnxt_pf_info *pf = &bp->pf;
3444         int rc;
3445
3446         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3447         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3448             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3449                 return 0;
3450
3451         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3452
3453         req.port_id = rte_cpu_to_le_16(pf->port_id);
3454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3455
3456         HWRM_CHECK_RESULT();
3457         HWRM_UNLOCK();
3458
3459         return rc;
3460 }
3461
3462 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3463 {
3464         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3465         struct hwrm_port_led_qcaps_input req = {0};
3466         int rc;
3467
3468         if (BNXT_VF(bp))
3469                 return 0;
3470
3471         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3472         req.port_id = bp->pf.port_id;
3473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3474
3475         HWRM_CHECK_RESULT();
3476
3477         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3478                 unsigned int i;
3479
3480                 bp->num_leds = resp->num_leds;
3481                 memcpy(bp->leds, &resp->led0_id,
3482                         sizeof(bp->leds[0]) * bp->num_leds);
3483                 for (i = 0; i < bp->num_leds; i++) {
3484                         struct bnxt_led_info *led = &bp->leds[i];
3485
3486                         uint16_t caps = led->led_state_caps;
3487
3488                         if (!led->led_group_id ||
3489                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3490                                 bp->num_leds = 0;
3491                                 break;
3492                         }
3493                 }
3494         }
3495
3496         HWRM_UNLOCK();
3497
3498         return rc;
3499 }
3500
3501 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3502 {
3503         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3504         struct hwrm_port_led_cfg_input req = {0};
3505         struct bnxt_led_cfg *led_cfg;
3506         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3507         uint16_t duration = 0;
3508         int rc, i;
3509
3510         if (!bp->num_leds || BNXT_VF(bp))
3511                 return -EOPNOTSUPP;
3512
3513         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3514
3515         if (led_on) {
3516                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3517                 duration = rte_cpu_to_le_16(500);
3518         }
3519         req.port_id = bp->pf.port_id;
3520         req.num_leds = bp->num_leds;
3521         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3522         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3523                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3524                 led_cfg->led_id = bp->leds[i].led_id;
3525                 led_cfg->led_state = led_state;
3526                 led_cfg->led_blink_on = duration;
3527                 led_cfg->led_blink_off = duration;
3528                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3529         }
3530
3531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3532
3533         HWRM_CHECK_RESULT();
3534         HWRM_UNLOCK();
3535
3536         return rc;
3537 }
3538
3539 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3540                                uint32_t *length)
3541 {
3542         int rc;
3543         struct hwrm_nvm_get_dir_info_input req = {0};
3544         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3545
3546         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3547
3548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3549
3550         HWRM_CHECK_RESULT();
3551         HWRM_UNLOCK();
3552
3553         if (!rc) {
3554                 *entries = rte_le_to_cpu_32(resp->entries);
3555                 *length = rte_le_to_cpu_32(resp->entry_length);
3556         }
3557         return rc;
3558 }
3559
3560 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3561 {
3562         int rc;
3563         uint32_t dir_entries;
3564         uint32_t entry_length;
3565         uint8_t *buf;
3566         size_t buflen;
3567         rte_iova_t dma_handle;
3568         struct hwrm_nvm_get_dir_entries_input req = {0};
3569         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3570
3571         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3572         if (rc != 0)
3573                 return rc;
3574
3575         *data++ = dir_entries;
3576         *data++ = entry_length;
3577         len -= 2;
3578         memset(data, 0xff, len);
3579
3580         buflen = dir_entries * entry_length;
3581         buf = rte_malloc("nvm_dir", buflen, 0);
3582         rte_mem_lock_page(buf);
3583         if (buf == NULL)
3584                 return -ENOMEM;
3585         dma_handle = rte_mem_virt2iova(buf);
3586         if (dma_handle == 0) {
3587                 PMD_DRV_LOG(ERR,
3588                         "unable to map response address to physical memory\n");
3589                 return -ENOMEM;
3590         }
3591         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3592         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3593         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3594
3595         if (rc == 0)
3596                 memcpy(data, buf, len > buflen ? buflen : len);
3597
3598         rte_free(buf);
3599         HWRM_CHECK_RESULT();
3600         HWRM_UNLOCK();
3601
3602         return rc;
3603 }
3604
3605 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3606                              uint32_t offset, uint32_t length,
3607                              uint8_t *data)
3608 {
3609         int rc;
3610         uint8_t *buf;
3611         rte_iova_t dma_handle;
3612         struct hwrm_nvm_read_input req = {0};
3613         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3614
3615         buf = rte_malloc("nvm_item", length, 0);
3616         rte_mem_lock_page(buf);
3617         if (!buf)
3618                 return -ENOMEM;
3619
3620         dma_handle = rte_mem_virt2iova(buf);
3621         if (dma_handle == 0) {
3622                 PMD_DRV_LOG(ERR,
3623                         "unable to map response address to physical memory\n");
3624                 return -ENOMEM;
3625         }
3626         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3627         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3628         req.dir_idx = rte_cpu_to_le_16(index);
3629         req.offset = rte_cpu_to_le_32(offset);
3630         req.len = rte_cpu_to_le_32(length);
3631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3632         if (rc == 0)
3633                 memcpy(data, buf, length);
3634
3635         rte_free(buf);
3636         HWRM_CHECK_RESULT();
3637         HWRM_UNLOCK();
3638
3639         return rc;
3640 }
3641
3642 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3643 {
3644         int rc;
3645         struct hwrm_nvm_erase_dir_entry_input req = {0};
3646         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3647
3648         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3649         req.dir_idx = rte_cpu_to_le_16(index);
3650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651         HWRM_CHECK_RESULT();
3652         HWRM_UNLOCK();
3653
3654         return rc;
3655 }
3656
3657
3658 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3659                           uint16_t dir_ordinal, uint16_t dir_ext,
3660                           uint16_t dir_attr, const uint8_t *data,
3661                           size_t data_len)
3662 {
3663         int rc;
3664         struct hwrm_nvm_write_input req = {0};
3665         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3666         rte_iova_t dma_handle;
3667         uint8_t *buf;
3668
3669         buf = rte_malloc("nvm_write", data_len, 0);
3670         rte_mem_lock_page(buf);
3671         if (!buf)
3672                 return -ENOMEM;
3673
3674         dma_handle = rte_mem_virt2iova(buf);
3675         if (dma_handle == 0) {
3676                 PMD_DRV_LOG(ERR,
3677                         "unable to map response address to physical memory\n");
3678                 return -ENOMEM;
3679         }
3680         memcpy(buf, data, data_len);
3681
3682         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3683
3684         req.dir_type = rte_cpu_to_le_16(dir_type);
3685         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3686         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3687         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3688         req.dir_data_length = rte_cpu_to_le_32(data_len);
3689         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3690
3691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3692
3693         rte_free(buf);
3694         HWRM_CHECK_RESULT();
3695         HWRM_UNLOCK();
3696
3697         return rc;
3698 }
3699
3700 static void
3701 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3702 {
3703         uint32_t *count = cbdata;
3704
3705         *count = *count + 1;
3706 }
3707
3708 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3709                                      struct bnxt_vnic_info *vnic __rte_unused)
3710 {
3711         return 0;
3712 }
3713
3714 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3715 {
3716         uint32_t count = 0;
3717
3718         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3719             &count, bnxt_vnic_count_hwrm_stub);
3720
3721         return count;
3722 }
3723
3724 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3725                                         uint16_t *vnic_ids)
3726 {
3727         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3728         struct hwrm_func_vf_vnic_ids_query_output *resp =
3729                                                 bp->hwrm_cmd_resp_addr;
3730         int rc;
3731
3732         /* First query all VNIC ids */
3733         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3734
3735         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3736         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3737         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3738
3739         if (req.vnic_id_tbl_addr == 0) {
3740                 HWRM_UNLOCK();
3741                 PMD_DRV_LOG(ERR,
3742                 "unable to map VNIC ID table address to physical memory\n");
3743                 return -ENOMEM;
3744         }
3745         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3746         if (rc) {
3747                 HWRM_UNLOCK();
3748                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3749                 return -1;
3750         } else if (resp->error_code) {
3751                 rc = rte_le_to_cpu_16(resp->error_code);
3752                 HWRM_UNLOCK();
3753                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3754                 return -1;
3755         }
3756         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3757
3758         HWRM_UNLOCK();
3759
3760         return rc;
3761 }
3762
3763 /*
3764  * This function queries the VNIC IDs  for a specified VF. It then calls
3765  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3766  * Then it calls the hwrm_cb function to program this new vnic configuration.
3767  */
3768 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3769         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3770         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3771 {
3772         struct bnxt_vnic_info vnic;
3773         int rc = 0;
3774         int i, num_vnic_ids;
3775         uint16_t *vnic_ids;
3776         size_t vnic_id_sz;
3777         size_t sz;
3778
3779         /* First query all VNIC ids */
3780         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3781         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3782                         RTE_CACHE_LINE_SIZE);
3783         if (vnic_ids == NULL) {
3784                 rc = -ENOMEM;
3785                 return rc;
3786         }
3787         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3788                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3789
3790         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3791
3792         if (num_vnic_ids < 0)
3793                 return num_vnic_ids;
3794
3795         /* Retrieve VNIC, update bd_stall then update */
3796
3797         for (i = 0; i < num_vnic_ids; i++) {
3798                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3799                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3800                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3801                 if (rc)
3802                         break;
3803                 if (vnic.mru <= 4)      /* Indicates unallocated */
3804                         continue;
3805
3806                 vnic_cb(&vnic, cbdata);
3807
3808                 rc = hwrm_cb(bp, &vnic);
3809                 if (rc)
3810                         break;
3811         }
3812
3813         rte_free(vnic_ids);
3814
3815         return rc;
3816 }
3817
3818 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3819                                               bool on)
3820 {
3821         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3822         struct hwrm_func_cfg_input req = {0};
3823         int rc;
3824
3825         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3826
3827         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3828         req.enables |= rte_cpu_to_le_32(
3829                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3830         req.vlan_antispoof_mode = on ?
3831                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3832                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3833         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3834
3835         HWRM_CHECK_RESULT();
3836         HWRM_UNLOCK();
3837
3838         return rc;
3839 }
3840
3841 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3842 {
3843         struct bnxt_vnic_info vnic;
3844         uint16_t *vnic_ids;
3845         size_t vnic_id_sz;
3846         int num_vnic_ids, i;
3847         size_t sz;
3848         int rc;
3849
3850         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3851         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3852                         RTE_CACHE_LINE_SIZE);
3853         if (vnic_ids == NULL) {
3854                 rc = -ENOMEM;
3855                 return rc;
3856         }
3857
3858         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3859                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3860
3861         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3862         if (rc <= 0)
3863                 goto exit;
3864         num_vnic_ids = rc;
3865
3866         /*
3867          * Loop through to find the default VNIC ID.
3868          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3869          * by sending the hwrm_func_qcfg command to the firmware.
3870          */
3871         for (i = 0; i < num_vnic_ids; i++) {
3872                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3873                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3874                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3875                                         bp->pf.first_vf_id + vf);
3876                 if (rc)
3877                         goto exit;
3878                 if (vnic.func_default) {
3879                         rte_free(vnic_ids);
3880                         return vnic.fw_vnic_id;
3881                 }
3882         }
3883         /* Could not find a default VNIC. */
3884         PMD_DRV_LOG(ERR, "No default VNIC\n");
3885 exit:
3886         rte_free(vnic_ids);
3887         return -1;
3888 }
3889
3890 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3891                          uint16_t dst_id,
3892                          struct bnxt_filter_info *filter)
3893 {
3894         int rc = 0;
3895         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3896         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3897         uint32_t enables = 0;
3898
3899         if (filter->fw_em_filter_id != UINT64_MAX)
3900                 bnxt_hwrm_clear_em_filter(bp, filter);
3901
3902         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3903
3904         req.flags = rte_cpu_to_le_32(filter->flags);
3905
3906         enables = filter->enables |
3907               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3908         req.dst_id = rte_cpu_to_le_16(dst_id);
3909
3910         if (filter->ip_addr_type) {
3911                 req.ip_addr_type = filter->ip_addr_type;
3912                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3913         }
3914         if (enables &
3915             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3916                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3917         if (enables &
3918             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3919                 memcpy(req.src_macaddr, filter->src_macaddr,
3920                        RTE_ETHER_ADDR_LEN);
3921         if (enables &
3922             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3923                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3924                        RTE_ETHER_ADDR_LEN);
3925         if (enables &
3926             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3927                 req.ovlan_vid = filter->l2_ovlan;
3928         if (enables &
3929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3930                 req.ivlan_vid = filter->l2_ivlan;
3931         if (enables &
3932             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3933                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3934         if (enables &
3935             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3936                 req.ip_protocol = filter->ip_protocol;
3937         if (enables &
3938             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3939                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3940         if (enables &
3941             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3942                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3943         if (enables &
3944             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3945                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3946         if (enables &
3947             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3948                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3949         if (enables &
3950             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3951                 req.mirror_vnic_id = filter->mirror_vnic_id;
3952
3953         req.enables = rte_cpu_to_le_32(enables);
3954
3955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3956
3957         HWRM_CHECK_RESULT();
3958
3959         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3960         HWRM_UNLOCK();
3961
3962         return rc;
3963 }
3964
3965 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3966 {
3967         int rc = 0;
3968         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3969         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3970
3971         if (filter->fw_em_filter_id == UINT64_MAX)
3972                 return 0;
3973
3974         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3975         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3976
3977         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3978
3979         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3980
3981         HWRM_CHECK_RESULT();
3982         HWRM_UNLOCK();
3983
3984         filter->fw_em_filter_id = UINT64_MAX;
3985         filter->fw_l2_filter_id = UINT64_MAX;
3986
3987         return 0;
3988 }
3989
3990 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3991                          uint16_t dst_id,
3992                          struct bnxt_filter_info *filter)
3993 {
3994         int rc = 0;
3995         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3996         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3997                                                 bp->hwrm_cmd_resp_addr;
3998         uint32_t enables = 0;
3999
4000         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4001                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4002
4003         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4004
4005         req.flags = rte_cpu_to_le_32(filter->flags);
4006
4007         enables = filter->enables |
4008               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4009         req.dst_id = rte_cpu_to_le_16(dst_id);
4010
4011
4012         if (filter->ip_addr_type) {
4013                 req.ip_addr_type = filter->ip_addr_type;
4014                 enables |=
4015                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4016         }
4017         if (enables &
4018             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4019                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4020         if (enables &
4021             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4022                 memcpy(req.src_macaddr, filter->src_macaddr,
4023                        RTE_ETHER_ADDR_LEN);
4024         //if (enables &
4025             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4026                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4027                        //RTE_ETHER_ADDR_LEN);
4028         if (enables &
4029             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4030                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4031         if (enables &
4032             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4033                 req.ip_protocol = filter->ip_protocol;
4034         if (enables &
4035             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4036                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4037         if (enables &
4038             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4039                 req.src_ipaddr_mask[0] =
4040                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4041         if (enables &
4042             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4043                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4044         if (enables &
4045             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4046                 req.dst_ipaddr_mask[0] =
4047                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4048         if (enables &
4049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4050                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4051         if (enables &
4052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4053                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4054         if (enables &
4055             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4056                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4057         if (enables &
4058             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4059                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4060         if (enables &
4061             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4062                 req.mirror_vnic_id = filter->mirror_vnic_id;
4063
4064         req.enables = rte_cpu_to_le_32(enables);
4065
4066         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4067
4068         HWRM_CHECK_RESULT();
4069
4070         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4071         HWRM_UNLOCK();
4072
4073         return rc;
4074 }
4075
4076 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4077                                 struct bnxt_filter_info *filter)
4078 {
4079         int rc = 0;
4080         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4081         struct hwrm_cfa_ntuple_filter_free_output *resp =
4082                                                 bp->hwrm_cmd_resp_addr;
4083
4084         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4085                 return 0;
4086
4087         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4088
4089         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4090
4091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4092
4093         HWRM_CHECK_RESULT();
4094         HWRM_UNLOCK();
4095
4096         filter->fw_ntuple_filter_id = UINT64_MAX;
4097
4098         return 0;
4099 }
4100
4101 static int
4102 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4103 {
4104         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4105         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4106         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4107         int nr_ctxs = bp->max_ring_grps;
4108         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4109         uint16_t *ring_tbl = vnic->rss_table;
4110         int max_rings = bp->rx_nr_rings;
4111         int i, j, k, cnt;
4112         int rc = 0;
4113
4114         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4115
4116         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4117         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4118         req.hash_mode_flags = vnic->hash_mode;
4119
4120         req.ring_grp_tbl_addr =
4121             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4122         req.hash_key_tbl_addr =
4123             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4124
4125         for (i = 0, k = 0; i < nr_ctxs; i++) {
4126                 struct bnxt_rx_ring_info *rxr;
4127                 struct bnxt_cp_ring_info *cpr;
4128
4129                 req.ring_table_pair_index = i;
4130                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4131
4132                 for (j = 0; j < 64; j++) {
4133                         uint16_t ring_id;
4134
4135                         /* Find next active ring. */
4136                         for (cnt = 0; cnt < max_rings; cnt++) {
4137                                 if (rx_queue_state[k] !=
4138                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4139                                         break;
4140                                 if (++k == max_rings)
4141                                         k = 0;
4142                         }
4143
4144                         /* Return if no rings are active. */
4145                         if (cnt == max_rings)
4146                                 return 0;
4147
4148                         /* Add rx/cp ring pair to RSS table. */
4149                         rxr = rxqs[k]->rx_ring;
4150                         cpr = rxqs[k]->cp_ring;
4151
4152                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4153                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4154                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4155                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4156
4157                         if (++k == max_rings)
4158                                 k = 0;
4159                 }
4160                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4161                                             BNXT_USE_CHIMP_MB);
4162
4163                 HWRM_CHECK_RESULT();
4164                 if (rc)
4165                         break;
4166         }
4167
4168         HWRM_UNLOCK();
4169
4170         return rc;
4171 }
4172
4173 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4174 {
4175         unsigned int rss_idx, fw_idx, i;
4176
4177         if (!(vnic->rss_table && vnic->hash_type))
4178                 return 0;
4179
4180         if (BNXT_CHIP_THOR(bp))
4181                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4182
4183         /*
4184          * Fill the RSS hash & redirection table with
4185          * ring group ids for all VNICs
4186          */
4187         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4188                 rss_idx++, fw_idx++) {
4189                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4190                         fw_idx %= bp->rx_cp_nr_rings;
4191                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4192                                 break;
4193                         fw_idx++;
4194                 }
4195                 if (i == bp->rx_cp_nr_rings)
4196                         return 0;
4197                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4198         }
4199         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4200 }
4201
4202 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4203         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4204 {
4205         uint16_t flags;
4206
4207         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4208
4209         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4210         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4211
4212         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4213         req->num_cmpl_dma_aggr_during_int =
4214                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4215
4216         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4217
4218         /* min timer set to 1/2 of interrupt timer */
4219         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4220
4221         /* buf timer set to 1/4 of interrupt timer */
4222         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4223
4224         req->cmpl_aggr_dma_tmr_during_int =
4225                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4226
4227         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4228                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4229         req->flags = rte_cpu_to_le_16(flags);
4230 }
4231
4232 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4233                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4234 {
4235         struct hwrm_ring_aggint_qcaps_input req = {0};
4236         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4237         uint32_t enables;
4238         uint16_t flags;
4239         int rc;
4240
4241         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4242         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4243         if (rc)
4244                 goto out;
4245
4246         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4247         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4248
4249         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4250                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4251         agg_req->flags = rte_cpu_to_le_16(flags);
4252         enables =
4253          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4254          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4255         agg_req->enables = rte_cpu_to_le_32(enables);
4256
4257 out:
4258         HWRM_CHECK_RESULT();
4259         HWRM_UNLOCK();
4260         return rc;
4261 }
4262
4263 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4264                         struct bnxt_coal *coal, uint16_t ring_id)
4265 {
4266         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4267         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4268                                                 bp->hwrm_cmd_resp_addr;
4269         int rc;
4270
4271         /* Set ring coalesce parameters only for 100G NICs */
4272         if (BNXT_CHIP_THOR(bp)) {
4273                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4274                         return -1;
4275         } else if (bnxt_stratus_device(bp)) {
4276                 bnxt_hwrm_set_coal_params(coal, &req);
4277         } else {
4278                 return 0;
4279         }
4280
4281         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4282         req.ring_id = rte_cpu_to_le_16(ring_id);
4283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4284         HWRM_CHECK_RESULT();
4285         HWRM_UNLOCK();
4286         return 0;
4287 }
4288
4289 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4290 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4291 {
4292         struct hwrm_func_backing_store_qcaps_input req = {0};
4293         struct hwrm_func_backing_store_qcaps_output *resp =
4294                 bp->hwrm_cmd_resp_addr;
4295         int rc;
4296
4297         if (!BNXT_CHIP_THOR(bp) ||
4298             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4299             BNXT_VF(bp) ||
4300             bp->ctx)
4301                 return 0;
4302
4303         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4305         HWRM_CHECK_RESULT_SILENT();
4306
4307         if (!rc) {
4308                 struct bnxt_ctx_pg_info *ctx_pg;
4309                 struct bnxt_ctx_mem_info *ctx;
4310                 int total_alloc_len;
4311                 int i;
4312
4313                 total_alloc_len = sizeof(*ctx);
4314                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4315                                  RTE_CACHE_LINE_SIZE);
4316                 if (!ctx) {
4317                         rc = -ENOMEM;
4318                         goto ctx_err;
4319                 }
4320                 memset(ctx, 0, total_alloc_len);
4321
4322                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4323                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4324                                     RTE_CACHE_LINE_SIZE);
4325                 if (!ctx_pg) {
4326                         rc = -ENOMEM;
4327                         goto ctx_err;
4328                 }
4329                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4330                         ctx->tqm_mem[i] = ctx_pg;
4331
4332                 bp->ctx = ctx;
4333                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4334                 ctx->qp_min_qp1_entries =
4335                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4336                 ctx->qp_max_l2_entries =
4337                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4338                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4339                 ctx->srq_max_l2_entries =
4340                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4341                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4342                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4343                 ctx->cq_max_l2_entries =
4344                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4345                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4346                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4347                 ctx->vnic_max_vnic_entries =
4348                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4349                 ctx->vnic_max_ring_table_entries =
4350                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4351                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4352                 ctx->stat_max_entries =
4353                         rte_le_to_cpu_32(resp->stat_max_entries);
4354                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4355                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4356                 ctx->tqm_min_entries_per_ring =
4357                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4358                 ctx->tqm_max_entries_per_ring =
4359                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4360                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4361                 if (!ctx->tqm_entries_multiple)
4362                         ctx->tqm_entries_multiple = 1;
4363                 ctx->mrav_max_entries =
4364                         rte_le_to_cpu_32(resp->mrav_max_entries);
4365                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4366                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4367                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4368         } else {
4369                 rc = 0;
4370         }
4371 ctx_err:
4372         HWRM_UNLOCK();
4373         return rc;
4374 }
4375
4376 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4377 {
4378         struct hwrm_func_backing_store_cfg_input req = {0};
4379         struct hwrm_func_backing_store_cfg_output *resp =
4380                 bp->hwrm_cmd_resp_addr;
4381         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4382         struct bnxt_ctx_pg_info *ctx_pg;
4383         uint32_t *num_entries;
4384         uint64_t *pg_dir;
4385         uint8_t *pg_attr;
4386         uint32_t ena;
4387         int i, rc;
4388
4389         if (!ctx)
4390                 return 0;
4391
4392         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4393         req.enables = rte_cpu_to_le_32(enables);
4394
4395         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4396                 ctx_pg = &ctx->qp_mem;
4397                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4398                 req.qp_num_qp1_entries =
4399                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4400                 req.qp_num_l2_entries =
4401                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4402                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4403                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4404                                       &req.qpc_pg_size_qpc_lvl,
4405                                       &req.qpc_page_dir);
4406         }
4407
4408         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4409                 ctx_pg = &ctx->srq_mem;
4410                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4411                 req.srq_num_l2_entries =
4412                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4413                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4414                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4415                                       &req.srq_pg_size_srq_lvl,
4416                                       &req.srq_page_dir);
4417         }
4418
4419         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4420                 ctx_pg = &ctx->cq_mem;
4421                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4422                 req.cq_num_l2_entries =
4423                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4424                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4425                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4426                                       &req.cq_pg_size_cq_lvl,
4427                                       &req.cq_page_dir);
4428         }
4429
4430         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4431                 ctx_pg = &ctx->vnic_mem;
4432                 req.vnic_num_vnic_entries =
4433                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4434                 req.vnic_num_ring_table_entries =
4435                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4436                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4437                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4438                                       &req.vnic_pg_size_vnic_lvl,
4439                                       &req.vnic_page_dir);
4440         }
4441
4442         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4443                 ctx_pg = &ctx->stat_mem;
4444                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4445                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4446                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4447                                       &req.stat_pg_size_stat_lvl,
4448                                       &req.stat_page_dir);
4449         }
4450
4451         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4452         num_entries = &req.tqm_sp_num_entries;
4453         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4454         pg_dir = &req.tqm_sp_page_dir;
4455         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4456         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4457                 if (!(enables & ena))
4458                         continue;
4459
4460                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4461
4462                 ctx_pg = ctx->tqm_mem[i];
4463                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4464                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4465         }
4466
4467         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4468         HWRM_CHECK_RESULT();
4469         HWRM_UNLOCK();
4470         if (rc)
4471                 rc = -EIO;
4472         return rc;
4473 }
4474
4475 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4476 {
4477         struct hwrm_port_qstats_ext_input req = {0};
4478         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4479         struct bnxt_pf_info *pf = &bp->pf;
4480         int rc;
4481
4482         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4483               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4484                 return 0;
4485
4486         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4487
4488         req.port_id = rte_cpu_to_le_16(pf->port_id);
4489         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4490                 req.tx_stat_host_addr =
4491                         rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4492                 req.tx_stat_size =
4493                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4494         }
4495         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4496                 req.rx_stat_host_addr =
4497                         rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4498                 req.rx_stat_size =
4499                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4500         }
4501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4502
4503         if (rc) {
4504                 bp->fw_rx_port_stats_ext_size = 0;
4505                 bp->fw_tx_port_stats_ext_size = 0;
4506         } else {
4507                 bp->fw_rx_port_stats_ext_size =
4508                         rte_le_to_cpu_16(resp->rx_stat_size);
4509                 bp->fw_tx_port_stats_ext_size =
4510                         rte_le_to_cpu_16(resp->tx_stat_size);
4511         }
4512
4513         HWRM_CHECK_RESULT();
4514         HWRM_UNLOCK();
4515
4516         return rc;
4517 }
4518
4519 int
4520 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4521 {
4522         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4523         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4524                 bp->hwrm_cmd_resp_addr;
4525         int rc = 0;
4526
4527         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4528         req.tunnel_type = type;
4529         req.dest_fid = bp->fw_fid;
4530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4531         HWRM_CHECK_RESULT();
4532
4533         HWRM_UNLOCK();
4534
4535         return rc;
4536 }
4537
4538 int
4539 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4540 {
4541         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4542         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4543                 bp->hwrm_cmd_resp_addr;
4544         int rc = 0;
4545
4546         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4547         req.tunnel_type = type;
4548         req.dest_fid = bp->fw_fid;
4549         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4550         HWRM_CHECK_RESULT();
4551
4552         HWRM_UNLOCK();
4553
4554         return rc;
4555 }
4556
4557 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4558 {
4559         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4560         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4561                 bp->hwrm_cmd_resp_addr;
4562         int rc = 0;
4563
4564         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4565         req.src_fid = bp->fw_fid;
4566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4567         HWRM_CHECK_RESULT();
4568
4569         if (type)
4570                 *type = resp->tunnel_mask;
4571
4572         HWRM_UNLOCK();
4573
4574         return rc;
4575 }
4576
4577 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4578                                    uint16_t *dst_fid)
4579 {
4580         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4581         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4582                 bp->hwrm_cmd_resp_addr;
4583         int rc = 0;
4584
4585         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4586         req.src_fid = bp->fw_fid;
4587         req.tunnel_type = tun_type;
4588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4589         HWRM_CHECK_RESULT();
4590
4591         if (dst_fid)
4592                 *dst_fid = resp->dest_fid;
4593
4594         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4595
4596         HWRM_UNLOCK();
4597
4598         return rc;
4599 }