drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 223                         rc = -ENOSPC; \
 224                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 225                         rc = -EINVAL; \
 226                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 227                         rc = -ENOTSUP; \
 228                 else if (rc > 0) \
 229                         rc = -EIO; \
 230                 return rc; \
 231         } \
 232         if (resp->error_code) { \
 233                 rc = rte_le_to_cpu_16(resp->error_code); \
 234                 if (resp->resp_len >= 16) { \
 235                         struct hwrm_err_output *tmp_hwrm_err_op = \
 236                                                 (void *)resp; \
 237                         PMD_DRV_LOG(ERR, \
 238                                 "error %d:%d:%08x:%04x\n", \
 239                                 rc, tmp_hwrm_err_op->cmd_err, \
 240                                 rte_le_to_cpu_32(\
 241                                         tmp_hwrm_err_op->opaque_0), \
 242                                 rte_le_to_cpu_16(\
 243                                         tmp_hwrm_err_op->opaque_1)); \
 244                 } else { \
 245                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 246                 } \
 247                 rte_spinlock_unlock(&bp->hwrm_lock); \
 248                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 249                         rc = -EACCES; \
 250                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 251                         rc = -ENOSPC; \
 252                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 253                         rc = -EINVAL; \
 254                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 255                         rc = -ENOTSUP; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 268         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 269
 270         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 272         req.mask = 0;
 273
 274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 275
 276         HWRM_CHECK_RESULT();
 277         HWRM_UNLOCK();
 278
 279         return rc;
 280 }
 281
 282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 283                                  struct bnxt_vnic_info *vnic,
 284                                  uint16_t vlan_count,
 285                                  struct bnxt_vlan_table_entry *vlan_table)
 286 {
 287         int rc = 0;
 288         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 289         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 290         uint32_t mask = 0;
 291
 292         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 293                 return rc;
 294
 295         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 297
 298         /* FIXME add multicast flag, when multicast adding options is supported
 299          * by ethtool.
 300          */
 301         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 302                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 303         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 304                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 305         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 306                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 307         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 308                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 309         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 310                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 311         if (vnic->mc_addr_cnt) {
 312                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 313                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 314                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 315         }
 316         if (vlan_table) {
 317                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 318                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 319                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 320                          rte_mem_virt2iova(vlan_table));
 321                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 322         }
 323         req.mask = rte_cpu_to_le_32(mask);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 326
 327         HWRM_CHECK_RESULT();
 328         HWRM_UNLOCK();
 329
 330         return rc;
 331 }
 332
 333 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 334                         uint16_t vlan_count,
 335                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 336 {
 337         int rc = 0;
 338         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 339         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 340                                                 bp->hwrm_cmd_resp_addr;
 341
 342         /*
 343          * Older HWRM versions did not support this command, and the set_rx_mask
 344          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 345          * removed from set_rx_mask call, and this command was added.
 346          *
 347          * This command is also present from 1.7.8.11 and higher,
 348          * as well as 1.7.8.0
 349          */
 350         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 351                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 352                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 353                                         (11)))
 354                                 return 0;
 355                 }
 356         }
 357         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 358         req.fid = rte_cpu_to_le_16(fid);
 359
 360         req.vlan_tag_mask_tbl_addr =
 361                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 362         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 363
 364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 365
 366         HWRM_CHECK_RESULT();
 367         HWRM_UNLOCK();
 368
 369         return rc;
 370 }
 371
 372 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 373                            struct bnxt_filter_info *filter)
 374 {
 375         int rc = 0;
 376         struct bnxt_filter_info *l2_filter = filter;
 377         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 378         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 379
 380         if (filter->fw_l2_filter_id == UINT64_MAX)
 381                 return 0;
 382
 383         if (filter->matching_l2_fltr_ptr)
 384                 l2_filter = filter->matching_l2_fltr_ptr;
 385
 386         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 387                     filter, l2_filter, l2_filter->l2_ref_cnt);
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 l2_filter->l2_ref_cnt--;
 391
 392         if (l2_filter->l2_ref_cnt > 0)
 393                 return 0;
 394
 395         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 396
 397         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 398
 399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 400
 401         HWRM_CHECK_RESULT();
 402         HWRM_UNLOCK();
 403
 404         filter->fw_l2_filter_id = UINT64_MAX;
 405
 406         return 0;
 407 }
 408
 409 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 410                          uint16_t dst_id,
 411                          struct bnxt_filter_info *filter)
 412 {
 413         int rc = 0;
 414         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 415         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 416         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 417         const struct rte_eth_vmdq_rx_conf *conf =
 418                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 419         uint32_t enables = 0;
 420         uint16_t j = dst_id - 1;
 421
 422         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 423         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 424             conf->pool_map[j].pools & (1UL << j)) {
 425                 PMD_DRV_LOG(DEBUG,
 426                         "Add vlan %u to vmdq pool %u\n",
 427                         conf->pool_map[j].vlan_id, j);
 428
 429                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 430                 filter->enables |=
 431                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 432                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 433         }
 434
 435         if (filter->fw_l2_filter_id != UINT64_MAX)
 436                 bnxt_hwrm_clear_l2_filter(bp, filter);
 437
 438         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 439
 440         req.flags = rte_cpu_to_le_32(filter->flags);
 441
 442         enables = filter->enables |
 443               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 444         req.dst_id = rte_cpu_to_le_16(dst_id);
 445
 446         if (enables &
 447             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 448                 memcpy(req.l2_addr, filter->l2_addr,
 449                        RTE_ETHER_ADDR_LEN);
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 452                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 453                        RTE_ETHER_ADDR_LEN);
 454         if (enables &
 455             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 456                 req.l2_ovlan = filter->l2_ovlan;
 457         if (enables &
 458             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 459                 req.l2_ivlan = filter->l2_ivlan;
 460         if (enables &
 461             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 462                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 463         if (enables &
 464             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 465                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 466         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 467                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 468         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 469                 req.src_type = filter->src_type;
 470         if (filter->pri_hint) {
 471                 req.pri_hint = filter->pri_hint;
 472                 req.l2_filter_id_hint =
 473                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 474         }
 475
 476         req.enables = rte_cpu_to_le_32(enables);
 477
 478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 479
 480         HWRM_CHECK_RESULT();
 481
 482         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 483         HWRM_UNLOCK();
 484
 485         return rc;
 486 }
 487
 488 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 489 {
 490         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 491         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 492         uint32_t flags = 0;
 493         int rc;
 494
 495         if (!ptp)
 496                 return 0;
 497
 498         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 499
 500         if (ptp->rx_filter)
 501                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 502         else
 503                 flags |=
 504                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 505         if (ptp->tx_tstamp_en)
 506                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 507         else
 508                 flags |=
 509                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 510         req.flags = rte_cpu_to_le_32(flags);
 511         req.enables = rte_cpu_to_le_32
 512                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 513         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 514
 515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 516         HWRM_UNLOCK();
 517
 518         return rc;
 519 }
 520
 521 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 522 {
 523         int rc = 0;
 524         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 525         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 526         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 527
 528 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 529         if (ptp)
 530                 return 0;
 531
 532         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 533
 534         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 535
 536         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 537
 538         HWRM_CHECK_RESULT();
 539
 540         if (!BNXT_CHIP_THOR(bp) &&
 541             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 542                 return 0;
 543
 544         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 545                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 546
 547         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 548         if (!ptp)
 549                 return -ENOMEM;
 550
 551         if (!BNXT_CHIP_THOR(bp)) {
 552                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 554                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 555                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 556                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 557                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 558                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 559                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 560                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 561                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 562                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 563                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 564                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 565                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 566                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 567                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 568                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 569                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 570         }
 571
 572         ptp->bp = bp;
 573         bp->ptp_cfg = ptp;
 574
 575         return 0;
 576 }
 577
 578 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 579 {
 580         int rc = 0;
 581         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 582         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 583         uint16_t new_max_vfs;
 584         uint32_t flags;
 585         int i;
 586
 587         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 588
 589         req.fid = rte_cpu_to_le_16(0xffff);
 590
 591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 592
 593         HWRM_CHECK_RESULT();
 594
 595         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 596         flags = rte_le_to_cpu_32(resp->flags);
 597         if (BNXT_PF(bp)) {
 598                 bp->pf.port_id = resp->port_id;
 599                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 600                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 601                 new_max_vfs = bp->pdev->max_vfs;
 602                 if (new_max_vfs != bp->pf.max_vfs) {
 603                         if (bp->pf.vf_info)
 604                                 rte_free(bp->pf.vf_info);
 605                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 606                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 607                         bp->pf.max_vfs = new_max_vfs;
 608                         for (i = 0; i < new_max_vfs; i++) {
 609                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 610                                 bp->pf.vf_info[i].vlan_table =
 611                                         rte_zmalloc("VF VLAN table",
 612                                                     getpagesize(),
 613                                                     getpagesize());
 614                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 615                                         PMD_DRV_LOG(ERR,
 616                                         "Fail to alloc VLAN table for VF %d\n",
 617                                         i);
 618                                 else
 619                                         rte_mem_lock_page(
 620                                                 bp->pf.vf_info[i].vlan_table);
 621                                 bp->pf.vf_info[i].vlan_as_table =
 622                                         rte_zmalloc("VF VLAN AS table",
 623                                                     getpagesize(),
 624                                                     getpagesize());
 625                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 626                                         PMD_DRV_LOG(ERR,
 627                                         "Alloc VLAN AS table for VF %d fail\n",
 628                                         i);
 629                                 else
 630                                         rte_mem_lock_page(
 631                                                bp->pf.vf_info[i].vlan_as_table);
 632                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 633                         }
 634                 }
 635         }
 636
 637         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 638         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 639         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 640         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 641         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 642         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 643         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 644         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 645         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 646         if (!BNXT_CHIP_THOR(bp))
 647                 bp->max_l2_ctx += bp->max_rx_em_flows;
 648         /* TODO: For now, do not support VMDq/RFS on VFs. */
 649         if (BNXT_PF(bp)) {
 650                 if (bp->pf.max_vfs)
 651                         bp->max_vnics = 1;
 652                 else
 653                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 654         } else {
 655                 bp->max_vnics = 1;
 656         }
 657         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 658         if (BNXT_PF(bp)) {
 659                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 660                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 661                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 662                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 663                         HWRM_UNLOCK();
 664                         bnxt_hwrm_ptp_qcfg(bp);
 665                 }
 666         }
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 669                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 672                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 673                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 674         } else {
 675                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 676         }
 677
 678         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 679                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 680         else
 681                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 682
 683         HWRM_UNLOCK();
 684
 685         return rc;
 686 }
 687
 688 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 689 {
 690         int rc;
 691
 692         rc = __bnxt_hwrm_func_qcaps(bp);
 693         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 694                 rc = bnxt_alloc_ctx_mem(bp);
 695                 if (rc)
 696                         return rc;
 697
 698                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 699                 if (!rc)
 700                         bp->flags |= BNXT_FLAG_NEW_RM;
 701         }
 702
 703         return rc;
 704 }
 705
 706 int bnxt_hwrm_func_reset(struct bnxt *bp)
 707 {
 708         int rc = 0;
 709         struct hwrm_func_reset_input req = {.req_type = 0 };
 710         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 711
 712         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 713
 714         req.enables = rte_cpu_to_le_32(0);
 715
 716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 717
 718         HWRM_CHECK_RESULT();
 719         HWRM_UNLOCK();
 720
 721         return rc;
 722 }
 723
 724 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 725 {
 726         int rc;
 727         uint32_t flags = 0;
 728         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 729         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 730
 731         if (bp->flags & BNXT_FLAG_REGISTERED)
 732                 return 0;
 733
 734         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 735         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 736                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 737
 738         /* PFs and trusted VFs should indicate the support of the
 739          * Master capability on non Stingray platform
 740          */
 741         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 742                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 743
 744         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 745         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 746                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 747         req.ver_maj = RTE_VER_YEAR;
 748         req.ver_min = RTE_VER_MONTH;
 749         req.ver_upd = RTE_VER_MINOR;
 750
 751         if (BNXT_PF(bp)) {
 752                 req.enables |= rte_cpu_to_le_32(
 753                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 754                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 755                        RTE_MIN(sizeof(req.vf_req_fwd),
 756                                sizeof(bp->pf.vf_req_fwd)));
 757
 758                 /*
 759                  * PF can sniff HWRM API issued by VF. This can be set up by
 760                  * linux driver and inherited by the DPDK PF driver. Clear
 761                  * this HWRM sniffer list in FW because DPDK PF driver does
 762                  * not support this.
 763                  */
 764                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 765         }
 766
 767         req.flags = rte_cpu_to_le_32(flags);
 768
 769         req.async_event_fwd[0] |=
 770                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 771                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 772                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 773                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 774                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 775         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 776                 req.async_event_fwd[0] |=
 777                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 778         req.async_event_fwd[1] |=
 779                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 780                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 781
 782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 783
 784         HWRM_CHECK_RESULT();
 785
 786         flags = rte_le_to_cpu_32(resp->flags);
 787         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 788                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 789
 790         HWRM_UNLOCK();
 791
 792         bp->flags |= BNXT_FLAG_REGISTERED;
 793
 794         return rc;
 795 }
 796
 797 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 798 {
 799         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 800                 return 0;
 801
 802         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 803 }
 804
 805 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 806 {
 807         int rc;
 808         uint32_t flags = 0;
 809         uint32_t enables;
 810         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 811         struct hwrm_func_vf_cfg_input req = {0};
 812
 813         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 814
 815         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 816                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 817                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 818                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 819                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 820
 821         if (BNXT_HAS_RING_GRPS(bp)) {
 822                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 823                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 824         }
 825
 826         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 827         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 828                                             AGG_RING_MULTIPLIER);
 829         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 830                                              bp->tx_nr_rings +
 831                                              BNXT_NUM_ASYNC_CPR(bp));
 832         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 833                                               bp->tx_nr_rings +
 834                                               BNXT_NUM_ASYNC_CPR(bp));
 835         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 836         if (bp->vf_resv_strategy ==
 837             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 838                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 839                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 840                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 841                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 842                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 843                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 844         }
 845
 846         if (test)
 847                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 848                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 849                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 850                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 851                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 852                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 853
 854         if (test && BNXT_HAS_RING_GRPS(bp))
 855                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 856
 857         req.flags = rte_cpu_to_le_32(flags);
 858         req.enables |= rte_cpu_to_le_32(enables);
 859
 860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 861
 862         if (test)
 863                 HWRM_CHECK_RESULT_SILENT();
 864         else
 865                 HWRM_CHECK_RESULT();
 866
 867         HWRM_UNLOCK();
 868         return rc;
 869 }
 870
 871 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 872 {
 873         int rc;
 874         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 875         struct hwrm_func_resource_qcaps_input req = {0};
 876
 877         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 878         req.fid = rte_cpu_to_le_16(0xffff);
 879
 880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 881
 882         HWRM_CHECK_RESULT();
 883
 884         if (BNXT_VF(bp)) {
 885                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 886                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 887                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 888                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 889                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 890                 /* func_resource_qcaps does not return max_rx_em_flows.
 891                  * So use the value provided by func_qcaps.
 892                  */
 893                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 894                 if (!BNXT_CHIP_THOR(bp))
 895                         bp->max_l2_ctx += bp->max_rx_em_flows;
 896                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 897                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 898         }
 899         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 900         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 901         if (bp->vf_resv_strategy >
 902             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 903                 bp->vf_resv_strategy =
 904                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 905
 906         HWRM_UNLOCK();
 907         return rc;
 908 }
 909
 910 int bnxt_hwrm_ver_get(struct bnxt *bp)
 911 {
 912         int rc = 0;
 913         struct hwrm_ver_get_input req = {.req_type = 0 };
 914         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 915         uint32_t fw_version;
 916         uint16_t max_resp_len;
 917         char type[RTE_MEMZONE_NAMESIZE];
 918         uint32_t dev_caps_cfg;
 919
 920         bp->max_req_len = HWRM_MAX_REQ_LEN;
 921         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 922
 923         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 924         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 925         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 926
 927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 928
 929         if (bp->flags & BNXT_FLAG_FW_RESET)
 930                 HWRM_CHECK_RESULT_SILENT();
 931         else
 932                 HWRM_CHECK_RESULT();
 933
 934         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 935                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 936                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 937                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 938         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 939                      (resp->hwrm_fw_min_8b << 16) |
 940                      (resp->hwrm_fw_bld_8b << 8) |
 941                      resp->hwrm_fw_rsvd_8b;
 942         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 943                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 944
 945         fw_version = resp->hwrm_intf_maj_8b << 16;
 946         fw_version |= resp->hwrm_intf_min_8b << 8;
 947         fw_version |= resp->hwrm_intf_upd_8b;
 948         bp->hwrm_spec_code = fw_version;
 949
 950         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 951                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 952                 rc = -EINVAL;
 953                 goto error;
 954         }
 955
 956         if (bp->max_req_len > resp->max_req_win_len) {
 957                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 958                 rc = -EINVAL;
 959         }
 960         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 961         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 962         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 963                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 964
 965         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 966         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 967
 968         if (bp->max_resp_len != max_resp_len) {
 969                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 970                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 971                         bp->pdev->addr.devid, bp->pdev->addr.function);
 972
 973                 rte_free(bp->hwrm_cmd_resp_addr);
 974
 975                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 976                 if (bp->hwrm_cmd_resp_addr == NULL) {
 977                         rc = -ENOMEM;
 978                         goto error;
 979                 }
 980                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 981                 bp->hwrm_cmd_resp_dma_addr =
 982                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 983                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 984                         PMD_DRV_LOG(ERR,
 985                         "Unable to map response buffer to physical memory.\n");
 986                         rc = -ENOMEM;
 987                         goto error;
 988                 }
 989                 bp->max_resp_len = max_resp_len;
 990         }
 991
 992         if ((dev_caps_cfg &
 993                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 994             (dev_caps_cfg &
 995              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 996                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 997                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 998         }
 999
1000         if (((dev_caps_cfg &
1001               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1002              (dev_caps_cfg &
1003               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1004             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1005                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1006                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1007                         bp->pdev->addr.devid, bp->pdev->addr.function);
1008
1009                 rte_free(bp->hwrm_short_cmd_req_addr);
1010
1011                 bp->hwrm_short_cmd_req_addr =
1012                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1013                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1014                         rc = -ENOMEM;
1015                         goto error;
1016                 }
1017                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1018                 bp->hwrm_short_cmd_req_dma_addr =
1019                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1020                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1021                         rte_free(bp->hwrm_short_cmd_req_addr);
1022                         PMD_DRV_LOG(ERR,
1023                                 "Unable to map buffer to physical memory.\n");
1024                         rc = -ENOMEM;
1025                         goto error;
1026                 }
1027         }
1028         if (dev_caps_cfg &
1029             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1030                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1031                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1032         }
1033         if (dev_caps_cfg &
1034             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1035                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1036         if (dev_caps_cfg &
1037             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1038                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1039                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1040         }
1041
1042 error:
1043         HWRM_UNLOCK();
1044         return rc;
1045 }
1046
1047 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1048 {
1049         int rc;
1050         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1051         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1052
1053         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1054                 return 0;
1055
1056         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1057         req.flags = flags;
1058
1059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1060
1061         HWRM_CHECK_RESULT();
1062         HWRM_UNLOCK();
1063
1064         return rc;
1065 }
1066
1067 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1068 {
1069         int rc = 0;
1070         struct hwrm_port_phy_cfg_input req = {0};
1071         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1072         uint32_t enables = 0;
1073
1074         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1075
1076         if (conf->link_up) {
1077                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1078                 if (bp->link_info.auto_mode && conf->link_speed) {
1079                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1080                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1081                 }
1082
1083                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1084                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1085                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1086                 /*
1087                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1088                  * any auto mode, even "none".
1089                  */
1090                 if (!conf->link_speed) {
1091                         /* No speeds specified. Enable AutoNeg - all speeds */
1092                         req.auto_mode =
1093                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1094                 }
1095                 /* AutoNeg - Advertise speeds specified. */
1096                 if (conf->auto_link_speed_mask &&
1097                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1098                         req.auto_mode =
1099                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1100                         req.auto_link_speed_mask =
1101                                 conf->auto_link_speed_mask;
1102                         enables |=
1103                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1104                 }
1105
1106                 req.auto_duplex = conf->duplex;
1107                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1108                 req.auto_pause = conf->auto_pause;
1109                 req.force_pause = conf->force_pause;
1110                 /* Set force_pause if there is no auto or if there is a force */
1111                 if (req.auto_pause && !req.force_pause)
1112                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1113                 else
1114                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1115
1116                 req.enables = rte_cpu_to_le_32(enables);
1117         } else {
1118                 req.flags =
1119                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1120                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1121         }
1122
1123         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1124
1125         HWRM_CHECK_RESULT();
1126         HWRM_UNLOCK();
1127
1128         return rc;
1129 }
1130
1131 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1132                                    struct bnxt_link_info *link_info)
1133 {
1134         int rc = 0;
1135         struct hwrm_port_phy_qcfg_input req = {0};
1136         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1137
1138         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1139
1140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1141
1142         HWRM_CHECK_RESULT();
1143
1144         link_info->phy_link_status = resp->link;
1145         link_info->link_up =
1146                 (link_info->phy_link_status ==
1147                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1148         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1149         link_info->duplex = resp->duplex_cfg;
1150         link_info->pause = resp->pause;
1151         link_info->auto_pause = resp->auto_pause;
1152         link_info->force_pause = resp->force_pause;
1153         link_info->auto_mode = resp->auto_mode;
1154         link_info->phy_type = resp->phy_type;
1155         link_info->media_type = resp->media_type;
1156
1157         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1158         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1159         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1160         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1161         link_info->phy_ver[0] = resp->phy_maj;
1162         link_info->phy_ver[1] = resp->phy_min;
1163         link_info->phy_ver[2] = resp->phy_bld;
1164
1165         HWRM_UNLOCK();
1166
1167         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1168         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1169         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1170         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1171         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1172                     link_info->auto_link_speed_mask);
1173         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1174                     link_info->force_link_speed);
1175
1176         return rc;
1177 }
1178
1179 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1180 {
1181         int rc = 0;
1182         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1183         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184         int i;
1185
1186         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1187
1188         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1189         /* HWRM Version >= 1.9.1 */
1190         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1191                 req.drv_qmap_cap =
1192                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1193         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1194
1195         HWRM_CHECK_RESULT();
1196
1197 #define GET_QUEUE_INFO(x) \
1198         bp->cos_queue[x].id = resp->queue_id##x; \
1199         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1200
1201         GET_QUEUE_INFO(0);
1202         GET_QUEUE_INFO(1);
1203         GET_QUEUE_INFO(2);
1204         GET_QUEUE_INFO(3);
1205         GET_QUEUE_INFO(4);
1206         GET_QUEUE_INFO(5);
1207         GET_QUEUE_INFO(6);
1208         GET_QUEUE_INFO(7);
1209
1210         HWRM_UNLOCK();
1211
1212         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1213                 bp->tx_cosq_id = bp->cos_queue[0].id;
1214         } else {
1215                 /* iterate and find the COSq profile to use for Tx */
1216                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1217                         if (bp->cos_queue[i].profile ==
1218                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1219                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1220                                 break;
1221                         }
1222                 }
1223         }
1224
1225         bp->max_tc = resp->max_configurable_queues;
1226         bp->max_lltc = resp->max_configurable_lossless_queues;
1227         if (bp->max_tc > BNXT_MAX_QUEUE)
1228                 bp->max_tc = BNXT_MAX_QUEUE;
1229         bp->max_q = bp->max_tc;
1230
1231         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1232
1233         return rc;
1234 }
1235
1236 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1237                          struct bnxt_ring *ring,
1238                          uint32_t ring_type, uint32_t map_index,
1239                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1240 {
1241         int rc = 0;
1242         uint32_t enables = 0;
1243         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1244         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1245         struct rte_mempool *mb_pool;
1246         uint16_t rx_buf_size;
1247
1248         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1249
1250         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1251         req.fbo = rte_cpu_to_le_32(0);
1252         /* Association of ring index with doorbell index */
1253         req.logical_id = rte_cpu_to_le_16(map_index);
1254         req.length = rte_cpu_to_le_32(ring->ring_size);
1255
1256         switch (ring_type) {
1257         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1258                 req.ring_type = ring_type;
1259                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1260                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1261                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1262                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1263                         enables |=
1264                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1265                 break;
1266         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1267                 req.ring_type = ring_type;
1268                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1269                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1270                 if (BNXT_CHIP_THOR(bp)) {
1271                         mb_pool = bp->rx_queues[0]->mb_pool;
1272                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1273                                       RTE_PKTMBUF_HEADROOM;
1274                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1275                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1276                         enables |=
1277                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1278                 }
1279                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1280                         enables |=
1281                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1282                 break;
1283         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1284                 req.ring_type = ring_type;
1285                 if (BNXT_HAS_NQ(bp)) {
1286                         /* Association of cp ring with nq */
1287                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1288                         enables |=
1289                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1290                 }
1291                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1292                 break;
1293         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1294                 req.ring_type = ring_type;
1295                 req.page_size = BNXT_PAGE_SHFT;
1296                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1297                 break;
1298         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1299                 req.ring_type = ring_type;
1300                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1301
1302                 mb_pool = bp->rx_queues[0]->mb_pool;
1303                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1304                               RTE_PKTMBUF_HEADROOM;
1305                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1306                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1307
1308                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1309                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1310                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1311                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1312                 break;
1313         default:
1314                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1315                         ring_type);
1316                 HWRM_UNLOCK();
1317                 return -EINVAL;
1318         }
1319         req.enables = rte_cpu_to_le_32(enables);
1320
1321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322
1323         if (rc || resp->error_code) {
1324                 if (rc == 0 && resp->error_code)
1325                         rc = rte_le_to_cpu_16(resp->error_code);
1326                 switch (ring_type) {
1327                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1328                         PMD_DRV_LOG(ERR,
1329                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1330                         HWRM_UNLOCK();
1331                         return rc;
1332                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1333                         PMD_DRV_LOG(ERR,
1334                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1335                         HWRM_UNLOCK();
1336                         return rc;
1337                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1338                         PMD_DRV_LOG(ERR,
1339                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1340                                     rc);
1341                         HWRM_UNLOCK();
1342                         return rc;
1343                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1344                         PMD_DRV_LOG(ERR,
1345                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1346                         HWRM_UNLOCK();
1347                         return rc;
1348                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1349                         PMD_DRV_LOG(ERR,
1350                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1351                         HWRM_UNLOCK();
1352                         return rc;
1353                 default:
1354                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1355                         HWRM_UNLOCK();
1356                         return rc;
1357                 }
1358         }
1359
1360         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1361         HWRM_UNLOCK();
1362         return rc;
1363 }
1364
1365 int bnxt_hwrm_ring_free(struct bnxt *bp,
1366                         struct bnxt_ring *ring, uint32_t ring_type)
1367 {
1368         int rc;
1369         struct hwrm_ring_free_input req = {.req_type = 0 };
1370         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1371
1372         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1373
1374         req.ring_type = ring_type;
1375         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1376
1377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1378
1379         if (rc || resp->error_code) {
1380                 if (rc == 0 && resp->error_code)
1381                         rc = rte_le_to_cpu_16(resp->error_code);
1382                 HWRM_UNLOCK();
1383
1384                 switch (ring_type) {
1385                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1386                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1387                                 rc);
1388                         return rc;
1389                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1390                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1391                                 rc);
1392                         return rc;
1393                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1394                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1395                                 rc);
1396                         return rc;
1397                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1398                         PMD_DRV_LOG(ERR,
1399                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1400                         return rc;
1401                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1404                         return rc;
1405                 default:
1406                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1407                         return rc;
1408                 }
1409         }
1410         HWRM_UNLOCK();
1411         return 0;
1412 }
1413
1414 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1415 {
1416         int rc = 0;
1417         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1418         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1419
1420         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1421
1422         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1423         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1424         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1425         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1426
1427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1428
1429         HWRM_CHECK_RESULT();
1430
1431         bp->grp_info[idx].fw_grp_id =
1432             rte_le_to_cpu_16(resp->ring_group_id);
1433
1434         HWRM_UNLOCK();
1435
1436         return rc;
1437 }
1438
1439 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1440 {
1441         int rc;
1442         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1443         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1444
1445         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1446
1447         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1448
1449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1450
1451         HWRM_CHECK_RESULT();
1452         HWRM_UNLOCK();
1453
1454         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1455         return rc;
1456 }
1457
1458 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1459 {
1460         int rc = 0;
1461         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1462         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1463
1464         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1465                 return rc;
1466
1467         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1468
1469         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1470
1471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1472
1473         HWRM_CHECK_RESULT();
1474         HWRM_UNLOCK();
1475
1476         return rc;
1477 }
1478
1479 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1480                                 unsigned int idx __rte_unused)
1481 {
1482         int rc;
1483         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1484         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1485
1486         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1487
1488         req.update_period_ms = rte_cpu_to_le_32(0);
1489
1490         req.stats_dma_addr =
1491             rte_cpu_to_le_64(cpr->hw_stats_map);
1492
1493         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1494
1495         HWRM_CHECK_RESULT();
1496
1497         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1498
1499         HWRM_UNLOCK();
1500
1501         return rc;
1502 }
1503
1504 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1505                                 unsigned int idx __rte_unused)
1506 {
1507         int rc;
1508         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1509         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1510
1511         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1512
1513         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1514
1515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1516
1517         HWRM_CHECK_RESULT();
1518         HWRM_UNLOCK();
1519
1520         return rc;
1521 }
1522
1523 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 {
1525         int rc = 0, i, j;
1526         struct hwrm_vnic_alloc_input req = { 0 };
1527         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1528
1529         if (!BNXT_HAS_RING_GRPS(bp))
1530                 goto skip_ring_grps;
1531
1532         /* map ring groups to this vnic */
1533         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1534                 vnic->start_grp_id, vnic->end_grp_id);
1535         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1536                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1537
1538         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1539         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1540         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1541         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1542
1543 skip_ring_grps:
1544         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1545                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1546         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1547
1548         if (vnic->func_default)
1549                 req.flags =
1550                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1552
1553         HWRM_CHECK_RESULT();
1554
1555         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1556         HWRM_UNLOCK();
1557         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1558         return rc;
1559 }
1560
1561 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1562                                         struct bnxt_vnic_info *vnic,
1563                                         struct bnxt_plcmodes_cfg *pmode)
1564 {
1565         int rc = 0;
1566         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1567         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1568
1569         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1570
1571         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1572
1573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1574
1575         HWRM_CHECK_RESULT();
1576
1577         pmode->flags = rte_le_to_cpu_32(resp->flags);
1578         /* dflt_vnic bit doesn't exist in the _cfg command */
1579         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1580         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1581         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1582         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1583
1584         HWRM_UNLOCK();
1585
1586         return rc;
1587 }
1588
1589 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1590                                        struct bnxt_vnic_info *vnic,
1591                                        struct bnxt_plcmodes_cfg *pmode)
1592 {
1593         int rc = 0;
1594         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1595         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1596
1597         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1598                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1599                 return rc;
1600         }
1601
1602         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1603
1604         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1605         req.flags = rte_cpu_to_le_32(pmode->flags);
1606         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1607         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1608         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1609         req.enables = rte_cpu_to_le_32(
1610             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1611             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1612             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1613         );
1614
1615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616
1617         HWRM_CHECK_RESULT();
1618         HWRM_UNLOCK();
1619
1620         return rc;
1621 }
1622
1623 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1624 {
1625         int rc = 0;
1626         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1627         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1628         struct bnxt_plcmodes_cfg pmodes = { 0 };
1629         uint32_t ctx_enable_flag = 0;
1630         uint32_t enables = 0;
1631
1632         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1633                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1634                 return rc;
1635         }
1636
1637         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1638         if (rc)
1639                 return rc;
1640
1641         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1642
1643         if (BNXT_CHIP_THOR(bp)) {
1644                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1645                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1646                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1647
1648                 req.default_rx_ring_id =
1649                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1650                 req.default_cmpl_ring_id =
1651                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1652                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1653                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1654                 goto config_mru;
1655         }
1656
1657         /* Only RSS support for now TBD: COS & LB */
1658         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1659         if (vnic->lb_rule != 0xffff)
1660                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1661         if (vnic->cos_rule != 0xffff)
1662                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1663         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1664                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1665                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1666         }
1667         enables |= ctx_enable_flag;
1668         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1669         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1670         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1671         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1672
1673 config_mru:
1674         req.enables = rte_cpu_to_le_32(enables);
1675         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1676         req.mru = rte_cpu_to_le_16(vnic->mru);
1677         /* Configure default VNIC only once. */
1678         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1679                 req.flags |=
1680                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1681                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1682         }
1683         if (vnic->vlan_strip)
1684                 req.flags |=
1685                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1686         if (vnic->bd_stall)
1687                 req.flags |=
1688                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1689         if (vnic->roce_dual)
1690                 req.flags |= rte_cpu_to_le_32(
1691                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1692         if (vnic->roce_only)
1693                 req.flags |= rte_cpu_to_le_32(
1694                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1695         if (vnic->rss_dflt_cr)
1696                 req.flags |= rte_cpu_to_le_32(
1697                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1698
1699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1700
1701         HWRM_CHECK_RESULT();
1702         HWRM_UNLOCK();
1703
1704         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1705
1706         return rc;
1707 }
1708
1709 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1710                 int16_t fw_vf_id)
1711 {
1712         int rc = 0;
1713         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1714         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1715
1716         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1717                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1718                 return rc;
1719         }
1720         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1721
1722         req.enables =
1723                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1724         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1725         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1726
1727         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1728
1729         HWRM_CHECK_RESULT();
1730
1731         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1732         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1733         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1734         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1735         vnic->mru = rte_le_to_cpu_16(resp->mru);
1736         vnic->func_default = rte_le_to_cpu_32(
1737                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1738         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1739                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1740         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1741                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1742         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1743                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1744         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1745                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1746         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1747                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1748
1749         HWRM_UNLOCK();
1750
1751         return rc;
1752 }
1753
1754 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1755                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1756 {
1757         int rc = 0;
1758         uint16_t ctx_id;
1759         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1760         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1761                                                 bp->hwrm_cmd_resp_addr;
1762
1763         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1764
1765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1766         HWRM_CHECK_RESULT();
1767
1768         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1769         if (!BNXT_HAS_RING_GRPS(bp))
1770                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1771         else if (ctx_idx == 0)
1772                 vnic->rss_rule = ctx_id;
1773
1774         HWRM_UNLOCK();
1775
1776         return rc;
1777 }
1778
1779 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1780                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1781 {
1782         int rc = 0;
1783         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1784         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1785                                                 bp->hwrm_cmd_resp_addr;
1786
1787         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1788                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1789                 return rc;
1790         }
1791         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1792
1793         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1794
1795         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1796
1797         HWRM_CHECK_RESULT();
1798         HWRM_UNLOCK();
1799
1800         return rc;
1801 }
1802
1803 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1804 {
1805         int rc = 0;
1806         struct hwrm_vnic_free_input req = {.req_type = 0 };
1807         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1808
1809         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1810                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1811                 return rc;
1812         }
1813
1814         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1815
1816         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1817
1818         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1819
1820         HWRM_CHECK_RESULT();
1821         HWRM_UNLOCK();
1822
1823         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1824         /* Configure default VNIC again if necessary. */
1825         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1826                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1827
1828         return rc;
1829 }
1830
1831 static int
1832 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1833 {
1834         int i;
1835         int rc = 0;
1836         int nr_ctxs = vnic->num_lb_ctxts;
1837         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1838         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1839
1840         for (i = 0; i < nr_ctxs; i++) {
1841                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1842
1843                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1844                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1845                 req.hash_mode_flags = vnic->hash_mode;
1846
1847                 req.hash_key_tbl_addr =
1848                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1849
1850                 req.ring_grp_tbl_addr =
1851                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1852                                          i * HW_HASH_INDEX_SIZE);
1853                 req.ring_table_pair_index = i;
1854                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1855
1856                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1857                                             BNXT_USE_CHIMP_MB);
1858
1859                 HWRM_CHECK_RESULT();
1860                 HWRM_UNLOCK();
1861         }
1862
1863         return rc;
1864 }
1865
1866 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1867                            struct bnxt_vnic_info *vnic)
1868 {
1869         int rc = 0;
1870         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1871         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1872
1873         if (!vnic->rss_table)
1874                 return 0;
1875
1876         if (BNXT_CHIP_THOR(bp))
1877                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1878
1879         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1880
1881         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1882         req.hash_mode_flags = vnic->hash_mode;
1883
1884         req.ring_grp_tbl_addr =
1885             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1886         req.hash_key_tbl_addr =
1887             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1888         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1889         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1890
1891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892
1893         HWRM_CHECK_RESULT();
1894         HWRM_UNLOCK();
1895
1896         return rc;
1897 }
1898
1899 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1900                         struct bnxt_vnic_info *vnic)
1901 {
1902         int rc = 0;
1903         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1904         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1905         uint16_t size;
1906
1907         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1908                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1909                 return rc;
1910         }
1911
1912         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1913
1914         req.flags = rte_cpu_to_le_32(
1915                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1916
1917         req.enables = rte_cpu_to_le_32(
1918                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1919
1920         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1921         size -= RTE_PKTMBUF_HEADROOM;
1922         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1923
1924         req.jumbo_thresh = rte_cpu_to_le_16(size);
1925         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1926
1927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1928
1929         HWRM_CHECK_RESULT();
1930         HWRM_UNLOCK();
1931
1932         return rc;
1933 }
1934
1935 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1936                         struct bnxt_vnic_info *vnic, bool enable)
1937 {
1938         int rc = 0;
1939         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1940         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1941
1942         if (BNXT_CHIP_THOR(bp))
1943                 return 0;
1944
1945         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1946
1947         if (enable) {
1948                 req.enables = rte_cpu_to_le_32(
1949                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1950                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1951                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1952                 req.flags = rte_cpu_to_le_32(
1953                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1954                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1955                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1956                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1957                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1958                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1959                 req.max_agg_segs = rte_cpu_to_le_16(5);
1960                 req.max_aggs =
1961                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1962                 req.min_agg_len = rte_cpu_to_le_32(512);
1963         }
1964         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1965
1966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1967
1968         HWRM_CHECK_RESULT();
1969         HWRM_UNLOCK();
1970
1971         return rc;
1972 }
1973
1974 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1975 {
1976         struct hwrm_func_cfg_input req = {0};
1977         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1978         int rc;
1979
1980         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1981         req.enables = rte_cpu_to_le_32(
1982                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1983         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1984         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1985
1986         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1987
1988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1989         HWRM_CHECK_RESULT();
1990         HWRM_UNLOCK();
1991
1992         bp->pf.vf_info[vf].random_mac = false;
1993
1994         return rc;
1995 }
1996
1997 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1998                                   uint64_t *dropped)
1999 {
2000         int rc = 0;
2001         struct hwrm_func_qstats_input req = {.req_type = 0};
2002         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2003
2004         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2005
2006         req.fid = rte_cpu_to_le_16(fid);
2007
2008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2009
2010         HWRM_CHECK_RESULT();
2011
2012         if (dropped)
2013                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2014
2015         HWRM_UNLOCK();
2016
2017         return rc;
2018 }
2019
2020 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2021                           struct rte_eth_stats *stats)
2022 {
2023         int rc = 0;
2024         struct hwrm_func_qstats_input req = {.req_type = 0};
2025         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2026
2027         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2028
2029         req.fid = rte_cpu_to_le_16(fid);
2030
2031         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2032
2033         HWRM_CHECK_RESULT();
2034
2035         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2036         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2037         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2038         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2039         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2040         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2041
2042         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2043         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2044         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2045         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2046         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2047         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2048
2049         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2050         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2051         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2052
2053         HWRM_UNLOCK();
2054
2055         return rc;
2056 }
2057
2058 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2059 {
2060         int rc = 0;
2061         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2062         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2063
2064         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2065
2066         req.fid = rte_cpu_to_le_16(fid);
2067
2068         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2069
2070         HWRM_CHECK_RESULT();
2071         HWRM_UNLOCK();
2072
2073         return rc;
2074 }
2075
2076 /*
2077  * HWRM utility functions
2078  */
2079
2080 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2081 {
2082         unsigned int i;
2083         int rc = 0;
2084
2085         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2086                 struct bnxt_tx_queue *txq;
2087                 struct bnxt_rx_queue *rxq;
2088                 struct bnxt_cp_ring_info *cpr;
2089
2090                 if (i >= bp->rx_cp_nr_rings) {
2091                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2092                         cpr = txq->cp_ring;
2093                 } else {
2094                         rxq = bp->rx_queues[i];
2095                         cpr = rxq->cp_ring;
2096                 }
2097
2098                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2099                 if (rc)
2100                         return rc;
2101         }
2102         return 0;
2103 }
2104
2105 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2106 {
2107         int rc;
2108         unsigned int i;
2109         struct bnxt_cp_ring_info *cpr;
2110
2111         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2112
2113                 if (i >= bp->rx_cp_nr_rings) {
2114                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2115                 } else {
2116                         cpr = bp->rx_queues[i]->cp_ring;
2117                         if (BNXT_HAS_RING_GRPS(bp))
2118                                 bp->grp_info[i].fw_stats_ctx = -1;
2119                 }
2120                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2121                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2122                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2123                         if (rc)
2124                                 return rc;
2125                 }
2126         }
2127         return 0;
2128 }
2129
2130 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2131 {
2132         unsigned int i;
2133         int rc = 0;
2134
2135         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2136                 struct bnxt_tx_queue *txq;
2137                 struct bnxt_rx_queue *rxq;
2138                 struct bnxt_cp_ring_info *cpr;
2139
2140                 if (i >= bp->rx_cp_nr_rings) {
2141                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2142                         cpr = txq->cp_ring;
2143                 } else {
2144                         rxq = bp->rx_queues[i];
2145                         cpr = rxq->cp_ring;
2146                 }
2147
2148                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2149
2150                 if (rc)
2151                         return rc;
2152         }
2153         return rc;
2154 }
2155
2156 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2157 {
2158         uint16_t idx;
2159         uint32_t rc = 0;
2160
2161         if (!BNXT_HAS_RING_GRPS(bp))
2162                 return 0;
2163
2164         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2165
2166                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2167                         continue;
2168
2169                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2170
2171                 if (rc)
2172                         return rc;
2173         }
2174         return rc;
2175 }
2176
2177 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2178 {
2179         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2180
2181         bnxt_hwrm_ring_free(bp, cp_ring,
2182                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2183         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2184         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2185                                      sizeof(*cpr->cp_desc_ring));
2186         cpr->cp_raw_cons = 0;
2187         cpr->valid = 0;
2188 }
2189
2190 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2191 {
2192         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2193
2194         bnxt_hwrm_ring_free(bp, cp_ring,
2195                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2196         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2197         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2198                         sizeof(*cpr->cp_desc_ring));
2199         cpr->cp_raw_cons = 0;
2200         cpr->valid = 0;
2201 }
2202
2203 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2204 {
2205         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2206         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2207         struct bnxt_ring *ring = rxr->rx_ring_struct;
2208         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2209
2210         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2211                 bnxt_hwrm_ring_free(bp, ring,
2212                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2213                 ring->fw_ring_id = INVALID_HW_RING_ID;
2214                 if (BNXT_HAS_RING_GRPS(bp))
2215                         bp->grp_info[queue_index].rx_fw_ring_id =
2216                                                         INVALID_HW_RING_ID;
2217                 memset(rxr->rx_desc_ring, 0,
2218                        rxr->rx_ring_struct->ring_size *
2219                        sizeof(*rxr->rx_desc_ring));
2220                 memset(rxr->rx_buf_ring, 0,
2221                        rxr->rx_ring_struct->ring_size *
2222                        sizeof(*rxr->rx_buf_ring));
2223                 rxr->rx_prod = 0;
2224         }
2225         ring = rxr->ag_ring_struct;
2226         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2227                 bnxt_hwrm_ring_free(bp, ring,
2228                                     BNXT_CHIP_THOR(bp) ?
2229                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2230                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2231                 ring->fw_ring_id = INVALID_HW_RING_ID;
2232                 memset(rxr->ag_buf_ring, 0,
2233                        rxr->ag_ring_struct->ring_size *
2234                        sizeof(*rxr->ag_buf_ring));
2235                 rxr->ag_prod = 0;
2236                 if (BNXT_HAS_RING_GRPS(bp))
2237                         bp->grp_info[queue_index].ag_fw_ring_id =
2238                                                         INVALID_HW_RING_ID;
2239         }
2240         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2241                 bnxt_free_cp_ring(bp, cpr);
2242                 if (rxq->nq_ring)
2243                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2244         }
2245
2246         if (BNXT_HAS_RING_GRPS(bp))
2247                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2248 }
2249
2250 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2251 {
2252         unsigned int i;
2253
2254         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2255                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2256                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2257                 struct bnxt_ring *ring = txr->tx_ring_struct;
2258                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2259
2260                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2261                         bnxt_hwrm_ring_free(bp, ring,
2262                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2263                         ring->fw_ring_id = INVALID_HW_RING_ID;
2264                         memset(txr->tx_desc_ring, 0,
2265                                         txr->tx_ring_struct->ring_size *
2266                                         sizeof(*txr->tx_desc_ring));
2267                         memset(txr->tx_buf_ring, 0,
2268                                         txr->tx_ring_struct->ring_size *
2269                                         sizeof(*txr->tx_buf_ring));
2270                         txr->tx_prod = 0;
2271                         txr->tx_cons = 0;
2272                 }
2273                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2274                         bnxt_free_cp_ring(bp, cpr);
2275                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2276                         if (txq->nq_ring)
2277                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2278                 }
2279         }
2280
2281         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2282                 bnxt_free_hwrm_rx_ring(bp, i);
2283
2284         return 0;
2285 }
2286
2287 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2288 {
2289         uint16_t i;
2290         uint32_t rc = 0;
2291
2292         if (!BNXT_HAS_RING_GRPS(bp))
2293                 return 0;
2294
2295         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2296                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2297                 if (rc)
2298                         return rc;
2299         }
2300         return rc;
2301 }
2302
2303 void bnxt_free_hwrm_resources(struct bnxt *bp)
2304 {
2305         /* Release memzone */
2306         rte_free(bp->hwrm_cmd_resp_addr);
2307         rte_free(bp->hwrm_short_cmd_req_addr);
2308         bp->hwrm_cmd_resp_addr = NULL;
2309         bp->hwrm_short_cmd_req_addr = NULL;
2310         bp->hwrm_cmd_resp_dma_addr = 0;
2311         bp->hwrm_short_cmd_req_dma_addr = 0;
2312 }
2313
2314 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2315 {
2316         struct rte_pci_device *pdev = bp->pdev;
2317         char type[RTE_MEMZONE_NAMESIZE];
2318
2319         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2320                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2321         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2322         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2323         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2324         if (bp->hwrm_cmd_resp_addr == NULL)
2325                 return -ENOMEM;
2326         bp->hwrm_cmd_resp_dma_addr =
2327                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2328         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2329                 PMD_DRV_LOG(ERR,
2330                         "unable to map response address to physical memory\n");
2331                 return -ENOMEM;
2332         }
2333         rte_spinlock_init(&bp->hwrm_lock);
2334
2335         return 0;
2336 }
2337
2338 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2339 {
2340         struct bnxt_filter_info *filter;
2341         int rc = 0;
2342
2343         STAILQ_FOREACH(filter, &vnic->filter, next) {
2344                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2345                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2346                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2347                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2348                 else
2349                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2350                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2351                 bnxt_free_filter(bp, filter);
2352                 //if (rc)
2353                         //break;
2354         }
2355         return rc;
2356 }
2357
2358 static int
2359 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2360 {
2361         struct bnxt_filter_info *filter;
2362         struct rte_flow *flow;
2363         int rc = 0;
2364
2365         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2366                 filter = flow->filter;
2367                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2368                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2369                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2370                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2371                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2372                 else
2373                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2374
2375                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2376                 rte_free(flow);
2377                 //if (rc)
2378                         //break;
2379         }
2380         return rc;
2381 }
2382
2383 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2384 {
2385         struct bnxt_filter_info *filter;
2386         int rc = 0;
2387
2388         STAILQ_FOREACH(filter, &vnic->filter, next) {
2389                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2390                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2391                                                      filter);
2392                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2393                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2394                                                          filter);
2395                 else
2396                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2397                                                      filter);
2398                 if (rc)
2399                         break;
2400         }
2401         return rc;
2402 }
2403
2404 void bnxt_free_tunnel_ports(struct bnxt *bp)
2405 {
2406         if (bp->vxlan_port_cnt)
2407                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2408                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2409         bp->vxlan_port = 0;
2410         if (bp->geneve_port_cnt)
2411                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2412                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2413         bp->geneve_port = 0;
2414 }
2415
2416 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2417 {
2418         int i, j;
2419
2420         if (bp->vnic_info == NULL)
2421                 return;
2422
2423         /*
2424          * Cleanup VNICs in reverse order, to make sure the L2 filter
2425          * from vnic0 is last to be cleaned up.
2426          */
2427         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2428                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2429
2430                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2431                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2432                         return;
2433                 }
2434
2435                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2436
2437                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2438
2439                 if (BNXT_CHIP_THOR(bp)) {
2440                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2441                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2442                                                         vnic->fw_grp_ids[j]);
2443                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2444                         }
2445                         vnic->num_lb_ctxts = 0;
2446                 } else {
2447                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2448                         vnic->rss_rule = INVALID_HW_RING_ID;
2449                 }
2450
2451                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2452
2453                 bnxt_hwrm_vnic_free(bp, vnic);
2454
2455                 rte_free(vnic->fw_grp_ids);
2456         }
2457         /* Ring resources */
2458         bnxt_free_all_hwrm_rings(bp);
2459         bnxt_free_all_hwrm_ring_grps(bp);
2460         bnxt_free_all_hwrm_stat_ctxs(bp);
2461         bnxt_free_tunnel_ports(bp);
2462 }
2463
2464 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2465 {
2466         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2467
2468         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2469                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2470
2471         switch (conf_link_speed) {
2472         case ETH_LINK_SPEED_10M_HD:
2473         case ETH_LINK_SPEED_100M_HD:
2474                 /* FALLTHROUGH */
2475                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2476         }
2477         return hw_link_duplex;
2478 }
2479
2480 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2481 {
2482         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2483 }
2484
2485 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2486 {
2487         uint16_t eth_link_speed = 0;
2488
2489         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2490                 return ETH_LINK_SPEED_AUTONEG;
2491
2492         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2493         case ETH_LINK_SPEED_100M:
2494         case ETH_LINK_SPEED_100M_HD:
2495                 /* FALLTHROUGH */
2496                 eth_link_speed =
2497                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2498                 break;
2499         case ETH_LINK_SPEED_1G:
2500                 eth_link_speed =
2501                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2502                 break;
2503         case ETH_LINK_SPEED_2_5G:
2504                 eth_link_speed =
2505                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2506                 break;
2507         case ETH_LINK_SPEED_10G:
2508                 eth_link_speed =
2509                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2510                 break;
2511         case ETH_LINK_SPEED_20G:
2512                 eth_link_speed =
2513                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2514                 break;
2515         case ETH_LINK_SPEED_25G:
2516                 eth_link_speed =
2517                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2518                 break;
2519         case ETH_LINK_SPEED_40G:
2520                 eth_link_speed =
2521                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2522                 break;
2523         case ETH_LINK_SPEED_50G:
2524                 eth_link_speed =
2525                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2526                 break;
2527         case ETH_LINK_SPEED_100G:
2528                 eth_link_speed =
2529                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2530                 break;
2531         default:
2532                 PMD_DRV_LOG(ERR,
2533                         "Unsupported link speed %d; default to AUTO\n",
2534                         conf_link_speed);
2535                 break;
2536         }
2537         return eth_link_speed;
2538 }
2539
2540 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2541                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2542                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2543                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2544
2545 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2546 {
2547         uint32_t one_speed;
2548
2549         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2550                 return 0;
2551
2552         if (link_speed & ETH_LINK_SPEED_FIXED) {
2553                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2554
2555                 if (one_speed & (one_speed - 1)) {
2556                         PMD_DRV_LOG(ERR,
2557                                 "Invalid advertised speeds (%u) for port %u\n",
2558                                 link_speed, port_id);
2559                         return -EINVAL;
2560                 }
2561                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2562                         PMD_DRV_LOG(ERR,
2563                                 "Unsupported advertised speed (%u) for port %u\n",
2564                                 link_speed, port_id);
2565                         return -EINVAL;
2566                 }
2567         } else {
2568                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2569                         PMD_DRV_LOG(ERR,
2570                                 "Unsupported advertised speeds (%u) for port %u\n",
2571                                 link_speed, port_id);
2572                         return -EINVAL;
2573                 }
2574         }
2575         return 0;
2576 }
2577
2578 static uint16_t
2579 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2580 {
2581         uint16_t ret = 0;
2582
2583         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2584                 if (bp->link_info.support_speeds)
2585                         return bp->link_info.support_speeds;
2586                 link_speed = BNXT_SUPPORTED_SPEEDS;
2587         }
2588
2589         if (link_speed & ETH_LINK_SPEED_100M)
2590                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2591         if (link_speed & ETH_LINK_SPEED_100M_HD)
2592                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2593         if (link_speed & ETH_LINK_SPEED_1G)
2594                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2595         if (link_speed & ETH_LINK_SPEED_2_5G)
2596                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2597         if (link_speed & ETH_LINK_SPEED_10G)
2598                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2599         if (link_speed & ETH_LINK_SPEED_20G)
2600                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2601         if (link_speed & ETH_LINK_SPEED_25G)
2602                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2603         if (link_speed & ETH_LINK_SPEED_40G)
2604                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2605         if (link_speed & ETH_LINK_SPEED_50G)
2606                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2607         if (link_speed & ETH_LINK_SPEED_100G)
2608                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2609         return ret;
2610 }
2611
2612 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2613 {
2614         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2615
2616         switch (hw_link_speed) {
2617         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2618                 eth_link_speed = ETH_SPEED_NUM_100M;
2619                 break;
2620         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2621                 eth_link_speed = ETH_SPEED_NUM_1G;
2622                 break;
2623         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2624                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2625                 break;
2626         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2627                 eth_link_speed = ETH_SPEED_NUM_10G;
2628                 break;
2629         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2630                 eth_link_speed = ETH_SPEED_NUM_20G;
2631                 break;
2632         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2633                 eth_link_speed = ETH_SPEED_NUM_25G;
2634                 break;
2635         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2636                 eth_link_speed = ETH_SPEED_NUM_40G;
2637                 break;
2638         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2639                 eth_link_speed = ETH_SPEED_NUM_50G;
2640                 break;
2641         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2642                 eth_link_speed = ETH_SPEED_NUM_100G;
2643                 break;
2644         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2645         default:
2646                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2647                         hw_link_speed);
2648                 break;
2649         }
2650         return eth_link_speed;
2651 }
2652
2653 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2654 {
2655         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2656
2657         switch (hw_link_duplex) {
2658         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2659         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2660                 /* FALLTHROUGH */
2661                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2662                 break;
2663         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2664                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2665                 break;
2666         default:
2667                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2668                         hw_link_duplex);
2669                 break;
2670         }
2671         return eth_link_duplex;
2672 }
2673
2674 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2675 {
2676         int rc = 0;
2677         struct bnxt_link_info *link_info = &bp->link_info;
2678
2679         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2680         if (rc) {
2681                 PMD_DRV_LOG(ERR,
2682                         "Get link config failed with rc %d\n", rc);
2683                 goto exit;
2684         }
2685         if (link_info->link_speed)
2686                 link->link_speed =
2687                         bnxt_parse_hw_link_speed(link_info->link_speed);
2688         else
2689                 link->link_speed = ETH_SPEED_NUM_NONE;
2690         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2691         link->link_status = link_info->link_up;
2692         link->link_autoneg = link_info->auto_mode ==
2693                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2694                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2695 exit:
2696         return rc;
2697 }
2698
2699 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2700 {
2701         int rc = 0;
2702         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2703         struct bnxt_link_info link_req;
2704         uint16_t speed, autoneg;
2705
2706         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2707                 return 0;
2708
2709         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2710                         bp->eth_dev->data->port_id);
2711         if (rc)
2712                 goto error;
2713
2714         memset(&link_req, 0, sizeof(link_req));
2715         link_req.link_up = link_up;
2716         if (!link_up)
2717                 goto port_phy_cfg;
2718
2719         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2720         if (BNXT_CHIP_THOR(bp) &&
2721             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2722                 /* 40G is not supported as part of media auto detect.
2723                  * The speed should be forced and autoneg disabled
2724                  * to configure 40G speed.
2725                  */
2726                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2727                 autoneg = 0;
2728         }
2729
2730         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2731         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2732         /* Autoneg can be done only when the FW allows.
2733          * When user configures fixed speed of 40G and later changes to
2734          * any other speed, auto_link_speed/force_link_speed is still set
2735          * to 40G until link comes up at new speed.
2736          */
2737         if (autoneg == 1 &&
2738             !(!BNXT_CHIP_THOR(bp) &&
2739               (bp->link_info.auto_link_speed ||
2740                bp->link_info.force_link_speed))) {
2741                 link_req.phy_flags |=
2742                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2743                 link_req.auto_link_speed_mask =
2744                         bnxt_parse_eth_link_speed_mask(bp,
2745                                                        dev_conf->link_speeds);
2746         } else {
2747                 if (bp->link_info.phy_type ==
2748                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2749                     bp->link_info.phy_type ==
2750                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2751                     bp->link_info.media_type ==
2752                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2753                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2754                         return -EINVAL;
2755                 }
2756
2757                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2758                 /* If user wants a particular speed try that first. */
2759                 if (speed)
2760                         link_req.link_speed = speed;
2761                 else if (bp->link_info.force_link_speed)
2762                         link_req.link_speed = bp->link_info.force_link_speed;
2763                 else
2764                         link_req.link_speed = bp->link_info.auto_link_speed;
2765         }
2766         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2767         link_req.auto_pause = bp->link_info.auto_pause;
2768         link_req.force_pause = bp->link_info.force_pause;
2769
2770 port_phy_cfg:
2771         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2772         if (rc) {
2773                 PMD_DRV_LOG(ERR,
2774                         "Set link config failed with rc %d\n", rc);
2775         }
2776
2777 error:
2778         return rc;
2779 }
2780
2781 /* JIRA 22088 */
2782 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2783 {
2784         struct hwrm_func_qcfg_input req = {0};
2785         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2786         uint16_t flags;
2787         int rc = 0;
2788
2789         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2790         req.fid = rte_cpu_to_le_16(0xffff);
2791
2792         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2793
2794         HWRM_CHECK_RESULT();
2795
2796         /* Hard Coded.. 0xfff VLAN ID mask */
2797         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2798         flags = rte_le_to_cpu_16(resp->flags);
2799         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2800                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2801
2802         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2803                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2804                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2805         } else if (BNXT_VF(bp) &&
2806                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2807                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2808                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2809         }
2810
2811         if (mtu)
2812                 *mtu = resp->mtu;
2813
2814         switch (resp->port_partition_type) {
2815         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2816         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2817         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2818                 /* FALLTHROUGH */
2819                 bp->port_partition_type = resp->port_partition_type;
2820                 break;
2821         default:
2822                 bp->port_partition_type = 0;
2823                 break;
2824         }
2825
2826         HWRM_UNLOCK();
2827
2828         return rc;
2829 }
2830
2831 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2832                                    struct hwrm_func_qcaps_output *qcaps)
2833 {
2834         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2835         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2836                sizeof(qcaps->mac_address));
2837         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2838         qcaps->max_rx_rings = fcfg->num_rx_rings;
2839         qcaps->max_tx_rings = fcfg->num_tx_rings;
2840         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2841         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2842         qcaps->max_vfs = 0;
2843         qcaps->first_vf_id = 0;
2844         qcaps->max_vnics = fcfg->num_vnics;
2845         qcaps->max_decap_records = 0;
2846         qcaps->max_encap_records = 0;
2847         qcaps->max_tx_wm_flows = 0;
2848         qcaps->max_tx_em_flows = 0;
2849         qcaps->max_rx_wm_flows = 0;
2850         qcaps->max_rx_em_flows = 0;
2851         qcaps->max_flow_id = 0;
2852         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2853         qcaps->max_sp_tx_rings = 0;
2854         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2855 }
2856
2857 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2858 {
2859         struct hwrm_func_cfg_input req = {0};
2860         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2861         uint32_t enables;
2862         int rc;
2863
2864         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2865                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2866                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2867                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2868                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2869                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2870                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2871                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2872                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2873
2874         if (BNXT_HAS_RING_GRPS(bp)) {
2875                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2876                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2877         } else if (BNXT_HAS_NQ(bp)) {
2878                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2879                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2880         }
2881
2882         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2883         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2884         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2885                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2886                                    BNXT_NUM_VLANS);
2887         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2888         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2889         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2890         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2891         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2892         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2893         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2894         req.fid = rte_cpu_to_le_16(0xffff);
2895         req.enables = rte_cpu_to_le_32(enables);
2896
2897         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2898
2899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2900
2901         HWRM_CHECK_RESULT();
2902         HWRM_UNLOCK();
2903
2904         return rc;
2905 }
2906
2907 static void populate_vf_func_cfg_req(struct bnxt *bp,
2908                                      struct hwrm_func_cfg_input *req,
2909                                      int num_vfs)
2910 {
2911         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2912                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2913                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2914                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2915                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2916                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2917                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2918                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2919                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2920                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2921
2922         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2923                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2924                                     BNXT_NUM_VLANS);
2925         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2926                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2927                                     BNXT_NUM_VLANS);
2928         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2929                                                 (num_vfs + 1));
2930         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2931         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2932                                                (num_vfs + 1));
2933         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2934         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2935         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2936         /* TODO: For now, do not support VMDq/RFS on VFs. */
2937         req->num_vnics = rte_cpu_to_le_16(1);
2938         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2939                                                  (num_vfs + 1));
2940 }
2941
2942 static void add_random_mac_if_needed(struct bnxt *bp,
2943                                      struct hwrm_func_cfg_input *cfg_req,
2944                                      int vf)
2945 {
2946         struct rte_ether_addr mac;
2947
2948         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2949                 return;
2950
2951         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2952                 cfg_req->enables |=
2953                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2954                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2955                 bp->pf.vf_info[vf].random_mac = true;
2956         } else {
2957                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2958                         RTE_ETHER_ADDR_LEN);
2959         }
2960 }
2961
2962 static void reserve_resources_from_vf(struct bnxt *bp,
2963                                       struct hwrm_func_cfg_input *cfg_req,
2964                                       int vf)
2965 {
2966         struct hwrm_func_qcaps_input req = {0};
2967         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2968         int rc;
2969
2970         /* Get the actual allocated values now */
2971         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2972         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2973         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2974
2975         if (rc) {
2976                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2977                 copy_func_cfg_to_qcaps(cfg_req, resp);
2978         } else if (resp->error_code) {
2979                 rc = rte_le_to_cpu_16(resp->error_code);
2980                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2981                 copy_func_cfg_to_qcaps(cfg_req, resp);
2982         }
2983
2984         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2985         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2986         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2987         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2988         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2989         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2990         /*
2991          * TODO: While not supporting VMDq with VFs, max_vnics is always
2992          * forced to 1 in this case
2993          */
2994         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2995         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2996
2997         HWRM_UNLOCK();
2998 }
2999
3000 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3001 {
3002         struct hwrm_func_qcfg_input req = {0};
3003         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3004         int rc;
3005
3006         /* Check for zero MAC address */
3007         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3008         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3010         HWRM_CHECK_RESULT();
3011         rc = rte_le_to_cpu_16(resp->vlan);
3012
3013         HWRM_UNLOCK();
3014
3015         return rc;
3016 }
3017
3018 static int update_pf_resource_max(struct bnxt *bp)
3019 {
3020         struct hwrm_func_qcfg_input req = {0};
3021         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3022         int rc;
3023
3024         /* And copy the allocated numbers into the pf struct */
3025         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3026         req.fid = rte_cpu_to_le_16(0xffff);
3027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3028         HWRM_CHECK_RESULT();
3029
3030         /* Only TX ring value reflects actual allocation? TODO */
3031         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3032         bp->pf.evb_mode = resp->evb_mode;
3033
3034         HWRM_UNLOCK();
3035
3036         return rc;
3037 }
3038
3039 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3040 {
3041         int rc;
3042
3043         if (!BNXT_PF(bp)) {
3044                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3045                 return -EINVAL;
3046         }
3047
3048         rc = bnxt_hwrm_func_qcaps(bp);
3049         if (rc)
3050                 return rc;
3051
3052         bp->pf.func_cfg_flags &=
3053                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3054                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3055         bp->pf.func_cfg_flags |=
3056                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3057         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3058         rc = __bnxt_hwrm_func_qcaps(bp);
3059         return rc;
3060 }
3061
3062 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3063 {
3064         struct hwrm_func_cfg_input req = {0};
3065         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3066         int i;
3067         size_t sz;
3068         int rc = 0;
3069         size_t req_buf_sz;
3070
3071         if (!BNXT_PF(bp)) {
3072                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3073                 return -EINVAL;
3074         }
3075
3076         rc = bnxt_hwrm_func_qcaps(bp);
3077
3078         if (rc)
3079                 return rc;
3080
3081         bp->pf.active_vfs = num_vfs;
3082
3083         /*
3084          * First, configure the PF to only use one TX ring.  This ensures that
3085          * there are enough rings for all VFs.
3086          *
3087          * If we don't do this, when we call func_alloc() later, we will lock
3088          * extra rings to the PF that won't be available during func_cfg() of
3089          * the VFs.
3090          *
3091          * This has been fixed with firmware versions above 20.6.54
3092          */
3093         bp->pf.func_cfg_flags &=
3094                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3095                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3096         bp->pf.func_cfg_flags |=
3097                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3098         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3099         if (rc)
3100                 return rc;
3101
3102         /*
3103          * Now, create and register a buffer to hold forwarded VF requests
3104          */
3105         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3106         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3107                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3108         if (bp->pf.vf_req_buf == NULL) {
3109                 rc = -ENOMEM;
3110                 goto error_free;
3111         }
3112         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3113                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3114         for (i = 0; i < num_vfs; i++)
3115                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3116                                         (i * HWRM_MAX_REQ_LEN);
3117
3118         rc = bnxt_hwrm_func_buf_rgtr(bp);
3119         if (rc)
3120                 goto error_free;
3121
3122         populate_vf_func_cfg_req(bp, &req, num_vfs);
3123
3124         bp->pf.active_vfs = 0;
3125         for (i = 0; i < num_vfs; i++) {
3126                 add_random_mac_if_needed(bp, &req, i);
3127
3128                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3129                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3130                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3131                 rc = bnxt_hwrm_send_message(bp,
3132                                             &req,
3133                                             sizeof(req),
3134                                             BNXT_USE_CHIMP_MB);
3135
3136                 /* Clear enable flag for next pass */
3137                 req.enables &= ~rte_cpu_to_le_32(
3138                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3139
3140                 if (rc || resp->error_code) {
3141                         PMD_DRV_LOG(ERR,
3142                                 "Failed to initizlie VF %d\n", i);
3143                         PMD_DRV_LOG(ERR,
3144                                 "Not all VFs available. (%d, %d)\n",
3145                                 rc, resp->error_code);
3146                         HWRM_UNLOCK();
3147                         break;
3148                 }
3149
3150                 HWRM_UNLOCK();
3151
3152                 reserve_resources_from_vf(bp, &req, i);
3153                 bp->pf.active_vfs++;
3154                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3155         }
3156
3157         /*
3158          * Now configure the PF to use "the rest" of the resources
3159          * We're using STD_TX_RING_MODE here though which will limit the TX
3160          * rings.  This will allow QoS to function properly.  Not setting this
3161          * will cause PF rings to break bandwidth settings.
3162          */
3163         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3164         if (rc)
3165                 goto error_free;
3166
3167         rc = update_pf_resource_max(bp);
3168         if (rc)
3169                 goto error_free;
3170
3171         return rc;
3172
3173 error_free:
3174         bnxt_hwrm_func_buf_unrgtr(bp);
3175         return rc;
3176 }
3177
3178 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3179 {
3180         struct hwrm_func_cfg_input req = {0};
3181         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3182         int rc;
3183
3184         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3185
3186         req.fid = rte_cpu_to_le_16(0xffff);
3187         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3188         req.evb_mode = bp->pf.evb_mode;
3189
3190         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3191         HWRM_CHECK_RESULT();
3192         HWRM_UNLOCK();
3193
3194         return rc;
3195 }
3196
3197 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3198                                 uint8_t tunnel_type)
3199 {
3200         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3201         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3202         int rc = 0;
3203
3204         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3205         req.tunnel_type = tunnel_type;
3206         req.tunnel_dst_port_val = port;
3207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3208         HWRM_CHECK_RESULT();
3209
3210         switch (tunnel_type) {
3211         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3212                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3213                 bp->vxlan_port = port;
3214                 break;
3215         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3216                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3217                 bp->geneve_port = port;
3218                 break;
3219         default:
3220                 break;
3221         }
3222
3223         HWRM_UNLOCK();
3224
3225         return rc;
3226 }
3227
3228 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3229                                 uint8_t tunnel_type)
3230 {
3231         struct hwrm_tunnel_dst_port_free_input req = {0};
3232         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3233         int rc = 0;
3234
3235         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3236
3237         req.tunnel_type = tunnel_type;
3238         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3239         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3240
3241         HWRM_CHECK_RESULT();
3242         HWRM_UNLOCK();
3243
3244         return rc;
3245 }
3246
3247 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3248                                         uint32_t flags)
3249 {
3250         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3251         struct hwrm_func_cfg_input req = {0};
3252         int rc;
3253
3254         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3255
3256         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3257         req.flags = rte_cpu_to_le_32(flags);
3258         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3259
3260         HWRM_CHECK_RESULT();
3261         HWRM_UNLOCK();
3262
3263         return rc;
3264 }
3265
3266 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3267 {
3268         uint32_t *flag = flagp;
3269
3270         vnic->flags = *flag;
3271 }
3272
3273 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3274 {
3275         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3276 }
3277
3278 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3279 {
3280         int rc = 0;
3281         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3282         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3283
3284         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3285
3286         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3287         req.req_buf_page_size = rte_cpu_to_le_16(
3288                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3289         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3290         req.req_buf_page_addr0 =
3291                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3292         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3293                 PMD_DRV_LOG(ERR,
3294                         "unable to map buffer address to physical memory\n");
3295                 return -ENOMEM;
3296         }
3297
3298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3299
3300         HWRM_CHECK_RESULT();
3301         HWRM_UNLOCK();
3302
3303         return rc;
3304 }
3305
3306 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3307 {
3308         int rc = 0;
3309         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3310         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3311
3312         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3313                 return 0;
3314
3315         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3316
3317         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3318
3319         HWRM_CHECK_RESULT();
3320         HWRM_UNLOCK();
3321
3322         return rc;
3323 }
3324
3325 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3326 {
3327         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3328         struct hwrm_func_cfg_input req = {0};
3329         int rc;
3330
3331         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3332
3333         req.fid = rte_cpu_to_le_16(0xffff);
3334         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3335         req.enables = rte_cpu_to_le_32(
3336                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3337         req.async_event_cr = rte_cpu_to_le_16(
3338                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340
3341         HWRM_CHECK_RESULT();
3342         HWRM_UNLOCK();
3343
3344         return rc;
3345 }
3346
3347 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3348 {
3349         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3350         struct hwrm_func_vf_cfg_input req = {0};
3351         int rc;
3352
3353         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3354
3355         req.enables = rte_cpu_to_le_32(
3356                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3357         req.async_event_cr = rte_cpu_to_le_16(
3358                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3360
3361         HWRM_CHECK_RESULT();
3362         HWRM_UNLOCK();
3363
3364         return rc;
3365 }
3366
3367 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3368 {
3369         struct hwrm_func_cfg_input req = {0};
3370         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3371         uint16_t dflt_vlan, fid;
3372         uint32_t func_cfg_flags;
3373         int rc = 0;
3374
3375         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3376
3377         if (is_vf) {
3378                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3379                 fid = bp->pf.vf_info[vf].fid;
3380                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3381         } else {
3382                 fid = rte_cpu_to_le_16(0xffff);
3383                 func_cfg_flags = bp->pf.func_cfg_flags;
3384                 dflt_vlan = bp->vlan;
3385         }
3386
3387         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3388         req.fid = rte_cpu_to_le_16(fid);
3389         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3390         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3391
3392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3393
3394         HWRM_CHECK_RESULT();
3395         HWRM_UNLOCK();
3396
3397         return rc;
3398 }
3399
3400 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3401                         uint16_t max_bw, uint16_t enables)
3402 {
3403         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3404         struct hwrm_func_cfg_input req = {0};
3405         int rc;
3406
3407         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3408
3409         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3410         req.enables |= rte_cpu_to_le_32(enables);
3411         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3412         req.max_bw = rte_cpu_to_le_32(max_bw);
3413         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3414
3415         HWRM_CHECK_RESULT();
3416         HWRM_UNLOCK();
3417
3418         return rc;
3419 }
3420
3421 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3422 {
3423         struct hwrm_func_cfg_input req = {0};
3424         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3425         int rc = 0;
3426
3427         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3428
3429         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3430         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3431         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3432         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3433
3434         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3435
3436         HWRM_CHECK_RESULT();
3437         HWRM_UNLOCK();
3438
3439         return rc;
3440 }
3441
3442 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3443 {
3444         int rc;
3445
3446         if (BNXT_PF(bp))
3447                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3448         else
3449                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3450
3451         return rc;
3452 }
3453
3454 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3455                               void *encaped, size_t ec_size)
3456 {
3457         int rc = 0;
3458         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3459         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3460
3461         if (ec_size > sizeof(req.encap_request))
3462                 return -1;
3463
3464         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3465
3466         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3467         memcpy(req.encap_request, encaped, ec_size);
3468
3469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3470
3471         HWRM_CHECK_RESULT();
3472         HWRM_UNLOCK();
3473
3474         return rc;
3475 }
3476
3477 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3478                                        struct rte_ether_addr *mac)
3479 {
3480         struct hwrm_func_qcfg_input req = {0};
3481         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3482         int rc;
3483
3484         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3485
3486         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3488
3489         HWRM_CHECK_RESULT();
3490
3491         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3492
3493         HWRM_UNLOCK();
3494
3495         return rc;
3496 }
3497
3498 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3499                             void *encaped, size_t ec_size)
3500 {
3501         int rc = 0;
3502         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3503         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3504
3505         if (ec_size > sizeof(req.encap_request))
3506                 return -1;
3507
3508         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3509
3510         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3511         memcpy(req.encap_request, encaped, ec_size);
3512
3513         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3514
3515         HWRM_CHECK_RESULT();
3516         HWRM_UNLOCK();
3517
3518         return rc;
3519 }
3520
3521 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3522                          struct rte_eth_stats *stats, uint8_t rx)
3523 {
3524         int rc = 0;
3525         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3526         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3527
3528         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3529
3530         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3531
3532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3533
3534         HWRM_CHECK_RESULT();
3535
3536         if (rx) {
3537                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3538                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3539                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3540                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3541                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3542                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3543                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3544                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3545         } else {
3546                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3547                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3548                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3549                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3550                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3551                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3552         }
3553
3554
3555         HWRM_UNLOCK();
3556
3557         return rc;
3558 }
3559
3560 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3561 {
3562         struct hwrm_port_qstats_input req = {0};
3563         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3564         struct bnxt_pf_info *pf = &bp->pf;
3565         int rc;
3566
3567         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3568
3569         req.port_id = rte_cpu_to_le_16(pf->port_id);
3570         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3571         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3573
3574         HWRM_CHECK_RESULT();
3575         HWRM_UNLOCK();
3576
3577         return rc;
3578 }
3579
3580 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3581 {
3582         struct hwrm_port_clr_stats_input req = {0};
3583         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3584         struct bnxt_pf_info *pf = &bp->pf;
3585         int rc;
3586
3587         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3588         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3589             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3590                 return 0;
3591
3592         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3593
3594         req.port_id = rte_cpu_to_le_16(pf->port_id);
3595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3596
3597         HWRM_CHECK_RESULT();
3598         HWRM_UNLOCK();
3599
3600         return rc;
3601 }
3602
3603 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3604 {
3605         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3606         struct hwrm_port_led_qcaps_input req = {0};
3607         int rc;
3608
3609         if (BNXT_VF(bp))
3610                 return 0;
3611
3612         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3613         req.port_id = bp->pf.port_id;
3614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3615
3616         HWRM_CHECK_RESULT();
3617
3618         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3619                 unsigned int i;
3620
3621                 bp->num_leds = resp->num_leds;
3622                 memcpy(bp->leds, &resp->led0_id,
3623                         sizeof(bp->leds[0]) * bp->num_leds);
3624                 for (i = 0; i < bp->num_leds; i++) {
3625                         struct bnxt_led_info *led = &bp->leds[i];
3626
3627                         uint16_t caps = led->led_state_caps;
3628
3629                         if (!led->led_group_id ||
3630                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3631                                 bp->num_leds = 0;
3632                                 break;
3633                         }
3634                 }
3635         }
3636
3637         HWRM_UNLOCK();
3638
3639         return rc;
3640 }
3641
3642 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3643 {
3644         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3645         struct hwrm_port_led_cfg_input req = {0};
3646         struct bnxt_led_cfg *led_cfg;
3647         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3648         uint16_t duration = 0;
3649         int rc, i;
3650
3651         if (!bp->num_leds || BNXT_VF(bp))
3652                 return -EOPNOTSUPP;
3653
3654         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3655
3656         if (led_on) {
3657                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3658                 duration = rte_cpu_to_le_16(500);
3659         }
3660         req.port_id = bp->pf.port_id;
3661         req.num_leds = bp->num_leds;
3662         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3663         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3664                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3665                 led_cfg->led_id = bp->leds[i].led_id;
3666                 led_cfg->led_state = led_state;
3667                 led_cfg->led_blink_on = duration;
3668                 led_cfg->led_blink_off = duration;
3669                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3670         }
3671
3672         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3673
3674         HWRM_CHECK_RESULT();
3675         HWRM_UNLOCK();
3676
3677         return rc;
3678 }
3679
3680 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3681                                uint32_t *length)
3682 {
3683         int rc;
3684         struct hwrm_nvm_get_dir_info_input req = {0};
3685         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3686
3687         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3688
3689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3690
3691         HWRM_CHECK_RESULT();
3692
3693         *entries = rte_le_to_cpu_32(resp->entries);
3694         *length = rte_le_to_cpu_32(resp->entry_length);
3695
3696         HWRM_UNLOCK();
3697         return rc;
3698 }
3699
3700 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3701 {
3702         int rc;
3703         uint32_t dir_entries;
3704         uint32_t entry_length;
3705         uint8_t *buf;
3706         size_t buflen;
3707         rte_iova_t dma_handle;
3708         struct hwrm_nvm_get_dir_entries_input req = {0};
3709         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3710
3711         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3712         if (rc != 0)
3713                 return rc;
3714
3715         *data++ = dir_entries;
3716         *data++ = entry_length;
3717         len -= 2;
3718         memset(data, 0xff, len);
3719
3720         buflen = dir_entries * entry_length;
3721         buf = rte_malloc("nvm_dir", buflen, 0);
3722         rte_mem_lock_page(buf);
3723         if (buf == NULL)
3724                 return -ENOMEM;
3725         dma_handle = rte_mem_virt2iova(buf);
3726         if (dma_handle == RTE_BAD_IOVA) {
3727                 PMD_DRV_LOG(ERR,
3728                         "unable to map response address to physical memory\n");
3729                 return -ENOMEM;
3730         }
3731         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3732         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3733         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3734
3735         if (rc == 0)
3736                 memcpy(data, buf, len > buflen ? buflen : len);
3737
3738         rte_free(buf);
3739         HWRM_CHECK_RESULT();
3740         HWRM_UNLOCK();
3741
3742         return rc;
3743 }
3744
3745 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3746                              uint32_t offset, uint32_t length,
3747                              uint8_t *data)
3748 {
3749         int rc;
3750         uint8_t *buf;
3751         rte_iova_t dma_handle;
3752         struct hwrm_nvm_read_input req = {0};
3753         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3754
3755         buf = rte_malloc("nvm_item", length, 0);
3756         rte_mem_lock_page(buf);
3757         if (!buf)
3758                 return -ENOMEM;
3759
3760         dma_handle = rte_mem_virt2iova(buf);
3761         if (dma_handle == RTE_BAD_IOVA) {
3762                 PMD_DRV_LOG(ERR,
3763                         "unable to map response address to physical memory\n");
3764                 return -ENOMEM;
3765         }
3766         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3767         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3768         req.dir_idx = rte_cpu_to_le_16(index);
3769         req.offset = rte_cpu_to_le_32(offset);
3770         req.len = rte_cpu_to_le_32(length);
3771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3772         if (rc == 0)
3773                 memcpy(data, buf, length);
3774
3775         rte_free(buf);
3776         HWRM_CHECK_RESULT();
3777         HWRM_UNLOCK();
3778
3779         return rc;
3780 }
3781
3782 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3783 {
3784         int rc;
3785         struct hwrm_nvm_erase_dir_entry_input req = {0};
3786         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3787
3788         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3789         req.dir_idx = rte_cpu_to_le_16(index);
3790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3791         HWRM_CHECK_RESULT();
3792         HWRM_UNLOCK();
3793
3794         return rc;
3795 }
3796
3797
3798 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3799                           uint16_t dir_ordinal, uint16_t dir_ext,
3800                           uint16_t dir_attr, const uint8_t *data,
3801                           size_t data_len)
3802 {
3803         int rc;
3804         struct hwrm_nvm_write_input req = {0};
3805         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3806         rte_iova_t dma_handle;
3807         uint8_t *buf;
3808
3809         buf = rte_malloc("nvm_write", data_len, 0);
3810         rte_mem_lock_page(buf);
3811         if (!buf)
3812                 return -ENOMEM;
3813
3814         dma_handle = rte_mem_virt2iova(buf);
3815         if (dma_handle == RTE_BAD_IOVA) {
3816                 PMD_DRV_LOG(ERR,
3817                         "unable to map response address to physical memory\n");
3818                 return -ENOMEM;
3819         }
3820         memcpy(buf, data, data_len);
3821
3822         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3823
3824         req.dir_type = rte_cpu_to_le_16(dir_type);
3825         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3826         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3827         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3828         req.dir_data_length = rte_cpu_to_le_32(data_len);
3829         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3830
3831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3832
3833         rte_free(buf);
3834         HWRM_CHECK_RESULT();
3835         HWRM_UNLOCK();
3836
3837         return rc;
3838 }
3839
3840 static void
3841 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3842 {
3843         uint32_t *count = cbdata;
3844
3845         *count = *count + 1;
3846 }
3847
3848 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3849                                      struct bnxt_vnic_info *vnic __rte_unused)
3850 {
3851         return 0;
3852 }
3853
3854 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3855 {
3856         uint32_t count = 0;
3857
3858         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3859             &count, bnxt_vnic_count_hwrm_stub);
3860
3861         return count;
3862 }
3863
3864 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3865                                         uint16_t *vnic_ids)
3866 {
3867         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3868         struct hwrm_func_vf_vnic_ids_query_output *resp =
3869                                                 bp->hwrm_cmd_resp_addr;
3870         int rc;
3871
3872         /* First query all VNIC ids */
3873         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3874
3875         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3876         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3877         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3878
3879         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3880                 HWRM_UNLOCK();
3881                 PMD_DRV_LOG(ERR,
3882                 "unable to map VNIC ID table address to physical memory\n");
3883                 return -ENOMEM;
3884         }
3885         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3886         HWRM_CHECK_RESULT();
3887         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3888
3889         HWRM_UNLOCK();
3890
3891         return rc;
3892 }
3893
3894 /*
3895  * This function queries the VNIC IDs  for a specified VF. It then calls
3896  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3897  * Then it calls the hwrm_cb function to program this new vnic configuration.
3898  */
3899 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3900         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3901         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3902 {
3903         struct bnxt_vnic_info vnic;
3904         int rc = 0;
3905         int i, num_vnic_ids;
3906         uint16_t *vnic_ids;
3907         size_t vnic_id_sz;
3908         size_t sz;
3909
3910         /* First query all VNIC ids */
3911         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3912         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3913                         RTE_CACHE_LINE_SIZE);
3914         if (vnic_ids == NULL)
3915                 return -ENOMEM;
3916
3917         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3918                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3919
3920         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3921
3922         if (num_vnic_ids < 0)
3923                 return num_vnic_ids;
3924
3925         /* Retrieve VNIC, update bd_stall then update */
3926
3927         for (i = 0; i < num_vnic_ids; i++) {
3928                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3929                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3930                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3931                 if (rc)
3932                         break;
3933                 if (vnic.mru <= 4)      /* Indicates unallocated */
3934                         continue;
3935
3936                 vnic_cb(&vnic, cbdata);
3937
3938                 rc = hwrm_cb(bp, &vnic);
3939                 if (rc)
3940                         break;
3941         }
3942
3943         rte_free(vnic_ids);
3944
3945         return rc;
3946 }
3947
3948 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3949                                               bool on)
3950 {
3951         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3952         struct hwrm_func_cfg_input req = {0};
3953         int rc;
3954
3955         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3956
3957         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3958         req.enables |= rte_cpu_to_le_32(
3959                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3960         req.vlan_antispoof_mode = on ?
3961                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3962                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3963         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3964
3965         HWRM_CHECK_RESULT();
3966         HWRM_UNLOCK();
3967
3968         return rc;
3969 }
3970
3971 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3972 {
3973         struct bnxt_vnic_info vnic;
3974         uint16_t *vnic_ids;
3975         size_t vnic_id_sz;
3976         int num_vnic_ids, i;
3977         size_t sz;
3978         int rc;
3979
3980         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3981         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3982                         RTE_CACHE_LINE_SIZE);
3983         if (vnic_ids == NULL)
3984                 return -ENOMEM;
3985
3986         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3987                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3988
3989         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3990         if (rc <= 0)
3991                 goto exit;
3992         num_vnic_ids = rc;
3993
3994         /*
3995          * Loop through to find the default VNIC ID.
3996          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3997          * by sending the hwrm_func_qcfg command to the firmware.
3998          */
3999         for (i = 0; i < num_vnic_ids; i++) {
4000                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4001                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4002                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4003                                         bp->pf.first_vf_id + vf);
4004                 if (rc)
4005                         goto exit;
4006                 if (vnic.func_default) {
4007                         rte_free(vnic_ids);
4008                         return vnic.fw_vnic_id;
4009                 }
4010         }
4011         /* Could not find a default VNIC. */
4012         PMD_DRV_LOG(ERR, "No default VNIC\n");
4013 exit:
4014         rte_free(vnic_ids);
4015         return rc;
4016 }
4017
4018 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4019                          uint16_t dst_id,
4020                          struct bnxt_filter_info *filter)
4021 {
4022         int rc = 0;
4023         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4024         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4025         uint32_t enables = 0;
4026
4027         if (filter->fw_em_filter_id != UINT64_MAX)
4028                 bnxt_hwrm_clear_em_filter(bp, filter);
4029
4030         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4031
4032         req.flags = rte_cpu_to_le_32(filter->flags);
4033
4034         enables = filter->enables |
4035               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4036         req.dst_id = rte_cpu_to_le_16(dst_id);
4037
4038         if (filter->ip_addr_type) {
4039                 req.ip_addr_type = filter->ip_addr_type;
4040                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4041         }
4042         if (enables &
4043             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4044                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4045         if (enables &
4046             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4047                 memcpy(req.src_macaddr, filter->src_macaddr,
4048                        RTE_ETHER_ADDR_LEN);
4049         if (enables &
4050             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4051                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4052                        RTE_ETHER_ADDR_LEN);
4053         if (enables &
4054             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4055                 req.ovlan_vid = filter->l2_ovlan;
4056         if (enables &
4057             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4058                 req.ivlan_vid = filter->l2_ivlan;
4059         if (enables &
4060             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4061                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4062         if (enables &
4063             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4064                 req.ip_protocol = filter->ip_protocol;
4065         if (enables &
4066             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4067                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4068         if (enables &
4069             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4070                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4071         if (enables &
4072             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4073                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4074         if (enables &
4075             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4076                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4077         if (enables &
4078             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4079                 req.mirror_vnic_id = filter->mirror_vnic_id;
4080
4081         req.enables = rte_cpu_to_le_32(enables);
4082
4083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4084
4085         HWRM_CHECK_RESULT();
4086
4087         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4088         HWRM_UNLOCK();
4089
4090         return rc;
4091 }
4092
4093 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4094 {
4095         int rc = 0;
4096         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4097         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4098
4099         if (filter->fw_em_filter_id == UINT64_MAX)
4100                 return 0;
4101
4102         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4103         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4104
4105         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4106
4107         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4108
4109         HWRM_CHECK_RESULT();
4110         HWRM_UNLOCK();
4111
4112         filter->fw_em_filter_id = UINT64_MAX;
4113         filter->fw_l2_filter_id = UINT64_MAX;
4114
4115         return 0;
4116 }
4117
4118 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4119                          uint16_t dst_id,
4120                          struct bnxt_filter_info *filter)
4121 {
4122         int rc = 0;
4123         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4124         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4125                                                 bp->hwrm_cmd_resp_addr;
4126         uint32_t enables = 0;
4127
4128         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4129                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4130
4131         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4132
4133         req.flags = rte_cpu_to_le_32(filter->flags);
4134
4135         enables = filter->enables |
4136               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4137         req.dst_id = rte_cpu_to_le_16(dst_id);
4138
4139
4140         if (filter->ip_addr_type) {
4141                 req.ip_addr_type = filter->ip_addr_type;
4142                 enables |=
4143                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4144         }
4145         if (enables &
4146             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4147                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4148         if (enables &
4149             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4150                 memcpy(req.src_macaddr, filter->src_macaddr,
4151                        RTE_ETHER_ADDR_LEN);
4152         //if (enables &
4153             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4154                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4155                        //RTE_ETHER_ADDR_LEN);
4156         if (enables &
4157             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4158                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4159         if (enables &
4160             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4161                 req.ip_protocol = filter->ip_protocol;
4162         if (enables &
4163             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4164                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4165         if (enables &
4166             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4167                 req.src_ipaddr_mask[0] =
4168                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4169         if (enables &
4170             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4171                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4172         if (enables &
4173             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4174                 req.dst_ipaddr_mask[0] =
4175                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4176         if (enables &
4177             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4178                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4179         if (enables &
4180             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4181                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4182         if (enables &
4183             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4184                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4185         if (enables &
4186             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4187                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4188         if (enables &
4189             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4190                 req.mirror_vnic_id = filter->mirror_vnic_id;
4191
4192         req.enables = rte_cpu_to_le_32(enables);
4193
4194         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4195
4196         HWRM_CHECK_RESULT();
4197
4198         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4199         HWRM_UNLOCK();
4200
4201         return rc;
4202 }
4203
4204 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4205                                 struct bnxt_filter_info *filter)
4206 {
4207         int rc = 0;
4208         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4209         struct hwrm_cfa_ntuple_filter_free_output *resp =
4210                                                 bp->hwrm_cmd_resp_addr;
4211
4212         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4213                 return 0;
4214
4215         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4216
4217         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4218
4219         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4220
4221         HWRM_CHECK_RESULT();
4222         HWRM_UNLOCK();
4223
4224         filter->fw_ntuple_filter_id = UINT64_MAX;
4225
4226         return 0;
4227 }
4228
4229 static int
4230 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4231 {
4232         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4233         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4234         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4235         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4236         uint16_t *ring_tbl = vnic->rss_table;
4237         int nr_ctxs = vnic->num_lb_ctxts;
4238         int max_rings = bp->rx_nr_rings;
4239         int i, j, k, cnt;
4240         int rc = 0;
4241
4242         for (i = 0, k = 0; i < nr_ctxs; i++) {
4243                 struct bnxt_rx_ring_info *rxr;
4244                 struct bnxt_cp_ring_info *cpr;
4245
4246                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4247
4248                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4249                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4250                 req.hash_mode_flags = vnic->hash_mode;
4251
4252                 req.ring_grp_tbl_addr =
4253                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4254                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4255                                      2 * sizeof(*ring_tbl));
4256                 req.hash_key_tbl_addr =
4257                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4258
4259                 req.ring_table_pair_index = i;
4260                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4261
4262                 for (j = 0; j < 64; j++) {
4263                         uint16_t ring_id;
4264
4265                         /* Find next active ring. */
4266                         for (cnt = 0; cnt < max_rings; cnt++) {
4267                                 if (rx_queue_state[k] !=
4268                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4269                                         break;
4270                                 if (++k == max_rings)
4271                                         k = 0;
4272                         }
4273
4274                         /* Return if no rings are active. */
4275                         if (cnt == max_rings)
4276                                 return 0;
4277
4278                         /* Add rx/cp ring pair to RSS table. */
4279                         rxr = rxqs[k]->rx_ring;
4280                         cpr = rxqs[k]->cp_ring;
4281
4282                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4283                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4284                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4285                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4286
4287                         if (++k == max_rings)
4288                                 k = 0;
4289                 }
4290                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4291                                             BNXT_USE_CHIMP_MB);
4292
4293                 HWRM_CHECK_RESULT();
4294                 HWRM_UNLOCK();
4295         }
4296
4297         return rc;
4298 }
4299
4300 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4301 {
4302         unsigned int rss_idx, fw_idx, i;
4303
4304         if (!(vnic->rss_table && vnic->hash_type))
4305                 return 0;
4306
4307         if (BNXT_CHIP_THOR(bp))
4308                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4309
4310         /*
4311          * Fill the RSS hash & redirection table with
4312          * ring group ids for all VNICs
4313          */
4314         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4315                 rss_idx++, fw_idx++) {
4316                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4317                         fw_idx %= bp->rx_cp_nr_rings;
4318                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4319                                 break;
4320                         fw_idx++;
4321                 }
4322                 if (i == bp->rx_cp_nr_rings)
4323                         return 0;
4324                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4325         }
4326         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4327 }
4328
4329 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4330         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4331 {
4332         uint16_t flags;
4333
4334         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4335
4336         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4337         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4338
4339         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4340         req->num_cmpl_dma_aggr_during_int =
4341                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4342
4343         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4344
4345         /* min timer set to 1/2 of interrupt timer */
4346         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4347
4348         /* buf timer set to 1/4 of interrupt timer */
4349         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4350
4351         req->cmpl_aggr_dma_tmr_during_int =
4352                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4353
4354         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4355                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4356         req->flags = rte_cpu_to_le_16(flags);
4357 }
4358
4359 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4360                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4361 {
4362         struct hwrm_ring_aggint_qcaps_input req = {0};
4363         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4364         uint32_t enables;
4365         uint16_t flags;
4366         int rc;
4367
4368         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4369         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4370         HWRM_CHECK_RESULT();
4371
4372         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4373         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4374
4375         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4376                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4377         agg_req->flags = rte_cpu_to_le_16(flags);
4378         enables =
4379          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4380          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4381         agg_req->enables = rte_cpu_to_le_32(enables);
4382
4383         HWRM_UNLOCK();
4384         return rc;
4385 }
4386
4387 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4388                         struct bnxt_coal *coal, uint16_t ring_id)
4389 {
4390         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4391         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4392                                                 bp->hwrm_cmd_resp_addr;
4393         int rc;
4394
4395         /* Set ring coalesce parameters only for 100G NICs */
4396         if (BNXT_CHIP_THOR(bp)) {
4397                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4398                         return -1;
4399         } else if (bnxt_stratus_device(bp)) {
4400                 bnxt_hwrm_set_coal_params(coal, &req);
4401         } else {
4402                 return 0;
4403         }
4404
4405         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4406         req.ring_id = rte_cpu_to_le_16(ring_id);
4407         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4408         HWRM_CHECK_RESULT();
4409         HWRM_UNLOCK();
4410         return 0;
4411 }
4412
4413 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4414 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4415 {
4416         struct hwrm_func_backing_store_qcaps_input req = {0};
4417         struct hwrm_func_backing_store_qcaps_output *resp =
4418                 bp->hwrm_cmd_resp_addr;
4419         struct bnxt_ctx_pg_info *ctx_pg;
4420         struct bnxt_ctx_mem_info *ctx;
4421         int total_alloc_len;
4422         int rc, i;
4423
4424         if (!BNXT_CHIP_THOR(bp) ||
4425             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4426             BNXT_VF(bp) ||
4427             bp->ctx)
4428                 return 0;
4429
4430         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4431         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4432         HWRM_CHECK_RESULT_SILENT();
4433
4434         total_alloc_len = sizeof(*ctx);
4435         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4436                           RTE_CACHE_LINE_SIZE);
4437         if (!ctx) {
4438                 rc = -ENOMEM;
4439                 goto ctx_err;
4440         }
4441
4442         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4443                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4444                             RTE_CACHE_LINE_SIZE);
4445         if (!ctx_pg) {
4446                 rc = -ENOMEM;
4447                 goto ctx_err;
4448         }
4449         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4450                 ctx->tqm_mem[i] = ctx_pg;
4451
4452         bp->ctx = ctx;
4453         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4454         ctx->qp_min_qp1_entries =
4455                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4456         ctx->qp_max_l2_entries =
4457                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4458         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4459         ctx->srq_max_l2_entries =
4460                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4461         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4462         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4463         ctx->cq_max_l2_entries =
4464                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4465         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4466         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4467         ctx->vnic_max_vnic_entries =
4468                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4469         ctx->vnic_max_ring_table_entries =
4470                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4471         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4472         ctx->stat_max_entries =
4473                 rte_le_to_cpu_32(resp->stat_max_entries);
4474         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4475         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4476         ctx->tqm_min_entries_per_ring =
4477                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4478         ctx->tqm_max_entries_per_ring =
4479                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4480         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4481         if (!ctx->tqm_entries_multiple)
4482                 ctx->tqm_entries_multiple = 1;
4483         ctx->mrav_max_entries =
4484                 rte_le_to_cpu_32(resp->mrav_max_entries);
4485         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4486         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4487         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4488 ctx_err:
4489         HWRM_UNLOCK();
4490         return rc;
4491 }
4492
4493 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4494 {
4495         struct hwrm_func_backing_store_cfg_input req = {0};
4496         struct hwrm_func_backing_store_cfg_output *resp =
4497                 bp->hwrm_cmd_resp_addr;
4498         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4499         struct bnxt_ctx_pg_info *ctx_pg;
4500         uint32_t *num_entries;
4501         uint64_t *pg_dir;
4502         uint8_t *pg_attr;
4503         uint32_t ena;
4504         int i, rc;
4505
4506         if (!ctx)
4507                 return 0;
4508
4509         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4510         req.enables = rte_cpu_to_le_32(enables);
4511
4512         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4513                 ctx_pg = &ctx->qp_mem;
4514                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4515                 req.qp_num_qp1_entries =
4516                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4517                 req.qp_num_l2_entries =
4518                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4519                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4520                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4521                                       &req.qpc_pg_size_qpc_lvl,
4522                                       &req.qpc_page_dir);
4523         }
4524
4525         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4526                 ctx_pg = &ctx->srq_mem;
4527                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4528                 req.srq_num_l2_entries =
4529                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4530                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4531                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4532                                       &req.srq_pg_size_srq_lvl,
4533                                       &req.srq_page_dir);
4534         }
4535
4536         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4537                 ctx_pg = &ctx->cq_mem;
4538                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4539                 req.cq_num_l2_entries =
4540                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4541                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4542                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4543                                       &req.cq_pg_size_cq_lvl,
4544                                       &req.cq_page_dir);
4545         }
4546
4547         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4548                 ctx_pg = &ctx->vnic_mem;
4549                 req.vnic_num_vnic_entries =
4550                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4551                 req.vnic_num_ring_table_entries =
4552                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4553                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4554                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4555                                       &req.vnic_pg_size_vnic_lvl,
4556                                       &req.vnic_page_dir);
4557         }
4558
4559         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4560                 ctx_pg = &ctx->stat_mem;
4561                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4562                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4563                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4564                                       &req.stat_pg_size_stat_lvl,
4565                                       &req.stat_page_dir);
4566         }
4567
4568         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4569         num_entries = &req.tqm_sp_num_entries;
4570         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4571         pg_dir = &req.tqm_sp_page_dir;
4572         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4573         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4574                 if (!(enables & ena))
4575                         continue;
4576
4577                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4578
4579                 ctx_pg = ctx->tqm_mem[i];
4580                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4581                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4582         }
4583
4584         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4585         HWRM_CHECK_RESULT();
4586         HWRM_UNLOCK();
4587
4588         return rc;
4589 }
4590
4591 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4592 {
4593         struct hwrm_port_qstats_ext_input req = {0};
4594         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4595         struct bnxt_pf_info *pf = &bp->pf;
4596         int rc;
4597
4598         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4599               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4600                 return 0;
4601
4602         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4603
4604         req.port_id = rte_cpu_to_le_16(pf->port_id);
4605         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4606                 req.tx_stat_host_addr =
4607                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4608                 req.tx_stat_size =
4609                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4610         }
4611         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4612                 req.rx_stat_host_addr =
4613                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4614                 req.rx_stat_size =
4615                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4616         }
4617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4618
4619         if (rc) {
4620                 bp->fw_rx_port_stats_ext_size = 0;
4621                 bp->fw_tx_port_stats_ext_size = 0;
4622         } else {
4623                 bp->fw_rx_port_stats_ext_size =
4624                         rte_le_to_cpu_16(resp->rx_stat_size);
4625                 bp->fw_tx_port_stats_ext_size =
4626                         rte_le_to_cpu_16(resp->tx_stat_size);
4627         }
4628
4629         HWRM_CHECK_RESULT();
4630         HWRM_UNLOCK();
4631
4632         return rc;
4633 }
4634
4635 int
4636 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4637 {
4638         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4639         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4640                 bp->hwrm_cmd_resp_addr;
4641         int rc = 0;
4642
4643         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4644         req.tunnel_type = type;
4645         req.dest_fid = bp->fw_fid;
4646         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4647         HWRM_CHECK_RESULT();
4648
4649         HWRM_UNLOCK();
4650
4651         return rc;
4652 }
4653
4654 int
4655 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4656 {
4657         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4658         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4659                 bp->hwrm_cmd_resp_addr;
4660         int rc = 0;
4661
4662         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4663         req.tunnel_type = type;
4664         req.dest_fid = bp->fw_fid;
4665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4666         HWRM_CHECK_RESULT();
4667
4668         HWRM_UNLOCK();
4669
4670         return rc;
4671 }
4672
4673 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4674 {
4675         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4676         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4677                 bp->hwrm_cmd_resp_addr;
4678         int rc = 0;
4679
4680         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4681         req.src_fid = bp->fw_fid;
4682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4683         HWRM_CHECK_RESULT();
4684
4685         if (type)
4686                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4687
4688         HWRM_UNLOCK();
4689
4690         return rc;
4691 }
4692
4693 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4694                                    uint16_t *dst_fid)
4695 {
4696         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4697         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4698                 bp->hwrm_cmd_resp_addr;
4699         int rc = 0;
4700
4701         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4702         req.src_fid = bp->fw_fid;
4703         req.tunnel_type = tun_type;
4704         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4705         HWRM_CHECK_RESULT();
4706
4707         if (dst_fid)
4708                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4709
4710         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4711
4712         HWRM_UNLOCK();
4713
4714         return rc;
4715 }
4716
4717 int bnxt_hwrm_set_mac(struct bnxt *bp)
4718 {
4719         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4720         struct hwrm_func_vf_cfg_input req = {0};
4721         int rc = 0;
4722
4723         if (!BNXT_VF(bp))
4724                 return 0;
4725
4726         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4727
4728         req.enables =
4729                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4730         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4731
4732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4733
4734         HWRM_CHECK_RESULT();
4735
4736         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4737         HWRM_UNLOCK();
4738
4739         return rc;
4740 }
4741
4742 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4743 {
4744         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4745         struct hwrm_func_drv_if_change_input req = {0};
4746         uint32_t flags;
4747         int rc;
4748
4749         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4750                 return 0;
4751
4752         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4753          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4754          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4755          */
4756         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4757                 return 0;
4758
4759         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4760
4761         if (up)
4762                 req.flags =
4763                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4764
4765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4766
4767         HWRM_CHECK_RESULT();
4768         flags = rte_le_to_cpu_32(resp->flags);
4769         HWRM_UNLOCK();
4770
4771         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4772                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4773                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4774         }
4775
4776         return 0;
4777 }
4778
4779 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4780 {
4781         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4782         struct bnxt_error_recovery_info *info = bp->recovery_info;
4783         struct hwrm_error_recovery_qcfg_input req = {0};
4784         uint32_t flags = 0;
4785         unsigned int i;
4786         int rc;
4787
4788         /* Older FW does not have error recovery support */
4789         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4790                 return 0;
4791
4792         if (!info) {
4793                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4794                                    sizeof(*info), 0);
4795                 bp->recovery_info = info;
4796                 if (info == NULL)
4797                         return -ENOMEM;
4798         } else {
4799                 memset(info, 0, sizeof(*info));
4800         }
4801
4802         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4803
4804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4805
4806         HWRM_CHECK_RESULT();
4807
4808         flags = rte_le_to_cpu_32(resp->flags);
4809         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4810                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4811         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4812                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4813
4814         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4815             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4816                 rc = -EINVAL;
4817                 goto err;
4818         }
4819
4820         /* FW returned values are in units of 100msec */
4821         info->driver_polling_freq =
4822                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4823         info->master_func_wait_period =
4824                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4825         info->normal_func_wait_period =
4826                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4827         info->master_func_wait_period_after_reset =
4828                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4829         info->max_bailout_time_after_reset =
4830                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4831         info->status_regs[BNXT_FW_STATUS_REG] =
4832                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4833         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4834                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4835         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4836                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4837         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4838                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4839         info->reg_array_cnt =
4840                 rte_le_to_cpu_32(resp->reg_array_cnt);
4841
4842         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4843                 rc = -EINVAL;
4844                 goto err;
4845         }
4846
4847         for (i = 0; i < info->reg_array_cnt; i++) {
4848                 info->reset_reg[i] =
4849                         rte_le_to_cpu_32(resp->reset_reg[i]);
4850                 info->reset_reg_val[i] =
4851                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4852                 info->delay_after_reset[i] =
4853                         resp->delay_after_reset[i];
4854         }
4855 err:
4856         HWRM_UNLOCK();
4857
4858         /* Map the FW status registers */
4859         if (!rc)
4860                 rc = bnxt_map_fw_health_status_regs(bp);
4861
4862         if (rc) {
4863                 rte_free(bp->recovery_info);
4864                 bp->recovery_info = NULL;
4865         }
4866         return rc;
4867 }
4868
4869 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4870 {
4871         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4872         struct hwrm_fw_reset_input req = {0};
4873         int rc;
4874
4875         if (!BNXT_PF(bp))
4876                 return -EOPNOTSUPP;
4877
4878         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4879
4880         req.embedded_proc_type =
4881                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4882         req.selfrst_status =
4883                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4884         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4885
4886         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4887                                     BNXT_USE_KONG(bp));
4888
4889         HWRM_CHECK_RESULT();
4890         HWRM_UNLOCK();
4891
4892         return rc;
4893 }
4894
4895 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4896 {
4897         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4898         struct hwrm_port_ts_query_input req = {0};
4899         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4900         uint32_t flags = 0;
4901         int rc;
4902
4903         if (!ptp)
4904                 return 0;
4905
4906         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4907
4908         switch (path) {
4909         case BNXT_PTP_FLAGS_PATH_TX:
4910                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4911                 break;
4912         case BNXT_PTP_FLAGS_PATH_RX:
4913                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4914                 break;
4915         case BNXT_PTP_FLAGS_CURRENT_TIME:
4916                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4917                 break;
4918         }
4919
4920         req.flags = rte_cpu_to_le_32(flags);
4921         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4922
4923         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4924
4925         HWRM_CHECK_RESULT();
4926
4927         if (timestamp) {
4928                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4929                 *timestamp |=
4930                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4931         }
4932         HWRM_UNLOCK();
4933
4934         return rc;
4935 }
4936
4937 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
4938 {
4939         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
4940                                         bp->hwrm_cmd_resp_addr;
4941         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
4942         uint32_t flags = 0;
4943         int rc = 0;
4944
4945         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
4946                 return rc;
4947
4948         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
4949                 PMD_DRV_LOG(DEBUG,
4950                             "Not a PF or trusted VF. Command not supported\n");
4951                 return 0;
4952         }
4953
4954         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
4955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4956
4957         HWRM_CHECK_RESULT();
4958         flags = rte_le_to_cpu_32(resp->flags);
4959         HWRM_UNLOCK();
4960
4961         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
4962                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
4963                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
4964         }
4965
4966         return rc;
4967 }