drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                10000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns.  If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 193 } while (0)
 194
 195 #define HWRM_CHECK_RESULT() do {\
 196         if (rc) { \
 197                 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 198                         __func__, rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 return rc; \
 201         } \
 202         if (resp->error_code) { \
 203                 rc = rte_le_to_cpu_16(resp->error_code); \
 204                 if (resp->resp_len >= 16) { \
 205                         struct hwrm_err_output *tmp_hwrm_err_op = \
 206                                                 (void *)resp; \
 207                         RTE_LOG(ERR, PMD, \
 208                                 "%s error %d:%d:%08x:%04x\n", \
 209                                 __func__, \
 210                                 rc, tmp_hwrm_err_op->cmd_err, \
 211                                 rte_le_to_cpu_32(\
 212                                         tmp_hwrm_err_op->opaque_0), \
 213                                 rte_le_to_cpu_16(\
 214                                         tmp_hwrm_err_op->opaque_1)); \
 215                 } \
 216                 else { \
 217                         RTE_LOG(ERR, PMD, \
 218                                 "%s error %d\n", __func__, rc); \
 219                 } \
 220                 rte_spinlock_unlock(&bp->hwrm_lock); \
 221                 return rc; \
 222         } \
 223 } while (0)
 224
 225 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 226
 227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 228 {
 229         int rc = 0;
 230         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 231         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 232
 233         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 234         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 235         req.mask = 0;
 236
 237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 238
 239         HWRM_CHECK_RESULT();
 240         HWRM_UNLOCK();
 241
 242         return rc;
 243 }
 244
 245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 246                                  struct bnxt_vnic_info *vnic,
 247                                  uint16_t vlan_count,
 248                                  struct bnxt_vlan_table_entry *vlan_table)
 249 {
 250         int rc = 0;
 251         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 252         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 253         uint32_t mask = 0;
 254
 255         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 257
 258         /* FIXME add multicast flag, when multicast adding options is supported
 259          * by ethtool.
 260          */
 261         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 262                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 263         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 264                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 265         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 266                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 267         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 268                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 269         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 271         if (vnic->mc_addr_cnt) {
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 273                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 274                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 275         }
 276         if (vlan_table) {
 277                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 278                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 279                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 280                          rte_mem_virt2phy(vlan_table));
 281                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 282         }
 283         req.mask = rte_cpu_to_le_32(mask);
 284
 285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 286
 287         HWRM_CHECK_RESULT();
 288         HWRM_UNLOCK();
 289
 290         return rc;
 291 }
 292
 293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 294                         uint16_t vlan_count,
 295                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 296 {
 297         int rc = 0;
 298         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 299         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 300                                                 bp->hwrm_cmd_resp_addr;
 301
 302         /*
 303          * Older HWRM versions did not support this command, and the set_rx_mask
 304          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 305          * removed from set_rx_mask call, and this command was added.
 306          *
 307          * This command is also present from 1.7.8.11 and higher,
 308          * as well as 1.7.8.0
 309          */
 310         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 311                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 312                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 313                                         (11)))
 314                                 return 0;
 315                 }
 316         }
 317         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 318         req.fid = rte_cpu_to_le_16(fid);
 319
 320         req.vlan_tag_mask_tbl_addr =
 321                 rte_cpu_to_le_64(rte_mem_virt2phy(vlan_table));
 322         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 323
 324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 325
 326         HWRM_CHECK_RESULT();
 327         HWRM_UNLOCK();
 328
 329         return rc;
 330 }
 331
 332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 333                            struct bnxt_filter_info *filter)
 334 {
 335         int rc = 0;
 336         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 337         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 338
 339         if (filter->fw_l2_filter_id == UINT64_MAX)
 340                 return 0;
 341
 342         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 343
 344         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 345
 346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 347
 348         HWRM_CHECK_RESULT();
 349         HWRM_UNLOCK();
 350
 351         filter->fw_l2_filter_id = -1;
 352
 353         return 0;
 354 }
 355
 356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 357                          uint16_t dst_id,
 358                          struct bnxt_filter_info *filter)
 359 {
 360         int rc = 0;
 361         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 362         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 363         uint32_t enables = 0;
 364
 365         if (filter->fw_l2_filter_id != UINT64_MAX)
 366                 bnxt_hwrm_clear_l2_filter(bp, filter);
 367
 368         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 369
 370         req.flags = rte_cpu_to_le_32(filter->flags);
 371
 372         enables = filter->enables |
 373               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 374         req.dst_id = rte_cpu_to_le_16(dst_id);
 375
 376         if (enables &
 377             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 378                 memcpy(req.l2_addr, filter->l2_addr,
 379                        ETHER_ADDR_LEN);
 380         if (enables &
 381             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 382                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 383                        ETHER_ADDR_LEN);
 384         if (enables &
 385             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 386                 req.l2_ovlan = filter->l2_ovlan;
 387         if (enables &
 388             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 389                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 390         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 391                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 392         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 393                 req.src_type = filter->src_type;
 394
 395         req.enables = rte_cpu_to_le_32(enables);
 396
 397         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 398
 399         HWRM_CHECK_RESULT();
 400
 401         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 402         HWRM_UNLOCK();
 403
 404         return rc;
 405 }
 406
 407 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 408 {
 409         int rc = 0;
 410         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 411         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 412         uint16_t new_max_vfs;
 413         int i;
 414
 415         HWRM_PREP(req, FUNC_QCAPS);
 416
 417         req.fid = rte_cpu_to_le_16(0xffff);
 418
 419         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 420
 421         HWRM_CHECK_RESULT();
 422
 423         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 424         if (BNXT_PF(bp)) {
 425                 bp->pf.port_id = resp->port_id;
 426                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 427                 new_max_vfs = bp->pdev->max_vfs;
 428                 if (new_max_vfs != bp->pf.max_vfs) {
 429                         if (bp->pf.vf_info)
 430                                 rte_free(bp->pf.vf_info);
 431                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 432                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 433                         bp->pf.max_vfs = new_max_vfs;
 434                         for (i = 0; i < new_max_vfs; i++) {
 435                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 436                                 bp->pf.vf_info[i].vlan_table =
 437                                         rte_zmalloc("VF VLAN table",
 438                                                     getpagesize(),
 439                                                     getpagesize());
 440                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 441                                         RTE_LOG(ERR, PMD,
 442                                         "Fail to alloc VLAN table for VF %d\n",
 443                                         i);
 444                                 else
 445                                         rte_mem_lock_page(
 446                                                 bp->pf.vf_info[i].vlan_table);
 447                                 bp->pf.vf_info[i].vlan_as_table =
 448                                         rte_zmalloc("VF VLAN AS table",
 449                                                     getpagesize(),
 450                                                     getpagesize());
 451                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 452                                         RTE_LOG(ERR, PMD,
 453                                         "Alloc VLAN AS table for VF %d fail\n",
 454                                         i);
 455                                 else
 456                                         rte_mem_lock_page(
 457                                                bp->pf.vf_info[i].vlan_as_table);
 458                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 459                         }
 460                 }
 461         }
 462
 463         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 464         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 465         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 466         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 467         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 468         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 469         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 470         /* TODO: For now, do not support VMDq/RFS on VFs. */
 471         if (BNXT_PF(bp)) {
 472                 if (bp->pf.max_vfs)
 473                         bp->max_vnics = 1;
 474                 else
 475                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 476         } else {
 477                 bp->max_vnics = 1;
 478         }
 479         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 480         if (BNXT_PF(bp))
 481                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 482         HWRM_UNLOCK();
 483
 484         return rc;
 485 }
 486
 487 int bnxt_hwrm_func_reset(struct bnxt *bp)
 488 {
 489         int rc = 0;
 490         struct hwrm_func_reset_input req = {.req_type = 0 };
 491         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 492
 493         HWRM_PREP(req, FUNC_RESET);
 494
 495         req.enables = rte_cpu_to_le_32(0);
 496
 497         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 498
 499         HWRM_CHECK_RESULT();
 500         HWRM_UNLOCK();
 501
 502         return rc;
 503 }
 504
 505 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 506 {
 507         int rc;
 508         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 509         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 510
 511         if (bp->flags & BNXT_FLAG_REGISTERED)
 512                 return 0;
 513
 514         HWRM_PREP(req, FUNC_DRV_RGTR);
 515         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 516                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 517         req.ver_maj = RTE_VER_YEAR;
 518         req.ver_min = RTE_VER_MONTH;
 519         req.ver_upd = RTE_VER_MINOR;
 520
 521         if (BNXT_PF(bp)) {
 522                 req.enables |= rte_cpu_to_le_32(
 523                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 524                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 525                        RTE_MIN(sizeof(req.vf_req_fwd),
 526                                sizeof(bp->pf.vf_req_fwd)));
 527         }
 528
 529         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 530         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 531
 532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 533
 534         HWRM_CHECK_RESULT();
 535         HWRM_UNLOCK();
 536
 537         bp->flags |= BNXT_FLAG_REGISTERED;
 538
 539         return rc;
 540 }
 541
 542 int bnxt_hwrm_ver_get(struct bnxt *bp)
 543 {
 544         int rc = 0;
 545         struct hwrm_ver_get_input req = {.req_type = 0 };
 546         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 547         uint32_t my_version;
 548         uint32_t fw_version;
 549         uint16_t max_resp_len;
 550         char type[RTE_MEMZONE_NAMESIZE];
 551         uint32_t dev_caps_cfg;
 552
 553         bp->max_req_len = HWRM_MAX_REQ_LEN;
 554         HWRM_PREP(req, VER_GET);
 555
 556         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 557         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 558         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 561
 562         HWRM_CHECK_RESULT();
 563
 564         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 565                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 566                 resp->hwrm_intf_upd,
 567                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 568         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 569                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 570         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 571                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 572
 573         my_version = HWRM_VERSION_MAJOR << 16;
 574         my_version |= HWRM_VERSION_MINOR << 8;
 575         my_version |= HWRM_VERSION_UPDATE;
 576
 577         fw_version = resp->hwrm_intf_maj << 16;
 578         fw_version |= resp->hwrm_intf_min << 8;
 579         fw_version |= resp->hwrm_intf_upd;
 580
 581         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 582                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 583                 rc = -EINVAL;
 584                 goto error;
 585         }
 586
 587         if (my_version != fw_version) {
 588                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 589                 if (my_version < fw_version) {
 590                         RTE_LOG(INFO, PMD,
 591                                 "Firmware API version is newer than driver.\n");
 592                         RTE_LOG(INFO, PMD,
 593                                 "The driver may be missing features.\n");
 594                 } else {
 595                         RTE_LOG(INFO, PMD,
 596                                 "Firmware API version is older than driver.\n");
 597                         RTE_LOG(INFO, PMD,
 598                                 "Not all driver features may be functional.\n");
 599                 }
 600         }
 601
 602         if (bp->max_req_len > resp->max_req_win_len) {
 603                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 604                 rc = -EINVAL;
 605         }
 606         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 607         max_resp_len = resp->max_resp_len;
 608         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 609
 610         if (bp->max_resp_len != max_resp_len) {
 611                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 612                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 613                         bp->pdev->addr.devid, bp->pdev->addr.function);
 614
 615                 rte_free(bp->hwrm_cmd_resp_addr);
 616
 617                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 618                 if (bp->hwrm_cmd_resp_addr == NULL) {
 619                         rc = -ENOMEM;
 620                         goto error;
 621                 }
 622                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 623                 bp->hwrm_cmd_resp_dma_addr =
 624                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 625                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 626                         RTE_LOG(ERR, PMD,
 627                         "Unable to map response buffer to physical memory.\n");
 628                         rc = -ENOMEM;
 629                         goto error;
 630                 }
 631                 bp->max_resp_len = max_resp_len;
 632         }
 633
 634         if ((dev_caps_cfg &
 635                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 636             (dev_caps_cfg &
 637              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 638                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 639
 640                 rte_free(bp->hwrm_short_cmd_req_addr);
 641
 642                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 643                                                         bp->max_req_len, 0);
 644                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 645                         rc = -ENOMEM;
 646                         goto error;
 647                 }
 648                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 649                 bp->hwrm_short_cmd_req_dma_addr =
 650                         rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
 651                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 652                         rte_free(bp->hwrm_short_cmd_req_addr);
 653                         RTE_LOG(ERR, PMD,
 654                                 "Unable to map buffer to physical memory.\n");
 655                         rc = -ENOMEM;
 656                         goto error;
 657                 }
 658
 659                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 660         }
 661
 662 error:
 663         HWRM_UNLOCK();
 664         return rc;
 665 }
 666
 667 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 668 {
 669         int rc;
 670         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 671         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 672
 673         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 674                 return 0;
 675
 676         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 677         req.flags = flags;
 678
 679         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 680
 681         HWRM_CHECK_RESULT();
 682         HWRM_UNLOCK();
 683
 684         bp->flags &= ~BNXT_FLAG_REGISTERED;
 685
 686         return rc;
 687 }
 688
 689 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 690 {
 691         int rc = 0;
 692         struct hwrm_port_phy_cfg_input req = {0};
 693         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 694         uint32_t enables = 0;
 695         uint32_t link_speed_mask =
 696                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 697
 698         HWRM_PREP(req, PORT_PHY_CFG);
 699
 700         if (conf->link_up) {
 701                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 702                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 703                 /*
 704                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 705                  * any auto mode, even "none".
 706                  */
 707                 if (!conf->link_speed) {
 708                         req.auto_mode = conf->auto_mode;
 709                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 710                         if (conf->auto_mode ==
 711                             HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
 712                                 req.auto_link_speed_mask =
 713                                         conf->auto_link_speed_mask;
 714                                 enables |= link_speed_mask;
 715                         }
 716                         if (bp->link_info.auto_link_speed) {
 717                                 req.auto_link_speed =
 718                                         bp->link_info.auto_link_speed;
 719                                 enables |=
 720                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 721                         }
 722                 }
 723                 req.auto_duplex = conf->duplex;
 724                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 725                 req.auto_pause = conf->auto_pause;
 726                 req.force_pause = conf->force_pause;
 727                 /* Set force_pause if there is no auto or if there is a force */
 728                 if (req.auto_pause && !req.force_pause)
 729                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 730                 else
 731                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 732
 733                 req.enables = rte_cpu_to_le_32(enables);
 734         } else {
 735                 req.flags =
 736                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 737                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 738         }
 739
 740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 741
 742         HWRM_CHECK_RESULT();
 743         HWRM_UNLOCK();
 744
 745         return rc;
 746 }
 747
 748 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 749                                    struct bnxt_link_info *link_info)
 750 {
 751         int rc = 0;
 752         struct hwrm_port_phy_qcfg_input req = {0};
 753         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 754
 755         HWRM_PREP(req, PORT_PHY_QCFG);
 756
 757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 758
 759         HWRM_CHECK_RESULT();
 760
 761         link_info->phy_link_status = resp->link;
 762         link_info->link_up =
 763                 (link_info->phy_link_status ==
 764                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 765         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 766         link_info->duplex = resp->duplex;
 767         link_info->pause = resp->pause;
 768         link_info->auto_pause = resp->auto_pause;
 769         link_info->force_pause = resp->force_pause;
 770         link_info->auto_mode = resp->auto_mode;
 771
 772         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 773         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 774         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 775         link_info->phy_ver[0] = resp->phy_maj;
 776         link_info->phy_ver[1] = resp->phy_min;
 777         link_info->phy_ver[2] = resp->phy_bld;
 778
 779         HWRM_UNLOCK();
 780
 781         return rc;
 782 }
 783
 784 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 785 {
 786         int rc = 0;
 787         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 788         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 789
 790         HWRM_PREP(req, QUEUE_QPORTCFG);
 791
 792         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 793
 794         HWRM_CHECK_RESULT();
 795
 796 #define GET_QUEUE_INFO(x) \
 797         bp->cos_queue[x].id = resp->queue_id##x; \
 798         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 799
 800         GET_QUEUE_INFO(0);
 801         GET_QUEUE_INFO(1);
 802         GET_QUEUE_INFO(2);
 803         GET_QUEUE_INFO(3);
 804         GET_QUEUE_INFO(4);
 805         GET_QUEUE_INFO(5);
 806         GET_QUEUE_INFO(6);
 807         GET_QUEUE_INFO(7);
 808
 809         HWRM_UNLOCK();
 810
 811         return rc;
 812 }
 813
 814 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 815                          struct bnxt_ring *ring,
 816                          uint32_t ring_type, uint32_t map_index,
 817                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 818 {
 819         int rc = 0;
 820         uint32_t enables = 0;
 821         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 822         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 823
 824         HWRM_PREP(req, RING_ALLOC);
 825
 826         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 827         req.fbo = rte_cpu_to_le_32(0);
 828         /* Association of ring index with doorbell index */
 829         req.logical_id = rte_cpu_to_le_16(map_index);
 830         req.length = rte_cpu_to_le_32(ring->ring_size);
 831
 832         switch (ring_type) {
 833         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 834                 req.queue_id = bp->cos_queue[0].id;
 835                 /* FALLTHROUGH */
 836         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 837                 req.ring_type = ring_type;
 838                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 839                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 840                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 841                         enables |=
 842                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 843                 break;
 844         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 845                 req.ring_type = ring_type;
 846                 /*
 847                  * TODO: Some HWRM versions crash with
 848                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 849                  */
 850                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 851                 break;
 852         default:
 853                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 854                         ring_type);
 855                 HWRM_UNLOCK();
 856                 return -1;
 857         }
 858         req.enables = rte_cpu_to_le_32(enables);
 859
 860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 861
 862         if (rc || resp->error_code) {
 863                 if (rc == 0 && resp->error_code)
 864                         rc = rte_le_to_cpu_16(resp->error_code);
 865                 switch (ring_type) {
 866                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 867                         RTE_LOG(ERR, PMD,
 868                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 869                         HWRM_UNLOCK();
 870                         return rc;
 871                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 872                         RTE_LOG(ERR, PMD,
 873                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 874                         HWRM_UNLOCK();
 875                         return rc;
 876                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 877                         RTE_LOG(ERR, PMD,
 878                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 879                         HWRM_UNLOCK();
 880                         return rc;
 881                 default:
 882                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 883                         HWRM_UNLOCK();
 884                         return rc;
 885                 }
 886         }
 887
 888         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 889         HWRM_UNLOCK();
 890         return rc;
 891 }
 892
 893 int bnxt_hwrm_ring_free(struct bnxt *bp,
 894                         struct bnxt_ring *ring, uint32_t ring_type)
 895 {
 896         int rc;
 897         struct hwrm_ring_free_input req = {.req_type = 0 };
 898         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 899
 900         HWRM_PREP(req, RING_FREE);
 901
 902         req.ring_type = ring_type;
 903         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 904
 905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 906
 907         if (rc || resp->error_code) {
 908                 if (rc == 0 && resp->error_code)
 909                         rc = rte_le_to_cpu_16(resp->error_code);
 910                 HWRM_UNLOCK();
 911
 912                 switch (ring_type) {
 913                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 914                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 915                                 rc);
 916                         return rc;
 917                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 918                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 919                                 rc);
 920                         return rc;
 921                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 922                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 923                                 rc);
 924                         return rc;
 925                 default:
 926                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 927                         return rc;
 928                 }
 929         }
 930         HWRM_UNLOCK();
 931         return 0;
 932 }
 933
 934 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 935 {
 936         int rc = 0;
 937         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 938         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 939
 940         HWRM_PREP(req, RING_GRP_ALLOC);
 941
 942         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 943         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 944         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 945         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 946
 947         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 948
 949         HWRM_CHECK_RESULT();
 950
 951         bp->grp_info[idx].fw_grp_id =
 952             rte_le_to_cpu_16(resp->ring_group_id);
 953
 954         HWRM_UNLOCK();
 955
 956         return rc;
 957 }
 958
 959 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 960 {
 961         int rc;
 962         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 963         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 964
 965         HWRM_PREP(req, RING_GRP_FREE);
 966
 967         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 968
 969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 970
 971         HWRM_CHECK_RESULT();
 972         HWRM_UNLOCK();
 973
 974         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 975         return rc;
 976 }
 977
 978 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 979 {
 980         int rc = 0;
 981         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 982         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 983
 984         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 985                 return rc;
 986
 987         HWRM_PREP(req, STAT_CTX_CLR_STATS);
 988
 989         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 990
 991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 992
 993         HWRM_CHECK_RESULT();
 994         HWRM_UNLOCK();
 995
 996         return rc;
 997 }
 998
 999 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1000                                 unsigned int idx __rte_unused)
1001 {
1002         int rc;
1003         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1004         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1005
1006         HWRM_PREP(req, STAT_CTX_ALLOC);
1007
1008         req.update_period_ms = rte_cpu_to_le_32(0);
1009
1010         req.stats_dma_addr =
1011             rte_cpu_to_le_64(cpr->hw_stats_map);
1012
1013         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1014
1015         HWRM_CHECK_RESULT();
1016
1017         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1018
1019         HWRM_UNLOCK();
1020         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
1021
1022         return rc;
1023 }
1024
1025 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1026                                 unsigned int idx __rte_unused)
1027 {
1028         int rc;
1029         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1030         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1031
1032         HWRM_PREP(req, STAT_CTX_FREE);
1033
1034         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1035
1036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1037
1038         HWRM_CHECK_RESULT();
1039         HWRM_UNLOCK();
1040
1041         return rc;
1042 }
1043
1044 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1045 {
1046         int rc = 0, i, j;
1047         struct hwrm_vnic_alloc_input req = { 0 };
1048         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1049
1050         /* map ring groups to this vnic */
1051         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1052                 vnic->start_grp_id, vnic->end_grp_id);
1053         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1054                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1055         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1056         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1057         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1058         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1059         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1060                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1061         HWRM_PREP(req, VNIC_ALLOC);
1062
1063         if (vnic->func_default)
1064                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1066
1067         HWRM_CHECK_RESULT();
1068
1069         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1070         HWRM_UNLOCK();
1071         RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1072         return rc;
1073 }
1074
1075 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1076                                         struct bnxt_vnic_info *vnic,
1077                                         struct bnxt_plcmodes_cfg *pmode)
1078 {
1079         int rc = 0;
1080         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1081         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1082
1083         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1084
1085         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1086
1087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1088
1089         HWRM_CHECK_RESULT();
1090
1091         pmode->flags = rte_le_to_cpu_32(resp->flags);
1092         /* dflt_vnic bit doesn't exist in the _cfg command */
1093         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1094         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1095         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1096         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1097
1098         HWRM_UNLOCK();
1099
1100         return rc;
1101 }
1102
1103 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1104                                        struct bnxt_vnic_info *vnic,
1105                                        struct bnxt_plcmodes_cfg *pmode)
1106 {
1107         int rc = 0;
1108         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1109         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1110
1111         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1112
1113         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1114         req.flags = rte_cpu_to_le_32(pmode->flags);
1115         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1116         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1117         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1118         req.enables = rte_cpu_to_le_32(
1119             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1120             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1121             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1122         );
1123
1124         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1125
1126         HWRM_CHECK_RESULT();
1127         HWRM_UNLOCK();
1128
1129         return rc;
1130 }
1131
1132 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1133 {
1134         int rc = 0;
1135         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1136         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1137         uint32_t ctx_enable_flag = 0;
1138         struct bnxt_plcmodes_cfg pmodes;
1139
1140         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1141                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1142                 return rc;
1143         }
1144
1145         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1146         if (rc)
1147                 return rc;
1148
1149         HWRM_PREP(req, VNIC_CFG);
1150
1151         /* Only RSS support for now TBD: COS & LB */
1152         req.enables =
1153             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1154         if (vnic->lb_rule != 0xffff)
1155                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1156         if (vnic->cos_rule != 0xffff)
1157                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1158         if (vnic->rss_rule != 0xffff) {
1159                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1160                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1161         }
1162         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1163         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1164         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1165         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1166         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1167         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1168         req.mru = rte_cpu_to_le_16(vnic->mru);
1169         if (vnic->func_default)
1170                 req.flags |=
1171                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1172         if (vnic->vlan_strip)
1173                 req.flags |=
1174                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1175         if (vnic->bd_stall)
1176                 req.flags |=
1177                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1178         if (vnic->roce_dual)
1179                 req.flags |= rte_cpu_to_le_32(
1180                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1181         if (vnic->roce_only)
1182                 req.flags |= rte_cpu_to_le_32(
1183                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1184         if (vnic->rss_dflt_cr)
1185                 req.flags |= rte_cpu_to_le_32(
1186                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1187
1188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1189
1190         HWRM_CHECK_RESULT();
1191         HWRM_UNLOCK();
1192
1193         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1194
1195         return rc;
1196 }
1197
1198 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1199                 int16_t fw_vf_id)
1200 {
1201         int rc = 0;
1202         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1203         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1204
1205         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1206                 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1207                 return rc;
1208         }
1209         HWRM_PREP(req, VNIC_QCFG);
1210
1211         req.enables =
1212                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1213         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1214         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1215
1216         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1217
1218         HWRM_CHECK_RESULT();
1219
1220         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1221         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1222         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1223         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1224         vnic->mru = rte_le_to_cpu_16(resp->mru);
1225         vnic->func_default = rte_le_to_cpu_32(
1226                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1227         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1228                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1229         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1230                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1231         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1232                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1233         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1234                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1235         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1236                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1237
1238         HWRM_UNLOCK();
1239
1240         return rc;
1241 }
1242
1243 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1244 {
1245         int rc = 0;
1246         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1247         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1248                                                 bp->hwrm_cmd_resp_addr;
1249
1250         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1251
1252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1253
1254         HWRM_CHECK_RESULT();
1255
1256         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1257         HWRM_UNLOCK();
1258         RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1259
1260         return rc;
1261 }
1262
1263 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1264 {
1265         int rc = 0;
1266         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1267         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1268                                                 bp->hwrm_cmd_resp_addr;
1269
1270         if (vnic->rss_rule == 0xffff) {
1271                 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1272                 return rc;
1273         }
1274         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1275
1276         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1277
1278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1279
1280         HWRM_CHECK_RESULT();
1281         HWRM_UNLOCK();
1282
1283         vnic->rss_rule = INVALID_HW_RING_ID;
1284
1285         return rc;
1286 }
1287
1288 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1289 {
1290         int rc = 0;
1291         struct hwrm_vnic_free_input req = {.req_type = 0 };
1292         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1293
1294         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1295                 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1296                 return rc;
1297         }
1298
1299         HWRM_PREP(req, VNIC_FREE);
1300
1301         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1302
1303         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1304
1305         HWRM_CHECK_RESULT();
1306         HWRM_UNLOCK();
1307
1308         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1309         return rc;
1310 }
1311
1312 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1313                            struct bnxt_vnic_info *vnic)
1314 {
1315         int rc = 0;
1316         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1317         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1318
1319         HWRM_PREP(req, VNIC_RSS_CFG);
1320
1321         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1322
1323         req.ring_grp_tbl_addr =
1324             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1325         req.hash_key_tbl_addr =
1326             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1327         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1328
1329         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1330
1331         HWRM_CHECK_RESULT();
1332         HWRM_UNLOCK();
1333
1334         return rc;
1335 }
1336
1337 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1338                         struct bnxt_vnic_info *vnic)
1339 {
1340         int rc = 0;
1341         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1342         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1343         uint16_t size;
1344
1345         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1346
1347         req.flags = rte_cpu_to_le_32(
1348                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1349
1350         req.enables = rte_cpu_to_le_32(
1351                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1352
1353         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1354         size -= RTE_PKTMBUF_HEADROOM;
1355
1356         req.jumbo_thresh = rte_cpu_to_le_16(size);
1357         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1358
1359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1360
1361         HWRM_CHECK_RESULT();
1362         HWRM_UNLOCK();
1363
1364         return rc;
1365 }
1366
1367 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1368                         struct bnxt_vnic_info *vnic, bool enable)
1369 {
1370         int rc = 0;
1371         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1372         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1373
1374         HWRM_PREP(req, VNIC_TPA_CFG);
1375
1376         if (enable) {
1377                 req.enables = rte_cpu_to_le_32(
1378                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1379                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1380                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1381                 req.flags = rte_cpu_to_le_32(
1382                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1383                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1384                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1385                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1386                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1387                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1388                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1389                 req.max_agg_segs = rte_cpu_to_le_16(5);
1390                 req.max_aggs =
1391                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1392                 req.min_agg_len = rte_cpu_to_le_32(512);
1393         }
1394
1395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1396
1397         HWRM_CHECK_RESULT();
1398         HWRM_UNLOCK();
1399
1400         return rc;
1401 }
1402
1403 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1404 {
1405         struct hwrm_func_cfg_input req = {0};
1406         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1407         int rc;
1408
1409         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1410         req.enables = rte_cpu_to_le_32(
1411                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1412         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1413         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1414
1415         HWRM_PREP(req, FUNC_CFG);
1416
1417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1418         HWRM_CHECK_RESULT();
1419         HWRM_UNLOCK();
1420
1421         bp->pf.vf_info[vf].random_mac = false;
1422
1423         return rc;
1424 }
1425
1426 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1427                                   uint64_t *dropped)
1428 {
1429         int rc = 0;
1430         struct hwrm_func_qstats_input req = {.req_type = 0};
1431         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1432
1433         HWRM_PREP(req, FUNC_QSTATS);
1434
1435         req.fid = rte_cpu_to_le_16(fid);
1436
1437         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1438
1439         HWRM_CHECK_RESULT();
1440
1441         if (dropped)
1442                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1443
1444         HWRM_UNLOCK();
1445
1446         return rc;
1447 }
1448
1449 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1450                           struct rte_eth_stats *stats)
1451 {
1452         int rc = 0;
1453         struct hwrm_func_qstats_input req = {.req_type = 0};
1454         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1455
1456         HWRM_PREP(req, FUNC_QSTATS);
1457
1458         req.fid = rte_cpu_to_le_16(fid);
1459
1460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1461
1462         HWRM_CHECK_RESULT();
1463
1464         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1465         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1466         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1467         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1468         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1469         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1470
1471         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1472         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1473         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1474         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1475         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1476         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1477
1478         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1479         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1480
1481         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1482
1483         HWRM_UNLOCK();
1484
1485         return rc;
1486 }
1487
1488 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1489 {
1490         int rc = 0;
1491         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1492         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1493
1494         HWRM_PREP(req, FUNC_CLR_STATS);
1495
1496         req.fid = rte_cpu_to_le_16(fid);
1497
1498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1499
1500         HWRM_CHECK_RESULT();
1501         HWRM_UNLOCK();
1502
1503         return rc;
1504 }
1505
1506 /*
1507  * HWRM utility functions
1508  */
1509
1510 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1511 {
1512         unsigned int i;
1513         int rc = 0;
1514
1515         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1516                 struct bnxt_tx_queue *txq;
1517                 struct bnxt_rx_queue *rxq;
1518                 struct bnxt_cp_ring_info *cpr;
1519
1520                 if (i >= bp->rx_cp_nr_rings) {
1521                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1522                         cpr = txq->cp_ring;
1523                 } else {
1524                         rxq = bp->rx_queues[i];
1525                         cpr = rxq->cp_ring;
1526                 }
1527
1528                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1529                 if (rc)
1530                         return rc;
1531         }
1532         return 0;
1533 }
1534
1535 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1536 {
1537         int rc;
1538         unsigned int i;
1539         struct bnxt_cp_ring_info *cpr;
1540
1541         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1542
1543                 if (i >= bp->rx_cp_nr_rings)
1544                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1545                 else
1546                         cpr = bp->rx_queues[i]->cp_ring;
1547                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1548                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1549                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1550                         /*
1551                          * TODO. Need a better way to reset grp_info.stats_ctx
1552                          * for Rx rings only. stats_ctx is not saved for Tx
1553                          * in grp_info.
1554                          */
1555                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1556                         if (rc)
1557                                 return rc;
1558                 }
1559         }
1560         return 0;
1561 }
1562
1563 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1564 {
1565         unsigned int i;
1566         int rc = 0;
1567
1568         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1569                 struct bnxt_tx_queue *txq;
1570                 struct bnxt_rx_queue *rxq;
1571                 struct bnxt_cp_ring_info *cpr;
1572
1573                 if (i >= bp->rx_cp_nr_rings) {
1574                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1575                         cpr = txq->cp_ring;
1576                 } else {
1577                         rxq = bp->rx_queues[i];
1578                         cpr = rxq->cp_ring;
1579                 }
1580
1581                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1582
1583                 if (rc)
1584                         return rc;
1585         }
1586         return rc;
1587 }
1588
1589 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1590 {
1591         uint16_t idx;
1592         uint32_t rc = 0;
1593
1594         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1595
1596                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1597                         continue;
1598
1599                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1600
1601                 if (rc)
1602                         return rc;
1603         }
1604         return rc;
1605 }
1606
1607 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1608                                 unsigned int idx __rte_unused)
1609 {
1610         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1611
1612         bnxt_hwrm_ring_free(bp, cp_ring,
1613                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1614         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1615         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1616         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1617                         sizeof(*cpr->cp_desc_ring));
1618         cpr->cp_raw_cons = 0;
1619 }
1620
1621 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1622 {
1623         unsigned int i;
1624         int rc = 0;
1625
1626         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1627                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1628                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1629                 struct bnxt_ring *ring = txr->tx_ring_struct;
1630                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1631                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1632
1633                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1634                         bnxt_hwrm_ring_free(bp, ring,
1635                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1636                         ring->fw_ring_id = INVALID_HW_RING_ID;
1637                         memset(txr->tx_desc_ring, 0,
1638                                         txr->tx_ring_struct->ring_size *
1639                                         sizeof(*txr->tx_desc_ring));
1640                         memset(txr->tx_buf_ring, 0,
1641                                         txr->tx_ring_struct->ring_size *
1642                                         sizeof(*txr->tx_buf_ring));
1643                         txr->tx_prod = 0;
1644                         txr->tx_cons = 0;
1645                 }
1646                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1647                         bnxt_free_cp_ring(bp, cpr, idx);
1648                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1649                 }
1650         }
1651
1652         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1653                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1654                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1655                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1656                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1657                 unsigned int idx = i + 1;
1658
1659                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1660                         bnxt_hwrm_ring_free(bp, ring,
1661                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1662                         ring->fw_ring_id = INVALID_HW_RING_ID;
1663                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1664                         memset(rxr->rx_desc_ring, 0,
1665                                         rxr->rx_ring_struct->ring_size *
1666                                         sizeof(*rxr->rx_desc_ring));
1667                         memset(rxr->rx_buf_ring, 0,
1668                                         rxr->rx_ring_struct->ring_size *
1669                                         sizeof(*rxr->rx_buf_ring));
1670                         rxr->rx_prod = 0;
1671                         memset(rxr->ag_buf_ring, 0,
1672                                         rxr->ag_ring_struct->ring_size *
1673                                         sizeof(*rxr->ag_buf_ring));
1674                         rxr->ag_prod = 0;
1675                 }
1676                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1677                         bnxt_free_cp_ring(bp, cpr, idx);
1678                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1679                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1680                 }
1681         }
1682
1683         /* Default completion ring */
1684         {
1685                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1686
1687                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1688                         bnxt_free_cp_ring(bp, cpr, 0);
1689                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1690                 }
1691         }
1692
1693         return rc;
1694 }
1695
1696 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1697 {
1698         uint16_t i;
1699         uint32_t rc = 0;
1700
1701         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1702                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1703                 if (rc)
1704                         return rc;
1705         }
1706         return rc;
1707 }
1708
1709 void bnxt_free_hwrm_resources(struct bnxt *bp)
1710 {
1711         /* Release memzone */
1712         rte_free(bp->hwrm_cmd_resp_addr);
1713         rte_free(bp->hwrm_short_cmd_req_addr);
1714         bp->hwrm_cmd_resp_addr = NULL;
1715         bp->hwrm_short_cmd_req_addr = NULL;
1716         bp->hwrm_cmd_resp_dma_addr = 0;
1717         bp->hwrm_short_cmd_req_dma_addr = 0;
1718 }
1719
1720 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1721 {
1722         struct rte_pci_device *pdev = bp->pdev;
1723         char type[RTE_MEMZONE_NAMESIZE];
1724
1725         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1726                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1727         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1728         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1729         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1730         if (bp->hwrm_cmd_resp_addr == NULL)
1731                 return -ENOMEM;
1732         bp->hwrm_cmd_resp_dma_addr =
1733                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1734         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1735                 RTE_LOG(ERR, PMD,
1736                         "unable to map response address to physical memory\n");
1737                 return -ENOMEM;
1738         }
1739         rte_spinlock_init(&bp->hwrm_lock);
1740
1741         return 0;
1742 }
1743
1744 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1745 {
1746         struct bnxt_filter_info *filter;
1747         int rc = 0;
1748
1749         STAILQ_FOREACH(filter, &vnic->filter, next) {
1750                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1751                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1752                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1753                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1754                 else
1755                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1756                 //if (rc)
1757                         //break;
1758         }
1759         return rc;
1760 }
1761
1762 static int
1763 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1764 {
1765         struct bnxt_filter_info *filter;
1766         struct rte_flow *flow;
1767         int rc = 0;
1768
1769         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1770                 filter = flow->filter;
1771                 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1772                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1773                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1774                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1775                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1776                 else
1777                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1778
1779                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1780                 rte_free(flow);
1781                 //if (rc)
1782                         //break;
1783         }
1784         return rc;
1785 }
1786
1787 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1788 {
1789         struct bnxt_filter_info *filter;
1790         int rc = 0;
1791
1792         STAILQ_FOREACH(filter, &vnic->filter, next) {
1793                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1794                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1795                                                      filter);
1796                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1797                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1798                                                          filter);
1799                 else
1800                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1801                                                      filter);
1802                 if (rc)
1803                         break;
1804         }
1805         return rc;
1806 }
1807
1808 void bnxt_free_tunnel_ports(struct bnxt *bp)
1809 {
1810         if (bp->vxlan_port_cnt)
1811                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1812                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1813         bp->vxlan_port = 0;
1814         if (bp->geneve_port_cnt)
1815                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1816                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1817         bp->geneve_port = 0;
1818 }
1819
1820 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1821 {
1822         int i;
1823
1824         if (bp->vnic_info == NULL)
1825                 return;
1826
1827         /*
1828          * Cleanup VNICs in reverse order, to make sure the L2 filter
1829          * from vnic0 is last to be cleaned up.
1830          */
1831         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1832                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1833
1834                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1835
1836                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1837
1838                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1839
1840                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1841
1842                 bnxt_hwrm_vnic_free(bp, vnic);
1843         }
1844         /* Ring resources */
1845         bnxt_free_all_hwrm_rings(bp);
1846         bnxt_free_all_hwrm_ring_grps(bp);
1847         bnxt_free_all_hwrm_stat_ctxs(bp);
1848         bnxt_free_tunnel_ports(bp);
1849 }
1850
1851 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1852 {
1853         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1854
1855         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1856                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1857
1858         switch (conf_link_speed) {
1859         case ETH_LINK_SPEED_10M_HD:
1860         case ETH_LINK_SPEED_100M_HD:
1861                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1862         }
1863         return hw_link_duplex;
1864 }
1865
1866 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1867 {
1868         uint16_t eth_link_speed = 0;
1869
1870         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1871                 return ETH_LINK_SPEED_AUTONEG;
1872
1873         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1874         case ETH_LINK_SPEED_100M:
1875         case ETH_LINK_SPEED_100M_HD:
1876                 eth_link_speed =
1877                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1878                 break;
1879         case ETH_LINK_SPEED_1G:
1880                 eth_link_speed =
1881                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1882                 break;
1883         case ETH_LINK_SPEED_2_5G:
1884                 eth_link_speed =
1885                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1886                 break;
1887         case ETH_LINK_SPEED_10G:
1888                 eth_link_speed =
1889                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1890                 break;
1891         case ETH_LINK_SPEED_20G:
1892                 eth_link_speed =
1893                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1894                 break;
1895         case ETH_LINK_SPEED_25G:
1896                 eth_link_speed =
1897                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1898                 break;
1899         case ETH_LINK_SPEED_40G:
1900                 eth_link_speed =
1901                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1902                 break;
1903         case ETH_LINK_SPEED_50G:
1904                 eth_link_speed =
1905                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1906                 break;
1907         default:
1908                 RTE_LOG(ERR, PMD,
1909                         "Unsupported link speed %d; default to AUTO\n",
1910                         conf_link_speed);
1911                 break;
1912         }
1913         return eth_link_speed;
1914 }
1915
1916 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1917                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1918                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1919                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1920
1921 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1922 {
1923         uint32_t one_speed;
1924
1925         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1926                 return 0;
1927
1928         if (link_speed & ETH_LINK_SPEED_FIXED) {
1929                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1930
1931                 if (one_speed & (one_speed - 1)) {
1932                         RTE_LOG(ERR, PMD,
1933                                 "Invalid advertised speeds (%u) for port %u\n",
1934                                 link_speed, port_id);
1935                         return -EINVAL;
1936                 }
1937                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1938                         RTE_LOG(ERR, PMD,
1939                                 "Unsupported advertised speed (%u) for port %u\n",
1940                                 link_speed, port_id);
1941                         return -EINVAL;
1942                 }
1943         } else {
1944                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1945                         RTE_LOG(ERR, PMD,
1946                                 "Unsupported advertised speeds (%u) for port %u\n",
1947                                 link_speed, port_id);
1948                         return -EINVAL;
1949                 }
1950         }
1951         return 0;
1952 }
1953
1954 static uint16_t
1955 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1956 {
1957         uint16_t ret = 0;
1958
1959         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1960                 if (bp->link_info.support_speeds)
1961                         return bp->link_info.support_speeds;
1962                 link_speed = BNXT_SUPPORTED_SPEEDS;
1963         }
1964
1965         if (link_speed & ETH_LINK_SPEED_100M)
1966                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1967         if (link_speed & ETH_LINK_SPEED_100M_HD)
1968                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1969         if (link_speed & ETH_LINK_SPEED_1G)
1970                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1971         if (link_speed & ETH_LINK_SPEED_2_5G)
1972                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1973         if (link_speed & ETH_LINK_SPEED_10G)
1974                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1975         if (link_speed & ETH_LINK_SPEED_20G)
1976                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1977         if (link_speed & ETH_LINK_SPEED_25G)
1978                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1979         if (link_speed & ETH_LINK_SPEED_40G)
1980                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1981         if (link_speed & ETH_LINK_SPEED_50G)
1982                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1983         return ret;
1984 }
1985
1986 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1987 {
1988         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1989
1990         switch (hw_link_speed) {
1991         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1992                 eth_link_speed = ETH_SPEED_NUM_100M;
1993                 break;
1994         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1995                 eth_link_speed = ETH_SPEED_NUM_1G;
1996                 break;
1997         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1998                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1999                 break;
2000         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2001                 eth_link_speed = ETH_SPEED_NUM_10G;
2002                 break;
2003         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2004                 eth_link_speed = ETH_SPEED_NUM_20G;
2005                 break;
2006         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2007                 eth_link_speed = ETH_SPEED_NUM_25G;
2008                 break;
2009         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2010                 eth_link_speed = ETH_SPEED_NUM_40G;
2011                 break;
2012         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2013                 eth_link_speed = ETH_SPEED_NUM_50G;
2014                 break;
2015         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2016         default:
2017                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2018                         hw_link_speed);
2019                 break;
2020         }
2021         return eth_link_speed;
2022 }
2023
2024 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2025 {
2026         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2027
2028         switch (hw_link_duplex) {
2029         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2030         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2031                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2032                 break;
2033         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2034                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2035                 break;
2036         default:
2037                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2038                         hw_link_duplex);
2039                 break;
2040         }
2041         return eth_link_duplex;
2042 }
2043
2044 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2045 {
2046         int rc = 0;
2047         struct bnxt_link_info *link_info = &bp->link_info;
2048
2049         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2050         if (rc) {
2051                 RTE_LOG(ERR, PMD,
2052                         "Get link config failed with rc %d\n", rc);
2053                 goto exit;
2054         }
2055         if (link_info->link_speed)
2056                 link->link_speed =
2057                         bnxt_parse_hw_link_speed(link_info->link_speed);
2058         else
2059                 link->link_speed = ETH_SPEED_NUM_NONE;
2060         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2061         link->link_status = link_info->link_up;
2062         link->link_autoneg = link_info->auto_mode ==
2063                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2064                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2065 exit:
2066         return rc;
2067 }
2068
2069 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2070 {
2071         int rc = 0;
2072         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2073         struct bnxt_link_info link_req;
2074         uint16_t speed;
2075
2076         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2077                 return 0;
2078
2079         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2080                         bp->eth_dev->data->port_id);
2081         if (rc)
2082                 goto error;
2083
2084         memset(&link_req, 0, sizeof(link_req));
2085         link_req.link_up = link_up;
2086         if (!link_up)
2087                 goto port_phy_cfg;
2088
2089         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2090         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2091         if (speed == 0) {
2092                 link_req.phy_flags |=
2093                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2094                 link_req.auto_mode =
2095                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
2096                 link_req.auto_link_speed_mask =
2097                         bnxt_parse_eth_link_speed_mask(bp,
2098                                                        dev_conf->link_speeds);
2099         } else {
2100                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2101                 link_req.link_speed = speed;
2102                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
2103         }
2104         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2105         link_req.auto_pause = bp->link_info.auto_pause;
2106         link_req.force_pause = bp->link_info.force_pause;
2107
2108 port_phy_cfg:
2109         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2110         if (rc) {
2111                 RTE_LOG(ERR, PMD,
2112                         "Set link config failed with rc %d\n", rc);
2113         }
2114
2115 error:
2116         return rc;
2117 }
2118
2119 /* JIRA 22088 */
2120 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2121 {
2122         struct hwrm_func_qcfg_input req = {0};
2123         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2124         int rc = 0;
2125
2126         HWRM_PREP(req, FUNC_QCFG);
2127         req.fid = rte_cpu_to_le_16(0xffff);
2128
2129         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2130
2131         HWRM_CHECK_RESULT();
2132
2133         /* Hard Coded.. 0xfff VLAN ID mask */
2134         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2135
2136         switch (resp->port_partition_type) {
2137         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2138         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2139         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2140                 bp->port_partition_type = resp->port_partition_type;
2141                 break;
2142         default:
2143                 bp->port_partition_type = 0;
2144                 break;
2145         }
2146
2147         HWRM_UNLOCK();
2148
2149         return rc;
2150 }
2151
2152 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2153                                    struct hwrm_func_qcaps_output *qcaps)
2154 {
2155         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2156         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2157                sizeof(qcaps->mac_address));
2158         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2159         qcaps->max_rx_rings = fcfg->num_rx_rings;
2160         qcaps->max_tx_rings = fcfg->num_tx_rings;
2161         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2162         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2163         qcaps->max_vfs = 0;
2164         qcaps->first_vf_id = 0;
2165         qcaps->max_vnics = fcfg->num_vnics;
2166         qcaps->max_decap_records = 0;
2167         qcaps->max_encap_records = 0;
2168         qcaps->max_tx_wm_flows = 0;
2169         qcaps->max_tx_em_flows = 0;
2170         qcaps->max_rx_wm_flows = 0;
2171         qcaps->max_rx_em_flows = 0;
2172         qcaps->max_flow_id = 0;
2173         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2174         qcaps->max_sp_tx_rings = 0;
2175         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2176 }
2177
2178 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2179 {
2180         struct hwrm_func_cfg_input req = {0};
2181         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2182         int rc;
2183
2184         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2185                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2186                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2187                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2188                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2189                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2190                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2191                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2192                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2193                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2194         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2195         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2196         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2197                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2198         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2199         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2200         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2201         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2202         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2203         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2204         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2205         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2206         req.fid = rte_cpu_to_le_16(0xffff);
2207
2208         HWRM_PREP(req, FUNC_CFG);
2209
2210         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2211
2212         HWRM_CHECK_RESULT();
2213         HWRM_UNLOCK();
2214
2215         return rc;
2216 }
2217
2218 static void populate_vf_func_cfg_req(struct bnxt *bp,
2219                                      struct hwrm_func_cfg_input *req,
2220                                      int num_vfs)
2221 {
2222         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2223                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2224                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2225                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2226                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2227                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2228                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2229                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2230                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2231                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2232
2233         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2234                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2235         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2236                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2237         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2238                                                 (num_vfs + 1));
2239         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2240         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2241                                                (num_vfs + 1));
2242         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2243         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2244         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2245         /* TODO: For now, do not support VMDq/RFS on VFs. */
2246         req->num_vnics = rte_cpu_to_le_16(1);
2247         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2248                                                  (num_vfs + 1));
2249 }
2250
2251 static void add_random_mac_if_needed(struct bnxt *bp,
2252                                      struct hwrm_func_cfg_input *cfg_req,
2253                                      int vf)
2254 {
2255         struct ether_addr mac;
2256
2257         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2258                 return;
2259
2260         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2261                 cfg_req->enables |=
2262                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2263                 eth_random_addr(cfg_req->dflt_mac_addr);
2264                 bp->pf.vf_info[vf].random_mac = true;
2265         } else {
2266                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2267         }
2268 }
2269
2270 static void reserve_resources_from_vf(struct bnxt *bp,
2271                                       struct hwrm_func_cfg_input *cfg_req,
2272                                       int vf)
2273 {
2274         struct hwrm_func_qcaps_input req = {0};
2275         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2276         int rc;
2277
2278         /* Get the actual allocated values now */
2279         HWRM_PREP(req, FUNC_QCAPS);
2280         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2282
2283         if (rc) {
2284                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2285                 copy_func_cfg_to_qcaps(cfg_req, resp);
2286         } else if (resp->error_code) {
2287                 rc = rte_le_to_cpu_16(resp->error_code);
2288                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2289                 copy_func_cfg_to_qcaps(cfg_req, resp);
2290         }
2291
2292         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2293         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2294         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2295         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2296         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2297         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2298         /*
2299          * TODO: While not supporting VMDq with VFs, max_vnics is always
2300          * forced to 1 in this case
2301          */
2302         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2303         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2304
2305         HWRM_UNLOCK();
2306 }
2307
2308 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2309 {
2310         struct hwrm_func_qcfg_input req = {0};
2311         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2312         int rc;
2313
2314         /* Check for zero MAC address */
2315         HWRM_PREP(req, FUNC_QCFG);
2316         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2317         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2318         if (rc) {
2319                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2320                 return -1;
2321         } else if (resp->error_code) {
2322                 rc = rte_le_to_cpu_16(resp->error_code);
2323                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2324                 return -1;
2325         }
2326         rc = rte_le_to_cpu_16(resp->vlan);
2327
2328         HWRM_UNLOCK();
2329
2330         return rc;
2331 }
2332
2333 static int update_pf_resource_max(struct bnxt *bp)
2334 {
2335         struct hwrm_func_qcfg_input req = {0};
2336         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2337         int rc;
2338
2339         /* And copy the allocated numbers into the pf struct */
2340         HWRM_PREP(req, FUNC_QCFG);
2341         req.fid = rte_cpu_to_le_16(0xffff);
2342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2343         HWRM_CHECK_RESULT();
2344
2345         /* Only TX ring value reflects actual allocation? TODO */
2346         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2347         bp->pf.evb_mode = resp->evb_mode;
2348
2349         HWRM_UNLOCK();
2350
2351         return rc;
2352 }
2353
2354 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2355 {
2356         int rc;
2357
2358         if (!BNXT_PF(bp)) {
2359                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2360                 return -1;
2361         }
2362
2363         rc = bnxt_hwrm_func_qcaps(bp);
2364         if (rc)
2365                 return rc;
2366
2367         bp->pf.func_cfg_flags &=
2368                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2369                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2370         bp->pf.func_cfg_flags |=
2371                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2372         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2373         return rc;
2374 }
2375
2376 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2377 {
2378         struct hwrm_func_cfg_input req = {0};
2379         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2380         int i;
2381         size_t sz;
2382         int rc = 0;
2383         size_t req_buf_sz;
2384
2385         if (!BNXT_PF(bp)) {
2386                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2387                 return -1;
2388         }
2389
2390         rc = bnxt_hwrm_func_qcaps(bp);
2391
2392         if (rc)
2393                 return rc;
2394
2395         bp->pf.active_vfs = num_vfs;
2396
2397         /*
2398          * First, configure the PF to only use one TX ring.  This ensures that
2399          * there are enough rings for all VFs.
2400          *
2401          * If we don't do this, when we call func_alloc() later, we will lock
2402          * extra rings to the PF that won't be available during func_cfg() of
2403          * the VFs.
2404          *
2405          * This has been fixed with firmware versions above 20.6.54
2406          */
2407         bp->pf.func_cfg_flags &=
2408                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2409                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2410         bp->pf.func_cfg_flags |=
2411                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2412         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2413         if (rc)
2414                 return rc;
2415
2416         /*
2417          * Now, create and register a buffer to hold forwarded VF requests
2418          */
2419         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2420         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2421                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2422         if (bp->pf.vf_req_buf == NULL) {
2423                 rc = -ENOMEM;
2424                 goto error_free;
2425         }
2426         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2427                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2428         for (i = 0; i < num_vfs; i++)
2429                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2430                                         (i * HWRM_MAX_REQ_LEN);
2431
2432         rc = bnxt_hwrm_func_buf_rgtr(bp);
2433         if (rc)
2434                 goto error_free;
2435
2436         populate_vf_func_cfg_req(bp, &req, num_vfs);
2437
2438         bp->pf.active_vfs = 0;
2439         for (i = 0; i < num_vfs; i++) {
2440                 add_random_mac_if_needed(bp, &req, i);
2441
2442                 HWRM_PREP(req, FUNC_CFG);
2443                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2444                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2445                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2446
2447                 /* Clear enable flag for next pass */
2448                 req.enables &= ~rte_cpu_to_le_32(
2449                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2450
2451                 if (rc || resp->error_code) {
2452                         RTE_LOG(ERR, PMD,
2453                                 "Failed to initizlie VF %d\n", i);
2454                         RTE_LOG(ERR, PMD,
2455                                 "Not all VFs available. (%d, %d)\n",
2456                                 rc, resp->error_code);
2457                         HWRM_UNLOCK();
2458                         break;
2459                 }
2460
2461                 HWRM_UNLOCK();
2462
2463                 reserve_resources_from_vf(bp, &req, i);
2464                 bp->pf.active_vfs++;
2465                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2466         }
2467
2468         /*
2469          * Now configure the PF to use "the rest" of the resources
2470          * We're using STD_TX_RING_MODE here though which will limit the TX
2471          * rings.  This will allow QoS to function properly.  Not setting this
2472          * will cause PF rings to break bandwidth settings.
2473          */
2474         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2475         if (rc)
2476                 goto error_free;
2477
2478         rc = update_pf_resource_max(bp);
2479         if (rc)
2480                 goto error_free;
2481
2482         return rc;
2483
2484 error_free:
2485         bnxt_hwrm_func_buf_unrgtr(bp);
2486         return rc;
2487 }
2488
2489 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2490 {
2491         struct hwrm_func_cfg_input req = {0};
2492         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2493         int rc;
2494
2495         HWRM_PREP(req, FUNC_CFG);
2496
2497         req.fid = rte_cpu_to_le_16(0xffff);
2498         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2499         req.evb_mode = bp->pf.evb_mode;
2500
2501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2502         HWRM_CHECK_RESULT();
2503         HWRM_UNLOCK();
2504
2505         return rc;
2506 }
2507
2508 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2509                                 uint8_t tunnel_type)
2510 {
2511         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2512         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2513         int rc = 0;
2514
2515         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2516         req.tunnel_type = tunnel_type;
2517         req.tunnel_dst_port_val = port;
2518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2519         HWRM_CHECK_RESULT();
2520
2521         switch (tunnel_type) {
2522         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2523                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2524                 bp->vxlan_port = port;
2525                 break;
2526         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2527                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2528                 bp->geneve_port = port;
2529                 break;
2530         default:
2531                 break;
2532         }
2533
2534         HWRM_UNLOCK();
2535
2536         return rc;
2537 }
2538
2539 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2540                                 uint8_t tunnel_type)
2541 {
2542         struct hwrm_tunnel_dst_port_free_input req = {0};
2543         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2544         int rc = 0;
2545
2546         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2547
2548         req.tunnel_type = tunnel_type;
2549         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2551
2552         HWRM_CHECK_RESULT();
2553         HWRM_UNLOCK();
2554
2555         return rc;
2556 }
2557
2558 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2559                                         uint32_t flags)
2560 {
2561         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2562         struct hwrm_func_cfg_input req = {0};
2563         int rc;
2564
2565         HWRM_PREP(req, FUNC_CFG);
2566
2567         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2568         req.flags = rte_cpu_to_le_32(flags);
2569         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2570
2571         HWRM_CHECK_RESULT();
2572         HWRM_UNLOCK();
2573
2574         return rc;
2575 }
2576
2577 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2578 {
2579         uint32_t *flag = flagp;
2580
2581         vnic->flags = *flag;
2582 }
2583
2584 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2585 {
2586         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2587 }
2588
2589 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2590 {
2591         int rc = 0;
2592         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2593         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2594
2595         HWRM_PREP(req, FUNC_BUF_RGTR);
2596
2597         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2598         req.req_buf_page_size = rte_cpu_to_le_16(
2599                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2600         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2601         req.req_buf_page_addr[0] =
2602                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2603         if (req.req_buf_page_addr[0] == 0) {
2604                 RTE_LOG(ERR, PMD,
2605                         "unable to map buffer address to physical memory\n");
2606                 return -ENOMEM;
2607         }
2608
2609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2610
2611         HWRM_CHECK_RESULT();
2612         HWRM_UNLOCK();
2613
2614         return rc;
2615 }
2616
2617 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2618 {
2619         int rc = 0;
2620         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2621         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2622
2623         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2624
2625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2626
2627         HWRM_CHECK_RESULT();
2628         HWRM_UNLOCK();
2629
2630         return rc;
2631 }
2632
2633 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2634 {
2635         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2636         struct hwrm_func_cfg_input req = {0};
2637         int rc;
2638
2639         HWRM_PREP(req, FUNC_CFG);
2640
2641         req.fid = rte_cpu_to_le_16(0xffff);
2642         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2643         req.enables = rte_cpu_to_le_32(
2644                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2645         req.async_event_cr = rte_cpu_to_le_16(
2646                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2648
2649         HWRM_CHECK_RESULT();
2650         HWRM_UNLOCK();
2651
2652         return rc;
2653 }
2654
2655 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2656 {
2657         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2658         struct hwrm_func_vf_cfg_input req = {0};
2659         int rc;
2660
2661         HWRM_PREP(req, FUNC_VF_CFG);
2662
2663         req.enables = rte_cpu_to_le_32(
2664                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2665         req.async_event_cr = rte_cpu_to_le_16(
2666                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2668
2669         HWRM_CHECK_RESULT();
2670         HWRM_UNLOCK();
2671
2672         return rc;
2673 }
2674
2675 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2676 {
2677         struct hwrm_func_cfg_input req = {0};
2678         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2679         uint16_t dflt_vlan, fid;
2680         uint32_t func_cfg_flags;
2681         int rc = 0;
2682
2683         HWRM_PREP(req, FUNC_CFG);
2684
2685         if (is_vf) {
2686                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2687                 fid = bp->pf.vf_info[vf].fid;
2688                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2689         } else {
2690                 fid = rte_cpu_to_le_16(0xffff);
2691                 func_cfg_flags = bp->pf.func_cfg_flags;
2692                 dflt_vlan = bp->vlan;
2693         }
2694
2695         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2696         req.fid = rte_cpu_to_le_16(fid);
2697         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2698         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2699
2700         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2701
2702         HWRM_CHECK_RESULT();
2703         HWRM_UNLOCK();
2704
2705         return rc;
2706 }
2707
2708 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2709                         uint16_t max_bw, uint16_t enables)
2710 {
2711         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2712         struct hwrm_func_cfg_input req = {0};
2713         int rc;
2714
2715         HWRM_PREP(req, FUNC_CFG);
2716
2717         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2718         req.enables |= rte_cpu_to_le_32(enables);
2719         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2720         req.max_bw = rte_cpu_to_le_32(max_bw);
2721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2722
2723         HWRM_CHECK_RESULT();
2724         HWRM_UNLOCK();
2725
2726         return rc;
2727 }
2728
2729 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2730 {
2731         struct hwrm_func_cfg_input req = {0};
2732         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2733         int rc = 0;
2734
2735         HWRM_PREP(req, FUNC_CFG);
2736
2737         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2738         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2739         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2740         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2741
2742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2743
2744         HWRM_CHECK_RESULT();
2745         HWRM_UNLOCK();
2746
2747         return rc;
2748 }
2749
2750 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2751                               void *encaped, size_t ec_size)
2752 {
2753         int rc = 0;
2754         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2755         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2756
2757         if (ec_size > sizeof(req.encap_request))
2758                 return -1;
2759
2760         HWRM_PREP(req, REJECT_FWD_RESP);
2761
2762         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2763         memcpy(req.encap_request, encaped, ec_size);
2764
2765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2766
2767         HWRM_CHECK_RESULT();
2768         HWRM_UNLOCK();
2769
2770         return rc;
2771 }
2772
2773 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2774                                        struct ether_addr *mac)
2775 {
2776         struct hwrm_func_qcfg_input req = {0};
2777         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2778         int rc;
2779
2780         HWRM_PREP(req, FUNC_QCFG);
2781
2782         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2784
2785         HWRM_CHECK_RESULT();
2786
2787         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2788
2789         HWRM_UNLOCK();
2790
2791         return rc;
2792 }
2793
2794 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2795                             void *encaped, size_t ec_size)
2796 {
2797         int rc = 0;
2798         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2799         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2800
2801         if (ec_size > sizeof(req.encap_request))
2802                 return -1;
2803
2804         HWRM_PREP(req, EXEC_FWD_RESP);
2805
2806         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2807         memcpy(req.encap_request, encaped, ec_size);
2808
2809         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2810
2811         HWRM_CHECK_RESULT();
2812         HWRM_UNLOCK();
2813
2814         return rc;
2815 }
2816
2817 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2818                          struct rte_eth_stats *stats, uint8_t rx)
2819 {
2820         int rc = 0;
2821         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2822         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2823
2824         HWRM_PREP(req, STAT_CTX_QUERY);
2825
2826         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2827
2828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2829
2830         HWRM_CHECK_RESULT();
2831
2832         if (rx) {
2833                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2834                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2835                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2836                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2837                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2838                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2839                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2840                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2841         } else {
2842                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2843                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2844                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2845                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2846                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2847                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2848                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2849         }
2850
2851
2852         HWRM_UNLOCK();
2853
2854         return rc;
2855 }
2856
2857 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2858 {
2859         struct hwrm_port_qstats_input req = {0};
2860         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2861         struct bnxt_pf_info *pf = &bp->pf;
2862         int rc;
2863
2864         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2865                 return 0;
2866
2867         HWRM_PREP(req, PORT_QSTATS);
2868
2869         req.port_id = rte_cpu_to_le_16(pf->port_id);
2870         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2871         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2873
2874         HWRM_CHECK_RESULT();
2875         HWRM_UNLOCK();
2876
2877         return rc;
2878 }
2879
2880 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2881 {
2882         struct hwrm_port_clr_stats_input req = {0};
2883         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2884         struct bnxt_pf_info *pf = &bp->pf;
2885         int rc;
2886
2887         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2888                 return 0;
2889
2890         HWRM_PREP(req, PORT_CLR_STATS);
2891
2892         req.port_id = rte_cpu_to_le_16(pf->port_id);
2893         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2894
2895         HWRM_CHECK_RESULT();
2896         HWRM_UNLOCK();
2897
2898         return rc;
2899 }
2900
2901 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2902 {
2903         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2904         struct hwrm_port_led_qcaps_input req = {0};
2905         int rc;
2906
2907         if (BNXT_VF(bp))
2908                 return 0;
2909
2910         HWRM_PREP(req, PORT_LED_QCAPS);
2911         req.port_id = bp->pf.port_id;
2912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2913
2914         HWRM_CHECK_RESULT();
2915
2916         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2917                 unsigned int i;
2918
2919                 bp->num_leds = resp->num_leds;
2920                 memcpy(bp->leds, &resp->led0_id,
2921                         sizeof(bp->leds[0]) * bp->num_leds);
2922                 for (i = 0; i < bp->num_leds; i++) {
2923                         struct bnxt_led_info *led = &bp->leds[i];
2924
2925                         uint16_t caps = led->led_state_caps;
2926
2927                         if (!led->led_group_id ||
2928                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2929                                 bp->num_leds = 0;
2930                                 break;
2931                         }
2932                 }
2933         }
2934
2935         HWRM_UNLOCK();
2936
2937         return rc;
2938 }
2939
2940 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2941 {
2942         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2943         struct hwrm_port_led_cfg_input req = {0};
2944         struct bnxt_led_cfg *led_cfg;
2945         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2946         uint16_t duration = 0;
2947         int rc, i;
2948
2949         if (!bp->num_leds || BNXT_VF(bp))
2950                 return -EOPNOTSUPP;
2951
2952         HWRM_PREP(req, PORT_LED_CFG);
2953
2954         if (led_on) {
2955                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2956                 duration = rte_cpu_to_le_16(500);
2957         }
2958         req.port_id = bp->pf.port_id;
2959         req.num_leds = bp->num_leds;
2960         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2961         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2962                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2963                 led_cfg->led_id = bp->leds[i].led_id;
2964                 led_cfg->led_state = led_state;
2965                 led_cfg->led_blink_on = duration;
2966                 led_cfg->led_blink_off = duration;
2967                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2968         }
2969
2970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2971
2972         HWRM_CHECK_RESULT();
2973         HWRM_UNLOCK();
2974
2975         return rc;
2976 }
2977
2978 static void
2979 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
2980 {
2981         uint32_t *count = cbdata;
2982
2983         *count = *count + 1;
2984 }
2985
2986 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
2987                                      struct bnxt_vnic_info *vnic __rte_unused)
2988 {
2989         return 0;
2990 }
2991
2992 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
2993 {
2994         uint32_t count = 0;
2995
2996         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
2997             &count, bnxt_vnic_count_hwrm_stub);
2998
2999         return count;
3000 }
3001
3002 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3003                                         uint16_t *vnic_ids)
3004 {
3005         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3006         struct hwrm_func_vf_vnic_ids_query_output *resp =
3007                                                 bp->hwrm_cmd_resp_addr;
3008         int rc;
3009
3010         /* First query all VNIC ids */
3011         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3012
3013         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3014         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3015         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
3016
3017         if (req.vnic_id_tbl_addr == 0) {
3018                 HWRM_UNLOCK();
3019                 RTE_LOG(ERR, PMD,
3020                 "unable to map VNIC ID table address to physical memory\n");
3021                 return -ENOMEM;
3022         }
3023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3024         if (rc) {
3025                 HWRM_UNLOCK();
3026                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3027                 return -1;
3028         } else if (resp->error_code) {
3029                 rc = rte_le_to_cpu_16(resp->error_code);
3030                 HWRM_UNLOCK();
3031                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3032                 return -1;
3033         }
3034         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3035
3036         HWRM_UNLOCK();
3037
3038         return rc;
3039 }
3040
3041 /*
3042  * This function queries the VNIC IDs  for a specified VF. It then calls
3043  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3044  * Then it calls the hwrm_cb function to program this new vnic configuration.
3045  */
3046 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3047         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3048         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3049 {
3050         struct bnxt_vnic_info vnic;
3051         int rc = 0;
3052         int i, num_vnic_ids;
3053         uint16_t *vnic_ids;
3054         size_t vnic_id_sz;
3055         size_t sz;
3056
3057         /* First query all VNIC ids */
3058         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3059         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3060                         RTE_CACHE_LINE_SIZE);
3061         if (vnic_ids == NULL) {
3062                 rc = -ENOMEM;
3063                 return rc;
3064         }
3065         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3066                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3067
3068         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3069
3070         if (num_vnic_ids < 0)
3071                 return num_vnic_ids;
3072
3073         /* Retrieve VNIC, update bd_stall then update */
3074
3075         for (i = 0; i < num_vnic_ids; i++) {
3076                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3077                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3078                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3079                 if (rc)
3080                         break;
3081                 if (vnic.mru <= 4)      /* Indicates unallocated */
3082                         continue;
3083
3084                 vnic_cb(&vnic, cbdata);
3085
3086                 rc = hwrm_cb(bp, &vnic);
3087                 if (rc)
3088                         break;
3089         }
3090
3091         rte_free(vnic_ids);
3092
3093         return rc;
3094 }
3095
3096 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3097                                               bool on)
3098 {
3099         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3100         struct hwrm_func_cfg_input req = {0};
3101         int rc;
3102
3103         HWRM_PREP(req, FUNC_CFG);
3104
3105         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3106         req.enables |= rte_cpu_to_le_32(
3107                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3108         req.vlan_antispoof_mode = on ?
3109                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3110                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3112
3113         HWRM_CHECK_RESULT();
3114         HWRM_UNLOCK();
3115
3116         return rc;
3117 }
3118
3119 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3120 {
3121         struct bnxt_vnic_info vnic;
3122         uint16_t *vnic_ids;
3123         size_t vnic_id_sz;
3124         int num_vnic_ids, i;
3125         size_t sz;
3126         int rc;
3127
3128         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3129         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3130                         RTE_CACHE_LINE_SIZE);
3131         if (vnic_ids == NULL) {
3132                 rc = -ENOMEM;
3133                 return rc;
3134         }
3135
3136         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3137                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3138
3139         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3140         if (rc <= 0)
3141                 goto exit;
3142         num_vnic_ids = rc;
3143
3144         /*
3145          * Loop through to find the default VNIC ID.
3146          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3147          * by sending the hwrm_func_qcfg command to the firmware.
3148          */
3149         for (i = 0; i < num_vnic_ids; i++) {
3150                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3151                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3152                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3153                                         bp->pf.first_vf_id + vf);
3154                 if (rc)
3155                         goto exit;
3156                 if (vnic.func_default) {
3157                         rte_free(vnic_ids);
3158                         return vnic.fw_vnic_id;
3159                 }
3160         }
3161         /* Could not find a default VNIC. */
3162         RTE_LOG(ERR, PMD, "No default VNIC\n");
3163 exit:
3164         rte_free(vnic_ids);
3165         return -1;
3166 }
3167
3168 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3169                          uint16_t dst_id,
3170                          struct bnxt_filter_info *filter)
3171 {
3172         int rc = 0;
3173         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3174         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3175         uint32_t enables = 0;
3176
3177         if (filter->fw_em_filter_id != UINT64_MAX)
3178                 bnxt_hwrm_clear_em_filter(bp, filter);
3179
3180         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3181
3182         req.flags = rte_cpu_to_le_32(filter->flags);
3183
3184         enables = filter->enables |
3185               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3186         req.dst_id = rte_cpu_to_le_16(dst_id);
3187
3188         if (filter->ip_addr_type) {
3189                 req.ip_addr_type = filter->ip_addr_type;
3190                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3191         }
3192         if (enables &
3193             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3194                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3195         if (enables &
3196             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3197                 memcpy(req.src_macaddr, filter->src_macaddr,
3198                        ETHER_ADDR_LEN);
3199         if (enables &
3200             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3201                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3202                        ETHER_ADDR_LEN);
3203         if (enables &
3204             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3205                 req.ovlan_vid = filter->l2_ovlan;
3206         if (enables &
3207             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3208                 req.ivlan_vid = filter->l2_ivlan;
3209         if (enables &
3210             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3211                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3212         if (enables &
3213             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3214                 req.ip_protocol = filter->ip_protocol;
3215         if (enables &
3216             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3217                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3218         if (enables &
3219             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3220                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3221         if (enables &
3222             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3223                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3224         if (enables &
3225             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3226                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3227         if (enables &
3228             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3229                 req.mirror_vnic_id = filter->mirror_vnic_id;
3230
3231         req.enables = rte_cpu_to_le_32(enables);
3232
3233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3234
3235         HWRM_CHECK_RESULT();
3236
3237         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3238         HWRM_UNLOCK();
3239
3240         return rc;
3241 }
3242
3243 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3244 {
3245         int rc = 0;
3246         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3247         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3248
3249         if (filter->fw_em_filter_id == UINT64_MAX)
3250                 return 0;
3251
3252         RTE_LOG(ERR, PMD, "Clear EM filter\n");
3253         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3254
3255         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3256
3257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3258
3259         HWRM_CHECK_RESULT();
3260         HWRM_UNLOCK();
3261
3262         filter->fw_em_filter_id = -1;
3263         filter->fw_l2_filter_id = -1;
3264
3265         return 0;
3266 }
3267
3268 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3269                          uint16_t dst_id,
3270                          struct bnxt_filter_info *filter)
3271 {
3272         int rc = 0;
3273         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3274         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3275                                                 bp->hwrm_cmd_resp_addr;
3276         uint32_t enables = 0;
3277
3278         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3279                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3280
3281         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3282
3283         req.flags = rte_cpu_to_le_32(filter->flags);
3284
3285         enables = filter->enables |
3286               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3287         req.dst_id = rte_cpu_to_le_16(dst_id);
3288
3289
3290         if (filter->ip_addr_type) {
3291                 req.ip_addr_type = filter->ip_addr_type;
3292                 enables |=
3293                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3294         }
3295         if (enables &
3296             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3297                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3298         if (enables &
3299             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3300                 memcpy(req.src_macaddr, filter->src_macaddr,
3301                        ETHER_ADDR_LEN);
3302         //if (enables &
3303             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3304                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3305                        //ETHER_ADDR_LEN);
3306         if (enables &
3307             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3308                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3309         if (enables &
3310             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3311                 req.ip_protocol = filter->ip_protocol;
3312         if (enables &
3313             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3314                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3315         if (enables &
3316             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3317                 req.src_ipaddr_mask[0] =
3318                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3319         if (enables &
3320             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3321                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3322         if (enables &
3323             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3324                 req.dst_ipaddr_mask[0] =
3325                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3326         if (enables &
3327             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3328                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3329         if (enables &
3330             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3331                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3332         if (enables &
3333             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3334                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3335         if (enables &
3336             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3337                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3338         if (enables &
3339             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3340                 req.mirror_vnic_id = filter->mirror_vnic_id;
3341
3342         req.enables = rte_cpu_to_le_32(enables);
3343
3344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3345
3346         HWRM_CHECK_RESULT();
3347
3348         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3349         HWRM_UNLOCK();
3350
3351         return rc;
3352 }
3353
3354 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3355                                 struct bnxt_filter_info *filter)
3356 {
3357         int rc = 0;
3358         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3359         struct hwrm_cfa_ntuple_filter_free_output *resp =
3360                                                 bp->hwrm_cmd_resp_addr;
3361
3362         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3363                 return 0;
3364
3365         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3366
3367         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3368
3369         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3370
3371         HWRM_CHECK_RESULT();
3372         HWRM_UNLOCK();
3373
3374         filter->fw_ntuple_filter_id = -1;
3375         filter->fw_l2_filter_id = -1;
3376
3377         return 0;
3378 }