drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                              struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct bnxt_vnic_info *vnic = NULL;
 371         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 372         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 373
 374         if (filter->fw_l2_filter_id == UINT64_MAX)
 375                 return 0;
 376
 377         if (filter->matching_l2_fltr_ptr)
 378                 l2_filter = filter->matching_l2_fltr_ptr;
 379
 380         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 381                     filter, l2_filter, l2_filter->l2_ref_cnt);
 382
 383         if (l2_filter->l2_ref_cnt == 0)
 384                 return 0;
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402         if (l2_filter->l2_ref_cnt == 0) {
 403                 vnic = l2_filter->vnic;
 404                 if (vnic) {
 405                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 406                                       bnxt_filter_info, next);
 407                         bnxt_free_filter(bp, l2_filter);
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 415                          uint16_t dst_id,
 416                          struct bnxt_filter_info *filter)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 420         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 421         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 422         const struct rte_eth_vmdq_rx_conf *conf =
 423                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 424         uint32_t enables = 0;
 425         uint16_t j = dst_id - 1;
 426
 427         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 428         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 429             conf->pool_map[j].pools & (1UL << j)) {
 430                 PMD_DRV_LOG(DEBUG,
 431                         "Add vlan %u to vmdq pool %u\n",
 432                         conf->pool_map[j].vlan_id, j);
 433
 434                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 435                 filter->enables |=
 436                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 437                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 438         }
 439
 440         if (filter->fw_l2_filter_id != UINT64_MAX)
 441                 bnxt_hwrm_clear_l2_filter(bp, filter);
 442
 443         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 444
 445         req.flags = rte_cpu_to_le_32(filter->flags);
 446
 447         enables = filter->enables |
 448               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 449         req.dst_id = rte_cpu_to_le_16(dst_id);
 450
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 453                 memcpy(req.l2_addr, filter->l2_addr,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 457                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 458                        RTE_ETHER_ADDR_LEN);
 459         if (enables &
 460             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 461                 req.l2_ovlan = filter->l2_ovlan;
 462         if (enables &
 463             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 464                 req.l2_ivlan = filter->l2_ivlan;
 465         if (enables &
 466             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 467                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 468         if (enables &
 469             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 470                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 471         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 472                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 473         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 474                 req.src_type = filter->src_type;
 475         if (filter->pri_hint) {
 476                 req.pri_hint = filter->pri_hint;
 477                 req.l2_filter_id_hint =
 478                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 479         }
 480
 481         req.enables = rte_cpu_to_le_32(enables);
 482
 483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 484
 485         HWRM_CHECK_RESULT();
 486
 487         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 488         HWRM_UNLOCK();
 489
 490         return rc;
 491 }
 492
 493 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 494 {
 495         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 496         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 497         uint32_t flags = 0;
 498         int rc;
 499
 500         if (!ptp)
 501                 return 0;
 502
 503         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 504
 505         if (ptp->rx_filter)
 506                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 507         else
 508                 flags |=
 509                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 510         if (ptp->tx_tstamp_en)
 511                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 512         else
 513                 flags |=
 514                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 515         req.flags = rte_cpu_to_le_32(flags);
 516         req.enables = rte_cpu_to_le_32
 517                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 518         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 519
 520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 521         HWRM_UNLOCK();
 522
 523         return rc;
 524 }
 525
 526 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 527 {
 528         int rc = 0;
 529         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 530         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 531         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 532
 533         if (ptp)
 534                 return 0;
 535
 536         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 537
 538         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         if (!BNXT_CHIP_THOR(bp) &&
 545             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 546                 return 0;
 547
 548         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 549                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 550
 551         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 552         if (!ptp)
 553                 return -ENOMEM;
 554
 555         if (!BNXT_CHIP_THOR(bp)) {
 556                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 557                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 558                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 559                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 560                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 561                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 562                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 563                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 564                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 565                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 566                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 567                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 568                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 569                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 570                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 571                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 572                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 573                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 574         }
 575
 576         ptp->bp = bp;
 577         bp->ptp_cfg = ptp;
 578
 579         return 0;
 580 }
 581
 582 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 583 {
 584         int rc = 0;
 585         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 586         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 587         uint16_t new_max_vfs;
 588         uint32_t flags;
 589         int i;
 590
 591         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 592
 593         req.fid = rte_cpu_to_le_16(0xffff);
 594
 595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 596
 597         HWRM_CHECK_RESULT();
 598
 599         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 600         flags = rte_le_to_cpu_32(resp->flags);
 601         if (BNXT_PF(bp)) {
 602                 bp->pf.port_id = resp->port_id;
 603                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 604                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 605                 new_max_vfs = bp->pdev->max_vfs;
 606                 if (new_max_vfs != bp->pf.max_vfs) {
 607                         if (bp->pf.vf_info)
 608                                 rte_free(bp->pf.vf_info);
 609                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 610                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 611                         bp->pf.max_vfs = new_max_vfs;
 612                         for (i = 0; i < new_max_vfs; i++) {
 613                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 614                                 bp->pf.vf_info[i].vlan_table =
 615                                         rte_zmalloc("VF VLAN table",
 616                                                     getpagesize(),
 617                                                     getpagesize());
 618                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 619                                         PMD_DRV_LOG(ERR,
 620                                         "Fail to alloc VLAN table for VF %d\n",
 621                                         i);
 622                                 else
 623                                         rte_mem_lock_page(
 624                                                 bp->pf.vf_info[i].vlan_table);
 625                                 bp->pf.vf_info[i].vlan_as_table =
 626                                         rte_zmalloc("VF VLAN AS table",
 627                                                     getpagesize(),
 628                                                     getpagesize());
 629                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 630                                         PMD_DRV_LOG(ERR,
 631                                         "Alloc VLAN AS table for VF %d fail\n",
 632                                         i);
 633                                 else
 634                                         rte_mem_lock_page(
 635                                                bp->pf.vf_info[i].vlan_as_table);
 636                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 637                         }
 638                 }
 639         }
 640
 641         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 642         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 643         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 644         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 645         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 646         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 647         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 648         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 649         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 650         if (!BNXT_CHIP_THOR(bp))
 651                 bp->max_l2_ctx += bp->max_rx_em_flows;
 652         /* TODO: For now, do not support VMDq/RFS on VFs. */
 653         if (BNXT_PF(bp)) {
 654                 if (bp->pf.max_vfs)
 655                         bp->max_vnics = 1;
 656                 else
 657                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 658         } else {
 659                 bp->max_vnics = 1;
 660         }
 661         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 662         if (BNXT_PF(bp)) {
 663                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 664                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 665                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 666                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 667                         HWRM_UNLOCK();
 668                         bnxt_hwrm_ptp_qcfg(bp);
 669                 }
 670         }
 671
 672         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 673                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 676                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 677                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 678         }
 679
 680         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 681                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 682
 683         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 684                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 685
 686         HWRM_UNLOCK();
 687
 688         return rc;
 689 }
 690
 691 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 692 {
 693         int rc;
 694
 695         rc = __bnxt_hwrm_func_qcaps(bp);
 696         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 697                 rc = bnxt_alloc_ctx_mem(bp);
 698                 if (rc)
 699                         return rc;
 700
 701                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 702                 if (!rc)
 703                         bp->flags |= BNXT_FLAG_NEW_RM;
 704         }
 705
 706         /* On older FW,
 707          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 708          * But the error can be ignored. Return success.
 709          */
 710
 711         return 0;
 712 }
 713
 714 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 715 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 716 {
 717         int rc = 0;
 718         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 719         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 720
 721         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 722
 723         req.target_id = rte_cpu_to_le_16(0xffff);
 724
 725         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 726
 727         HWRM_CHECK_RESULT();
 728
 729         if (rte_le_to_cpu_32(resp->flags) &
 730             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 731                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 732                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 733         }
 734
 735         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 736
 737         HWRM_UNLOCK();
 738
 739         return rc;
 740 }
 741
 742 int bnxt_hwrm_func_reset(struct bnxt *bp)
 743 {
 744         int rc = 0;
 745         struct hwrm_func_reset_input req = {.req_type = 0 };
 746         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 747
 748         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 749
 750         req.enables = rte_cpu_to_le_32(0);
 751
 752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 753
 754         HWRM_CHECK_RESULT();
 755         HWRM_UNLOCK();
 756
 757         return rc;
 758 }
 759
 760 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 761 {
 762         int rc;
 763         uint32_t flags = 0;
 764         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 765         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 766
 767         if (bp->flags & BNXT_FLAG_REGISTERED)
 768                 return 0;
 769
 770         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 771                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 772         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 773                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 774
 775         /* PFs and trusted VFs should indicate the support of the
 776          * Master capability on non Stingray platform
 777          */
 778         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 779                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 780
 781         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 782         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 783                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 784         req.ver_maj = RTE_VER_YEAR;
 785         req.ver_min = RTE_VER_MONTH;
 786         req.ver_upd = RTE_VER_MINOR;
 787
 788         if (BNXT_PF(bp)) {
 789                 req.enables |= rte_cpu_to_le_32(
 790                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 791                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 792                        RTE_MIN(sizeof(req.vf_req_fwd),
 793                                sizeof(bp->pf.vf_req_fwd)));
 794
 795                 /*
 796                  * PF can sniff HWRM API issued by VF. This can be set up by
 797                  * linux driver and inherited by the DPDK PF driver. Clear
 798                  * this HWRM sniffer list in FW because DPDK PF driver does
 799                  * not support this.
 800                  */
 801                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 802         }
 803
 804         req.flags = rte_cpu_to_le_32(flags);
 805
 806         req.async_event_fwd[0] |=
 807                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 808                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 809                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 810                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 811                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 812         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 813                 req.async_event_fwd[0] |=
 814                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 815         req.async_event_fwd[1] |=
 816                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 817                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 818
 819         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 820
 821         HWRM_CHECK_RESULT();
 822
 823         flags = rte_le_to_cpu_32(resp->flags);
 824         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 825                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 826
 827         HWRM_UNLOCK();
 828
 829         bp->flags |= BNXT_FLAG_REGISTERED;
 830
 831         return rc;
 832 }
 833
 834 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 835 {
 836         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 837                 return 0;
 838
 839         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 840 }
 841
 842 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 843 {
 844         int rc;
 845         uint32_t flags = 0;
 846         uint32_t enables;
 847         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 848         struct hwrm_func_vf_cfg_input req = {0};
 849
 850         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 851
 852         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 853                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 854                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 855                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 856                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 857
 858         if (BNXT_HAS_RING_GRPS(bp)) {
 859                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 860                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 861         }
 862
 863         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 864         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 865                                             AGG_RING_MULTIPLIER);
 866         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 867         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 868                                               bp->tx_nr_rings +
 869                                               BNXT_NUM_ASYNC_CPR(bp));
 870         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 871         if (bp->vf_resv_strategy ==
 872             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 873                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 874                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 875                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 876                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 877                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 878                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 879         } else if (bp->vf_resv_strategy ==
 880                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 881                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 882                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 883         }
 884
 885         if (test)
 886                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 887                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 888                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 889                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 890                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 891                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 892
 893         if (test && BNXT_HAS_RING_GRPS(bp))
 894                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 895
 896         req.flags = rte_cpu_to_le_32(flags);
 897         req.enables |= rte_cpu_to_le_32(enables);
 898
 899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 900
 901         if (test)
 902                 HWRM_CHECK_RESULT_SILENT();
 903         else
 904                 HWRM_CHECK_RESULT();
 905
 906         HWRM_UNLOCK();
 907         return rc;
 908 }
 909
 910 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 911 {
 912         int rc;
 913         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 914         struct hwrm_func_resource_qcaps_input req = {0};
 915
 916         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 917         req.fid = rte_cpu_to_le_16(0xffff);
 918
 919         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 920
 921         HWRM_CHECK_RESULT_SILENT();
 922
 923         if (BNXT_VF(bp)) {
 924                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 925                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 926                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 927                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 928                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 929                 /* func_resource_qcaps does not return max_rx_em_flows.
 930                  * So use the value provided by func_qcaps.
 931                  */
 932                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 933                 if (!BNXT_CHIP_THOR(bp))
 934                         bp->max_l2_ctx += bp->max_rx_em_flows;
 935                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 936                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 937         }
 938         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 939         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 940         if (bp->vf_resv_strategy >
 941             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 942                 bp->vf_resv_strategy =
 943                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 944
 945         HWRM_UNLOCK();
 946         return rc;
 947 }
 948
 949 int bnxt_hwrm_ver_get(struct bnxt *bp)
 950 {
 951         int rc = 0;
 952         struct hwrm_ver_get_input req = {.req_type = 0 };
 953         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 954         uint32_t fw_version;
 955         uint16_t max_resp_len;
 956         char type[RTE_MEMZONE_NAMESIZE];
 957         uint32_t dev_caps_cfg;
 958
 959         bp->max_req_len = HWRM_MAX_REQ_LEN;
 960         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 961
 962         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 963         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 964         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 965
 966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 967
 968         if (bp->flags & BNXT_FLAG_FW_RESET)
 969                 HWRM_CHECK_RESULT_SILENT();
 970         else
 971                 HWRM_CHECK_RESULT();
 972
 973         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 974                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 975                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 976                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 977         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 978                      (resp->hwrm_fw_min_8b << 16) |
 979                      (resp->hwrm_fw_bld_8b << 8) |
 980                      resp->hwrm_fw_rsvd_8b;
 981         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 982                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 983
 984         fw_version = resp->hwrm_intf_maj_8b << 16;
 985         fw_version |= resp->hwrm_intf_min_8b << 8;
 986         fw_version |= resp->hwrm_intf_upd_8b;
 987         bp->hwrm_spec_code = fw_version;
 988
 989         /* def_req_timeout value is in milliseconds */
 990         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 991         /* convert timeout to usec */
 992         bp->hwrm_cmd_timeout *= 1000;
 993         if (!bp->hwrm_cmd_timeout)
 994                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 995
 996         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 997                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 998                 rc = -EINVAL;
 999                 goto error;
1000         }
1001
1002         if (bp->max_req_len > resp->max_req_win_len) {
1003                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1004                 rc = -EINVAL;
1005         }
1006         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1007         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1008         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1009                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1010
1011         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1012         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1013
1014         if (bp->max_resp_len != max_resp_len) {
1015                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1016                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1017                         bp->pdev->addr.devid, bp->pdev->addr.function);
1018
1019                 rte_free(bp->hwrm_cmd_resp_addr);
1020
1021                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1022                 if (bp->hwrm_cmd_resp_addr == NULL) {
1023                         rc = -ENOMEM;
1024                         goto error;
1025                 }
1026                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1027                 bp->hwrm_cmd_resp_dma_addr =
1028                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1029                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1030                         PMD_DRV_LOG(ERR,
1031                         "Unable to map response buffer to physical memory.\n");
1032                         rc = -ENOMEM;
1033                         goto error;
1034                 }
1035                 bp->max_resp_len = max_resp_len;
1036         }
1037
1038         if ((dev_caps_cfg &
1039                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1040             (dev_caps_cfg &
1041              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1042                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1043                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1044         }
1045
1046         if (((dev_caps_cfg &
1047               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1048              (dev_caps_cfg &
1049               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1050             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1051                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1052                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1053                         bp->pdev->addr.devid, bp->pdev->addr.function);
1054
1055                 rte_free(bp->hwrm_short_cmd_req_addr);
1056
1057                 bp->hwrm_short_cmd_req_addr =
1058                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1059                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1060                         rc = -ENOMEM;
1061                         goto error;
1062                 }
1063                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1064                 bp->hwrm_short_cmd_req_dma_addr =
1065                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1066                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1067                         rte_free(bp->hwrm_short_cmd_req_addr);
1068                         PMD_DRV_LOG(ERR,
1069                                 "Unable to map buffer to physical memory.\n");
1070                         rc = -ENOMEM;
1071                         goto error;
1072                 }
1073         }
1074         if (dev_caps_cfg &
1075             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1076                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1077                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1078         }
1079         if (dev_caps_cfg &
1080             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1081                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1082         if (dev_caps_cfg &
1083             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1084                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1085                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1086         }
1087
1088 error:
1089         HWRM_UNLOCK();
1090         return rc;
1091 }
1092
1093 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1094 {
1095         int rc;
1096         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1097         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1098
1099         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1100                 return 0;
1101
1102         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1103         req.flags = flags;
1104
1105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1106
1107         HWRM_CHECK_RESULT();
1108         HWRM_UNLOCK();
1109
1110         return rc;
1111 }
1112
1113 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1114 {
1115         int rc = 0;
1116         struct hwrm_port_phy_cfg_input req = {0};
1117         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1118         uint32_t enables = 0;
1119
1120         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1121
1122         if (conf->link_up) {
1123                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1124                 if (bp->link_info.auto_mode && conf->link_speed) {
1125                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1126                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1127                 }
1128
1129                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1130                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1131                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1132                 /*
1133                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1134                  * any auto mode, even "none".
1135                  */
1136                 if (!conf->link_speed) {
1137                         /* No speeds specified. Enable AutoNeg - all speeds */
1138                         req.auto_mode =
1139                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1140                 }
1141                 /* AutoNeg - Advertise speeds specified. */
1142                 if (conf->auto_link_speed_mask &&
1143                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1144                         req.auto_mode =
1145                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1146                         req.auto_link_speed_mask =
1147                                 conf->auto_link_speed_mask;
1148                         enables |=
1149                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1150                 }
1151
1152                 req.auto_duplex = conf->duplex;
1153                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1154                 req.auto_pause = conf->auto_pause;
1155                 req.force_pause = conf->force_pause;
1156                 /* Set force_pause if there is no auto or if there is a force */
1157                 if (req.auto_pause && !req.force_pause)
1158                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1159                 else
1160                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1161
1162                 req.enables = rte_cpu_to_le_32(enables);
1163         } else {
1164                 req.flags =
1165                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1166                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1167         }
1168
1169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1170
1171         HWRM_CHECK_RESULT();
1172         HWRM_UNLOCK();
1173
1174         return rc;
1175 }
1176
1177 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1178                                    struct bnxt_link_info *link_info)
1179 {
1180         int rc = 0;
1181         struct hwrm_port_phy_qcfg_input req = {0};
1182         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1183
1184         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1185
1186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1187
1188         HWRM_CHECK_RESULT();
1189
1190         link_info->phy_link_status = resp->link;
1191         link_info->link_up =
1192                 (link_info->phy_link_status ==
1193                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1194         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1195         link_info->duplex = resp->duplex_cfg;
1196         link_info->pause = resp->pause;
1197         link_info->auto_pause = resp->auto_pause;
1198         link_info->force_pause = resp->force_pause;
1199         link_info->auto_mode = resp->auto_mode;
1200         link_info->phy_type = resp->phy_type;
1201         link_info->media_type = resp->media_type;
1202
1203         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1204         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1205         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1206         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1207         link_info->phy_ver[0] = resp->phy_maj;
1208         link_info->phy_ver[1] = resp->phy_min;
1209         link_info->phy_ver[2] = resp->phy_bld;
1210
1211         HWRM_UNLOCK();
1212
1213         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1214         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1215         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1216         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1217         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1218                     link_info->auto_link_speed_mask);
1219         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1220                     link_info->force_link_speed);
1221
1222         return rc;
1223 }
1224
1225 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1226 {
1227         int i = 0;
1228
1229         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1230                 if (bp->tx_cos_queue[i].profile ==
1231                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1232                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1233                         return true;
1234                 }
1235         }
1236         return false;
1237 }
1238
1239 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1240 {
1241         int i = 0;
1242
1243         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1244                 if (bp->tx_cos_queue[i].profile !=
1245                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1246                     bp->tx_cos_queue[i].id !=
1247                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1248                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1249                         break;
1250                 }
1251         }
1252 }
1253
1254 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1255 {
1256         int rc = 0;
1257         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1258         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1259         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1260         int i;
1261
1262 get_rx_info:
1263         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1264
1265         req.flags = rte_cpu_to_le_32(dir);
1266         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1267         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1268             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1269                 req.drv_qmap_cap =
1270                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1272
1273         HWRM_CHECK_RESULT();
1274
1275         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1276                 GET_TX_QUEUE_INFO(0);
1277                 GET_TX_QUEUE_INFO(1);
1278                 GET_TX_QUEUE_INFO(2);
1279                 GET_TX_QUEUE_INFO(3);
1280                 GET_TX_QUEUE_INFO(4);
1281                 GET_TX_QUEUE_INFO(5);
1282                 GET_TX_QUEUE_INFO(6);
1283                 GET_TX_QUEUE_INFO(7);
1284         } else  {
1285                 GET_RX_QUEUE_INFO(0);
1286                 GET_RX_QUEUE_INFO(1);
1287                 GET_RX_QUEUE_INFO(2);
1288                 GET_RX_QUEUE_INFO(3);
1289                 GET_RX_QUEUE_INFO(4);
1290                 GET_RX_QUEUE_INFO(5);
1291                 GET_RX_QUEUE_INFO(6);
1292                 GET_RX_QUEUE_INFO(7);
1293         }
1294
1295         HWRM_UNLOCK();
1296
1297         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1298                 goto done;
1299
1300         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1301                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1302         } else {
1303                 int j;
1304
1305                 /* iterate and find the COSq profile to use for Tx */
1306                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1307                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1308                                 if (bp->tx_cos_queue[i].id != 0xff)
1309                                         bp->tx_cosq_id[j++] =
1310                                                 bp->tx_cos_queue[i].id;
1311                         }
1312                 } else {
1313                         /* When CoS classification is disabled, for normal NIC
1314                          * operations, ideally we should look to use LOSSY.
1315                          * If not found, fallback to the first valid profile
1316                          */
1317                         if (!bnxt_find_lossy_profile(bp))
1318                                 bnxt_find_first_valid_profile(bp);
1319
1320                 }
1321         }
1322
1323         bp->max_tc = resp->max_configurable_queues;
1324         bp->max_lltc = resp->max_configurable_lossless_queues;
1325         if (bp->max_tc > BNXT_MAX_QUEUE)
1326                 bp->max_tc = BNXT_MAX_QUEUE;
1327         bp->max_q = bp->max_tc;
1328
1329         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1330                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1331                 goto get_rx_info;
1332         }
1333
1334 done:
1335         return rc;
1336 }
1337
1338 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1339                          struct bnxt_ring *ring,
1340                          uint32_t ring_type, uint32_t map_index,
1341                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1342                          uint16_t tx_cosq_id)
1343 {
1344         int rc = 0;
1345         uint32_t enables = 0;
1346         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1347         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1348         struct rte_mempool *mb_pool;
1349         uint16_t rx_buf_size;
1350
1351         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1352
1353         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1354         req.fbo = rte_cpu_to_le_32(0);
1355         /* Association of ring index with doorbell index */
1356         req.logical_id = rte_cpu_to_le_16(map_index);
1357         req.length = rte_cpu_to_le_32(ring->ring_size);
1358
1359         switch (ring_type) {
1360         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1361                 req.ring_type = ring_type;
1362                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1363                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1364                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1365                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1366                         enables |=
1367                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1368                 break;
1369         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1370                 req.ring_type = ring_type;
1371                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1372                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1373                 if (BNXT_CHIP_THOR(bp)) {
1374                         mb_pool = bp->rx_queues[0]->mb_pool;
1375                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1376                                       RTE_PKTMBUF_HEADROOM;
1377                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1378                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1379                         enables |=
1380                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1381                 }
1382                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1383                         enables |=
1384                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1385                 break;
1386         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1387                 req.ring_type = ring_type;
1388                 if (BNXT_HAS_NQ(bp)) {
1389                         /* Association of cp ring with nq */
1390                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1391                         enables |=
1392                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1393                 }
1394                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1395                 break;
1396         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1397                 req.ring_type = ring_type;
1398                 req.page_size = BNXT_PAGE_SHFT;
1399                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1400                 break;
1401         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1402                 req.ring_type = ring_type;
1403                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1404
1405                 mb_pool = bp->rx_queues[0]->mb_pool;
1406                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1407                               RTE_PKTMBUF_HEADROOM;
1408                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1409                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1410
1411                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1412                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1413                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1414                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1415                 break;
1416         default:
1417                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1418                         ring_type);
1419                 HWRM_UNLOCK();
1420                 return -EINVAL;
1421         }
1422         req.enables = rte_cpu_to_le_32(enables);
1423
1424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1425
1426         if (rc || resp->error_code) {
1427                 if (rc == 0 && resp->error_code)
1428                         rc = rte_le_to_cpu_16(resp->error_code);
1429                 switch (ring_type) {
1430                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1431                         PMD_DRV_LOG(ERR,
1432                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1433                         HWRM_UNLOCK();
1434                         return rc;
1435                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1436                         PMD_DRV_LOG(ERR,
1437                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1438                         HWRM_UNLOCK();
1439                         return rc;
1440                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1441                         PMD_DRV_LOG(ERR,
1442                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1443                                     rc);
1444                         HWRM_UNLOCK();
1445                         return rc;
1446                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1447                         PMD_DRV_LOG(ERR,
1448                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1449                         HWRM_UNLOCK();
1450                         return rc;
1451                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1452                         PMD_DRV_LOG(ERR,
1453                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1454                         HWRM_UNLOCK();
1455                         return rc;
1456                 default:
1457                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1458                         HWRM_UNLOCK();
1459                         return rc;
1460                 }
1461         }
1462
1463         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1464         HWRM_UNLOCK();
1465         return rc;
1466 }
1467
1468 int bnxt_hwrm_ring_free(struct bnxt *bp,
1469                         struct bnxt_ring *ring, uint32_t ring_type)
1470 {
1471         int rc;
1472         struct hwrm_ring_free_input req = {.req_type = 0 };
1473         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1474
1475         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1476
1477         req.ring_type = ring_type;
1478         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         if (rc || resp->error_code) {
1483                 if (rc == 0 && resp->error_code)
1484                         rc = rte_le_to_cpu_16(resp->error_code);
1485                 HWRM_UNLOCK();
1486
1487                 switch (ring_type) {
1488                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1489                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1490                                 rc);
1491                         return rc;
1492                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1493                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1494                                 rc);
1495                         return rc;
1496                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1497                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1498                                 rc);
1499                         return rc;
1500                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1501                         PMD_DRV_LOG(ERR,
1502                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1503                         return rc;
1504                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1505                         PMD_DRV_LOG(ERR,
1506                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1507                         return rc;
1508                 default:
1509                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1510                         return rc;
1511                 }
1512         }
1513         HWRM_UNLOCK();
1514         return 0;
1515 }
1516
1517 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1518 {
1519         int rc = 0;
1520         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1521         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1522
1523         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1524
1525         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1526         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1527         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1528         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1529
1530         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1531
1532         HWRM_CHECK_RESULT();
1533
1534         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1535
1536         HWRM_UNLOCK();
1537
1538         return rc;
1539 }
1540
1541 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1542 {
1543         int rc;
1544         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1545         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1546
1547         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1548
1549         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1550
1551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1552
1553         HWRM_CHECK_RESULT();
1554         HWRM_UNLOCK();
1555
1556         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1557         return rc;
1558 }
1559
1560 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1561 {
1562         int rc = 0;
1563         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1564         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1565
1566         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1567                 return rc;
1568
1569         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1570
1571         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1572
1573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1574
1575         HWRM_CHECK_RESULT();
1576         HWRM_UNLOCK();
1577
1578         return rc;
1579 }
1580
1581 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1582                                 unsigned int idx __rte_unused)
1583 {
1584         int rc;
1585         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1586         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1587
1588         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1589
1590         req.update_period_ms = rte_cpu_to_le_32(0);
1591
1592         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1593
1594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1595
1596         HWRM_CHECK_RESULT();
1597
1598         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1599
1600         HWRM_UNLOCK();
1601
1602         return rc;
1603 }
1604
1605 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1606                                 unsigned int idx __rte_unused)
1607 {
1608         int rc;
1609         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1610         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1611
1612         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1613
1614         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1615
1616         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1617
1618         HWRM_CHECK_RESULT();
1619         HWRM_UNLOCK();
1620
1621         return rc;
1622 }
1623
1624 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1625 {
1626         int rc = 0, i, j;
1627         struct hwrm_vnic_alloc_input req = { 0 };
1628         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1629
1630         if (!BNXT_HAS_RING_GRPS(bp))
1631                 goto skip_ring_grps;
1632
1633         /* map ring groups to this vnic */
1634         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1635                 vnic->start_grp_id, vnic->end_grp_id);
1636         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1637                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1638
1639         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1640         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1641         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1643
1644 skip_ring_grps:
1645         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1646         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1647
1648         if (vnic->func_default)
1649                 req.flags =
1650                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1652
1653         HWRM_CHECK_RESULT();
1654
1655         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1656         HWRM_UNLOCK();
1657         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1658         return rc;
1659 }
1660
1661 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1662                                         struct bnxt_vnic_info *vnic,
1663                                         struct bnxt_plcmodes_cfg *pmode)
1664 {
1665         int rc = 0;
1666         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1667         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1668
1669         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1670
1671         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1672
1673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1674
1675         HWRM_CHECK_RESULT();
1676
1677         pmode->flags = rte_le_to_cpu_32(resp->flags);
1678         /* dflt_vnic bit doesn't exist in the _cfg command */
1679         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1680         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1681         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1682         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1683
1684         HWRM_UNLOCK();
1685
1686         return rc;
1687 }
1688
1689 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1690                                        struct bnxt_vnic_info *vnic,
1691                                        struct bnxt_plcmodes_cfg *pmode)
1692 {
1693         int rc = 0;
1694         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1695         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1696
1697         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1698                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1699                 return rc;
1700         }
1701
1702         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1703
1704         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1705         req.flags = rte_cpu_to_le_32(pmode->flags);
1706         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1707         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1708         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1709         req.enables = rte_cpu_to_le_32(
1710             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1711             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1712             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1713         );
1714
1715         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1716
1717         HWRM_CHECK_RESULT();
1718         HWRM_UNLOCK();
1719
1720         return rc;
1721 }
1722
1723 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1724 {
1725         int rc = 0;
1726         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1727         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1728         struct bnxt_plcmodes_cfg pmodes = { 0 };
1729         uint32_t ctx_enable_flag = 0;
1730         uint32_t enables = 0;
1731
1732         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1733                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1734                 return rc;
1735         }
1736
1737         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1738         if (rc)
1739                 return rc;
1740
1741         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1742
1743         if (BNXT_CHIP_THOR(bp)) {
1744                 int dflt_rxq = vnic->start_grp_id;
1745                 struct bnxt_rx_ring_info *rxr;
1746                 struct bnxt_cp_ring_info *cpr;
1747                 struct bnxt_rx_queue *rxq;
1748                 int i;
1749
1750                 /*
1751                  * The first active receive ring is used as the VNIC
1752                  * default receive ring. If there are no active receive
1753                  * rings (all corresponding receive queues are stopped),
1754                  * the first receive ring is used.
1755                  */
1756                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1757                         rxq = bp->eth_dev->data->rx_queues[i];
1758                         if (rxq->rx_started) {
1759                                 dflt_rxq = i;
1760                                 break;
1761                         }
1762                 }
1763
1764                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1765                 rxr = rxq->rx_ring;
1766                 cpr = rxq->cp_ring;
1767
1768                 req.default_rx_ring_id =
1769                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1770                 req.default_cmpl_ring_id =
1771                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1772                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1773                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1774                 goto config_mru;
1775         }
1776
1777         /* Only RSS support for now TBD: COS & LB */
1778         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1779         if (vnic->lb_rule != 0xffff)
1780                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1781         if (vnic->cos_rule != 0xffff)
1782                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1783         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1784                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1785                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1786         }
1787         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1788                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1789                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1790         }
1791
1792         enables |= ctx_enable_flag;
1793         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1794         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1795         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1796         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1797
1798 config_mru:
1799         req.enables = rte_cpu_to_le_32(enables);
1800         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1801         req.mru = rte_cpu_to_le_16(vnic->mru);
1802         /* Configure default VNIC only once. */
1803         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1804                 req.flags |=
1805                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1806                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1807         }
1808         if (vnic->vlan_strip)
1809                 req.flags |=
1810                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1811         if (vnic->bd_stall)
1812                 req.flags |=
1813                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1814         if (vnic->roce_dual)
1815                 req.flags |= rte_cpu_to_le_32(
1816                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1817         if (vnic->roce_only)
1818                 req.flags |= rte_cpu_to_le_32(
1819                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1820         if (vnic->rss_dflt_cr)
1821                 req.flags |= rte_cpu_to_le_32(
1822                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1823
1824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1825
1826         HWRM_CHECK_RESULT();
1827         HWRM_UNLOCK();
1828
1829         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1830
1831         return rc;
1832 }
1833
1834 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1835                 int16_t fw_vf_id)
1836 {
1837         int rc = 0;
1838         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1839         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1840
1841         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1842                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1843                 return rc;
1844         }
1845         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1846
1847         req.enables =
1848                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1849         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1850         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1851
1852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1853
1854         HWRM_CHECK_RESULT();
1855
1856         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1857         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1858         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1859         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1860         vnic->mru = rte_le_to_cpu_16(resp->mru);
1861         vnic->func_default = rte_le_to_cpu_32(
1862                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1863         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1864                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1865         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1866                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1867         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1868                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1869         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1870                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1871         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1872                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1873
1874         HWRM_UNLOCK();
1875
1876         return rc;
1877 }
1878
1879 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1880                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1881 {
1882         int rc = 0;
1883         uint16_t ctx_id;
1884         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1885         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1886                                                 bp->hwrm_cmd_resp_addr;
1887
1888         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1889
1890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1891         HWRM_CHECK_RESULT();
1892
1893         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1894         if (!BNXT_HAS_RING_GRPS(bp))
1895                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1896         else if (ctx_idx == 0)
1897                 vnic->rss_rule = ctx_id;
1898
1899         HWRM_UNLOCK();
1900
1901         return rc;
1902 }
1903
1904 static
1905 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1906                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1907 {
1908         int rc = 0;
1909         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1910         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1911                                                 bp->hwrm_cmd_resp_addr;
1912
1913         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1914                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1915                 return rc;
1916         }
1917         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1918
1919         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1920
1921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1922
1923         HWRM_CHECK_RESULT();
1924         HWRM_UNLOCK();
1925
1926         return rc;
1927 }
1928
1929 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1930 {
1931         int rc = 0;
1932
1933         if (BNXT_CHIP_THOR(bp)) {
1934                 int j;
1935
1936                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1937                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1938                                                       vnic,
1939                                                       vnic->fw_grp_ids[j]);
1940                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1941                 }
1942                 vnic->num_lb_ctxts = 0;
1943         } else {
1944                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1945                 vnic->rss_rule = INVALID_HW_RING_ID;
1946         }
1947
1948         return rc;
1949 }
1950
1951 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1952 {
1953         int rc = 0;
1954         struct hwrm_vnic_free_input req = {.req_type = 0 };
1955         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1956
1957         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1958                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1959                 return rc;
1960         }
1961
1962         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1963
1964         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1965
1966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1967
1968         HWRM_CHECK_RESULT();
1969         HWRM_UNLOCK();
1970
1971         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1972         /* Configure default VNIC again if necessary. */
1973         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1974                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1975
1976         return rc;
1977 }
1978
1979 static int
1980 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1981 {
1982         int i;
1983         int rc = 0;
1984         int nr_ctxs = vnic->num_lb_ctxts;
1985         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1986         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1987
1988         for (i = 0; i < nr_ctxs; i++) {
1989                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1990
1991                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1992                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1993                 req.hash_mode_flags = vnic->hash_mode;
1994
1995                 req.hash_key_tbl_addr =
1996                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1997
1998                 req.ring_grp_tbl_addr =
1999                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2000                                          i * HW_HASH_INDEX_SIZE);
2001                 req.ring_table_pair_index = i;
2002                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2003
2004                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2005                                             BNXT_USE_CHIMP_MB);
2006
2007                 HWRM_CHECK_RESULT();
2008                 HWRM_UNLOCK();
2009         }
2010
2011         return rc;
2012 }
2013
2014 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2015                            struct bnxt_vnic_info *vnic)
2016 {
2017         int rc = 0;
2018         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2019         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2020
2021         if (!vnic->rss_table)
2022                 return 0;
2023
2024         if (BNXT_CHIP_THOR(bp))
2025                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2026
2027         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2028
2029         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2030         req.hash_mode_flags = vnic->hash_mode;
2031
2032         req.ring_grp_tbl_addr =
2033             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2034         req.hash_key_tbl_addr =
2035             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2036         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2037         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2038
2039         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2040
2041         HWRM_CHECK_RESULT();
2042         HWRM_UNLOCK();
2043
2044         return rc;
2045 }
2046
2047 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2048                         struct bnxt_vnic_info *vnic)
2049 {
2050         int rc = 0;
2051         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2052         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2053         uint16_t size;
2054
2055         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2056                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2057                 return rc;
2058         }
2059
2060         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2061
2062         req.flags = rte_cpu_to_le_32(
2063                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2064
2065         req.enables = rte_cpu_to_le_32(
2066                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2067
2068         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2069         size -= RTE_PKTMBUF_HEADROOM;
2070         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2071
2072         req.jumbo_thresh = rte_cpu_to_le_16(size);
2073         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2074
2075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2076
2077         HWRM_CHECK_RESULT();
2078         HWRM_UNLOCK();
2079
2080         return rc;
2081 }
2082
2083 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2084                         struct bnxt_vnic_info *vnic, bool enable)
2085 {
2086         int rc = 0;
2087         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2088         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2089
2090         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2091                 if (enable)
2092                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2093                 return -ENOTSUP;
2094         }
2095
2096         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2097                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2098                 return 0;
2099         }
2100
2101         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2102
2103         if (enable) {
2104                 req.enables = rte_cpu_to_le_32(
2105                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2106                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2107                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2108                 req.flags = rte_cpu_to_le_32(
2109                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2110                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2112                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2113                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2114                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2115                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2116                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2117                 req.min_agg_len = rte_cpu_to_le_32(512);
2118         }
2119         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2120
2121         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2122
2123         HWRM_CHECK_RESULT();
2124         HWRM_UNLOCK();
2125
2126         return rc;
2127 }
2128
2129 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2130 {
2131         struct hwrm_func_cfg_input req = {0};
2132         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2133         int rc;
2134
2135         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2136         req.enables = rte_cpu_to_le_32(
2137                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2138         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2139         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2140
2141         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2142
2143         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2144         HWRM_CHECK_RESULT();
2145         HWRM_UNLOCK();
2146
2147         bp->pf.vf_info[vf].random_mac = false;
2148
2149         return rc;
2150 }
2151
2152 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2153                                   uint64_t *dropped)
2154 {
2155         int rc = 0;
2156         struct hwrm_func_qstats_input req = {.req_type = 0};
2157         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2158
2159         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2160
2161         req.fid = rte_cpu_to_le_16(fid);
2162
2163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2164
2165         HWRM_CHECK_RESULT();
2166
2167         if (dropped)
2168                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2169
2170         HWRM_UNLOCK();
2171
2172         return rc;
2173 }
2174
2175 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2176                           struct rte_eth_stats *stats)
2177 {
2178         int rc = 0;
2179         struct hwrm_func_qstats_input req = {.req_type = 0};
2180         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2181
2182         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2183
2184         req.fid = rte_cpu_to_le_16(fid);
2185
2186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2187
2188         HWRM_CHECK_RESULT();
2189
2190         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2191         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2192         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2193         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2194         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2195         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2196
2197         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2198         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2199         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2200         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2201         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2202         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2203
2204         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2205         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2206         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2207
2208         HWRM_UNLOCK();
2209
2210         return rc;
2211 }
2212
2213 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2214 {
2215         int rc = 0;
2216         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2217         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2218
2219         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2220
2221         req.fid = rte_cpu_to_le_16(fid);
2222
2223         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2224
2225         HWRM_CHECK_RESULT();
2226         HWRM_UNLOCK();
2227
2228         return rc;
2229 }
2230
2231 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2232 {
2233         unsigned int i;
2234         int rc = 0;
2235
2236         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2237                 struct bnxt_tx_queue *txq;
2238                 struct bnxt_rx_queue *rxq;
2239                 struct bnxt_cp_ring_info *cpr;
2240
2241                 if (i >= bp->rx_cp_nr_rings) {
2242                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2243                         cpr = txq->cp_ring;
2244                 } else {
2245                         rxq = bp->rx_queues[i];
2246                         cpr = rxq->cp_ring;
2247                 }
2248
2249                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2250                 if (rc)
2251                         return rc;
2252         }
2253         return 0;
2254 }
2255
2256 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2257 {
2258         int rc;
2259         unsigned int i;
2260         struct bnxt_cp_ring_info *cpr;
2261
2262         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2263
2264                 if (i >= bp->rx_cp_nr_rings) {
2265                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2266                 } else {
2267                         cpr = bp->rx_queues[i]->cp_ring;
2268                         if (BNXT_HAS_RING_GRPS(bp))
2269                                 bp->grp_info[i].fw_stats_ctx = -1;
2270                 }
2271                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2272                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2273                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2274                         if (rc)
2275                                 return rc;
2276                 }
2277         }
2278         return 0;
2279 }
2280
2281 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2282 {
2283         unsigned int i;
2284         int rc = 0;
2285
2286         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2287                 struct bnxt_tx_queue *txq;
2288                 struct bnxt_rx_queue *rxq;
2289                 struct bnxt_cp_ring_info *cpr;
2290
2291                 if (i >= bp->rx_cp_nr_rings) {
2292                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2293                         cpr = txq->cp_ring;
2294                 } else {
2295                         rxq = bp->rx_queues[i];
2296                         cpr = rxq->cp_ring;
2297                 }
2298
2299                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2300
2301                 if (rc)
2302                         return rc;
2303         }
2304         return rc;
2305 }
2306
2307 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2308 {
2309         uint16_t idx;
2310         uint32_t rc = 0;
2311
2312         if (!BNXT_HAS_RING_GRPS(bp))
2313                 return 0;
2314
2315         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2316
2317                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2318                         continue;
2319
2320                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2321
2322                 if (rc)
2323                         return rc;
2324         }
2325         return rc;
2326 }
2327
2328 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2329 {
2330         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2331
2332         bnxt_hwrm_ring_free(bp, cp_ring,
2333                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2334         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2335         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2336                                      sizeof(*cpr->cp_desc_ring));
2337         cpr->cp_raw_cons = 0;
2338         cpr->valid = 0;
2339 }
2340
2341 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2342 {
2343         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2344
2345         bnxt_hwrm_ring_free(bp, cp_ring,
2346                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2347         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2348         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2349                         sizeof(*cpr->cp_desc_ring));
2350         cpr->cp_raw_cons = 0;
2351         cpr->valid = 0;
2352 }
2353
2354 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2355 {
2356         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2357         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2358         struct bnxt_ring *ring = rxr->rx_ring_struct;
2359         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2360
2361         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2362                 bnxt_hwrm_ring_free(bp, ring,
2363                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2364                 ring->fw_ring_id = INVALID_HW_RING_ID;
2365                 if (BNXT_HAS_RING_GRPS(bp))
2366                         bp->grp_info[queue_index].rx_fw_ring_id =
2367                                                         INVALID_HW_RING_ID;
2368                 memset(rxr->rx_desc_ring, 0,
2369                        rxr->rx_ring_struct->ring_size *
2370                        sizeof(*rxr->rx_desc_ring));
2371                 memset(rxr->rx_buf_ring, 0,
2372                        rxr->rx_ring_struct->ring_size *
2373                        sizeof(*rxr->rx_buf_ring));
2374                 rxr->rx_prod = 0;
2375         }
2376         ring = rxr->ag_ring_struct;
2377         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2378                 bnxt_hwrm_ring_free(bp, ring,
2379                                     BNXT_CHIP_THOR(bp) ?
2380                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2381                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2382                 ring->fw_ring_id = INVALID_HW_RING_ID;
2383                 memset(rxr->ag_buf_ring, 0,
2384                        rxr->ag_ring_struct->ring_size *
2385                        sizeof(*rxr->ag_buf_ring));
2386                 rxr->ag_prod = 0;
2387                 if (BNXT_HAS_RING_GRPS(bp))
2388                         bp->grp_info[queue_index].ag_fw_ring_id =
2389                                                         INVALID_HW_RING_ID;
2390         }
2391         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2392                 bnxt_free_cp_ring(bp, cpr);
2393
2394         if (BNXT_HAS_RING_GRPS(bp))
2395                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2396 }
2397
2398 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2399 {
2400         unsigned int i;
2401
2402         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2403                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2404                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2405                 struct bnxt_ring *ring = txr->tx_ring_struct;
2406                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2407
2408                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2409                         bnxt_hwrm_ring_free(bp, ring,
2410                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2411                         ring->fw_ring_id = INVALID_HW_RING_ID;
2412                         memset(txr->tx_desc_ring, 0,
2413                                         txr->tx_ring_struct->ring_size *
2414                                         sizeof(*txr->tx_desc_ring));
2415                         memset(txr->tx_buf_ring, 0,
2416                                         txr->tx_ring_struct->ring_size *
2417                                         sizeof(*txr->tx_buf_ring));
2418                         txr->tx_prod = 0;
2419                         txr->tx_cons = 0;
2420                 }
2421                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2422                         bnxt_free_cp_ring(bp, cpr);
2423                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2424                 }
2425         }
2426
2427         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2428                 bnxt_free_hwrm_rx_ring(bp, i);
2429
2430         return 0;
2431 }
2432
2433 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2434 {
2435         uint16_t i;
2436         uint32_t rc = 0;
2437
2438         if (!BNXT_HAS_RING_GRPS(bp))
2439                 return 0;
2440
2441         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2442                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2443                 if (rc)
2444                         return rc;
2445         }
2446         return rc;
2447 }
2448
2449 /*
2450  * HWRM utility functions
2451  */
2452
2453 void bnxt_free_hwrm_resources(struct bnxt *bp)
2454 {
2455         /* Release memzone */
2456         rte_free(bp->hwrm_cmd_resp_addr);
2457         rte_free(bp->hwrm_short_cmd_req_addr);
2458         bp->hwrm_cmd_resp_addr = NULL;
2459         bp->hwrm_short_cmd_req_addr = NULL;
2460         bp->hwrm_cmd_resp_dma_addr = 0;
2461         bp->hwrm_short_cmd_req_dma_addr = 0;
2462 }
2463
2464 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2465 {
2466         struct rte_pci_device *pdev = bp->pdev;
2467         char type[RTE_MEMZONE_NAMESIZE];
2468
2469         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2470                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2471         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2472         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2473         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2474         if (bp->hwrm_cmd_resp_addr == NULL)
2475                 return -ENOMEM;
2476         bp->hwrm_cmd_resp_dma_addr =
2477                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2478         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2479                 PMD_DRV_LOG(ERR,
2480                         "unable to map response address to physical memory\n");
2481                 return -ENOMEM;
2482         }
2483         rte_spinlock_init(&bp->hwrm_lock);
2484
2485         return 0;
2486 }
2487
2488 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2489 {
2490         struct bnxt_filter_info *filter;
2491         int rc = 0;
2492
2493         STAILQ_FOREACH(filter, &vnic->filter, next) {
2494                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2495                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2496                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2497                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2498                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2499                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2500                 bnxt_free_filter(bp, filter);
2501         }
2502         return rc;
2503 }
2504
2505 static int
2506 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2507 {
2508         struct bnxt_filter_info *filter;
2509         struct rte_flow *flow;
2510         int rc = 0;
2511
2512         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2513                 flow = STAILQ_FIRST(&vnic->flow_list);
2514                 filter = flow->filter;
2515                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2516                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2517                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2518                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2519                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2520                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2521
2522                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2523                 rte_free(flow);
2524         }
2525         return rc;
2526 }
2527
2528 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2529 {
2530         struct bnxt_filter_info *filter;
2531         int rc = 0;
2532
2533         STAILQ_FOREACH(filter, &vnic->filter, next) {
2534                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2535                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2536                                                      filter);
2537                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2538                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2539                                                          filter);
2540                 else
2541                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2542                                                      filter);
2543                 if (rc)
2544                         break;
2545         }
2546         return rc;
2547 }
2548
2549 void bnxt_free_tunnel_ports(struct bnxt *bp)
2550 {
2551         if (bp->vxlan_port_cnt)
2552                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2553                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2554         bp->vxlan_port = 0;
2555         if (bp->geneve_port_cnt)
2556                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2557                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2558         bp->geneve_port = 0;
2559 }
2560
2561 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2562 {
2563         int i;
2564
2565         if (bp->vnic_info == NULL)
2566                 return;
2567
2568         /*
2569          * Cleanup VNICs in reverse order, to make sure the L2 filter
2570          * from vnic0 is last to be cleaned up.
2571          */
2572         for (i = bp->max_vnics - 1; i >= 0; i--) {
2573                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2574
2575                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2576                         continue;
2577
2578                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2579
2580                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2581
2582                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2583
2584                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2585
2586                 bnxt_hwrm_vnic_free(bp, vnic);
2587
2588                 rte_free(vnic->fw_grp_ids);
2589         }
2590         /* Ring resources */
2591         bnxt_free_all_hwrm_rings(bp);
2592         bnxt_free_all_hwrm_ring_grps(bp);
2593         bnxt_free_all_hwrm_stat_ctxs(bp);
2594         bnxt_free_tunnel_ports(bp);
2595 }
2596
2597 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2598 {
2599         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2600
2601         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2602                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2603
2604         switch (conf_link_speed) {
2605         case ETH_LINK_SPEED_10M_HD:
2606         case ETH_LINK_SPEED_100M_HD:
2607                 /* FALLTHROUGH */
2608                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2609         }
2610         return hw_link_duplex;
2611 }
2612
2613 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2614 {
2615         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2616 }
2617
2618 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2619 {
2620         uint16_t eth_link_speed = 0;
2621
2622         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2623                 return ETH_LINK_SPEED_AUTONEG;
2624
2625         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2626         case ETH_LINK_SPEED_100M:
2627         case ETH_LINK_SPEED_100M_HD:
2628                 /* FALLTHROUGH */
2629                 eth_link_speed =
2630                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2631                 break;
2632         case ETH_LINK_SPEED_1G:
2633                 eth_link_speed =
2634                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2635                 break;
2636         case ETH_LINK_SPEED_2_5G:
2637                 eth_link_speed =
2638                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2639                 break;
2640         case ETH_LINK_SPEED_10G:
2641                 eth_link_speed =
2642                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2643                 break;
2644         case ETH_LINK_SPEED_20G:
2645                 eth_link_speed =
2646                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2647                 break;
2648         case ETH_LINK_SPEED_25G:
2649                 eth_link_speed =
2650                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2651                 break;
2652         case ETH_LINK_SPEED_40G:
2653                 eth_link_speed =
2654                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2655                 break;
2656         case ETH_LINK_SPEED_50G:
2657                 eth_link_speed =
2658                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2659                 break;
2660         case ETH_LINK_SPEED_100G:
2661                 eth_link_speed =
2662                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2663                 break;
2664         default:
2665                 PMD_DRV_LOG(ERR,
2666                         "Unsupported link speed %d; default to AUTO\n",
2667                         conf_link_speed);
2668                 break;
2669         }
2670         return eth_link_speed;
2671 }
2672
2673 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2674                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2675                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2676                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2677
2678 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2679 {
2680         uint32_t one_speed;
2681
2682         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2683                 return 0;
2684
2685         if (link_speed & ETH_LINK_SPEED_FIXED) {
2686                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2687
2688                 if (one_speed & (one_speed - 1)) {
2689                         PMD_DRV_LOG(ERR,
2690                                 "Invalid advertised speeds (%u) for port %u\n",
2691                                 link_speed, port_id);
2692                         return -EINVAL;
2693                 }
2694                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2695                         PMD_DRV_LOG(ERR,
2696                                 "Unsupported advertised speed (%u) for port %u\n",
2697                                 link_speed, port_id);
2698                         return -EINVAL;
2699                 }
2700         } else {
2701                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2702                         PMD_DRV_LOG(ERR,
2703                                 "Unsupported advertised speeds (%u) for port %u\n",
2704                                 link_speed, port_id);
2705                         return -EINVAL;
2706                 }
2707         }
2708         return 0;
2709 }
2710
2711 static uint16_t
2712 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2713 {
2714         uint16_t ret = 0;
2715
2716         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2717                 if (bp->link_info.support_speeds)
2718                         return bp->link_info.support_speeds;
2719                 link_speed = BNXT_SUPPORTED_SPEEDS;
2720         }
2721
2722         if (link_speed & ETH_LINK_SPEED_100M)
2723                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2724         if (link_speed & ETH_LINK_SPEED_100M_HD)
2725                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2726         if (link_speed & ETH_LINK_SPEED_1G)
2727                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2728         if (link_speed & ETH_LINK_SPEED_2_5G)
2729                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2730         if (link_speed & ETH_LINK_SPEED_10G)
2731                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2732         if (link_speed & ETH_LINK_SPEED_20G)
2733                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2734         if (link_speed & ETH_LINK_SPEED_25G)
2735                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2736         if (link_speed & ETH_LINK_SPEED_40G)
2737                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2738         if (link_speed & ETH_LINK_SPEED_50G)
2739                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2740         if (link_speed & ETH_LINK_SPEED_100G)
2741                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2742         return ret;
2743 }
2744
2745 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2746 {
2747         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2748
2749         switch (hw_link_speed) {
2750         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2751                 eth_link_speed = ETH_SPEED_NUM_100M;
2752                 break;
2753         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2754                 eth_link_speed = ETH_SPEED_NUM_1G;
2755                 break;
2756         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2757                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2758                 break;
2759         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2760                 eth_link_speed = ETH_SPEED_NUM_10G;
2761                 break;
2762         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2763                 eth_link_speed = ETH_SPEED_NUM_20G;
2764                 break;
2765         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2766                 eth_link_speed = ETH_SPEED_NUM_25G;
2767                 break;
2768         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2769                 eth_link_speed = ETH_SPEED_NUM_40G;
2770                 break;
2771         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2772                 eth_link_speed = ETH_SPEED_NUM_50G;
2773                 break;
2774         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2775                 eth_link_speed = ETH_SPEED_NUM_100G;
2776                 break;
2777         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2778         default:
2779                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2780                         hw_link_speed);
2781                 break;
2782         }
2783         return eth_link_speed;
2784 }
2785
2786 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2787 {
2788         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2789
2790         switch (hw_link_duplex) {
2791         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2792         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2793                 /* FALLTHROUGH */
2794                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2795                 break;
2796         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2797                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2798                 break;
2799         default:
2800                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2801                         hw_link_duplex);
2802                 break;
2803         }
2804         return eth_link_duplex;
2805 }
2806
2807 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2808 {
2809         int rc = 0;
2810         struct bnxt_link_info *link_info = &bp->link_info;
2811
2812         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2813         if (rc) {
2814                 PMD_DRV_LOG(ERR,
2815                         "Get link config failed with rc %d\n", rc);
2816                 goto exit;
2817         }
2818         if (link_info->link_speed)
2819                 link->link_speed =
2820                         bnxt_parse_hw_link_speed(link_info->link_speed);
2821         else
2822                 link->link_speed = ETH_SPEED_NUM_NONE;
2823         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2824         link->link_status = link_info->link_up;
2825         link->link_autoneg = link_info->auto_mode ==
2826                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2827                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2828 exit:
2829         return rc;
2830 }
2831
2832 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2833 {
2834         int rc = 0;
2835         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2836         struct bnxt_link_info link_req;
2837         uint16_t speed, autoneg;
2838
2839         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2840                 return 0;
2841
2842         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2843                         bp->eth_dev->data->port_id);
2844         if (rc)
2845                 goto error;
2846
2847         memset(&link_req, 0, sizeof(link_req));
2848         link_req.link_up = link_up;
2849         if (!link_up)
2850                 goto port_phy_cfg;
2851
2852         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2853         if (BNXT_CHIP_THOR(bp) &&
2854             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2855                 /* 40G is not supported as part of media auto detect.
2856                  * The speed should be forced and autoneg disabled
2857                  * to configure 40G speed.
2858                  */
2859                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2860                 autoneg = 0;
2861         }
2862
2863         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2864         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2865         /* Autoneg can be done only when the FW allows.
2866          * When user configures fixed speed of 40G and later changes to
2867          * any other speed, auto_link_speed/force_link_speed is still set
2868          * to 40G until link comes up at new speed.
2869          */
2870         if (autoneg == 1 &&
2871             !(!BNXT_CHIP_THOR(bp) &&
2872               (bp->link_info.auto_link_speed ||
2873                bp->link_info.force_link_speed))) {
2874                 link_req.phy_flags |=
2875                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2876                 link_req.auto_link_speed_mask =
2877                         bnxt_parse_eth_link_speed_mask(bp,
2878                                                        dev_conf->link_speeds);
2879         } else {
2880                 if (bp->link_info.phy_type ==
2881                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2882                     bp->link_info.phy_type ==
2883                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2884                     bp->link_info.media_type ==
2885                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2886                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2887                         return -EINVAL;
2888                 }
2889
2890                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2891                 /* If user wants a particular speed try that first. */
2892                 if (speed)
2893                         link_req.link_speed = speed;
2894                 else if (bp->link_info.force_link_speed)
2895                         link_req.link_speed = bp->link_info.force_link_speed;
2896                 else
2897                         link_req.link_speed = bp->link_info.auto_link_speed;
2898         }
2899         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2900         link_req.auto_pause = bp->link_info.auto_pause;
2901         link_req.force_pause = bp->link_info.force_pause;
2902
2903 port_phy_cfg:
2904         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2905         if (rc) {
2906                 PMD_DRV_LOG(ERR,
2907                         "Set link config failed with rc %d\n", rc);
2908         }
2909
2910 error:
2911         return rc;
2912 }
2913
2914 /* JIRA 22088 */
2915 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2916 {
2917         struct hwrm_func_qcfg_input req = {0};
2918         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2919         uint16_t flags;
2920         int rc = 0;
2921
2922         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2923         req.fid = rte_cpu_to_le_16(0xffff);
2924
2925         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2926
2927         HWRM_CHECK_RESULT();
2928
2929         /* Hard Coded.. 0xfff VLAN ID mask */
2930         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2931         flags = rte_le_to_cpu_16(resp->flags);
2932         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2933                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2934
2935         if (BNXT_VF(bp) &&
2936             !BNXT_VF_IS_TRUSTED(bp) &&
2937             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2938                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2939                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2940         } else if (BNXT_VF(bp) &&
2941                    BNXT_VF_IS_TRUSTED(bp) &&
2942                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2943                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2944                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2945         }
2946
2947         if (mtu)
2948                 *mtu = rte_le_to_cpu_16(resp->mtu);
2949
2950         switch (resp->port_partition_type) {
2951         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2952         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2953         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2954                 /* FALLTHROUGH */
2955                 bp->port_partition_type = resp->port_partition_type;
2956                 break;
2957         default:
2958                 bp->port_partition_type = 0;
2959                 break;
2960         }
2961
2962         HWRM_UNLOCK();
2963
2964         return rc;
2965 }
2966
2967 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2968                                    struct hwrm_func_qcaps_output *qcaps)
2969 {
2970         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2971         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2972                sizeof(qcaps->mac_address));
2973         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2974         qcaps->max_rx_rings = fcfg->num_rx_rings;
2975         qcaps->max_tx_rings = fcfg->num_tx_rings;
2976         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2977         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2978         qcaps->max_vfs = 0;
2979         qcaps->first_vf_id = 0;
2980         qcaps->max_vnics = fcfg->num_vnics;
2981         qcaps->max_decap_records = 0;
2982         qcaps->max_encap_records = 0;
2983         qcaps->max_tx_wm_flows = 0;
2984         qcaps->max_tx_em_flows = 0;
2985         qcaps->max_rx_wm_flows = 0;
2986         qcaps->max_rx_em_flows = 0;
2987         qcaps->max_flow_id = 0;
2988         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2989         qcaps->max_sp_tx_rings = 0;
2990         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2991 }
2992
2993 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2994 {
2995         struct hwrm_func_cfg_input req = {0};
2996         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2997         uint32_t enables;
2998         int rc;
2999
3000         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3001                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3002                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3003                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3004                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3005                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3006                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3007                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3008                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3009
3010         if (BNXT_HAS_RING_GRPS(bp)) {
3011                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3012                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3013         } else if (BNXT_HAS_NQ(bp)) {
3014                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3015                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3016         }
3017
3018         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3019         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3020         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3021         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3022         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3023         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3024         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3025         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3026         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3027         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3028         req.fid = rte_cpu_to_le_16(0xffff);
3029         req.enables = rte_cpu_to_le_32(enables);
3030
3031         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3032
3033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3034
3035         HWRM_CHECK_RESULT();
3036         HWRM_UNLOCK();
3037
3038         return rc;
3039 }
3040
3041 static void populate_vf_func_cfg_req(struct bnxt *bp,
3042                                      struct hwrm_func_cfg_input *req,
3043                                      int num_vfs)
3044 {
3045         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3046                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3047                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3048                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3049                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3050                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3051                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3052                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3053                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3054                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3055
3056         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3057                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3058                                     BNXT_NUM_VLANS);
3059         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3060         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3061                                                 (num_vfs + 1));
3062         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3063         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3064                                                (num_vfs + 1));
3065         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3066         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3067         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3068         /* TODO: For now, do not support VMDq/RFS on VFs. */
3069         req->num_vnics = rte_cpu_to_le_16(1);
3070         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3071                                                  (num_vfs + 1));
3072 }
3073
3074 static void add_random_mac_if_needed(struct bnxt *bp,
3075                                      struct hwrm_func_cfg_input *cfg_req,
3076                                      int vf)
3077 {
3078         struct rte_ether_addr mac;
3079
3080         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3081                 return;
3082
3083         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3084                 cfg_req->enables |=
3085                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3086                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3087                 bp->pf.vf_info[vf].random_mac = true;
3088         } else {
3089                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3090                         RTE_ETHER_ADDR_LEN);
3091         }
3092 }
3093
3094 static void reserve_resources_from_vf(struct bnxt *bp,
3095                                       struct hwrm_func_cfg_input *cfg_req,
3096                                       int vf)
3097 {
3098         struct hwrm_func_qcaps_input req = {0};
3099         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3100         int rc;
3101
3102         /* Get the actual allocated values now */
3103         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3104         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3106
3107         if (rc) {
3108                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3109                 copy_func_cfg_to_qcaps(cfg_req, resp);
3110         } else if (resp->error_code) {
3111                 rc = rte_le_to_cpu_16(resp->error_code);
3112                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3113                 copy_func_cfg_to_qcaps(cfg_req, resp);
3114         }
3115
3116         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3117         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3118         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3119         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3120         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3121         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3122         /*
3123          * TODO: While not supporting VMDq with VFs, max_vnics is always
3124          * forced to 1 in this case
3125          */
3126         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3127         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3128
3129         HWRM_UNLOCK();
3130 }
3131
3132 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3133 {
3134         struct hwrm_func_qcfg_input req = {0};
3135         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3136         int rc;
3137
3138         /* Check for zero MAC address */
3139         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3140         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3142         HWRM_CHECK_RESULT();
3143         rc = rte_le_to_cpu_16(resp->vlan);
3144
3145         HWRM_UNLOCK();
3146
3147         return rc;
3148 }
3149
3150 static int update_pf_resource_max(struct bnxt *bp)
3151 {
3152         struct hwrm_func_qcfg_input req = {0};
3153         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3154         int rc;
3155
3156         /* And copy the allocated numbers into the pf struct */
3157         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3158         req.fid = rte_cpu_to_le_16(0xffff);
3159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3160         HWRM_CHECK_RESULT();
3161
3162         /* Only TX ring value reflects actual allocation? TODO */
3163         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3164         bp->pf.evb_mode = resp->evb_mode;
3165
3166         HWRM_UNLOCK();
3167
3168         return rc;
3169 }
3170
3171 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3172 {
3173         int rc;
3174
3175         if (!BNXT_PF(bp)) {
3176                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3177                 return -EINVAL;
3178         }
3179
3180         rc = bnxt_hwrm_func_qcaps(bp);
3181         if (rc)
3182                 return rc;
3183
3184         bp->pf.func_cfg_flags &=
3185                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3186                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3187         bp->pf.func_cfg_flags |=
3188                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3189         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3190         rc = __bnxt_hwrm_func_qcaps(bp);
3191         return rc;
3192 }
3193
3194 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3195 {
3196         struct hwrm_func_cfg_input req = {0};
3197         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3198         int i;
3199         size_t sz;
3200         int rc = 0;
3201         size_t req_buf_sz;
3202
3203         if (!BNXT_PF(bp)) {
3204                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3205                 return -EINVAL;
3206         }
3207
3208         rc = bnxt_hwrm_func_qcaps(bp);
3209
3210         if (rc)
3211                 return rc;
3212
3213         bp->pf.active_vfs = num_vfs;
3214
3215         /*
3216          * First, configure the PF to only use one TX ring.  This ensures that
3217          * there are enough rings for all VFs.
3218          *
3219          * If we don't do this, when we call func_alloc() later, we will lock
3220          * extra rings to the PF that won't be available during func_cfg() of
3221          * the VFs.
3222          *
3223          * This has been fixed with firmware versions above 20.6.54
3224          */
3225         bp->pf.func_cfg_flags &=
3226                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3227                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3228         bp->pf.func_cfg_flags |=
3229                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3230         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3231         if (rc)
3232                 return rc;
3233
3234         /*
3235          * Now, create and register a buffer to hold forwarded VF requests
3236          */
3237         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3238         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3239                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3240         if (bp->pf.vf_req_buf == NULL) {
3241                 rc = -ENOMEM;
3242                 goto error_free;
3243         }
3244         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3245                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3246         for (i = 0; i < num_vfs; i++)
3247                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3248                                         (i * HWRM_MAX_REQ_LEN);
3249
3250         rc = bnxt_hwrm_func_buf_rgtr(bp);
3251         if (rc)
3252                 goto error_free;
3253
3254         populate_vf_func_cfg_req(bp, &req, num_vfs);
3255
3256         bp->pf.active_vfs = 0;
3257         for (i = 0; i < num_vfs; i++) {
3258                 add_random_mac_if_needed(bp, &req, i);
3259
3260                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3261                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3262                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3263                 rc = bnxt_hwrm_send_message(bp,
3264                                             &req,
3265                                             sizeof(req),
3266                                             BNXT_USE_CHIMP_MB);
3267
3268                 /* Clear enable flag for next pass */
3269                 req.enables &= ~rte_cpu_to_le_32(
3270                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3271
3272                 if (rc || resp->error_code) {
3273                         PMD_DRV_LOG(ERR,
3274                                 "Failed to initizlie VF %d\n", i);
3275                         PMD_DRV_LOG(ERR,
3276                                 "Not all VFs available. (%d, %d)\n",
3277                                 rc, resp->error_code);
3278                         HWRM_UNLOCK();
3279                         break;
3280                 }
3281
3282                 HWRM_UNLOCK();
3283
3284                 reserve_resources_from_vf(bp, &req, i);
3285                 bp->pf.active_vfs++;
3286                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3287         }
3288
3289         /*
3290          * Now configure the PF to use "the rest" of the resources
3291          * We're using STD_TX_RING_MODE here though which will limit the TX
3292          * rings.  This will allow QoS to function properly.  Not setting this
3293          * will cause PF rings to break bandwidth settings.
3294          */
3295         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3296         if (rc)
3297                 goto error_free;
3298
3299         rc = update_pf_resource_max(bp);
3300         if (rc)
3301                 goto error_free;
3302
3303         return rc;
3304
3305 error_free:
3306         bnxt_hwrm_func_buf_unrgtr(bp);
3307         return rc;
3308 }
3309
3310 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3311 {
3312         struct hwrm_func_cfg_input req = {0};
3313         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3314         int rc;
3315
3316         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3317
3318         req.fid = rte_cpu_to_le_16(0xffff);
3319         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3320         req.evb_mode = bp->pf.evb_mode;
3321
3322         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3323         HWRM_CHECK_RESULT();
3324         HWRM_UNLOCK();
3325
3326         return rc;
3327 }
3328
3329 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3330                                 uint8_t tunnel_type)
3331 {
3332         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3333         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3334         int rc = 0;
3335
3336         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3337         req.tunnel_type = tunnel_type;
3338         req.tunnel_dst_port_val = port;
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340         HWRM_CHECK_RESULT();
3341
3342         switch (tunnel_type) {
3343         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3344                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3345                 bp->vxlan_port = port;
3346                 break;
3347         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3348                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3349                 bp->geneve_port = port;
3350                 break;
3351         default:
3352                 break;
3353         }
3354
3355         HWRM_UNLOCK();
3356
3357         return rc;
3358 }
3359
3360 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3361                                 uint8_t tunnel_type)
3362 {
3363         struct hwrm_tunnel_dst_port_free_input req = {0};
3364         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3365         int rc = 0;
3366
3367         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3368
3369         req.tunnel_type = tunnel_type;
3370         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372
3373         HWRM_CHECK_RESULT();
3374         HWRM_UNLOCK();
3375
3376         return rc;
3377 }
3378
3379 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3380                                         uint32_t flags)
3381 {
3382         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3383         struct hwrm_func_cfg_input req = {0};
3384         int rc;
3385
3386         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3387
3388         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3389         req.flags = rte_cpu_to_le_32(flags);
3390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3391
3392         HWRM_CHECK_RESULT();
3393         HWRM_UNLOCK();
3394
3395         return rc;
3396 }
3397
3398 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3399 {
3400         uint32_t *flag = flagp;
3401
3402         vnic->flags = *flag;
3403 }
3404
3405 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3406 {
3407         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3408 }
3409
3410 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3411 {
3412         int rc = 0;
3413         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3414         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3415
3416         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3417
3418         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3419         req.req_buf_page_size = rte_cpu_to_le_16(
3420                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3421         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3422         req.req_buf_page_addr0 =
3423                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3424         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3425                 PMD_DRV_LOG(ERR,
3426                         "unable to map buffer address to physical memory\n");
3427                 return -ENOMEM;
3428         }
3429
3430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3431
3432         HWRM_CHECK_RESULT();
3433         HWRM_UNLOCK();
3434
3435         return rc;
3436 }
3437
3438 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3439 {
3440         int rc = 0;
3441         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3442         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3443
3444         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3445                 return 0;
3446
3447         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3448
3449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3450
3451         HWRM_CHECK_RESULT();
3452         HWRM_UNLOCK();
3453
3454         return rc;
3455 }
3456
3457 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3458 {
3459         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3460         struct hwrm_func_cfg_input req = {0};
3461         int rc;
3462
3463         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3464
3465         req.fid = rte_cpu_to_le_16(0xffff);
3466         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3467         req.enables = rte_cpu_to_le_32(
3468                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3469         req.async_event_cr = rte_cpu_to_le_16(
3470                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472
3473         HWRM_CHECK_RESULT();
3474         HWRM_UNLOCK();
3475
3476         return rc;
3477 }
3478
3479 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3480 {
3481         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3482         struct hwrm_func_vf_cfg_input req = {0};
3483         int rc;
3484
3485         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3486
3487         req.enables = rte_cpu_to_le_32(
3488                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3489         req.async_event_cr = rte_cpu_to_le_16(
3490                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3492
3493         HWRM_CHECK_RESULT();
3494         HWRM_UNLOCK();
3495
3496         return rc;
3497 }
3498
3499 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3500 {
3501         struct hwrm_func_cfg_input req = {0};
3502         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3503         uint16_t dflt_vlan, fid;
3504         uint32_t func_cfg_flags;
3505         int rc = 0;
3506
3507         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3508
3509         if (is_vf) {
3510                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3511                 fid = bp->pf.vf_info[vf].fid;
3512                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3513         } else {
3514                 fid = rte_cpu_to_le_16(0xffff);
3515                 func_cfg_flags = bp->pf.func_cfg_flags;
3516                 dflt_vlan = bp->vlan;
3517         }
3518
3519         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3520         req.fid = rte_cpu_to_le_16(fid);
3521         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3522         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3523
3524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3525
3526         HWRM_CHECK_RESULT();
3527         HWRM_UNLOCK();
3528
3529         return rc;
3530 }
3531
3532 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3533                         uint16_t max_bw, uint16_t enables)
3534 {
3535         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3536         struct hwrm_func_cfg_input req = {0};
3537         int rc;
3538
3539         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3540
3541         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3542         req.enables |= rte_cpu_to_le_32(enables);
3543         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3544         req.max_bw = rte_cpu_to_le_32(max_bw);
3545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3546
3547         HWRM_CHECK_RESULT();
3548         HWRM_UNLOCK();
3549
3550         return rc;
3551 }
3552
3553 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3554 {
3555         struct hwrm_func_cfg_input req = {0};
3556         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3557         int rc = 0;
3558
3559         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3560
3561         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3562         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3563         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3564         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3565
3566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3567
3568         HWRM_CHECK_RESULT();
3569         HWRM_UNLOCK();
3570
3571         return rc;
3572 }
3573
3574 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3575 {
3576         int rc;
3577
3578         if (BNXT_PF(bp))
3579                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3580         else
3581                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3582
3583         return rc;
3584 }
3585
3586 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3587                               void *encaped, size_t ec_size)
3588 {
3589         int rc = 0;
3590         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3591         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3592
3593         if (ec_size > sizeof(req.encap_request))
3594                 return -1;
3595
3596         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3597
3598         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3599         memcpy(req.encap_request, encaped, ec_size);
3600
3601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3602
3603         HWRM_CHECK_RESULT();
3604         HWRM_UNLOCK();
3605
3606         return rc;
3607 }
3608
3609 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3610                                        struct rte_ether_addr *mac)
3611 {
3612         struct hwrm_func_qcfg_input req = {0};
3613         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3614         int rc;
3615
3616         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3617
3618         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3620
3621         HWRM_CHECK_RESULT();
3622
3623         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3624
3625         HWRM_UNLOCK();
3626
3627         return rc;
3628 }
3629
3630 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3631                             void *encaped, size_t ec_size)
3632 {
3633         int rc = 0;
3634         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3635         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3636
3637         if (ec_size > sizeof(req.encap_request))
3638                 return -1;
3639
3640         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3641
3642         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3643         memcpy(req.encap_request, encaped, ec_size);
3644
3645         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3646
3647         HWRM_CHECK_RESULT();
3648         HWRM_UNLOCK();
3649
3650         return rc;
3651 }
3652
3653 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3654                          struct rte_eth_stats *stats, uint8_t rx)
3655 {
3656         int rc = 0;
3657         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3658         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3659
3660         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3661
3662         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3663
3664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3665
3666         HWRM_CHECK_RESULT();
3667
3668         if (rx) {
3669                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3670                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3671                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3672                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3673                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3674                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3675                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3676                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3677         } else {
3678                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3679                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3680                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3681                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3682                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3683                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3684         }
3685
3686         HWRM_UNLOCK();
3687
3688         return rc;
3689 }
3690
3691 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3692 {
3693         struct hwrm_port_qstats_input req = {0};
3694         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3695         struct bnxt_pf_info *pf = &bp->pf;
3696         int rc;
3697
3698         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3699
3700         req.port_id = rte_cpu_to_le_16(pf->port_id);
3701         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3702         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3704
3705         HWRM_CHECK_RESULT();
3706         HWRM_UNLOCK();
3707
3708         return rc;
3709 }
3710
3711 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3712 {
3713         struct hwrm_port_clr_stats_input req = {0};
3714         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3715         struct bnxt_pf_info *pf = &bp->pf;
3716         int rc;
3717
3718         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3719         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3720             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3721                 return 0;
3722
3723         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3724
3725         req.port_id = rte_cpu_to_le_16(pf->port_id);
3726         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3727
3728         HWRM_CHECK_RESULT();
3729         HWRM_UNLOCK();
3730
3731         return rc;
3732 }
3733
3734 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3735 {
3736         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3737         struct hwrm_port_led_qcaps_input req = {0};
3738         int rc;
3739
3740         if (BNXT_VF(bp))
3741                 return 0;
3742
3743         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3744         req.port_id = bp->pf.port_id;
3745         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3746
3747         HWRM_CHECK_RESULT();
3748
3749         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3750                 unsigned int i;
3751
3752                 bp->num_leds = resp->num_leds;
3753                 memcpy(bp->leds, &resp->led0_id,
3754                         sizeof(bp->leds[0]) * bp->num_leds);
3755                 for (i = 0; i < bp->num_leds; i++) {
3756                         struct bnxt_led_info *led = &bp->leds[i];
3757
3758                         uint16_t caps = led->led_state_caps;
3759
3760                         if (!led->led_group_id ||
3761                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3762                                 bp->num_leds = 0;
3763                                 break;
3764                         }
3765                 }
3766         }
3767
3768         HWRM_UNLOCK();
3769
3770         return rc;
3771 }
3772
3773 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3774 {
3775         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3776         struct hwrm_port_led_cfg_input req = {0};
3777         struct bnxt_led_cfg *led_cfg;
3778         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3779         uint16_t duration = 0;
3780         int rc, i;
3781
3782         if (!bp->num_leds || BNXT_VF(bp))
3783                 return -EOPNOTSUPP;
3784
3785         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3786
3787         if (led_on) {
3788                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3789                 duration = rte_cpu_to_le_16(500);
3790         }
3791         req.port_id = bp->pf.port_id;
3792         req.num_leds = bp->num_leds;
3793         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3794         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3795                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3796                 led_cfg->led_id = bp->leds[i].led_id;
3797                 led_cfg->led_state = led_state;
3798                 led_cfg->led_blink_on = duration;
3799                 led_cfg->led_blink_off = duration;
3800                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3801         }
3802
3803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3804
3805         HWRM_CHECK_RESULT();
3806         HWRM_UNLOCK();
3807
3808         return rc;
3809 }
3810
3811 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3812                                uint32_t *length)
3813 {
3814         int rc;
3815         struct hwrm_nvm_get_dir_info_input req = {0};
3816         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3817
3818         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3819
3820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3821
3822         HWRM_CHECK_RESULT();
3823
3824         *entries = rte_le_to_cpu_32(resp->entries);
3825         *length = rte_le_to_cpu_32(resp->entry_length);
3826
3827         HWRM_UNLOCK();
3828         return rc;
3829 }
3830
3831 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3832 {
3833         int rc;
3834         uint32_t dir_entries;
3835         uint32_t entry_length;
3836         uint8_t *buf;
3837         size_t buflen;
3838         rte_iova_t dma_handle;
3839         struct hwrm_nvm_get_dir_entries_input req = {0};
3840         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3841
3842         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3843         if (rc != 0)
3844                 return rc;
3845
3846         *data++ = dir_entries;
3847         *data++ = entry_length;
3848         len -= 2;
3849         memset(data, 0xff, len);
3850
3851         buflen = dir_entries * entry_length;
3852         buf = rte_malloc("nvm_dir", buflen, 0);
3853         rte_mem_lock_page(buf);
3854         if (buf == NULL)
3855                 return -ENOMEM;
3856         dma_handle = rte_mem_virt2iova(buf);
3857         if (dma_handle == RTE_BAD_IOVA) {
3858                 PMD_DRV_LOG(ERR,
3859                         "unable to map response address to physical memory\n");
3860                 return -ENOMEM;
3861         }
3862         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3863         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3865
3866         if (rc == 0)
3867                 memcpy(data, buf, len > buflen ? buflen : len);
3868
3869         rte_free(buf);
3870         HWRM_CHECK_RESULT();
3871         HWRM_UNLOCK();
3872
3873         return rc;
3874 }
3875
3876 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3877                              uint32_t offset, uint32_t length,
3878                              uint8_t *data)
3879 {
3880         int rc;
3881         uint8_t *buf;
3882         rte_iova_t dma_handle;
3883         struct hwrm_nvm_read_input req = {0};
3884         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3885
3886         buf = rte_malloc("nvm_item", length, 0);
3887         rte_mem_lock_page(buf);
3888         if (!buf)
3889                 return -ENOMEM;
3890
3891         dma_handle = rte_mem_virt2iova(buf);
3892         if (dma_handle == RTE_BAD_IOVA) {
3893                 PMD_DRV_LOG(ERR,
3894                         "unable to map response address to physical memory\n");
3895                 return -ENOMEM;
3896         }
3897         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3898         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3899         req.dir_idx = rte_cpu_to_le_16(index);
3900         req.offset = rte_cpu_to_le_32(offset);
3901         req.len = rte_cpu_to_le_32(length);
3902         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3903         if (rc == 0)
3904                 memcpy(data, buf, length);
3905
3906         rte_free(buf);
3907         HWRM_CHECK_RESULT();
3908         HWRM_UNLOCK();
3909
3910         return rc;
3911 }
3912
3913 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3914 {
3915         int rc;
3916         struct hwrm_nvm_erase_dir_entry_input req = {0};
3917         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3918
3919         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3920         req.dir_idx = rte_cpu_to_le_16(index);
3921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3922         HWRM_CHECK_RESULT();
3923         HWRM_UNLOCK();
3924
3925         return rc;
3926 }
3927
3928
3929 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3930                           uint16_t dir_ordinal, uint16_t dir_ext,
3931                           uint16_t dir_attr, const uint8_t *data,
3932                           size_t data_len)
3933 {
3934         int rc;
3935         struct hwrm_nvm_write_input req = {0};
3936         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3937         rte_iova_t dma_handle;
3938         uint8_t *buf;
3939
3940         buf = rte_malloc("nvm_write", data_len, 0);
3941         rte_mem_lock_page(buf);
3942         if (!buf)
3943                 return -ENOMEM;
3944
3945         dma_handle = rte_mem_virt2iova(buf);
3946         if (dma_handle == RTE_BAD_IOVA) {
3947                 PMD_DRV_LOG(ERR,
3948                         "unable to map response address to physical memory\n");
3949                 return -ENOMEM;
3950         }
3951         memcpy(buf, data, data_len);
3952
3953         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3954
3955         req.dir_type = rte_cpu_to_le_16(dir_type);
3956         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3957         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3958         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3959         req.dir_data_length = rte_cpu_to_le_32(data_len);
3960         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3961
3962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3963
3964         rte_free(buf);
3965         HWRM_CHECK_RESULT();
3966         HWRM_UNLOCK();
3967
3968         return rc;
3969 }
3970
3971 static void
3972 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3973 {
3974         uint32_t *count = cbdata;
3975
3976         *count = *count + 1;
3977 }
3978
3979 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3980                                      struct bnxt_vnic_info *vnic __rte_unused)
3981 {
3982         return 0;
3983 }
3984
3985 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3986 {
3987         uint32_t count = 0;
3988
3989         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3990             &count, bnxt_vnic_count_hwrm_stub);
3991
3992         return count;
3993 }
3994
3995 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3996                                         uint16_t *vnic_ids)
3997 {
3998         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3999         struct hwrm_func_vf_vnic_ids_query_output *resp =
4000                                                 bp->hwrm_cmd_resp_addr;
4001         int rc;
4002
4003         /* First query all VNIC ids */
4004         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4005
4006         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4007         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4008         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
4009
4010         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4011                 HWRM_UNLOCK();
4012                 PMD_DRV_LOG(ERR,
4013                 "unable to map VNIC ID table address to physical memory\n");
4014                 return -ENOMEM;
4015         }
4016         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4017         HWRM_CHECK_RESULT();
4018         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4019
4020         HWRM_UNLOCK();
4021
4022         return rc;
4023 }
4024
4025 /*
4026  * This function queries the VNIC IDs  for a specified VF. It then calls
4027  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4028  * Then it calls the hwrm_cb function to program this new vnic configuration.
4029  */
4030 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4031         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4032         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4033 {
4034         struct bnxt_vnic_info vnic;
4035         int rc = 0;
4036         int i, num_vnic_ids;
4037         uint16_t *vnic_ids;
4038         size_t vnic_id_sz;
4039         size_t sz;
4040
4041         /* First query all VNIC ids */
4042         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4043         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4044                         RTE_CACHE_LINE_SIZE);
4045         if (vnic_ids == NULL)
4046                 return -ENOMEM;
4047
4048         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4049                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4050
4051         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4052
4053         if (num_vnic_ids < 0)
4054                 return num_vnic_ids;
4055
4056         /* Retrieve VNIC, update bd_stall then update */
4057
4058         for (i = 0; i < num_vnic_ids; i++) {
4059                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4060                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4061                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4062                 if (rc)
4063                         break;
4064                 if (vnic.mru <= 4)      /* Indicates unallocated */
4065                         continue;
4066
4067                 vnic_cb(&vnic, cbdata);
4068
4069                 rc = hwrm_cb(bp, &vnic);
4070                 if (rc)
4071                         break;
4072         }
4073
4074         rte_free(vnic_ids);
4075
4076         return rc;
4077 }
4078
4079 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4080                                               bool on)
4081 {
4082         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4083         struct hwrm_func_cfg_input req = {0};
4084         int rc;
4085
4086         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4087
4088         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4089         req.enables |= rte_cpu_to_le_32(
4090                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4091         req.vlan_antispoof_mode = on ?
4092                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4093                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4094         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4095
4096         HWRM_CHECK_RESULT();
4097         HWRM_UNLOCK();
4098
4099         return rc;
4100 }
4101
4102 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4103 {
4104         struct bnxt_vnic_info vnic;
4105         uint16_t *vnic_ids;
4106         size_t vnic_id_sz;
4107         int num_vnic_ids, i;
4108         size_t sz;
4109         int rc;
4110
4111         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4112         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4113                         RTE_CACHE_LINE_SIZE);
4114         if (vnic_ids == NULL)
4115                 return -ENOMEM;
4116
4117         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4118                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4119
4120         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4121         if (rc <= 0)
4122                 goto exit;
4123         num_vnic_ids = rc;
4124
4125         /*
4126          * Loop through to find the default VNIC ID.
4127          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4128          * by sending the hwrm_func_qcfg command to the firmware.
4129          */
4130         for (i = 0; i < num_vnic_ids; i++) {
4131                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4132                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4133                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4134                                         bp->pf.first_vf_id + vf);
4135                 if (rc)
4136                         goto exit;
4137                 if (vnic.func_default) {
4138                         rte_free(vnic_ids);
4139                         return vnic.fw_vnic_id;
4140                 }
4141         }
4142         /* Could not find a default VNIC. */
4143         PMD_DRV_LOG(ERR, "No default VNIC\n");
4144 exit:
4145         rte_free(vnic_ids);
4146         return rc;
4147 }
4148
4149 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4150                          uint16_t dst_id,
4151                          struct bnxt_filter_info *filter)
4152 {
4153         int rc = 0;
4154         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4155         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4156         uint32_t enables = 0;
4157
4158         if (filter->fw_em_filter_id != UINT64_MAX)
4159                 bnxt_hwrm_clear_em_filter(bp, filter);
4160
4161         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4162
4163         req.flags = rte_cpu_to_le_32(filter->flags);
4164
4165         enables = filter->enables |
4166               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4167         req.dst_id = rte_cpu_to_le_16(dst_id);
4168
4169         if (filter->ip_addr_type) {
4170                 req.ip_addr_type = filter->ip_addr_type;
4171                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4172         }
4173         if (enables &
4174             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4175                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4176         if (enables &
4177             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4178                 memcpy(req.src_macaddr, filter->src_macaddr,
4179                        RTE_ETHER_ADDR_LEN);
4180         if (enables &
4181             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4182                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4183                        RTE_ETHER_ADDR_LEN);
4184         if (enables &
4185             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4186                 req.ovlan_vid = filter->l2_ovlan;
4187         if (enables &
4188             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4189                 req.ivlan_vid = filter->l2_ivlan;
4190         if (enables &
4191             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4192                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4193         if (enables &
4194             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4195                 req.ip_protocol = filter->ip_protocol;
4196         if (enables &
4197             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4198                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4199         if (enables &
4200             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4201                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4202         if (enables &
4203             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4204                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4205         if (enables &
4206             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4207                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4208         if (enables &
4209             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4210                 req.mirror_vnic_id = filter->mirror_vnic_id;
4211
4212         req.enables = rte_cpu_to_le_32(enables);
4213
4214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4215
4216         HWRM_CHECK_RESULT();
4217
4218         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4219         HWRM_UNLOCK();
4220
4221         return rc;
4222 }
4223
4224 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4225 {
4226         int rc = 0;
4227         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4228         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4229
4230         if (filter->fw_em_filter_id == UINT64_MAX)
4231                 return 0;
4232
4233         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4234
4235         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4236
4237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4238
4239         HWRM_CHECK_RESULT();
4240         HWRM_UNLOCK();
4241
4242         filter->fw_em_filter_id = UINT64_MAX;
4243         filter->fw_l2_filter_id = UINT64_MAX;
4244
4245         return 0;
4246 }
4247
4248 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4249                          uint16_t dst_id,
4250                          struct bnxt_filter_info *filter)
4251 {
4252         int rc = 0;
4253         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4254         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4255                                                 bp->hwrm_cmd_resp_addr;
4256         uint32_t enables = 0;
4257
4258         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4259                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4260
4261         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4262
4263         req.flags = rte_cpu_to_le_32(filter->flags);
4264
4265         enables = filter->enables |
4266               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4267         req.dst_id = rte_cpu_to_le_16(dst_id);
4268
4269         if (filter->ip_addr_type) {
4270                 req.ip_addr_type = filter->ip_addr_type;
4271                 enables |=
4272                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4273         }
4274         if (enables &
4275             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4276                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4277         if (enables &
4278             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4279                 memcpy(req.src_macaddr, filter->src_macaddr,
4280                        RTE_ETHER_ADDR_LEN);
4281         if (enables &
4282             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4283                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4284         if (enables &
4285             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4286                 req.ip_protocol = filter->ip_protocol;
4287         if (enables &
4288             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4289                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4290         if (enables &
4291             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4292                 req.src_ipaddr_mask[0] =
4293                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4294         if (enables &
4295             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4296                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4297         if (enables &
4298             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4299                 req.dst_ipaddr_mask[0] =
4300                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4301         if (enables &
4302             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4303                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4304         if (enables &
4305             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4306                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4307         if (enables &
4308             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4309                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4310         if (enables &
4311             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4312                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4313         if (enables &
4314             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4315                 req.mirror_vnic_id = filter->mirror_vnic_id;
4316
4317         req.enables = rte_cpu_to_le_32(enables);
4318
4319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4320
4321         HWRM_CHECK_RESULT();
4322
4323         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4324         HWRM_UNLOCK();
4325
4326         return rc;
4327 }
4328
4329 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4330                                 struct bnxt_filter_info *filter)
4331 {
4332         int rc = 0;
4333         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4334         struct hwrm_cfa_ntuple_filter_free_output *resp =
4335                                                 bp->hwrm_cmd_resp_addr;
4336
4337         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4338                 return 0;
4339
4340         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4341
4342         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4343
4344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4345
4346         HWRM_CHECK_RESULT();
4347         HWRM_UNLOCK();
4348
4349         filter->fw_ntuple_filter_id = UINT64_MAX;
4350
4351         return 0;
4352 }
4353
4354 static int
4355 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4356 {
4357         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4358         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4359         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4360         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4361         uint16_t *ring_tbl = vnic->rss_table;
4362         int nr_ctxs = vnic->num_lb_ctxts;
4363         int max_rings = bp->rx_nr_rings;
4364         int i, j, k, cnt;
4365         int rc = 0;
4366
4367         for (i = 0, k = 0; i < nr_ctxs; i++) {
4368                 struct bnxt_rx_ring_info *rxr;
4369                 struct bnxt_cp_ring_info *cpr;
4370
4371                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4372
4373                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4374                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4375                 req.hash_mode_flags = vnic->hash_mode;
4376
4377                 req.ring_grp_tbl_addr =
4378                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4379                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4380                                      2 * sizeof(*ring_tbl));
4381                 req.hash_key_tbl_addr =
4382                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4383
4384                 req.ring_table_pair_index = i;
4385                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4386
4387                 for (j = 0; j < 64; j++) {
4388                         uint16_t ring_id;
4389
4390                         /* Find next active ring. */
4391                         for (cnt = 0; cnt < max_rings; cnt++) {
4392                                 if (rx_queue_state[k] !=
4393                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4394                                         break;
4395                                 if (++k == max_rings)
4396                                         k = 0;
4397                         }
4398
4399                         /* Return if no rings are active. */
4400                         if (cnt == max_rings) {
4401                                 HWRM_UNLOCK();
4402                                 return 0;
4403                         }
4404
4405                         /* Add rx/cp ring pair to RSS table. */
4406                         rxr = rxqs[k]->rx_ring;
4407                         cpr = rxqs[k]->cp_ring;
4408
4409                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4410                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4411                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4412                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4413
4414                         if (++k == max_rings)
4415                                 k = 0;
4416                 }
4417                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4418                                             BNXT_USE_CHIMP_MB);
4419
4420                 HWRM_CHECK_RESULT();
4421                 HWRM_UNLOCK();
4422         }
4423
4424         return rc;
4425 }
4426
4427 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4428 {
4429         unsigned int rss_idx, fw_idx, i;
4430
4431         if (!(vnic->rss_table && vnic->hash_type))
4432                 return 0;
4433
4434         if (BNXT_CHIP_THOR(bp))
4435                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4436
4437         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4438                 return 0;
4439
4440         if (vnic->rss_table && vnic->hash_type) {
4441                 /*
4442                  * Fill the RSS hash & redirection table with
4443                  * ring group ids for all VNICs
4444                  */
4445                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4446                         rss_idx++, fw_idx++) {
4447                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4448                                 fw_idx %= bp->rx_cp_nr_rings;
4449                                 if (vnic->fw_grp_ids[fw_idx] !=
4450                                     INVALID_HW_RING_ID)
4451                                         break;
4452                                 fw_idx++;
4453                         }
4454                         if (i == bp->rx_cp_nr_rings)
4455                                 return 0;
4456                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4457                 }
4458                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4459         }
4460
4461         return 0;
4462 }
4463
4464 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4465         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4466 {
4467         uint16_t flags;
4468
4469         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4470
4471         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4472         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4473
4474         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4475         req->num_cmpl_dma_aggr_during_int =
4476                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4477
4478         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4479
4480         /* min timer set to 1/2 of interrupt timer */
4481         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4482
4483         /* buf timer set to 1/4 of interrupt timer */
4484         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4485
4486         req->cmpl_aggr_dma_tmr_during_int =
4487                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4488
4489         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4490                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4491         req->flags = rte_cpu_to_le_16(flags);
4492 }
4493
4494 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4495                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4496 {
4497         struct hwrm_ring_aggint_qcaps_input req = {0};
4498         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4499         uint32_t enables;
4500         uint16_t flags;
4501         int rc;
4502
4503         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4504         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4505         HWRM_CHECK_RESULT();
4506
4507         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4508         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4509
4510         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4511                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4512         agg_req->flags = rte_cpu_to_le_16(flags);
4513         enables =
4514          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4515          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4516         agg_req->enables = rte_cpu_to_le_32(enables);
4517
4518         HWRM_UNLOCK();
4519         return rc;
4520 }
4521
4522 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4523                         struct bnxt_coal *coal, uint16_t ring_id)
4524 {
4525         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4526         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4527                                                 bp->hwrm_cmd_resp_addr;
4528         int rc;
4529
4530         /* Set ring coalesce parameters only for 100G NICs */
4531         if (BNXT_CHIP_THOR(bp)) {
4532                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4533                         return -1;
4534         } else if (bnxt_stratus_device(bp)) {
4535                 bnxt_hwrm_set_coal_params(coal, &req);
4536         } else {
4537                 return 0;
4538         }
4539
4540         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4541         req.ring_id = rte_cpu_to_le_16(ring_id);
4542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4543         HWRM_CHECK_RESULT();
4544         HWRM_UNLOCK();
4545         return 0;
4546 }
4547
4548 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4549 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4550 {
4551         struct hwrm_func_backing_store_qcaps_input req = {0};
4552         struct hwrm_func_backing_store_qcaps_output *resp =
4553                 bp->hwrm_cmd_resp_addr;
4554         struct bnxt_ctx_pg_info *ctx_pg;
4555         struct bnxt_ctx_mem_info *ctx;
4556         int total_alloc_len;
4557         int rc, i;
4558
4559         if (!BNXT_CHIP_THOR(bp) ||
4560             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4561             BNXT_VF(bp) ||
4562             bp->ctx)
4563                 return 0;
4564
4565         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4567         HWRM_CHECK_RESULT_SILENT();
4568
4569         total_alloc_len = sizeof(*ctx);
4570         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4571                           RTE_CACHE_LINE_SIZE);
4572         if (!ctx) {
4573                 rc = -ENOMEM;
4574                 goto ctx_err;
4575         }
4576
4577         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4578                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4579                             RTE_CACHE_LINE_SIZE);
4580         if (!ctx_pg) {
4581                 rc = -ENOMEM;
4582                 goto ctx_err;
4583         }
4584         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4585                 ctx->tqm_mem[i] = ctx_pg;
4586
4587         bp->ctx = ctx;
4588         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4589         ctx->qp_min_qp1_entries =
4590                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4591         ctx->qp_max_l2_entries =
4592                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4593         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4594         ctx->srq_max_l2_entries =
4595                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4596         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4597         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4598         ctx->cq_max_l2_entries =
4599                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4600         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4601         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4602         ctx->vnic_max_vnic_entries =
4603                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4604         ctx->vnic_max_ring_table_entries =
4605                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4606         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4607         ctx->stat_max_entries =
4608                 rte_le_to_cpu_32(resp->stat_max_entries);
4609         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4610         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4611         ctx->tqm_min_entries_per_ring =
4612                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4613         ctx->tqm_max_entries_per_ring =
4614                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4615         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4616         if (!ctx->tqm_entries_multiple)
4617                 ctx->tqm_entries_multiple = 1;
4618         ctx->mrav_max_entries =
4619                 rte_le_to_cpu_32(resp->mrav_max_entries);
4620         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4621         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4622         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4623 ctx_err:
4624         HWRM_UNLOCK();
4625         return rc;
4626 }
4627
4628 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4629 {
4630         struct hwrm_func_backing_store_cfg_input req = {0};
4631         struct hwrm_func_backing_store_cfg_output *resp =
4632                 bp->hwrm_cmd_resp_addr;
4633         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4634         struct bnxt_ctx_pg_info *ctx_pg;
4635         uint32_t *num_entries;
4636         uint64_t *pg_dir;
4637         uint8_t *pg_attr;
4638         uint32_t ena;
4639         int i, rc;
4640
4641         if (!ctx)
4642                 return 0;
4643
4644         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4645         req.enables = rte_cpu_to_le_32(enables);
4646
4647         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4648                 ctx_pg = &ctx->qp_mem;
4649                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4650                 req.qp_num_qp1_entries =
4651                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4652                 req.qp_num_l2_entries =
4653                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4654                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4655                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4656                                       &req.qpc_pg_size_qpc_lvl,
4657                                       &req.qpc_page_dir);
4658         }
4659
4660         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4661                 ctx_pg = &ctx->srq_mem;
4662                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4663                 req.srq_num_l2_entries =
4664                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4665                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4666                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4667                                       &req.srq_pg_size_srq_lvl,
4668                                       &req.srq_page_dir);
4669         }
4670
4671         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4672                 ctx_pg = &ctx->cq_mem;
4673                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4674                 req.cq_num_l2_entries =
4675                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4676                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4677                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4678                                       &req.cq_pg_size_cq_lvl,
4679                                       &req.cq_page_dir);
4680         }
4681
4682         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4683                 ctx_pg = &ctx->vnic_mem;
4684                 req.vnic_num_vnic_entries =
4685                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4686                 req.vnic_num_ring_table_entries =
4687                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4688                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4689                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4690                                       &req.vnic_pg_size_vnic_lvl,
4691                                       &req.vnic_page_dir);
4692         }
4693
4694         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4695                 ctx_pg = &ctx->stat_mem;
4696                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4697                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4698                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4699                                       &req.stat_pg_size_stat_lvl,
4700                                       &req.stat_page_dir);
4701         }
4702
4703         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4704         num_entries = &req.tqm_sp_num_entries;
4705         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4706         pg_dir = &req.tqm_sp_page_dir;
4707         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4708         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4709                 if (!(enables & ena))
4710                         continue;
4711
4712                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4713
4714                 ctx_pg = ctx->tqm_mem[i];
4715                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4716                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4717         }
4718
4719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4720         HWRM_CHECK_RESULT();
4721         HWRM_UNLOCK();
4722
4723         return rc;
4724 }
4725
4726 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4727 {
4728         struct hwrm_port_qstats_ext_input req = {0};
4729         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4730         struct bnxt_pf_info *pf = &bp->pf;
4731         int rc;
4732
4733         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4734               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4735                 return 0;
4736
4737         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4738
4739         req.port_id = rte_cpu_to_le_16(pf->port_id);
4740         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4741                 req.tx_stat_host_addr =
4742                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4743                 req.tx_stat_size =
4744                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4745         }
4746         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4747                 req.rx_stat_host_addr =
4748                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4749                 req.rx_stat_size =
4750                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4751         }
4752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4753
4754         if (rc) {
4755                 bp->fw_rx_port_stats_ext_size = 0;
4756                 bp->fw_tx_port_stats_ext_size = 0;
4757         } else {
4758                 bp->fw_rx_port_stats_ext_size =
4759                         rte_le_to_cpu_16(resp->rx_stat_size);
4760                 bp->fw_tx_port_stats_ext_size =
4761                         rte_le_to_cpu_16(resp->tx_stat_size);
4762         }
4763
4764         HWRM_CHECK_RESULT();
4765         HWRM_UNLOCK();
4766
4767         return rc;
4768 }
4769
4770 int
4771 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4772 {
4773         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4774         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4775                 bp->hwrm_cmd_resp_addr;
4776         int rc = 0;
4777
4778         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4779         req.tunnel_type = type;
4780         req.dest_fid = bp->fw_fid;
4781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4782         HWRM_CHECK_RESULT();
4783
4784         HWRM_UNLOCK();
4785
4786         return rc;
4787 }
4788
4789 int
4790 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4791 {
4792         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4793         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4794                 bp->hwrm_cmd_resp_addr;
4795         int rc = 0;
4796
4797         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4798         req.tunnel_type = type;
4799         req.dest_fid = bp->fw_fid;
4800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4801         HWRM_CHECK_RESULT();
4802
4803         HWRM_UNLOCK();
4804
4805         return rc;
4806 }
4807
4808 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4809 {
4810         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4811         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4812                 bp->hwrm_cmd_resp_addr;
4813         int rc = 0;
4814
4815         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4816         req.src_fid = bp->fw_fid;
4817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4818         HWRM_CHECK_RESULT();
4819
4820         if (type)
4821                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4822
4823         HWRM_UNLOCK();
4824
4825         return rc;
4826 }
4827
4828 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4829                                    uint16_t *dst_fid)
4830 {
4831         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4832         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4833                 bp->hwrm_cmd_resp_addr;
4834         int rc = 0;
4835
4836         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4837         req.src_fid = bp->fw_fid;
4838         req.tunnel_type = tun_type;
4839         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4840         HWRM_CHECK_RESULT();
4841
4842         if (dst_fid)
4843                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4844
4845         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4846
4847         HWRM_UNLOCK();
4848
4849         return rc;
4850 }
4851
4852 int bnxt_hwrm_set_mac(struct bnxt *bp)
4853 {
4854         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4855         struct hwrm_func_vf_cfg_input req = {0};
4856         int rc = 0;
4857
4858         if (!BNXT_VF(bp))
4859                 return 0;
4860
4861         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4862
4863         req.enables =
4864                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4865         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4866
4867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4868
4869         HWRM_CHECK_RESULT();
4870
4871         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4872         HWRM_UNLOCK();
4873
4874         return rc;
4875 }
4876
4877 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4878 {
4879         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4880         struct hwrm_func_drv_if_change_input req = {0};
4881         uint32_t flags;
4882         int rc;
4883
4884         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4885                 return 0;
4886
4887         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4888          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4889          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4890          */
4891         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4892                 return 0;
4893
4894         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4895
4896         if (up)
4897                 req.flags =
4898                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4899
4900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4901
4902         HWRM_CHECK_RESULT();
4903         flags = rte_le_to_cpu_32(resp->flags);
4904         HWRM_UNLOCK();
4905
4906         if (!up)
4907                 return 0;
4908
4909         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4910                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4911                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4912         }
4913
4914         return 0;
4915 }
4916
4917 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4918 {
4919         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4920         struct bnxt_error_recovery_info *info = bp->recovery_info;
4921         struct hwrm_error_recovery_qcfg_input req = {0};
4922         uint32_t flags = 0;
4923         unsigned int i;
4924         int rc;
4925
4926         /* Older FW does not have error recovery support */
4927         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4928                 return 0;
4929
4930         if (!info) {
4931                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4932                                    sizeof(*info), 0);
4933                 bp->recovery_info = info;
4934                 if (info == NULL)
4935                         return -ENOMEM;
4936         } else {
4937                 memset(info, 0, sizeof(*info));
4938         }
4939
4940         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4941
4942         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4943
4944         HWRM_CHECK_RESULT();
4945
4946         flags = rte_le_to_cpu_32(resp->flags);
4947         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4948                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4949         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4950                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4951
4952         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4953             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4954                 rc = -EINVAL;
4955                 goto err;
4956         }
4957
4958         /* FW returned values are in units of 100msec */
4959         info->driver_polling_freq =
4960                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4961         info->master_func_wait_period =
4962                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4963         info->normal_func_wait_period =
4964                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4965         info->master_func_wait_period_after_reset =
4966                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4967         info->max_bailout_time_after_reset =
4968                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4969         info->status_regs[BNXT_FW_STATUS_REG] =
4970                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4971         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4972                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4973         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4974                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4975         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4976                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4977         info->reg_array_cnt =
4978                 rte_le_to_cpu_32(resp->reg_array_cnt);
4979
4980         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4981                 rc = -EINVAL;
4982                 goto err;
4983         }
4984
4985         for (i = 0; i < info->reg_array_cnt; i++) {
4986                 info->reset_reg[i] =
4987                         rte_le_to_cpu_32(resp->reset_reg[i]);
4988                 info->reset_reg_val[i] =
4989                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4990                 info->delay_after_reset[i] =
4991                         resp->delay_after_reset[i];
4992         }
4993 err:
4994         HWRM_UNLOCK();
4995
4996         /* Map the FW status registers */
4997         if (!rc)
4998                 rc = bnxt_map_fw_health_status_regs(bp);
4999
5000         if (rc) {
5001                 rte_free(bp->recovery_info);
5002                 bp->recovery_info = NULL;
5003         }
5004         return rc;
5005 }
5006
5007 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5008 {
5009         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5010         struct hwrm_fw_reset_input req = {0};
5011         int rc;
5012
5013         if (!BNXT_PF(bp))
5014                 return -EOPNOTSUPP;
5015
5016         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5017
5018         req.embedded_proc_type =
5019                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5020         req.selfrst_status =
5021                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5022         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5023
5024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5025                                     BNXT_USE_KONG(bp));
5026
5027         HWRM_CHECK_RESULT();
5028         HWRM_UNLOCK();
5029
5030         return rc;
5031 }
5032
5033 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5034 {
5035         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5036         struct hwrm_port_ts_query_input req = {0};
5037         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5038         uint32_t flags = 0;
5039         int rc;
5040
5041         if (!ptp)
5042                 return 0;
5043
5044         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5045
5046         switch (path) {
5047         case BNXT_PTP_FLAGS_PATH_TX:
5048                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5049                 break;
5050         case BNXT_PTP_FLAGS_PATH_RX:
5051                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5052                 break;
5053         case BNXT_PTP_FLAGS_CURRENT_TIME:
5054                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5055                 break;
5056         }
5057
5058         req.flags = rte_cpu_to_le_32(flags);
5059         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5060
5061         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5062
5063         HWRM_CHECK_RESULT();
5064
5065         if (timestamp) {
5066                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5067                 *timestamp |=
5068                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5069         }
5070         HWRM_UNLOCK();
5071
5072         return rc;
5073 }
5074
5075 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5076 {
5077         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5078                                         bp->hwrm_cmd_resp_addr;
5079         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5080         uint32_t flags = 0;
5081         int rc = 0;
5082
5083         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5084                 return rc;
5085
5086         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5087                 PMD_DRV_LOG(DEBUG,
5088                             "Not a PF or trusted VF. Command not supported\n");
5089                 return 0;
5090         }
5091
5092         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5094
5095         HWRM_CHECK_RESULT();
5096         flags = rte_le_to_cpu_32(resp->flags);
5097         HWRM_UNLOCK();
5098
5099         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5100                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5101                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5102         }
5103
5104         return rc;
5105 }