drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 223                         rc = -ENOSPC; \
 224                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 225                         rc = -EINVAL; \
 226                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 227                         rc = -ENOTSUP; \
 228                 else if (rc > 0) \
 229                         rc = -EIO; \
 230                 return rc; \
 231         } \
 232         if (resp->error_code) { \
 233                 rc = rte_le_to_cpu_16(resp->error_code); \
 234                 if (resp->resp_len >= 16) { \
 235                         struct hwrm_err_output *tmp_hwrm_err_op = \
 236                                                 (void *)resp; \
 237                         PMD_DRV_LOG(ERR, \
 238                                 "error %d:%d:%08x:%04x\n", \
 239                                 rc, tmp_hwrm_err_op->cmd_err, \
 240                                 rte_le_to_cpu_32(\
 241                                         tmp_hwrm_err_op->opaque_0), \
 242                                 rte_le_to_cpu_16(\
 243                                         tmp_hwrm_err_op->opaque_1)); \
 244                 } else { \
 245                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 246                 } \
 247                 rte_spinlock_unlock(&bp->hwrm_lock); \
 248                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 249                         rc = -EACCES; \
 250                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 251                         rc = -ENOSPC; \
 252                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 253                         rc = -EINVAL; \
 254                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 255                         rc = -ENOTSUP; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 268         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 269
 270         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 272         req.mask = 0;
 273
 274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 275
 276         HWRM_CHECK_RESULT();
 277         HWRM_UNLOCK();
 278
 279         return rc;
 280 }
 281
 282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 283                                  struct bnxt_vnic_info *vnic,
 284                                  uint16_t vlan_count,
 285                                  struct bnxt_vlan_table_entry *vlan_table)
 286 {
 287         int rc = 0;
 288         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 289         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 290         uint32_t mask = 0;
 291
 292         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 293                 return rc;
 294
 295         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 297
 298         /* FIXME add multicast flag, when multicast adding options is supported
 299          * by ethtool.
 300          */
 301         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 302                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 303         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 304                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 305         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 306                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 307         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 308                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 309         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 310                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 311         if (vnic->mc_addr_cnt) {
 312                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 313                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 314                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 315         }
 316         if (vlan_table) {
 317                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 318                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 319                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 320                          rte_mem_virt2iova(vlan_table));
 321                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 322         }
 323         req.mask = rte_cpu_to_le_32(mask);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 326
 327         HWRM_CHECK_RESULT();
 328         HWRM_UNLOCK();
 329
 330         return rc;
 331 }
 332
 333 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 334                         uint16_t vlan_count,
 335                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 336 {
 337         int rc = 0;
 338         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 339         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 340                                                 bp->hwrm_cmd_resp_addr;
 341
 342         /*
 343          * Older HWRM versions did not support this command, and the set_rx_mask
 344          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 345          * removed from set_rx_mask call, and this command was added.
 346          *
 347          * This command is also present from 1.7.8.11 and higher,
 348          * as well as 1.7.8.0
 349          */
 350         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 351                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 352                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 353                                         (11)))
 354                                 return 0;
 355                 }
 356         }
 357         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 358         req.fid = rte_cpu_to_le_16(fid);
 359
 360         req.vlan_tag_mask_tbl_addr =
 361                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 362         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 363
 364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 365
 366         HWRM_CHECK_RESULT();
 367         HWRM_UNLOCK();
 368
 369         return rc;
 370 }
 371
 372 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 373                            struct bnxt_filter_info *filter)
 374 {
 375         int rc = 0;
 376         struct bnxt_filter_info *l2_filter = filter;
 377         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 378         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 379
 380         if (filter->fw_l2_filter_id == UINT64_MAX)
 381                 return 0;
 382
 383         if (filter->matching_l2_fltr_ptr)
 384                 l2_filter = filter->matching_l2_fltr_ptr;
 385
 386         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 387                     filter, l2_filter, l2_filter->l2_ref_cnt);
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 l2_filter->l2_ref_cnt--;
 391
 392         if (l2_filter->l2_ref_cnt > 0)
 393                 return 0;
 394
 395         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 396
 397         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 398
 399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 400
 401         HWRM_CHECK_RESULT();
 402         HWRM_UNLOCK();
 403
 404         filter->fw_l2_filter_id = UINT64_MAX;
 405
 406         return 0;
 407 }
 408
 409 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 410                          uint16_t dst_id,
 411                          struct bnxt_filter_info *filter)
 412 {
 413         int rc = 0;
 414         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 415         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 416         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 417         const struct rte_eth_vmdq_rx_conf *conf =
 418                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 419         uint32_t enables = 0;
 420         uint16_t j = dst_id - 1;
 421
 422         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 423         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 424             conf->pool_map[j].pools & (1UL << j)) {
 425                 PMD_DRV_LOG(DEBUG,
 426                         "Add vlan %u to vmdq pool %u\n",
 427                         conf->pool_map[j].vlan_id, j);
 428
 429                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 430                 filter->enables |=
 431                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 432                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 433         }
 434
 435         if (filter->fw_l2_filter_id != UINT64_MAX)
 436                 bnxt_hwrm_clear_l2_filter(bp, filter);
 437
 438         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 439
 440         req.flags = rte_cpu_to_le_32(filter->flags);
 441
 442         enables = filter->enables |
 443               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 444         req.dst_id = rte_cpu_to_le_16(dst_id);
 445
 446         if (enables &
 447             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 448                 memcpy(req.l2_addr, filter->l2_addr,
 449                        RTE_ETHER_ADDR_LEN);
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 452                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 453                        RTE_ETHER_ADDR_LEN);
 454         if (enables &
 455             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 456                 req.l2_ovlan = filter->l2_ovlan;
 457         if (enables &
 458             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 459                 req.l2_ivlan = filter->l2_ivlan;
 460         if (enables &
 461             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 462                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 463         if (enables &
 464             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 465                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 466         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 467                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 468         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 469                 req.src_type = filter->src_type;
 470         if (filter->pri_hint) {
 471                 req.pri_hint = filter->pri_hint;
 472                 req.l2_filter_id_hint =
 473                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 474         }
 475
 476         req.enables = rte_cpu_to_le_32(enables);
 477
 478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 479
 480         HWRM_CHECK_RESULT();
 481
 482         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 483         HWRM_UNLOCK();
 484
 485         return rc;
 486 }
 487
 488 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 489 {
 490         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 491         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 492         uint32_t flags = 0;
 493         int rc;
 494
 495         if (!ptp)
 496                 return 0;
 497
 498         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 499
 500         if (ptp->rx_filter)
 501                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 502         else
 503                 flags |=
 504                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 505         if (ptp->tx_tstamp_en)
 506                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 507         else
 508                 flags |=
 509                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 510         req.flags = rte_cpu_to_le_32(flags);
 511         req.enables = rte_cpu_to_le_32
 512                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 513         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 514
 515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 516         HWRM_UNLOCK();
 517
 518         return rc;
 519 }
 520
 521 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 522 {
 523         int rc = 0;
 524         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 525         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 526         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 527
 528 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 529         if (ptp)
 530                 return 0;
 531
 532         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 533
 534         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 535
 536         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 537
 538         HWRM_CHECK_RESULT();
 539
 540         if (!BNXT_CHIP_THOR(bp) &&
 541             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 542                 return 0;
 543
 544         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 545                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 546
 547         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 548         if (!ptp)
 549                 return -ENOMEM;
 550
 551         if (!BNXT_CHIP_THOR(bp)) {
 552                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 554                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 555                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 556                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 557                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 558                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 559                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 560                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 561                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 562                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 563                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 564                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 565                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 566                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 567                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 568                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 569                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 570         }
 571
 572         ptp->bp = bp;
 573         bp->ptp_cfg = ptp;
 574
 575         return 0;
 576 }
 577
 578 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 579 {
 580         int rc = 0;
 581         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 582         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 583         uint16_t new_max_vfs;
 584         uint32_t flags;
 585         int i;
 586
 587         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 588
 589         req.fid = rte_cpu_to_le_16(0xffff);
 590
 591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 592
 593         HWRM_CHECK_RESULT();
 594
 595         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 596         flags = rte_le_to_cpu_32(resp->flags);
 597         if (BNXT_PF(bp)) {
 598                 bp->pf.port_id = resp->port_id;
 599                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 600                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 601                 new_max_vfs = bp->pdev->max_vfs;
 602                 if (new_max_vfs != bp->pf.max_vfs) {
 603                         if (bp->pf.vf_info)
 604                                 rte_free(bp->pf.vf_info);
 605                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 606                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 607                         bp->pf.max_vfs = new_max_vfs;
 608                         for (i = 0; i < new_max_vfs; i++) {
 609                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 610                                 bp->pf.vf_info[i].vlan_table =
 611                                         rte_zmalloc("VF VLAN table",
 612                                                     getpagesize(),
 613                                                     getpagesize());
 614                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 615                                         PMD_DRV_LOG(ERR,
 616                                         "Fail to alloc VLAN table for VF %d\n",
 617                                         i);
 618                                 else
 619                                         rte_mem_lock_page(
 620                                                 bp->pf.vf_info[i].vlan_table);
 621                                 bp->pf.vf_info[i].vlan_as_table =
 622                                         rte_zmalloc("VF VLAN AS table",
 623                                                     getpagesize(),
 624                                                     getpagesize());
 625                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 626                                         PMD_DRV_LOG(ERR,
 627                                         "Alloc VLAN AS table for VF %d fail\n",
 628                                         i);
 629                                 else
 630                                         rte_mem_lock_page(
 631                                                bp->pf.vf_info[i].vlan_as_table);
 632                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 633                         }
 634                 }
 635         }
 636
 637         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 638         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 639         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 640         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 641         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 642         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 643         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 644         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 645         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 646         if (!BNXT_CHIP_THOR(bp))
 647                 bp->max_l2_ctx += bp->max_rx_em_flows;
 648         /* TODO: For now, do not support VMDq/RFS on VFs. */
 649         if (BNXT_PF(bp)) {
 650                 if (bp->pf.max_vfs)
 651                         bp->max_vnics = 1;
 652                 else
 653                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 654         } else {
 655                 bp->max_vnics = 1;
 656         }
 657         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 658         if (BNXT_PF(bp)) {
 659                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 660                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 661                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 662                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 663                         HWRM_UNLOCK();
 664                         bnxt_hwrm_ptp_qcfg(bp);
 665                 }
 666         }
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 669                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 672                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 673                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 674         } else {
 675                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 676         }
 677
 678         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 679                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 680         else
 681                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 682
 683         HWRM_UNLOCK();
 684
 685         return rc;
 686 }
 687
 688 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 689 {
 690         int rc;
 691
 692         rc = __bnxt_hwrm_func_qcaps(bp);
 693         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 694                 rc = bnxt_alloc_ctx_mem(bp);
 695                 if (rc)
 696                         return rc;
 697
 698                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 699                 if (!rc)
 700                         bp->flags |= BNXT_FLAG_NEW_RM;
 701         }
 702
 703         return rc;
 704 }
 705
 706 int bnxt_hwrm_func_reset(struct bnxt *bp)
 707 {
 708         int rc = 0;
 709         struct hwrm_func_reset_input req = {.req_type = 0 };
 710         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 711
 712         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 713
 714         req.enables = rte_cpu_to_le_32(0);
 715
 716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 717
 718         HWRM_CHECK_RESULT();
 719         HWRM_UNLOCK();
 720
 721         return rc;
 722 }
 723
 724 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 725 {
 726         int rc;
 727         uint32_t flags = 0;
 728         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 729         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 730
 731         if (bp->flags & BNXT_FLAG_REGISTERED)
 732                 return 0;
 733
 734         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 735         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 736                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 737
 738         /* PFs and trusted VFs should indicate the support of the
 739          * Master capability on non Stingray platform
 740          */
 741         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 742                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 743
 744         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 745         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 746                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 747         req.ver_maj = RTE_VER_YEAR;
 748         req.ver_min = RTE_VER_MONTH;
 749         req.ver_upd = RTE_VER_MINOR;
 750
 751         if (BNXT_PF(bp)) {
 752                 req.enables |= rte_cpu_to_le_32(
 753                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 754                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 755                        RTE_MIN(sizeof(req.vf_req_fwd),
 756                                sizeof(bp->pf.vf_req_fwd)));
 757
 758                 /*
 759                  * PF can sniff HWRM API issued by VF. This can be set up by
 760                  * linux driver and inherited by the DPDK PF driver. Clear
 761                  * this HWRM sniffer list in FW because DPDK PF driver does
 762                  * not support this.
 763                  */
 764                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 765         }
 766
 767         req.flags = rte_cpu_to_le_32(flags);
 768
 769         req.async_event_fwd[0] |=
 770                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 771                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 772                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 773                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 774                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 775         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 776                 req.async_event_fwd[0] |=
 777                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 778         req.async_event_fwd[1] |=
 779                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 780                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 781
 782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 783
 784         HWRM_CHECK_RESULT();
 785
 786         flags = rte_le_to_cpu_32(resp->flags);
 787         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 788                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 789
 790         HWRM_UNLOCK();
 791
 792         bp->flags |= BNXT_FLAG_REGISTERED;
 793
 794         return rc;
 795 }
 796
 797 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 798 {
 799         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 800                 return 0;
 801
 802         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 803 }
 804
 805 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 806 {
 807         int rc;
 808         uint32_t flags = 0;
 809         uint32_t enables;
 810         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 811         struct hwrm_func_vf_cfg_input req = {0};
 812
 813         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 814
 815         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 816                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 817                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 818                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 819                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 820
 821         if (BNXT_HAS_RING_GRPS(bp)) {
 822                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 823                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 824         }
 825
 826         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 827         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 828                                             AGG_RING_MULTIPLIER);
 829         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 830                                              bp->tx_nr_rings +
 831                                              BNXT_NUM_ASYNC_CPR(bp));
 832         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 833                                               bp->tx_nr_rings +
 834                                               BNXT_NUM_ASYNC_CPR(bp));
 835         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 836         if (bp->vf_resv_strategy ==
 837             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 838                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 839                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 840                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 841                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 842                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 843                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 844         }
 845
 846         if (test)
 847                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 848                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 849                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 850                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 851                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 852                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 853
 854         if (test && BNXT_HAS_RING_GRPS(bp))
 855                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 856
 857         req.flags = rte_cpu_to_le_32(flags);
 858         req.enables |= rte_cpu_to_le_32(enables);
 859
 860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 861
 862         if (test)
 863                 HWRM_CHECK_RESULT_SILENT();
 864         else
 865                 HWRM_CHECK_RESULT();
 866
 867         HWRM_UNLOCK();
 868         return rc;
 869 }
 870
 871 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 872 {
 873         int rc;
 874         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 875         struct hwrm_func_resource_qcaps_input req = {0};
 876
 877         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 878         req.fid = rte_cpu_to_le_16(0xffff);
 879
 880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 881
 882         HWRM_CHECK_RESULT();
 883
 884         if (BNXT_VF(bp)) {
 885                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 886                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 887                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 888                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 889                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 890                 /* func_resource_qcaps does not return max_rx_em_flows.
 891                  * So use the value provided by func_qcaps.
 892                  */
 893                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 894                 if (!BNXT_CHIP_THOR(bp))
 895                         bp->max_l2_ctx += bp->max_rx_em_flows;
 896                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 897                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 898         }
 899         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 900         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 901         if (bp->vf_resv_strategy >
 902             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 903                 bp->vf_resv_strategy =
 904                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 905
 906         HWRM_UNLOCK();
 907         return rc;
 908 }
 909
 910 int bnxt_hwrm_ver_get(struct bnxt *bp)
 911 {
 912         int rc = 0;
 913         struct hwrm_ver_get_input req = {.req_type = 0 };
 914         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 915         uint32_t fw_version;
 916         uint16_t max_resp_len;
 917         char type[RTE_MEMZONE_NAMESIZE];
 918         uint32_t dev_caps_cfg;
 919
 920         bp->max_req_len = HWRM_MAX_REQ_LEN;
 921         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 922
 923         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 924         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 925         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 926
 927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 928
 929         if (bp->flags & BNXT_FLAG_FW_RESET)
 930                 HWRM_CHECK_RESULT_SILENT();
 931         else
 932                 HWRM_CHECK_RESULT();
 933
 934         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 935                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 936                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 937                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 938         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 939                      (resp->hwrm_fw_min_8b << 16) |
 940                      (resp->hwrm_fw_bld_8b << 8) |
 941                      resp->hwrm_fw_rsvd_8b;
 942         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 943                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 944
 945         fw_version = resp->hwrm_intf_maj_8b << 16;
 946         fw_version |= resp->hwrm_intf_min_8b << 8;
 947         fw_version |= resp->hwrm_intf_upd_8b;
 948         bp->hwrm_spec_code = fw_version;
 949
 950         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 951                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 952                 rc = -EINVAL;
 953                 goto error;
 954         }
 955
 956         if (bp->max_req_len > resp->max_req_win_len) {
 957                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 958                 rc = -EINVAL;
 959         }
 960         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 961         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 962         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 963                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 964
 965         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 966         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 967
 968         if (bp->max_resp_len != max_resp_len) {
 969                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 970                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 971                         bp->pdev->addr.devid, bp->pdev->addr.function);
 972
 973                 rte_free(bp->hwrm_cmd_resp_addr);
 974
 975                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 976                 if (bp->hwrm_cmd_resp_addr == NULL) {
 977                         rc = -ENOMEM;
 978                         goto error;
 979                 }
 980                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 981                 bp->hwrm_cmd_resp_dma_addr =
 982                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 983                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 984                         PMD_DRV_LOG(ERR,
 985                         "Unable to map response buffer to physical memory.\n");
 986                         rc = -ENOMEM;
 987                         goto error;
 988                 }
 989                 bp->max_resp_len = max_resp_len;
 990         }
 991
 992         if ((dev_caps_cfg &
 993                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 994             (dev_caps_cfg &
 995              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 996                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 997                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 998         }
 999
1000         if (((dev_caps_cfg &
1001               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1002              (dev_caps_cfg &
1003               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1004             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1005                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1006                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1007                         bp->pdev->addr.devid, bp->pdev->addr.function);
1008
1009                 rte_free(bp->hwrm_short_cmd_req_addr);
1010
1011                 bp->hwrm_short_cmd_req_addr =
1012                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1013                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1014                         rc = -ENOMEM;
1015                         goto error;
1016                 }
1017                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1018                 bp->hwrm_short_cmd_req_dma_addr =
1019                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1020                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1021                         rte_free(bp->hwrm_short_cmd_req_addr);
1022                         PMD_DRV_LOG(ERR,
1023                                 "Unable to map buffer to physical memory.\n");
1024                         rc = -ENOMEM;
1025                         goto error;
1026                 }
1027         }
1028         if (dev_caps_cfg &
1029             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1030                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1031                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1032         }
1033         if (dev_caps_cfg &
1034             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1035                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1036         if (dev_caps_cfg &
1037             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1038                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1039                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1040         }
1041
1042 error:
1043         HWRM_UNLOCK();
1044         return rc;
1045 }
1046
1047 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1048 {
1049         int rc;
1050         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1051         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1052
1053         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1054                 return 0;
1055
1056         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1057         req.flags = flags;
1058
1059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1060
1061         HWRM_CHECK_RESULT();
1062         HWRM_UNLOCK();
1063
1064         return rc;
1065 }
1066
1067 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1068 {
1069         int rc = 0;
1070         struct hwrm_port_phy_cfg_input req = {0};
1071         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1072         uint32_t enables = 0;
1073
1074         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1075
1076         if (conf->link_up) {
1077                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1078                 if (bp->link_info.auto_mode && conf->link_speed) {
1079                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1080                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1081                 }
1082
1083                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1084                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1085                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1086                 /*
1087                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1088                  * any auto mode, even "none".
1089                  */
1090                 if (!conf->link_speed) {
1091                         /* No speeds specified. Enable AutoNeg - all speeds */
1092                         req.auto_mode =
1093                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1094                 }
1095                 /* AutoNeg - Advertise speeds specified. */
1096                 if (conf->auto_link_speed_mask &&
1097                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1098                         req.auto_mode =
1099                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1100                         req.auto_link_speed_mask =
1101                                 conf->auto_link_speed_mask;
1102                         enables |=
1103                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1104                 }
1105
1106                 req.auto_duplex = conf->duplex;
1107                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1108                 req.auto_pause = conf->auto_pause;
1109                 req.force_pause = conf->force_pause;
1110                 /* Set force_pause if there is no auto or if there is a force */
1111                 if (req.auto_pause && !req.force_pause)
1112                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1113                 else
1114                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1115
1116                 req.enables = rte_cpu_to_le_32(enables);
1117         } else {
1118                 req.flags =
1119                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1120                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1121         }
1122
1123         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1124
1125         HWRM_CHECK_RESULT();
1126         HWRM_UNLOCK();
1127
1128         return rc;
1129 }
1130
1131 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1132                                    struct bnxt_link_info *link_info)
1133 {
1134         int rc = 0;
1135         struct hwrm_port_phy_qcfg_input req = {0};
1136         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1137
1138         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1139
1140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1141
1142         HWRM_CHECK_RESULT();
1143
1144         link_info->phy_link_status = resp->link;
1145         link_info->link_up =
1146                 (link_info->phy_link_status ==
1147                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1148         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1149         link_info->duplex = resp->duplex_cfg;
1150         link_info->pause = resp->pause;
1151         link_info->auto_pause = resp->auto_pause;
1152         link_info->force_pause = resp->force_pause;
1153         link_info->auto_mode = resp->auto_mode;
1154         link_info->phy_type = resp->phy_type;
1155         link_info->media_type = resp->media_type;
1156
1157         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1158         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1159         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1160         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1161         link_info->phy_ver[0] = resp->phy_maj;
1162         link_info->phy_ver[1] = resp->phy_min;
1163         link_info->phy_ver[2] = resp->phy_bld;
1164
1165         HWRM_UNLOCK();
1166
1167         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1168         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1169         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1170         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1171         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1172                     link_info->auto_link_speed_mask);
1173         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1174                     link_info->force_link_speed);
1175
1176         return rc;
1177 }
1178
1179 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1180 {
1181         int rc = 0;
1182         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1183         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184         int i;
1185
1186         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1187
1188         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1189         /* HWRM Version >= 1.9.1 */
1190         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1191                 req.drv_qmap_cap =
1192                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1193         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1194
1195         HWRM_CHECK_RESULT();
1196
1197 #define GET_QUEUE_INFO(x) \
1198         bp->cos_queue[x].id = resp->queue_id##x; \
1199         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1200
1201         GET_QUEUE_INFO(0);
1202         GET_QUEUE_INFO(1);
1203         GET_QUEUE_INFO(2);
1204         GET_QUEUE_INFO(3);
1205         GET_QUEUE_INFO(4);
1206         GET_QUEUE_INFO(5);
1207         GET_QUEUE_INFO(6);
1208         GET_QUEUE_INFO(7);
1209
1210         HWRM_UNLOCK();
1211
1212         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1213                 bp->tx_cosq_id = bp->cos_queue[0].id;
1214         } else {
1215                 /* iterate and find the COSq profile to use for Tx */
1216                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1217                         if (bp->cos_queue[i].profile ==
1218                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1219                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1220                                 break;
1221                         }
1222                 }
1223         }
1224
1225         bp->max_tc = resp->max_configurable_queues;
1226         bp->max_lltc = resp->max_configurable_lossless_queues;
1227         if (bp->max_tc > BNXT_MAX_QUEUE)
1228                 bp->max_tc = BNXT_MAX_QUEUE;
1229         bp->max_q = bp->max_tc;
1230
1231         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1232
1233         return rc;
1234 }
1235
1236 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1237                          struct bnxt_ring *ring,
1238                          uint32_t ring_type, uint32_t map_index,
1239                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1240 {
1241         int rc = 0;
1242         uint32_t enables = 0;
1243         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1244         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1245         struct rte_mempool *mb_pool;
1246         uint16_t rx_buf_size;
1247
1248         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1249
1250         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1251         req.fbo = rte_cpu_to_le_32(0);
1252         /* Association of ring index with doorbell index */
1253         req.logical_id = rte_cpu_to_le_16(map_index);
1254         req.length = rte_cpu_to_le_32(ring->ring_size);
1255
1256         switch (ring_type) {
1257         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1258                 req.ring_type = ring_type;
1259                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1260                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1261                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1262                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1263                         enables |=
1264                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1265                 break;
1266         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1267                 req.ring_type = ring_type;
1268                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1269                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1270                 if (BNXT_CHIP_THOR(bp)) {
1271                         mb_pool = bp->rx_queues[0]->mb_pool;
1272                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1273                                       RTE_PKTMBUF_HEADROOM;
1274                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1275                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1276                         enables |=
1277                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1278                 }
1279                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1280                         enables |=
1281                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1282                 break;
1283         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1284                 req.ring_type = ring_type;
1285                 if (BNXT_HAS_NQ(bp)) {
1286                         /* Association of cp ring with nq */
1287                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1288                         enables |=
1289                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1290                 }
1291                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1292                 break;
1293         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1294                 req.ring_type = ring_type;
1295                 req.page_size = BNXT_PAGE_SHFT;
1296                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1297                 break;
1298         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1299                 req.ring_type = ring_type;
1300                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1301
1302                 mb_pool = bp->rx_queues[0]->mb_pool;
1303                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1304                               RTE_PKTMBUF_HEADROOM;
1305                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1306                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1307
1308                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1309                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1310                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1311                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1312                 break;
1313         default:
1314                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1315                         ring_type);
1316                 HWRM_UNLOCK();
1317                 return -EINVAL;
1318         }
1319         req.enables = rte_cpu_to_le_32(enables);
1320
1321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322
1323         if (rc || resp->error_code) {
1324                 if (rc == 0 && resp->error_code)
1325                         rc = rte_le_to_cpu_16(resp->error_code);
1326                 switch (ring_type) {
1327                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1328                         PMD_DRV_LOG(ERR,
1329                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1330                         HWRM_UNLOCK();
1331                         return rc;
1332                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1333                         PMD_DRV_LOG(ERR,
1334                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1335                         HWRM_UNLOCK();
1336                         return rc;
1337                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1338                         PMD_DRV_LOG(ERR,
1339                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1340                                     rc);
1341                         HWRM_UNLOCK();
1342                         return rc;
1343                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1344                         PMD_DRV_LOG(ERR,
1345                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1346                         HWRM_UNLOCK();
1347                         return rc;
1348                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1349                         PMD_DRV_LOG(ERR,
1350                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1351                         HWRM_UNLOCK();
1352                         return rc;
1353                 default:
1354                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1355                         HWRM_UNLOCK();
1356                         return rc;
1357                 }
1358         }
1359
1360         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1361         HWRM_UNLOCK();
1362         return rc;
1363 }
1364
1365 int bnxt_hwrm_ring_free(struct bnxt *bp,
1366                         struct bnxt_ring *ring, uint32_t ring_type)
1367 {
1368         int rc;
1369         struct hwrm_ring_free_input req = {.req_type = 0 };
1370         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1371
1372         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1373
1374         req.ring_type = ring_type;
1375         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1376
1377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1378
1379         if (rc || resp->error_code) {
1380                 if (rc == 0 && resp->error_code)
1381                         rc = rte_le_to_cpu_16(resp->error_code);
1382                 HWRM_UNLOCK();
1383
1384                 switch (ring_type) {
1385                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1386                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1387                                 rc);
1388                         return rc;
1389                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1390                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1391                                 rc);
1392                         return rc;
1393                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1394                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1395                                 rc);
1396                         return rc;
1397                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1398                         PMD_DRV_LOG(ERR,
1399                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1400                         return rc;
1401                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1404                         return rc;
1405                 default:
1406                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1407                         return rc;
1408                 }
1409         }
1410         HWRM_UNLOCK();
1411         return 0;
1412 }
1413
1414 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1415 {
1416         int rc = 0;
1417         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1418         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1419
1420         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1421
1422         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1423         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1424         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1425         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1426
1427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1428
1429         HWRM_CHECK_RESULT();
1430
1431         bp->grp_info[idx].fw_grp_id =
1432             rte_le_to_cpu_16(resp->ring_group_id);
1433
1434         HWRM_UNLOCK();
1435
1436         return rc;
1437 }
1438
1439 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1440 {
1441         int rc;
1442         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1443         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1444
1445         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1446
1447         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1448
1449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1450
1451         HWRM_CHECK_RESULT();
1452         HWRM_UNLOCK();
1453
1454         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1455         return rc;
1456 }
1457
1458 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1459 {
1460         int rc = 0;
1461         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1462         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1463
1464         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1465                 return rc;
1466
1467         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1468
1469         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1470
1471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1472
1473         HWRM_CHECK_RESULT();
1474         HWRM_UNLOCK();
1475
1476         return rc;
1477 }
1478
1479 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1480                                 unsigned int idx __rte_unused)
1481 {
1482         int rc;
1483         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1484         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1485
1486         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1487
1488         req.update_period_ms = rte_cpu_to_le_32(0);
1489
1490         req.stats_dma_addr =
1491             rte_cpu_to_le_64(cpr->hw_stats_map);
1492
1493         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1494
1495         HWRM_CHECK_RESULT();
1496
1497         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1498
1499         HWRM_UNLOCK();
1500
1501         return rc;
1502 }
1503
1504 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1505                                 unsigned int idx __rte_unused)
1506 {
1507         int rc;
1508         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1509         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1510
1511         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1512
1513         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1514
1515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1516
1517         HWRM_CHECK_RESULT();
1518         HWRM_UNLOCK();
1519
1520         return rc;
1521 }
1522
1523 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 {
1525         int rc = 0, i, j;
1526         struct hwrm_vnic_alloc_input req = { 0 };
1527         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1528
1529         if (!BNXT_HAS_RING_GRPS(bp))
1530                 goto skip_ring_grps;
1531
1532         /* map ring groups to this vnic */
1533         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1534                 vnic->start_grp_id, vnic->end_grp_id);
1535         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1536                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1537
1538         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1539         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1540         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1541         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1542
1543 skip_ring_grps:
1544         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1545                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1546         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1547
1548         if (vnic->func_default)
1549                 req.flags =
1550                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1552
1553         HWRM_CHECK_RESULT();
1554
1555         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1556         HWRM_UNLOCK();
1557         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1558         return rc;
1559 }
1560
1561 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1562                                         struct bnxt_vnic_info *vnic,
1563                                         struct bnxt_plcmodes_cfg *pmode)
1564 {
1565         int rc = 0;
1566         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1567         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1568
1569         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1570
1571         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1572
1573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1574
1575         HWRM_CHECK_RESULT();
1576
1577         pmode->flags = rte_le_to_cpu_32(resp->flags);
1578         /* dflt_vnic bit doesn't exist in the _cfg command */
1579         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1580         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1581         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1582         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1583
1584         HWRM_UNLOCK();
1585
1586         return rc;
1587 }
1588
1589 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1590                                        struct bnxt_vnic_info *vnic,
1591                                        struct bnxt_plcmodes_cfg *pmode)
1592 {
1593         int rc = 0;
1594         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1595         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1596
1597         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1598                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1599                 return rc;
1600         }
1601
1602         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1603
1604         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1605         req.flags = rte_cpu_to_le_32(pmode->flags);
1606         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1607         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1608         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1609         req.enables = rte_cpu_to_le_32(
1610             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1611             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1612             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1613         );
1614
1615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616
1617         HWRM_CHECK_RESULT();
1618         HWRM_UNLOCK();
1619
1620         return rc;
1621 }
1622
1623 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1624 {
1625         int rc = 0;
1626         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1627         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1628         struct bnxt_plcmodes_cfg pmodes = { 0 };
1629         uint32_t ctx_enable_flag = 0;
1630         uint32_t enables = 0;
1631
1632         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1633                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1634                 return rc;
1635         }
1636
1637         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1638         if (rc)
1639                 return rc;
1640
1641         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1642
1643         if (BNXT_CHIP_THOR(bp)) {
1644                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1645                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1646                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1647
1648                 req.default_rx_ring_id =
1649                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1650                 req.default_cmpl_ring_id =
1651                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1652                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1653                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1654                 goto config_mru;
1655         }
1656
1657         /* Only RSS support for now TBD: COS & LB */
1658         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1659         if (vnic->lb_rule != 0xffff)
1660                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1661         if (vnic->cos_rule != 0xffff)
1662                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1663         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1664                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1665                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1666         }
1667         enables |= ctx_enable_flag;
1668         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1669         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1670         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1671         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1672
1673 config_mru:
1674         req.enables = rte_cpu_to_le_32(enables);
1675         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1676         req.mru = rte_cpu_to_le_16(vnic->mru);
1677         /* Configure default VNIC only once. */
1678         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1679                 req.flags |=
1680                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1681                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1682         }
1683         if (vnic->vlan_strip)
1684                 req.flags |=
1685                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1686         if (vnic->bd_stall)
1687                 req.flags |=
1688                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1689         if (vnic->roce_dual)
1690                 req.flags |= rte_cpu_to_le_32(
1691                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1692         if (vnic->roce_only)
1693                 req.flags |= rte_cpu_to_le_32(
1694                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1695         if (vnic->rss_dflt_cr)
1696                 req.flags |= rte_cpu_to_le_32(
1697                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1698
1699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1700
1701         HWRM_CHECK_RESULT();
1702         HWRM_UNLOCK();
1703
1704         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1705
1706         return rc;
1707 }
1708
1709 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1710                 int16_t fw_vf_id)
1711 {
1712         int rc = 0;
1713         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1714         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1715
1716         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1717                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1718                 return rc;
1719         }
1720         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1721
1722         req.enables =
1723                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1724         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1725         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1726
1727         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1728
1729         HWRM_CHECK_RESULT();
1730
1731         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1732         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1733         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1734         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1735         vnic->mru = rte_le_to_cpu_16(resp->mru);
1736         vnic->func_default = rte_le_to_cpu_32(
1737                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1738         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1739                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1740         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1741                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1742         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1743                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1744         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1745                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1746         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1747                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1748
1749         HWRM_UNLOCK();
1750
1751         return rc;
1752 }
1753
1754 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1755                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1756 {
1757         int rc = 0;
1758         uint16_t ctx_id;
1759         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1760         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1761                                                 bp->hwrm_cmd_resp_addr;
1762
1763         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1764
1765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1766         HWRM_CHECK_RESULT();
1767
1768         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1769         if (!BNXT_HAS_RING_GRPS(bp))
1770                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1771         else if (ctx_idx == 0)
1772                 vnic->rss_rule = ctx_id;
1773
1774         HWRM_UNLOCK();
1775
1776         return rc;
1777 }
1778
1779 static
1780 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1781                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1782 {
1783         int rc = 0;
1784         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1785         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1786                                                 bp->hwrm_cmd_resp_addr;
1787
1788         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1789                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1790                 return rc;
1791         }
1792         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1793
1794         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1795
1796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1797
1798         HWRM_CHECK_RESULT();
1799         HWRM_UNLOCK();
1800
1801         return rc;
1802 }
1803
1804 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1805 {
1806         int rc = 0;
1807
1808         if (BNXT_CHIP_THOR(bp)) {
1809                 int j;
1810
1811                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1812                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1813                                                       vnic,
1814                                                       vnic->fw_grp_ids[j]);
1815                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1816                 }
1817                 vnic->num_lb_ctxts = 0;
1818         } else {
1819                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1820                 vnic->rss_rule = INVALID_HW_RING_ID;
1821         }
1822
1823         return rc;
1824 }
1825
1826 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1827 {
1828         int rc = 0;
1829         struct hwrm_vnic_free_input req = {.req_type = 0 };
1830         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1831
1832         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1833                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1834                 return rc;
1835         }
1836
1837         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1838
1839         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1840
1841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1842
1843         HWRM_CHECK_RESULT();
1844         HWRM_UNLOCK();
1845
1846         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1847         /* Configure default VNIC again if necessary. */
1848         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1849                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1850
1851         return rc;
1852 }
1853
1854 static int
1855 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1856 {
1857         int i;
1858         int rc = 0;
1859         int nr_ctxs = vnic->num_lb_ctxts;
1860         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1861         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1862
1863         for (i = 0; i < nr_ctxs; i++) {
1864                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1865
1866                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1867                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1868                 req.hash_mode_flags = vnic->hash_mode;
1869
1870                 req.hash_key_tbl_addr =
1871                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1872
1873                 req.ring_grp_tbl_addr =
1874                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1875                                          i * HW_HASH_INDEX_SIZE);
1876                 req.ring_table_pair_index = i;
1877                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1878
1879                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1880                                             BNXT_USE_CHIMP_MB);
1881
1882                 HWRM_CHECK_RESULT();
1883                 HWRM_UNLOCK();
1884         }
1885
1886         return rc;
1887 }
1888
1889 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1890                            struct bnxt_vnic_info *vnic)
1891 {
1892         int rc = 0;
1893         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1894         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1895
1896         if (!vnic->rss_table)
1897                 return 0;
1898
1899         if (BNXT_CHIP_THOR(bp))
1900                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1901
1902         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1903
1904         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1905         req.hash_mode_flags = vnic->hash_mode;
1906
1907         req.ring_grp_tbl_addr =
1908             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1909         req.hash_key_tbl_addr =
1910             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1911         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1912         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1913
1914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1915
1916         HWRM_CHECK_RESULT();
1917         HWRM_UNLOCK();
1918
1919         return rc;
1920 }
1921
1922 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1923                         struct bnxt_vnic_info *vnic)
1924 {
1925         int rc = 0;
1926         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1927         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1928         uint16_t size;
1929
1930         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1931                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1932                 return rc;
1933         }
1934
1935         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1936
1937         req.flags = rte_cpu_to_le_32(
1938                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1939
1940         req.enables = rte_cpu_to_le_32(
1941                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1942
1943         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1944         size -= RTE_PKTMBUF_HEADROOM;
1945         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1946
1947         req.jumbo_thresh = rte_cpu_to_le_16(size);
1948         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1949
1950         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1951
1952         HWRM_CHECK_RESULT();
1953         HWRM_UNLOCK();
1954
1955         return rc;
1956 }
1957
1958 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1959                         struct bnxt_vnic_info *vnic, bool enable)
1960 {
1961         int rc = 0;
1962         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1963         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1964
1965         if (BNXT_CHIP_THOR(bp))
1966                 return 0;
1967
1968         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1969
1970         if (enable) {
1971                 req.enables = rte_cpu_to_le_32(
1972                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1973                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1974                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1975                 req.flags = rte_cpu_to_le_32(
1976                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1977                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1978                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1979                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1980                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1981                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1982                 req.max_agg_segs = rte_cpu_to_le_16(5);
1983                 req.max_aggs =
1984                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1985                 req.min_agg_len = rte_cpu_to_le_32(512);
1986         }
1987         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1988
1989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1990
1991         HWRM_CHECK_RESULT();
1992         HWRM_UNLOCK();
1993
1994         return rc;
1995 }
1996
1997 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1998 {
1999         struct hwrm_func_cfg_input req = {0};
2000         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2001         int rc;
2002
2003         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2004         req.enables = rte_cpu_to_le_32(
2005                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2006         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2007         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2008
2009         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2010
2011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012         HWRM_CHECK_RESULT();
2013         HWRM_UNLOCK();
2014
2015         bp->pf.vf_info[vf].random_mac = false;
2016
2017         return rc;
2018 }
2019
2020 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2021                                   uint64_t *dropped)
2022 {
2023         int rc = 0;
2024         struct hwrm_func_qstats_input req = {.req_type = 0};
2025         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2026
2027         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2028
2029         req.fid = rte_cpu_to_le_16(fid);
2030
2031         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2032
2033         HWRM_CHECK_RESULT();
2034
2035         if (dropped)
2036                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2037
2038         HWRM_UNLOCK();
2039
2040         return rc;
2041 }
2042
2043 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2044                           struct rte_eth_stats *stats)
2045 {
2046         int rc = 0;
2047         struct hwrm_func_qstats_input req = {.req_type = 0};
2048         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2049
2050         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2051
2052         req.fid = rte_cpu_to_le_16(fid);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057
2058         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2059         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2060         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2061         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2062         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2063         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2064
2065         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2066         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2067         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2068         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2069         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2070         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2071
2072         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2073         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2074         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2075
2076         HWRM_UNLOCK();
2077
2078         return rc;
2079 }
2080
2081 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2082 {
2083         int rc = 0;
2084         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2085         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2086
2087         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2088
2089         req.fid = rte_cpu_to_le_16(fid);
2090
2091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2092
2093         HWRM_CHECK_RESULT();
2094         HWRM_UNLOCK();
2095
2096         return rc;
2097 }
2098
2099 /*
2100  * HWRM utility functions
2101  */
2102
2103 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2104 {
2105         unsigned int i;
2106         int rc = 0;
2107
2108         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2109                 struct bnxt_tx_queue *txq;
2110                 struct bnxt_rx_queue *rxq;
2111                 struct bnxt_cp_ring_info *cpr;
2112
2113                 if (i >= bp->rx_cp_nr_rings) {
2114                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2115                         cpr = txq->cp_ring;
2116                 } else {
2117                         rxq = bp->rx_queues[i];
2118                         cpr = rxq->cp_ring;
2119                 }
2120
2121                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2122                 if (rc)
2123                         return rc;
2124         }
2125         return 0;
2126 }
2127
2128 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2129 {
2130         int rc;
2131         unsigned int i;
2132         struct bnxt_cp_ring_info *cpr;
2133
2134         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2135
2136                 if (i >= bp->rx_cp_nr_rings) {
2137                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2138                 } else {
2139                         cpr = bp->rx_queues[i]->cp_ring;
2140                         if (BNXT_HAS_RING_GRPS(bp))
2141                                 bp->grp_info[i].fw_stats_ctx = -1;
2142                 }
2143                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2144                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2145                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2146                         if (rc)
2147                                 return rc;
2148                 }
2149         }
2150         return 0;
2151 }
2152
2153 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2154 {
2155         unsigned int i;
2156         int rc = 0;
2157
2158         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2159                 struct bnxt_tx_queue *txq;
2160                 struct bnxt_rx_queue *rxq;
2161                 struct bnxt_cp_ring_info *cpr;
2162
2163                 if (i >= bp->rx_cp_nr_rings) {
2164                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2165                         cpr = txq->cp_ring;
2166                 } else {
2167                         rxq = bp->rx_queues[i];
2168                         cpr = rxq->cp_ring;
2169                 }
2170
2171                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2172
2173                 if (rc)
2174                         return rc;
2175         }
2176         return rc;
2177 }
2178
2179 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2180 {
2181         uint16_t idx;
2182         uint32_t rc = 0;
2183
2184         if (!BNXT_HAS_RING_GRPS(bp))
2185                 return 0;
2186
2187         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2188
2189                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2190                         continue;
2191
2192                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2193
2194                 if (rc)
2195                         return rc;
2196         }
2197         return rc;
2198 }
2199
2200 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2201 {
2202         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2203
2204         bnxt_hwrm_ring_free(bp, cp_ring,
2205                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2206         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2207         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2208                                      sizeof(*cpr->cp_desc_ring));
2209         cpr->cp_raw_cons = 0;
2210         cpr->valid = 0;
2211 }
2212
2213 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2214 {
2215         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2216
2217         bnxt_hwrm_ring_free(bp, cp_ring,
2218                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2219         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2220         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2221                         sizeof(*cpr->cp_desc_ring));
2222         cpr->cp_raw_cons = 0;
2223         cpr->valid = 0;
2224 }
2225
2226 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2227 {
2228         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2229         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2230         struct bnxt_ring *ring = rxr->rx_ring_struct;
2231         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2232
2233         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2234                 bnxt_hwrm_ring_free(bp, ring,
2235                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2236                 ring->fw_ring_id = INVALID_HW_RING_ID;
2237                 if (BNXT_HAS_RING_GRPS(bp))
2238                         bp->grp_info[queue_index].rx_fw_ring_id =
2239                                                         INVALID_HW_RING_ID;
2240                 memset(rxr->rx_desc_ring, 0,
2241                        rxr->rx_ring_struct->ring_size *
2242                        sizeof(*rxr->rx_desc_ring));
2243                 memset(rxr->rx_buf_ring, 0,
2244                        rxr->rx_ring_struct->ring_size *
2245                        sizeof(*rxr->rx_buf_ring));
2246                 rxr->rx_prod = 0;
2247         }
2248         ring = rxr->ag_ring_struct;
2249         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2250                 bnxt_hwrm_ring_free(bp, ring,
2251                                     BNXT_CHIP_THOR(bp) ?
2252                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2253                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2254                 ring->fw_ring_id = INVALID_HW_RING_ID;
2255                 memset(rxr->ag_buf_ring, 0,
2256                        rxr->ag_ring_struct->ring_size *
2257                        sizeof(*rxr->ag_buf_ring));
2258                 rxr->ag_prod = 0;
2259                 if (BNXT_HAS_RING_GRPS(bp))
2260                         bp->grp_info[queue_index].ag_fw_ring_id =
2261                                                         INVALID_HW_RING_ID;
2262         }
2263         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2264                 bnxt_free_cp_ring(bp, cpr);
2265                 if (rxq->nq_ring)
2266                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2267         }
2268
2269         if (BNXT_HAS_RING_GRPS(bp))
2270                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2271 }
2272
2273 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2274 {
2275         unsigned int i;
2276
2277         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2278                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2279                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2280                 struct bnxt_ring *ring = txr->tx_ring_struct;
2281                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2282
2283                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2284                         bnxt_hwrm_ring_free(bp, ring,
2285                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2286                         ring->fw_ring_id = INVALID_HW_RING_ID;
2287                         memset(txr->tx_desc_ring, 0,
2288                                         txr->tx_ring_struct->ring_size *
2289                                         sizeof(*txr->tx_desc_ring));
2290                         memset(txr->tx_buf_ring, 0,
2291                                         txr->tx_ring_struct->ring_size *
2292                                         sizeof(*txr->tx_buf_ring));
2293                         txr->tx_prod = 0;
2294                         txr->tx_cons = 0;
2295                 }
2296                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2297                         bnxt_free_cp_ring(bp, cpr);
2298                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2299                         if (txq->nq_ring)
2300                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2301                 }
2302         }
2303
2304         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2305                 bnxt_free_hwrm_rx_ring(bp, i);
2306
2307         return 0;
2308 }
2309
2310 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2311 {
2312         uint16_t i;
2313         uint32_t rc = 0;
2314
2315         if (!BNXT_HAS_RING_GRPS(bp))
2316                 return 0;
2317
2318         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2319                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2320                 if (rc)
2321                         return rc;
2322         }
2323         return rc;
2324 }
2325
2326 void bnxt_free_hwrm_resources(struct bnxt *bp)
2327 {
2328         /* Release memzone */
2329         rte_free(bp->hwrm_cmd_resp_addr);
2330         rte_free(bp->hwrm_short_cmd_req_addr);
2331         bp->hwrm_cmd_resp_addr = NULL;
2332         bp->hwrm_short_cmd_req_addr = NULL;
2333         bp->hwrm_cmd_resp_dma_addr = 0;
2334         bp->hwrm_short_cmd_req_dma_addr = 0;
2335 }
2336
2337 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2338 {
2339         struct rte_pci_device *pdev = bp->pdev;
2340         char type[RTE_MEMZONE_NAMESIZE];
2341
2342         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2343                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2344         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2345         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2346         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2347         if (bp->hwrm_cmd_resp_addr == NULL)
2348                 return -ENOMEM;
2349         bp->hwrm_cmd_resp_dma_addr =
2350                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2351         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2352                 PMD_DRV_LOG(ERR,
2353                         "unable to map response address to physical memory\n");
2354                 return -ENOMEM;
2355         }
2356         rte_spinlock_init(&bp->hwrm_lock);
2357
2358         return 0;
2359 }
2360
2361 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2362 {
2363         struct bnxt_filter_info *filter;
2364         int rc = 0;
2365
2366         STAILQ_FOREACH(filter, &vnic->filter, next) {
2367                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2368                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2369                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2370                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2371                 else
2372                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2373                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2374                 bnxt_free_filter(bp, filter);
2375                 //if (rc)
2376                         //break;
2377         }
2378         return rc;
2379 }
2380
2381 static int
2382 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2383 {
2384         struct bnxt_filter_info *filter;
2385         struct rte_flow *flow;
2386         int rc = 0;
2387
2388         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2389                 flow = STAILQ_FIRST(&vnic->flow_list);
2390                 filter = flow->filter;
2391                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2392                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2393                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2394                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2395                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2396                 else
2397                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2398
2399                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2400                 rte_free(flow);
2401                 //if (rc)
2402                         //break;
2403         }
2404         return rc;
2405 }
2406
2407 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2408 {
2409         struct bnxt_filter_info *filter;
2410         int rc = 0;
2411
2412         STAILQ_FOREACH(filter, &vnic->filter, next) {
2413                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2414                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2415                                                      filter);
2416                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2417                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2418                                                          filter);
2419                 else
2420                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2421                                                      filter);
2422                 if (rc)
2423                         break;
2424         }
2425         return rc;
2426 }
2427
2428 void bnxt_free_tunnel_ports(struct bnxt *bp)
2429 {
2430         if (bp->vxlan_port_cnt)
2431                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2432                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2433         bp->vxlan_port = 0;
2434         if (bp->geneve_port_cnt)
2435                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2436                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2437         bp->geneve_port = 0;
2438 }
2439
2440 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2441 {
2442         int i;
2443
2444         if (bp->vnic_info == NULL)
2445                 return;
2446
2447         /*
2448          * Cleanup VNICs in reverse order, to make sure the L2 filter
2449          * from vnic0 is last to be cleaned up.
2450          */
2451         for (i = bp->max_vnics - 1; i >= 0; i--) {
2452                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2453
2454                 // If the VNIC ID is invalid we are not currently using the VNIC
2455                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2456                         continue;
2457
2458                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2459
2460                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2461
2462                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2463
2464                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2465
2466                 bnxt_hwrm_vnic_free(bp, vnic);
2467
2468                 rte_free(vnic->fw_grp_ids);
2469         }
2470         /* Ring resources */
2471         bnxt_free_all_hwrm_rings(bp);
2472         bnxt_free_all_hwrm_ring_grps(bp);
2473         bnxt_free_all_hwrm_stat_ctxs(bp);
2474         bnxt_free_tunnel_ports(bp);
2475 }
2476
2477 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2478 {
2479         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2480
2481         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2482                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2483
2484         switch (conf_link_speed) {
2485         case ETH_LINK_SPEED_10M_HD:
2486         case ETH_LINK_SPEED_100M_HD:
2487                 /* FALLTHROUGH */
2488                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2489         }
2490         return hw_link_duplex;
2491 }
2492
2493 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2494 {
2495         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2496 }
2497
2498 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2499 {
2500         uint16_t eth_link_speed = 0;
2501
2502         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2503                 return ETH_LINK_SPEED_AUTONEG;
2504
2505         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2506         case ETH_LINK_SPEED_100M:
2507         case ETH_LINK_SPEED_100M_HD:
2508                 /* FALLTHROUGH */
2509                 eth_link_speed =
2510                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2511                 break;
2512         case ETH_LINK_SPEED_1G:
2513                 eth_link_speed =
2514                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2515                 break;
2516         case ETH_LINK_SPEED_2_5G:
2517                 eth_link_speed =
2518                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2519                 break;
2520         case ETH_LINK_SPEED_10G:
2521                 eth_link_speed =
2522                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2523                 break;
2524         case ETH_LINK_SPEED_20G:
2525                 eth_link_speed =
2526                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2527                 break;
2528         case ETH_LINK_SPEED_25G:
2529                 eth_link_speed =
2530                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2531                 break;
2532         case ETH_LINK_SPEED_40G:
2533                 eth_link_speed =
2534                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2535                 break;
2536         case ETH_LINK_SPEED_50G:
2537                 eth_link_speed =
2538                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2539                 break;
2540         case ETH_LINK_SPEED_100G:
2541                 eth_link_speed =
2542                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2543                 break;
2544         default:
2545                 PMD_DRV_LOG(ERR,
2546                         "Unsupported link speed %d; default to AUTO\n",
2547                         conf_link_speed);
2548                 break;
2549         }
2550         return eth_link_speed;
2551 }
2552
2553 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2554                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2555                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2556                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2557
2558 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2559 {
2560         uint32_t one_speed;
2561
2562         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2563                 return 0;
2564
2565         if (link_speed & ETH_LINK_SPEED_FIXED) {
2566                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2567
2568                 if (one_speed & (one_speed - 1)) {
2569                         PMD_DRV_LOG(ERR,
2570                                 "Invalid advertised speeds (%u) for port %u\n",
2571                                 link_speed, port_id);
2572                         return -EINVAL;
2573                 }
2574                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2575                         PMD_DRV_LOG(ERR,
2576                                 "Unsupported advertised speed (%u) for port %u\n",
2577                                 link_speed, port_id);
2578                         return -EINVAL;
2579                 }
2580         } else {
2581                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2582                         PMD_DRV_LOG(ERR,
2583                                 "Unsupported advertised speeds (%u) for port %u\n",
2584                                 link_speed, port_id);
2585                         return -EINVAL;
2586                 }
2587         }
2588         return 0;
2589 }
2590
2591 static uint16_t
2592 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2593 {
2594         uint16_t ret = 0;
2595
2596         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2597                 if (bp->link_info.support_speeds)
2598                         return bp->link_info.support_speeds;
2599                 link_speed = BNXT_SUPPORTED_SPEEDS;
2600         }
2601
2602         if (link_speed & ETH_LINK_SPEED_100M)
2603                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2604         if (link_speed & ETH_LINK_SPEED_100M_HD)
2605                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2606         if (link_speed & ETH_LINK_SPEED_1G)
2607                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2608         if (link_speed & ETH_LINK_SPEED_2_5G)
2609                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2610         if (link_speed & ETH_LINK_SPEED_10G)
2611                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2612         if (link_speed & ETH_LINK_SPEED_20G)
2613                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2614         if (link_speed & ETH_LINK_SPEED_25G)
2615                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2616         if (link_speed & ETH_LINK_SPEED_40G)
2617                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2618         if (link_speed & ETH_LINK_SPEED_50G)
2619                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2620         if (link_speed & ETH_LINK_SPEED_100G)
2621                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2622         return ret;
2623 }
2624
2625 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2626 {
2627         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2628
2629         switch (hw_link_speed) {
2630         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2631                 eth_link_speed = ETH_SPEED_NUM_100M;
2632                 break;
2633         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2634                 eth_link_speed = ETH_SPEED_NUM_1G;
2635                 break;
2636         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2637                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2638                 break;
2639         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2640                 eth_link_speed = ETH_SPEED_NUM_10G;
2641                 break;
2642         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2643                 eth_link_speed = ETH_SPEED_NUM_20G;
2644                 break;
2645         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2646                 eth_link_speed = ETH_SPEED_NUM_25G;
2647                 break;
2648         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2649                 eth_link_speed = ETH_SPEED_NUM_40G;
2650                 break;
2651         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2652                 eth_link_speed = ETH_SPEED_NUM_50G;
2653                 break;
2654         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2655                 eth_link_speed = ETH_SPEED_NUM_100G;
2656                 break;
2657         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2658         default:
2659                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2660                         hw_link_speed);
2661                 break;
2662         }
2663         return eth_link_speed;
2664 }
2665
2666 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2667 {
2668         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2669
2670         switch (hw_link_duplex) {
2671         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2672         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2673                 /* FALLTHROUGH */
2674                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2675                 break;
2676         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2677                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2678                 break;
2679         default:
2680                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2681                         hw_link_duplex);
2682                 break;
2683         }
2684         return eth_link_duplex;
2685 }
2686
2687 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2688 {
2689         int rc = 0;
2690         struct bnxt_link_info *link_info = &bp->link_info;
2691
2692         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2693         if (rc) {
2694                 PMD_DRV_LOG(ERR,
2695                         "Get link config failed with rc %d\n", rc);
2696                 goto exit;
2697         }
2698         if (link_info->link_speed)
2699                 link->link_speed =
2700                         bnxt_parse_hw_link_speed(link_info->link_speed);
2701         else
2702                 link->link_speed = ETH_SPEED_NUM_NONE;
2703         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2704         link->link_status = link_info->link_up;
2705         link->link_autoneg = link_info->auto_mode ==
2706                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2707                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2708 exit:
2709         return rc;
2710 }
2711
2712 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2713 {
2714         int rc = 0;
2715         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2716         struct bnxt_link_info link_req;
2717         uint16_t speed, autoneg;
2718
2719         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2720                 return 0;
2721
2722         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2723                         bp->eth_dev->data->port_id);
2724         if (rc)
2725                 goto error;
2726
2727         memset(&link_req, 0, sizeof(link_req));
2728         link_req.link_up = link_up;
2729         if (!link_up)
2730                 goto port_phy_cfg;
2731
2732         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2733         if (BNXT_CHIP_THOR(bp) &&
2734             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2735                 /* 40G is not supported as part of media auto detect.
2736                  * The speed should be forced and autoneg disabled
2737                  * to configure 40G speed.
2738                  */
2739                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2740                 autoneg = 0;
2741         }
2742
2743         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2744         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2745         /* Autoneg can be done only when the FW allows.
2746          * When user configures fixed speed of 40G and later changes to
2747          * any other speed, auto_link_speed/force_link_speed is still set
2748          * to 40G until link comes up at new speed.
2749          */
2750         if (autoneg == 1 &&
2751             !(!BNXT_CHIP_THOR(bp) &&
2752               (bp->link_info.auto_link_speed ||
2753                bp->link_info.force_link_speed))) {
2754                 link_req.phy_flags |=
2755                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2756                 link_req.auto_link_speed_mask =
2757                         bnxt_parse_eth_link_speed_mask(bp,
2758                                                        dev_conf->link_speeds);
2759         } else {
2760                 if (bp->link_info.phy_type ==
2761                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2762                     bp->link_info.phy_type ==
2763                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2764                     bp->link_info.media_type ==
2765                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2766                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2767                         return -EINVAL;
2768                 }
2769
2770                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2771                 /* If user wants a particular speed try that first. */
2772                 if (speed)
2773                         link_req.link_speed = speed;
2774                 else if (bp->link_info.force_link_speed)
2775                         link_req.link_speed = bp->link_info.force_link_speed;
2776                 else
2777                         link_req.link_speed = bp->link_info.auto_link_speed;
2778         }
2779         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2780         link_req.auto_pause = bp->link_info.auto_pause;
2781         link_req.force_pause = bp->link_info.force_pause;
2782
2783 port_phy_cfg:
2784         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2785         if (rc) {
2786                 PMD_DRV_LOG(ERR,
2787                         "Set link config failed with rc %d\n", rc);
2788         }
2789
2790 error:
2791         return rc;
2792 }
2793
2794 /* JIRA 22088 */
2795 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2796 {
2797         struct hwrm_func_qcfg_input req = {0};
2798         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2799         uint16_t flags;
2800         int rc = 0;
2801
2802         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2803         req.fid = rte_cpu_to_le_16(0xffff);
2804
2805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2806
2807         HWRM_CHECK_RESULT();
2808
2809         /* Hard Coded.. 0xfff VLAN ID mask */
2810         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2811         flags = rte_le_to_cpu_16(resp->flags);
2812         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2813                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2814
2815         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2816                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2817                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2818         } else if (BNXT_VF(bp) &&
2819                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2820                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2821                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2822         }
2823
2824         if (mtu)
2825                 *mtu = resp->mtu;
2826
2827         switch (resp->port_partition_type) {
2828         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2829         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2830         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2831                 /* FALLTHROUGH */
2832                 bp->port_partition_type = resp->port_partition_type;
2833                 break;
2834         default:
2835                 bp->port_partition_type = 0;
2836                 break;
2837         }
2838
2839         HWRM_UNLOCK();
2840
2841         return rc;
2842 }
2843
2844 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2845                                    struct hwrm_func_qcaps_output *qcaps)
2846 {
2847         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2848         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2849                sizeof(qcaps->mac_address));
2850         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2851         qcaps->max_rx_rings = fcfg->num_rx_rings;
2852         qcaps->max_tx_rings = fcfg->num_tx_rings;
2853         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2854         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2855         qcaps->max_vfs = 0;
2856         qcaps->first_vf_id = 0;
2857         qcaps->max_vnics = fcfg->num_vnics;
2858         qcaps->max_decap_records = 0;
2859         qcaps->max_encap_records = 0;
2860         qcaps->max_tx_wm_flows = 0;
2861         qcaps->max_tx_em_flows = 0;
2862         qcaps->max_rx_wm_flows = 0;
2863         qcaps->max_rx_em_flows = 0;
2864         qcaps->max_flow_id = 0;
2865         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2866         qcaps->max_sp_tx_rings = 0;
2867         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2868 }
2869
2870 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2871 {
2872         struct hwrm_func_cfg_input req = {0};
2873         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2874         uint32_t enables;
2875         int rc;
2876
2877         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2878                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2879                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2880                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2881                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2882                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2883                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2884                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2885                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2886
2887         if (BNXT_HAS_RING_GRPS(bp)) {
2888                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2889                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2890         } else if (BNXT_HAS_NQ(bp)) {
2891                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2892                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2893         }
2894
2895         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2896         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2897         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2898                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2899                                    BNXT_NUM_VLANS);
2900         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2901         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2902         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2903         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2904         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2905         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2906         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2907         req.fid = rte_cpu_to_le_16(0xffff);
2908         req.enables = rte_cpu_to_le_32(enables);
2909
2910         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2911
2912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2913
2914         HWRM_CHECK_RESULT();
2915         HWRM_UNLOCK();
2916
2917         return rc;
2918 }
2919
2920 static void populate_vf_func_cfg_req(struct bnxt *bp,
2921                                      struct hwrm_func_cfg_input *req,
2922                                      int num_vfs)
2923 {
2924         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2925                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2926                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2927                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2928                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2929                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2930                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2931                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2932                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2933                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2934
2935         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2936                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2937                                     BNXT_NUM_VLANS);
2938         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2939                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2940                                     BNXT_NUM_VLANS);
2941         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2942                                                 (num_vfs + 1));
2943         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2944         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2945                                                (num_vfs + 1));
2946         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2947         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2948         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2949         /* TODO: For now, do not support VMDq/RFS on VFs. */
2950         req->num_vnics = rte_cpu_to_le_16(1);
2951         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2952                                                  (num_vfs + 1));
2953 }
2954
2955 static void add_random_mac_if_needed(struct bnxt *bp,
2956                                      struct hwrm_func_cfg_input *cfg_req,
2957                                      int vf)
2958 {
2959         struct rte_ether_addr mac;
2960
2961         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2962                 return;
2963
2964         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2965                 cfg_req->enables |=
2966                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2967                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2968                 bp->pf.vf_info[vf].random_mac = true;
2969         } else {
2970                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2971                         RTE_ETHER_ADDR_LEN);
2972         }
2973 }
2974
2975 static void reserve_resources_from_vf(struct bnxt *bp,
2976                                       struct hwrm_func_cfg_input *cfg_req,
2977                                       int vf)
2978 {
2979         struct hwrm_func_qcaps_input req = {0};
2980         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2981         int rc;
2982
2983         /* Get the actual allocated values now */
2984         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2985         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2987
2988         if (rc) {
2989                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2990                 copy_func_cfg_to_qcaps(cfg_req, resp);
2991         } else if (resp->error_code) {
2992                 rc = rte_le_to_cpu_16(resp->error_code);
2993                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2994                 copy_func_cfg_to_qcaps(cfg_req, resp);
2995         }
2996
2997         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2998         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2999         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3000         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3001         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3002         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3003         /*
3004          * TODO: While not supporting VMDq with VFs, max_vnics is always
3005          * forced to 1 in this case
3006          */
3007         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3008         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3009
3010         HWRM_UNLOCK();
3011 }
3012
3013 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3014 {
3015         struct hwrm_func_qcfg_input req = {0};
3016         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3017         int rc;
3018
3019         /* Check for zero MAC address */
3020         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3021         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3022         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3023         HWRM_CHECK_RESULT();
3024         rc = rte_le_to_cpu_16(resp->vlan);
3025
3026         HWRM_UNLOCK();
3027
3028         return rc;
3029 }
3030
3031 static int update_pf_resource_max(struct bnxt *bp)
3032 {
3033         struct hwrm_func_qcfg_input req = {0};
3034         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3035         int rc;
3036
3037         /* And copy the allocated numbers into the pf struct */
3038         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3039         req.fid = rte_cpu_to_le_16(0xffff);
3040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3041         HWRM_CHECK_RESULT();
3042
3043         /* Only TX ring value reflects actual allocation? TODO */
3044         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3045         bp->pf.evb_mode = resp->evb_mode;
3046
3047         HWRM_UNLOCK();
3048
3049         return rc;
3050 }
3051
3052 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3053 {
3054         int rc;
3055
3056         if (!BNXT_PF(bp)) {
3057                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3058                 return -EINVAL;
3059         }
3060
3061         rc = bnxt_hwrm_func_qcaps(bp);
3062         if (rc)
3063                 return rc;
3064
3065         bp->pf.func_cfg_flags &=
3066                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3067                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3068         bp->pf.func_cfg_flags |=
3069                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3070         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3071         rc = __bnxt_hwrm_func_qcaps(bp);
3072         return rc;
3073 }
3074
3075 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3076 {
3077         struct hwrm_func_cfg_input req = {0};
3078         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3079         int i;
3080         size_t sz;
3081         int rc = 0;
3082         size_t req_buf_sz;
3083
3084         if (!BNXT_PF(bp)) {
3085                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3086                 return -EINVAL;
3087         }
3088
3089         rc = bnxt_hwrm_func_qcaps(bp);
3090
3091         if (rc)
3092                 return rc;
3093
3094         bp->pf.active_vfs = num_vfs;
3095
3096         /*
3097          * First, configure the PF to only use one TX ring.  This ensures that
3098          * there are enough rings for all VFs.
3099          *
3100          * If we don't do this, when we call func_alloc() later, we will lock
3101          * extra rings to the PF that won't be available during func_cfg() of
3102          * the VFs.
3103          *
3104          * This has been fixed with firmware versions above 20.6.54
3105          */
3106         bp->pf.func_cfg_flags &=
3107                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3108                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3109         bp->pf.func_cfg_flags |=
3110                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3111         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3112         if (rc)
3113                 return rc;
3114
3115         /*
3116          * Now, create and register a buffer to hold forwarded VF requests
3117          */
3118         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3119         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3120                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3121         if (bp->pf.vf_req_buf == NULL) {
3122                 rc = -ENOMEM;
3123                 goto error_free;
3124         }
3125         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3126                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3127         for (i = 0; i < num_vfs; i++)
3128                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3129                                         (i * HWRM_MAX_REQ_LEN);
3130
3131         rc = bnxt_hwrm_func_buf_rgtr(bp);
3132         if (rc)
3133                 goto error_free;
3134
3135         populate_vf_func_cfg_req(bp, &req, num_vfs);
3136
3137         bp->pf.active_vfs = 0;
3138         for (i = 0; i < num_vfs; i++) {
3139                 add_random_mac_if_needed(bp, &req, i);
3140
3141                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3142                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3143                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3144                 rc = bnxt_hwrm_send_message(bp,
3145                                             &req,
3146                                             sizeof(req),
3147                                             BNXT_USE_CHIMP_MB);
3148
3149                 /* Clear enable flag for next pass */
3150                 req.enables &= ~rte_cpu_to_le_32(
3151                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3152
3153                 if (rc || resp->error_code) {
3154                         PMD_DRV_LOG(ERR,
3155                                 "Failed to initizlie VF %d\n", i);
3156                         PMD_DRV_LOG(ERR,
3157                                 "Not all VFs available. (%d, %d)\n",
3158                                 rc, resp->error_code);
3159                         HWRM_UNLOCK();
3160                         break;
3161                 }
3162
3163                 HWRM_UNLOCK();
3164
3165                 reserve_resources_from_vf(bp, &req, i);
3166                 bp->pf.active_vfs++;
3167                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3168         }
3169
3170         /*
3171          * Now configure the PF to use "the rest" of the resources
3172          * We're using STD_TX_RING_MODE here though which will limit the TX
3173          * rings.  This will allow QoS to function properly.  Not setting this
3174          * will cause PF rings to break bandwidth settings.
3175          */
3176         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3177         if (rc)
3178                 goto error_free;
3179
3180         rc = update_pf_resource_max(bp);
3181         if (rc)
3182                 goto error_free;
3183
3184         return rc;
3185
3186 error_free:
3187         bnxt_hwrm_func_buf_unrgtr(bp);
3188         return rc;
3189 }
3190
3191 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3192 {
3193         struct hwrm_func_cfg_input req = {0};
3194         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3195         int rc;
3196
3197         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3198
3199         req.fid = rte_cpu_to_le_16(0xffff);
3200         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3201         req.evb_mode = bp->pf.evb_mode;
3202
3203         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3204         HWRM_CHECK_RESULT();
3205         HWRM_UNLOCK();
3206
3207         return rc;
3208 }
3209
3210 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3211                                 uint8_t tunnel_type)
3212 {
3213         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3214         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3215         int rc = 0;
3216
3217         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3218         req.tunnel_type = tunnel_type;
3219         req.tunnel_dst_port_val = port;
3220         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3221         HWRM_CHECK_RESULT();
3222
3223         switch (tunnel_type) {
3224         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3225                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3226                 bp->vxlan_port = port;
3227                 break;
3228         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3229                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3230                 bp->geneve_port = port;
3231                 break;
3232         default:
3233                 break;
3234         }
3235
3236         HWRM_UNLOCK();
3237
3238         return rc;
3239 }
3240
3241 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3242                                 uint8_t tunnel_type)
3243 {
3244         struct hwrm_tunnel_dst_port_free_input req = {0};
3245         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3246         int rc = 0;
3247
3248         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3249
3250         req.tunnel_type = tunnel_type;
3251         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3253
3254         HWRM_CHECK_RESULT();
3255         HWRM_UNLOCK();
3256
3257         return rc;
3258 }
3259
3260 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3261                                         uint32_t flags)
3262 {
3263         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3264         struct hwrm_func_cfg_input req = {0};
3265         int rc;
3266
3267         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3268
3269         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3270         req.flags = rte_cpu_to_le_32(flags);
3271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3272
3273         HWRM_CHECK_RESULT();
3274         HWRM_UNLOCK();
3275
3276         return rc;
3277 }
3278
3279 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3280 {
3281         uint32_t *flag = flagp;
3282
3283         vnic->flags = *flag;
3284 }
3285
3286 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3287 {
3288         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3289 }
3290
3291 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3292 {
3293         int rc = 0;
3294         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3295         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3296
3297         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3298
3299         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3300         req.req_buf_page_size = rte_cpu_to_le_16(
3301                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3302         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3303         req.req_buf_page_addr0 =
3304                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3305         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3306                 PMD_DRV_LOG(ERR,
3307                         "unable to map buffer address to physical memory\n");
3308                 return -ENOMEM;
3309         }
3310
3311         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3312
3313         HWRM_CHECK_RESULT();
3314         HWRM_UNLOCK();
3315
3316         return rc;
3317 }
3318
3319 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3320 {
3321         int rc = 0;
3322         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3323         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3324
3325         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3326                 return 0;
3327
3328         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3329
3330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3331
3332         HWRM_CHECK_RESULT();
3333         HWRM_UNLOCK();
3334
3335         return rc;
3336 }
3337
3338 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3339 {
3340         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3341         struct hwrm_func_cfg_input req = {0};
3342         int rc;
3343
3344         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3345
3346         req.fid = rte_cpu_to_le_16(0xffff);
3347         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3348         req.enables = rte_cpu_to_le_32(
3349                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3350         req.async_event_cr = rte_cpu_to_le_16(
3351                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3353
3354         HWRM_CHECK_RESULT();
3355         HWRM_UNLOCK();
3356
3357         return rc;
3358 }
3359
3360 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3361 {
3362         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3363         struct hwrm_func_vf_cfg_input req = {0};
3364         int rc;
3365
3366         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3367
3368         req.enables = rte_cpu_to_le_32(
3369                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3370         req.async_event_cr = rte_cpu_to_le_16(
3371                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3373
3374         HWRM_CHECK_RESULT();
3375         HWRM_UNLOCK();
3376
3377         return rc;
3378 }
3379
3380 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3381 {
3382         struct hwrm_func_cfg_input req = {0};
3383         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3384         uint16_t dflt_vlan, fid;
3385         uint32_t func_cfg_flags;
3386         int rc = 0;
3387
3388         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3389
3390         if (is_vf) {
3391                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3392                 fid = bp->pf.vf_info[vf].fid;
3393                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3394         } else {
3395                 fid = rte_cpu_to_le_16(0xffff);
3396                 func_cfg_flags = bp->pf.func_cfg_flags;
3397                 dflt_vlan = bp->vlan;
3398         }
3399
3400         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3401         req.fid = rte_cpu_to_le_16(fid);
3402         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3403         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3404
3405         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3406
3407         HWRM_CHECK_RESULT();
3408         HWRM_UNLOCK();
3409
3410         return rc;
3411 }
3412
3413 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3414                         uint16_t max_bw, uint16_t enables)
3415 {
3416         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3417         struct hwrm_func_cfg_input req = {0};
3418         int rc;
3419
3420         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3421
3422         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3423         req.enables |= rte_cpu_to_le_32(enables);
3424         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3425         req.max_bw = rte_cpu_to_le_32(max_bw);
3426         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3427
3428         HWRM_CHECK_RESULT();
3429         HWRM_UNLOCK();
3430
3431         return rc;
3432 }
3433
3434 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3435 {
3436         struct hwrm_func_cfg_input req = {0};
3437         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3438         int rc = 0;
3439
3440         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3441
3442         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3443         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3444         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3445         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3446
3447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3448
3449         HWRM_CHECK_RESULT();
3450         HWRM_UNLOCK();
3451
3452         return rc;
3453 }
3454
3455 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3456 {
3457         int rc;
3458
3459         if (BNXT_PF(bp))
3460                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3461         else
3462                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3463
3464         return rc;
3465 }
3466
3467 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3468                               void *encaped, size_t ec_size)
3469 {
3470         int rc = 0;
3471         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3472         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3473
3474         if (ec_size > sizeof(req.encap_request))
3475                 return -1;
3476
3477         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3478
3479         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3480         memcpy(req.encap_request, encaped, ec_size);
3481
3482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3483
3484         HWRM_CHECK_RESULT();
3485         HWRM_UNLOCK();
3486
3487         return rc;
3488 }
3489
3490 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3491                                        struct rte_ether_addr *mac)
3492 {
3493         struct hwrm_func_qcfg_input req = {0};
3494         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3495         int rc;
3496
3497         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3498
3499         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3500         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3501
3502         HWRM_CHECK_RESULT();
3503
3504         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3505
3506         HWRM_UNLOCK();
3507
3508         return rc;
3509 }
3510
3511 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3512                             void *encaped, size_t ec_size)
3513 {
3514         int rc = 0;
3515         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3516         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3517
3518         if (ec_size > sizeof(req.encap_request))
3519                 return -1;
3520
3521         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3522
3523         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3524         memcpy(req.encap_request, encaped, ec_size);
3525
3526         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3527
3528         HWRM_CHECK_RESULT();
3529         HWRM_UNLOCK();
3530
3531         return rc;
3532 }
3533
3534 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3535                          struct rte_eth_stats *stats, uint8_t rx)
3536 {
3537         int rc = 0;
3538         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3539         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3540
3541         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3542
3543         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3544
3545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3546
3547         HWRM_CHECK_RESULT();
3548
3549         if (rx) {
3550                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3551                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3552                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3553                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3554                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3555                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3556                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3557                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3558         } else {
3559                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3560                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3561                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3562                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3563                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3564                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3565         }
3566
3567
3568         HWRM_UNLOCK();
3569
3570         return rc;
3571 }
3572
3573 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3574 {
3575         struct hwrm_port_qstats_input req = {0};
3576         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3577         struct bnxt_pf_info *pf = &bp->pf;
3578         int rc;
3579
3580         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3581
3582         req.port_id = rte_cpu_to_le_16(pf->port_id);
3583         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3584         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3585         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3586
3587         HWRM_CHECK_RESULT();
3588         HWRM_UNLOCK();
3589
3590         return rc;
3591 }
3592
3593 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3594 {
3595         struct hwrm_port_clr_stats_input req = {0};
3596         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3597         struct bnxt_pf_info *pf = &bp->pf;
3598         int rc;
3599
3600         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3601         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3602             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3603                 return 0;
3604
3605         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3606
3607         req.port_id = rte_cpu_to_le_16(pf->port_id);
3608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3609
3610         HWRM_CHECK_RESULT();
3611         HWRM_UNLOCK();
3612
3613         return rc;
3614 }
3615
3616 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3617 {
3618         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3619         struct hwrm_port_led_qcaps_input req = {0};
3620         int rc;
3621
3622         if (BNXT_VF(bp))
3623                 return 0;
3624
3625         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3626         req.port_id = bp->pf.port_id;
3627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3628
3629         HWRM_CHECK_RESULT();
3630
3631         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3632                 unsigned int i;
3633
3634                 bp->num_leds = resp->num_leds;
3635                 memcpy(bp->leds, &resp->led0_id,
3636                         sizeof(bp->leds[0]) * bp->num_leds);
3637                 for (i = 0; i < bp->num_leds; i++) {
3638                         struct bnxt_led_info *led = &bp->leds[i];
3639
3640                         uint16_t caps = led->led_state_caps;
3641
3642                         if (!led->led_group_id ||
3643                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3644                                 bp->num_leds = 0;
3645                                 break;
3646                         }
3647                 }
3648         }
3649
3650         HWRM_UNLOCK();
3651
3652         return rc;
3653 }
3654
3655 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3656 {
3657         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3658         struct hwrm_port_led_cfg_input req = {0};
3659         struct bnxt_led_cfg *led_cfg;
3660         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3661         uint16_t duration = 0;
3662         int rc, i;
3663
3664         if (!bp->num_leds || BNXT_VF(bp))
3665                 return -EOPNOTSUPP;
3666
3667         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3668
3669         if (led_on) {
3670                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3671                 duration = rte_cpu_to_le_16(500);
3672         }
3673         req.port_id = bp->pf.port_id;
3674         req.num_leds = bp->num_leds;
3675         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3676         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3677                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3678                 led_cfg->led_id = bp->leds[i].led_id;
3679                 led_cfg->led_state = led_state;
3680                 led_cfg->led_blink_on = duration;
3681                 led_cfg->led_blink_off = duration;
3682                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3683         }
3684
3685         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3686
3687         HWRM_CHECK_RESULT();
3688         HWRM_UNLOCK();
3689
3690         return rc;
3691 }
3692
3693 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3694                                uint32_t *length)
3695 {
3696         int rc;
3697         struct hwrm_nvm_get_dir_info_input req = {0};
3698         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3699
3700         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3701
3702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3703
3704         HWRM_CHECK_RESULT();
3705
3706         *entries = rte_le_to_cpu_32(resp->entries);
3707         *length = rte_le_to_cpu_32(resp->entry_length);
3708
3709         HWRM_UNLOCK();
3710         return rc;
3711 }
3712
3713 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3714 {
3715         int rc;
3716         uint32_t dir_entries;
3717         uint32_t entry_length;
3718         uint8_t *buf;
3719         size_t buflen;
3720         rte_iova_t dma_handle;
3721         struct hwrm_nvm_get_dir_entries_input req = {0};
3722         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3723
3724         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3725         if (rc != 0)
3726                 return rc;
3727
3728         *data++ = dir_entries;
3729         *data++ = entry_length;
3730         len -= 2;
3731         memset(data, 0xff, len);
3732
3733         buflen = dir_entries * entry_length;
3734         buf = rte_malloc("nvm_dir", buflen, 0);
3735         rte_mem_lock_page(buf);
3736         if (buf == NULL)
3737                 return -ENOMEM;
3738         dma_handle = rte_mem_virt2iova(buf);
3739         if (dma_handle == RTE_BAD_IOVA) {
3740                 PMD_DRV_LOG(ERR,
3741                         "unable to map response address to physical memory\n");
3742                 return -ENOMEM;
3743         }
3744         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3745         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3747
3748         if (rc == 0)
3749                 memcpy(data, buf, len > buflen ? buflen : len);
3750
3751         rte_free(buf);
3752         HWRM_CHECK_RESULT();
3753         HWRM_UNLOCK();
3754
3755         return rc;
3756 }
3757
3758 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3759                              uint32_t offset, uint32_t length,
3760                              uint8_t *data)
3761 {
3762         int rc;
3763         uint8_t *buf;
3764         rte_iova_t dma_handle;
3765         struct hwrm_nvm_read_input req = {0};
3766         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3767
3768         buf = rte_malloc("nvm_item", length, 0);
3769         rte_mem_lock_page(buf);
3770         if (!buf)
3771                 return -ENOMEM;
3772
3773         dma_handle = rte_mem_virt2iova(buf);
3774         if (dma_handle == RTE_BAD_IOVA) {
3775                 PMD_DRV_LOG(ERR,
3776                         "unable to map response address to physical memory\n");
3777                 return -ENOMEM;
3778         }
3779         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3780         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3781         req.dir_idx = rte_cpu_to_le_16(index);
3782         req.offset = rte_cpu_to_le_32(offset);
3783         req.len = rte_cpu_to_le_32(length);
3784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3785         if (rc == 0)
3786                 memcpy(data, buf, length);
3787
3788         rte_free(buf);
3789         HWRM_CHECK_RESULT();
3790         HWRM_UNLOCK();
3791
3792         return rc;
3793 }
3794
3795 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3796 {
3797         int rc;
3798         struct hwrm_nvm_erase_dir_entry_input req = {0};
3799         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3800
3801         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3802         req.dir_idx = rte_cpu_to_le_16(index);
3803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3804         HWRM_CHECK_RESULT();
3805         HWRM_UNLOCK();
3806
3807         return rc;
3808 }
3809
3810
3811 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3812                           uint16_t dir_ordinal, uint16_t dir_ext,
3813                           uint16_t dir_attr, const uint8_t *data,
3814                           size_t data_len)
3815 {
3816         int rc;
3817         struct hwrm_nvm_write_input req = {0};
3818         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3819         rte_iova_t dma_handle;
3820         uint8_t *buf;
3821
3822         buf = rte_malloc("nvm_write", data_len, 0);
3823         rte_mem_lock_page(buf);
3824         if (!buf)
3825                 return -ENOMEM;
3826
3827         dma_handle = rte_mem_virt2iova(buf);
3828         if (dma_handle == RTE_BAD_IOVA) {
3829                 PMD_DRV_LOG(ERR,
3830                         "unable to map response address to physical memory\n");
3831                 return -ENOMEM;
3832         }
3833         memcpy(buf, data, data_len);
3834
3835         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3836
3837         req.dir_type = rte_cpu_to_le_16(dir_type);
3838         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3839         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3840         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3841         req.dir_data_length = rte_cpu_to_le_32(data_len);
3842         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3843
3844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3845
3846         rte_free(buf);
3847         HWRM_CHECK_RESULT();
3848         HWRM_UNLOCK();
3849
3850         return rc;
3851 }
3852
3853 static void
3854 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3855 {
3856         uint32_t *count = cbdata;
3857
3858         *count = *count + 1;
3859 }
3860
3861 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3862                                      struct bnxt_vnic_info *vnic __rte_unused)
3863 {
3864         return 0;
3865 }
3866
3867 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3868 {
3869         uint32_t count = 0;
3870
3871         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3872             &count, bnxt_vnic_count_hwrm_stub);
3873
3874         return count;
3875 }
3876
3877 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3878                                         uint16_t *vnic_ids)
3879 {
3880         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3881         struct hwrm_func_vf_vnic_ids_query_output *resp =
3882                                                 bp->hwrm_cmd_resp_addr;
3883         int rc;
3884
3885         /* First query all VNIC ids */
3886         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3887
3888         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3889         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3890         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3891
3892         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3893                 HWRM_UNLOCK();
3894                 PMD_DRV_LOG(ERR,
3895                 "unable to map VNIC ID table address to physical memory\n");
3896                 return -ENOMEM;
3897         }
3898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3899         HWRM_CHECK_RESULT();
3900         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3901
3902         HWRM_UNLOCK();
3903
3904         return rc;
3905 }
3906
3907 /*
3908  * This function queries the VNIC IDs  for a specified VF. It then calls
3909  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3910  * Then it calls the hwrm_cb function to program this new vnic configuration.
3911  */
3912 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3913         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3914         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3915 {
3916         struct bnxt_vnic_info vnic;
3917         int rc = 0;
3918         int i, num_vnic_ids;
3919         uint16_t *vnic_ids;
3920         size_t vnic_id_sz;
3921         size_t sz;
3922
3923         /* First query all VNIC ids */
3924         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3925         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3926                         RTE_CACHE_LINE_SIZE);
3927         if (vnic_ids == NULL)
3928                 return -ENOMEM;
3929
3930         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3931                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3932
3933         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3934
3935         if (num_vnic_ids < 0)
3936                 return num_vnic_ids;
3937
3938         /* Retrieve VNIC, update bd_stall then update */
3939
3940         for (i = 0; i < num_vnic_ids; i++) {
3941                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3942                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3943                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3944                 if (rc)
3945                         break;
3946                 if (vnic.mru <= 4)      /* Indicates unallocated */
3947                         continue;
3948
3949                 vnic_cb(&vnic, cbdata);
3950
3951                 rc = hwrm_cb(bp, &vnic);
3952                 if (rc)
3953                         break;
3954         }
3955
3956         rte_free(vnic_ids);
3957
3958         return rc;
3959 }
3960
3961 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3962                                               bool on)
3963 {
3964         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3965         struct hwrm_func_cfg_input req = {0};
3966         int rc;
3967
3968         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3969
3970         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3971         req.enables |= rte_cpu_to_le_32(
3972                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3973         req.vlan_antispoof_mode = on ?
3974                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3975                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3977
3978         HWRM_CHECK_RESULT();
3979         HWRM_UNLOCK();
3980
3981         return rc;
3982 }
3983
3984 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3985 {
3986         struct bnxt_vnic_info vnic;
3987         uint16_t *vnic_ids;
3988         size_t vnic_id_sz;
3989         int num_vnic_ids, i;
3990         size_t sz;
3991         int rc;
3992
3993         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3994         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3995                         RTE_CACHE_LINE_SIZE);
3996         if (vnic_ids == NULL)
3997                 return -ENOMEM;
3998
3999         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4000                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4001
4002         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4003         if (rc <= 0)
4004                 goto exit;
4005         num_vnic_ids = rc;
4006
4007         /*
4008          * Loop through to find the default VNIC ID.
4009          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4010          * by sending the hwrm_func_qcfg command to the firmware.
4011          */
4012         for (i = 0; i < num_vnic_ids; i++) {
4013                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4014                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4015                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4016                                         bp->pf.first_vf_id + vf);
4017                 if (rc)
4018                         goto exit;
4019                 if (vnic.func_default) {
4020                         rte_free(vnic_ids);
4021                         return vnic.fw_vnic_id;
4022                 }
4023         }
4024         /* Could not find a default VNIC. */
4025         PMD_DRV_LOG(ERR, "No default VNIC\n");
4026 exit:
4027         rte_free(vnic_ids);
4028         return rc;
4029 }
4030
4031 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4032                          uint16_t dst_id,
4033                          struct bnxt_filter_info *filter)
4034 {
4035         int rc = 0;
4036         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4037         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4038         uint32_t enables = 0;
4039
4040         if (filter->fw_em_filter_id != UINT64_MAX)
4041                 bnxt_hwrm_clear_em_filter(bp, filter);
4042
4043         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4044
4045         req.flags = rte_cpu_to_le_32(filter->flags);
4046
4047         enables = filter->enables |
4048               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4049         req.dst_id = rte_cpu_to_le_16(dst_id);
4050
4051         if (filter->ip_addr_type) {
4052                 req.ip_addr_type = filter->ip_addr_type;
4053                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4054         }
4055         if (enables &
4056             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4057                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4058         if (enables &
4059             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4060                 memcpy(req.src_macaddr, filter->src_macaddr,
4061                        RTE_ETHER_ADDR_LEN);
4062         if (enables &
4063             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4064                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4065                        RTE_ETHER_ADDR_LEN);
4066         if (enables &
4067             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4068                 req.ovlan_vid = filter->l2_ovlan;
4069         if (enables &
4070             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4071                 req.ivlan_vid = filter->l2_ivlan;
4072         if (enables &
4073             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4074                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4075         if (enables &
4076             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4077                 req.ip_protocol = filter->ip_protocol;
4078         if (enables &
4079             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4080                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4081         if (enables &
4082             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4083                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4084         if (enables &
4085             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4086                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4087         if (enables &
4088             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4089                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4090         if (enables &
4091             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4092                 req.mirror_vnic_id = filter->mirror_vnic_id;
4093
4094         req.enables = rte_cpu_to_le_32(enables);
4095
4096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4097
4098         HWRM_CHECK_RESULT();
4099
4100         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4101         HWRM_UNLOCK();
4102
4103         return rc;
4104 }
4105
4106 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4107 {
4108         int rc = 0;
4109         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4110         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4111
4112         if (filter->fw_em_filter_id == UINT64_MAX)
4113                 return 0;
4114
4115         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4116         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4117
4118         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4119
4120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4121
4122         HWRM_CHECK_RESULT();
4123         HWRM_UNLOCK();
4124
4125         filter->fw_em_filter_id = UINT64_MAX;
4126         filter->fw_l2_filter_id = UINT64_MAX;
4127
4128         return 0;
4129 }
4130
4131 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4132                          uint16_t dst_id,
4133                          struct bnxt_filter_info *filter)
4134 {
4135         int rc = 0;
4136         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4137         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4138                                                 bp->hwrm_cmd_resp_addr;
4139         uint32_t enables = 0;
4140
4141         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4142                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4143
4144         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4145
4146         req.flags = rte_cpu_to_le_32(filter->flags);
4147
4148         enables = filter->enables |
4149               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4150         req.dst_id = rte_cpu_to_le_16(dst_id);
4151
4152
4153         if (filter->ip_addr_type) {
4154                 req.ip_addr_type = filter->ip_addr_type;
4155                 enables |=
4156                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4157         }
4158         if (enables &
4159             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4160                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4161         if (enables &
4162             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4163                 memcpy(req.src_macaddr, filter->src_macaddr,
4164                        RTE_ETHER_ADDR_LEN);
4165         //if (enables &
4166             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4167                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4168                        //RTE_ETHER_ADDR_LEN);
4169         if (enables &
4170             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4171                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4172         if (enables &
4173             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4174                 req.ip_protocol = filter->ip_protocol;
4175         if (enables &
4176             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4177                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4178         if (enables &
4179             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4180                 req.src_ipaddr_mask[0] =
4181                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4182         if (enables &
4183             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4184                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4185         if (enables &
4186             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4187                 req.dst_ipaddr_mask[0] =
4188                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4189         if (enables &
4190             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4191                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4192         if (enables &
4193             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4194                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4195         if (enables &
4196             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4197                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4198         if (enables &
4199             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4200                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4201         if (enables &
4202             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4203                 req.mirror_vnic_id = filter->mirror_vnic_id;
4204
4205         req.enables = rte_cpu_to_le_32(enables);
4206
4207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4208
4209         HWRM_CHECK_RESULT();
4210
4211         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4212         HWRM_UNLOCK();
4213
4214         return rc;
4215 }
4216
4217 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4218                                 struct bnxt_filter_info *filter)
4219 {
4220         int rc = 0;
4221         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4222         struct hwrm_cfa_ntuple_filter_free_output *resp =
4223                                                 bp->hwrm_cmd_resp_addr;
4224
4225         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4226                 return 0;
4227
4228         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4229
4230         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4231
4232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4233
4234         HWRM_CHECK_RESULT();
4235         HWRM_UNLOCK();
4236
4237         filter->fw_ntuple_filter_id = UINT64_MAX;
4238
4239         return 0;
4240 }
4241
4242 static int
4243 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4244 {
4245         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4246         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4247         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4248         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4249         uint16_t *ring_tbl = vnic->rss_table;
4250         int nr_ctxs = vnic->num_lb_ctxts;
4251         int max_rings = bp->rx_nr_rings;
4252         int i, j, k, cnt;
4253         int rc = 0;
4254
4255         for (i = 0, k = 0; i < nr_ctxs; i++) {
4256                 struct bnxt_rx_ring_info *rxr;
4257                 struct bnxt_cp_ring_info *cpr;
4258
4259                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4260
4261                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4262                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4263                 req.hash_mode_flags = vnic->hash_mode;
4264
4265                 req.ring_grp_tbl_addr =
4266                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4267                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4268                                      2 * sizeof(*ring_tbl));
4269                 req.hash_key_tbl_addr =
4270                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4271
4272                 req.ring_table_pair_index = i;
4273                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4274
4275                 for (j = 0; j < 64; j++) {
4276                         uint16_t ring_id;
4277
4278                         /* Find next active ring. */
4279                         for (cnt = 0; cnt < max_rings; cnt++) {
4280                                 if (rx_queue_state[k] !=
4281                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4282                                         break;
4283                                 if (++k == max_rings)
4284                                         k = 0;
4285                         }
4286
4287                         /* Return if no rings are active. */
4288                         if (cnt == max_rings)
4289                                 return 0;
4290
4291                         /* Add rx/cp ring pair to RSS table. */
4292                         rxr = rxqs[k]->rx_ring;
4293                         cpr = rxqs[k]->cp_ring;
4294
4295                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4296                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4297                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4298                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4299
4300                         if (++k == max_rings)
4301                                 k = 0;
4302                 }
4303                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4304                                             BNXT_USE_CHIMP_MB);
4305
4306                 HWRM_CHECK_RESULT();
4307                 HWRM_UNLOCK();
4308         }
4309
4310         return rc;
4311 }
4312
4313 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4314 {
4315         unsigned int rss_idx, fw_idx, i;
4316
4317         if (!(vnic->rss_table && vnic->hash_type))
4318                 return 0;
4319
4320         if (BNXT_CHIP_THOR(bp))
4321                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4322
4323         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4324                 return 0;
4325
4326         if (vnic->rss_table && vnic->hash_type) {
4327                 /*
4328                  * Fill the RSS hash & redirection table with
4329                  * ring group ids for all VNICs
4330                  */
4331                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4332                         rss_idx++, fw_idx++) {
4333                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4334                                 fw_idx %= bp->rx_cp_nr_rings;
4335                                 if (vnic->fw_grp_ids[fw_idx] !=
4336                                     INVALID_HW_RING_ID)
4337                                         break;
4338                                 fw_idx++;
4339                         }
4340                         if (i == bp->rx_cp_nr_rings)
4341                                 return 0;
4342                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4343                 }
4344                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4345         }
4346
4347         return 0;
4348 }
4349
4350 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4351         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4352 {
4353         uint16_t flags;
4354
4355         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4356
4357         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4358         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4359
4360         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4361         req->num_cmpl_dma_aggr_during_int =
4362                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4363
4364         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4365
4366         /* min timer set to 1/2 of interrupt timer */
4367         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4368
4369         /* buf timer set to 1/4 of interrupt timer */
4370         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4371
4372         req->cmpl_aggr_dma_tmr_during_int =
4373                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4374
4375         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4376                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4377         req->flags = rte_cpu_to_le_16(flags);
4378 }
4379
4380 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4381                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4382 {
4383         struct hwrm_ring_aggint_qcaps_input req = {0};
4384         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4385         uint32_t enables;
4386         uint16_t flags;
4387         int rc;
4388
4389         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4391         HWRM_CHECK_RESULT();
4392
4393         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4394         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4395
4396         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4397                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4398         agg_req->flags = rte_cpu_to_le_16(flags);
4399         enables =
4400          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4401          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4402         agg_req->enables = rte_cpu_to_le_32(enables);
4403
4404         HWRM_UNLOCK();
4405         return rc;
4406 }
4407
4408 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4409                         struct bnxt_coal *coal, uint16_t ring_id)
4410 {
4411         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4412         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4413                                                 bp->hwrm_cmd_resp_addr;
4414         int rc;
4415
4416         /* Set ring coalesce parameters only for 100G NICs */
4417         if (BNXT_CHIP_THOR(bp)) {
4418                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4419                         return -1;
4420         } else if (bnxt_stratus_device(bp)) {
4421                 bnxt_hwrm_set_coal_params(coal, &req);
4422         } else {
4423                 return 0;
4424         }
4425
4426         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4427         req.ring_id = rte_cpu_to_le_16(ring_id);
4428         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4429         HWRM_CHECK_RESULT();
4430         HWRM_UNLOCK();
4431         return 0;
4432 }
4433
4434 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4435 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4436 {
4437         struct hwrm_func_backing_store_qcaps_input req = {0};
4438         struct hwrm_func_backing_store_qcaps_output *resp =
4439                 bp->hwrm_cmd_resp_addr;
4440         struct bnxt_ctx_pg_info *ctx_pg;
4441         struct bnxt_ctx_mem_info *ctx;
4442         int total_alloc_len;
4443         int rc, i;
4444
4445         if (!BNXT_CHIP_THOR(bp) ||
4446             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4447             BNXT_VF(bp) ||
4448             bp->ctx)
4449                 return 0;
4450
4451         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4453         HWRM_CHECK_RESULT_SILENT();
4454
4455         total_alloc_len = sizeof(*ctx);
4456         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4457                           RTE_CACHE_LINE_SIZE);
4458         if (!ctx) {
4459                 rc = -ENOMEM;
4460                 goto ctx_err;
4461         }
4462
4463         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4464                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4465                             RTE_CACHE_LINE_SIZE);
4466         if (!ctx_pg) {
4467                 rc = -ENOMEM;
4468                 goto ctx_err;
4469         }
4470         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4471                 ctx->tqm_mem[i] = ctx_pg;
4472
4473         bp->ctx = ctx;
4474         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4475         ctx->qp_min_qp1_entries =
4476                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4477         ctx->qp_max_l2_entries =
4478                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4479         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4480         ctx->srq_max_l2_entries =
4481                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4482         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4483         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4484         ctx->cq_max_l2_entries =
4485                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4486         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4487         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4488         ctx->vnic_max_vnic_entries =
4489                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4490         ctx->vnic_max_ring_table_entries =
4491                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4492         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4493         ctx->stat_max_entries =
4494                 rte_le_to_cpu_32(resp->stat_max_entries);
4495         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4496         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4497         ctx->tqm_min_entries_per_ring =
4498                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4499         ctx->tqm_max_entries_per_ring =
4500                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4501         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4502         if (!ctx->tqm_entries_multiple)
4503                 ctx->tqm_entries_multiple = 1;
4504         ctx->mrav_max_entries =
4505                 rte_le_to_cpu_32(resp->mrav_max_entries);
4506         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4507         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4508         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4509 ctx_err:
4510         HWRM_UNLOCK();
4511         return rc;
4512 }
4513
4514 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4515 {
4516         struct hwrm_func_backing_store_cfg_input req = {0};
4517         struct hwrm_func_backing_store_cfg_output *resp =
4518                 bp->hwrm_cmd_resp_addr;
4519         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4520         struct bnxt_ctx_pg_info *ctx_pg;
4521         uint32_t *num_entries;
4522         uint64_t *pg_dir;
4523         uint8_t *pg_attr;
4524         uint32_t ena;
4525         int i, rc;
4526
4527         if (!ctx)
4528                 return 0;
4529
4530         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4531         req.enables = rte_cpu_to_le_32(enables);
4532
4533         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4534                 ctx_pg = &ctx->qp_mem;
4535                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4536                 req.qp_num_qp1_entries =
4537                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4538                 req.qp_num_l2_entries =
4539                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4540                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4541                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4542                                       &req.qpc_pg_size_qpc_lvl,
4543                                       &req.qpc_page_dir);
4544         }
4545
4546         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4547                 ctx_pg = &ctx->srq_mem;
4548                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4549                 req.srq_num_l2_entries =
4550                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4551                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4552                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4553                                       &req.srq_pg_size_srq_lvl,
4554                                       &req.srq_page_dir);
4555         }
4556
4557         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4558                 ctx_pg = &ctx->cq_mem;
4559                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4560                 req.cq_num_l2_entries =
4561                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4562                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4563                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4564                                       &req.cq_pg_size_cq_lvl,
4565                                       &req.cq_page_dir);
4566         }
4567
4568         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4569                 ctx_pg = &ctx->vnic_mem;
4570                 req.vnic_num_vnic_entries =
4571                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4572                 req.vnic_num_ring_table_entries =
4573                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4574                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4575                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4576                                       &req.vnic_pg_size_vnic_lvl,
4577                                       &req.vnic_page_dir);
4578         }
4579
4580         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4581                 ctx_pg = &ctx->stat_mem;
4582                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4583                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4584                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4585                                       &req.stat_pg_size_stat_lvl,
4586                                       &req.stat_page_dir);
4587         }
4588
4589         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4590         num_entries = &req.tqm_sp_num_entries;
4591         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4592         pg_dir = &req.tqm_sp_page_dir;
4593         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4594         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4595                 if (!(enables & ena))
4596                         continue;
4597
4598                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4599
4600                 ctx_pg = ctx->tqm_mem[i];
4601                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4602                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4603         }
4604
4605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4606         HWRM_CHECK_RESULT();
4607         HWRM_UNLOCK();
4608
4609         return rc;
4610 }
4611
4612 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4613 {
4614         struct hwrm_port_qstats_ext_input req = {0};
4615         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4616         struct bnxt_pf_info *pf = &bp->pf;
4617         int rc;
4618
4619         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4620               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4621                 return 0;
4622
4623         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4624
4625         req.port_id = rte_cpu_to_le_16(pf->port_id);
4626         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4627                 req.tx_stat_host_addr =
4628                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4629                 req.tx_stat_size =
4630                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4631         }
4632         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4633                 req.rx_stat_host_addr =
4634                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4635                 req.rx_stat_size =
4636                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4637         }
4638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4639
4640         if (rc) {
4641                 bp->fw_rx_port_stats_ext_size = 0;
4642                 bp->fw_tx_port_stats_ext_size = 0;
4643         } else {
4644                 bp->fw_rx_port_stats_ext_size =
4645                         rte_le_to_cpu_16(resp->rx_stat_size);
4646                 bp->fw_tx_port_stats_ext_size =
4647                         rte_le_to_cpu_16(resp->tx_stat_size);
4648         }
4649
4650         HWRM_CHECK_RESULT();
4651         HWRM_UNLOCK();
4652
4653         return rc;
4654 }
4655
4656 int
4657 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4658 {
4659         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4660         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4661                 bp->hwrm_cmd_resp_addr;
4662         int rc = 0;
4663
4664         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4665         req.tunnel_type = type;
4666         req.dest_fid = bp->fw_fid;
4667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4668         HWRM_CHECK_RESULT();
4669
4670         HWRM_UNLOCK();
4671
4672         return rc;
4673 }
4674
4675 int
4676 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4677 {
4678         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4679         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4680                 bp->hwrm_cmd_resp_addr;
4681         int rc = 0;
4682
4683         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4684         req.tunnel_type = type;
4685         req.dest_fid = bp->fw_fid;
4686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4687         HWRM_CHECK_RESULT();
4688
4689         HWRM_UNLOCK();
4690
4691         return rc;
4692 }
4693
4694 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4695 {
4696         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4697         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4698                 bp->hwrm_cmd_resp_addr;
4699         int rc = 0;
4700
4701         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4702         req.src_fid = bp->fw_fid;
4703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4704         HWRM_CHECK_RESULT();
4705
4706         if (type)
4707                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4708
4709         HWRM_UNLOCK();
4710
4711         return rc;
4712 }
4713
4714 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4715                                    uint16_t *dst_fid)
4716 {
4717         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4718         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4719                 bp->hwrm_cmd_resp_addr;
4720         int rc = 0;
4721
4722         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4723         req.src_fid = bp->fw_fid;
4724         req.tunnel_type = tun_type;
4725         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4726         HWRM_CHECK_RESULT();
4727
4728         if (dst_fid)
4729                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4730
4731         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4732
4733         HWRM_UNLOCK();
4734
4735         return rc;
4736 }
4737
4738 int bnxt_hwrm_set_mac(struct bnxt *bp)
4739 {
4740         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4741         struct hwrm_func_vf_cfg_input req = {0};
4742         int rc = 0;
4743
4744         if (!BNXT_VF(bp))
4745                 return 0;
4746
4747         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4748
4749         req.enables =
4750                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4751         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4752
4753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4754
4755         HWRM_CHECK_RESULT();
4756
4757         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4758         HWRM_UNLOCK();
4759
4760         return rc;
4761 }
4762
4763 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4764 {
4765         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4766         struct hwrm_func_drv_if_change_input req = {0};
4767         uint32_t flags;
4768         int rc;
4769
4770         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4771                 return 0;
4772
4773         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4774          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4775          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4776          */
4777         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4778                 return 0;
4779
4780         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4781
4782         if (up)
4783                 req.flags =
4784                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4785
4786         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4787
4788         HWRM_CHECK_RESULT();
4789         flags = rte_le_to_cpu_32(resp->flags);
4790         HWRM_UNLOCK();
4791
4792         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4793                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4794                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4795         }
4796
4797         return 0;
4798 }
4799
4800 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4801 {
4802         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4803         struct bnxt_error_recovery_info *info = bp->recovery_info;
4804         struct hwrm_error_recovery_qcfg_input req = {0};
4805         uint32_t flags = 0;
4806         unsigned int i;
4807         int rc;
4808
4809         /* Older FW does not have error recovery support */
4810         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4811                 return 0;
4812
4813         if (!info) {
4814                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4815                                    sizeof(*info), 0);
4816                 bp->recovery_info = info;
4817                 if (info == NULL)
4818                         return -ENOMEM;
4819         } else {
4820                 memset(info, 0, sizeof(*info));
4821         }
4822
4823         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4824
4825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4826
4827         HWRM_CHECK_RESULT();
4828
4829         flags = rte_le_to_cpu_32(resp->flags);
4830         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4831                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4832         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4833                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4834
4835         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4836             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4837                 rc = -EINVAL;
4838                 goto err;
4839         }
4840
4841         /* FW returned values are in units of 100msec */
4842         info->driver_polling_freq =
4843                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4844         info->master_func_wait_period =
4845                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4846         info->normal_func_wait_period =
4847                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4848         info->master_func_wait_period_after_reset =
4849                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4850         info->max_bailout_time_after_reset =
4851                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4852         info->status_regs[BNXT_FW_STATUS_REG] =
4853                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4854         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4855                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4856         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4857                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4858         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4859                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4860         info->reg_array_cnt =
4861                 rte_le_to_cpu_32(resp->reg_array_cnt);
4862
4863         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4864                 rc = -EINVAL;
4865                 goto err;
4866         }
4867
4868         for (i = 0; i < info->reg_array_cnt; i++) {
4869                 info->reset_reg[i] =
4870                         rte_le_to_cpu_32(resp->reset_reg[i]);
4871                 info->reset_reg_val[i] =
4872                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4873                 info->delay_after_reset[i] =
4874                         resp->delay_after_reset[i];
4875         }
4876 err:
4877         HWRM_UNLOCK();
4878
4879         /* Map the FW status registers */
4880         if (!rc)
4881                 rc = bnxt_map_fw_health_status_regs(bp);
4882
4883         if (rc) {
4884                 rte_free(bp->recovery_info);
4885                 bp->recovery_info = NULL;
4886         }
4887         return rc;
4888 }
4889
4890 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4891 {
4892         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4893         struct hwrm_fw_reset_input req = {0};
4894         int rc;
4895
4896         if (!BNXT_PF(bp))
4897                 return -EOPNOTSUPP;
4898
4899         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4900
4901         req.embedded_proc_type =
4902                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4903         req.selfrst_status =
4904                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4905         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4906
4907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4908                                     BNXT_USE_KONG(bp));
4909
4910         HWRM_CHECK_RESULT();
4911         HWRM_UNLOCK();
4912
4913         return rc;
4914 }
4915
4916 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4917 {
4918         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4919         struct hwrm_port_ts_query_input req = {0};
4920         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4921         uint32_t flags = 0;
4922         int rc;
4923
4924         if (!ptp)
4925                 return 0;
4926
4927         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4928
4929         switch (path) {
4930         case BNXT_PTP_FLAGS_PATH_TX:
4931                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4932                 break;
4933         case BNXT_PTP_FLAGS_PATH_RX:
4934                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4935                 break;
4936         case BNXT_PTP_FLAGS_CURRENT_TIME:
4937                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4938                 break;
4939         }
4940
4941         req.flags = rte_cpu_to_le_32(flags);
4942         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4943
4944         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4945
4946         HWRM_CHECK_RESULT();
4947
4948         if (timestamp) {
4949                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4950                 *timestamp |=
4951                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4952         }
4953         HWRM_UNLOCK();
4954
4955         return rc;
4956 }
4957
4958 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
4959 {
4960         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
4961                                         bp->hwrm_cmd_resp_addr;
4962         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
4963         uint32_t flags = 0;
4964         int rc = 0;
4965
4966         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
4967                 return rc;
4968
4969         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
4970                 PMD_DRV_LOG(DEBUG,
4971                             "Not a PF or trusted VF. Command not supported\n");
4972                 return 0;
4973         }
4974
4975         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
4976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4977
4978         HWRM_CHECK_RESULT();
4979         flags = rte_le_to_cpu_32(resp->flags);
4980         HWRM_UNLOCK();
4981
4982         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
4983                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
4984                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
4985         }
4986
4987         return rc;
4988 }