drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 674 {
 675         int rc = 0;
 676         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 677         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 678         uint16_t new_max_vfs;
 679         uint32_t flags;
 680         int i;
 681
 682         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 683
 684         req.fid = rte_cpu_to_le_16(0xffff);
 685
 686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 687
 688         HWRM_CHECK_RESULT();
 689
 690         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 691         flags = rte_le_to_cpu_32(resp->flags);
 692         if (BNXT_PF(bp)) {
 693                 bp->pf->port_id = resp->port_id;
 694                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 695                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 696                 new_max_vfs = bp->pdev->max_vfs;
 697                 if (new_max_vfs != bp->pf->max_vfs) {
 698                         if (bp->pf->vf_info)
 699                                 rte_free(bp->pf->vf_info);
 700                         bp->pf->vf_info = rte_malloc("bnxt_vf_info",
 701                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 702                         bp->pf->max_vfs = new_max_vfs;
 703                         for (i = 0; i < new_max_vfs; i++) {
 704                                 bp->pf->vf_info[i].fid =
 705                                         bp->pf->first_vf_id + i;
 706                                 bp->pf->vf_info[i].vlan_table =
 707                                         rte_zmalloc("VF VLAN table",
 708                                                     getpagesize(),
 709                                                     getpagesize());
 710                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 711                                         PMD_DRV_LOG(ERR,
 712                                         "Fail to alloc VLAN table for VF %d\n",
 713                                         i);
 714                                 else
 715                                         rte_mem_lock_page(
 716                                                 bp->pf->vf_info[i].vlan_table);
 717                                 bp->pf->vf_info[i].vlan_as_table =
 718                                         rte_zmalloc("VF VLAN AS table",
 719                                                     getpagesize(),
 720                                                     getpagesize());
 721                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 722                                         PMD_DRV_LOG(ERR,
 723                                         "Alloc VLAN AS table for VF %d fail\n",
 724                                         i);
 725                                 else
 726                                         rte_mem_lock_page(
 727                                               bp->pf->vf_info[i].vlan_as_table);
 728                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 729                         }
 730                 }
 731         }
 732
 733         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 734         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 735                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 736                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 737         } else {
 738                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 739         }
 740         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 741         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 742         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 743         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 744         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 745         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 746         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 747         if (!BNXT_CHIP_THOR(bp))
 748                 bp->max_l2_ctx += bp->max_rx_em_flows;
 749         /* TODO: For now, do not support VMDq/RFS on VFs. */
 750         if (BNXT_PF(bp)) {
 751                 if (bp->pf->max_vfs)
 752                         bp->max_vnics = 1;
 753                 else
 754                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 755         } else {
 756                 bp->max_vnics = 1;
 757         }
 758         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 759                     bp->max_l2_ctx, bp->max_vnics);
 760         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 761         if (BNXT_PF(bp)) {
 762                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 763                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 764                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 765                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 766                         HWRM_UNLOCK();
 767                         bnxt_hwrm_ptp_qcfg(bp);
 768                 }
 769         }
 770
 771         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 772                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 773
 774         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 775                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 776                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 777         }
 778
 779         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 780                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 781
 782         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 783                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 784
 785         HWRM_UNLOCK();
 786
 787         return rc;
 788 }
 789
 790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 791 {
 792         int rc;
 793
 794         rc = __bnxt_hwrm_func_qcaps(bp);
 795         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 796                 rc = bnxt_alloc_ctx_mem(bp);
 797                 if (rc)
 798                         return rc;
 799
 800                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 801                 if (!rc)
 802                         bp->flags |= BNXT_FLAG_NEW_RM;
 803         }
 804
 805         /* On older FW,
 806          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 807          * But the error can be ignored. Return success.
 808          */
 809
 810         return 0;
 811 }
 812
 813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 815 {
 816         int rc = 0;
 817         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 818         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 819
 820         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 821
 822         req.target_id = rte_cpu_to_le_16(0xffff);
 823
 824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 825
 826         HWRM_CHECK_RESULT();
 827
 828         if (rte_le_to_cpu_32(resp->flags) &
 829             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 830                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 831                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 832         }
 833
 834         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 835
 836         HWRM_UNLOCK();
 837
 838         return rc;
 839 }
 840
 841 int bnxt_hwrm_func_reset(struct bnxt *bp)
 842 {
 843         int rc = 0;
 844         struct hwrm_func_reset_input req = {.req_type = 0 };
 845         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 846
 847         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 848
 849         req.enables = rte_cpu_to_le_32(0);
 850
 851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 852
 853         HWRM_CHECK_RESULT();
 854         HWRM_UNLOCK();
 855
 856         return rc;
 857 }
 858
 859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 860 {
 861         int rc;
 862         uint32_t flags = 0;
 863         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 864         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 865
 866         if (bp->flags & BNXT_FLAG_REGISTERED)
 867                 return 0;
 868
 869         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 870                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 871         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 872                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 873
 874         /* PFs and trusted VFs should indicate the support of the
 875          * Master capability on non Stingray platform
 876          */
 877         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 878                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 879
 880         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 881         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 882                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 883         req.ver_maj = RTE_VER_YEAR;
 884         req.ver_min = RTE_VER_MONTH;
 885         req.ver_upd = RTE_VER_MINOR;
 886
 887         if (BNXT_PF(bp)) {
 888                 req.enables |= rte_cpu_to_le_32(
 889                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 890                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 891                        RTE_MIN(sizeof(req.vf_req_fwd),
 892                                sizeof(bp->pf->vf_req_fwd)));
 893
 894                 /*
 895                  * PF can sniff HWRM API issued by VF. This can be set up by
 896                  * linux driver and inherited by the DPDK PF driver. Clear
 897                  * this HWRM sniffer list in FW because DPDK PF driver does
 898                  * not support this.
 899                  */
 900                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 901         }
 902
 903         req.flags = rte_cpu_to_le_32(flags);
 904
 905         req.async_event_fwd[0] |=
 906                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 907                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 908                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 909                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 910                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 911         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 912                 req.async_event_fwd[0] |=
 913                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 914         req.async_event_fwd[1] |=
 915                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 916                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 917         if (BNXT_PF(bp))
 918                 req.async_event_fwd[1] |=
 919                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 920
 921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 922
 923         HWRM_CHECK_RESULT();
 924
 925         flags = rte_le_to_cpu_32(resp->flags);
 926         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 927                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 928
 929         HWRM_UNLOCK();
 930
 931         bp->flags |= BNXT_FLAG_REGISTERED;
 932
 933         return rc;
 934 }
 935
 936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 937 {
 938         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 939                 return 0;
 940
 941         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 942 }
 943
 944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 945 {
 946         int rc;
 947         uint32_t flags = 0;
 948         uint32_t enables;
 949         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 950         struct hwrm_func_vf_cfg_input req = {0};
 951
 952         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 953
 954         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 955                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 956                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 957                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 958                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 959
 960         if (BNXT_HAS_RING_GRPS(bp)) {
 961                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 962                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 963         }
 964
 965         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 966         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 967                                             AGG_RING_MULTIPLIER);
 968         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 969         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 970                                               bp->tx_nr_rings +
 971                                               BNXT_NUM_ASYNC_CPR(bp));
 972         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 973         if (bp->vf_resv_strategy ==
 974             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 975                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 976                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 977                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 978                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 979                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 980                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 981         } else if (bp->vf_resv_strategy ==
 982                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 983                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 984                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 985         }
 986
 987         if (test)
 988                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 989                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 990                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 991                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 992                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 993                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 994
 995         if (test && BNXT_HAS_RING_GRPS(bp))
 996                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 997
 998         req.flags = rte_cpu_to_le_32(flags);
 999         req.enables |= rte_cpu_to_le_32(enables);
1000
1001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1002
1003         if (test)
1004                 HWRM_CHECK_RESULT_SILENT();
1005         else
1006                 HWRM_CHECK_RESULT();
1007
1008         HWRM_UNLOCK();
1009         return rc;
1010 }
1011
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1013 {
1014         int rc;
1015         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016         struct hwrm_func_resource_qcaps_input req = {0};
1017
1018         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019         req.fid = rte_cpu_to_le_16(0xffff);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT_SILENT();
1024
1025         if (BNXT_VF(bp)) {
1026                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031                 /* func_resource_qcaps does not return max_rx_em_flows.
1032                  * So use the value provided by func_qcaps.
1033                  */
1034                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035                 if (!BNXT_CHIP_THOR(bp))
1036                         bp->max_l2_ctx += bp->max_rx_em_flows;
1037                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1039         }
1040         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042         if (bp->vf_resv_strategy >
1043             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044                 bp->vf_resv_strategy =
1045                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1046
1047         HWRM_UNLOCK();
1048         return rc;
1049 }
1050
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1052 {
1053         int rc = 0;
1054         struct hwrm_ver_get_input req = {.req_type = 0 };
1055         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056         uint32_t fw_version;
1057         uint16_t max_resp_len;
1058         char type[RTE_MEMZONE_NAMESIZE];
1059         uint32_t dev_caps_cfg;
1060
1061         bp->max_req_len = HWRM_MAX_REQ_LEN;
1062         bp->hwrm_cmd_timeout = timeout;
1063         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1064
1065         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1068
1069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1070
1071         if (bp->flags & BNXT_FLAG_FW_RESET)
1072                 HWRM_CHECK_RESULT_SILENT();
1073         else
1074                 HWRM_CHECK_RESULT();
1075
1076         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081                      (resp->hwrm_fw_min_8b << 16) |
1082                      (resp->hwrm_fw_bld_8b << 8) |
1083                      resp->hwrm_fw_rsvd_8b;
1084         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1086
1087         fw_version = resp->hwrm_intf_maj_8b << 16;
1088         fw_version |= resp->hwrm_intf_min_8b << 8;
1089         fw_version |= resp->hwrm_intf_upd_8b;
1090         bp->hwrm_spec_code = fw_version;
1091
1092         /* def_req_timeout value is in milliseconds */
1093         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094         /* convert timeout to usec */
1095         bp->hwrm_cmd_timeout *= 1000;
1096         if (!bp->hwrm_cmd_timeout)
1097                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1098
1099         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1101                 rc = -EINVAL;
1102                 goto error;
1103         }
1104
1105         if (bp->max_req_len > resp->max_req_win_len) {
1106                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1107                 rc = -EINVAL;
1108         }
1109         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1113
1114         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1116
1117         if (bp->max_resp_len != max_resp_len) {
1118                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1120                         bp->pdev->addr.devid, bp->pdev->addr.function);
1121
1122                 rte_free(bp->hwrm_cmd_resp_addr);
1123
1124                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125                 if (bp->hwrm_cmd_resp_addr == NULL) {
1126                         rc = -ENOMEM;
1127                         goto error;
1128                 }
1129                 bp->hwrm_cmd_resp_dma_addr =
1130                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1132                         PMD_DRV_LOG(ERR,
1133                         "Unable to map response buffer to physical memory.\n");
1134                         rc = -ENOMEM;
1135                         goto error;
1136                 }
1137                 bp->max_resp_len = max_resp_len;
1138         }
1139
1140         if ((dev_caps_cfg &
1141                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1142             (dev_caps_cfg &
1143              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1146         }
1147
1148         if (((dev_caps_cfg &
1149               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1150              (dev_caps_cfg &
1151               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1155                         bp->pdev->addr.devid, bp->pdev->addr.function);
1156
1157                 rte_free(bp->hwrm_short_cmd_req_addr);
1158
1159                 bp->hwrm_short_cmd_req_addr =
1160                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1162                         rc = -ENOMEM;
1163                         goto error;
1164                 }
1165                 bp->hwrm_short_cmd_req_dma_addr =
1166                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168                         rte_free(bp->hwrm_short_cmd_req_addr);
1169                         PMD_DRV_LOG(ERR,
1170                                 "Unable to map buffer to physical memory.\n");
1171                         rc = -ENOMEM;
1172                         goto error;
1173                 }
1174         }
1175         if (dev_caps_cfg &
1176             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1179         }
1180         if (dev_caps_cfg &
1181             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1183         if (dev_caps_cfg &
1184             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1187         }
1188
1189         if (dev_caps_cfg &
1190             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1193         }
1194
1195
1196 error:
1197         HWRM_UNLOCK();
1198         return rc;
1199 }
1200
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1202 {
1203         int rc;
1204         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1206
1207         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1208                 return 0;
1209
1210         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1211         req.flags = flags;
1212
1213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1214
1215         HWRM_CHECK_RESULT();
1216         HWRM_UNLOCK();
1217
1218         return rc;
1219 }
1220
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1222 {
1223         int rc = 0;
1224         struct hwrm_port_phy_cfg_input req = {0};
1225         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226         uint32_t enables = 0;
1227
1228         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1229
1230         if (conf->link_up) {
1231                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232                 if (bp->link_info->auto_mode && conf->link_speed) {
1233                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1235                 }
1236
1237                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1240                 /*
1241                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242                  * any auto mode, even "none".
1243                  */
1244                 if (!conf->link_speed) {
1245                         /* No speeds specified. Enable AutoNeg - all speeds */
1246                         req.auto_mode =
1247                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1248                 }
1249                 /* AutoNeg - Advertise speeds specified. */
1250                 if (conf->auto_link_speed_mask &&
1251                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1252                         req.auto_mode =
1253                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254                         req.auto_link_speed_mask =
1255                                 conf->auto_link_speed_mask;
1256                         enables |=
1257                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1258                 }
1259
1260                 req.auto_duplex = conf->duplex;
1261                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262                 req.auto_pause = conf->auto_pause;
1263                 req.force_pause = conf->force_pause;
1264                 /* Set force_pause if there is no auto or if there is a force */
1265                 if (req.auto_pause && !req.force_pause)
1266                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1267                 else
1268                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1269
1270                 req.enables = rte_cpu_to_le_32(enables);
1271         } else {
1272                 req.flags =
1273                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1275         }
1276
1277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279         HWRM_CHECK_RESULT();
1280         HWRM_UNLOCK();
1281
1282         return rc;
1283 }
1284
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286                                    struct bnxt_link_info *link_info)
1287 {
1288         int rc = 0;
1289         struct hwrm_port_phy_qcfg_input req = {0};
1290         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1291
1292         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1293
1294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1295
1296         HWRM_CHECK_RESULT();
1297
1298         link_info->phy_link_status = resp->link;
1299         link_info->link_up =
1300                 (link_info->phy_link_status ==
1301                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303         link_info->duplex = resp->duplex_cfg;
1304         link_info->pause = resp->pause;
1305         link_info->auto_pause = resp->auto_pause;
1306         link_info->force_pause = resp->force_pause;
1307         link_info->auto_mode = resp->auto_mode;
1308         link_info->phy_type = resp->phy_type;
1309         link_info->media_type = resp->media_type;
1310
1311         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315         link_info->phy_ver[0] = resp->phy_maj;
1316         link_info->phy_ver[1] = resp->phy_min;
1317         link_info->phy_ver[2] = resp->phy_bld;
1318
1319         HWRM_UNLOCK();
1320
1321         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326                     link_info->auto_link_speed_mask);
1327         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328                     link_info->force_link_speed);
1329
1330         return rc;
1331 }
1332
1333 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1334 {
1335         int i = 0;
1336
1337         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1338                 if (bp->tx_cos_queue[i].profile ==
1339                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1340                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1341                         return true;
1342                 }
1343         }
1344         return false;
1345 }
1346
1347 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1348 {
1349         int i = 0;
1350
1351         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1352                 if (bp->tx_cos_queue[i].profile !=
1353                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1354                     bp->tx_cos_queue[i].id !=
1355                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1356                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1357                         break;
1358                 }
1359         }
1360 }
1361
1362 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1363 {
1364         int rc = 0;
1365         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1366         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1367         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1368         int i;
1369
1370 get_rx_info:
1371         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1372
1373         req.flags = rte_cpu_to_le_32(dir);
1374         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1375         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1376             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1377                 req.drv_qmap_cap =
1378                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380
1381         HWRM_CHECK_RESULT();
1382
1383         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1384                 GET_TX_QUEUE_INFO(0);
1385                 GET_TX_QUEUE_INFO(1);
1386                 GET_TX_QUEUE_INFO(2);
1387                 GET_TX_QUEUE_INFO(3);
1388                 GET_TX_QUEUE_INFO(4);
1389                 GET_TX_QUEUE_INFO(5);
1390                 GET_TX_QUEUE_INFO(6);
1391                 GET_TX_QUEUE_INFO(7);
1392         } else  {
1393                 GET_RX_QUEUE_INFO(0);
1394                 GET_RX_QUEUE_INFO(1);
1395                 GET_RX_QUEUE_INFO(2);
1396                 GET_RX_QUEUE_INFO(3);
1397                 GET_RX_QUEUE_INFO(4);
1398                 GET_RX_QUEUE_INFO(5);
1399                 GET_RX_QUEUE_INFO(6);
1400                 GET_RX_QUEUE_INFO(7);
1401         }
1402
1403         HWRM_UNLOCK();
1404
1405         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1406                 goto done;
1407
1408         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1409                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1410         } else {
1411                 int j;
1412
1413                 /* iterate and find the COSq profile to use for Tx */
1414                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1415                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1416                                 if (bp->tx_cos_queue[i].id != 0xff)
1417                                         bp->tx_cosq_id[j++] =
1418                                                 bp->tx_cos_queue[i].id;
1419                         }
1420                 } else {
1421                         /* When CoS classification is disabled, for normal NIC
1422                          * operations, ideally we should look to use LOSSY.
1423                          * If not found, fallback to the first valid profile
1424                          */
1425                         if (!bnxt_find_lossy_profile(bp))
1426                                 bnxt_find_first_valid_profile(bp);
1427
1428                 }
1429         }
1430
1431         bp->max_tc = resp->max_configurable_queues;
1432         bp->max_lltc = resp->max_configurable_lossless_queues;
1433         if (bp->max_tc > BNXT_MAX_QUEUE)
1434                 bp->max_tc = BNXT_MAX_QUEUE;
1435         bp->max_q = bp->max_tc;
1436
1437         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1438                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1439                 goto get_rx_info;
1440         }
1441
1442 done:
1443         return rc;
1444 }
1445
1446 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1447                          struct bnxt_ring *ring,
1448                          uint32_t ring_type, uint32_t map_index,
1449                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1450                          uint16_t tx_cosq_id)
1451 {
1452         int rc = 0;
1453         uint32_t enables = 0;
1454         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1455         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1456         struct rte_mempool *mb_pool;
1457         uint16_t rx_buf_size;
1458
1459         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1460
1461         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1462         req.fbo = rte_cpu_to_le_32(0);
1463         /* Association of ring index with doorbell index */
1464         req.logical_id = rte_cpu_to_le_16(map_index);
1465         req.length = rte_cpu_to_le_32(ring->ring_size);
1466
1467         switch (ring_type) {
1468         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1469                 req.ring_type = ring_type;
1470                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1471                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1472                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1473                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1474                         enables |=
1475                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1476                 break;
1477         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1478                 req.ring_type = ring_type;
1479                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1480                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1481                 if (BNXT_CHIP_THOR(bp)) {
1482                         mb_pool = bp->rx_queues[0]->mb_pool;
1483                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1484                                       RTE_PKTMBUF_HEADROOM;
1485                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1486                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1487                         enables |=
1488                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1489                 }
1490                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1491                         enables |=
1492                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1493                 break;
1494         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1495                 req.ring_type = ring_type;
1496                 if (BNXT_HAS_NQ(bp)) {
1497                         /* Association of cp ring with nq */
1498                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1499                         enables |=
1500                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1501                 }
1502                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1503                 break;
1504         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1505                 req.ring_type = ring_type;
1506                 req.page_size = BNXT_PAGE_SHFT;
1507                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1508                 break;
1509         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1510                 req.ring_type = ring_type;
1511                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1512
1513                 mb_pool = bp->rx_queues[0]->mb_pool;
1514                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1515                               RTE_PKTMBUF_HEADROOM;
1516                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1517                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1518
1519                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1520                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1521                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1522                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1523                 break;
1524         default:
1525                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1526                         ring_type);
1527                 HWRM_UNLOCK();
1528                 return -EINVAL;
1529         }
1530         req.enables = rte_cpu_to_le_32(enables);
1531
1532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1533
1534         if (rc || resp->error_code) {
1535                 if (rc == 0 && resp->error_code)
1536                         rc = rte_le_to_cpu_16(resp->error_code);
1537                 switch (ring_type) {
1538                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1539                         PMD_DRV_LOG(ERR,
1540                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1541                         HWRM_UNLOCK();
1542                         return rc;
1543                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1544                         PMD_DRV_LOG(ERR,
1545                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1546                         HWRM_UNLOCK();
1547                         return rc;
1548                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1549                         PMD_DRV_LOG(ERR,
1550                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1551                                     rc);
1552                         HWRM_UNLOCK();
1553                         return rc;
1554                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1555                         PMD_DRV_LOG(ERR,
1556                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1557                         HWRM_UNLOCK();
1558                         return rc;
1559                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1560                         PMD_DRV_LOG(ERR,
1561                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1562                         HWRM_UNLOCK();
1563                         return rc;
1564                 default:
1565                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1566                         HWRM_UNLOCK();
1567                         return rc;
1568                 }
1569         }
1570
1571         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1572         HWRM_UNLOCK();
1573         return rc;
1574 }
1575
1576 int bnxt_hwrm_ring_free(struct bnxt *bp,
1577                         struct bnxt_ring *ring, uint32_t ring_type)
1578 {
1579         int rc;
1580         struct hwrm_ring_free_input req = {.req_type = 0 };
1581         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1582
1583         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1584
1585         req.ring_type = ring_type;
1586         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1587
1588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1589
1590         if (rc || resp->error_code) {
1591                 if (rc == 0 && resp->error_code)
1592                         rc = rte_le_to_cpu_16(resp->error_code);
1593                 HWRM_UNLOCK();
1594
1595                 switch (ring_type) {
1596                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1597                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1598                                 rc);
1599                         return rc;
1600                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1601                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1602                                 rc);
1603                         return rc;
1604                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1605                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1606                                 rc);
1607                         return rc;
1608                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1609                         PMD_DRV_LOG(ERR,
1610                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1611                         return rc;
1612                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1613                         PMD_DRV_LOG(ERR,
1614                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1615                         return rc;
1616                 default:
1617                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1618                         return rc;
1619                 }
1620         }
1621         HWRM_UNLOCK();
1622         return 0;
1623 }
1624
1625 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1626 {
1627         int rc = 0;
1628         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1629         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630
1631         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1632
1633         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1634         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1635         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1636         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1637
1638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1639
1640         HWRM_CHECK_RESULT();
1641
1642         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1643
1644         HWRM_UNLOCK();
1645
1646         return rc;
1647 }
1648
1649 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1650 {
1651         int rc;
1652         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1653         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1654
1655         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1656
1657         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1658
1659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1660
1661         HWRM_CHECK_RESULT();
1662         HWRM_UNLOCK();
1663
1664         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1665         return rc;
1666 }
1667
1668 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1669 {
1670         int rc = 0;
1671         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1672         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1673
1674         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1675                 return rc;
1676
1677         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1678
1679         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1680
1681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1682
1683         HWRM_CHECK_RESULT();
1684         HWRM_UNLOCK();
1685
1686         return rc;
1687 }
1688
1689 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1690                                 unsigned int idx __rte_unused)
1691 {
1692         int rc;
1693         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1694         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1695
1696         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1697
1698         req.update_period_ms = rte_cpu_to_le_32(0);
1699
1700         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1701
1702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703
1704         HWRM_CHECK_RESULT();
1705
1706         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1707
1708         HWRM_UNLOCK();
1709
1710         return rc;
1711 }
1712
1713 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1714                                 unsigned int idx __rte_unused)
1715 {
1716         int rc;
1717         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1718         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1719
1720         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1721
1722         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1723
1724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1725
1726         HWRM_CHECK_RESULT();
1727         HWRM_UNLOCK();
1728
1729         return rc;
1730 }
1731
1732 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1733 {
1734         int rc = 0, i, j;
1735         struct hwrm_vnic_alloc_input req = { 0 };
1736         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1737
1738         if (!BNXT_HAS_RING_GRPS(bp))
1739                 goto skip_ring_grps;
1740
1741         /* map ring groups to this vnic */
1742         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1743                 vnic->start_grp_id, vnic->end_grp_id);
1744         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1745                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1746
1747         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1748         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1749         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1750         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1751
1752 skip_ring_grps:
1753         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1754         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1755
1756         if (vnic->func_default)
1757                 req.flags =
1758                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1760
1761         HWRM_CHECK_RESULT();
1762
1763         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1764         HWRM_UNLOCK();
1765         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1766         return rc;
1767 }
1768
1769 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1770                                         struct bnxt_vnic_info *vnic,
1771                                         struct bnxt_plcmodes_cfg *pmode)
1772 {
1773         int rc = 0;
1774         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1775         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1776
1777         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1778
1779         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1780
1781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1782
1783         HWRM_CHECK_RESULT();
1784
1785         pmode->flags = rte_le_to_cpu_32(resp->flags);
1786         /* dflt_vnic bit doesn't exist in the _cfg command */
1787         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1788         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1789         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1790         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1791
1792         HWRM_UNLOCK();
1793
1794         return rc;
1795 }
1796
1797 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1798                                        struct bnxt_vnic_info *vnic,
1799                                        struct bnxt_plcmodes_cfg *pmode)
1800 {
1801         int rc = 0;
1802         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1803         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1804
1805         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1806                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1807                 return rc;
1808         }
1809
1810         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1811
1812         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1813         req.flags = rte_cpu_to_le_32(pmode->flags);
1814         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1815         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1816         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1817         req.enables = rte_cpu_to_le_32(
1818             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1819             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1820             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1821         );
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824
1825         HWRM_CHECK_RESULT();
1826         HWRM_UNLOCK();
1827
1828         return rc;
1829 }
1830
1831 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1832 {
1833         int rc = 0;
1834         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1835         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1836         struct bnxt_plcmodes_cfg pmodes = { 0 };
1837         uint32_t ctx_enable_flag = 0;
1838         uint32_t enables = 0;
1839
1840         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1841                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1842                 return rc;
1843         }
1844
1845         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1846         if (rc)
1847                 return rc;
1848
1849         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1850
1851         if (BNXT_CHIP_THOR(bp)) {
1852                 int dflt_rxq = vnic->start_grp_id;
1853                 struct bnxt_rx_ring_info *rxr;
1854                 struct bnxt_cp_ring_info *cpr;
1855                 struct bnxt_rx_queue *rxq;
1856                 int i;
1857
1858                 /*
1859                  * The first active receive ring is used as the VNIC
1860                  * default receive ring. If there are no active receive
1861                  * rings (all corresponding receive queues are stopped),
1862                  * the first receive ring is used.
1863                  */
1864                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1865                         rxq = bp->eth_dev->data->rx_queues[i];
1866                         if (rxq->rx_started) {
1867                                 dflt_rxq = i;
1868                                 break;
1869                         }
1870                 }
1871
1872                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1873                 rxr = rxq->rx_ring;
1874                 cpr = rxq->cp_ring;
1875
1876                 req.default_rx_ring_id =
1877                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1878                 req.default_cmpl_ring_id =
1879                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1880                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1881                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1882                 goto config_mru;
1883         }
1884
1885         /* Only RSS support for now TBD: COS & LB */
1886         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1887         if (vnic->lb_rule != 0xffff)
1888                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1889         if (vnic->cos_rule != 0xffff)
1890                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1891         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1892                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1893                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1894         }
1895         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1896                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1897                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1898         }
1899
1900         enables |= ctx_enable_flag;
1901         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1902         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1903         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1904         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1905
1906 config_mru:
1907         req.enables = rte_cpu_to_le_32(enables);
1908         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1909         req.mru = rte_cpu_to_le_16(vnic->mru);
1910         /* Configure default VNIC only once. */
1911         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1912                 req.flags |=
1913                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1914                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1915         }
1916         if (vnic->vlan_strip)
1917                 req.flags |=
1918                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1919         if (vnic->bd_stall)
1920                 req.flags |=
1921                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1922         if (vnic->roce_dual)
1923                 req.flags |= rte_cpu_to_le_32(
1924                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1925         if (vnic->roce_only)
1926                 req.flags |= rte_cpu_to_le_32(
1927                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1928         if (vnic->rss_dflt_cr)
1929                 req.flags |= rte_cpu_to_le_32(
1930                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935         HWRM_UNLOCK();
1936
1937         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1938
1939         return rc;
1940 }
1941
1942 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1943                 int16_t fw_vf_id)
1944 {
1945         int rc = 0;
1946         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1947         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1950                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1951                 return rc;
1952         }
1953         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1954
1955         req.enables =
1956                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1957         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1958         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1959
1960         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1961
1962         HWRM_CHECK_RESULT();
1963
1964         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1965         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1966         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1967         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1968         vnic->mru = rte_le_to_cpu_16(resp->mru);
1969         vnic->func_default = rte_le_to_cpu_32(
1970                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1971         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1972                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1973         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1974                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1975         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1976                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1977         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1978                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1979         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1980                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1981
1982         HWRM_UNLOCK();
1983
1984         return rc;
1985 }
1986
1987 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1988                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1989 {
1990         int rc = 0;
1991         uint16_t ctx_id;
1992         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1993         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1994                                                 bp->hwrm_cmd_resp_addr;
1995
1996         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1997
1998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999         HWRM_CHECK_RESULT();
2000
2001         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2002         if (!BNXT_HAS_RING_GRPS(bp))
2003                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2004         else if (ctx_idx == 0)
2005                 vnic->rss_rule = ctx_id;
2006
2007         HWRM_UNLOCK();
2008
2009         return rc;
2010 }
2011
2012 static
2013 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2014                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2015 {
2016         int rc = 0;
2017         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2018         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2019                                                 bp->hwrm_cmd_resp_addr;
2020
2021         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2022                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2023                 return rc;
2024         }
2025         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2026
2027         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2028
2029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2030
2031         HWRM_CHECK_RESULT();
2032         HWRM_UNLOCK();
2033
2034         return rc;
2035 }
2036
2037 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2038 {
2039         int rc = 0;
2040
2041         if (BNXT_CHIP_THOR(bp)) {
2042                 int j;
2043
2044                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2045                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2046                                                       vnic,
2047                                                       vnic->fw_grp_ids[j]);
2048                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2049                 }
2050                 vnic->num_lb_ctxts = 0;
2051         } else {
2052                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2053                 vnic->rss_rule = INVALID_HW_RING_ID;
2054         }
2055
2056         return rc;
2057 }
2058
2059 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2060 {
2061         int rc = 0;
2062         struct hwrm_vnic_free_input req = {.req_type = 0 };
2063         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2064
2065         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2066                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2067                 return rc;
2068         }
2069
2070         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2071
2072         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2073
2074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075
2076         HWRM_CHECK_RESULT();
2077         HWRM_UNLOCK();
2078
2079         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2080         /* Configure default VNIC again if necessary. */
2081         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2082                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2083
2084         return rc;
2085 }
2086
2087 static int
2088 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2089 {
2090         int i;
2091         int rc = 0;
2092         int nr_ctxs = vnic->num_lb_ctxts;
2093         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2094         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2095
2096         for (i = 0; i < nr_ctxs; i++) {
2097                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2098
2099                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2100                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2101                 req.hash_mode_flags = vnic->hash_mode;
2102
2103                 req.hash_key_tbl_addr =
2104                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2105
2106                 req.ring_grp_tbl_addr =
2107                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2108                                          i * HW_HASH_INDEX_SIZE);
2109                 req.ring_table_pair_index = i;
2110                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2111
2112                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2113                                             BNXT_USE_CHIMP_MB);
2114
2115                 HWRM_CHECK_RESULT();
2116                 HWRM_UNLOCK();
2117         }
2118
2119         return rc;
2120 }
2121
2122 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2123                            struct bnxt_vnic_info *vnic)
2124 {
2125         int rc = 0;
2126         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2127         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2128
2129         if (!vnic->rss_table)
2130                 return 0;
2131
2132         if (BNXT_CHIP_THOR(bp))
2133                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2134
2135         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2136
2137         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2138         req.hash_mode_flags = vnic->hash_mode;
2139
2140         req.ring_grp_tbl_addr =
2141             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2142         req.hash_key_tbl_addr =
2143             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2144         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2145         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2146
2147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2148
2149         HWRM_CHECK_RESULT();
2150         HWRM_UNLOCK();
2151
2152         return rc;
2153 }
2154
2155 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2156                         struct bnxt_vnic_info *vnic)
2157 {
2158         int rc = 0;
2159         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2160         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2161         uint16_t size;
2162
2163         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2164                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2165                 return rc;
2166         }
2167
2168         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2169
2170         req.flags = rte_cpu_to_le_32(
2171                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2172
2173         req.enables = rte_cpu_to_le_32(
2174                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2175
2176         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2177         size -= RTE_PKTMBUF_HEADROOM;
2178         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2179
2180         req.jumbo_thresh = rte_cpu_to_le_16(size);
2181         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2182
2183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2184
2185         HWRM_CHECK_RESULT();
2186         HWRM_UNLOCK();
2187
2188         return rc;
2189 }
2190
2191 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2192                         struct bnxt_vnic_info *vnic, bool enable)
2193 {
2194         int rc = 0;
2195         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2196         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2197
2198         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2199                 if (enable)
2200                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2201                 return -ENOTSUP;
2202         }
2203
2204         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2205                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2206                 return 0;
2207         }
2208
2209         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2210
2211         if (enable) {
2212                 req.enables = rte_cpu_to_le_32(
2213                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2214                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2215                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2216                 req.flags = rte_cpu_to_le_32(
2217                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2218                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2219                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2220                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2221                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2222                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2223                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2224                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2225                 req.min_agg_len = rte_cpu_to_le_32(512);
2226         }
2227         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2228
2229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2230
2231         HWRM_CHECK_RESULT();
2232         HWRM_UNLOCK();
2233
2234         return rc;
2235 }
2236
2237 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2238 {
2239         struct hwrm_func_cfg_input req = {0};
2240         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2241         int rc;
2242
2243         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2244         req.enables = rte_cpu_to_le_32(
2245                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2246         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2247         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2248
2249         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2250
2251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252         HWRM_CHECK_RESULT();
2253         HWRM_UNLOCK();
2254
2255         bp->pf->vf_info[vf].random_mac = false;
2256
2257         return rc;
2258 }
2259
2260 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2261                                   uint64_t *dropped)
2262 {
2263         int rc = 0;
2264         struct hwrm_func_qstats_input req = {.req_type = 0};
2265         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2266
2267         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2268
2269         req.fid = rte_cpu_to_le_16(fid);
2270
2271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2272
2273         HWRM_CHECK_RESULT();
2274
2275         if (dropped)
2276                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2277
2278         HWRM_UNLOCK();
2279
2280         return rc;
2281 }
2282
2283 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2284                           struct rte_eth_stats *stats,
2285                           struct hwrm_func_qstats_output *func_qstats)
2286 {
2287         int rc = 0;
2288         struct hwrm_func_qstats_input req = {.req_type = 0};
2289         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2290
2291         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2292
2293         req.fid = rte_cpu_to_le_16(fid);
2294
2295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2296
2297         HWRM_CHECK_RESULT();
2298         if (func_qstats)
2299                 memcpy(func_qstats, resp,
2300                        sizeof(struct hwrm_func_qstats_output));
2301
2302         if (!stats)
2303                 goto exit;
2304
2305         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2306         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2307         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2308         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2309         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2310         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2311
2312         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2313         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2314         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2315         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2316         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2317         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2318
2319         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2320         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2321         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2322
2323 exit:
2324         HWRM_UNLOCK();
2325
2326         return rc;
2327 }
2328
2329 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2330 {
2331         int rc = 0;
2332         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2333         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2334
2335         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2336
2337         req.fid = rte_cpu_to_le_16(fid);
2338
2339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2340
2341         HWRM_CHECK_RESULT();
2342         HWRM_UNLOCK();
2343
2344         return rc;
2345 }
2346
2347 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2348 {
2349         unsigned int i;
2350         int rc = 0;
2351
2352         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2353                 struct bnxt_tx_queue *txq;
2354                 struct bnxt_rx_queue *rxq;
2355                 struct bnxt_cp_ring_info *cpr;
2356
2357                 if (i >= bp->rx_cp_nr_rings) {
2358                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2359                         cpr = txq->cp_ring;
2360                 } else {
2361                         rxq = bp->rx_queues[i];
2362                         cpr = rxq->cp_ring;
2363                 }
2364
2365                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2366                 if (rc)
2367                         return rc;
2368         }
2369         return 0;
2370 }
2371
2372 static int
2373 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2374 {
2375         int rc;
2376         unsigned int i;
2377         struct bnxt_cp_ring_info *cpr;
2378
2379         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2380
2381                 if (i >= bp->rx_cp_nr_rings) {
2382                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2383                 } else {
2384                         cpr = bp->rx_queues[i]->cp_ring;
2385                         if (BNXT_HAS_RING_GRPS(bp))
2386                                 bp->grp_info[i].fw_stats_ctx = -1;
2387                 }
2388                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2389                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2390                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2391                         if (rc)
2392                                 return rc;
2393                 }
2394         }
2395         return 0;
2396 }
2397
2398 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2399 {
2400         unsigned int i;
2401         int rc = 0;
2402
2403         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2404                 struct bnxt_tx_queue *txq;
2405                 struct bnxt_rx_queue *rxq;
2406                 struct bnxt_cp_ring_info *cpr;
2407
2408                 if (i >= bp->rx_cp_nr_rings) {
2409                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2410                         cpr = txq->cp_ring;
2411                 } else {
2412                         rxq = bp->rx_queues[i];
2413                         cpr = rxq->cp_ring;
2414                 }
2415
2416                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2417
2418                 if (rc)
2419                         return rc;
2420         }
2421         return rc;
2422 }
2423
2424 static int
2425 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2426 {
2427         uint16_t idx;
2428         uint32_t rc = 0;
2429
2430         if (!BNXT_HAS_RING_GRPS(bp))
2431                 return 0;
2432
2433         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2434
2435                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2436                         continue;
2437
2438                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2439
2440                 if (rc)
2441                         return rc;
2442         }
2443         return rc;
2444 }
2445
2446 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2447 {
2448         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2449
2450         bnxt_hwrm_ring_free(bp, cp_ring,
2451                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2452         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2453         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2454                                      sizeof(*cpr->cp_desc_ring));
2455         cpr->cp_raw_cons = 0;
2456         cpr->valid = 0;
2457 }
2458
2459 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2460 {
2461         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2462
2463         bnxt_hwrm_ring_free(bp, cp_ring,
2464                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2465         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2466         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2467                         sizeof(*cpr->cp_desc_ring));
2468         cpr->cp_raw_cons = 0;
2469         cpr->valid = 0;
2470 }
2471
2472 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2473 {
2474         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2475         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2476         struct bnxt_ring *ring = rxr->rx_ring_struct;
2477         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2478
2479         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2480                 bnxt_hwrm_ring_free(bp, ring,
2481                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2482                 ring->fw_ring_id = INVALID_HW_RING_ID;
2483                 if (BNXT_HAS_RING_GRPS(bp))
2484                         bp->grp_info[queue_index].rx_fw_ring_id =
2485                                                         INVALID_HW_RING_ID;
2486         }
2487         ring = rxr->ag_ring_struct;
2488         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2489                 bnxt_hwrm_ring_free(bp, ring,
2490                                     BNXT_CHIP_THOR(bp) ?
2491                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2492                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2493                 if (BNXT_HAS_RING_GRPS(bp))
2494                         bp->grp_info[queue_index].ag_fw_ring_id =
2495                                                         INVALID_HW_RING_ID;
2496         }
2497         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2498                 bnxt_free_cp_ring(bp, cpr);
2499
2500         if (BNXT_HAS_RING_GRPS(bp))
2501                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2502 }
2503
2504 static int
2505 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2506 {
2507         unsigned int i;
2508
2509         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2510                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2511                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2512                 struct bnxt_ring *ring = txr->tx_ring_struct;
2513                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2514
2515                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2516                         bnxt_hwrm_ring_free(bp, ring,
2517                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2518                         ring->fw_ring_id = INVALID_HW_RING_ID;
2519                         memset(txr->tx_desc_ring, 0,
2520                                         txr->tx_ring_struct->ring_size *
2521                                         sizeof(*txr->tx_desc_ring));
2522                         memset(txr->tx_buf_ring, 0,
2523                                         txr->tx_ring_struct->ring_size *
2524                                         sizeof(*txr->tx_buf_ring));
2525                         txr->tx_prod = 0;
2526                         txr->tx_cons = 0;
2527                 }
2528                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2529                         bnxt_free_cp_ring(bp, cpr);
2530                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2531                 }
2532         }
2533
2534         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2535                 bnxt_free_hwrm_rx_ring(bp, i);
2536
2537         return 0;
2538 }
2539
2540 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2541 {
2542         uint16_t i;
2543         uint32_t rc = 0;
2544
2545         if (!BNXT_HAS_RING_GRPS(bp))
2546                 return 0;
2547
2548         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2549                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2550                 if (rc)
2551                         return rc;
2552         }
2553         return rc;
2554 }
2555
2556 /*
2557  * HWRM utility functions
2558  */
2559
2560 void bnxt_free_hwrm_resources(struct bnxt *bp)
2561 {
2562         /* Release memzone */
2563         rte_free(bp->hwrm_cmd_resp_addr);
2564         rte_free(bp->hwrm_short_cmd_req_addr);
2565         bp->hwrm_cmd_resp_addr = NULL;
2566         bp->hwrm_short_cmd_req_addr = NULL;
2567         bp->hwrm_cmd_resp_dma_addr = 0;
2568         bp->hwrm_short_cmd_req_dma_addr = 0;
2569 }
2570
2571 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2572 {
2573         struct rte_pci_device *pdev = bp->pdev;
2574         char type[RTE_MEMZONE_NAMESIZE];
2575
2576         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2578         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2579         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2580         if (bp->hwrm_cmd_resp_addr == NULL)
2581                 return -ENOMEM;
2582         bp->hwrm_cmd_resp_dma_addr =
2583                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2584         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2585                 PMD_DRV_LOG(ERR,
2586                         "unable to map response address to physical memory\n");
2587                 return -ENOMEM;
2588         }
2589         rte_spinlock_init(&bp->hwrm_lock);
2590
2591         return 0;
2592 }
2593
2594 static int
2595 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2596 {
2597         struct bnxt_filter_info *filter;
2598         int rc = 0;
2599
2600         STAILQ_FOREACH(filter, &vnic->filter, next) {
2601                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2602                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2603                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2604                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2605                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2606                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2607                 bnxt_free_filter(bp, filter);
2608         }
2609         return rc;
2610 }
2611
2612 static int
2613 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2614 {
2615         struct bnxt_filter_info *filter;
2616         struct rte_flow *flow;
2617         int rc = 0;
2618
2619         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2620                 flow = STAILQ_FIRST(&vnic->flow_list);
2621                 filter = flow->filter;
2622                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2623                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2624                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2625                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2626                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2628
2629                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2630                 rte_free(flow);
2631         }
2632         return rc;
2633 }
2634
2635 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2636 {
2637         struct bnxt_filter_info *filter;
2638         int rc = 0;
2639
2640         STAILQ_FOREACH(filter, &vnic->filter, next) {
2641                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2642                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2643                                                      filter);
2644                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2645                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2646                                                          filter);
2647                 else
2648                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2649                                                      filter);
2650                 if (rc)
2651                         break;
2652         }
2653         return rc;
2654 }
2655
2656 static void
2657 bnxt_free_tunnel_ports(struct bnxt *bp)
2658 {
2659         if (bp->vxlan_port_cnt)
2660                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2661                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2662         bp->vxlan_port = 0;
2663         if (bp->geneve_port_cnt)
2664                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2665                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2666         bp->geneve_port = 0;
2667 }
2668
2669 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2670 {
2671         int i;
2672
2673         if (bp->vnic_info == NULL)
2674                 return;
2675
2676         /*
2677          * Cleanup VNICs in reverse order, to make sure the L2 filter
2678          * from vnic0 is last to be cleaned up.
2679          */
2680         for (i = bp->max_vnics - 1; i >= 0; i--) {
2681                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2682
2683                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2684                         continue;
2685
2686                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2687
2688                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2689
2690                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2691
2692                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2693
2694                 bnxt_hwrm_vnic_free(bp, vnic);
2695
2696                 rte_free(vnic->fw_grp_ids);
2697         }
2698         /* Ring resources */
2699         bnxt_free_all_hwrm_rings(bp);
2700         bnxt_free_all_hwrm_ring_grps(bp);
2701         bnxt_free_all_hwrm_stat_ctxs(bp);
2702         bnxt_free_tunnel_ports(bp);
2703 }
2704
2705 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2706 {
2707         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2708
2709         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2710                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2711
2712         switch (conf_link_speed) {
2713         case ETH_LINK_SPEED_10M_HD:
2714         case ETH_LINK_SPEED_100M_HD:
2715                 /* FALLTHROUGH */
2716                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2717         }
2718         return hw_link_duplex;
2719 }
2720
2721 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2722 {
2723         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2724 }
2725
2726 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2727 {
2728         uint16_t eth_link_speed = 0;
2729
2730         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2731                 return ETH_LINK_SPEED_AUTONEG;
2732
2733         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2734         case ETH_LINK_SPEED_100M:
2735         case ETH_LINK_SPEED_100M_HD:
2736                 /* FALLTHROUGH */
2737                 eth_link_speed =
2738                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2739                 break;
2740         case ETH_LINK_SPEED_1G:
2741                 eth_link_speed =
2742                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2743                 break;
2744         case ETH_LINK_SPEED_2_5G:
2745                 eth_link_speed =
2746                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2747                 break;
2748         case ETH_LINK_SPEED_10G:
2749                 eth_link_speed =
2750                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2751                 break;
2752         case ETH_LINK_SPEED_20G:
2753                 eth_link_speed =
2754                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2755                 break;
2756         case ETH_LINK_SPEED_25G:
2757                 eth_link_speed =
2758                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2759                 break;
2760         case ETH_LINK_SPEED_40G:
2761                 eth_link_speed =
2762                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2763                 break;
2764         case ETH_LINK_SPEED_50G:
2765                 eth_link_speed =
2766                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2767                 break;
2768         case ETH_LINK_SPEED_100G:
2769                 eth_link_speed =
2770                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2771                 break;
2772         case ETH_LINK_SPEED_200G:
2773                 eth_link_speed =
2774                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2775                 break;
2776         default:
2777                 PMD_DRV_LOG(ERR,
2778                         "Unsupported link speed %d; default to AUTO\n",
2779                         conf_link_speed);
2780                 break;
2781         }
2782         return eth_link_speed;
2783 }
2784
2785 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2786                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2787                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2788                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2789                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2790
2791 static int bnxt_validate_link_speed(struct bnxt *bp)
2792 {
2793         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2794         uint16_t port_id = bp->eth_dev->data->port_id;
2795         uint32_t link_speed_capa;
2796         uint32_t one_speed;
2797
2798         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2799                 return 0;
2800
2801         link_speed_capa = bnxt_get_speed_capabilities(bp);
2802
2803         if (link_speed & ETH_LINK_SPEED_FIXED) {
2804                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2805
2806                 if (one_speed & (one_speed - 1)) {
2807                         PMD_DRV_LOG(ERR,
2808                                 "Invalid advertised speeds (%u) for port %u\n",
2809                                 link_speed, port_id);
2810                         return -EINVAL;
2811                 }
2812                 if ((one_speed & link_speed_capa) != one_speed) {
2813                         PMD_DRV_LOG(ERR,
2814                                 "Unsupported advertised speed (%u) for port %u\n",
2815                                 link_speed, port_id);
2816                         return -EINVAL;
2817                 }
2818         } else {
2819                 if (!(link_speed & link_speed_capa)) {
2820                         PMD_DRV_LOG(ERR,
2821                                 "Unsupported advertised speeds (%u) for port %u\n",
2822                                 link_speed, port_id);
2823                         return -EINVAL;
2824                 }
2825         }
2826         return 0;
2827 }
2828
2829 static uint16_t
2830 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2831 {
2832         uint16_t ret = 0;
2833
2834         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2835                 if (bp->link_info->support_speeds)
2836                         return bp->link_info->support_speeds;
2837                 link_speed = BNXT_SUPPORTED_SPEEDS;
2838         }
2839
2840         if (link_speed & ETH_LINK_SPEED_100M)
2841                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2842         if (link_speed & ETH_LINK_SPEED_100M_HD)
2843                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2844         if (link_speed & ETH_LINK_SPEED_1G)
2845                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2846         if (link_speed & ETH_LINK_SPEED_2_5G)
2847                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2848         if (link_speed & ETH_LINK_SPEED_10G)
2849                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2850         if (link_speed & ETH_LINK_SPEED_20G)
2851                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2852         if (link_speed & ETH_LINK_SPEED_25G)
2853                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2854         if (link_speed & ETH_LINK_SPEED_40G)
2855                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2856         if (link_speed & ETH_LINK_SPEED_50G)
2857                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2858         if (link_speed & ETH_LINK_SPEED_100G)
2859                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2860         if (link_speed & ETH_LINK_SPEED_200G)
2861                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2862         return ret;
2863 }
2864
2865 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2866 {
2867         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2868
2869         switch (hw_link_speed) {
2870         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2871                 eth_link_speed = ETH_SPEED_NUM_100M;
2872                 break;
2873         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2874                 eth_link_speed = ETH_SPEED_NUM_1G;
2875                 break;
2876         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2877                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2878                 break;
2879         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2880                 eth_link_speed = ETH_SPEED_NUM_10G;
2881                 break;
2882         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2883                 eth_link_speed = ETH_SPEED_NUM_20G;
2884                 break;
2885         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2886                 eth_link_speed = ETH_SPEED_NUM_25G;
2887                 break;
2888         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2889                 eth_link_speed = ETH_SPEED_NUM_40G;
2890                 break;
2891         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2892                 eth_link_speed = ETH_SPEED_NUM_50G;
2893                 break;
2894         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2895                 eth_link_speed = ETH_SPEED_NUM_100G;
2896                 break;
2897         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2898                 eth_link_speed = ETH_SPEED_NUM_200G;
2899                 break;
2900         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2901         default:
2902                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2903                         hw_link_speed);
2904                 break;
2905         }
2906         return eth_link_speed;
2907 }
2908
2909 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2910 {
2911         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2912
2913         switch (hw_link_duplex) {
2914         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2915         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2916                 /* FALLTHROUGH */
2917                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2918                 break;
2919         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2920                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2921                 break;
2922         default:
2923                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2924                         hw_link_duplex);
2925                 break;
2926         }
2927         return eth_link_duplex;
2928 }
2929
2930 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2931 {
2932         int rc = 0;
2933         struct bnxt_link_info *link_info = bp->link_info;
2934
2935         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2936         if (rc) {
2937                 PMD_DRV_LOG(ERR,
2938                         "Get link config failed with rc %d\n", rc);
2939                 goto exit;
2940         }
2941         if (link_info->link_speed)
2942                 link->link_speed =
2943                         bnxt_parse_hw_link_speed(link_info->link_speed);
2944         else
2945                 link->link_speed = ETH_SPEED_NUM_NONE;
2946         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2947         link->link_status = link_info->link_up;
2948         link->link_autoneg = link_info->auto_mode ==
2949                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2950                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2951 exit:
2952         return rc;
2953 }
2954
2955 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2956 {
2957         int rc = 0;
2958         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2959         struct bnxt_link_info link_req;
2960         uint16_t speed, autoneg;
2961
2962         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2963                 return 0;
2964
2965         rc = bnxt_validate_link_speed(bp);
2966         if (rc)
2967                 goto error;
2968
2969         memset(&link_req, 0, sizeof(link_req));
2970         link_req.link_up = link_up;
2971         if (!link_up)
2972                 goto port_phy_cfg;
2973
2974         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2975         if (BNXT_CHIP_THOR(bp) &&
2976             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2977                 /* 40G is not supported as part of media auto detect.
2978                  * The speed should be forced and autoneg disabled
2979                  * to configure 40G speed.
2980                  */
2981                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2982                 autoneg = 0;
2983         }
2984
2985         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2986         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2987         /* Autoneg can be done only when the FW allows.
2988          * When user configures fixed speed of 40G and later changes to
2989          * any other speed, auto_link_speed/force_link_speed is still set
2990          * to 40G until link comes up at new speed.
2991          */
2992         if (autoneg == 1 &&
2993             !(!BNXT_CHIP_THOR(bp) &&
2994               (bp->link_info->auto_link_speed ||
2995                bp->link_info->force_link_speed))) {
2996                 link_req.phy_flags |=
2997                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2998                 link_req.auto_link_speed_mask =
2999                         bnxt_parse_eth_link_speed_mask(bp,
3000                                                        dev_conf->link_speeds);
3001         } else {
3002                 if (bp->link_info->phy_type ==
3003                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3004                     bp->link_info->phy_type ==
3005                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3006                     bp->link_info->media_type ==
3007                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3008                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3009                         return -EINVAL;
3010                 }
3011
3012                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3013                 /* If user wants a particular speed try that first. */
3014                 if (speed)
3015                         link_req.link_speed = speed;
3016                 else if (bp->link_info->force_link_speed)
3017                         link_req.link_speed = bp->link_info->force_link_speed;
3018                 else
3019                         link_req.link_speed = bp->link_info->auto_link_speed;
3020         }
3021         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3022         link_req.auto_pause = bp->link_info->auto_pause;
3023         link_req.force_pause = bp->link_info->force_pause;
3024
3025 port_phy_cfg:
3026         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3027         if (rc) {
3028                 PMD_DRV_LOG(ERR,
3029                         "Set link config failed with rc %d\n", rc);
3030         }
3031
3032 error:
3033         return rc;
3034 }
3035
3036 /* JIRA 22088 */
3037 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3038 {
3039         struct hwrm_func_qcfg_input req = {0};
3040         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3041         uint16_t flags;
3042         int rc = 0;
3043         bp->func_svif = BNXT_SVIF_INVALID;
3044         uint16_t svif_info;
3045
3046         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3047         req.fid = rte_cpu_to_le_16(0xffff);
3048
3049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3050
3051         HWRM_CHECK_RESULT();
3052
3053         /* Hard Coded.. 0xfff VLAN ID mask */
3054         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3055
3056         svif_info = rte_le_to_cpu_16(resp->svif_info);
3057         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3058                 bp->func_svif = svif_info &
3059                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3060
3061         flags = rte_le_to_cpu_16(resp->flags);
3062         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3063                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3064
3065         if (BNXT_VF(bp) &&
3066             !BNXT_VF_IS_TRUSTED(bp) &&
3067             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3068                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3069                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3070         } else if (BNXT_VF(bp) &&
3071                    BNXT_VF_IS_TRUSTED(bp) &&
3072                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3073                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3074                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3075         }
3076
3077         if (mtu)
3078                 *mtu = rte_le_to_cpu_16(resp->mtu);
3079
3080         switch (resp->port_partition_type) {
3081         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3082         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3083         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3084                 /* FALLTHROUGH */
3085                 bp->flags |= BNXT_FLAG_NPAR_PF;
3086                 break;
3087         default:
3088                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3089                 break;
3090         }
3091
3092         HWRM_UNLOCK();
3093
3094         return rc;
3095 }
3096
3097 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3098 {
3099         struct hwrm_port_mac_qcfg_input req = {0};
3100         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3101         uint16_t port_svif_info;
3102         int rc;
3103
3104         bp->port_svif = BNXT_SVIF_INVALID;
3105
3106         if (!BNXT_PF(bp))
3107                 return 0;
3108
3109         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3110
3111         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3112
3113         HWRM_CHECK_RESULT();
3114
3115         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3116         if (port_svif_info &
3117             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3118                 bp->port_svif = port_svif_info &
3119                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3120
3121         HWRM_UNLOCK();
3122
3123         return 0;
3124 }
3125
3126 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3127                                    struct hwrm_func_qcaps_output *qcaps)
3128 {
3129         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3130         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3131                sizeof(qcaps->mac_address));
3132         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3133         qcaps->max_rx_rings = fcfg->num_rx_rings;
3134         qcaps->max_tx_rings = fcfg->num_tx_rings;
3135         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3136         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3137         qcaps->max_vfs = 0;
3138         qcaps->first_vf_id = 0;
3139         qcaps->max_vnics = fcfg->num_vnics;
3140         qcaps->max_decap_records = 0;
3141         qcaps->max_encap_records = 0;
3142         qcaps->max_tx_wm_flows = 0;
3143         qcaps->max_tx_em_flows = 0;
3144         qcaps->max_rx_wm_flows = 0;
3145         qcaps->max_rx_em_flows = 0;
3146         qcaps->max_flow_id = 0;
3147         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3148         qcaps->max_sp_tx_rings = 0;
3149         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3150 }
3151
3152 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3153 {
3154         struct hwrm_func_cfg_input req = {0};
3155         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3156         uint32_t enables;
3157         int rc;
3158
3159         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3160                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3161                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3162                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3163                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3164                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3165                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3166                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3167                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3168
3169         if (BNXT_HAS_RING_GRPS(bp)) {
3170                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3171                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3172         } else if (BNXT_HAS_NQ(bp)) {
3173                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3174                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3175         }
3176
3177         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3178         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3179         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3180         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3181         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3182         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3183         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3184         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3185         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3186         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3187         req.fid = rte_cpu_to_le_16(0xffff);
3188         req.enables = rte_cpu_to_le_32(enables);
3189
3190         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3191
3192         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3193
3194         HWRM_CHECK_RESULT();
3195         HWRM_UNLOCK();
3196
3197         return rc;
3198 }
3199
3200 static void populate_vf_func_cfg_req(struct bnxt *bp,
3201                                      struct hwrm_func_cfg_input *req,
3202                                      int num_vfs)
3203 {
3204         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3205                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3206                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3207                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3208                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3209                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3210                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3211                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3212                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3213                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3214
3215         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3216                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3217                                     BNXT_NUM_VLANS);
3218         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3219         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3220                                                 (num_vfs + 1));
3221         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3222         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3223                                                (num_vfs + 1));
3224         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3225         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3226         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3227         /* TODO: For now, do not support VMDq/RFS on VFs. */
3228         req->num_vnics = rte_cpu_to_le_16(1);
3229         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3230                                                  (num_vfs + 1));
3231 }
3232
3233 static void add_random_mac_if_needed(struct bnxt *bp,
3234                                      struct hwrm_func_cfg_input *cfg_req,
3235                                      int vf)
3236 {
3237         struct rte_ether_addr mac;
3238
3239         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3240                 return;
3241
3242         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3243                 cfg_req->enables |=
3244                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3245                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3246                 bp->pf->vf_info[vf].random_mac = true;
3247         } else {
3248                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3249                         RTE_ETHER_ADDR_LEN);
3250         }
3251 }
3252
3253 static int reserve_resources_from_vf(struct bnxt *bp,
3254                                      struct hwrm_func_cfg_input *cfg_req,
3255                                      int vf)
3256 {
3257         struct hwrm_func_qcaps_input req = {0};
3258         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3259         int rc;
3260
3261         /* Get the actual allocated values now */
3262         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3263         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3264         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3265
3266         if (rc) {
3267                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3268                 copy_func_cfg_to_qcaps(cfg_req, resp);
3269         } else if (resp->error_code) {
3270                 rc = rte_le_to_cpu_16(resp->error_code);
3271                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3272                 copy_func_cfg_to_qcaps(cfg_req, resp);
3273         }
3274
3275         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3276         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3277         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3278         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3279         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3280         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3281         /*
3282          * TODO: While not supporting VMDq with VFs, max_vnics is always
3283          * forced to 1 in this case
3284          */
3285         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3286         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3287
3288         HWRM_UNLOCK();
3289
3290         return 0;
3291 }
3292
3293 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3294 {
3295         struct hwrm_func_qcfg_input req = {0};
3296         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3297         int rc;
3298
3299         /* Check for zero MAC address */
3300         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3301         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3302         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3303         HWRM_CHECK_RESULT();
3304         rc = rte_le_to_cpu_16(resp->vlan);
3305
3306         HWRM_UNLOCK();
3307
3308         return rc;
3309 }
3310
3311 static int update_pf_resource_max(struct bnxt *bp)
3312 {
3313         struct hwrm_func_qcfg_input req = {0};
3314         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3315         int rc;
3316
3317         /* And copy the allocated numbers into the pf struct */
3318         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3319         req.fid = rte_cpu_to_le_16(0xffff);
3320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3321         HWRM_CHECK_RESULT();
3322
3323         /* Only TX ring value reflects actual allocation? TODO */
3324         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3325         bp->pf->evb_mode = resp->evb_mode;
3326
3327         HWRM_UNLOCK();
3328
3329         return rc;
3330 }
3331
3332 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3333 {
3334         int rc;
3335
3336         if (!BNXT_PF(bp)) {
3337                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3338                 return -EINVAL;
3339         }
3340
3341         rc = bnxt_hwrm_func_qcaps(bp);
3342         if (rc)
3343                 return rc;
3344
3345         bp->pf->func_cfg_flags &=
3346                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3347                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3348         bp->pf->func_cfg_flags |=
3349                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3350         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3351         rc = __bnxt_hwrm_func_qcaps(bp);
3352         return rc;
3353 }
3354
3355 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3356 {
3357         struct hwrm_func_cfg_input req = {0};
3358         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3359         int i;
3360         size_t sz;
3361         int rc = 0;
3362         size_t req_buf_sz;
3363
3364         if (!BNXT_PF(bp)) {
3365                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3366                 return -EINVAL;
3367         }
3368
3369         rc = bnxt_hwrm_func_qcaps(bp);
3370
3371         if (rc)
3372                 return rc;
3373
3374         bp->pf->active_vfs = num_vfs;
3375
3376         /*
3377          * First, configure the PF to only use one TX ring.  This ensures that
3378          * there are enough rings for all VFs.
3379          *
3380          * If we don't do this, when we call func_alloc() later, we will lock
3381          * extra rings to the PF that won't be available during func_cfg() of
3382          * the VFs.
3383          *
3384          * This has been fixed with firmware versions above 20.6.54
3385          */
3386         bp->pf->func_cfg_flags &=
3387                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3388                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3389         bp->pf->func_cfg_flags |=
3390                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3391         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3392         if (rc)
3393                 return rc;
3394
3395         /*
3396          * Now, create and register a buffer to hold forwarded VF requests
3397          */
3398         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3399         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3400                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3401         if (bp->pf->vf_req_buf == NULL) {
3402                 rc = -ENOMEM;
3403                 goto error_free;
3404         }
3405         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3406                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3407         for (i = 0; i < num_vfs; i++)
3408                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3409                                         (i * HWRM_MAX_REQ_LEN);
3410
3411         rc = bnxt_hwrm_func_buf_rgtr(bp);
3412         if (rc)
3413                 goto error_free;
3414
3415         populate_vf_func_cfg_req(bp, &req, num_vfs);
3416
3417         bp->pf->active_vfs = 0;
3418         for (i = 0; i < num_vfs; i++) {
3419                 add_random_mac_if_needed(bp, &req, i);
3420
3421                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3422                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3423                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3424                 rc = bnxt_hwrm_send_message(bp,
3425                                             &req,
3426                                             sizeof(req),
3427                                             BNXT_USE_CHIMP_MB);
3428
3429                 /* Clear enable flag for next pass */
3430                 req.enables &= ~rte_cpu_to_le_32(
3431                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3432
3433                 if (rc || resp->error_code) {
3434                         PMD_DRV_LOG(ERR,
3435                                 "Failed to initizlie VF %d\n", i);
3436                         PMD_DRV_LOG(ERR,
3437                                 "Not all VFs available. (%d, %d)\n",
3438                                 rc, resp->error_code);
3439                         HWRM_UNLOCK();
3440                         break;
3441                 }
3442
3443                 HWRM_UNLOCK();
3444
3445                 reserve_resources_from_vf(bp, &req, i);
3446                 bp->pf->active_vfs++;
3447                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3448         }
3449
3450         /*
3451          * Now configure the PF to use "the rest" of the resources
3452          * We're using STD_TX_RING_MODE here though which will limit the TX
3453          * rings.  This will allow QoS to function properly.  Not setting this
3454          * will cause PF rings to break bandwidth settings.
3455          */
3456         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3457         if (rc)
3458                 goto error_free;
3459
3460         rc = update_pf_resource_max(bp);
3461         if (rc)
3462                 goto error_free;
3463
3464         return rc;
3465
3466 error_free:
3467         bnxt_hwrm_func_buf_unrgtr(bp);
3468         return rc;
3469 }
3470
3471 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3472 {
3473         struct hwrm_func_cfg_input req = {0};
3474         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3475         int rc;
3476
3477         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3478
3479         req.fid = rte_cpu_to_le_16(0xffff);
3480         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3481         req.evb_mode = bp->pf->evb_mode;
3482
3483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3484         HWRM_CHECK_RESULT();
3485         HWRM_UNLOCK();
3486
3487         return rc;
3488 }
3489
3490 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3491                                 uint8_t tunnel_type)
3492 {
3493         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3494         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3495         int rc = 0;
3496
3497         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3498         req.tunnel_type = tunnel_type;
3499         req.tunnel_dst_port_val = port;
3500         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3501         HWRM_CHECK_RESULT();
3502
3503         switch (tunnel_type) {
3504         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3505                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3506                 bp->vxlan_port = port;
3507                 break;
3508         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3509                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3510                 bp->geneve_port = port;
3511                 break;
3512         default:
3513                 break;
3514         }
3515
3516         HWRM_UNLOCK();
3517
3518         return rc;
3519 }
3520
3521 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3522                                 uint8_t tunnel_type)
3523 {
3524         struct hwrm_tunnel_dst_port_free_input req = {0};
3525         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3526         int rc = 0;
3527
3528         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3529
3530         req.tunnel_type = tunnel_type;
3531         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3533
3534         HWRM_CHECK_RESULT();
3535         HWRM_UNLOCK();
3536
3537         return rc;
3538 }
3539
3540 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3541                                         uint32_t flags)
3542 {
3543         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3544         struct hwrm_func_cfg_input req = {0};
3545         int rc;
3546
3547         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3548
3549         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3550         req.flags = rte_cpu_to_le_32(flags);
3551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3552
3553         HWRM_CHECK_RESULT();
3554         HWRM_UNLOCK();
3555
3556         return rc;
3557 }
3558
3559 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3560 {
3561         uint32_t *flag = flagp;
3562
3563         vnic->flags = *flag;
3564 }
3565
3566 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3567 {
3568         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3569 }
3570
3571 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3572 {
3573         int rc = 0;
3574         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3575         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3576
3577         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3578
3579         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3580         req.req_buf_page_size = rte_cpu_to_le_16(
3581                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3582         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3583         req.req_buf_page_addr0 =
3584                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3585         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3586                 PMD_DRV_LOG(ERR,
3587                         "unable to map buffer address to physical memory\n");
3588                 return -ENOMEM;
3589         }
3590
3591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592
3593         HWRM_CHECK_RESULT();
3594         HWRM_UNLOCK();
3595
3596         return rc;
3597 }
3598
3599 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3600 {
3601         int rc = 0;
3602         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3603         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3604
3605         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3606                 return 0;
3607
3608         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3609
3610         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3611
3612         HWRM_CHECK_RESULT();
3613         HWRM_UNLOCK();
3614
3615         return rc;
3616 }
3617
3618 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3619 {
3620         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3621         struct hwrm_func_cfg_input req = {0};
3622         int rc;
3623
3624         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3625
3626         req.fid = rte_cpu_to_le_16(0xffff);
3627         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3628         req.enables = rte_cpu_to_le_32(
3629                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3630         req.async_event_cr = rte_cpu_to_le_16(
3631                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633
3634         HWRM_CHECK_RESULT();
3635         HWRM_UNLOCK();
3636
3637         return rc;
3638 }
3639
3640 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3641 {
3642         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3643         struct hwrm_func_vf_cfg_input req = {0};
3644         int rc;
3645
3646         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3647
3648         req.enables = rte_cpu_to_le_32(
3649                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3650         req.async_event_cr = rte_cpu_to_le_16(
3651                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3653
3654         HWRM_CHECK_RESULT();
3655         HWRM_UNLOCK();
3656
3657         return rc;
3658 }
3659
3660 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3661 {
3662         struct hwrm_func_cfg_input req = {0};
3663         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3664         uint16_t dflt_vlan, fid;
3665         uint32_t func_cfg_flags;
3666         int rc = 0;
3667
3668         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3669
3670         if (is_vf) {
3671                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3672                 fid = bp->pf->vf_info[vf].fid;
3673                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3674         } else {
3675                 fid = rte_cpu_to_le_16(0xffff);
3676                 func_cfg_flags = bp->pf->func_cfg_flags;
3677                 dflt_vlan = bp->vlan;
3678         }
3679
3680         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3681         req.fid = rte_cpu_to_le_16(fid);
3682         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3683         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3684
3685         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3686
3687         HWRM_CHECK_RESULT();
3688         HWRM_UNLOCK();
3689
3690         return rc;
3691 }
3692
3693 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3694                         uint16_t max_bw, uint16_t enables)
3695 {
3696         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3697         struct hwrm_func_cfg_input req = {0};
3698         int rc;
3699
3700         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3701
3702         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3703         req.enables |= rte_cpu_to_le_32(enables);
3704         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3705         req.max_bw = rte_cpu_to_le_32(max_bw);
3706         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3707
3708         HWRM_CHECK_RESULT();
3709         HWRM_UNLOCK();
3710
3711         return rc;
3712 }
3713
3714 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3715 {
3716         struct hwrm_func_cfg_input req = {0};
3717         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3718         int rc = 0;
3719
3720         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3721
3722         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3723         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3724         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3725         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3726
3727         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3728
3729         HWRM_CHECK_RESULT();
3730         HWRM_UNLOCK();
3731
3732         return rc;
3733 }
3734
3735 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3736 {
3737         int rc;
3738
3739         if (BNXT_PF(bp))
3740                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3741         else
3742                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3743
3744         return rc;
3745 }
3746
3747 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3748                               void *encaped, size_t ec_size)
3749 {
3750         int rc = 0;
3751         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3752         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3753
3754         if (ec_size > sizeof(req.encap_request))
3755                 return -1;
3756
3757         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3758
3759         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3760         memcpy(req.encap_request, encaped, ec_size);
3761
3762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3763
3764         HWRM_CHECK_RESULT();
3765         HWRM_UNLOCK();
3766
3767         return rc;
3768 }
3769
3770 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3771                                        struct rte_ether_addr *mac)
3772 {
3773         struct hwrm_func_qcfg_input req = {0};
3774         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3775         int rc;
3776
3777         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3778
3779         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3780         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3781
3782         HWRM_CHECK_RESULT();
3783
3784         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3785
3786         HWRM_UNLOCK();
3787
3788         return rc;
3789 }
3790
3791 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3792                             void *encaped, size_t ec_size)
3793 {
3794         int rc = 0;
3795         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3796         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3797
3798         if (ec_size > sizeof(req.encap_request))
3799                 return -1;
3800
3801         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3802
3803         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3804         memcpy(req.encap_request, encaped, ec_size);
3805
3806         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3807
3808         HWRM_CHECK_RESULT();
3809         HWRM_UNLOCK();
3810
3811         return rc;
3812 }
3813
3814 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3815                          struct rte_eth_stats *stats, uint8_t rx)
3816 {
3817         int rc = 0;
3818         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3819         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3820
3821         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3822
3823         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3824
3825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3826
3827         HWRM_CHECK_RESULT();
3828
3829         if (rx) {
3830                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3831                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3832                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3833                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3834                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3835                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3836                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3837                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3838         } else {
3839                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3840                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3841                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3842                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3843                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3844                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3845         }
3846
3847         HWRM_UNLOCK();
3848
3849         return rc;
3850 }
3851
3852 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3853 {
3854         struct hwrm_port_qstats_input req = {0};
3855         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3856         struct bnxt_pf_info *pf = bp->pf;
3857         int rc;
3858
3859         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3860
3861         req.port_id = rte_cpu_to_le_16(pf->port_id);
3862         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3863         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3865
3866         HWRM_CHECK_RESULT();
3867         HWRM_UNLOCK();
3868
3869         return rc;
3870 }
3871
3872 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3873 {
3874         struct hwrm_port_clr_stats_input req = {0};
3875         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3876         struct bnxt_pf_info *pf = bp->pf;
3877         int rc;
3878
3879         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3880         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3881             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3882                 return 0;
3883
3884         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3885
3886         req.port_id = rte_cpu_to_le_16(pf->port_id);
3887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3888
3889         HWRM_CHECK_RESULT();
3890         HWRM_UNLOCK();
3891
3892         return rc;
3893 }
3894
3895 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3896 {
3897         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3898         struct hwrm_port_led_qcaps_input req = {0};
3899         int rc;
3900
3901         if (BNXT_VF(bp))
3902                 return 0;
3903
3904         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3905         req.port_id = bp->pf->port_id;
3906         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3907
3908         HWRM_CHECK_RESULT();
3909
3910         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3911                 unsigned int i;
3912
3913                 bp->leds->num_leds = resp->num_leds;
3914                 memcpy(bp->leds, &resp->led0_id,
3915                         sizeof(bp->leds[0]) * bp->leds->num_leds);
3916                 for (i = 0; i < bp->leds->num_leds; i++) {
3917                         struct bnxt_led_info *led = &bp->leds[i];
3918
3919                         uint16_t caps = led->led_state_caps;
3920
3921                         if (!led->led_group_id ||
3922                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3923                                 bp->leds->num_leds = 0;
3924                                 break;
3925                         }
3926                 }
3927         }
3928
3929         HWRM_UNLOCK();
3930
3931         return rc;
3932 }
3933
3934 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3935 {
3936         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3937         struct hwrm_port_led_cfg_input req = {0};
3938         struct bnxt_led_cfg *led_cfg;
3939         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3940         uint16_t duration = 0;
3941         int rc, i;
3942
3943         if (!bp->leds->num_leds || BNXT_VF(bp))
3944                 return -EOPNOTSUPP;
3945
3946         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3947
3948         if (led_on) {
3949                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3950                 duration = rte_cpu_to_le_16(500);
3951         }
3952         req.port_id = bp->pf->port_id;
3953         req.num_leds = bp->leds->num_leds;
3954         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3955         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
3956                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3957                 led_cfg->led_id = bp->leds[i].led_id;
3958                 led_cfg->led_state = led_state;
3959                 led_cfg->led_blink_on = duration;
3960                 led_cfg->led_blink_off = duration;
3961                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3962         }
3963
3964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3965
3966         HWRM_CHECK_RESULT();
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3973                                uint32_t *length)
3974 {
3975         int rc;
3976         struct hwrm_nvm_get_dir_info_input req = {0};
3977         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3978
3979         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3980
3981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3982
3983         HWRM_CHECK_RESULT();
3984
3985         *entries = rte_le_to_cpu_32(resp->entries);
3986         *length = rte_le_to_cpu_32(resp->entry_length);
3987
3988         HWRM_UNLOCK();
3989         return rc;
3990 }
3991
3992 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3993 {
3994         int rc;
3995         uint32_t dir_entries;
3996         uint32_t entry_length;
3997         uint8_t *buf;
3998         size_t buflen;
3999         rte_iova_t dma_handle;
4000         struct hwrm_nvm_get_dir_entries_input req = {0};
4001         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4002
4003         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4004         if (rc != 0)
4005                 return rc;
4006
4007         *data++ = dir_entries;
4008         *data++ = entry_length;
4009         len -= 2;
4010         memset(data, 0xff, len);
4011
4012         buflen = dir_entries * entry_length;
4013         buf = rte_malloc("nvm_dir", buflen, 0);
4014         if (buf == NULL)
4015                 return -ENOMEM;
4016         dma_handle = rte_malloc_virt2iova(buf);
4017         if (dma_handle == RTE_BAD_IOVA) {
4018                 PMD_DRV_LOG(ERR,
4019                         "unable to map response address to physical memory\n");
4020                 return -ENOMEM;
4021         }
4022         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4023         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4025
4026         if (rc == 0)
4027                 memcpy(data, buf, len > buflen ? buflen : len);
4028
4029         rte_free(buf);
4030         HWRM_CHECK_RESULT();
4031         HWRM_UNLOCK();
4032
4033         return rc;
4034 }
4035
4036 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4037                              uint32_t offset, uint32_t length,
4038                              uint8_t *data)
4039 {
4040         int rc;
4041         uint8_t *buf;
4042         rte_iova_t dma_handle;
4043         struct hwrm_nvm_read_input req = {0};
4044         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4045
4046         buf = rte_malloc("nvm_item", length, 0);
4047         if (!buf)
4048                 return -ENOMEM;
4049
4050         dma_handle = rte_malloc_virt2iova(buf);
4051         if (dma_handle == RTE_BAD_IOVA) {
4052                 PMD_DRV_LOG(ERR,
4053                         "unable to map response address to physical memory\n");
4054                 return -ENOMEM;
4055         }
4056         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4057         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4058         req.dir_idx = rte_cpu_to_le_16(index);
4059         req.offset = rte_cpu_to_le_32(offset);
4060         req.len = rte_cpu_to_le_32(length);
4061         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4062         if (rc == 0)
4063                 memcpy(data, buf, length);
4064
4065         rte_free(buf);
4066         HWRM_CHECK_RESULT();
4067         HWRM_UNLOCK();
4068
4069         return rc;
4070 }
4071
4072 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4073 {
4074         int rc;
4075         struct hwrm_nvm_erase_dir_entry_input req = {0};
4076         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4077
4078         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4079         req.dir_idx = rte_cpu_to_le_16(index);
4080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4081         HWRM_CHECK_RESULT();
4082         HWRM_UNLOCK();
4083
4084         return rc;
4085 }
4086
4087
4088 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4089                           uint16_t dir_ordinal, uint16_t dir_ext,
4090                           uint16_t dir_attr, const uint8_t *data,
4091                           size_t data_len)
4092 {
4093         int rc;
4094         struct hwrm_nvm_write_input req = {0};
4095         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4096         rte_iova_t dma_handle;
4097         uint8_t *buf;
4098
4099         buf = rte_malloc("nvm_write", data_len, 0);
4100         if (!buf)
4101                 return -ENOMEM;
4102
4103         dma_handle = rte_malloc_virt2iova(buf);
4104         if (dma_handle == RTE_BAD_IOVA) {
4105                 PMD_DRV_LOG(ERR,
4106                         "unable to map response address to physical memory\n");
4107                 return -ENOMEM;
4108         }
4109         memcpy(buf, data, data_len);
4110
4111         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4112
4113         req.dir_type = rte_cpu_to_le_16(dir_type);
4114         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4115         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4116         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4117         req.dir_data_length = rte_cpu_to_le_32(data_len);
4118         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4119
4120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4121
4122         rte_free(buf);
4123         HWRM_CHECK_RESULT();
4124         HWRM_UNLOCK();
4125
4126         return rc;
4127 }
4128
4129 static void
4130 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4131 {
4132         uint32_t *count = cbdata;
4133
4134         *count = *count + 1;
4135 }
4136
4137 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4138                                      struct bnxt_vnic_info *vnic __rte_unused)
4139 {
4140         return 0;
4141 }
4142
4143 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4144 {
4145         uint32_t count = 0;
4146
4147         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4148             &count, bnxt_vnic_count_hwrm_stub);
4149
4150         return count;
4151 }
4152
4153 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4154                                         uint16_t *vnic_ids)
4155 {
4156         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4157         struct hwrm_func_vf_vnic_ids_query_output *resp =
4158                                                 bp->hwrm_cmd_resp_addr;
4159         int rc;
4160
4161         /* First query all VNIC ids */
4162         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4163
4164         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4165         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4166         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4167
4168         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4169                 HWRM_UNLOCK();
4170                 PMD_DRV_LOG(ERR,
4171                 "unable to map VNIC ID table address to physical memory\n");
4172                 return -ENOMEM;
4173         }
4174         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4175         HWRM_CHECK_RESULT();
4176         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4177
4178         HWRM_UNLOCK();
4179
4180         return rc;
4181 }
4182
4183 /*
4184  * This function queries the VNIC IDs  for a specified VF. It then calls
4185  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4186  * Then it calls the hwrm_cb function to program this new vnic configuration.
4187  */
4188 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4189         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4190         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4191 {
4192         struct bnxt_vnic_info vnic;
4193         int rc = 0;
4194         int i, num_vnic_ids;
4195         uint16_t *vnic_ids;
4196         size_t vnic_id_sz;
4197         size_t sz;
4198
4199         /* First query all VNIC ids */
4200         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4201         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4202                         RTE_CACHE_LINE_SIZE);
4203         if (vnic_ids == NULL)
4204                 return -ENOMEM;
4205
4206         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4207                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4208
4209         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4210
4211         if (num_vnic_ids < 0)
4212                 return num_vnic_ids;
4213
4214         /* Retrieve VNIC, update bd_stall then update */
4215
4216         for (i = 0; i < num_vnic_ids; i++) {
4217                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4218                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4219                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4220                 if (rc)
4221                         break;
4222                 if (vnic.mru <= 4)      /* Indicates unallocated */
4223                         continue;
4224
4225                 vnic_cb(&vnic, cbdata);
4226
4227                 rc = hwrm_cb(bp, &vnic);
4228                 if (rc)
4229                         break;
4230         }
4231
4232         rte_free(vnic_ids);
4233
4234         return rc;
4235 }
4236
4237 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4238                                               bool on)
4239 {
4240         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4241         struct hwrm_func_cfg_input req = {0};
4242         int rc;
4243
4244         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4245
4246         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4247         req.enables |= rte_cpu_to_le_32(
4248                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4249         req.vlan_antispoof_mode = on ?
4250                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4251                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4253
4254         HWRM_CHECK_RESULT();
4255         HWRM_UNLOCK();
4256
4257         return rc;
4258 }
4259
4260 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4261 {
4262         struct bnxt_vnic_info vnic;
4263         uint16_t *vnic_ids;
4264         size_t vnic_id_sz;
4265         int num_vnic_ids, i;
4266         size_t sz;
4267         int rc;
4268
4269         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4270         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4271                         RTE_CACHE_LINE_SIZE);
4272         if (vnic_ids == NULL)
4273                 return -ENOMEM;
4274
4275         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4276                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4277
4278         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4279         if (rc <= 0)
4280                 goto exit;
4281         num_vnic_ids = rc;
4282
4283         /*
4284          * Loop through to find the default VNIC ID.
4285          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4286          * by sending the hwrm_func_qcfg command to the firmware.
4287          */
4288         for (i = 0; i < num_vnic_ids; i++) {
4289                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4290                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4291                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4292                                         bp->pf->first_vf_id + vf);
4293                 if (rc)
4294                         goto exit;
4295                 if (vnic.func_default) {
4296                         rte_free(vnic_ids);
4297                         return vnic.fw_vnic_id;
4298                 }
4299         }
4300         /* Could not find a default VNIC. */
4301         PMD_DRV_LOG(ERR, "No default VNIC\n");
4302 exit:
4303         rte_free(vnic_ids);
4304         return rc;
4305 }
4306
4307 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4308                          uint16_t dst_id,
4309                          struct bnxt_filter_info *filter)
4310 {
4311         int rc = 0;
4312         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4313         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4314         uint32_t enables = 0;
4315
4316         if (filter->fw_em_filter_id != UINT64_MAX)
4317                 bnxt_hwrm_clear_em_filter(bp, filter);
4318
4319         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4320
4321         req.flags = rte_cpu_to_le_32(filter->flags);
4322
4323         enables = filter->enables |
4324               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4325         req.dst_id = rte_cpu_to_le_16(dst_id);
4326
4327         if (filter->ip_addr_type) {
4328                 req.ip_addr_type = filter->ip_addr_type;
4329                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4330         }
4331         if (enables &
4332             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4333                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4334         if (enables &
4335             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4336                 memcpy(req.src_macaddr, filter->src_macaddr,
4337                        RTE_ETHER_ADDR_LEN);
4338         if (enables &
4339             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4340                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4341                        RTE_ETHER_ADDR_LEN);
4342         if (enables &
4343             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4344                 req.ovlan_vid = filter->l2_ovlan;
4345         if (enables &
4346             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4347                 req.ivlan_vid = filter->l2_ivlan;
4348         if (enables &
4349             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4350                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4351         if (enables &
4352             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4353                 req.ip_protocol = filter->ip_protocol;
4354         if (enables &
4355             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4356                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4357         if (enables &
4358             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4359                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4360         if (enables &
4361             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4362                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4363         if (enables &
4364             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4365                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4366         if (enables &
4367             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4368                 req.mirror_vnic_id = filter->mirror_vnic_id;
4369
4370         req.enables = rte_cpu_to_le_32(enables);
4371
4372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4373
4374         HWRM_CHECK_RESULT();
4375
4376         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4377         HWRM_UNLOCK();
4378
4379         return rc;
4380 }
4381
4382 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4383 {
4384         int rc = 0;
4385         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4386         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4387
4388         if (filter->fw_em_filter_id == UINT64_MAX)
4389                 return 0;
4390
4391         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4392
4393         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4394
4395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4396
4397         HWRM_CHECK_RESULT();
4398         HWRM_UNLOCK();
4399
4400         filter->fw_em_filter_id = UINT64_MAX;
4401         filter->fw_l2_filter_id = UINT64_MAX;
4402
4403         return 0;
4404 }
4405
4406 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4407                          uint16_t dst_id,
4408                          struct bnxt_filter_info *filter)
4409 {
4410         int rc = 0;
4411         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4412         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4413                                                 bp->hwrm_cmd_resp_addr;
4414         uint32_t enables = 0;
4415
4416         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4417                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4418
4419         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4420
4421         req.flags = rte_cpu_to_le_32(filter->flags);
4422
4423         enables = filter->enables |
4424               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4425         req.dst_id = rte_cpu_to_le_16(dst_id);
4426
4427         if (filter->ip_addr_type) {
4428                 req.ip_addr_type = filter->ip_addr_type;
4429                 enables |=
4430                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4431         }
4432         if (enables &
4433             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4434                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4435         if (enables &
4436             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4437                 memcpy(req.src_macaddr, filter->src_macaddr,
4438                        RTE_ETHER_ADDR_LEN);
4439         if (enables &
4440             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4441                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4442         if (enables &
4443             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4444                 req.ip_protocol = filter->ip_protocol;
4445         if (enables &
4446             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4447                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4448         if (enables &
4449             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4450                 req.src_ipaddr_mask[0] =
4451                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4452         if (enables &
4453             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4454                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4455         if (enables &
4456             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4457                 req.dst_ipaddr_mask[0] =
4458                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4459         if (enables &
4460             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4461                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4462         if (enables &
4463             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4464                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4465         if (enables &
4466             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4467                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4468         if (enables &
4469             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4470                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4471         if (enables &
4472             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4473                 req.mirror_vnic_id = filter->mirror_vnic_id;
4474
4475         req.enables = rte_cpu_to_le_32(enables);
4476
4477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4478
4479         HWRM_CHECK_RESULT();
4480
4481         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4482         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4483         HWRM_UNLOCK();
4484
4485         return rc;
4486 }
4487
4488 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4489                                 struct bnxt_filter_info *filter)
4490 {
4491         int rc = 0;
4492         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4493         struct hwrm_cfa_ntuple_filter_free_output *resp =
4494                                                 bp->hwrm_cmd_resp_addr;
4495
4496         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4497                 return 0;
4498
4499         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4500
4501         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4502
4503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4504
4505         HWRM_CHECK_RESULT();
4506         HWRM_UNLOCK();
4507
4508         filter->fw_ntuple_filter_id = UINT64_MAX;
4509
4510         return 0;
4511 }
4512
4513 static int
4514 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4515 {
4516         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4517         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4518         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4519         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4520         uint16_t *ring_tbl = vnic->rss_table;
4521         int nr_ctxs = vnic->num_lb_ctxts;
4522         int max_rings = bp->rx_nr_rings;
4523         int i, j, k, cnt;
4524         int rc = 0;
4525
4526         for (i = 0, k = 0; i < nr_ctxs; i++) {
4527                 struct bnxt_rx_ring_info *rxr;
4528                 struct bnxt_cp_ring_info *cpr;
4529
4530                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4531
4532                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4533                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4534                 req.hash_mode_flags = vnic->hash_mode;
4535
4536                 req.ring_grp_tbl_addr =
4537                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4538                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4539                                      2 * sizeof(*ring_tbl));
4540                 req.hash_key_tbl_addr =
4541                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4542
4543                 req.ring_table_pair_index = i;
4544                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4545
4546                 for (j = 0; j < 64; j++) {
4547                         uint16_t ring_id;
4548
4549                         /* Find next active ring. */
4550                         for (cnt = 0; cnt < max_rings; cnt++) {
4551                                 if (rx_queue_state[k] !=
4552                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4553                                         break;
4554                                 if (++k == max_rings)
4555                                         k = 0;
4556                         }
4557
4558                         /* Return if no rings are active. */
4559                         if (cnt == max_rings) {
4560                                 HWRM_UNLOCK();
4561                                 return 0;
4562                         }
4563
4564                         /* Add rx/cp ring pair to RSS table. */
4565                         rxr = rxqs[k]->rx_ring;
4566                         cpr = rxqs[k]->cp_ring;
4567
4568                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4569                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4570                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4571                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4572
4573                         if (++k == max_rings)
4574                                 k = 0;
4575                 }
4576                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4577                                             BNXT_USE_CHIMP_MB);
4578
4579                 HWRM_CHECK_RESULT();
4580                 HWRM_UNLOCK();
4581         }
4582
4583         return rc;
4584 }
4585
4586 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4587 {
4588         unsigned int rss_idx, fw_idx, i;
4589
4590         if (!(vnic->rss_table && vnic->hash_type))
4591                 return 0;
4592
4593         if (BNXT_CHIP_THOR(bp))
4594                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4595
4596         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4597                 return 0;
4598
4599         if (vnic->rss_table && vnic->hash_type) {
4600                 /*
4601                  * Fill the RSS hash & redirection table with
4602                  * ring group ids for all VNICs
4603                  */
4604                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4605                         rss_idx++, fw_idx++) {
4606                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4607                                 fw_idx %= bp->rx_cp_nr_rings;
4608                                 if (vnic->fw_grp_ids[fw_idx] !=
4609                                     INVALID_HW_RING_ID)
4610                                         break;
4611                                 fw_idx++;
4612                         }
4613                         if (i == bp->rx_cp_nr_rings)
4614                                 return 0;
4615                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4616                 }
4617                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4618         }
4619
4620         return 0;
4621 }
4622
4623 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4624         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4625 {
4626         uint16_t flags;
4627
4628         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4629
4630         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4631         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4632
4633         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4634         req->num_cmpl_dma_aggr_during_int =
4635                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4636
4637         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4638
4639         /* min timer set to 1/2 of interrupt timer */
4640         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4641
4642         /* buf timer set to 1/4 of interrupt timer */
4643         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4644
4645         req->cmpl_aggr_dma_tmr_during_int =
4646                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4647
4648         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4649                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4650         req->flags = rte_cpu_to_le_16(flags);
4651 }
4652
4653 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4654                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4655 {
4656         struct hwrm_ring_aggint_qcaps_input req = {0};
4657         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4658         uint32_t enables;
4659         uint16_t flags;
4660         int rc;
4661
4662         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4663         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4664         HWRM_CHECK_RESULT();
4665
4666         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4667         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4668
4669         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4670                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4671         agg_req->flags = rte_cpu_to_le_16(flags);
4672         enables =
4673          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4674          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4675         agg_req->enables = rte_cpu_to_le_32(enables);
4676
4677         HWRM_UNLOCK();
4678         return rc;
4679 }
4680
4681 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4682                         struct bnxt_coal *coal, uint16_t ring_id)
4683 {
4684         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4685         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4686                                                 bp->hwrm_cmd_resp_addr;
4687         int rc;
4688
4689         /* Set ring coalesce parameters only for 100G NICs */
4690         if (BNXT_CHIP_THOR(bp)) {
4691                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4692                         return -1;
4693         } else if (bnxt_stratus_device(bp)) {
4694                 bnxt_hwrm_set_coal_params(coal, &req);
4695         } else {
4696                 return 0;
4697         }
4698
4699         HWRM_PREP(&req,
4700                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4701                   BNXT_USE_CHIMP_MB);
4702         req.ring_id = rte_cpu_to_le_16(ring_id);
4703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4704         HWRM_CHECK_RESULT();
4705         HWRM_UNLOCK();
4706         return 0;
4707 }
4708
4709 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4710 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4711 {
4712         struct hwrm_func_backing_store_qcaps_input req = {0};
4713         struct hwrm_func_backing_store_qcaps_output *resp =
4714                 bp->hwrm_cmd_resp_addr;
4715         struct bnxt_ctx_pg_info *ctx_pg;
4716         struct bnxt_ctx_mem_info *ctx;
4717         int total_alloc_len;
4718         int rc, i, tqm_rings;
4719
4720         if (!BNXT_CHIP_THOR(bp) ||
4721             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4722             BNXT_VF(bp) ||
4723             bp->ctx)
4724                 return 0;
4725
4726         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4727         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4728         HWRM_CHECK_RESULT_SILENT();
4729
4730         total_alloc_len = sizeof(*ctx);
4731         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4732                           RTE_CACHE_LINE_SIZE);
4733         if (!ctx) {
4734                 rc = -ENOMEM;
4735                 goto ctx_err;
4736         }
4737
4738         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4739         ctx->qp_min_qp1_entries =
4740                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4741         ctx->qp_max_l2_entries =
4742                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4743         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4744         ctx->srq_max_l2_entries =
4745                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4746         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4747         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4748         ctx->cq_max_l2_entries =
4749                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4750         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4751         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4752         ctx->vnic_max_vnic_entries =
4753                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4754         ctx->vnic_max_ring_table_entries =
4755                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4756         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4757         ctx->stat_max_entries =
4758                 rte_le_to_cpu_32(resp->stat_max_entries);
4759         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4760         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4761         ctx->tqm_min_entries_per_ring =
4762                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4763         ctx->tqm_max_entries_per_ring =
4764                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4765         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4766         if (!ctx->tqm_entries_multiple)
4767                 ctx->tqm_entries_multiple = 1;
4768         ctx->mrav_max_entries =
4769                 rte_le_to_cpu_32(resp->mrav_max_entries);
4770         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4771         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4772         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4773         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4774
4775         if (!ctx->tqm_fp_rings_count)
4776                 ctx->tqm_fp_rings_count = bp->max_q;
4777
4778         tqm_rings = ctx->tqm_fp_rings_count + 1;
4779
4780         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4781                             sizeof(*ctx_pg) * tqm_rings,
4782                             RTE_CACHE_LINE_SIZE);
4783         if (!ctx_pg) {
4784                 rc = -ENOMEM;
4785                 goto ctx_err;
4786         }
4787         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4788                 ctx->tqm_mem[i] = ctx_pg;
4789
4790         bp->ctx = ctx;
4791 ctx_err:
4792         HWRM_UNLOCK();
4793         return rc;
4794 }
4795
4796 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4797 {
4798         struct hwrm_func_backing_store_cfg_input req = {0};
4799         struct hwrm_func_backing_store_cfg_output *resp =
4800                 bp->hwrm_cmd_resp_addr;
4801         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4802         struct bnxt_ctx_pg_info *ctx_pg;
4803         uint32_t *num_entries;
4804         uint64_t *pg_dir;
4805         uint8_t *pg_attr;
4806         uint32_t ena;
4807         int i, rc;
4808
4809         if (!ctx)
4810                 return 0;
4811
4812         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4813         req.enables = rte_cpu_to_le_32(enables);
4814
4815         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4816                 ctx_pg = &ctx->qp_mem;
4817                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4818                 req.qp_num_qp1_entries =
4819                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4820                 req.qp_num_l2_entries =
4821                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4822                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4823                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4824                                       &req.qpc_pg_size_qpc_lvl,
4825                                       &req.qpc_page_dir);
4826         }
4827
4828         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4829                 ctx_pg = &ctx->srq_mem;
4830                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4831                 req.srq_num_l2_entries =
4832                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4833                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4834                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4835                                       &req.srq_pg_size_srq_lvl,
4836                                       &req.srq_page_dir);
4837         }
4838
4839         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4840                 ctx_pg = &ctx->cq_mem;
4841                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4842                 req.cq_num_l2_entries =
4843                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4844                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4845                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4846                                       &req.cq_pg_size_cq_lvl,
4847                                       &req.cq_page_dir);
4848         }
4849
4850         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4851                 ctx_pg = &ctx->vnic_mem;
4852                 req.vnic_num_vnic_entries =
4853                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4854                 req.vnic_num_ring_table_entries =
4855                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4856                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4857                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4858                                       &req.vnic_pg_size_vnic_lvl,
4859                                       &req.vnic_page_dir);
4860         }
4861
4862         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4863                 ctx_pg = &ctx->stat_mem;
4864                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4865                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4866                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4867                                       &req.stat_pg_size_stat_lvl,
4868                                       &req.stat_page_dir);
4869         }
4870
4871         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4872         num_entries = &req.tqm_sp_num_entries;
4873         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4874         pg_dir = &req.tqm_sp_page_dir;
4875         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4876         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4877                 if (!(enables & ena))
4878                         continue;
4879
4880                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4881
4882                 ctx_pg = ctx->tqm_mem[i];
4883                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4884                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4885         }
4886
4887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4888         HWRM_CHECK_RESULT();
4889         HWRM_UNLOCK();
4890
4891         return rc;
4892 }
4893
4894 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4895 {
4896         struct hwrm_port_qstats_ext_input req = {0};
4897         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4898         struct bnxt_pf_info *pf = bp->pf;
4899         int rc;
4900
4901         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4902               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4903                 return 0;
4904
4905         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4906
4907         req.port_id = rte_cpu_to_le_16(pf->port_id);
4908         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4909                 req.tx_stat_host_addr =
4910                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4911                 req.tx_stat_size =
4912                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4913         }
4914         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4915                 req.rx_stat_host_addr =
4916                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4917                 req.rx_stat_size =
4918                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4919         }
4920         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4921
4922         if (rc) {
4923                 bp->fw_rx_port_stats_ext_size = 0;
4924                 bp->fw_tx_port_stats_ext_size = 0;
4925         } else {
4926                 bp->fw_rx_port_stats_ext_size =
4927                         rte_le_to_cpu_16(resp->rx_stat_size);
4928                 bp->fw_tx_port_stats_ext_size =
4929                         rte_le_to_cpu_16(resp->tx_stat_size);
4930         }
4931
4932         HWRM_CHECK_RESULT();
4933         HWRM_UNLOCK();
4934
4935         return rc;
4936 }
4937
4938 int
4939 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4940 {
4941         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4942         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4943                 bp->hwrm_cmd_resp_addr;
4944         int rc = 0;
4945
4946         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4947         req.tunnel_type = type;
4948         req.dest_fid = bp->fw_fid;
4949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4950         HWRM_CHECK_RESULT();
4951
4952         HWRM_UNLOCK();
4953
4954         return rc;
4955 }
4956
4957 int
4958 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4959 {
4960         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4961         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4962                 bp->hwrm_cmd_resp_addr;
4963         int rc = 0;
4964
4965         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4966         req.tunnel_type = type;
4967         req.dest_fid = bp->fw_fid;
4968         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4969         HWRM_CHECK_RESULT();
4970
4971         HWRM_UNLOCK();
4972
4973         return rc;
4974 }
4975
4976 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4977 {
4978         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4979         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4980                 bp->hwrm_cmd_resp_addr;
4981         int rc = 0;
4982
4983         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4984         req.src_fid = bp->fw_fid;
4985         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4986         HWRM_CHECK_RESULT();
4987
4988         if (type)
4989                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4990
4991         HWRM_UNLOCK();
4992
4993         return rc;
4994 }
4995
4996 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4997                                    uint16_t *dst_fid)
4998 {
4999         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5000         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5001                 bp->hwrm_cmd_resp_addr;
5002         int rc = 0;
5003
5004         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5005         req.src_fid = bp->fw_fid;
5006         req.tunnel_type = tun_type;
5007         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5008         HWRM_CHECK_RESULT();
5009
5010         if (dst_fid)
5011                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5012
5013         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5014
5015         HWRM_UNLOCK();
5016
5017         return rc;
5018 }
5019
5020 int bnxt_hwrm_set_mac(struct bnxt *bp)
5021 {
5022         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5023         struct hwrm_func_vf_cfg_input req = {0};
5024         int rc = 0;
5025
5026         if (!BNXT_VF(bp))
5027                 return 0;
5028
5029         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5030
5031         req.enables =
5032                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5033         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5034
5035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5036
5037         HWRM_CHECK_RESULT();
5038
5039         HWRM_UNLOCK();
5040
5041         return rc;
5042 }
5043
5044 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5045 {
5046         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5047         struct hwrm_func_drv_if_change_input req = {0};
5048         uint32_t flags;
5049         int rc;
5050
5051         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5052                 return 0;
5053
5054         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5055          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5056          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5057          */
5058         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5059                 return 0;
5060
5061         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5062
5063         if (up)
5064                 req.flags =
5065                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5066
5067         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5068
5069         HWRM_CHECK_RESULT();
5070         flags = rte_le_to_cpu_32(resp->flags);
5071         HWRM_UNLOCK();
5072
5073         if (!up)
5074                 return 0;
5075
5076         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5077                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5078                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5079         }
5080
5081         return 0;
5082 }
5083
5084 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5085 {
5086         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5087         struct bnxt_error_recovery_info *info = bp->recovery_info;
5088         struct hwrm_error_recovery_qcfg_input req = {0};
5089         uint32_t flags = 0;
5090         unsigned int i;
5091         int rc;
5092
5093         /* Older FW does not have error recovery support */
5094         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5095                 return 0;
5096
5097         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5098
5099         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5100
5101         HWRM_CHECK_RESULT();
5102
5103         flags = rte_le_to_cpu_32(resp->flags);
5104         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5105                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5106         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5107                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5108
5109         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5110             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5111                 rc = -EINVAL;
5112                 goto err;
5113         }
5114
5115         /* FW returned values are in units of 100msec */
5116         info->driver_polling_freq =
5117                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5118         info->master_func_wait_period =
5119                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5120         info->normal_func_wait_period =
5121                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5122         info->master_func_wait_period_after_reset =
5123                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5124         info->max_bailout_time_after_reset =
5125                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5126         info->status_regs[BNXT_FW_STATUS_REG] =
5127                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5128         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5129                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5130         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5131                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5132         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5133                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5134         info->reg_array_cnt =
5135                 rte_le_to_cpu_32(resp->reg_array_cnt);
5136
5137         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5138                 rc = -EINVAL;
5139                 goto err;
5140         }
5141
5142         for (i = 0; i < info->reg_array_cnt; i++) {
5143                 info->reset_reg[i] =
5144                         rte_le_to_cpu_32(resp->reset_reg[i]);
5145                 info->reset_reg_val[i] =
5146                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5147                 info->delay_after_reset[i] =
5148                         resp->delay_after_reset[i];
5149         }
5150 err:
5151         HWRM_UNLOCK();
5152
5153         /* Map the FW status registers */
5154         if (!rc)
5155                 rc = bnxt_map_fw_health_status_regs(bp);
5156
5157         if (rc) {
5158                 rte_free(bp->recovery_info);
5159                 bp->recovery_info = NULL;
5160         }
5161         return rc;
5162 }
5163
5164 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5165 {
5166         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5167         struct hwrm_fw_reset_input req = {0};
5168         int rc;
5169
5170         if (!BNXT_PF(bp))
5171                 return -EOPNOTSUPP;
5172
5173         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5174
5175         req.embedded_proc_type =
5176                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5177         req.selfrst_status =
5178                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5179         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5180
5181         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5182                                     BNXT_USE_KONG(bp));
5183
5184         HWRM_CHECK_RESULT();
5185         HWRM_UNLOCK();
5186
5187         return rc;
5188 }
5189
5190 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5191 {
5192         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5193         struct hwrm_port_ts_query_input req = {0};
5194         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5195         uint32_t flags = 0;
5196         int rc;
5197
5198         if (!ptp)
5199                 return 0;
5200
5201         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5202
5203         switch (path) {
5204         case BNXT_PTP_FLAGS_PATH_TX:
5205                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5206                 break;
5207         case BNXT_PTP_FLAGS_PATH_RX:
5208                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5209                 break;
5210         case BNXT_PTP_FLAGS_CURRENT_TIME:
5211                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5212                 break;
5213         }
5214
5215         req.flags = rte_cpu_to_le_32(flags);
5216         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5217
5218         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5219
5220         HWRM_CHECK_RESULT();
5221
5222         if (timestamp) {
5223                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5224                 *timestamp |=
5225                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5226         }
5227         HWRM_UNLOCK();
5228
5229         return rc;
5230 }
5231
5232 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5233 {
5234         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5235                                         bp->hwrm_cmd_resp_addr;
5236         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5237         uint32_t flags = 0;
5238         int rc = 0;
5239
5240         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5241                 return rc;
5242
5243         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5244                 PMD_DRV_LOG(DEBUG,
5245                             "Not a PF or trusted VF. Command not supported\n");
5246                 return 0;
5247         }
5248
5249         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5251
5252         HWRM_CHECK_RESULT();
5253         flags = rte_le_to_cpu_32(resp->flags);
5254         HWRM_UNLOCK();
5255
5256         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5257                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5258                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5259         }
5260
5261         return rc;
5262 }
5263
5264 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5265 {
5266         int rc = 0;
5267
5268         struct hwrm_cfa_counter_qcaps_input req = {0};
5269         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5270
5271         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5272                 PMD_DRV_LOG(DEBUG,
5273                             "Not a PF or trusted VF. Command not supported\n");
5274                 return 0;
5275         }
5276
5277         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5278         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5279         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5280
5281         HWRM_CHECK_RESULT();
5282         if (max_fc)
5283                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5284         HWRM_UNLOCK();
5285
5286         return 0;
5287 }
5288
5289 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5290 {
5291         int rc = 0;
5292         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5293         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5294
5295         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5296                 PMD_DRV_LOG(DEBUG,
5297                             "Not a PF or trusted VF. Command not supported\n");
5298                 return 0;
5299         }
5300
5301         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5302
5303         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5304         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5305         req.page_dir = rte_cpu_to_le_64(dma_addr);
5306
5307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5308
5309         HWRM_CHECK_RESULT();
5310         if (ctx_id) {
5311                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5312                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5313         }
5314         HWRM_UNLOCK();
5315
5316         return 0;
5317 }
5318
5319 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5320 {
5321         int rc = 0;
5322         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5323         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5324
5325         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5326                 PMD_DRV_LOG(DEBUG,
5327                             "Not a PF or trusted VF. Command not supported\n");
5328                 return 0;
5329         }
5330
5331         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5332
5333         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5334
5335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5336
5337         HWRM_CHECK_RESULT();
5338         HWRM_UNLOCK();
5339
5340         return rc;
5341 }
5342
5343 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5344                               uint16_t cntr, uint16_t ctx_id,
5345                               uint32_t num_entries, bool enable)
5346 {
5347         struct hwrm_cfa_counter_cfg_input req = {0};
5348         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5349         uint16_t flags = 0;
5350         int rc;
5351
5352         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5353                 PMD_DRV_LOG(DEBUG,
5354                             "Not a PF or trusted VF. Command not supported\n");
5355                 return 0;
5356         }
5357
5358         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5359
5360         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5361         req.counter_type = rte_cpu_to_le_16(cntr);
5362         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5363                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5364         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5365         if (dir == BNXT_DIR_RX)
5366                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5367         else if (dir == BNXT_DIR_TX)
5368                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5369         req.flags = rte_cpu_to_le_16(flags);
5370         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5371         req.num_entries = rte_cpu_to_le_32(num_entries);
5372
5373         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5374         HWRM_CHECK_RESULT();
5375         HWRM_UNLOCK();
5376
5377         return 0;
5378 }
5379
5380 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5381                                  enum bnxt_flow_dir dir,
5382                                  uint16_t cntr,
5383                                  uint16_t num_entries)
5384 {
5385         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5386         struct hwrm_cfa_counter_qstats_input req = {0};
5387         uint16_t flow_ctx_id = 0;
5388         uint16_t flags = 0;
5389         int rc = 0;
5390
5391         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5392                 PMD_DRV_LOG(DEBUG,
5393                             "Not a PF or trusted VF. Command not supported\n");
5394                 return 0;
5395         }
5396
5397         if (dir == BNXT_DIR_RX) {
5398                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5399                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5400         } else if (dir == BNXT_DIR_TX) {
5401                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5402                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5403         }
5404
5405         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5406         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5407         req.counter_type = rte_cpu_to_le_16(cntr);
5408         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5409         req.num_entries = rte_cpu_to_le_16(num_entries);
5410         req.flags = rte_cpu_to_le_16(flags);
5411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5412
5413         HWRM_CHECK_RESULT();
5414         HWRM_UNLOCK();
5415
5416         return 0;
5417 }