drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (!BNXT_CHIP_P5(bp) &&
 754             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 755                 return 0;
 756
 757         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 758                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 759
 760         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 761         if (!ptp)
 762                 return -ENOMEM;
 763
 764         if (!BNXT_CHIP_P5(bp)) {
 765                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 766                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 767                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 768                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 769                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 771                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 773                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 775                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 776                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 777                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 778                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 779                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 781                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 783         }
 784
 785         ptp->bp = bp;
 786         bp->ptp_cfg = ptp;
 787
 788         return 0;
 789 }
 790
 791 void bnxt_free_vf_info(struct bnxt *bp)
 792 {
 793         int i;
 794
 795         if (bp->pf->vf_info == NULL)
 796                 return;
 797
 798         for (i = 0; i < bp->pf->max_vfs; i++) {
 799                 rte_free(bp->pf->vf_info[i].vlan_table);
 800                 bp->pf->vf_info[i].vlan_table = NULL;
 801                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 802                 bp->pf->vf_info[i].vlan_as_table = NULL;
 803         }
 804         rte_free(bp->pf->vf_info);
 805         bp->pf->vf_info = NULL;
 806 }
 807
 808 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 809 {
 810         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 811         int i;
 812
 813         if (vf_info)
 814                 bnxt_free_vf_info(bp);
 815
 816         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 817         if (vf_info == NULL) {
 818                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 819                 return -ENOMEM;
 820         }
 821
 822         bp->pf->max_vfs = max_vfs;
 823         for (i = 0; i < max_vfs; i++) {
 824                 vf_info[i].fid = bp->pf->first_vf_id + i;
 825                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 826                                                     getpagesize(), getpagesize());
 827                 if (vf_info[i].vlan_table == NULL) {
 828                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 829                         goto err;
 830                 }
 831                 rte_mem_lock_page(vf_info[i].vlan_table);
 832
 833                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 834                                                        getpagesize(), getpagesize());
 835                 if (vf_info[i].vlan_as_table == NULL) {
 836                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 837                         goto err;
 838                 }
 839                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 840
 841                 STAILQ_INIT(&vf_info[i].filter);
 842         }
 843
 844         bp->pf->vf_info = vf_info;
 845
 846         return 0;
 847 err:
 848         bnxt_free_vf_info(bp);
 849         return -ENOMEM;
 850 }
 851
 852 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 853 {
 854         int rc = 0;
 855         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 856         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 857         uint16_t new_max_vfs;
 858         uint32_t flags;
 859
 860         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 861
 862         req.fid = rte_cpu_to_le_16(0xffff);
 863
 864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 865
 866         HWRM_CHECK_RESULT();
 867
 868         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 869         flags = rte_le_to_cpu_32(resp->flags);
 870         if (BNXT_PF(bp)) {
 871                 bp->pf->port_id = resp->port_id;
 872                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 873                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 874                 new_max_vfs = bp->pdev->max_vfs;
 875                 if (new_max_vfs != bp->pf->max_vfs) {
 876                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 877                         if (rc)
 878                                 goto unlock;
 879                 }
 880         }
 881
 882         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 883         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 884                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 885                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 886         } else {
 887                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 888         }
 889         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 890         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 891         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 892         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 893         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 894         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 895         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 896         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 897                 bp->max_l2_ctx += bp->max_rx_em_flows;
 898         /* TODO: For now, do not support VMDq/RFS on VFs. */
 899         if (BNXT_PF(bp)) {
 900                 if (bp->pf->max_vfs)
 901                         bp->max_vnics = 1;
 902                 else
 903                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 904         } else {
 905                 bp->max_vnics = 1;
 906         }
 907         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 908                     bp->max_l2_ctx, bp->max_vnics);
 909         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 910         if (BNXT_PF(bp)) {
 911                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 912                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 913                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 914                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 915                         HWRM_UNLOCK();
 916                         bnxt_hwrm_ptp_qcfg(bp);
 917                 }
 918         }
 919
 920         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 921                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 922
 923         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 924                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 925                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 926         }
 927
 928         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 929                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 930
 931         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 932                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 933
 934         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 935                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 936
 937 unlock:
 938         HWRM_UNLOCK();
 939
 940         return rc;
 941 }
 942
 943 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 944 {
 945         int rc;
 946
 947         rc = __bnxt_hwrm_func_qcaps(bp);
 948         if (rc == -ENOMEM)
 949                 return rc;
 950
 951         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 952                 rc = bnxt_alloc_ctx_mem(bp);
 953                 if (rc)
 954                         return rc;
 955
 956                 /* On older FW,
 957                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 958                  * But the error can be ignored. Return success.
 959                  */
 960                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 961                 if (!rc)
 962                         bp->flags |= BNXT_FLAG_NEW_RM;
 963         }
 964
 965         return 0;
 966 }
 967
 968 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 969 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 970 {
 971         int rc = 0;
 972         uint32_t flags;
 973         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 974         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 975
 976         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 977
 978         req.target_id = rte_cpu_to_le_16(0xffff);
 979
 980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 981
 982         HWRM_CHECK_RESULT();
 983
 984         flags = rte_le_to_cpu_32(resp->flags);
 985
 986         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 987                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 988                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 989         }
 990
 991         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 992                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 993
 994         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 995                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 996
 997         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 998
 999         HWRM_UNLOCK();
1000
1001         return rc;
1002 }
1003
1004 int bnxt_hwrm_func_reset(struct bnxt *bp)
1005 {
1006         int rc = 0;
1007         struct hwrm_func_reset_input req = {.req_type = 0 };
1008         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1009
1010         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1011
1012         req.enables = rte_cpu_to_le_32(0);
1013
1014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1015
1016         HWRM_CHECK_RESULT();
1017         HWRM_UNLOCK();
1018
1019         return rc;
1020 }
1021
1022 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1023 {
1024         int rc;
1025         uint32_t flags = 0;
1026         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1027         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1028
1029         if (bp->flags & BNXT_FLAG_REGISTERED)
1030                 return 0;
1031
1032         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1033                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1034         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1035                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1036
1037         /* PFs and trusted VFs should indicate the support of the
1038          * Master capability on non Stingray platform
1039          */
1040         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1041                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1042
1043         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1044         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1045                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1046         req.ver_maj = RTE_VER_YEAR;
1047         req.ver_min = RTE_VER_MONTH;
1048         req.ver_upd = RTE_VER_MINOR;
1049
1050         if (BNXT_PF(bp)) {
1051                 req.enables |= rte_cpu_to_le_32(
1052                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1053                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1054                        RTE_MIN(sizeof(req.vf_req_fwd),
1055                                sizeof(bp->pf->vf_req_fwd)));
1056         }
1057
1058         req.flags = rte_cpu_to_le_32(flags);
1059
1060         req.async_event_fwd[0] |=
1061                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1062                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1063                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1064                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1065                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1066         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1067                 req.async_event_fwd[0] |=
1068                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1069         req.async_event_fwd[1] |=
1070                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1071                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1072         if (BNXT_PF(bp))
1073                 req.async_event_fwd[1] |=
1074                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1075
1076         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1077                 req.async_event_fwd[1] |=
1078                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1079
1080         req.async_event_fwd[2] |=
1081                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1082
1083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1084
1085         HWRM_CHECK_RESULT();
1086
1087         flags = rte_le_to_cpu_32(resp->flags);
1088         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1089                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1090
1091         HWRM_UNLOCK();
1092
1093         bp->flags |= BNXT_FLAG_REGISTERED;
1094
1095         return rc;
1096 }
1097
1098 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1099 {
1100         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1101                 return 0;
1102
1103         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1104 }
1105
1106 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1107 {
1108         int rc;
1109         uint32_t flags = 0;
1110         uint32_t enables;
1111         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1112         struct hwrm_func_vf_cfg_input req = {0};
1113
1114         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1115
1116         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1117                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1118                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1119                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1120                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1121
1122         if (BNXT_HAS_RING_GRPS(bp)) {
1123                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1124                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1125         }
1126
1127         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1128         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1129                                             AGG_RING_MULTIPLIER);
1130         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1131         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1132                                               bp->tx_nr_rings +
1133                                               BNXT_NUM_ASYNC_CPR(bp));
1134         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1135         if (bp->vf_resv_strategy ==
1136             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1137                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1138                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1139                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1140                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1141                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1142                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1143         } else if (bp->vf_resv_strategy ==
1144                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1145                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1146                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1147         }
1148
1149         if (test)
1150                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1151                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1152                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1153                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1154                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1155                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1156
1157         if (test && BNXT_HAS_RING_GRPS(bp))
1158                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1159
1160         req.flags = rte_cpu_to_le_32(flags);
1161         req.enables |= rte_cpu_to_le_32(enables);
1162
1163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1164
1165         if (test)
1166                 HWRM_CHECK_RESULT_SILENT();
1167         else
1168                 HWRM_CHECK_RESULT();
1169
1170         HWRM_UNLOCK();
1171         return rc;
1172 }
1173
1174 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1175 {
1176         int rc;
1177         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1178         struct hwrm_func_resource_qcaps_input req = {0};
1179
1180         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1181         req.fid = rte_cpu_to_le_16(0xffff);
1182
1183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1184
1185         HWRM_CHECK_RESULT_SILENT();
1186
1187         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1188         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1189         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1190         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1191         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1192         /* func_resource_qcaps does not return max_rx_em_flows.
1193          * So use the value provided by func_qcaps.
1194          */
1195         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1196         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1197                 bp->max_l2_ctx += bp->max_rx_em_flows;
1198         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1199         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1200         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1201         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1202         if (bp->vf_resv_strategy >
1203             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1204                 bp->vf_resv_strategy =
1205                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1206
1207         HWRM_UNLOCK();
1208         return rc;
1209 }
1210
1211 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1212 {
1213         int rc = 0;
1214         struct hwrm_ver_get_input req = {.req_type = 0 };
1215         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1216         uint32_t fw_version;
1217         uint16_t max_resp_len;
1218         char type[RTE_MEMZONE_NAMESIZE];
1219         uint32_t dev_caps_cfg;
1220
1221         bp->max_req_len = HWRM_MAX_REQ_LEN;
1222         bp->hwrm_cmd_timeout = timeout;
1223         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1224
1225         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1226         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1227         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1228
1229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1230
1231         if (bp->flags & BNXT_FLAG_FW_RESET)
1232                 HWRM_CHECK_RESULT_SILENT();
1233         else
1234                 HWRM_CHECK_RESULT();
1235
1236         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1237                 rc = -EAGAIN;
1238                 goto error;
1239         }
1240
1241         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1242                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1243                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1244                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1245                 resp->hwrm_fw_rsvd_8b);
1246         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1247                      (resp->hwrm_fw_min_8b << 16) |
1248                      (resp->hwrm_fw_bld_8b << 8) |
1249                      resp->hwrm_fw_rsvd_8b;
1250         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1251                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1252
1253         fw_version = resp->hwrm_intf_maj_8b << 16;
1254         fw_version |= resp->hwrm_intf_min_8b << 8;
1255         fw_version |= resp->hwrm_intf_upd_8b;
1256         bp->hwrm_spec_code = fw_version;
1257
1258         /* def_req_timeout value is in milliseconds */
1259         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1260         /* convert timeout to usec */
1261         bp->hwrm_cmd_timeout *= 1000;
1262         if (!bp->hwrm_cmd_timeout)
1263                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1264
1265         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1266                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1267                 rc = -EINVAL;
1268                 goto error;
1269         }
1270
1271         if (bp->max_req_len > resp->max_req_win_len) {
1272                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1273                 rc = -EINVAL;
1274                 goto error;
1275         }
1276
1277         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1278
1279         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1280         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1281         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1282                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1283
1284         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1285         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1286
1287         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1288         bp->max_resp_len = max_resp_len;
1289
1290         if ((dev_caps_cfg &
1291                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1292             (dev_caps_cfg &
1293              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1294                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1295                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1296         }
1297
1298         if (((dev_caps_cfg &
1299               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1300              (dev_caps_cfg &
1301               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1302             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1303                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1304                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1305                         bp->pdev->addr.devid, bp->pdev->addr.function);
1306
1307                 rte_free(bp->hwrm_short_cmd_req_addr);
1308
1309                 bp->hwrm_short_cmd_req_addr =
1310                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1311                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1312                         rc = -ENOMEM;
1313                         goto error;
1314                 }
1315                 bp->hwrm_short_cmd_req_dma_addr =
1316                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1317                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1318                         rte_free(bp->hwrm_short_cmd_req_addr);
1319                         PMD_DRV_LOG(ERR,
1320                                 "Unable to map buffer to physical memory.\n");
1321                         rc = -ENOMEM;
1322                         goto error;
1323                 }
1324         }
1325         if (dev_caps_cfg &
1326             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1327                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1328                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1329         }
1330         if (dev_caps_cfg &
1331             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1332                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1333         if (dev_caps_cfg &
1334             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1335                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1336                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1337         }
1338
1339         if (dev_caps_cfg &
1340             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1341                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1342                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1343         }
1344
1345 error:
1346         HWRM_UNLOCK();
1347         return rc;
1348 }
1349
1350 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1351 {
1352         int rc;
1353         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1354         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1355
1356         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1357                 return 0;
1358
1359         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1360         req.flags = flags;
1361
1362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1363
1364         HWRM_CHECK_RESULT();
1365         HWRM_UNLOCK();
1366
1367         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1368                     bp->eth_dev->data->port_id);
1369
1370         return rc;
1371 }
1372
1373 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1374 {
1375         int rc = 0;
1376         struct hwrm_port_phy_cfg_input req = {0};
1377         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1378         uint32_t enables = 0;
1379
1380         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1381
1382         if (conf->link_up) {
1383                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1384                 if (bp->link_info->auto_mode && conf->link_speed) {
1385                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1386                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1387                 }
1388
1389                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1390                 /*
1391                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1392                  * any auto mode, even "none".
1393                  */
1394                 if (!conf->link_speed) {
1395                         /* No speeds specified. Enable AutoNeg - all speeds */
1396                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1397                         req.auto_mode =
1398                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1399                 } else {
1400                         if (bp->link_info->link_signal_mode) {
1401                                 enables |=
1402                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1403                                 req.force_pam4_link_speed =
1404                                         rte_cpu_to_le_16(conf->link_speed);
1405                         } else {
1406                                 req.force_link_speed =
1407                                         rte_cpu_to_le_16(conf->link_speed);
1408                         }
1409                 }
1410                 /* AutoNeg - Advertise speeds specified. */
1411                 if (conf->auto_link_speed_mask &&
1412                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1413                         req.auto_mode =
1414                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1415                         req.auto_link_speed_mask =
1416                                 conf->auto_link_speed_mask;
1417                         if (conf->auto_pam4_link_speeds) {
1418                                 enables |=
1419                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1420                                 req.auto_link_pam4_speed_mask =
1421                                         conf->auto_pam4_link_speeds;
1422                         } else {
1423                                 enables |=
1424                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1425                         }
1426                 }
1427                 if (conf->auto_link_speed &&
1428                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1429                         enables |=
1430                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1431
1432                 req.auto_duplex = conf->duplex;
1433                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1434                 req.auto_pause = conf->auto_pause;
1435                 req.force_pause = conf->force_pause;
1436                 /* Set force_pause if there is no auto or if there is a force */
1437                 if (req.auto_pause && !req.force_pause)
1438                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1439                 else
1440                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1441
1442                 req.enables = rte_cpu_to_le_32(enables);
1443         } else {
1444                 req.flags =
1445                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1446                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1447         }
1448
1449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1450
1451         HWRM_CHECK_RESULT();
1452         HWRM_UNLOCK();
1453
1454         return rc;
1455 }
1456
1457 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1458                                    struct bnxt_link_info *link_info)
1459 {
1460         int rc = 0;
1461         struct hwrm_port_phy_qcfg_input req = {0};
1462         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1463
1464         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1465
1466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1467
1468         HWRM_CHECK_RESULT();
1469
1470         link_info->phy_link_status = resp->link;
1471         link_info->link_up =
1472                 (link_info->phy_link_status ==
1473                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1474         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1475         link_info->duplex = resp->duplex_cfg;
1476         link_info->pause = resp->pause;
1477         link_info->auto_pause = resp->auto_pause;
1478         link_info->force_pause = resp->force_pause;
1479         link_info->auto_mode = resp->auto_mode;
1480         link_info->phy_type = resp->phy_type;
1481         link_info->media_type = resp->media_type;
1482
1483         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1484         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1485         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1486         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1487         link_info->phy_ver[0] = resp->phy_maj;
1488         link_info->phy_ver[1] = resp->phy_min;
1489         link_info->phy_ver[2] = resp->phy_bld;
1490         link_info->link_signal_mode =
1491                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1492         link_info->force_pam4_link_speed =
1493                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1494         link_info->support_pam4_speeds =
1495                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1496         link_info->auto_pam4_link_speeds =
1497                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1498         HWRM_UNLOCK();
1499
1500         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1501                     link_info->link_speed, link_info->auto_mode,
1502                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1503                     link_info->support_speeds, link_info->force_link_speed);
1504         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1505                     link_info->link_signal_mode,
1506                     link_info->auto_pam4_link_speeds,
1507                     link_info->support_pam4_speeds,
1508                     link_info->force_pam4_link_speed);
1509         return rc;
1510 }
1511
1512 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1513 {
1514         int rc = 0;
1515         struct hwrm_port_phy_qcaps_input req = {0};
1516         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1517         struct bnxt_link_info *link_info = bp->link_info;
1518
1519         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1520                 return 0;
1521
1522         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1523
1524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1525
1526         HWRM_CHECK_RESULT_SILENT();
1527
1528         bp->port_cnt = resp->port_cnt;
1529         if (resp->supported_speeds_auto_mode)
1530                 link_info->support_auto_speeds =
1531                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1532         if (resp->supported_pam4_speeds_auto_mode)
1533                 link_info->support_pam4_auto_speeds =
1534                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1535
1536         HWRM_UNLOCK();
1537
1538         return 0;
1539 }
1540
1541 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1542 {
1543         int i = 0;
1544
1545         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1546                 if (bp->tx_cos_queue[i].profile ==
1547                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1548                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1549                         return true;
1550                 }
1551         }
1552         return false;
1553 }
1554
1555 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1556 {
1557         int i = 0;
1558
1559         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1560                 if (bp->tx_cos_queue[i].profile !=
1561                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1562                     bp->tx_cos_queue[i].id !=
1563                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1564                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1565                         break;
1566                 }
1567         }
1568 }
1569
1570 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1571 {
1572         int rc = 0;
1573         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1574         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1575         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1576         int i;
1577
1578 get_rx_info:
1579         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1580
1581         req.flags = rte_cpu_to_le_32(dir);
1582         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1583         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1584             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1585                 req.drv_qmap_cap =
1586                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1588
1589         HWRM_CHECK_RESULT();
1590
1591         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1592                 GET_TX_QUEUE_INFO(0);
1593                 GET_TX_QUEUE_INFO(1);
1594                 GET_TX_QUEUE_INFO(2);
1595                 GET_TX_QUEUE_INFO(3);
1596                 GET_TX_QUEUE_INFO(4);
1597                 GET_TX_QUEUE_INFO(5);
1598                 GET_TX_QUEUE_INFO(6);
1599                 GET_TX_QUEUE_INFO(7);
1600         } else  {
1601                 GET_RX_QUEUE_INFO(0);
1602                 GET_RX_QUEUE_INFO(1);
1603                 GET_RX_QUEUE_INFO(2);
1604                 GET_RX_QUEUE_INFO(3);
1605                 GET_RX_QUEUE_INFO(4);
1606                 GET_RX_QUEUE_INFO(5);
1607                 GET_RX_QUEUE_INFO(6);
1608                 GET_RX_QUEUE_INFO(7);
1609         }
1610
1611         HWRM_UNLOCK();
1612
1613         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1614                 goto done;
1615
1616         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1617                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1618         } else {
1619                 int j;
1620
1621                 /* iterate and find the COSq profile to use for Tx */
1622                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1623                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1624                                 if (bp->tx_cos_queue[i].id != 0xff)
1625                                         bp->tx_cosq_id[j++] =
1626                                                 bp->tx_cos_queue[i].id;
1627                         }
1628                 } else {
1629                         /* When CoS classification is disabled, for normal NIC
1630                          * operations, ideally we should look to use LOSSY.
1631                          * If not found, fallback to the first valid profile
1632                          */
1633                         if (!bnxt_find_lossy_profile(bp))
1634                                 bnxt_find_first_valid_profile(bp);
1635
1636                 }
1637         }
1638
1639         bp->max_tc = resp->max_configurable_queues;
1640         bp->max_lltc = resp->max_configurable_lossless_queues;
1641         if (bp->max_tc > BNXT_MAX_QUEUE)
1642                 bp->max_tc = BNXT_MAX_QUEUE;
1643         bp->max_q = bp->max_tc;
1644
1645         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1646                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1647                 goto get_rx_info;
1648         }
1649
1650 done:
1651         return rc;
1652 }
1653
1654 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1655                          struct bnxt_ring *ring,
1656                          uint32_t ring_type, uint32_t map_index,
1657                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1658                          uint16_t tx_cosq_id)
1659 {
1660         int rc = 0;
1661         uint32_t enables = 0;
1662         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1663         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1664         struct rte_mempool *mb_pool;
1665         uint16_t rx_buf_size;
1666
1667         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1668
1669         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1670         req.fbo = rte_cpu_to_le_32(0);
1671         /* Association of ring index with doorbell index */
1672         req.logical_id = rte_cpu_to_le_16(map_index);
1673         req.length = rte_cpu_to_le_32(ring->ring_size);
1674
1675         switch (ring_type) {
1676         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1677                 req.ring_type = ring_type;
1678                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1679                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1680                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1681                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1682                         enables |=
1683                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1684                 break;
1685         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1686                 req.ring_type = ring_type;
1687                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1688                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1689                 if (BNXT_CHIP_P5(bp)) {
1690                         mb_pool = bp->rx_queues[0]->mb_pool;
1691                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1692                                       RTE_PKTMBUF_HEADROOM;
1693                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1694                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1695                         enables |=
1696                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1697                 }
1698                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1699                         enables |=
1700                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1701                 break;
1702         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1703                 req.ring_type = ring_type;
1704                 if (BNXT_HAS_NQ(bp)) {
1705                         /* Association of cp ring with nq */
1706                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1707                         enables |=
1708                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1709                 }
1710                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1711                 break;
1712         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1713                 req.ring_type = ring_type;
1714                 req.page_size = BNXT_PAGE_SHFT;
1715                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1716                 break;
1717         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1718                 req.ring_type = ring_type;
1719                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1720
1721                 mb_pool = bp->rx_queues[0]->mb_pool;
1722                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1723                               RTE_PKTMBUF_HEADROOM;
1724                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1725                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1726
1727                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1728                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1729                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1730                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1731                 break;
1732         default:
1733                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1734                         ring_type);
1735                 HWRM_UNLOCK();
1736                 return -EINVAL;
1737         }
1738         req.enables = rte_cpu_to_le_32(enables);
1739
1740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1741
1742         if (rc || resp->error_code) {
1743                 if (rc == 0 && resp->error_code)
1744                         rc = rte_le_to_cpu_16(resp->error_code);
1745                 switch (ring_type) {
1746                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1747                         PMD_DRV_LOG(ERR,
1748                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1749                         HWRM_UNLOCK();
1750                         return rc;
1751                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1752                         PMD_DRV_LOG(ERR,
1753                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1754                         HWRM_UNLOCK();
1755                         return rc;
1756                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1757                         PMD_DRV_LOG(ERR,
1758                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1759                                     rc);
1760                         HWRM_UNLOCK();
1761                         return rc;
1762                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1763                         PMD_DRV_LOG(ERR,
1764                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1765                         HWRM_UNLOCK();
1766                         return rc;
1767                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1768                         PMD_DRV_LOG(ERR,
1769                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1770                         HWRM_UNLOCK();
1771                         return rc;
1772                 default:
1773                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1774                         HWRM_UNLOCK();
1775                         return rc;
1776                 }
1777         }
1778
1779         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1780         HWRM_UNLOCK();
1781         return rc;
1782 }
1783
1784 int bnxt_hwrm_ring_free(struct bnxt *bp,
1785                         struct bnxt_ring *ring, uint32_t ring_type,
1786                         uint16_t cp_ring_id)
1787 {
1788         int rc;
1789         struct hwrm_ring_free_input req = {.req_type = 0 };
1790         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1791
1792         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1793
1794         req.ring_type = ring_type;
1795         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1796         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1797
1798         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1799
1800         if (rc || resp->error_code) {
1801                 if (rc == 0 && resp->error_code)
1802                         rc = rte_le_to_cpu_16(resp->error_code);
1803                 HWRM_UNLOCK();
1804
1805                 switch (ring_type) {
1806                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1807                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1808                                 rc);
1809                         return rc;
1810                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1811                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1812                                 rc);
1813                         return rc;
1814                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1815                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1816                                 rc);
1817                         return rc;
1818                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1819                         PMD_DRV_LOG(ERR,
1820                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1821                         return rc;
1822                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1823                         PMD_DRV_LOG(ERR,
1824                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1825                         return rc;
1826                 default:
1827                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1828                         return rc;
1829                 }
1830         }
1831         HWRM_UNLOCK();
1832         return 0;
1833 }
1834
1835 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1836 {
1837         int rc = 0;
1838         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1839         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1840
1841         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1842
1843         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1844         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1845         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1846         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1847
1848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1849
1850         HWRM_CHECK_RESULT();
1851
1852         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1853
1854         HWRM_UNLOCK();
1855
1856         return rc;
1857 }
1858
1859 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1860 {
1861         int rc;
1862         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1863         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1864
1865         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1866
1867         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1868
1869         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1870
1871         HWRM_CHECK_RESULT();
1872         HWRM_UNLOCK();
1873
1874         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1875         return rc;
1876 }
1877
1878 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1879 {
1880         int rc = 0;
1881         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1882         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1883
1884         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1885                 return rc;
1886
1887         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1888
1889         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1890
1891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892
1893         HWRM_CHECK_RESULT();
1894         HWRM_UNLOCK();
1895
1896         return rc;
1897 }
1898
1899 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1900                                 unsigned int idx __rte_unused)
1901 {
1902         int rc;
1903         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1904         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1905
1906         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1907
1908         req.update_period_ms = rte_cpu_to_le_32(0);
1909
1910         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1911
1912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913
1914         HWRM_CHECK_RESULT();
1915
1916         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1917
1918         HWRM_UNLOCK();
1919
1920         return rc;
1921 }
1922
1923 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1924                                 unsigned int idx __rte_unused)
1925 {
1926         int rc;
1927         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1928         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1929
1930         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1931
1932         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1933
1934         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1935
1936         HWRM_CHECK_RESULT();
1937         HWRM_UNLOCK();
1938
1939         return rc;
1940 }
1941
1942 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1943 {
1944         int rc = 0, i, j;
1945         struct hwrm_vnic_alloc_input req = { 0 };
1946         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1947
1948         if (!BNXT_HAS_RING_GRPS(bp))
1949                 goto skip_ring_grps;
1950
1951         /* map ring groups to this vnic */
1952         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1953                 vnic->start_grp_id, vnic->end_grp_id);
1954         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1955                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1956
1957         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1958         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1959         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1960         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1961
1962 skip_ring_grps:
1963         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1964         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1965
1966         if (vnic->func_default)
1967                 req.flags =
1968                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1970
1971         HWRM_CHECK_RESULT();
1972
1973         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1974         HWRM_UNLOCK();
1975         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1976         return rc;
1977 }
1978
1979 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1980                                         struct bnxt_vnic_info *vnic,
1981                                         struct bnxt_plcmodes_cfg *pmode)
1982 {
1983         int rc = 0;
1984         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1985         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1986
1987         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1988
1989         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1990
1991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1992
1993         HWRM_CHECK_RESULT();
1994
1995         pmode->flags = rte_le_to_cpu_32(resp->flags);
1996         /* dflt_vnic bit doesn't exist in the _cfg command */
1997         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1998         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1999         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2000         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2001
2002         HWRM_UNLOCK();
2003
2004         return rc;
2005 }
2006
2007 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2008                                        struct bnxt_vnic_info *vnic,
2009                                        struct bnxt_plcmodes_cfg *pmode)
2010 {
2011         int rc = 0;
2012         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2013         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2014
2015         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2016                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2017                 return rc;
2018         }
2019
2020         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2021
2022         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2023         req.flags = rte_cpu_to_le_32(pmode->flags);
2024         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2025         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2026         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2027         req.enables = rte_cpu_to_le_32(
2028             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2029             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2030             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2031         );
2032
2033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2034
2035         HWRM_CHECK_RESULT();
2036         HWRM_UNLOCK();
2037
2038         return rc;
2039 }
2040
2041 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2042 {
2043         int rc = 0;
2044         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2045         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2046         struct bnxt_plcmodes_cfg pmodes = { 0 };
2047         uint32_t ctx_enable_flag = 0;
2048         uint32_t enables = 0;
2049
2050         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2051                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2052                 return rc;
2053         }
2054
2055         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2056         if (rc)
2057                 return rc;
2058
2059         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2060
2061         if (BNXT_CHIP_P5(bp)) {
2062                 int dflt_rxq = vnic->start_grp_id;
2063                 struct bnxt_rx_ring_info *rxr;
2064                 struct bnxt_cp_ring_info *cpr;
2065                 struct bnxt_rx_queue *rxq;
2066                 int i;
2067
2068                 /*
2069                  * The first active receive ring is used as the VNIC
2070                  * default receive ring. If there are no active receive
2071                  * rings (all corresponding receive queues are stopped),
2072                  * the first receive ring is used.
2073                  */
2074                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2075                         rxq = bp->eth_dev->data->rx_queues[i];
2076                         if (rxq->rx_started) {
2077                                 dflt_rxq = i;
2078                                 break;
2079                         }
2080                 }
2081
2082                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2083                 rxr = rxq->rx_ring;
2084                 cpr = rxq->cp_ring;
2085
2086                 req.default_rx_ring_id =
2087                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2088                 req.default_cmpl_ring_id =
2089                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2090                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2091                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2092                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2093                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2094                         req.rx_csum_v2_mode =
2095                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2096                 }
2097                 goto config_mru;
2098         }
2099
2100         /* Only RSS support for now TBD: COS & LB */
2101         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2102         if (vnic->lb_rule != 0xffff)
2103                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2104         if (vnic->cos_rule != 0xffff)
2105                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2106         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2107                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2108                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2109         }
2110         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2111                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2112                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2113         }
2114
2115         enables |= ctx_enable_flag;
2116         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2117         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2118         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2119         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2120
2121 config_mru:
2122         req.enables = rte_cpu_to_le_32(enables);
2123         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2124         req.mru = rte_cpu_to_le_16(vnic->mru);
2125         /* Configure default VNIC only once. */
2126         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2127                 req.flags |=
2128                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2129                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2130         }
2131         if (vnic->vlan_strip)
2132                 req.flags |=
2133                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2134         if (vnic->bd_stall)
2135                 req.flags |=
2136                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2137         if (vnic->rss_dflt_cr)
2138                 req.flags |= rte_cpu_to_le_32(
2139                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2140
2141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2142
2143         HWRM_CHECK_RESULT();
2144         HWRM_UNLOCK();
2145
2146         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2147
2148         return rc;
2149 }
2150
2151 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2152                 int16_t fw_vf_id)
2153 {
2154         int rc = 0;
2155         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2156         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2157
2158         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2159                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2160                 return rc;
2161         }
2162         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2163
2164         req.enables =
2165                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2166         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2167         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2168
2169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2170
2171         HWRM_CHECK_RESULT();
2172
2173         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2174         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2175         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2176         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2177         vnic->mru = rte_le_to_cpu_16(resp->mru);
2178         vnic->func_default = rte_le_to_cpu_32(
2179                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2180         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2181                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2182         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2183                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2184         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2185                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2186
2187         HWRM_UNLOCK();
2188
2189         return rc;
2190 }
2191
2192 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2193                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2194 {
2195         int rc = 0;
2196         uint16_t ctx_id;
2197         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2198         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2199                                                 bp->hwrm_cmd_resp_addr;
2200
2201         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2202
2203         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2204         HWRM_CHECK_RESULT();
2205
2206         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2207         if (!BNXT_HAS_RING_GRPS(bp))
2208                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2209         else if (ctx_idx == 0)
2210                 vnic->rss_rule = ctx_id;
2211
2212         HWRM_UNLOCK();
2213
2214         return rc;
2215 }
2216
2217 static
2218 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2219                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2220 {
2221         int rc = 0;
2222         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2223         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2224                                                 bp->hwrm_cmd_resp_addr;
2225
2226         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2227                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2228                 return rc;
2229         }
2230         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2231
2232         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2233
2234         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2235
2236         HWRM_CHECK_RESULT();
2237         HWRM_UNLOCK();
2238
2239         return rc;
2240 }
2241
2242 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2243 {
2244         int rc = 0;
2245
2246         if (BNXT_CHIP_P5(bp)) {
2247                 int j;
2248
2249                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2250                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2251                                                       vnic,
2252                                                       vnic->fw_grp_ids[j]);
2253                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2254                 }
2255                 vnic->num_lb_ctxts = 0;
2256         } else {
2257                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2258                 vnic->rss_rule = INVALID_HW_RING_ID;
2259         }
2260
2261         return rc;
2262 }
2263
2264 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2265 {
2266         int rc = 0;
2267         struct hwrm_vnic_free_input req = {.req_type = 0 };
2268         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2269
2270         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2271                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2272                 return rc;
2273         }
2274
2275         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2276
2277         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2278
2279         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2280
2281         HWRM_CHECK_RESULT();
2282         HWRM_UNLOCK();
2283
2284         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2285         /* Configure default VNIC again if necessary. */
2286         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2287                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2288
2289         return rc;
2290 }
2291
2292 static int
2293 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2294 {
2295         int i;
2296         int rc = 0;
2297         int nr_ctxs = vnic->num_lb_ctxts;
2298         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2299         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2300
2301         for (i = 0; i < nr_ctxs; i++) {
2302                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2303
2304                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2305                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2306                 req.hash_mode_flags = vnic->hash_mode;
2307
2308                 req.hash_key_tbl_addr =
2309                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2310
2311                 req.ring_grp_tbl_addr =
2312                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2313                                          i * HW_HASH_INDEX_SIZE);
2314                 req.ring_table_pair_index = i;
2315                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2316
2317                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2318                                             BNXT_USE_CHIMP_MB);
2319
2320                 HWRM_CHECK_RESULT();
2321                 HWRM_UNLOCK();
2322         }
2323
2324         return rc;
2325 }
2326
2327 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2328                            struct bnxt_vnic_info *vnic)
2329 {
2330         int rc = 0;
2331         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2332         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2333
2334         if (!vnic->rss_table)
2335                 return 0;
2336
2337         if (BNXT_CHIP_P5(bp))
2338                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2339
2340         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2341
2342         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2343         req.hash_mode_flags = vnic->hash_mode;
2344
2345         req.ring_grp_tbl_addr =
2346             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2347         req.hash_key_tbl_addr =
2348             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2349         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2350         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2351
2352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2353
2354         HWRM_CHECK_RESULT();
2355         HWRM_UNLOCK();
2356
2357         return rc;
2358 }
2359
2360 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2361                         struct bnxt_vnic_info *vnic)
2362 {
2363         int rc = 0;
2364         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2365         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2366         uint16_t size;
2367
2368         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2369                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2370                 return rc;
2371         }
2372
2373         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2374
2375         req.flags = rte_cpu_to_le_32(
2376                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2377
2378         req.enables = rte_cpu_to_le_32(
2379                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2380
2381         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2382         size -= RTE_PKTMBUF_HEADROOM;
2383         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2384
2385         req.jumbo_thresh = rte_cpu_to_le_16(size);
2386         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2387
2388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2389
2390         HWRM_CHECK_RESULT();
2391         HWRM_UNLOCK();
2392
2393         return rc;
2394 }
2395
2396 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2397                         struct bnxt_vnic_info *vnic, bool enable)
2398 {
2399         int rc = 0;
2400         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2401         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2402
2403         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2404                 if (enable)
2405                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2406                 return -ENOTSUP;
2407         }
2408
2409         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2410                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2411                 return 0;
2412         }
2413
2414         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2415
2416         if (enable) {
2417                 req.enables = rte_cpu_to_le_32(
2418                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2419                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2420                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2421                 req.flags = rte_cpu_to_le_32(
2422                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2423                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2424                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2425                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2426                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2427                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2428                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2429                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2430                 req.min_agg_len = rte_cpu_to_le_32(512);
2431         }
2432         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2433
2434         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2435
2436         HWRM_CHECK_RESULT();
2437         HWRM_UNLOCK();
2438
2439         return rc;
2440 }
2441
2442 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2443 {
2444         struct hwrm_func_cfg_input req = {0};
2445         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2446         int rc;
2447
2448         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2449         req.enables = rte_cpu_to_le_32(
2450                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2451         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2452         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2453
2454         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2455
2456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2457         HWRM_CHECK_RESULT();
2458         HWRM_UNLOCK();
2459
2460         bp->pf->vf_info[vf].random_mac = false;
2461
2462         return rc;
2463 }
2464
2465 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2466                                   uint64_t *dropped)
2467 {
2468         int rc = 0;
2469         struct hwrm_func_qstats_input req = {.req_type = 0};
2470         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2471
2472         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2473
2474         req.fid = rte_cpu_to_le_16(fid);
2475
2476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2477
2478         HWRM_CHECK_RESULT();
2479
2480         if (dropped)
2481                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2482
2483         HWRM_UNLOCK();
2484
2485         return rc;
2486 }
2487
2488 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2489                           struct rte_eth_stats *stats,
2490                           struct hwrm_func_qstats_output *func_qstats)
2491 {
2492         int rc = 0;
2493         struct hwrm_func_qstats_input req = {.req_type = 0};
2494         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2495
2496         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2497
2498         req.fid = rte_cpu_to_le_16(fid);
2499
2500         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2501
2502         HWRM_CHECK_RESULT();
2503         if (func_qstats)
2504                 memcpy(func_qstats, resp,
2505                        sizeof(struct hwrm_func_qstats_output));
2506
2507         if (!stats)
2508                 goto exit;
2509
2510         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2511         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2512         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2513         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2514         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2515         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2516
2517         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2518         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2519         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2520         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2521         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2522         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2523
2524         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2525         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2526         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2527
2528 exit:
2529         HWRM_UNLOCK();
2530
2531         return rc;
2532 }
2533
2534 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2535 {
2536         int rc = 0;
2537         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2538         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2539
2540         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2541
2542         req.fid = rte_cpu_to_le_16(fid);
2543
2544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2545
2546         HWRM_CHECK_RESULT();
2547         HWRM_UNLOCK();
2548
2549         return rc;
2550 }
2551
2552 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2553 {
2554         unsigned int i;
2555         int rc = 0;
2556
2557         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2558                 struct bnxt_tx_queue *txq;
2559                 struct bnxt_rx_queue *rxq;
2560                 struct bnxt_cp_ring_info *cpr;
2561
2562                 if (i >= bp->rx_cp_nr_rings) {
2563                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2564                         cpr = txq->cp_ring;
2565                 } else {
2566                         rxq = bp->rx_queues[i];
2567                         cpr = rxq->cp_ring;
2568                 }
2569
2570                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2571                 if (rc)
2572                         return rc;
2573         }
2574         return 0;
2575 }
2576
2577 static int
2578 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2579 {
2580         int rc;
2581         unsigned int i;
2582         struct bnxt_cp_ring_info *cpr;
2583
2584         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2585
2586                 if (i >= bp->rx_cp_nr_rings) {
2587                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2588                 } else {
2589                         cpr = bp->rx_queues[i]->cp_ring;
2590                         if (BNXT_HAS_RING_GRPS(bp))
2591                                 bp->grp_info[i].fw_stats_ctx = -1;
2592                 }
2593                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2594                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2595                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2596                         if (rc)
2597                                 return rc;
2598                 }
2599         }
2600         return 0;
2601 }
2602
2603 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2604 {
2605         unsigned int i;
2606         int rc = 0;
2607
2608         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2609                 struct bnxt_tx_queue *txq;
2610                 struct bnxt_rx_queue *rxq;
2611                 struct bnxt_cp_ring_info *cpr;
2612
2613                 if (i >= bp->rx_cp_nr_rings) {
2614                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2615                         cpr = txq->cp_ring;
2616                 } else {
2617                         rxq = bp->rx_queues[i];
2618                         cpr = rxq->cp_ring;
2619                 }
2620
2621                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2622
2623                 if (rc)
2624                         return rc;
2625         }
2626         return rc;
2627 }
2628
2629 static int
2630 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2631 {
2632         uint16_t idx;
2633         uint32_t rc = 0;
2634
2635         if (!BNXT_HAS_RING_GRPS(bp))
2636                 return 0;
2637
2638         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2639
2640                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2641                         continue;
2642
2643                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2644
2645                 if (rc)
2646                         return rc;
2647         }
2648         return rc;
2649 }
2650
2651 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2652 {
2653         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2654
2655         bnxt_hwrm_ring_free(bp, cp_ring,
2656                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2657                             INVALID_HW_RING_ID);
2658         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2659         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2660                                      sizeof(*cpr->cp_desc_ring));
2661         cpr->cp_raw_cons = 0;
2662         cpr->valid = 0;
2663 }
2664
2665 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2666 {
2667         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2668
2669         bnxt_hwrm_ring_free(bp, cp_ring,
2670                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2671                         INVALID_HW_RING_ID);
2672         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2673         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2674                         sizeof(*cpr->cp_desc_ring));
2675         cpr->cp_raw_cons = 0;
2676         cpr->valid = 0;
2677 }
2678
2679 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2680 {
2681         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2682         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2683         struct bnxt_ring *ring = rxr->rx_ring_struct;
2684         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2685
2686         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2687                 bnxt_hwrm_ring_free(bp, ring,
2688                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2689                                     cpr->cp_ring_struct->fw_ring_id);
2690                 ring->fw_ring_id = INVALID_HW_RING_ID;
2691                 if (BNXT_HAS_RING_GRPS(bp))
2692                         bp->grp_info[queue_index].rx_fw_ring_id =
2693                                                         INVALID_HW_RING_ID;
2694         }
2695         ring = rxr->ag_ring_struct;
2696         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2697                 bnxt_hwrm_ring_free(bp, ring,
2698                                     BNXT_CHIP_P5(bp) ?
2699                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2700                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2701                                     cpr->cp_ring_struct->fw_ring_id);
2702                 if (BNXT_HAS_RING_GRPS(bp))
2703                         bp->grp_info[queue_index].ag_fw_ring_id =
2704                                                         INVALID_HW_RING_ID;
2705         }
2706         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2707                 bnxt_free_cp_ring(bp, cpr);
2708
2709         if (BNXT_HAS_RING_GRPS(bp))
2710                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2711 }
2712
2713 static int
2714 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2715 {
2716         unsigned int i;
2717
2718         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2719                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2720                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2721                 struct bnxt_ring *ring = txr->tx_ring_struct;
2722                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2723
2724                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2725                         bnxt_hwrm_ring_free(bp, ring,
2726                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2727                                         cpr->cp_ring_struct->fw_ring_id);
2728                         ring->fw_ring_id = INVALID_HW_RING_ID;
2729                         memset(txr->tx_desc_ring, 0,
2730                                         txr->tx_ring_struct->ring_size *
2731                                         sizeof(*txr->tx_desc_ring));
2732                         memset(txr->tx_buf_ring, 0,
2733                                         txr->tx_ring_struct->ring_size *
2734                                         sizeof(*txr->tx_buf_ring));
2735                         txr->tx_raw_prod = 0;
2736                         txr->tx_raw_cons = 0;
2737                 }
2738                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2739                         bnxt_free_cp_ring(bp, cpr);
2740                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2741                 }
2742         }
2743
2744         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2745                 bnxt_free_hwrm_rx_ring(bp, i);
2746
2747         return 0;
2748 }
2749
2750 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2751 {
2752         uint16_t i;
2753         uint32_t rc = 0;
2754
2755         if (!BNXT_HAS_RING_GRPS(bp))
2756                 return 0;
2757
2758         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2759                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2760                 if (rc)
2761                         return rc;
2762         }
2763         return rc;
2764 }
2765
2766 /*
2767  * HWRM utility functions
2768  */
2769
2770 void bnxt_free_hwrm_resources(struct bnxt *bp)
2771 {
2772         /* Release memzone */
2773         rte_free(bp->hwrm_cmd_resp_addr);
2774         rte_free(bp->hwrm_short_cmd_req_addr);
2775         bp->hwrm_cmd_resp_addr = NULL;
2776         bp->hwrm_short_cmd_req_addr = NULL;
2777         bp->hwrm_cmd_resp_dma_addr = 0;
2778         bp->hwrm_short_cmd_req_dma_addr = 0;
2779 }
2780
2781 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2782 {
2783         struct rte_pci_device *pdev = bp->pdev;
2784         char type[RTE_MEMZONE_NAMESIZE];
2785
2786         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2787                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2788         bp->max_resp_len = BNXT_PAGE_SIZE;
2789         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2790         if (bp->hwrm_cmd_resp_addr == NULL)
2791                 return -ENOMEM;
2792         bp->hwrm_cmd_resp_dma_addr =
2793                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2794         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2795                 PMD_DRV_LOG(ERR,
2796                         "unable to map response address to physical memory\n");
2797                 return -ENOMEM;
2798         }
2799         rte_spinlock_init(&bp->hwrm_lock);
2800
2801         return 0;
2802 }
2803
2804 int
2805 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2806 {
2807         int rc = 0;
2808
2809         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2810                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2811                 if (rc)
2812                         return rc;
2813         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2814                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2815                 if (rc)
2816                         return rc;
2817         }
2818
2819         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2820         return rc;
2821 }
2822
2823 static int
2824 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2825 {
2826         struct bnxt_filter_info *filter;
2827         int rc = 0;
2828
2829         STAILQ_FOREACH(filter, &vnic->filter, next) {
2830                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2831                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2832                 bnxt_free_filter(bp, filter);
2833         }
2834         return rc;
2835 }
2836
2837 static int
2838 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2839 {
2840         struct bnxt_filter_info *filter;
2841         struct rte_flow *flow;
2842         int rc = 0;
2843
2844         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2845                 flow = STAILQ_FIRST(&vnic->flow_list);
2846                 filter = flow->filter;
2847                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2848                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2849
2850                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2851                 rte_free(flow);
2852         }
2853         return rc;
2854 }
2855
2856 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2857 {
2858         struct bnxt_filter_info *filter;
2859         int rc = 0;
2860
2861         STAILQ_FOREACH(filter, &vnic->filter, next) {
2862                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2863                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2864                                                      filter);
2865                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2866                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2867                                                          filter);
2868                 else
2869                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2870                                                      filter);
2871                 if (rc)
2872                         break;
2873         }
2874         return rc;
2875 }
2876
2877 static void
2878 bnxt_free_tunnel_ports(struct bnxt *bp)
2879 {
2880         if (bp->vxlan_port_cnt)
2881                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2882                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2883
2884         if (bp->geneve_port_cnt)
2885                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2886                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2887 }
2888
2889 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2890 {
2891         int i;
2892
2893         if (bp->vnic_info == NULL)
2894                 return;
2895
2896         /*
2897          * Cleanup VNICs in reverse order, to make sure the L2 filter
2898          * from vnic0 is last to be cleaned up.
2899          */
2900         for (i = bp->max_vnics - 1; i >= 0; i--) {
2901                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2902
2903                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2904                         continue;
2905
2906                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2907
2908                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2909
2910                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2911
2912                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2913
2914                 bnxt_hwrm_vnic_free(bp, vnic);
2915
2916                 rte_free(vnic->fw_grp_ids);
2917         }
2918         /* Ring resources */
2919         bnxt_free_all_hwrm_rings(bp);
2920         bnxt_free_all_hwrm_ring_grps(bp);
2921         bnxt_free_all_hwrm_stat_ctxs(bp);
2922         bnxt_free_tunnel_ports(bp);
2923 }
2924
2925 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2926 {
2927         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2928
2929         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2930                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2931
2932         switch (conf_link_speed) {
2933         case ETH_LINK_SPEED_10M_HD:
2934         case ETH_LINK_SPEED_100M_HD:
2935                 /* FALLTHROUGH */
2936                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2937         }
2938         return hw_link_duplex;
2939 }
2940
2941 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2942 {
2943         return !conf_link;
2944 }
2945
2946 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2947                                           uint16_t pam4_link)
2948 {
2949         uint16_t eth_link_speed = 0;
2950
2951         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2952                 return ETH_LINK_SPEED_AUTONEG;
2953
2954         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2955         case ETH_LINK_SPEED_100M:
2956         case ETH_LINK_SPEED_100M_HD:
2957                 /* FALLTHROUGH */
2958                 eth_link_speed =
2959                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2960                 break;
2961         case ETH_LINK_SPEED_1G:
2962                 eth_link_speed =
2963                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2964                 break;
2965         case ETH_LINK_SPEED_2_5G:
2966                 eth_link_speed =
2967                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2968                 break;
2969         case ETH_LINK_SPEED_10G:
2970                 eth_link_speed =
2971                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2972                 break;
2973         case ETH_LINK_SPEED_20G:
2974                 eth_link_speed =
2975                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2976                 break;
2977         case ETH_LINK_SPEED_25G:
2978                 eth_link_speed =
2979                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2980                 break;
2981         case ETH_LINK_SPEED_40G:
2982                 eth_link_speed =
2983                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2984                 break;
2985         case ETH_LINK_SPEED_50G:
2986                 eth_link_speed = pam4_link ?
2987                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2988                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2989                 break;
2990         case ETH_LINK_SPEED_100G:
2991                 eth_link_speed = pam4_link ?
2992                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2993                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2994                 break;
2995         case ETH_LINK_SPEED_200G:
2996                 eth_link_speed =
2997                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
2998                 break;
2999         default:
3000                 PMD_DRV_LOG(ERR,
3001                         "Unsupported link speed %d; default to AUTO\n",
3002                         conf_link_speed);
3003                 break;
3004         }
3005         return eth_link_speed;
3006 }
3007
3008 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3009                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3010                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3011                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3012                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3013
3014 static int bnxt_validate_link_speed(struct bnxt *bp)
3015 {
3016         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3017         uint16_t port_id = bp->eth_dev->data->port_id;
3018         uint32_t link_speed_capa;
3019         uint32_t one_speed;
3020
3021         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3022                 return 0;
3023
3024         link_speed_capa = bnxt_get_speed_capabilities(bp);
3025
3026         if (link_speed & ETH_LINK_SPEED_FIXED) {
3027                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3028
3029                 if (one_speed & (one_speed - 1)) {
3030                         PMD_DRV_LOG(ERR,
3031                                 "Invalid advertised speeds (%u) for port %u\n",
3032                                 link_speed, port_id);
3033                         return -EINVAL;
3034                 }
3035                 if ((one_speed & link_speed_capa) != one_speed) {
3036                         PMD_DRV_LOG(ERR,
3037                                 "Unsupported advertised speed (%u) for port %u\n",
3038                                 link_speed, port_id);
3039                         return -EINVAL;
3040                 }
3041         } else {
3042                 if (!(link_speed & link_speed_capa)) {
3043                         PMD_DRV_LOG(ERR,
3044                                 "Unsupported advertised speeds (%u) for port %u\n",
3045                                 link_speed, port_id);
3046                         return -EINVAL;
3047                 }
3048         }
3049         return 0;
3050 }
3051
3052 static uint16_t
3053 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3054 {
3055         uint16_t ret = 0;
3056
3057         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3058                 if (bp->link_info->support_speeds)
3059                         return bp->link_info->support_speeds;
3060                 link_speed = BNXT_SUPPORTED_SPEEDS;
3061         }
3062
3063         if (link_speed & ETH_LINK_SPEED_100M)
3064                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3065         if (link_speed & ETH_LINK_SPEED_100M_HD)
3066                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3067         if (link_speed & ETH_LINK_SPEED_1G)
3068                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3069         if (link_speed & ETH_LINK_SPEED_2_5G)
3070                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3071         if (link_speed & ETH_LINK_SPEED_10G)
3072                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3073         if (link_speed & ETH_LINK_SPEED_20G)
3074                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3075         if (link_speed & ETH_LINK_SPEED_25G)
3076                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3077         if (link_speed & ETH_LINK_SPEED_40G)
3078                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3079         if (link_speed & ETH_LINK_SPEED_50G)
3080                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3081         if (link_speed & ETH_LINK_SPEED_100G)
3082                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3083         if (link_speed & ETH_LINK_SPEED_200G)
3084                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3085         return ret;
3086 }
3087
3088 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3089 {
3090         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3091
3092         switch (hw_link_speed) {
3093         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3094                 eth_link_speed = ETH_SPEED_NUM_100M;
3095                 break;
3096         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3097                 eth_link_speed = ETH_SPEED_NUM_1G;
3098                 break;
3099         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3100                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3101                 break;
3102         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3103                 eth_link_speed = ETH_SPEED_NUM_10G;
3104                 break;
3105         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3106                 eth_link_speed = ETH_SPEED_NUM_20G;
3107                 break;
3108         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3109                 eth_link_speed = ETH_SPEED_NUM_25G;
3110                 break;
3111         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3112                 eth_link_speed = ETH_SPEED_NUM_40G;
3113                 break;
3114         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3115                 eth_link_speed = ETH_SPEED_NUM_50G;
3116                 break;
3117         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3118                 eth_link_speed = ETH_SPEED_NUM_100G;
3119                 break;
3120         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3121                 eth_link_speed = ETH_SPEED_NUM_200G;
3122                 break;
3123         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3124         default:
3125                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3126                         hw_link_speed);
3127                 break;
3128         }
3129         return eth_link_speed;
3130 }
3131
3132 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3133 {
3134         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3135
3136         switch (hw_link_duplex) {
3137         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3138         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3139                 /* FALLTHROUGH */
3140                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3141                 break;
3142         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3143                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3144                 break;
3145         default:
3146                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3147                         hw_link_duplex);
3148                 break;
3149         }
3150         return eth_link_duplex;
3151 }
3152
3153 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3154 {
3155         int rc = 0;
3156         struct bnxt_link_info *link_info = bp->link_info;
3157
3158         rc = bnxt_hwrm_port_phy_qcaps(bp);
3159         if (rc)
3160                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3161
3162         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3163         if (rc) {
3164                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3165                 goto exit;
3166         }
3167
3168         if (link_info->link_speed)
3169                 link->link_speed =
3170                         bnxt_parse_hw_link_speed(link_info->link_speed);
3171         else
3172                 link->link_speed = ETH_SPEED_NUM_NONE;
3173         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3174         link->link_status = link_info->link_up;
3175         link->link_autoneg = link_info->auto_mode ==
3176                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3177                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3178 exit:
3179         return rc;
3180 }
3181
3182 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3183 {
3184         int rc = 0;
3185         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3186         struct bnxt_link_info link_req;
3187         uint16_t speed, autoneg;
3188
3189         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3190                 return 0;
3191
3192         rc = bnxt_validate_link_speed(bp);
3193         if (rc)
3194                 goto error;
3195
3196         memset(&link_req, 0, sizeof(link_req));
3197         link_req.link_up = link_up;
3198         if (!link_up)
3199                 goto port_phy_cfg;
3200
3201         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3202         if (BNXT_CHIP_P5(bp) &&
3203             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3204                 /* 40G is not supported as part of media auto detect.
3205                  * The speed should be forced and autoneg disabled
3206                  * to configure 40G speed.
3207                  */
3208                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3209                 autoneg = 0;
3210         }
3211
3212         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3213         if (bp->link_info->auto_link_speed == 0 &&
3214             bp->link_info->link_signal_mode &&
3215             bp->link_info->auto_pam4_link_speeds == 0)
3216                 autoneg = 0;
3217
3218         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3219                                           bp->link_info->link_signal_mode);
3220         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3221         /* Autoneg can be done only when the FW allows.
3222          * When user configures fixed speed of 40G and later changes to
3223          * any other speed, auto_link_speed/force_link_speed is still set
3224          * to 40G until link comes up at new speed.
3225          */
3226         if (autoneg == 1 &&
3227             !(!BNXT_CHIP_P5(bp) &&
3228               (bp->link_info->auto_link_speed ||
3229                bp->link_info->force_link_speed))) {
3230                 link_req.phy_flags |=
3231                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3232                 link_req.auto_link_speed_mask =
3233                         bnxt_parse_eth_link_speed_mask(bp,
3234                                                        dev_conf->link_speeds);
3235         } else {
3236                 if (bp->link_info->phy_type ==
3237                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3238                     bp->link_info->phy_type ==
3239                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3240                     bp->link_info->media_type ==
3241                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3242                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3243                         return -EINVAL;
3244                 }
3245
3246                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3247                 /* If user wants a particular speed try that first. */
3248                 if (speed)
3249                         link_req.link_speed = speed;
3250                 else if (bp->link_info->force_pam4_link_speed)
3251                         link_req.link_speed =
3252                                 bp->link_info->force_pam4_link_speed;
3253                 else if (bp->link_info->auto_pam4_link_speeds)
3254                         link_req.link_speed =
3255                                 bp->link_info->auto_pam4_link_speeds;
3256                 else if (bp->link_info->support_pam4_speeds)
3257                         link_req.link_speed =
3258                                 bp->link_info->support_pam4_speeds;
3259                 else if (bp->link_info->force_link_speed)
3260                         link_req.link_speed = bp->link_info->force_link_speed;
3261                 else
3262                         link_req.link_speed = bp->link_info->auto_link_speed;
3263                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3264                  * zero. Use the auto_link_speed.
3265                  */
3266                 if (bp->link_info->auto_link_speed != 0 &&
3267                     bp->link_info->auto_pam4_link_speeds == 0)
3268                         link_req.link_speed = bp->link_info->auto_link_speed;
3269         }
3270         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3271         link_req.auto_pause = bp->link_info->auto_pause;
3272         link_req.force_pause = bp->link_info->force_pause;
3273
3274 port_phy_cfg:
3275         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3276         if (rc) {
3277                 PMD_DRV_LOG(ERR,
3278                         "Set link config failed with rc %d\n", rc);
3279         }
3280
3281 error:
3282         return rc;
3283 }
3284
3285 /* JIRA 22088 */
3286 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3287 {
3288         struct hwrm_func_qcfg_input req = {0};
3289         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3290         uint16_t flags;
3291         int rc = 0;
3292         bp->func_svif = BNXT_SVIF_INVALID;
3293         uint16_t svif_info;
3294
3295         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3296         req.fid = rte_cpu_to_le_16(0xffff);
3297
3298         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3299
3300         HWRM_CHECK_RESULT();
3301
3302         /* Hard Coded.. 0xfff VLAN ID mask */
3303         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3304
3305         svif_info = rte_le_to_cpu_16(resp->svif_info);
3306         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3307                 bp->func_svif = svif_info &
3308                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3309
3310         flags = rte_le_to_cpu_16(resp->flags);
3311         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3312                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3313
3314         if (BNXT_VF(bp) &&
3315             !BNXT_VF_IS_TRUSTED(bp) &&
3316             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3317                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3318                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3319         } else if (BNXT_VF(bp) &&
3320                    BNXT_VF_IS_TRUSTED(bp) &&
3321                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3322                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3323                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3324         }
3325
3326         if (mtu)
3327                 *mtu = rte_le_to_cpu_16(resp->mtu);
3328
3329         switch (resp->port_partition_type) {
3330         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3331         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3332         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3333                 /* FALLTHROUGH */
3334                 bp->flags |= BNXT_FLAG_NPAR_PF;
3335                 break;
3336         default:
3337                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3338                 break;
3339         }
3340
3341         bp->legacy_db_size =
3342                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3343
3344         HWRM_UNLOCK();
3345
3346         return rc;
3347 }
3348
3349 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3350 {
3351         struct hwrm_func_qcfg_input req = {0};
3352         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3353         int rc;
3354
3355         if (!BNXT_VF_IS_TRUSTED(bp))
3356                 return 0;
3357
3358         if (!bp->parent)
3359                 return -EINVAL;
3360
3361         bp->parent->fid = BNXT_PF_FID_INVALID;
3362
3363         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3364
3365         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3366
3367         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3368
3369         HWRM_CHECK_RESULT_SILENT();
3370
3371         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3372         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3373         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3374         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3375
3376         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3377         if (bp->parent->vnic == 0) {
3378                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3379                 /* Use hard-coded values appropriate for current Wh+ fw. */
3380                 if (bp->parent->fid == 2)
3381                         bp->parent->vnic = 0x100;
3382                 else
3383                         bp->parent->vnic = 1;
3384         }
3385
3386         HWRM_UNLOCK();
3387
3388         return 0;
3389 }
3390
3391 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3392                                  uint16_t *vnic_id, uint16_t *svif)
3393 {
3394         struct hwrm_func_qcfg_input req = {0};
3395         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3396         uint16_t svif_info;
3397         int rc = 0;
3398
3399         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3400         req.fid = rte_cpu_to_le_16(fid);
3401
3402         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3403
3404         HWRM_CHECK_RESULT();
3405
3406         if (vnic_id)
3407                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3408
3409         svif_info = rte_le_to_cpu_16(resp->svif_info);
3410         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3411                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3412
3413         HWRM_UNLOCK();
3414
3415         return rc;
3416 }
3417
3418 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3419 {
3420         struct hwrm_port_mac_qcfg_input req = {0};
3421         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3422         uint16_t port_svif_info;
3423         int rc;
3424
3425         bp->port_svif = BNXT_SVIF_INVALID;
3426
3427         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3428                 return 0;
3429
3430         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3431
3432         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3433
3434         HWRM_CHECK_RESULT_SILENT();
3435
3436         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3437         if (port_svif_info &
3438             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3439                 bp->port_svif = port_svif_info &
3440                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3441
3442         HWRM_UNLOCK();
3443
3444         return 0;
3445 }
3446
3447 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3448                                  struct bnxt_pf_resource_info *pf_resc)
3449 {
3450         struct hwrm_func_cfg_input req = {0};
3451         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3452         uint32_t enables;
3453         int rc;
3454
3455         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3456                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3457                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3458                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3459                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3460                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3461                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3462                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3463                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3464
3465         if (BNXT_HAS_RING_GRPS(bp)) {
3466                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3467                 req.num_hw_ring_grps =
3468                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3469         } else if (BNXT_HAS_NQ(bp)) {
3470                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3471                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3472         }
3473
3474         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3475         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3476         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3477         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3478         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3479         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3480         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3481         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3482         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3483         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3484         req.fid = rte_cpu_to_le_16(0xffff);
3485         req.enables = rte_cpu_to_le_32(enables);
3486
3487         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3488
3489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3490
3491         HWRM_CHECK_RESULT();
3492         HWRM_UNLOCK();
3493
3494         return rc;
3495 }
3496
3497 /* min values are the guaranteed resources and max values are subject
3498  * to availability. The strategy for now is to keep both min & max
3499  * values the same.
3500  */
3501 static void
3502 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3503                               struct hwrm_func_vf_resource_cfg_input *req,
3504                               int num_vfs)
3505 {
3506         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3507                                                (num_vfs + 1));
3508         req->min_rsscos_ctx = req->max_rsscos_ctx;
3509         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3510         req->min_stat_ctx = req->max_stat_ctx;
3511         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3512                                                (num_vfs + 1));
3513         req->min_cmpl_rings = req->max_cmpl_rings;
3514         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3515         req->min_tx_rings = req->max_tx_rings;
3516         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3517         req->min_rx_rings = req->max_rx_rings;
3518         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3519         req->min_l2_ctxs = req->max_l2_ctxs;
3520         /* TODO: For now, do not support VMDq/RFS on VFs. */
3521         req->max_vnics = rte_cpu_to_le_16(1);
3522         req->min_vnics = req->max_vnics;
3523         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3524                                                  (num_vfs + 1));
3525         req->min_hw_ring_grps = req->max_hw_ring_grps;
3526         req->flags =
3527          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3528 }
3529
3530 static void
3531 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3532                               struct hwrm_func_cfg_input *req,
3533                               int num_vfs)
3534 {
3535         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3536                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3537                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3538                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3539                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3540                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3541                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3542                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3543                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3544                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3545
3546         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3547                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3548                                     BNXT_NUM_VLANS);
3549         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3550         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3551                                                 (num_vfs + 1));
3552         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3553         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3554                                                (num_vfs + 1));
3555         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3556         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3557         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3558         /* TODO: For now, do not support VMDq/RFS on VFs. */
3559         req->num_vnics = rte_cpu_to_le_16(1);
3560         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3561                                                  (num_vfs + 1));
3562 }
3563
3564 /* Update the port wide resource values based on how many resources
3565  * got allocated to the VF.
3566  */
3567 static int bnxt_update_max_resources(struct bnxt *bp,
3568                                      int vf)
3569 {
3570         struct hwrm_func_qcfg_input req = {0};
3571         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3572         int rc;
3573
3574         /* Get the actual allocated values now */
3575         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3576         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3578         HWRM_CHECK_RESULT();
3579
3580         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3581         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3582         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3583         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3584         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3585         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3586         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3587
3588         HWRM_UNLOCK();
3589
3590         return 0;
3591 }
3592
3593 /* Update the PF resource values based on how many resources
3594  * got allocated to it.
3595  */
3596 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3597 {
3598         struct hwrm_func_qcfg_input req = {0};
3599         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3600         int rc;
3601
3602         /* Get the actual allocated values now */
3603         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3604         req.fid = rte_cpu_to_le_16(0xffff);
3605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3606         HWRM_CHECK_RESULT();
3607
3608         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3609         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3610         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3611         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3612         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3613         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3614         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3615         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3616
3617         HWRM_UNLOCK();
3618
3619         return 0;
3620 }
3621
3622 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3623 {
3624         struct hwrm_func_qcfg_input req = {0};
3625         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3626         int rc;
3627
3628         /* Check for zero MAC address */
3629         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3630         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3632         HWRM_CHECK_RESULT();
3633         rc = rte_le_to_cpu_16(resp->vlan);
3634
3635         HWRM_UNLOCK();
3636
3637         return rc;
3638 }
3639
3640 static int bnxt_query_pf_resources(struct bnxt *bp,
3641                                    struct bnxt_pf_resource_info *pf_resc)
3642 {
3643         struct hwrm_func_qcfg_input req = {0};
3644         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3645         int rc;
3646
3647         /* And copy the allocated numbers into the pf struct */
3648         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3649         req.fid = rte_cpu_to_le_16(0xffff);
3650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651         HWRM_CHECK_RESULT();
3652
3653         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3654         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3655         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3656         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3657         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3658         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3659         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3660         bp->pf->evb_mode = resp->evb_mode;
3661
3662         HWRM_UNLOCK();
3663
3664         return rc;
3665 }
3666
3667 static void
3668 bnxt_calculate_pf_resources(struct bnxt *bp,
3669                             struct bnxt_pf_resource_info *pf_resc,
3670                             int num_vfs)
3671 {
3672         if (!num_vfs) {
3673                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3674                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3675                 pf_resc->num_cp_rings = bp->max_cp_rings;
3676                 pf_resc->num_tx_rings = bp->max_tx_rings;
3677                 pf_resc->num_rx_rings = bp->max_rx_rings;
3678                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3679                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3680
3681                 return;
3682         }
3683
3684         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3685                                    bp->max_rsscos_ctx % (num_vfs + 1);
3686         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3687                                  bp->max_stat_ctx % (num_vfs + 1);
3688         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3689                                 bp->max_cp_rings % (num_vfs + 1);
3690         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3691                                 bp->max_tx_rings % (num_vfs + 1);
3692         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3693                                 bp->max_rx_rings % (num_vfs + 1);
3694         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3695                                bp->max_l2_ctx % (num_vfs + 1);
3696         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3697                                     bp->max_ring_grps % (num_vfs + 1);
3698 }
3699
3700 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3701 {
3702         struct bnxt_pf_resource_info pf_resc = { 0 };
3703         int rc;
3704
3705         if (!BNXT_PF(bp)) {
3706                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3707                 return -EINVAL;
3708         }
3709
3710         rc = bnxt_hwrm_func_qcaps(bp);
3711         if (rc)
3712                 return rc;
3713
3714         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3715
3716         bp->pf->func_cfg_flags &=
3717                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3718                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3719         bp->pf->func_cfg_flags |=
3720                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3721
3722         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3723         if (rc)
3724                 return rc;
3725
3726         rc = bnxt_update_max_resources_pf_only(bp);
3727
3728         return rc;
3729 }
3730
3731 static int
3732 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3733 {
3734         size_t req_buf_sz, sz;
3735         int i, rc;
3736
3737         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3738         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3739                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3740         if (bp->pf->vf_req_buf == NULL) {
3741                 return -ENOMEM;
3742         }
3743
3744         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3745                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3746
3747         for (i = 0; i < num_vfs; i++)
3748                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3749                                              (i * HWRM_MAX_REQ_LEN);
3750
3751         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3752         if (rc)
3753                 rte_free(bp->pf->vf_req_buf);
3754
3755         return rc;
3756 }
3757
3758 static int
3759 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3760 {
3761         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3762         struct hwrm_func_vf_resource_cfg_input req = {0};
3763         int i, rc = 0;
3764
3765         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3766         bp->pf->active_vfs = 0;
3767         for (i = 0; i < num_vfs; i++) {
3768                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3769                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3770                 rc = bnxt_hwrm_send_message(bp,
3771                                             &req,
3772                                             sizeof(req),
3773                                             BNXT_USE_CHIMP_MB);
3774                 if (rc || resp->error_code) {
3775                         PMD_DRV_LOG(ERR,
3776                                 "Failed to initialize VF %d\n", i);
3777                         PMD_DRV_LOG(ERR,
3778                                 "Not all VFs available. (%d, %d)\n",
3779                                 rc, resp->error_code);
3780                         HWRM_UNLOCK();
3781
3782                         /* If the first VF configuration itself fails,
3783                          * unregister the vf_fwd_request buffer.
3784                          */
3785                         if (i == 0)
3786                                 bnxt_hwrm_func_buf_unrgtr(bp);
3787                         break;
3788                 }
3789                 HWRM_UNLOCK();
3790
3791                 /* Update the max resource values based on the resource values
3792                  * allocated to the VF.
3793                  */
3794                 bnxt_update_max_resources(bp, i);
3795                 bp->pf->active_vfs++;
3796                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3797         }
3798
3799         return 0;
3800 }
3801
3802 static int
3803 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3804 {
3805         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3806         struct hwrm_func_cfg_input req = {0};
3807         int i, rc;
3808
3809         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3810
3811         bp->pf->active_vfs = 0;
3812         for (i = 0; i < num_vfs; i++) {
3813                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3814                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3815                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3816                 rc = bnxt_hwrm_send_message(bp,
3817                                             &req,
3818                                             sizeof(req),
3819                                             BNXT_USE_CHIMP_MB);
3820
3821                 /* Clear enable flag for next pass */
3822                 req.enables &= ~rte_cpu_to_le_32(
3823                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3824
3825                 if (rc || resp->error_code) {
3826                         PMD_DRV_LOG(ERR,
3827                                 "Failed to initialize VF %d\n", i);
3828                         PMD_DRV_LOG(ERR,
3829                                 "Not all VFs available. (%d, %d)\n",
3830                                 rc, resp->error_code);
3831                         HWRM_UNLOCK();
3832
3833                         /* If the first VF configuration itself fails,
3834                          * unregister the vf_fwd_request buffer.
3835                          */
3836                         if (i == 0)
3837                                 bnxt_hwrm_func_buf_unrgtr(bp);
3838                         break;
3839                 }
3840
3841                 HWRM_UNLOCK();
3842
3843                 /* Update the max resource values based on the resource values
3844                  * allocated to the VF.
3845                  */
3846                 bnxt_update_max_resources(bp, i);
3847                 bp->pf->active_vfs++;
3848                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3849         }
3850
3851         return 0;
3852 }
3853
3854 static void
3855 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3856 {
3857         if (bp->flags & BNXT_FLAG_NEW_RM)
3858                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3859         else
3860                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3861 }
3862
3863 static void
3864 bnxt_update_pf_resources(struct bnxt *bp,
3865                          struct bnxt_pf_resource_info *pf_resc)
3866 {
3867         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3868         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3869         bp->max_cp_rings = pf_resc->num_cp_rings;
3870         bp->max_tx_rings = pf_resc->num_tx_rings;
3871         bp->max_rx_rings = pf_resc->num_rx_rings;
3872         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3873 }
3874
3875 static int32_t
3876 bnxt_configure_pf_resources(struct bnxt *bp,
3877                             struct bnxt_pf_resource_info *pf_resc)
3878 {
3879         /*
3880          * We're using STD_TX_RING_MODE here which will limit the TX
3881          * rings. This will allow QoS to function properly. Not setting this
3882          * will cause PF rings to break bandwidth settings.
3883          */
3884         bp->pf->func_cfg_flags &=
3885                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3886                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3887         bp->pf->func_cfg_flags |=
3888                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3889         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3890 }
3891
3892 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3893 {
3894         struct bnxt_pf_resource_info pf_resc = { 0 };
3895         int rc;
3896
3897         if (!BNXT_PF(bp)) {
3898                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3899                 return -EINVAL;
3900         }
3901
3902         rc = bnxt_hwrm_func_qcaps(bp);
3903         if (rc)
3904                 return rc;
3905
3906         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3907
3908         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3909         if (rc)
3910                 return rc;
3911
3912         rc = bnxt_query_pf_resources(bp, &pf_resc);
3913         if (rc)
3914                 return rc;
3915
3916         /*
3917          * Now, create and register a buffer to hold forwarded VF requests
3918          */
3919         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3920         if (rc)
3921                 return rc;
3922
3923         bnxt_configure_vf_resources(bp, num_vfs);
3924
3925         bnxt_update_pf_resources(bp, &pf_resc);
3926
3927         return 0;
3928 }
3929
3930 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3931 {
3932         struct hwrm_func_cfg_input req = {0};
3933         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3934         int rc;
3935
3936         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3937
3938         req.fid = rte_cpu_to_le_16(0xffff);
3939         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3940         req.evb_mode = bp->pf->evb_mode;
3941
3942         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3943         HWRM_CHECK_RESULT();
3944         HWRM_UNLOCK();
3945
3946         return rc;
3947 }
3948
3949 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3950                                 uint8_t tunnel_type)
3951 {
3952         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3953         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3954         int rc = 0;
3955
3956         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3957         req.tunnel_type = tunnel_type;
3958         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3959         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3960         HWRM_CHECK_RESULT();
3961
3962         switch (tunnel_type) {
3963         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3964                 bp->vxlan_fw_dst_port_id =
3965                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3966                 bp->vxlan_port = port;
3967                 break;
3968         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3969                 bp->geneve_fw_dst_port_id =
3970                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3971                 bp->geneve_port = port;
3972                 break;
3973         default:
3974                 break;
3975         }
3976
3977         HWRM_UNLOCK();
3978
3979         return rc;
3980 }
3981
3982 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3983                                 uint8_t tunnel_type)
3984 {
3985         struct hwrm_tunnel_dst_port_free_input req = {0};
3986         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3987         int rc = 0;
3988
3989         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3990
3991         req.tunnel_type = tunnel_type;
3992         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3994
3995         HWRM_CHECK_RESULT();
3996         HWRM_UNLOCK();
3997
3998         if (tunnel_type ==
3999             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4000                 bp->vxlan_port = 0;
4001                 bp->vxlan_port_cnt = 0;
4002         }
4003
4004         if (tunnel_type ==
4005             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4006                 bp->geneve_port = 0;
4007                 bp->geneve_port_cnt = 0;
4008         }
4009
4010         return rc;
4011 }
4012
4013 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4014                                         uint32_t flags)
4015 {
4016         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4017         struct hwrm_func_cfg_input req = {0};
4018         int rc;
4019
4020         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4021
4022         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4023         req.flags = rte_cpu_to_le_32(flags);
4024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4025
4026         HWRM_CHECK_RESULT();
4027         HWRM_UNLOCK();
4028
4029         return rc;
4030 }
4031
4032 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4033 {
4034         uint32_t *flag = flagp;
4035
4036         vnic->flags = *flag;
4037 }
4038
4039 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4040 {
4041         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4042 }
4043
4044 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4045 {
4046         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4047         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4048         int rc;
4049
4050         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4051
4052         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4053         req.req_buf_page_size =
4054                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4055         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4056         req.req_buf_page_addr0 =
4057                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4058         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4059                 PMD_DRV_LOG(ERR,
4060                         "unable to map buffer address to physical memory\n");
4061                 HWRM_UNLOCK();
4062                 return -ENOMEM;
4063         }
4064
4065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4066
4067         HWRM_CHECK_RESULT();
4068         HWRM_UNLOCK();
4069
4070         return rc;
4071 }
4072
4073 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4074 {
4075         int rc = 0;
4076         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4077         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4078
4079         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4080                 return 0;
4081
4082         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4083
4084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4085
4086         HWRM_CHECK_RESULT();
4087         HWRM_UNLOCK();
4088
4089         return rc;
4090 }
4091
4092 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4093 {
4094         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4095         struct hwrm_func_cfg_input req = {0};
4096         int rc;
4097
4098         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4099
4100         req.fid = rte_cpu_to_le_16(0xffff);
4101         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4102         req.enables = rte_cpu_to_le_32(
4103                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4104         req.async_event_cr = rte_cpu_to_le_16(
4105                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4107
4108         HWRM_CHECK_RESULT();
4109         HWRM_UNLOCK();
4110
4111         return rc;
4112 }
4113
4114 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4115 {
4116         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4117         struct hwrm_func_vf_cfg_input req = {0};
4118         int rc;
4119
4120         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4121
4122         req.enables = rte_cpu_to_le_32(
4123                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4124         req.async_event_cr = rte_cpu_to_le_16(
4125                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4126         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4127
4128         HWRM_CHECK_RESULT();
4129         HWRM_UNLOCK();
4130
4131         return rc;
4132 }
4133
4134 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4135 {
4136         struct hwrm_func_cfg_input req = {0};
4137         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4138         uint16_t dflt_vlan, fid;
4139         uint32_t func_cfg_flags;
4140         int rc = 0;
4141
4142         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4143
4144         if (is_vf) {
4145                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4146                 fid = bp->pf->vf_info[vf].fid;
4147                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4148         } else {
4149                 fid = rte_cpu_to_le_16(0xffff);
4150                 func_cfg_flags = bp->pf->func_cfg_flags;
4151                 dflt_vlan = bp->vlan;
4152         }
4153
4154         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4155         req.fid = rte_cpu_to_le_16(fid);
4156         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4157         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4158
4159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4160
4161         HWRM_CHECK_RESULT();
4162         HWRM_UNLOCK();
4163
4164         return rc;
4165 }
4166
4167 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4168                         uint16_t max_bw, uint16_t enables)
4169 {
4170         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4171         struct hwrm_func_cfg_input req = {0};
4172         int rc;
4173
4174         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4175
4176         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4177         req.enables |= rte_cpu_to_le_32(enables);
4178         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4179         req.max_bw = rte_cpu_to_le_32(max_bw);
4180         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4181
4182         HWRM_CHECK_RESULT();
4183         HWRM_UNLOCK();
4184
4185         return rc;
4186 }
4187
4188 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4189 {
4190         struct hwrm_func_cfg_input req = {0};
4191         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4192         int rc = 0;
4193
4194         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4195
4196         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4197         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4198         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4199         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4200
4201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4202
4203         HWRM_CHECK_RESULT();
4204         HWRM_UNLOCK();
4205
4206         return rc;
4207 }
4208
4209 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4210 {
4211         int rc;
4212
4213         if (BNXT_PF(bp))
4214                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4215         else
4216                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4217
4218         return rc;
4219 }
4220
4221 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4222                               void *encaped, size_t ec_size)
4223 {
4224         int rc = 0;
4225         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4226         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4227
4228         if (ec_size > sizeof(req.encap_request))
4229                 return -1;
4230
4231         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4232
4233         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4234         memcpy(req.encap_request, encaped, ec_size);
4235
4236         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4237
4238         HWRM_CHECK_RESULT();
4239         HWRM_UNLOCK();
4240
4241         return rc;
4242 }
4243
4244 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4245                                        struct rte_ether_addr *mac)
4246 {
4247         struct hwrm_func_qcfg_input req = {0};
4248         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4249         int rc;
4250
4251         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4252
4253         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4254         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4255
4256         HWRM_CHECK_RESULT();
4257
4258         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4259
4260         HWRM_UNLOCK();
4261
4262         return rc;
4263 }
4264
4265 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4266                             void *encaped, size_t ec_size)
4267 {
4268         int rc = 0;
4269         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4270         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4271
4272         if (ec_size > sizeof(req.encap_request))
4273                 return -1;
4274
4275         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4276
4277         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4278         memcpy(req.encap_request, encaped, ec_size);
4279
4280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4281
4282         HWRM_CHECK_RESULT();
4283         HWRM_UNLOCK();
4284
4285         return rc;
4286 }
4287
4288 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4289                          struct rte_eth_stats *stats, uint8_t rx)
4290 {
4291         int rc = 0;
4292         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4293         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4294
4295         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4296
4297         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4298
4299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4300
4301         HWRM_CHECK_RESULT();
4302
4303         if (rx) {
4304                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4305                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4306                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4307                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4308                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4309                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4310                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4311                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4312         } else {
4313                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4314                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4315                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4316                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4317                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4318                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4319         }
4320
4321         HWRM_UNLOCK();
4322
4323         return rc;
4324 }
4325
4326 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4327 {
4328         struct hwrm_port_qstats_input req = {0};
4329         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4330         struct bnxt_pf_info *pf = bp->pf;
4331         int rc;
4332
4333         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4334
4335         req.port_id = rte_cpu_to_le_16(pf->port_id);
4336         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4337         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4338         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4339
4340         HWRM_CHECK_RESULT();
4341         HWRM_UNLOCK();
4342
4343         return rc;
4344 }
4345
4346 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4347 {
4348         struct hwrm_port_clr_stats_input req = {0};
4349         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4350         struct bnxt_pf_info *pf = bp->pf;
4351         int rc;
4352
4353         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4354         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4355             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4356                 return 0;
4357
4358         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4359
4360         req.port_id = rte_cpu_to_le_16(pf->port_id);
4361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4362
4363         HWRM_CHECK_RESULT();
4364         HWRM_UNLOCK();
4365
4366         return rc;
4367 }
4368
4369 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4370 {
4371         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4372         struct hwrm_port_led_qcaps_input req = {0};
4373         int rc;
4374
4375         if (BNXT_VF(bp))
4376                 return 0;
4377
4378         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4379         req.port_id = bp->pf->port_id;
4380         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4381
4382         HWRM_CHECK_RESULT_SILENT();
4383
4384         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4385                 unsigned int i;
4386
4387                 bp->leds->num_leds = resp->num_leds;
4388                 memcpy(bp->leds, &resp->led0_id,
4389                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4390                 for (i = 0; i < bp->leds->num_leds; i++) {
4391                         struct bnxt_led_info *led = &bp->leds[i];
4392
4393                         uint16_t caps = led->led_state_caps;
4394
4395                         if (!led->led_group_id ||
4396                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4397                                 bp->leds->num_leds = 0;
4398                                 break;
4399                         }
4400                 }
4401         }
4402
4403         HWRM_UNLOCK();
4404
4405         return rc;
4406 }
4407
4408 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4409 {
4410         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4411         struct hwrm_port_led_cfg_input req = {0};
4412         struct bnxt_led_cfg *led_cfg;
4413         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4414         uint16_t duration = 0;
4415         int rc, i;
4416
4417         if (!bp->leds->num_leds || BNXT_VF(bp))
4418                 return -EOPNOTSUPP;
4419
4420         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4421
4422         if (led_on) {
4423                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4424                 duration = rte_cpu_to_le_16(500);
4425         }
4426         req.port_id = bp->pf->port_id;
4427         req.num_leds = bp->leds->num_leds;
4428         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4429         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4430                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4431                 led_cfg->led_id = bp->leds[i].led_id;
4432                 led_cfg->led_state = led_state;
4433                 led_cfg->led_blink_on = duration;
4434                 led_cfg->led_blink_off = duration;
4435                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4436         }
4437
4438         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4439
4440         HWRM_CHECK_RESULT();
4441         HWRM_UNLOCK();
4442
4443         return rc;
4444 }
4445
4446 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4447                                uint32_t *length)
4448 {
4449         int rc;
4450         struct hwrm_nvm_get_dir_info_input req = {0};
4451         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4452
4453         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4454
4455         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4456
4457         HWRM_CHECK_RESULT();
4458
4459         *entries = rte_le_to_cpu_32(resp->entries);
4460         *length = rte_le_to_cpu_32(resp->entry_length);
4461
4462         HWRM_UNLOCK();
4463         return rc;
4464 }
4465
4466 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4467 {
4468         int rc;
4469         uint32_t dir_entries;
4470         uint32_t entry_length;
4471         uint8_t *buf;
4472         size_t buflen;
4473         rte_iova_t dma_handle;
4474         struct hwrm_nvm_get_dir_entries_input req = {0};
4475         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4476
4477         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4478         if (rc != 0)
4479                 return rc;
4480
4481         *data++ = dir_entries;
4482         *data++ = entry_length;
4483         len -= 2;
4484         memset(data, 0xff, len);
4485
4486         buflen = dir_entries * entry_length;
4487         buf = rte_malloc("nvm_dir", buflen, 0);
4488         if (buf == NULL)
4489                 return -ENOMEM;
4490         dma_handle = rte_malloc_virt2iova(buf);
4491         if (dma_handle == RTE_BAD_IOVA) {
4492                 rte_free(buf);
4493                 PMD_DRV_LOG(ERR,
4494                         "unable to map response address to physical memory\n");
4495                 return -ENOMEM;
4496         }
4497         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4498         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4500
4501         if (rc == 0)
4502                 memcpy(data, buf, len > buflen ? buflen : len);
4503
4504         rte_free(buf);
4505         HWRM_CHECK_RESULT();
4506         HWRM_UNLOCK();
4507
4508         return rc;
4509 }
4510
4511 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4512                              uint32_t offset, uint32_t length,
4513                              uint8_t *data)
4514 {
4515         int rc;
4516         uint8_t *buf;
4517         rte_iova_t dma_handle;
4518         struct hwrm_nvm_read_input req = {0};
4519         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4520
4521         buf = rte_malloc("nvm_item", length, 0);
4522         if (!buf)
4523                 return -ENOMEM;
4524
4525         dma_handle = rte_malloc_virt2iova(buf);
4526         if (dma_handle == RTE_BAD_IOVA) {
4527                 rte_free(buf);
4528                 PMD_DRV_LOG(ERR,
4529                         "unable to map response address to physical memory\n");
4530                 return -ENOMEM;
4531         }
4532         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4533         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4534         req.dir_idx = rte_cpu_to_le_16(index);
4535         req.offset = rte_cpu_to_le_32(offset);
4536         req.len = rte_cpu_to_le_32(length);
4537         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4538         if (rc == 0)
4539                 memcpy(data, buf, length);
4540
4541         rte_free(buf);
4542         HWRM_CHECK_RESULT();
4543         HWRM_UNLOCK();
4544
4545         return rc;
4546 }
4547
4548 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4549 {
4550         int rc;
4551         struct hwrm_nvm_erase_dir_entry_input req = {0};
4552         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4553
4554         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4555         req.dir_idx = rte_cpu_to_le_16(index);
4556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4557         HWRM_CHECK_RESULT();
4558         HWRM_UNLOCK();
4559
4560         return rc;
4561 }
4562
4563
4564 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4565                           uint16_t dir_ordinal, uint16_t dir_ext,
4566                           uint16_t dir_attr, const uint8_t *data,
4567                           size_t data_len)
4568 {
4569         int rc;
4570         struct hwrm_nvm_write_input req = {0};
4571         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4572         rte_iova_t dma_handle;
4573         uint8_t *buf;
4574
4575         buf = rte_malloc("nvm_write", data_len, 0);
4576         if (!buf)
4577                 return -ENOMEM;
4578
4579         dma_handle = rte_malloc_virt2iova(buf);
4580         if (dma_handle == RTE_BAD_IOVA) {
4581                 rte_free(buf);
4582                 PMD_DRV_LOG(ERR,
4583                         "unable to map response address to physical memory\n");
4584                 return -ENOMEM;
4585         }
4586         memcpy(buf, data, data_len);
4587
4588         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4589
4590         req.dir_type = rte_cpu_to_le_16(dir_type);
4591         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4592         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4593         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4594         req.dir_data_length = rte_cpu_to_le_32(data_len);
4595         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4596
4597         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4598
4599         rte_free(buf);
4600         HWRM_CHECK_RESULT();
4601         HWRM_UNLOCK();
4602
4603         return rc;
4604 }
4605
4606 static void
4607 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4608 {
4609         uint32_t *count = cbdata;
4610
4611         *count = *count + 1;
4612 }
4613
4614 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4615                                      struct bnxt_vnic_info *vnic __rte_unused)
4616 {
4617         return 0;
4618 }
4619
4620 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4621 {
4622         uint32_t count = 0;
4623
4624         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4625             &count, bnxt_vnic_count_hwrm_stub);
4626
4627         return count;
4628 }
4629
4630 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4631                                         uint16_t *vnic_ids)
4632 {
4633         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4634         struct hwrm_func_vf_vnic_ids_query_output *resp =
4635                                                 bp->hwrm_cmd_resp_addr;
4636         int rc;
4637
4638         /* First query all VNIC ids */
4639         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4640
4641         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4642         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4643         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4644
4645         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4646                 HWRM_UNLOCK();
4647                 PMD_DRV_LOG(ERR,
4648                 "unable to map VNIC ID table address to physical memory\n");
4649                 return -ENOMEM;
4650         }
4651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4652         HWRM_CHECK_RESULT();
4653         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4654
4655         HWRM_UNLOCK();
4656
4657         return rc;
4658 }
4659
4660 /*
4661  * This function queries the VNIC IDs  for a specified VF. It then calls
4662  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4663  * Then it calls the hwrm_cb function to program this new vnic configuration.
4664  */
4665 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4666         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4667         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4668 {
4669         struct bnxt_vnic_info vnic;
4670         int rc = 0;
4671         int i, num_vnic_ids;
4672         uint16_t *vnic_ids;
4673         size_t vnic_id_sz;
4674         size_t sz;
4675
4676         /* First query all VNIC ids */
4677         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4678         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4679                         RTE_CACHE_LINE_SIZE);
4680         if (vnic_ids == NULL)
4681                 return -ENOMEM;
4682
4683         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4684                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4685
4686         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4687
4688         if (num_vnic_ids < 0)
4689                 return num_vnic_ids;
4690
4691         /* Retrieve VNIC, update bd_stall then update */
4692
4693         for (i = 0; i < num_vnic_ids; i++) {
4694                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4695                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4696                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4697                 if (rc)
4698                         break;
4699                 if (vnic.mru <= 4)      /* Indicates unallocated */
4700                         continue;
4701
4702                 vnic_cb(&vnic, cbdata);
4703
4704                 rc = hwrm_cb(bp, &vnic);
4705                 if (rc)
4706                         break;
4707         }
4708
4709         rte_free(vnic_ids);
4710
4711         return rc;
4712 }
4713
4714 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4715                                               bool on)
4716 {
4717         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4718         struct hwrm_func_cfg_input req = {0};
4719         int rc;
4720
4721         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4722
4723         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4724         req.enables |= rte_cpu_to_le_32(
4725                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4726         req.vlan_antispoof_mode = on ?
4727                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4728                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4730
4731         HWRM_CHECK_RESULT();
4732         HWRM_UNLOCK();
4733
4734         return rc;
4735 }
4736
4737 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4738 {
4739         struct bnxt_vnic_info vnic;
4740         uint16_t *vnic_ids;
4741         size_t vnic_id_sz;
4742         int num_vnic_ids, i;
4743         size_t sz;
4744         int rc;
4745
4746         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4747         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4748                         RTE_CACHE_LINE_SIZE);
4749         if (vnic_ids == NULL)
4750                 return -ENOMEM;
4751
4752         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4753                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4754
4755         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4756         if (rc <= 0)
4757                 goto exit;
4758         num_vnic_ids = rc;
4759
4760         /*
4761          * Loop through to find the default VNIC ID.
4762          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4763          * by sending the hwrm_func_qcfg command to the firmware.
4764          */
4765         for (i = 0; i < num_vnic_ids; i++) {
4766                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4767                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4768                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4769                                         bp->pf->first_vf_id + vf);
4770                 if (rc)
4771                         goto exit;
4772                 if (vnic.func_default) {
4773                         rte_free(vnic_ids);
4774                         return vnic.fw_vnic_id;
4775                 }
4776         }
4777         /* Could not find a default VNIC. */
4778         PMD_DRV_LOG(ERR, "No default VNIC\n");
4779 exit:
4780         rte_free(vnic_ids);
4781         return rc;
4782 }
4783
4784 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4785                          uint16_t dst_id,
4786                          struct bnxt_filter_info *filter)
4787 {
4788         int rc = 0;
4789         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4790         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4791         uint32_t enables = 0;
4792
4793         if (filter->fw_em_filter_id != UINT64_MAX)
4794                 bnxt_hwrm_clear_em_filter(bp, filter);
4795
4796         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4797
4798         req.flags = rte_cpu_to_le_32(filter->flags);
4799
4800         enables = filter->enables |
4801               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4802         req.dst_id = rte_cpu_to_le_16(dst_id);
4803
4804         if (filter->ip_addr_type) {
4805                 req.ip_addr_type = filter->ip_addr_type;
4806                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4807         }
4808         if (enables &
4809             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4810                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4811         if (enables &
4812             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4813                 memcpy(req.src_macaddr, filter->src_macaddr,
4814                        RTE_ETHER_ADDR_LEN);
4815         if (enables &
4816             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4817                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4818                        RTE_ETHER_ADDR_LEN);
4819         if (enables &
4820             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4821                 req.ovlan_vid = filter->l2_ovlan;
4822         if (enables &
4823             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4824                 req.ivlan_vid = filter->l2_ivlan;
4825         if (enables &
4826             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4827                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4828         if (enables &
4829             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4830                 req.ip_protocol = filter->ip_protocol;
4831         if (enables &
4832             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4833                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4834         if (enables &
4835             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4836                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4837         if (enables &
4838             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4839                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4840         if (enables &
4841             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4842                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4843         if (enables &
4844             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4845                 req.mirror_vnic_id = filter->mirror_vnic_id;
4846
4847         req.enables = rte_cpu_to_le_32(enables);
4848
4849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4850
4851         HWRM_CHECK_RESULT();
4852
4853         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4854         HWRM_UNLOCK();
4855
4856         return rc;
4857 }
4858
4859 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4860 {
4861         int rc = 0;
4862         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4863         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4864
4865         if (filter->fw_em_filter_id == UINT64_MAX)
4866                 return 0;
4867
4868         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4869
4870         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4871
4872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4873
4874         HWRM_CHECK_RESULT();
4875         HWRM_UNLOCK();
4876
4877         filter->fw_em_filter_id = UINT64_MAX;
4878         filter->fw_l2_filter_id = UINT64_MAX;
4879
4880         return 0;
4881 }
4882
4883 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4884                          uint16_t dst_id,
4885                          struct bnxt_filter_info *filter)
4886 {
4887         int rc = 0;
4888         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4889         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4890                                                 bp->hwrm_cmd_resp_addr;
4891         uint32_t enables = 0;
4892
4893         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4894                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4895
4896         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4897
4898         req.flags = rte_cpu_to_le_32(filter->flags);
4899
4900         enables = filter->enables |
4901               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4902         req.dst_id = rte_cpu_to_le_16(dst_id);
4903
4904         if (filter->ip_addr_type) {
4905                 req.ip_addr_type = filter->ip_addr_type;
4906                 enables |=
4907                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4908         }
4909         if (enables &
4910             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4911                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4912         if (enables &
4913             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4914                 memcpy(req.src_macaddr, filter->src_macaddr,
4915                        RTE_ETHER_ADDR_LEN);
4916         if (enables &
4917             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4918                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4919         if (enables &
4920             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4921                 req.ip_protocol = filter->ip_protocol;
4922         if (enables &
4923             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4924                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4925         if (enables &
4926             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4927                 req.src_ipaddr_mask[0] =
4928                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4929         if (enables &
4930             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4931                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4932         if (enables &
4933             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4934                 req.dst_ipaddr_mask[0] =
4935                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4936         if (enables &
4937             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4938                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4939         if (enables &
4940             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4941                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4942         if (enables &
4943             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4944                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4945         if (enables &
4946             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4947                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4948         if (enables &
4949             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4950                 req.mirror_vnic_id = filter->mirror_vnic_id;
4951
4952         req.enables = rte_cpu_to_le_32(enables);
4953
4954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4955
4956         HWRM_CHECK_RESULT();
4957
4958         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4959         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4960         HWRM_UNLOCK();
4961
4962         return rc;
4963 }
4964
4965 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4966                                 struct bnxt_filter_info *filter)
4967 {
4968         int rc = 0;
4969         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4970         struct hwrm_cfa_ntuple_filter_free_output *resp =
4971                                                 bp->hwrm_cmd_resp_addr;
4972
4973         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4974                 return 0;
4975
4976         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4977
4978         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4979
4980         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4981
4982         HWRM_CHECK_RESULT();
4983         HWRM_UNLOCK();
4984
4985         filter->fw_ntuple_filter_id = UINT64_MAX;
4986
4987         return 0;
4988 }
4989
4990 static int
4991 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4992 {
4993         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4994         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4995         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4996         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4997         uint16_t *ring_tbl = vnic->rss_table;
4998         int nr_ctxs = vnic->num_lb_ctxts;
4999         int max_rings = bp->rx_nr_rings;
5000         int i, j, k, cnt;
5001         int rc = 0;
5002
5003         for (i = 0, k = 0; i < nr_ctxs; i++) {
5004                 struct bnxt_rx_ring_info *rxr;
5005                 struct bnxt_cp_ring_info *cpr;
5006
5007                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5008
5009                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5010                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5011                 req.hash_mode_flags = vnic->hash_mode;
5012
5013                 req.ring_grp_tbl_addr =
5014                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5015                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5016                                      2 * sizeof(*ring_tbl));
5017                 req.hash_key_tbl_addr =
5018                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5019
5020                 req.ring_table_pair_index = i;
5021                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5022
5023                 for (j = 0; j < 64; j++) {
5024                         uint16_t ring_id;
5025
5026                         /* Find next active ring. */
5027                         for (cnt = 0; cnt < max_rings; cnt++) {
5028                                 if (rx_queue_state[k] !=
5029                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5030                                         break;
5031                                 if (++k == max_rings)
5032                                         k = 0;
5033                         }
5034
5035                         /* Return if no rings are active. */
5036                         if (cnt == max_rings) {
5037                                 HWRM_UNLOCK();
5038                                 return 0;
5039                         }
5040
5041                         /* Add rx/cp ring pair to RSS table. */
5042                         rxr = rxqs[k]->rx_ring;
5043                         cpr = rxqs[k]->cp_ring;
5044
5045                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5046                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5047                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5048                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5049
5050                         if (++k == max_rings)
5051                                 k = 0;
5052                 }
5053                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5054                                             BNXT_USE_CHIMP_MB);
5055
5056                 HWRM_CHECK_RESULT();
5057                 HWRM_UNLOCK();
5058         }
5059
5060         return rc;
5061 }
5062
5063 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5064 {
5065         unsigned int rss_idx, fw_idx, i;
5066
5067         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5068                 return 0;
5069
5070         if (!(vnic->rss_table && vnic->hash_type))
5071                 return 0;
5072
5073         if (BNXT_CHIP_P5(bp))
5074                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5075
5076         /*
5077          * Fill the RSS hash & redirection table with
5078          * ring group ids for all VNICs
5079          */
5080         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5081              rss_idx++, fw_idx++) {
5082                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5083                         fw_idx %= bp->rx_cp_nr_rings;
5084                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5085                                 break;
5086                         fw_idx++;
5087                 }
5088
5089                 if (i == bp->rx_cp_nr_rings)
5090                         return 0;
5091
5092                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5093         }
5094
5095         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5096 }
5097
5098 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5099         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5100 {
5101         uint16_t flags;
5102
5103         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5104
5105         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5106         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5107
5108         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5109         req->num_cmpl_dma_aggr_during_int =
5110                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5111
5112         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5113
5114         /* min timer set to 1/2 of interrupt timer */
5115         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5116
5117         /* buf timer set to 1/4 of interrupt timer */
5118         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5119
5120         req->cmpl_aggr_dma_tmr_during_int =
5121                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5122
5123         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5124                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5125         req->flags = rte_cpu_to_le_16(flags);
5126 }
5127
5128 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5129                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5130 {
5131         struct hwrm_ring_aggint_qcaps_input req = {0};
5132         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5133         uint32_t enables;
5134         uint16_t flags;
5135         int rc;
5136
5137         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5138         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5139         HWRM_CHECK_RESULT();
5140
5141         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5142         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5143
5144         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5145                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5146         agg_req->flags = rte_cpu_to_le_16(flags);
5147         enables =
5148          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5149          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5150         agg_req->enables = rte_cpu_to_le_32(enables);
5151
5152         HWRM_UNLOCK();
5153         return rc;
5154 }
5155
5156 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5157                         struct bnxt_coal *coal, uint16_t ring_id)
5158 {
5159         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5160         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5161                                                 bp->hwrm_cmd_resp_addr;
5162         int rc;
5163
5164         /* Set ring coalesce parameters only for 100G NICs */
5165         if (BNXT_CHIP_P5(bp)) {
5166                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5167                         return -1;
5168         } else if (bnxt_stratus_device(bp)) {
5169                 bnxt_hwrm_set_coal_params(coal, &req);
5170         } else {
5171                 return 0;
5172         }
5173
5174         HWRM_PREP(&req,
5175                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5176                   BNXT_USE_CHIMP_MB);
5177         req.ring_id = rte_cpu_to_le_16(ring_id);
5178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5179         HWRM_CHECK_RESULT();
5180         HWRM_UNLOCK();
5181         return 0;
5182 }
5183
5184 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5185 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5186 {
5187         struct hwrm_func_backing_store_qcaps_input req = {0};
5188         struct hwrm_func_backing_store_qcaps_output *resp =
5189                 bp->hwrm_cmd_resp_addr;
5190         struct bnxt_ctx_pg_info *ctx_pg;
5191         struct bnxt_ctx_mem_info *ctx;
5192         int total_alloc_len;
5193         int rc, i, tqm_rings;
5194
5195         if (!BNXT_CHIP_P5(bp) ||
5196             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5197             BNXT_VF(bp) ||
5198             bp->ctx)
5199                 return 0;
5200
5201         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5202         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5203         HWRM_CHECK_RESULT_SILENT();
5204
5205         total_alloc_len = sizeof(*ctx);
5206         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5207                           RTE_CACHE_LINE_SIZE);
5208         if (!ctx) {
5209                 rc = -ENOMEM;
5210                 goto ctx_err;
5211         }
5212
5213         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5214         ctx->qp_min_qp1_entries =
5215                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5216         ctx->qp_max_l2_entries =
5217                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5218         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5219         ctx->srq_max_l2_entries =
5220                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5221         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5222         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5223         ctx->cq_max_l2_entries =
5224                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5225         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5226         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5227         ctx->vnic_max_vnic_entries =
5228                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5229         ctx->vnic_max_ring_table_entries =
5230                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5231         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5232         ctx->stat_max_entries =
5233                 rte_le_to_cpu_32(resp->stat_max_entries);
5234         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5235         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5236         ctx->tqm_min_entries_per_ring =
5237                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5238         ctx->tqm_max_entries_per_ring =
5239                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5240         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5241         if (!ctx->tqm_entries_multiple)
5242                 ctx->tqm_entries_multiple = 1;
5243         ctx->mrav_max_entries =
5244                 rte_le_to_cpu_32(resp->mrav_max_entries);
5245         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5246         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5247         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5248         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5249
5250         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5251                                   RTE_MIN(ctx->tqm_fp_rings_count,
5252                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5253                                   bp->max_q;
5254
5255         /* Check if the ext ring count needs to be counted.
5256          * Ext ring count is available only with new FW so we should not
5257          * look at the field on older FW.
5258          */
5259         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5260             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5261                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5262                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5263                                                   ctx->tqm_fp_rings_count);
5264         }
5265
5266         tqm_rings = ctx->tqm_fp_rings_count + 1;
5267
5268         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5269                             sizeof(*ctx_pg) * tqm_rings,
5270                             RTE_CACHE_LINE_SIZE);
5271         if (!ctx_pg) {
5272                 rc = -ENOMEM;
5273                 goto ctx_err;
5274         }
5275         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5276                 ctx->tqm_mem[i] = ctx_pg;
5277
5278         bp->ctx = ctx;
5279 ctx_err:
5280         HWRM_UNLOCK();
5281         return rc;
5282 }
5283
5284 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5285 {
5286         struct hwrm_func_backing_store_cfg_input req = {0};
5287         struct hwrm_func_backing_store_cfg_output *resp =
5288                 bp->hwrm_cmd_resp_addr;
5289         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5290         struct bnxt_ctx_pg_info *ctx_pg;
5291         uint32_t *num_entries;
5292         uint64_t *pg_dir;
5293         uint8_t *pg_attr;
5294         uint32_t ena;
5295         int i, rc;
5296
5297         if (!ctx)
5298                 return 0;
5299
5300         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5301         req.enables = rte_cpu_to_le_32(enables);
5302
5303         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5304                 ctx_pg = &ctx->qp_mem;
5305                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5306                 req.qp_num_qp1_entries =
5307                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5308                 req.qp_num_l2_entries =
5309                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5310                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5311                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5312                                       &req.qpc_pg_size_qpc_lvl,
5313                                       &req.qpc_page_dir);
5314         }
5315
5316         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5317                 ctx_pg = &ctx->srq_mem;
5318                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5319                 req.srq_num_l2_entries =
5320                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5321                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5322                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5323                                       &req.srq_pg_size_srq_lvl,
5324                                       &req.srq_page_dir);
5325         }
5326
5327         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5328                 ctx_pg = &ctx->cq_mem;
5329                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5330                 req.cq_num_l2_entries =
5331                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5332                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5333                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5334                                       &req.cq_pg_size_cq_lvl,
5335                                       &req.cq_page_dir);
5336         }
5337
5338         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5339                 ctx_pg = &ctx->vnic_mem;
5340                 req.vnic_num_vnic_entries =
5341                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5342                 req.vnic_num_ring_table_entries =
5343                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5344                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5345                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5346                                       &req.vnic_pg_size_vnic_lvl,
5347                                       &req.vnic_page_dir);
5348         }
5349
5350         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5351                 ctx_pg = &ctx->stat_mem;
5352                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5353                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5354                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5355                                       &req.stat_pg_size_stat_lvl,
5356                                       &req.stat_page_dir);
5357         }
5358
5359         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5360         num_entries = &req.tqm_sp_num_entries;
5361         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5362         pg_dir = &req.tqm_sp_page_dir;
5363         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5364         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5365                 if (!(enables & ena))
5366                         continue;
5367
5368                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5369
5370                 ctx_pg = ctx->tqm_mem[i];
5371                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5372                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5373         }
5374
5375         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5376                 /* DPDK does not need to configure MRAV and TIM type.
5377                  * So we are skipping over MRAV and TIM. Skip to configure
5378                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5379                  */
5380                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5381                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5382                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5383                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5384                                       &req.tqm_ring8_page_dir);
5385         }
5386
5387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5388         HWRM_CHECK_RESULT();
5389         HWRM_UNLOCK();
5390
5391         return rc;
5392 }
5393
5394 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5395 {
5396         struct hwrm_port_qstats_ext_input req = {0};
5397         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5398         struct bnxt_pf_info *pf = bp->pf;
5399         int rc;
5400
5401         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5402               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5403                 return 0;
5404
5405         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5406
5407         req.port_id = rte_cpu_to_le_16(pf->port_id);
5408         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5409                 req.tx_stat_host_addr =
5410                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5411                 req.tx_stat_size =
5412                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5413         }
5414         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5415                 req.rx_stat_host_addr =
5416                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5417                 req.rx_stat_size =
5418                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5419         }
5420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5421
5422         if (rc) {
5423                 bp->fw_rx_port_stats_ext_size = 0;
5424                 bp->fw_tx_port_stats_ext_size = 0;
5425         } else {
5426                 bp->fw_rx_port_stats_ext_size =
5427                         rte_le_to_cpu_16(resp->rx_stat_size);
5428                 bp->fw_tx_port_stats_ext_size =
5429                         rte_le_to_cpu_16(resp->tx_stat_size);
5430         }
5431
5432         HWRM_CHECK_RESULT();
5433         HWRM_UNLOCK();
5434
5435         return rc;
5436 }
5437
5438 int
5439 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5440 {
5441         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5442         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5443                 bp->hwrm_cmd_resp_addr;
5444         int rc = 0;
5445
5446         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5447         req.tunnel_type = type;
5448         req.dest_fid = bp->fw_fid;
5449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5450         HWRM_CHECK_RESULT();
5451
5452         HWRM_UNLOCK();
5453
5454         return rc;
5455 }
5456
5457 int
5458 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5459 {
5460         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5461         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5462                 bp->hwrm_cmd_resp_addr;
5463         int rc = 0;
5464
5465         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5466         req.tunnel_type = type;
5467         req.dest_fid = bp->fw_fid;
5468         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5469         HWRM_CHECK_RESULT();
5470
5471         HWRM_UNLOCK();
5472
5473         return rc;
5474 }
5475
5476 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5477 {
5478         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5479         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5480                 bp->hwrm_cmd_resp_addr;
5481         int rc = 0;
5482
5483         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5484         req.src_fid = bp->fw_fid;
5485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5486         HWRM_CHECK_RESULT();
5487
5488         if (type)
5489                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5490
5491         HWRM_UNLOCK();
5492
5493         return rc;
5494 }
5495
5496 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5497                                    uint16_t *dst_fid)
5498 {
5499         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5500         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5501                 bp->hwrm_cmd_resp_addr;
5502         int rc = 0;
5503
5504         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5505         req.src_fid = bp->fw_fid;
5506         req.tunnel_type = tun_type;
5507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5508         HWRM_CHECK_RESULT();
5509
5510         if (dst_fid)
5511                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5512
5513         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5514
5515         HWRM_UNLOCK();
5516
5517         return rc;
5518 }
5519
5520 int bnxt_hwrm_set_mac(struct bnxt *bp)
5521 {
5522         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5523         struct hwrm_func_vf_cfg_input req = {0};
5524         int rc = 0;
5525
5526         if (!BNXT_VF(bp))
5527                 return 0;
5528
5529         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5530
5531         req.enables =
5532                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5533         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5534
5535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5536
5537         HWRM_CHECK_RESULT();
5538
5539         HWRM_UNLOCK();
5540
5541         return rc;
5542 }
5543
5544 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5545 {
5546         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5547         struct hwrm_func_drv_if_change_input req = {0};
5548         uint32_t flags;
5549         int rc;
5550
5551         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5552                 return 0;
5553
5554         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5555          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5556          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5557          */
5558         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5559                 return 0;
5560
5561         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5562
5563         if (up)
5564                 req.flags =
5565                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5566
5567         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5568
5569         HWRM_CHECK_RESULT();
5570         flags = rte_le_to_cpu_32(resp->flags);
5571         HWRM_UNLOCK();
5572
5573         if (!up)
5574                 return 0;
5575
5576         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5577                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5578                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5579         }
5580
5581         return 0;
5582 }
5583
5584 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5585 {
5586         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5587         struct bnxt_error_recovery_info *info = bp->recovery_info;
5588         struct hwrm_error_recovery_qcfg_input req = {0};
5589         uint32_t flags = 0;
5590         unsigned int i;
5591         int rc;
5592
5593         /* Older FW does not have error recovery support */
5594         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5595                 return 0;
5596
5597         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5598
5599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5600
5601         HWRM_CHECK_RESULT();
5602
5603         flags = rte_le_to_cpu_32(resp->flags);
5604         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5605                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5606         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5607                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5608
5609         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5610             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5611                 rc = -EINVAL;
5612                 goto err;
5613         }
5614
5615         /* FW returned values are in units of 100msec */
5616         info->driver_polling_freq =
5617                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5618         info->master_func_wait_period =
5619                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5620         info->normal_func_wait_period =
5621                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5622         info->master_func_wait_period_after_reset =
5623                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5624         info->max_bailout_time_after_reset =
5625                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5626         info->status_regs[BNXT_FW_STATUS_REG] =
5627                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5628         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5629                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5630         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5631                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5632         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5633                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5634         info->reg_array_cnt =
5635                 rte_le_to_cpu_32(resp->reg_array_cnt);
5636
5637         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5638                 rc = -EINVAL;
5639                 goto err;
5640         }
5641
5642         for (i = 0; i < info->reg_array_cnt; i++) {
5643                 info->reset_reg[i] =
5644                         rte_le_to_cpu_32(resp->reset_reg[i]);
5645                 info->reset_reg_val[i] =
5646                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5647                 info->delay_after_reset[i] =
5648                         resp->delay_after_reset[i];
5649         }
5650 err:
5651         HWRM_UNLOCK();
5652
5653         /* Map the FW status registers */
5654         if (!rc)
5655                 rc = bnxt_map_fw_health_status_regs(bp);
5656
5657         if (rc) {
5658                 rte_free(bp->recovery_info);
5659                 bp->recovery_info = NULL;
5660         }
5661         return rc;
5662 }
5663
5664 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5665 {
5666         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5667         struct hwrm_fw_reset_input req = {0};
5668         int rc;
5669
5670         if (!BNXT_PF(bp))
5671                 return -EOPNOTSUPP;
5672
5673         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5674
5675         req.embedded_proc_type =
5676                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5677         req.selfrst_status =
5678                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5679         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5680
5681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5682                                     BNXT_USE_KONG(bp));
5683
5684         HWRM_CHECK_RESULT();
5685         HWRM_UNLOCK();
5686
5687         return rc;
5688 }
5689
5690 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5691 {
5692         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5693         struct hwrm_port_ts_query_input req = {0};
5694         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5695         uint32_t flags = 0;
5696         int rc;
5697
5698         if (!ptp)
5699                 return 0;
5700
5701         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5702
5703         switch (path) {
5704         case BNXT_PTP_FLAGS_PATH_TX:
5705                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5706                 break;
5707         case BNXT_PTP_FLAGS_PATH_RX:
5708                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5709                 break;
5710         case BNXT_PTP_FLAGS_CURRENT_TIME:
5711                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5712                 break;
5713         }
5714
5715         req.flags = rte_cpu_to_le_32(flags);
5716         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5717
5718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5719
5720         HWRM_CHECK_RESULT();
5721
5722         if (timestamp) {
5723                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5724                 *timestamp |=
5725                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5726         }
5727         HWRM_UNLOCK();
5728
5729         return rc;
5730 }
5731
5732 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5733 {
5734         int rc = 0;
5735
5736         struct hwrm_cfa_counter_qcaps_input req = {0};
5737         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5738
5739         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5740                 PMD_DRV_LOG(DEBUG,
5741                             "Not a PF or trusted VF. Command not supported\n");
5742                 return 0;
5743         }
5744
5745         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5746         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5747         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5748
5749         HWRM_CHECK_RESULT();
5750         if (max_fc)
5751                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5752         HWRM_UNLOCK();
5753
5754         return 0;
5755 }
5756
5757 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5758 {
5759         int rc = 0;
5760         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5761         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5762
5763         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5764                 PMD_DRV_LOG(DEBUG,
5765                             "Not a PF or trusted VF. Command not supported\n");
5766                 return 0;
5767         }
5768
5769         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5770
5771         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5772         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5773         req.page_dir = rte_cpu_to_le_64(dma_addr);
5774
5775         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5776
5777         HWRM_CHECK_RESULT();
5778         if (ctx_id) {
5779                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5780                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5781         }
5782         HWRM_UNLOCK();
5783
5784         return 0;
5785 }
5786
5787 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5788 {
5789         int rc = 0;
5790         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5791         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5792
5793         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5794                 PMD_DRV_LOG(DEBUG,
5795                             "Not a PF or trusted VF. Command not supported\n");
5796                 return 0;
5797         }
5798
5799         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5800
5801         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5802
5803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5804
5805         HWRM_CHECK_RESULT();
5806         HWRM_UNLOCK();
5807
5808         return rc;
5809 }
5810
5811 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5812                               uint16_t cntr, uint16_t ctx_id,
5813                               uint32_t num_entries, bool enable)
5814 {
5815         struct hwrm_cfa_counter_cfg_input req = {0};
5816         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5817         uint16_t flags = 0;
5818         int rc;
5819
5820         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5821                 PMD_DRV_LOG(DEBUG,
5822                             "Not a PF or trusted VF. Command not supported\n");
5823                 return 0;
5824         }
5825
5826         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5827
5828         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5829         req.counter_type = rte_cpu_to_le_16(cntr);
5830         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5831                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5832         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5833         if (dir == BNXT_DIR_RX)
5834                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5835         else if (dir == BNXT_DIR_TX)
5836                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5837         req.flags = rte_cpu_to_le_16(flags);
5838         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5839         req.num_entries = rte_cpu_to_le_32(num_entries);
5840
5841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5842         HWRM_CHECK_RESULT();
5843         HWRM_UNLOCK();
5844
5845         return 0;
5846 }
5847
5848 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5849                                  enum bnxt_flow_dir dir,
5850                                  uint16_t cntr,
5851                                  uint16_t num_entries)
5852 {
5853         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5854         struct hwrm_cfa_counter_qstats_input req = {0};
5855         uint16_t flow_ctx_id = 0;
5856         uint16_t flags = 0;
5857         int rc = 0;
5858
5859         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5860                 PMD_DRV_LOG(DEBUG,
5861                             "Not a PF or trusted VF. Command not supported\n");
5862                 return 0;
5863         }
5864
5865         if (dir == BNXT_DIR_RX) {
5866                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5867                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5868         } else if (dir == BNXT_DIR_TX) {
5869                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5870                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5871         }
5872
5873         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5874         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5875         req.counter_type = rte_cpu_to_le_16(cntr);
5876         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5877         req.num_entries = rte_cpu_to_le_16(num_entries);
5878         req.flags = rte_cpu_to_le_16(flags);
5879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5880
5881         HWRM_CHECK_RESULT();
5882         HWRM_UNLOCK();
5883
5884         return 0;
5885 }
5886
5887 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5888                                 uint16_t *first_vf_id)
5889 {
5890         int rc = 0;
5891         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5892         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5893
5894         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5895
5896         req.fid = rte_cpu_to_le_16(fid);
5897
5898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5899
5900         HWRM_CHECK_RESULT();
5901
5902         if (first_vf_id)
5903                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5904
5905         HWRM_UNLOCK();
5906
5907         return rc;
5908 }
5909
5910 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5911 {
5912         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5913         struct hwrm_cfa_pair_alloc_input req = {0};
5914         int rc;
5915
5916         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5917                 PMD_DRV_LOG(DEBUG,
5918                             "Not a PF or trusted VF. Command not supported\n");
5919                 return 0;
5920         }
5921
5922         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5923         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5924         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5925                  bp->eth_dev->data->name, rep_bp->vf_id);
5926
5927         req.pf_b_id = rep_bp->parent_pf_idx;
5928         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5929                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5930         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5931         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5932
5933         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5934                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5935         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5936                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5937         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5938                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5939         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5940                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5941
5942         req.q_ab = rep_bp->rep_q_r2f;
5943         req.q_ba = rep_bp->rep_q_f2r;
5944         req.fc_ab = rep_bp->rep_fc_r2f;
5945         req.fc_ba = rep_bp->rep_fc_f2r;
5946
5947         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5948         HWRM_CHECK_RESULT();
5949
5950         HWRM_UNLOCK();
5951         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5952                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5953         return rc;
5954 }
5955
5956 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5957 {
5958         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5959         struct hwrm_cfa_pair_free_input req = {0};
5960         int rc;
5961
5962         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5963                 PMD_DRV_LOG(DEBUG,
5964                             "Not a PF or trusted VF. Command not supported\n");
5965                 return 0;
5966         }
5967
5968         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5969         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5970                  bp->eth_dev->data->name, rep_bp->vf_id);
5971         req.pf_b_id = rep_bp->parent_pf_idx;
5972         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5973         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5974                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5976         HWRM_CHECK_RESULT();
5977         HWRM_UNLOCK();
5978         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5979                     rep_bp->vf_id);
5980         return rc;
5981 }
5982
5983 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5984 {
5985         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5986                                         bp->hwrm_cmd_resp_addr;
5987         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5988         uint32_t flags = 0;
5989         int rc = 0;
5990
5991         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5992                 return 0;
5993
5994         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5995                 PMD_DRV_LOG(DEBUG,
5996                             "Not a PF or trusted VF. Command not supported\n");
5997                 return 0;
5998         }
5999
6000         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6002
6003         HWRM_CHECK_RESULT();
6004         flags = rte_le_to_cpu_32(resp->flags);
6005         HWRM_UNLOCK();
6006
6007         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6008                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6009         else
6010                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6011
6012         return rc;
6013 }
6014
6015 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6016                             uint32_t echo_req_data2)
6017 {
6018         struct hwrm_func_echo_response_input req = {0};
6019         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6020         int rc;
6021
6022         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6023         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6024         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6025
6026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6027
6028         HWRM_CHECK_RESULT();
6029         HWRM_UNLOCK();
6030
6031         return rc;
6032 }
6033
6034 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6035 {
6036         struct hwrm_ver_get_input req = {.req_type = 0 };
6037         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6038         int rc = 0;
6039
6040         bp->max_req_len = HWRM_MAX_REQ_LEN;
6041         bp->max_resp_len = BNXT_PAGE_SIZE;
6042         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6043
6044         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6045         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6046         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6047         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6048
6049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6050
6051         HWRM_CHECK_RESULT_SILENT();
6052
6053         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6054                 rc = -EAGAIN;
6055
6056         HWRM_UNLOCK();
6057
6058         return rc;
6059 }