drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         if (bp->hwrm_cmd_resp_addr == NULL) { \
 188                 rte_spinlock_unlock(&bp->hwrm_lock); \
 189                 return -EACCES; \
 190         } \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr =
 313                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                              struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct bnxt_vnic_info *vnic = NULL;
 371         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 372         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 373
 374         if (filter->fw_l2_filter_id == UINT64_MAX)
 375                 return 0;
 376
 377         if (filter->matching_l2_fltr_ptr)
 378                 l2_filter = filter->matching_l2_fltr_ptr;
 379
 380         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 381                     filter, l2_filter, l2_filter->l2_ref_cnt);
 382
 383         if (l2_filter->l2_ref_cnt == 0)
 384                 return 0;
 385
 386         if (l2_filter->l2_ref_cnt > 0)
 387                 l2_filter->l2_ref_cnt--;
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 return 0;
 391
 392         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 393
 394         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 395
 396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 397
 398         HWRM_CHECK_RESULT();
 399         HWRM_UNLOCK();
 400
 401         filter->fw_l2_filter_id = UINT64_MAX;
 402         if (l2_filter->l2_ref_cnt == 0) {
 403                 vnic = l2_filter->vnic;
 404                 if (vnic) {
 405                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 406                                       bnxt_filter_info, next);
 407                         bnxt_free_filter(bp, l2_filter);
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 415                          uint16_t dst_id,
 416                          struct bnxt_filter_info *filter)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 420         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 421         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 422         const struct rte_eth_vmdq_rx_conf *conf =
 423                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 424         uint32_t enables = 0;
 425         uint16_t j = dst_id - 1;
 426
 427         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 428         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 429             conf->pool_map[j].pools & (1UL << j)) {
 430                 PMD_DRV_LOG(DEBUG,
 431                         "Add vlan %u to vmdq pool %u\n",
 432                         conf->pool_map[j].vlan_id, j);
 433
 434                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 435                 filter->enables |=
 436                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 437                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 438         }
 439
 440         if (filter->fw_l2_filter_id != UINT64_MAX)
 441                 bnxt_hwrm_clear_l2_filter(bp, filter);
 442
 443         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 444
 445         req.flags = rte_cpu_to_le_32(filter->flags);
 446
 447         enables = filter->enables |
 448               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 449         req.dst_id = rte_cpu_to_le_16(dst_id);
 450
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 453                 memcpy(req.l2_addr, filter->l2_addr,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 457                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 458                        RTE_ETHER_ADDR_LEN);
 459         if (enables &
 460             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 461                 req.l2_ovlan = filter->l2_ovlan;
 462         if (enables &
 463             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 464                 req.l2_ivlan = filter->l2_ivlan;
 465         if (enables &
 466             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 467                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 468         if (enables &
 469             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 470                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 471         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 472                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 473         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 474                 req.src_type = filter->src_type;
 475         if (filter->pri_hint) {
 476                 req.pri_hint = filter->pri_hint;
 477                 req.l2_filter_id_hint =
 478                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 479         }
 480
 481         req.enables = rte_cpu_to_le_32(enables);
 482
 483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 484
 485         HWRM_CHECK_RESULT();
 486
 487         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 488         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 489         HWRM_UNLOCK();
 490
 491         filter->l2_ref_cnt++;
 492
 493         return rc;
 494 }
 495
 496 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 497 {
 498         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 499         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 500         uint32_t flags = 0;
 501         int rc;
 502
 503         if (!ptp)
 504                 return 0;
 505
 506         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 507
 508         if (ptp->rx_filter)
 509                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 510         else
 511                 flags |=
 512                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 513         if (ptp->tx_tstamp_en)
 514                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 515         else
 516                 flags |=
 517                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 518         req.flags = rte_cpu_to_le_32(flags);
 519         req.enables = rte_cpu_to_le_32
 520                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 521         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 522
 523         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 530 {
 531         int rc = 0;
 532         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 533         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 534         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 535
 536         if (ptp)
 537                 return 0;
 538
 539         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 540
 541         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 542
 543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 544
 545         HWRM_CHECK_RESULT();
 546
 547         if (!BNXT_CHIP_THOR(bp) &&
 548             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 549                 return 0;
 550
 551         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 552                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 553
 554         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 555         if (!ptp)
 556                 return -ENOMEM;
 557
 558         if (!BNXT_CHIP_THOR(bp)) {
 559                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 560                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 561                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 562                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 563                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 564                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 565                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 566                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 567                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 568                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 569                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 570                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 571                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 572                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 573                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 574                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 575                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 576                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 577         }
 578
 579         ptp->bp = bp;
 580         bp->ptp_cfg = ptp;
 581
 582         return 0;
 583 }
 584
 585 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 586 {
 587         int rc = 0;
 588         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 589         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 590         uint16_t new_max_vfs;
 591         uint32_t flags;
 592         int i;
 593
 594         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 595
 596         req.fid = rte_cpu_to_le_16(0xffff);
 597
 598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 599
 600         HWRM_CHECK_RESULT();
 601
 602         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 603         flags = rte_le_to_cpu_32(resp->flags);
 604         if (BNXT_PF(bp)) {
 605                 bp->pf.port_id = resp->port_id;
 606                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 607                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 608                 new_max_vfs = bp->pdev->max_vfs;
 609                 if (new_max_vfs != bp->pf.max_vfs) {
 610                         if (bp->pf.vf_info)
 611                                 rte_free(bp->pf.vf_info);
 612                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 613                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 614                         bp->pf.max_vfs = new_max_vfs;
 615                         for (i = 0; i < new_max_vfs; i++) {
 616                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 617                                 bp->pf.vf_info[i].vlan_table =
 618                                         rte_zmalloc("VF VLAN table",
 619                                                     getpagesize(),
 620                                                     getpagesize());
 621                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 622                                         PMD_DRV_LOG(ERR,
 623                                         "Fail to alloc VLAN table for VF %d\n",
 624                                         i);
 625                                 else
 626                                         rte_mem_lock_page(
 627                                                 bp->pf.vf_info[i].vlan_table);
 628                                 bp->pf.vf_info[i].vlan_as_table =
 629                                         rte_zmalloc("VF VLAN AS table",
 630                                                     getpagesize(),
 631                                                     getpagesize());
 632                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 633                                         PMD_DRV_LOG(ERR,
 634                                         "Alloc VLAN AS table for VF %d fail\n",
 635                                         i);
 636                                 else
 637                                         rte_mem_lock_page(
 638                                                bp->pf.vf_info[i].vlan_as_table);
 639                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 640                         }
 641                 }
 642         }
 643
 644         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 645         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 646         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 647         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 648         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 649         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 650         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 651         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 652         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 653         if (!BNXT_CHIP_THOR(bp))
 654                 bp->max_l2_ctx += bp->max_rx_em_flows;
 655         /* TODO: For now, do not support VMDq/RFS on VFs. */
 656         if (BNXT_PF(bp)) {
 657                 if (bp->pf.max_vfs)
 658                         bp->max_vnics = 1;
 659                 else
 660                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 661         } else {
 662                 bp->max_vnics = 1;
 663         }
 664         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 665         if (BNXT_PF(bp)) {
 666                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 667                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 668                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 669                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 670                         HWRM_UNLOCK();
 671                         bnxt_hwrm_ptp_qcfg(bp);
 672                 }
 673         }
 674
 675         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 676                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 677
 678         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 679                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 680                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 681         }
 682
 683         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 684                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 685
 686         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 687                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 688
 689         HWRM_UNLOCK();
 690
 691         return rc;
 692 }
 693
 694 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 695 {
 696         int rc;
 697
 698         rc = __bnxt_hwrm_func_qcaps(bp);
 699         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 700                 rc = bnxt_alloc_ctx_mem(bp);
 701                 if (rc)
 702                         return rc;
 703
 704                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 705                 if (!rc)
 706                         bp->flags |= BNXT_FLAG_NEW_RM;
 707         }
 708
 709         /* On older FW,
 710          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 711          * But the error can be ignored. Return success.
 712          */
 713
 714         return 0;
 715 }
 716
 717 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 718 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 719 {
 720         int rc = 0;
 721         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 722         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 723
 724         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 725
 726         req.target_id = rte_cpu_to_le_16(0xffff);
 727
 728         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 729
 730         HWRM_CHECK_RESULT();
 731
 732         if (rte_le_to_cpu_32(resp->flags) &
 733             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 734                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 735                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 736         }
 737
 738         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 739
 740         HWRM_UNLOCK();
 741
 742         return rc;
 743 }
 744
 745 int bnxt_hwrm_func_reset(struct bnxt *bp)
 746 {
 747         int rc = 0;
 748         struct hwrm_func_reset_input req = {.req_type = 0 };
 749         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 750
 751         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 752
 753         req.enables = rte_cpu_to_le_32(0);
 754
 755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 756
 757         HWRM_CHECK_RESULT();
 758         HWRM_UNLOCK();
 759
 760         return rc;
 761 }
 762
 763 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 764 {
 765         int rc;
 766         uint32_t flags = 0;
 767         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 768         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 769
 770         if (bp->flags & BNXT_FLAG_REGISTERED)
 771                 return 0;
 772
 773         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 774                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 775         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 776                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 777
 778         /* PFs and trusted VFs should indicate the support of the
 779          * Master capability on non Stingray platform
 780          */
 781         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 782                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 783
 784         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 785         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 786                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 787         req.ver_maj = RTE_VER_YEAR;
 788         req.ver_min = RTE_VER_MONTH;
 789         req.ver_upd = RTE_VER_MINOR;
 790
 791         if (BNXT_PF(bp)) {
 792                 req.enables |= rte_cpu_to_le_32(
 793                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 794                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 795                        RTE_MIN(sizeof(req.vf_req_fwd),
 796                                sizeof(bp->pf.vf_req_fwd)));
 797
 798                 /*
 799                  * PF can sniff HWRM API issued by VF. This can be set up by
 800                  * linux driver and inherited by the DPDK PF driver. Clear
 801                  * this HWRM sniffer list in FW because DPDK PF driver does
 802                  * not support this.
 803                  */
 804                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 805         }
 806
 807         req.flags = rte_cpu_to_le_32(flags);
 808
 809         req.async_event_fwd[0] |=
 810                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 811                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 812                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 813                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 814                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 815         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 816                 req.async_event_fwd[0] |=
 817                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 818         req.async_event_fwd[1] |=
 819                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 820                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 821         if (BNXT_PF(bp))
 822                 req.async_event_fwd[1] |=
 823                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 824
 825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 826
 827         HWRM_CHECK_RESULT();
 828
 829         flags = rte_le_to_cpu_32(resp->flags);
 830         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 831                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 832
 833         HWRM_UNLOCK();
 834
 835         bp->flags |= BNXT_FLAG_REGISTERED;
 836
 837         return rc;
 838 }
 839
 840 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 841 {
 842         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 843                 return 0;
 844
 845         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 846 }
 847
 848 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 849 {
 850         int rc;
 851         uint32_t flags = 0;
 852         uint32_t enables;
 853         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 854         struct hwrm_func_vf_cfg_input req = {0};
 855
 856         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 857
 858         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 859                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 860                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 861                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 862                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 863
 864         if (BNXT_HAS_RING_GRPS(bp)) {
 865                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 866                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 867         }
 868
 869         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 870         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 871                                             AGG_RING_MULTIPLIER);
 872         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 873         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 874                                               bp->tx_nr_rings +
 875                                               BNXT_NUM_ASYNC_CPR(bp));
 876         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 877         if (bp->vf_resv_strategy ==
 878             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 879                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 880                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 881                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 882                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 883                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 884                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 885         } else if (bp->vf_resv_strategy ==
 886                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 887                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 888                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 889         }
 890
 891         if (test)
 892                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 893                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 894                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 895                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 896                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 897                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 898
 899         if (test && BNXT_HAS_RING_GRPS(bp))
 900                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 901
 902         req.flags = rte_cpu_to_le_32(flags);
 903         req.enables |= rte_cpu_to_le_32(enables);
 904
 905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 906
 907         if (test)
 908                 HWRM_CHECK_RESULT_SILENT();
 909         else
 910                 HWRM_CHECK_RESULT();
 911
 912         HWRM_UNLOCK();
 913         return rc;
 914 }
 915
 916 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 917 {
 918         int rc;
 919         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 920         struct hwrm_func_resource_qcaps_input req = {0};
 921
 922         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 923         req.fid = rte_cpu_to_le_16(0xffff);
 924
 925         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 926
 927         HWRM_CHECK_RESULT_SILENT();
 928
 929         if (BNXT_VF(bp)) {
 930                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 931                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 932                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 933                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 934                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 935                 /* func_resource_qcaps does not return max_rx_em_flows.
 936                  * So use the value provided by func_qcaps.
 937                  */
 938                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 939                 if (!BNXT_CHIP_THOR(bp))
 940                         bp->max_l2_ctx += bp->max_rx_em_flows;
 941                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 942                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 943         }
 944         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 945         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 946         if (bp->vf_resv_strategy >
 947             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 948                 bp->vf_resv_strategy =
 949                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 950
 951         HWRM_UNLOCK();
 952         return rc;
 953 }
 954
 955 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
 956 {
 957         int rc = 0;
 958         struct hwrm_ver_get_input req = {.req_type = 0 };
 959         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 960         uint32_t fw_version;
 961         uint16_t max_resp_len;
 962         char type[RTE_MEMZONE_NAMESIZE];
 963         uint32_t dev_caps_cfg;
 964
 965         bp->max_req_len = HWRM_MAX_REQ_LEN;
 966         bp->hwrm_cmd_timeout = timeout;
 967         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 968
 969         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 970         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 971         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 972
 973         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 974
 975         if (bp->flags & BNXT_FLAG_FW_RESET)
 976                 HWRM_CHECK_RESULT_SILENT();
 977         else
 978                 HWRM_CHECK_RESULT();
 979
 980         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 981                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 982                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 983                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 984         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 985                      (resp->hwrm_fw_min_8b << 16) |
 986                      (resp->hwrm_fw_bld_8b << 8) |
 987                      resp->hwrm_fw_rsvd_8b;
 988         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 989                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 990
 991         fw_version = resp->hwrm_intf_maj_8b << 16;
 992         fw_version |= resp->hwrm_intf_min_8b << 8;
 993         fw_version |= resp->hwrm_intf_upd_8b;
 994         bp->hwrm_spec_code = fw_version;
 995
 996         /* def_req_timeout value is in milliseconds */
 997         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 998         /* convert timeout to usec */
 999         bp->hwrm_cmd_timeout *= 1000;
1000         if (!bp->hwrm_cmd_timeout)
1001                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1002
1003         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1004                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1005                 rc = -EINVAL;
1006                 goto error;
1007         }
1008
1009         if (bp->max_req_len > resp->max_req_win_len) {
1010                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1011                 rc = -EINVAL;
1012         }
1013         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1014         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1015         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1016                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1017
1018         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1019         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1020
1021         if (bp->max_resp_len != max_resp_len) {
1022                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1023                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1024                         bp->pdev->addr.devid, bp->pdev->addr.function);
1025
1026                 rte_free(bp->hwrm_cmd_resp_addr);
1027
1028                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1029                 if (bp->hwrm_cmd_resp_addr == NULL) {
1030                         rc = -ENOMEM;
1031                         goto error;
1032                 }
1033                 bp->hwrm_cmd_resp_dma_addr =
1034                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1035                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1036                         PMD_DRV_LOG(ERR,
1037                         "Unable to map response buffer to physical memory.\n");
1038                         rc = -ENOMEM;
1039                         goto error;
1040                 }
1041                 bp->max_resp_len = max_resp_len;
1042         }
1043
1044         if ((dev_caps_cfg &
1045                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1046             (dev_caps_cfg &
1047              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1048                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1049                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1050         }
1051
1052         if (((dev_caps_cfg &
1053               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1054              (dev_caps_cfg &
1055               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1056             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1057                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1058                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1059                         bp->pdev->addr.devid, bp->pdev->addr.function);
1060
1061                 rte_free(bp->hwrm_short_cmd_req_addr);
1062
1063                 bp->hwrm_short_cmd_req_addr =
1064                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1065                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1066                         rc = -ENOMEM;
1067                         goto error;
1068                 }
1069                 bp->hwrm_short_cmd_req_dma_addr =
1070                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1071                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1072                         rte_free(bp->hwrm_short_cmd_req_addr);
1073                         PMD_DRV_LOG(ERR,
1074                                 "Unable to map buffer to physical memory.\n");
1075                         rc = -ENOMEM;
1076                         goto error;
1077                 }
1078         }
1079         if (dev_caps_cfg &
1080             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1081                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1082                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1083         }
1084         if (dev_caps_cfg &
1085             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1086                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1087         if (dev_caps_cfg &
1088             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1089                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1090                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1091         }
1092
1093 error:
1094         HWRM_UNLOCK();
1095         return rc;
1096 }
1097
1098 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1099 {
1100         int rc;
1101         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1102         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1103
1104         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1105                 return 0;
1106
1107         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1108         req.flags = flags;
1109
1110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1111
1112         HWRM_CHECK_RESULT();
1113         HWRM_UNLOCK();
1114
1115         return rc;
1116 }
1117
1118 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1119 {
1120         int rc = 0;
1121         struct hwrm_port_phy_cfg_input req = {0};
1122         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1123         uint32_t enables = 0;
1124
1125         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1126
1127         if (conf->link_up) {
1128                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1129                 if (bp->link_info.auto_mode && conf->link_speed) {
1130                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1131                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1132                 }
1133
1134                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1135                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1136                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1137                 /*
1138                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1139                  * any auto mode, even "none".
1140                  */
1141                 if (!conf->link_speed) {
1142                         /* No speeds specified. Enable AutoNeg - all speeds */
1143                         req.auto_mode =
1144                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1145                 }
1146                 /* AutoNeg - Advertise speeds specified. */
1147                 if (conf->auto_link_speed_mask &&
1148                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1149                         req.auto_mode =
1150                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1151                         req.auto_link_speed_mask =
1152                                 conf->auto_link_speed_mask;
1153                         enables |=
1154                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1155                 }
1156
1157                 req.auto_duplex = conf->duplex;
1158                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1159                 req.auto_pause = conf->auto_pause;
1160                 req.force_pause = conf->force_pause;
1161                 /* Set force_pause if there is no auto or if there is a force */
1162                 if (req.auto_pause && !req.force_pause)
1163                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1164                 else
1165                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1166
1167                 req.enables = rte_cpu_to_le_32(enables);
1168         } else {
1169                 req.flags =
1170                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1171                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1172         }
1173
1174         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1175
1176         HWRM_CHECK_RESULT();
1177         HWRM_UNLOCK();
1178
1179         return rc;
1180 }
1181
1182 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1183                                    struct bnxt_link_info *link_info)
1184 {
1185         int rc = 0;
1186         struct hwrm_port_phy_qcfg_input req = {0};
1187         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1188
1189         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1190
1191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1192
1193         HWRM_CHECK_RESULT();
1194
1195         link_info->phy_link_status = resp->link;
1196         link_info->link_up =
1197                 (link_info->phy_link_status ==
1198                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1199         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1200         link_info->duplex = resp->duplex_cfg;
1201         link_info->pause = resp->pause;
1202         link_info->auto_pause = resp->auto_pause;
1203         link_info->force_pause = resp->force_pause;
1204         link_info->auto_mode = resp->auto_mode;
1205         link_info->phy_type = resp->phy_type;
1206         link_info->media_type = resp->media_type;
1207
1208         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1209         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1210         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1211         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1212         link_info->phy_ver[0] = resp->phy_maj;
1213         link_info->phy_ver[1] = resp->phy_min;
1214         link_info->phy_ver[2] = resp->phy_bld;
1215
1216         HWRM_UNLOCK();
1217
1218         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1219         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1220         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1221         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1222         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1223                     link_info->auto_link_speed_mask);
1224         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1225                     link_info->force_link_speed);
1226
1227         return rc;
1228 }
1229
1230 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1231 {
1232         int i = 0;
1233
1234         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1235                 if (bp->tx_cos_queue[i].profile ==
1236                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1237                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1238                         return true;
1239                 }
1240         }
1241         return false;
1242 }
1243
1244 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1245 {
1246         int i = 0;
1247
1248         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1249                 if (bp->tx_cos_queue[i].profile !=
1250                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1251                     bp->tx_cos_queue[i].id !=
1252                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1253                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1254                         break;
1255                 }
1256         }
1257 }
1258
1259 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1260 {
1261         int rc = 0;
1262         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1263         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1264         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1265         int i;
1266
1267 get_rx_info:
1268         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1269
1270         req.flags = rte_cpu_to_le_32(dir);
1271         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1272         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1273             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1274                 req.drv_qmap_cap =
1275                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1277
1278         HWRM_CHECK_RESULT();
1279
1280         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1281                 GET_TX_QUEUE_INFO(0);
1282                 GET_TX_QUEUE_INFO(1);
1283                 GET_TX_QUEUE_INFO(2);
1284                 GET_TX_QUEUE_INFO(3);
1285                 GET_TX_QUEUE_INFO(4);
1286                 GET_TX_QUEUE_INFO(5);
1287                 GET_TX_QUEUE_INFO(6);
1288                 GET_TX_QUEUE_INFO(7);
1289         } else  {
1290                 GET_RX_QUEUE_INFO(0);
1291                 GET_RX_QUEUE_INFO(1);
1292                 GET_RX_QUEUE_INFO(2);
1293                 GET_RX_QUEUE_INFO(3);
1294                 GET_RX_QUEUE_INFO(4);
1295                 GET_RX_QUEUE_INFO(5);
1296                 GET_RX_QUEUE_INFO(6);
1297                 GET_RX_QUEUE_INFO(7);
1298         }
1299
1300         HWRM_UNLOCK();
1301
1302         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1303                 goto done;
1304
1305         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1306                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1307         } else {
1308                 int j;
1309
1310                 /* iterate and find the COSq profile to use for Tx */
1311                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1312                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1313                                 if (bp->tx_cos_queue[i].id != 0xff)
1314                                         bp->tx_cosq_id[j++] =
1315                                                 bp->tx_cos_queue[i].id;
1316                         }
1317                 } else {
1318                         /* When CoS classification is disabled, for normal NIC
1319                          * operations, ideally we should look to use LOSSY.
1320                          * If not found, fallback to the first valid profile
1321                          */
1322                         if (!bnxt_find_lossy_profile(bp))
1323                                 bnxt_find_first_valid_profile(bp);
1324
1325                 }
1326         }
1327
1328         bp->max_tc = resp->max_configurable_queues;
1329         bp->max_lltc = resp->max_configurable_lossless_queues;
1330         if (bp->max_tc > BNXT_MAX_QUEUE)
1331                 bp->max_tc = BNXT_MAX_QUEUE;
1332         bp->max_q = bp->max_tc;
1333
1334         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1335                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1336                 goto get_rx_info;
1337         }
1338
1339 done:
1340         return rc;
1341 }
1342
1343 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1344                          struct bnxt_ring *ring,
1345                          uint32_t ring_type, uint32_t map_index,
1346                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1347                          uint16_t tx_cosq_id)
1348 {
1349         int rc = 0;
1350         uint32_t enables = 0;
1351         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1352         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1353         struct rte_mempool *mb_pool;
1354         uint16_t rx_buf_size;
1355
1356         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1357
1358         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1359         req.fbo = rte_cpu_to_le_32(0);
1360         /* Association of ring index with doorbell index */
1361         req.logical_id = rte_cpu_to_le_16(map_index);
1362         req.length = rte_cpu_to_le_32(ring->ring_size);
1363
1364         switch (ring_type) {
1365         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1366                 req.ring_type = ring_type;
1367                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1368                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1369                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1370                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1371                         enables |=
1372                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1373                 break;
1374         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1375                 req.ring_type = ring_type;
1376                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1377                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1378                 if (BNXT_CHIP_THOR(bp)) {
1379                         mb_pool = bp->rx_queues[0]->mb_pool;
1380                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1381                                       RTE_PKTMBUF_HEADROOM;
1382                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1383                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1384                         enables |=
1385                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1386                 }
1387                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1388                         enables |=
1389                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1390                 break;
1391         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1392                 req.ring_type = ring_type;
1393                 if (BNXT_HAS_NQ(bp)) {
1394                         /* Association of cp ring with nq */
1395                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1396                         enables |=
1397                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1398                 }
1399                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1400                 break;
1401         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1402                 req.ring_type = ring_type;
1403                 req.page_size = BNXT_PAGE_SHFT;
1404                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1405                 break;
1406         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1407                 req.ring_type = ring_type;
1408                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1409
1410                 mb_pool = bp->rx_queues[0]->mb_pool;
1411                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1412                               RTE_PKTMBUF_HEADROOM;
1413                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1414                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1415
1416                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1417                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1418                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1419                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1420                 break;
1421         default:
1422                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1423                         ring_type);
1424                 HWRM_UNLOCK();
1425                 return -EINVAL;
1426         }
1427         req.enables = rte_cpu_to_le_32(enables);
1428
1429         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1430
1431         if (rc || resp->error_code) {
1432                 if (rc == 0 && resp->error_code)
1433                         rc = rte_le_to_cpu_16(resp->error_code);
1434                 switch (ring_type) {
1435                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1436                         PMD_DRV_LOG(ERR,
1437                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1438                         HWRM_UNLOCK();
1439                         return rc;
1440                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1441                         PMD_DRV_LOG(ERR,
1442                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1443                         HWRM_UNLOCK();
1444                         return rc;
1445                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1446                         PMD_DRV_LOG(ERR,
1447                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1448                                     rc);
1449                         HWRM_UNLOCK();
1450                         return rc;
1451                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1452                         PMD_DRV_LOG(ERR,
1453                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1454                         HWRM_UNLOCK();
1455                         return rc;
1456                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1457                         PMD_DRV_LOG(ERR,
1458                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1459                         HWRM_UNLOCK();
1460                         return rc;
1461                 default:
1462                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1463                         HWRM_UNLOCK();
1464                         return rc;
1465                 }
1466         }
1467
1468         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1469         HWRM_UNLOCK();
1470         return rc;
1471 }
1472
1473 int bnxt_hwrm_ring_free(struct bnxt *bp,
1474                         struct bnxt_ring *ring, uint32_t ring_type)
1475 {
1476         int rc;
1477         struct hwrm_ring_free_input req = {.req_type = 0 };
1478         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1479
1480         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1481
1482         req.ring_type = ring_type;
1483         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1484
1485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1486
1487         if (rc || resp->error_code) {
1488                 if (rc == 0 && resp->error_code)
1489                         rc = rte_le_to_cpu_16(resp->error_code);
1490                 HWRM_UNLOCK();
1491
1492                 switch (ring_type) {
1493                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1494                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1495                                 rc);
1496                         return rc;
1497                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1498                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1499                                 rc);
1500                         return rc;
1501                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1502                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1503                                 rc);
1504                         return rc;
1505                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1506                         PMD_DRV_LOG(ERR,
1507                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1508                         return rc;
1509                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1510                         PMD_DRV_LOG(ERR,
1511                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1512                         return rc;
1513                 default:
1514                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1515                         return rc;
1516                 }
1517         }
1518         HWRM_UNLOCK();
1519         return 0;
1520 }
1521
1522 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1523 {
1524         int rc = 0;
1525         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1526         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1527
1528         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1529
1530         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1531         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1532         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1533         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1534
1535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1536
1537         HWRM_CHECK_RESULT();
1538
1539         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1540
1541         HWRM_UNLOCK();
1542
1543         return rc;
1544 }
1545
1546 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1547 {
1548         int rc;
1549         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1550         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1551
1552         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1553
1554         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1555
1556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1557
1558         HWRM_CHECK_RESULT();
1559         HWRM_UNLOCK();
1560
1561         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1562         return rc;
1563 }
1564
1565 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1566 {
1567         int rc = 0;
1568         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1569         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1570
1571         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1572                 return rc;
1573
1574         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1575
1576         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1577
1578         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1579
1580         HWRM_CHECK_RESULT();
1581         HWRM_UNLOCK();
1582
1583         return rc;
1584 }
1585
1586 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1587                                 unsigned int idx __rte_unused)
1588 {
1589         int rc;
1590         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1591         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1592
1593         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1594
1595         req.update_period_ms = rte_cpu_to_le_32(0);
1596
1597         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1598
1599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1600
1601         HWRM_CHECK_RESULT();
1602
1603         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1604
1605         HWRM_UNLOCK();
1606
1607         return rc;
1608 }
1609
1610 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1611                                 unsigned int idx __rte_unused)
1612 {
1613         int rc;
1614         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1615         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1616
1617         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1618
1619         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1620
1621         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1622
1623         HWRM_CHECK_RESULT();
1624         HWRM_UNLOCK();
1625
1626         return rc;
1627 }
1628
1629 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1630 {
1631         int rc = 0, i, j;
1632         struct hwrm_vnic_alloc_input req = { 0 };
1633         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1634
1635         if (!BNXT_HAS_RING_GRPS(bp))
1636                 goto skip_ring_grps;
1637
1638         /* map ring groups to this vnic */
1639         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1640                 vnic->start_grp_id, vnic->end_grp_id);
1641         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1642                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1643
1644         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1645         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1646         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1647         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1648
1649 skip_ring_grps:
1650         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1651         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1652
1653         if (vnic->func_default)
1654                 req.flags =
1655                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1657
1658         HWRM_CHECK_RESULT();
1659
1660         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1661         HWRM_UNLOCK();
1662         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1663         return rc;
1664 }
1665
1666 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1667                                         struct bnxt_vnic_info *vnic,
1668                                         struct bnxt_plcmodes_cfg *pmode)
1669 {
1670         int rc = 0;
1671         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1672         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1673
1674         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1675
1676         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1677
1678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1679
1680         HWRM_CHECK_RESULT();
1681
1682         pmode->flags = rte_le_to_cpu_32(resp->flags);
1683         /* dflt_vnic bit doesn't exist in the _cfg command */
1684         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1685         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1686         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1687         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1688
1689         HWRM_UNLOCK();
1690
1691         return rc;
1692 }
1693
1694 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1695                                        struct bnxt_vnic_info *vnic,
1696                                        struct bnxt_plcmodes_cfg *pmode)
1697 {
1698         int rc = 0;
1699         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1700         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1701
1702         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1703                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1704                 return rc;
1705         }
1706
1707         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1708
1709         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1710         req.flags = rte_cpu_to_le_32(pmode->flags);
1711         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1712         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1713         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1714         req.enables = rte_cpu_to_le_32(
1715             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1716             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1717             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1718         );
1719
1720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1721
1722         HWRM_CHECK_RESULT();
1723         HWRM_UNLOCK();
1724
1725         return rc;
1726 }
1727
1728 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1729 {
1730         int rc = 0;
1731         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1732         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1733         struct bnxt_plcmodes_cfg pmodes = { 0 };
1734         uint32_t ctx_enable_flag = 0;
1735         uint32_t enables = 0;
1736
1737         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1738                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1739                 return rc;
1740         }
1741
1742         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1743         if (rc)
1744                 return rc;
1745
1746         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1747
1748         if (BNXT_CHIP_THOR(bp)) {
1749                 int dflt_rxq = vnic->start_grp_id;
1750                 struct bnxt_rx_ring_info *rxr;
1751                 struct bnxt_cp_ring_info *cpr;
1752                 struct bnxt_rx_queue *rxq;
1753                 int i;
1754
1755                 /*
1756                  * The first active receive ring is used as the VNIC
1757                  * default receive ring. If there are no active receive
1758                  * rings (all corresponding receive queues are stopped),
1759                  * the first receive ring is used.
1760                  */
1761                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1762                         rxq = bp->eth_dev->data->rx_queues[i];
1763                         if (rxq->rx_started) {
1764                                 dflt_rxq = i;
1765                                 break;
1766                         }
1767                 }
1768
1769                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1770                 rxr = rxq->rx_ring;
1771                 cpr = rxq->cp_ring;
1772
1773                 req.default_rx_ring_id =
1774                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1775                 req.default_cmpl_ring_id =
1776                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1777                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1778                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1779                 goto config_mru;
1780         }
1781
1782         /* Only RSS support for now TBD: COS & LB */
1783         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1784         if (vnic->lb_rule != 0xffff)
1785                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1786         if (vnic->cos_rule != 0xffff)
1787                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1788         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1789                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1790                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1791         }
1792         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1793                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1794                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1795         }
1796
1797         enables |= ctx_enable_flag;
1798         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1799         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1800         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1801         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1802
1803 config_mru:
1804         req.enables = rte_cpu_to_le_32(enables);
1805         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1806         req.mru = rte_cpu_to_le_16(vnic->mru);
1807         /* Configure default VNIC only once. */
1808         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1809                 req.flags |=
1810                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1811                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1812         }
1813         if (vnic->vlan_strip)
1814                 req.flags |=
1815                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1816         if (vnic->bd_stall)
1817                 req.flags |=
1818                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1819         if (vnic->roce_dual)
1820                 req.flags |= rte_cpu_to_le_32(
1821                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1822         if (vnic->roce_only)
1823                 req.flags |= rte_cpu_to_le_32(
1824                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1825         if (vnic->rss_dflt_cr)
1826                 req.flags |= rte_cpu_to_le_32(
1827                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1828
1829         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1830
1831         HWRM_CHECK_RESULT();
1832         HWRM_UNLOCK();
1833
1834         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1835
1836         return rc;
1837 }
1838
1839 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1840                 int16_t fw_vf_id)
1841 {
1842         int rc = 0;
1843         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1844         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1845
1846         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1847                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1848                 return rc;
1849         }
1850         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1851
1852         req.enables =
1853                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1854         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1856
1857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1858
1859         HWRM_CHECK_RESULT();
1860
1861         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1862         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1863         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1864         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1865         vnic->mru = rte_le_to_cpu_16(resp->mru);
1866         vnic->func_default = rte_le_to_cpu_32(
1867                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1868         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1869                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1870         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1871                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1872         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1873                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1874         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1875                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1876         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1877                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1878
1879         HWRM_UNLOCK();
1880
1881         return rc;
1882 }
1883
1884 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1885                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1886 {
1887         int rc = 0;
1888         uint16_t ctx_id;
1889         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1890         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1891                                                 bp->hwrm_cmd_resp_addr;
1892
1893         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1894
1895         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1896         HWRM_CHECK_RESULT();
1897
1898         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1899         if (!BNXT_HAS_RING_GRPS(bp))
1900                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1901         else if (ctx_idx == 0)
1902                 vnic->rss_rule = ctx_id;
1903
1904         HWRM_UNLOCK();
1905
1906         return rc;
1907 }
1908
1909 static
1910 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1911                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1912 {
1913         int rc = 0;
1914         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1915         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1916                                                 bp->hwrm_cmd_resp_addr;
1917
1918         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1919                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1920                 return rc;
1921         }
1922         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1923
1924         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1925
1926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1927
1928         HWRM_CHECK_RESULT();
1929         HWRM_UNLOCK();
1930
1931         return rc;
1932 }
1933
1934 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1935 {
1936         int rc = 0;
1937
1938         if (BNXT_CHIP_THOR(bp)) {
1939                 int j;
1940
1941                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1942                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1943                                                       vnic,
1944                                                       vnic->fw_grp_ids[j]);
1945                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1946                 }
1947                 vnic->num_lb_ctxts = 0;
1948         } else {
1949                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1950                 vnic->rss_rule = INVALID_HW_RING_ID;
1951         }
1952
1953         return rc;
1954 }
1955
1956 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1957 {
1958         int rc = 0;
1959         struct hwrm_vnic_free_input req = {.req_type = 0 };
1960         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1961
1962         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1963                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1964                 return rc;
1965         }
1966
1967         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1968
1969         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1970
1971         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1972
1973         HWRM_CHECK_RESULT();
1974         HWRM_UNLOCK();
1975
1976         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1977         /* Configure default VNIC again if necessary. */
1978         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1979                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1980
1981         return rc;
1982 }
1983
1984 static int
1985 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1986 {
1987         int i;
1988         int rc = 0;
1989         int nr_ctxs = vnic->num_lb_ctxts;
1990         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1991         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1992
1993         for (i = 0; i < nr_ctxs; i++) {
1994                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1995
1996                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1997                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1998                 req.hash_mode_flags = vnic->hash_mode;
1999
2000                 req.hash_key_tbl_addr =
2001                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2002
2003                 req.ring_grp_tbl_addr =
2004                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2005                                          i * HW_HASH_INDEX_SIZE);
2006                 req.ring_table_pair_index = i;
2007                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2008
2009                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2010                                             BNXT_USE_CHIMP_MB);
2011
2012                 HWRM_CHECK_RESULT();
2013                 HWRM_UNLOCK();
2014         }
2015
2016         return rc;
2017 }
2018
2019 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2020                            struct bnxt_vnic_info *vnic)
2021 {
2022         int rc = 0;
2023         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2024         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2025
2026         if (!vnic->rss_table)
2027                 return 0;
2028
2029         if (BNXT_CHIP_THOR(bp))
2030                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2031
2032         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2033
2034         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2035         req.hash_mode_flags = vnic->hash_mode;
2036
2037         req.ring_grp_tbl_addr =
2038             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2039         req.hash_key_tbl_addr =
2040             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2041         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2042         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2043
2044         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2045
2046         HWRM_CHECK_RESULT();
2047         HWRM_UNLOCK();
2048
2049         return rc;
2050 }
2051
2052 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2053                         struct bnxt_vnic_info *vnic)
2054 {
2055         int rc = 0;
2056         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2057         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2058         uint16_t size;
2059
2060         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2061                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2062                 return rc;
2063         }
2064
2065         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2066
2067         req.flags = rte_cpu_to_le_32(
2068                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2069
2070         req.enables = rte_cpu_to_le_32(
2071                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2072
2073         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2074         size -= RTE_PKTMBUF_HEADROOM;
2075         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2076
2077         req.jumbo_thresh = rte_cpu_to_le_16(size);
2078         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2079
2080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2081
2082         HWRM_CHECK_RESULT();
2083         HWRM_UNLOCK();
2084
2085         return rc;
2086 }
2087
2088 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2089                         struct bnxt_vnic_info *vnic, bool enable)
2090 {
2091         int rc = 0;
2092         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2093         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2094
2095         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2096                 if (enable)
2097                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2098                 return -ENOTSUP;
2099         }
2100
2101         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2102                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2103                 return 0;
2104         }
2105
2106         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2107
2108         if (enable) {
2109                 req.enables = rte_cpu_to_le_32(
2110                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2112                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2113                 req.flags = rte_cpu_to_le_32(
2114                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2115                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2116                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2117                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2118                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2119                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2120                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2121                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2122                 req.min_agg_len = rte_cpu_to_le_32(512);
2123         }
2124         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2125
2126         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2127
2128         HWRM_CHECK_RESULT();
2129         HWRM_UNLOCK();
2130
2131         return rc;
2132 }
2133
2134 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2135 {
2136         struct hwrm_func_cfg_input req = {0};
2137         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2138         int rc;
2139
2140         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2141         req.enables = rte_cpu_to_le_32(
2142                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2143         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2144         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2145
2146         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2147
2148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2149         HWRM_CHECK_RESULT();
2150         HWRM_UNLOCK();
2151
2152         bp->pf.vf_info[vf].random_mac = false;
2153
2154         return rc;
2155 }
2156
2157 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2158                                   uint64_t *dropped)
2159 {
2160         int rc = 0;
2161         struct hwrm_func_qstats_input req = {.req_type = 0};
2162         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2163
2164         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2165
2166         req.fid = rte_cpu_to_le_16(fid);
2167
2168         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2169
2170         HWRM_CHECK_RESULT();
2171
2172         if (dropped)
2173                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2174
2175         HWRM_UNLOCK();
2176
2177         return rc;
2178 }
2179
2180 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2181                           struct rte_eth_stats *stats)
2182 {
2183         int rc = 0;
2184         struct hwrm_func_qstats_input req = {.req_type = 0};
2185         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2186
2187         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2188
2189         req.fid = rte_cpu_to_le_16(fid);
2190
2191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2192
2193         HWRM_CHECK_RESULT();
2194
2195         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2196         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2197         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2198         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2199         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2200         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2201
2202         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2203         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2204         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2205         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2206         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2207         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2208
2209         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2210         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2211         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2212
2213         HWRM_UNLOCK();
2214
2215         return rc;
2216 }
2217
2218 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2219 {
2220         int rc = 0;
2221         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2222         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2223
2224         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2225
2226         req.fid = rte_cpu_to_le_16(fid);
2227
2228         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2229
2230         HWRM_CHECK_RESULT();
2231         HWRM_UNLOCK();
2232
2233         return rc;
2234 }
2235
2236 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2237 {
2238         unsigned int i;
2239         int rc = 0;
2240
2241         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2242                 struct bnxt_tx_queue *txq;
2243                 struct bnxt_rx_queue *rxq;
2244                 struct bnxt_cp_ring_info *cpr;
2245
2246                 if (i >= bp->rx_cp_nr_rings) {
2247                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2248                         cpr = txq->cp_ring;
2249                 } else {
2250                         rxq = bp->rx_queues[i];
2251                         cpr = rxq->cp_ring;
2252                 }
2253
2254                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2255                 if (rc)
2256                         return rc;
2257         }
2258         return 0;
2259 }
2260
2261 static int
2262 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2263 {
2264         int rc;
2265         unsigned int i;
2266         struct bnxt_cp_ring_info *cpr;
2267
2268         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2269
2270                 if (i >= bp->rx_cp_nr_rings) {
2271                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2272                 } else {
2273                         cpr = bp->rx_queues[i]->cp_ring;
2274                         if (BNXT_HAS_RING_GRPS(bp))
2275                                 bp->grp_info[i].fw_stats_ctx = -1;
2276                 }
2277                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2278                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2279                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2280                         if (rc)
2281                                 return rc;
2282                 }
2283         }
2284         return 0;
2285 }
2286
2287 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2288 {
2289         unsigned int i;
2290         int rc = 0;
2291
2292         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2293                 struct bnxt_tx_queue *txq;
2294                 struct bnxt_rx_queue *rxq;
2295                 struct bnxt_cp_ring_info *cpr;
2296
2297                 if (i >= bp->rx_cp_nr_rings) {
2298                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2299                         cpr = txq->cp_ring;
2300                 } else {
2301                         rxq = bp->rx_queues[i];
2302                         cpr = rxq->cp_ring;
2303                 }
2304
2305                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2306
2307                 if (rc)
2308                         return rc;
2309         }
2310         return rc;
2311 }
2312
2313 static int
2314 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2315 {
2316         uint16_t idx;
2317         uint32_t rc = 0;
2318
2319         if (!BNXT_HAS_RING_GRPS(bp))
2320                 return 0;
2321
2322         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2323
2324                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2325                         continue;
2326
2327                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2328
2329                 if (rc)
2330                         return rc;
2331         }
2332         return rc;
2333 }
2334
2335 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2336 {
2337         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2338
2339         bnxt_hwrm_ring_free(bp, cp_ring,
2340                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2341         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2342         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2343                                      sizeof(*cpr->cp_desc_ring));
2344         cpr->cp_raw_cons = 0;
2345         cpr->valid = 0;
2346 }
2347
2348 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2349 {
2350         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2351
2352         bnxt_hwrm_ring_free(bp, cp_ring,
2353                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2354         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2355         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2356                         sizeof(*cpr->cp_desc_ring));
2357         cpr->cp_raw_cons = 0;
2358         cpr->valid = 0;
2359 }
2360
2361 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2362 {
2363         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2364         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2365         struct bnxt_ring *ring = rxr->rx_ring_struct;
2366         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2367
2368         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2369                 bnxt_hwrm_ring_free(bp, ring,
2370                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2371                 ring->fw_ring_id = INVALID_HW_RING_ID;
2372                 if (BNXT_HAS_RING_GRPS(bp))
2373                         bp->grp_info[queue_index].rx_fw_ring_id =
2374                                                         INVALID_HW_RING_ID;
2375                 memset(rxr->rx_desc_ring, 0,
2376                        rxr->rx_ring_struct->ring_size *
2377                        sizeof(*rxr->rx_desc_ring));
2378                 memset(rxr->rx_buf_ring, 0,
2379                        rxr->rx_ring_struct->ring_size *
2380                        sizeof(*rxr->rx_buf_ring));
2381                 rxr->rx_prod = 0;
2382         }
2383         ring = rxr->ag_ring_struct;
2384         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2385                 bnxt_hwrm_ring_free(bp, ring,
2386                                     BNXT_CHIP_THOR(bp) ?
2387                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2388                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2389                 ring->fw_ring_id = INVALID_HW_RING_ID;
2390                 memset(rxr->ag_buf_ring, 0,
2391                        rxr->ag_ring_struct->ring_size *
2392                        sizeof(*rxr->ag_buf_ring));
2393                 rxr->ag_prod = 0;
2394                 if (BNXT_HAS_RING_GRPS(bp))
2395                         bp->grp_info[queue_index].ag_fw_ring_id =
2396                                                         INVALID_HW_RING_ID;
2397         }
2398         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2399                 bnxt_free_cp_ring(bp, cpr);
2400
2401         if (BNXT_HAS_RING_GRPS(bp))
2402                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2403 }
2404
2405 static int
2406 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2407 {
2408         unsigned int i;
2409
2410         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2411                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2412                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2413                 struct bnxt_ring *ring = txr->tx_ring_struct;
2414                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2415
2416                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2417                         bnxt_hwrm_ring_free(bp, ring,
2418                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2419                         ring->fw_ring_id = INVALID_HW_RING_ID;
2420                         memset(txr->tx_desc_ring, 0,
2421                                         txr->tx_ring_struct->ring_size *
2422                                         sizeof(*txr->tx_desc_ring));
2423                         memset(txr->tx_buf_ring, 0,
2424                                         txr->tx_ring_struct->ring_size *
2425                                         sizeof(*txr->tx_buf_ring));
2426                         txr->tx_prod = 0;
2427                         txr->tx_cons = 0;
2428                 }
2429                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2430                         bnxt_free_cp_ring(bp, cpr);
2431                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2432                 }
2433         }
2434
2435         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2436                 bnxt_free_hwrm_rx_ring(bp, i);
2437
2438         return 0;
2439 }
2440
2441 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2442 {
2443         uint16_t i;
2444         uint32_t rc = 0;
2445
2446         if (!BNXT_HAS_RING_GRPS(bp))
2447                 return 0;
2448
2449         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2450                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2451                 if (rc)
2452                         return rc;
2453         }
2454         return rc;
2455 }
2456
2457 /*
2458  * HWRM utility functions
2459  */
2460
2461 void bnxt_free_hwrm_resources(struct bnxt *bp)
2462 {
2463         /* Release memzone */
2464         rte_free(bp->hwrm_cmd_resp_addr);
2465         rte_free(bp->hwrm_short_cmd_req_addr);
2466         bp->hwrm_cmd_resp_addr = NULL;
2467         bp->hwrm_short_cmd_req_addr = NULL;
2468         bp->hwrm_cmd_resp_dma_addr = 0;
2469         bp->hwrm_short_cmd_req_dma_addr = 0;
2470 }
2471
2472 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2473 {
2474         struct rte_pci_device *pdev = bp->pdev;
2475         char type[RTE_MEMZONE_NAMESIZE];
2476
2477         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2478                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2479         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2480         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2481         if (bp->hwrm_cmd_resp_addr == NULL)
2482                 return -ENOMEM;
2483         bp->hwrm_cmd_resp_dma_addr =
2484                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2485         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2486                 PMD_DRV_LOG(ERR,
2487                         "unable to map response address to physical memory\n");
2488                 return -ENOMEM;
2489         }
2490         rte_spinlock_init(&bp->hwrm_lock);
2491
2492         return 0;
2493 }
2494
2495 static int
2496 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2497 {
2498         struct bnxt_filter_info *filter;
2499         int rc = 0;
2500
2501         STAILQ_FOREACH(filter, &vnic->filter, next) {
2502                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2503                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2504                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2505                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2506                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2507                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2508                 bnxt_free_filter(bp, filter);
2509         }
2510         return rc;
2511 }
2512
2513 static int
2514 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2515 {
2516         struct bnxt_filter_info *filter;
2517         struct rte_flow *flow;
2518         int rc = 0;
2519
2520         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2521                 flow = STAILQ_FIRST(&vnic->flow_list);
2522                 filter = flow->filter;
2523                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2524                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2525                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2526                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2527                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2528                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2529
2530                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2531                 rte_free(flow);
2532         }
2533         return rc;
2534 }
2535
2536 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2537 {
2538         struct bnxt_filter_info *filter;
2539         int rc = 0;
2540
2541         STAILQ_FOREACH(filter, &vnic->filter, next) {
2542                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2543                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2544                                                      filter);
2545                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2546                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2547                                                          filter);
2548                 else
2549                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2550                                                      filter);
2551                 if (rc)
2552                         break;
2553         }
2554         return rc;
2555 }
2556
2557 static void
2558 bnxt_free_tunnel_ports(struct bnxt *bp)
2559 {
2560         if (bp->vxlan_port_cnt)
2561                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2562                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2563         bp->vxlan_port = 0;
2564         if (bp->geneve_port_cnt)
2565                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2566                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2567         bp->geneve_port = 0;
2568 }
2569
2570 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2571 {
2572         int i;
2573
2574         if (bp->vnic_info == NULL)
2575                 return;
2576
2577         /*
2578          * Cleanup VNICs in reverse order, to make sure the L2 filter
2579          * from vnic0 is last to be cleaned up.
2580          */
2581         for (i = bp->max_vnics - 1; i >= 0; i--) {
2582                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2583
2584                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2585                         continue;
2586
2587                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2588
2589                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2590
2591                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2592
2593                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2594
2595                 bnxt_hwrm_vnic_free(bp, vnic);
2596
2597                 rte_free(vnic->fw_grp_ids);
2598         }
2599         /* Ring resources */
2600         bnxt_free_all_hwrm_rings(bp);
2601         bnxt_free_all_hwrm_ring_grps(bp);
2602         bnxt_free_all_hwrm_stat_ctxs(bp);
2603         bnxt_free_tunnel_ports(bp);
2604 }
2605
2606 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2607 {
2608         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2609
2610         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2611                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2612
2613         switch (conf_link_speed) {
2614         case ETH_LINK_SPEED_10M_HD:
2615         case ETH_LINK_SPEED_100M_HD:
2616                 /* FALLTHROUGH */
2617                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2618         }
2619         return hw_link_duplex;
2620 }
2621
2622 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2623 {
2624         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2625 }
2626
2627 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2628 {
2629         uint16_t eth_link_speed = 0;
2630
2631         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2632                 return ETH_LINK_SPEED_AUTONEG;
2633
2634         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2635         case ETH_LINK_SPEED_100M:
2636         case ETH_LINK_SPEED_100M_HD:
2637                 /* FALLTHROUGH */
2638                 eth_link_speed =
2639                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2640                 break;
2641         case ETH_LINK_SPEED_1G:
2642                 eth_link_speed =
2643                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2644                 break;
2645         case ETH_LINK_SPEED_2_5G:
2646                 eth_link_speed =
2647                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2648                 break;
2649         case ETH_LINK_SPEED_10G:
2650                 eth_link_speed =
2651                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2652                 break;
2653         case ETH_LINK_SPEED_20G:
2654                 eth_link_speed =
2655                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2656                 break;
2657         case ETH_LINK_SPEED_25G:
2658                 eth_link_speed =
2659                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2660                 break;
2661         case ETH_LINK_SPEED_40G:
2662                 eth_link_speed =
2663                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2664                 break;
2665         case ETH_LINK_SPEED_50G:
2666                 eth_link_speed =
2667                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2668                 break;
2669         case ETH_LINK_SPEED_100G:
2670                 eth_link_speed =
2671                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2672                 break;
2673         default:
2674                 PMD_DRV_LOG(ERR,
2675                         "Unsupported link speed %d; default to AUTO\n",
2676                         conf_link_speed);
2677                 break;
2678         }
2679         return eth_link_speed;
2680 }
2681
2682 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2683                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2684                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2685                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2686
2687 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2688 {
2689         uint32_t one_speed;
2690
2691         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2692                 return 0;
2693
2694         if (link_speed & ETH_LINK_SPEED_FIXED) {
2695                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2696
2697                 if (one_speed & (one_speed - 1)) {
2698                         PMD_DRV_LOG(ERR,
2699                                 "Invalid advertised speeds (%u) for port %u\n",
2700                                 link_speed, port_id);
2701                         return -EINVAL;
2702                 }
2703                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2704                         PMD_DRV_LOG(ERR,
2705                                 "Unsupported advertised speed (%u) for port %u\n",
2706                                 link_speed, port_id);
2707                         return -EINVAL;
2708                 }
2709         } else {
2710                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2711                         PMD_DRV_LOG(ERR,
2712                                 "Unsupported advertised speeds (%u) for port %u\n",
2713                                 link_speed, port_id);
2714                         return -EINVAL;
2715                 }
2716         }
2717         return 0;
2718 }
2719
2720 static uint16_t
2721 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2722 {
2723         uint16_t ret = 0;
2724
2725         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2726                 if (bp->link_info.support_speeds)
2727                         return bp->link_info.support_speeds;
2728                 link_speed = BNXT_SUPPORTED_SPEEDS;
2729         }
2730
2731         if (link_speed & ETH_LINK_SPEED_100M)
2732                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2733         if (link_speed & ETH_LINK_SPEED_100M_HD)
2734                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2735         if (link_speed & ETH_LINK_SPEED_1G)
2736                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2737         if (link_speed & ETH_LINK_SPEED_2_5G)
2738                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2739         if (link_speed & ETH_LINK_SPEED_10G)
2740                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2741         if (link_speed & ETH_LINK_SPEED_20G)
2742                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2743         if (link_speed & ETH_LINK_SPEED_25G)
2744                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2745         if (link_speed & ETH_LINK_SPEED_40G)
2746                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2747         if (link_speed & ETH_LINK_SPEED_50G)
2748                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2749         if (link_speed & ETH_LINK_SPEED_100G)
2750                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2751         return ret;
2752 }
2753
2754 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2755 {
2756         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2757
2758         switch (hw_link_speed) {
2759         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2760                 eth_link_speed = ETH_SPEED_NUM_100M;
2761                 break;
2762         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2763                 eth_link_speed = ETH_SPEED_NUM_1G;
2764                 break;
2765         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2766                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2767                 break;
2768         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2769                 eth_link_speed = ETH_SPEED_NUM_10G;
2770                 break;
2771         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2772                 eth_link_speed = ETH_SPEED_NUM_20G;
2773                 break;
2774         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2775                 eth_link_speed = ETH_SPEED_NUM_25G;
2776                 break;
2777         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2778                 eth_link_speed = ETH_SPEED_NUM_40G;
2779                 break;
2780         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2781                 eth_link_speed = ETH_SPEED_NUM_50G;
2782                 break;
2783         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2784                 eth_link_speed = ETH_SPEED_NUM_100G;
2785                 break;
2786         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2787         default:
2788                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2789                         hw_link_speed);
2790                 break;
2791         }
2792         return eth_link_speed;
2793 }
2794
2795 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2796 {
2797         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2798
2799         switch (hw_link_duplex) {
2800         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2801         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2802                 /* FALLTHROUGH */
2803                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2804                 break;
2805         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2806                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2807                 break;
2808         default:
2809                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2810                         hw_link_duplex);
2811                 break;
2812         }
2813         return eth_link_duplex;
2814 }
2815
2816 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2817 {
2818         int rc = 0;
2819         struct bnxt_link_info *link_info = &bp->link_info;
2820
2821         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2822         if (rc) {
2823                 PMD_DRV_LOG(ERR,
2824                         "Get link config failed with rc %d\n", rc);
2825                 goto exit;
2826         }
2827         if (link_info->link_speed)
2828                 link->link_speed =
2829                         bnxt_parse_hw_link_speed(link_info->link_speed);
2830         else
2831                 link->link_speed = ETH_SPEED_NUM_NONE;
2832         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2833         link->link_status = link_info->link_up;
2834         link->link_autoneg = link_info->auto_mode ==
2835                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2836                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2837 exit:
2838         return rc;
2839 }
2840
2841 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2842 {
2843         int rc = 0;
2844         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2845         struct bnxt_link_info link_req;
2846         uint16_t speed, autoneg;
2847
2848         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2849                 return 0;
2850
2851         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2852                         bp->eth_dev->data->port_id);
2853         if (rc)
2854                 goto error;
2855
2856         memset(&link_req, 0, sizeof(link_req));
2857         link_req.link_up = link_up;
2858         if (!link_up)
2859                 goto port_phy_cfg;
2860
2861         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2862         if (BNXT_CHIP_THOR(bp) &&
2863             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2864                 /* 40G is not supported as part of media auto detect.
2865                  * The speed should be forced and autoneg disabled
2866                  * to configure 40G speed.
2867                  */
2868                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2869                 autoneg = 0;
2870         }
2871
2872         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2873         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2874         /* Autoneg can be done only when the FW allows.
2875          * When user configures fixed speed of 40G and later changes to
2876          * any other speed, auto_link_speed/force_link_speed is still set
2877          * to 40G until link comes up at new speed.
2878          */
2879         if (autoneg == 1 &&
2880             !(!BNXT_CHIP_THOR(bp) &&
2881               (bp->link_info.auto_link_speed ||
2882                bp->link_info.force_link_speed))) {
2883                 link_req.phy_flags |=
2884                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2885                 link_req.auto_link_speed_mask =
2886                         bnxt_parse_eth_link_speed_mask(bp,
2887                                                        dev_conf->link_speeds);
2888         } else {
2889                 if (bp->link_info.phy_type ==
2890                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2891                     bp->link_info.phy_type ==
2892                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2893                     bp->link_info.media_type ==
2894                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2895                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2896                         return -EINVAL;
2897                 }
2898
2899                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2900                 /* If user wants a particular speed try that first. */
2901                 if (speed)
2902                         link_req.link_speed = speed;
2903                 else if (bp->link_info.force_link_speed)
2904                         link_req.link_speed = bp->link_info.force_link_speed;
2905                 else
2906                         link_req.link_speed = bp->link_info.auto_link_speed;
2907         }
2908         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2909         link_req.auto_pause = bp->link_info.auto_pause;
2910         link_req.force_pause = bp->link_info.force_pause;
2911
2912 port_phy_cfg:
2913         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2914         if (rc) {
2915                 PMD_DRV_LOG(ERR,
2916                         "Set link config failed with rc %d\n", rc);
2917         }
2918
2919 error:
2920         return rc;
2921 }
2922
2923 /* JIRA 22088 */
2924 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2925 {
2926         struct hwrm_func_qcfg_input req = {0};
2927         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2928         uint16_t flags;
2929         int rc = 0;
2930
2931         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2932         req.fid = rte_cpu_to_le_16(0xffff);
2933
2934         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2935
2936         HWRM_CHECK_RESULT();
2937
2938         /* Hard Coded.. 0xfff VLAN ID mask */
2939         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2940         flags = rte_le_to_cpu_16(resp->flags);
2941         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2942                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2943
2944         if (BNXT_VF(bp) &&
2945             !BNXT_VF_IS_TRUSTED(bp) &&
2946             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2947                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2948                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2949         } else if (BNXT_VF(bp) &&
2950                    BNXT_VF_IS_TRUSTED(bp) &&
2951                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2952                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2953                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2954         }
2955
2956         if (mtu)
2957                 *mtu = rte_le_to_cpu_16(resp->mtu);
2958
2959         switch (resp->port_partition_type) {
2960         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2961         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2962         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2963                 /* FALLTHROUGH */
2964                 bp->flags |= BNXT_FLAG_NPAR_PF;
2965                 break;
2966         default:
2967                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
2968                 break;
2969         }
2970
2971         HWRM_UNLOCK();
2972
2973         return rc;
2974 }
2975
2976 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2977                                    struct hwrm_func_qcaps_output *qcaps)
2978 {
2979         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2980         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2981                sizeof(qcaps->mac_address));
2982         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2983         qcaps->max_rx_rings = fcfg->num_rx_rings;
2984         qcaps->max_tx_rings = fcfg->num_tx_rings;
2985         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2986         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2987         qcaps->max_vfs = 0;
2988         qcaps->first_vf_id = 0;
2989         qcaps->max_vnics = fcfg->num_vnics;
2990         qcaps->max_decap_records = 0;
2991         qcaps->max_encap_records = 0;
2992         qcaps->max_tx_wm_flows = 0;
2993         qcaps->max_tx_em_flows = 0;
2994         qcaps->max_rx_wm_flows = 0;
2995         qcaps->max_rx_em_flows = 0;
2996         qcaps->max_flow_id = 0;
2997         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2998         qcaps->max_sp_tx_rings = 0;
2999         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3000 }
3001
3002 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3003 {
3004         struct hwrm_func_cfg_input req = {0};
3005         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3006         uint32_t enables;
3007         int rc;
3008
3009         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3010                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3011                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3012                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3013                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3014                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3015                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3016                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3017                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3018
3019         if (BNXT_HAS_RING_GRPS(bp)) {
3020                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3021                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3022         } else if (BNXT_HAS_NQ(bp)) {
3023                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3024                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3025         }
3026
3027         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3028         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3029         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3030         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3031         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3032         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3033         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3034         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3035         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3036         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3037         req.fid = rte_cpu_to_le_16(0xffff);
3038         req.enables = rte_cpu_to_le_32(enables);
3039
3040         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3041
3042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3043
3044         HWRM_CHECK_RESULT();
3045         HWRM_UNLOCK();
3046
3047         return rc;
3048 }
3049
3050 static void populate_vf_func_cfg_req(struct bnxt *bp,
3051                                      struct hwrm_func_cfg_input *req,
3052                                      int num_vfs)
3053 {
3054         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3055                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3056                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3057                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3058                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3059                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3060                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3061                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3062                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3063                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3064
3065         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3066                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3067                                     BNXT_NUM_VLANS);
3068         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3069         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3070                                                 (num_vfs + 1));
3071         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3072         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3073                                                (num_vfs + 1));
3074         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3075         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3076         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3077         /* TODO: For now, do not support VMDq/RFS on VFs. */
3078         req->num_vnics = rte_cpu_to_le_16(1);
3079         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3080                                                  (num_vfs + 1));
3081 }
3082
3083 static void add_random_mac_if_needed(struct bnxt *bp,
3084                                      struct hwrm_func_cfg_input *cfg_req,
3085                                      int vf)
3086 {
3087         struct rte_ether_addr mac;
3088
3089         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3090                 return;
3091
3092         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3093                 cfg_req->enables |=
3094                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3095                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3096                 bp->pf.vf_info[vf].random_mac = true;
3097         } else {
3098                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3099                         RTE_ETHER_ADDR_LEN);
3100         }
3101 }
3102
3103 static int reserve_resources_from_vf(struct bnxt *bp,
3104                                      struct hwrm_func_cfg_input *cfg_req,
3105                                      int vf)
3106 {
3107         struct hwrm_func_qcaps_input req = {0};
3108         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3109         int rc;
3110
3111         /* Get the actual allocated values now */
3112         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3113         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3114         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3115
3116         if (rc) {
3117                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3118                 copy_func_cfg_to_qcaps(cfg_req, resp);
3119         } else if (resp->error_code) {
3120                 rc = rte_le_to_cpu_16(resp->error_code);
3121                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3122                 copy_func_cfg_to_qcaps(cfg_req, resp);
3123         }
3124
3125         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3126         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3127         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3128         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3129         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3130         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3131         /*
3132          * TODO: While not supporting VMDq with VFs, max_vnics is always
3133          * forced to 1 in this case
3134          */
3135         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3136         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3137
3138         HWRM_UNLOCK();
3139
3140         return 0;
3141 }
3142
3143 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3144 {
3145         struct hwrm_func_qcfg_input req = {0};
3146         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3147         int rc;
3148
3149         /* Check for zero MAC address */
3150         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3151         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3153         HWRM_CHECK_RESULT();
3154         rc = rte_le_to_cpu_16(resp->vlan);
3155
3156         HWRM_UNLOCK();
3157
3158         return rc;
3159 }
3160
3161 static int update_pf_resource_max(struct bnxt *bp)
3162 {
3163         struct hwrm_func_qcfg_input req = {0};
3164         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3165         int rc;
3166
3167         /* And copy the allocated numbers into the pf struct */
3168         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3169         req.fid = rte_cpu_to_le_16(0xffff);
3170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3171         HWRM_CHECK_RESULT();
3172
3173         /* Only TX ring value reflects actual allocation? TODO */
3174         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3175         bp->pf.evb_mode = resp->evb_mode;
3176
3177         HWRM_UNLOCK();
3178
3179         return rc;
3180 }
3181
3182 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3183 {
3184         int rc;
3185
3186         if (!BNXT_PF(bp)) {
3187                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3188                 return -EINVAL;
3189         }
3190
3191         rc = bnxt_hwrm_func_qcaps(bp);
3192         if (rc)
3193                 return rc;
3194
3195         bp->pf.func_cfg_flags &=
3196                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3197                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3198         bp->pf.func_cfg_flags |=
3199                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3200         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3201         rc = __bnxt_hwrm_func_qcaps(bp);
3202         return rc;
3203 }
3204
3205 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3206 {
3207         struct hwrm_func_cfg_input req = {0};
3208         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3209         int i;
3210         size_t sz;
3211         int rc = 0;
3212         size_t req_buf_sz;
3213
3214         if (!BNXT_PF(bp)) {
3215                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3216                 return -EINVAL;
3217         }
3218
3219         rc = bnxt_hwrm_func_qcaps(bp);
3220
3221         if (rc)
3222                 return rc;
3223
3224         bp->pf.active_vfs = num_vfs;
3225
3226         /*
3227          * First, configure the PF to only use one TX ring.  This ensures that
3228          * there are enough rings for all VFs.
3229          *
3230          * If we don't do this, when we call func_alloc() later, we will lock
3231          * extra rings to the PF that won't be available during func_cfg() of
3232          * the VFs.
3233          *
3234          * This has been fixed with firmware versions above 20.6.54
3235          */
3236         bp->pf.func_cfg_flags &=
3237                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3238                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3239         bp->pf.func_cfg_flags |=
3240                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3241         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3242         if (rc)
3243                 return rc;
3244
3245         /*
3246          * Now, create and register a buffer to hold forwarded VF requests
3247          */
3248         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3249         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3250                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3251         if (bp->pf.vf_req_buf == NULL) {
3252                 rc = -ENOMEM;
3253                 goto error_free;
3254         }
3255         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3256                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3257         for (i = 0; i < num_vfs; i++)
3258                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3259                                         (i * HWRM_MAX_REQ_LEN);
3260
3261         rc = bnxt_hwrm_func_buf_rgtr(bp);
3262         if (rc)
3263                 goto error_free;
3264
3265         populate_vf_func_cfg_req(bp, &req, num_vfs);
3266
3267         bp->pf.active_vfs = 0;
3268         for (i = 0; i < num_vfs; i++) {
3269                 add_random_mac_if_needed(bp, &req, i);
3270
3271                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3272                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3273                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3274                 rc = bnxt_hwrm_send_message(bp,
3275                                             &req,
3276                                             sizeof(req),
3277                                             BNXT_USE_CHIMP_MB);
3278
3279                 /* Clear enable flag for next pass */
3280                 req.enables &= ~rte_cpu_to_le_32(
3281                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3282
3283                 if (rc || resp->error_code) {
3284                         PMD_DRV_LOG(ERR,
3285                                 "Failed to initizlie VF %d\n", i);
3286                         PMD_DRV_LOG(ERR,
3287                                 "Not all VFs available. (%d, %d)\n",
3288                                 rc, resp->error_code);
3289                         HWRM_UNLOCK();
3290                         break;
3291                 }
3292
3293                 HWRM_UNLOCK();
3294
3295                 reserve_resources_from_vf(bp, &req, i);
3296                 bp->pf.active_vfs++;
3297                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3298         }
3299
3300         /*
3301          * Now configure the PF to use "the rest" of the resources
3302          * We're using STD_TX_RING_MODE here though which will limit the TX
3303          * rings.  This will allow QoS to function properly.  Not setting this
3304          * will cause PF rings to break bandwidth settings.
3305          */
3306         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3307         if (rc)
3308                 goto error_free;
3309
3310         rc = update_pf_resource_max(bp);
3311         if (rc)
3312                 goto error_free;
3313
3314         return rc;
3315
3316 error_free:
3317         bnxt_hwrm_func_buf_unrgtr(bp);
3318         return rc;
3319 }
3320
3321 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3322 {
3323         struct hwrm_func_cfg_input req = {0};
3324         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3325         int rc;
3326
3327         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3328
3329         req.fid = rte_cpu_to_le_16(0xffff);
3330         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3331         req.evb_mode = bp->pf.evb_mode;
3332
3333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3334         HWRM_CHECK_RESULT();
3335         HWRM_UNLOCK();
3336
3337         return rc;
3338 }
3339
3340 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3341                                 uint8_t tunnel_type)
3342 {
3343         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3344         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3345         int rc = 0;
3346
3347         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3348         req.tunnel_type = tunnel_type;
3349         req.tunnel_dst_port_val = port;
3350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3351         HWRM_CHECK_RESULT();
3352
3353         switch (tunnel_type) {
3354         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3355                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3356                 bp->vxlan_port = port;
3357                 break;
3358         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3359                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3360                 bp->geneve_port = port;
3361                 break;
3362         default:
3363                 break;
3364         }
3365
3366         HWRM_UNLOCK();
3367
3368         return rc;
3369 }
3370
3371 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3372                                 uint8_t tunnel_type)
3373 {
3374         struct hwrm_tunnel_dst_port_free_input req = {0};
3375         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3376         int rc = 0;
3377
3378         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3379
3380         req.tunnel_type = tunnel_type;
3381         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3382         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3383
3384         HWRM_CHECK_RESULT();
3385         HWRM_UNLOCK();
3386
3387         return rc;
3388 }
3389
3390 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3391                                         uint32_t flags)
3392 {
3393         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3394         struct hwrm_func_cfg_input req = {0};
3395         int rc;
3396
3397         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3398
3399         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3400         req.flags = rte_cpu_to_le_32(flags);
3401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3402
3403         HWRM_CHECK_RESULT();
3404         HWRM_UNLOCK();
3405
3406         return rc;
3407 }
3408
3409 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3410 {
3411         uint32_t *flag = flagp;
3412
3413         vnic->flags = *flag;
3414 }
3415
3416 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3417 {
3418         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3419 }
3420
3421 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3422 {
3423         int rc = 0;
3424         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3425         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3426
3427         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3428
3429         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3430         req.req_buf_page_size = rte_cpu_to_le_16(
3431                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3432         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3433         req.req_buf_page_addr0 =
3434                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3435         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3436                 PMD_DRV_LOG(ERR,
3437                         "unable to map buffer address to physical memory\n");
3438                 return -ENOMEM;
3439         }
3440
3441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3442
3443         HWRM_CHECK_RESULT();
3444         HWRM_UNLOCK();
3445
3446         return rc;
3447 }
3448
3449 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3450 {
3451         int rc = 0;
3452         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3453         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3454
3455         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3456                 return 0;
3457
3458         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3459
3460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3461
3462         HWRM_CHECK_RESULT();
3463         HWRM_UNLOCK();
3464
3465         return rc;
3466 }
3467
3468 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3469 {
3470         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3471         struct hwrm_func_cfg_input req = {0};
3472         int rc;
3473
3474         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3475
3476         req.fid = rte_cpu_to_le_16(0xffff);
3477         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3478         req.enables = rte_cpu_to_le_32(
3479                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3480         req.async_event_cr = rte_cpu_to_le_16(
3481                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3483
3484         HWRM_CHECK_RESULT();
3485         HWRM_UNLOCK();
3486
3487         return rc;
3488 }
3489
3490 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3491 {
3492         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3493         struct hwrm_func_vf_cfg_input req = {0};
3494         int rc;
3495
3496         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3497
3498         req.enables = rte_cpu_to_le_32(
3499                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3500         req.async_event_cr = rte_cpu_to_le_16(
3501                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3503
3504         HWRM_CHECK_RESULT();
3505         HWRM_UNLOCK();
3506
3507         return rc;
3508 }
3509
3510 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3511 {
3512         struct hwrm_func_cfg_input req = {0};
3513         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3514         uint16_t dflt_vlan, fid;
3515         uint32_t func_cfg_flags;
3516         int rc = 0;
3517
3518         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3519
3520         if (is_vf) {
3521                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3522                 fid = bp->pf.vf_info[vf].fid;
3523                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3524         } else {
3525                 fid = rte_cpu_to_le_16(0xffff);
3526                 func_cfg_flags = bp->pf.func_cfg_flags;
3527                 dflt_vlan = bp->vlan;
3528         }
3529
3530         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3531         req.fid = rte_cpu_to_le_16(fid);
3532         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3533         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3534
3535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3536
3537         HWRM_CHECK_RESULT();
3538         HWRM_UNLOCK();
3539
3540         return rc;
3541 }
3542
3543 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3544                         uint16_t max_bw, uint16_t enables)
3545 {
3546         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3547         struct hwrm_func_cfg_input req = {0};
3548         int rc;
3549
3550         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3551
3552         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3553         req.enables |= rte_cpu_to_le_32(enables);
3554         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3555         req.max_bw = rte_cpu_to_le_32(max_bw);
3556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3557
3558         HWRM_CHECK_RESULT();
3559         HWRM_UNLOCK();
3560
3561         return rc;
3562 }
3563
3564 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3565 {
3566         struct hwrm_func_cfg_input req = {0};
3567         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3568         int rc = 0;
3569
3570         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3571
3572         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3573         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3574         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3575         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3576
3577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3578
3579         HWRM_CHECK_RESULT();
3580         HWRM_UNLOCK();
3581
3582         return rc;
3583 }
3584
3585 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3586 {
3587         int rc;
3588
3589         if (BNXT_PF(bp))
3590                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3591         else
3592                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3593
3594         return rc;
3595 }
3596
3597 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3598                               void *encaped, size_t ec_size)
3599 {
3600         int rc = 0;
3601         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3602         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3603
3604         if (ec_size > sizeof(req.encap_request))
3605                 return -1;
3606
3607         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3608
3609         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3610         memcpy(req.encap_request, encaped, ec_size);
3611
3612         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3613
3614         HWRM_CHECK_RESULT();
3615         HWRM_UNLOCK();
3616
3617         return rc;
3618 }
3619
3620 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3621                                        struct rte_ether_addr *mac)
3622 {
3623         struct hwrm_func_qcfg_input req = {0};
3624         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3625         int rc;
3626
3627         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3628
3629         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3631
3632         HWRM_CHECK_RESULT();
3633
3634         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3635
3636         HWRM_UNLOCK();
3637
3638         return rc;
3639 }
3640
3641 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3642                             void *encaped, size_t ec_size)
3643 {
3644         int rc = 0;
3645         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3646         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3647
3648         if (ec_size > sizeof(req.encap_request))
3649                 return -1;
3650
3651         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3652
3653         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3654         memcpy(req.encap_request, encaped, ec_size);
3655
3656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3657
3658         HWRM_CHECK_RESULT();
3659         HWRM_UNLOCK();
3660
3661         return rc;
3662 }
3663
3664 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3665                          struct rte_eth_stats *stats, uint8_t rx)
3666 {
3667         int rc = 0;
3668         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3669         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3670
3671         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3672
3673         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3674
3675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3676
3677         HWRM_CHECK_RESULT();
3678
3679         if (rx) {
3680                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3681                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3682                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3683                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3684                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3685                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3686                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3687                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3688         } else {
3689                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3690                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3691                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3692                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3693                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3694                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3695         }
3696
3697         HWRM_UNLOCK();
3698
3699         return rc;
3700 }
3701
3702 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3703 {
3704         struct hwrm_port_qstats_input req = {0};
3705         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3706         struct bnxt_pf_info *pf = &bp->pf;
3707         int rc;
3708
3709         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3710
3711         req.port_id = rte_cpu_to_le_16(pf->port_id);
3712         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3713         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3715
3716         HWRM_CHECK_RESULT();
3717         HWRM_UNLOCK();
3718
3719         return rc;
3720 }
3721
3722 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3723 {
3724         struct hwrm_port_clr_stats_input req = {0};
3725         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3726         struct bnxt_pf_info *pf = &bp->pf;
3727         int rc;
3728
3729         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3730         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3731             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3732                 return 0;
3733
3734         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3735
3736         req.port_id = rte_cpu_to_le_16(pf->port_id);
3737         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3738
3739         HWRM_CHECK_RESULT();
3740         HWRM_UNLOCK();
3741
3742         return rc;
3743 }
3744
3745 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3746 {
3747         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3748         struct hwrm_port_led_qcaps_input req = {0};
3749         int rc;
3750
3751         if (BNXT_VF(bp))
3752                 return 0;
3753
3754         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3755         req.port_id = bp->pf.port_id;
3756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3757
3758         HWRM_CHECK_RESULT();
3759
3760         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3761                 unsigned int i;
3762
3763                 bp->num_leds = resp->num_leds;
3764                 memcpy(bp->leds, &resp->led0_id,
3765                         sizeof(bp->leds[0]) * bp->num_leds);
3766                 for (i = 0; i < bp->num_leds; i++) {
3767                         struct bnxt_led_info *led = &bp->leds[i];
3768
3769                         uint16_t caps = led->led_state_caps;
3770
3771                         if (!led->led_group_id ||
3772                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3773                                 bp->num_leds = 0;
3774                                 break;
3775                         }
3776                 }
3777         }
3778
3779         HWRM_UNLOCK();
3780
3781         return rc;
3782 }
3783
3784 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3785 {
3786         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3787         struct hwrm_port_led_cfg_input req = {0};
3788         struct bnxt_led_cfg *led_cfg;
3789         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3790         uint16_t duration = 0;
3791         int rc, i;
3792
3793         if (!bp->num_leds || BNXT_VF(bp))
3794                 return -EOPNOTSUPP;
3795
3796         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3797
3798         if (led_on) {
3799                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3800                 duration = rte_cpu_to_le_16(500);
3801         }
3802         req.port_id = bp->pf.port_id;
3803         req.num_leds = bp->num_leds;
3804         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3805         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3806                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3807                 led_cfg->led_id = bp->leds[i].led_id;
3808                 led_cfg->led_state = led_state;
3809                 led_cfg->led_blink_on = duration;
3810                 led_cfg->led_blink_off = duration;
3811                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3812         }
3813
3814         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3815
3816         HWRM_CHECK_RESULT();
3817         HWRM_UNLOCK();
3818
3819         return rc;
3820 }
3821
3822 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3823                                uint32_t *length)
3824 {
3825         int rc;
3826         struct hwrm_nvm_get_dir_info_input req = {0};
3827         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3828
3829         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3830
3831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3832
3833         HWRM_CHECK_RESULT();
3834
3835         *entries = rte_le_to_cpu_32(resp->entries);
3836         *length = rte_le_to_cpu_32(resp->entry_length);
3837
3838         HWRM_UNLOCK();
3839         return rc;
3840 }
3841
3842 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3843 {
3844         int rc;
3845         uint32_t dir_entries;
3846         uint32_t entry_length;
3847         uint8_t *buf;
3848         size_t buflen;
3849         rte_iova_t dma_handle;
3850         struct hwrm_nvm_get_dir_entries_input req = {0};
3851         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3852
3853         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3854         if (rc != 0)
3855                 return rc;
3856
3857         *data++ = dir_entries;
3858         *data++ = entry_length;
3859         len -= 2;
3860         memset(data, 0xff, len);
3861
3862         buflen = dir_entries * entry_length;
3863         buf = rte_malloc("nvm_dir", buflen, 0);
3864         if (buf == NULL)
3865                 return -ENOMEM;
3866         dma_handle = rte_malloc_virt2iova(buf);
3867         if (dma_handle == RTE_BAD_IOVA) {
3868                 PMD_DRV_LOG(ERR,
3869                         "unable to map response address to physical memory\n");
3870                 return -ENOMEM;
3871         }
3872         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3873         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3874         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3875
3876         if (rc == 0)
3877                 memcpy(data, buf, len > buflen ? buflen : len);
3878
3879         rte_free(buf);
3880         HWRM_CHECK_RESULT();
3881         HWRM_UNLOCK();
3882
3883         return rc;
3884 }
3885
3886 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3887                              uint32_t offset, uint32_t length,
3888                              uint8_t *data)
3889 {
3890         int rc;
3891         uint8_t *buf;
3892         rte_iova_t dma_handle;
3893         struct hwrm_nvm_read_input req = {0};
3894         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3895
3896         buf = rte_malloc("nvm_item", length, 0);
3897         if (!buf)
3898                 return -ENOMEM;
3899
3900         dma_handle = rte_malloc_virt2iova(buf);
3901         if (dma_handle == RTE_BAD_IOVA) {
3902                 PMD_DRV_LOG(ERR,
3903                         "unable to map response address to physical memory\n");
3904                 return -ENOMEM;
3905         }
3906         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3907         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3908         req.dir_idx = rte_cpu_to_le_16(index);
3909         req.offset = rte_cpu_to_le_32(offset);
3910         req.len = rte_cpu_to_le_32(length);
3911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3912         if (rc == 0)
3913                 memcpy(data, buf, length);
3914
3915         rte_free(buf);
3916         HWRM_CHECK_RESULT();
3917         HWRM_UNLOCK();
3918
3919         return rc;
3920 }
3921
3922 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3923 {
3924         int rc;
3925         struct hwrm_nvm_erase_dir_entry_input req = {0};
3926         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3927
3928         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3929         req.dir_idx = rte_cpu_to_le_16(index);
3930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3931         HWRM_CHECK_RESULT();
3932         HWRM_UNLOCK();
3933
3934         return rc;
3935 }
3936
3937
3938 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3939                           uint16_t dir_ordinal, uint16_t dir_ext,
3940                           uint16_t dir_attr, const uint8_t *data,
3941                           size_t data_len)
3942 {
3943         int rc;
3944         struct hwrm_nvm_write_input req = {0};
3945         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3946         rte_iova_t dma_handle;
3947         uint8_t *buf;
3948
3949         buf = rte_malloc("nvm_write", data_len, 0);
3950         if (!buf)
3951                 return -ENOMEM;
3952
3953         dma_handle = rte_malloc_virt2iova(buf);
3954         if (dma_handle == RTE_BAD_IOVA) {
3955                 PMD_DRV_LOG(ERR,
3956                         "unable to map response address to physical memory\n");
3957                 return -ENOMEM;
3958         }
3959         memcpy(buf, data, data_len);
3960
3961         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3962
3963         req.dir_type = rte_cpu_to_le_16(dir_type);
3964         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3965         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3966         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3967         req.dir_data_length = rte_cpu_to_le_32(data_len);
3968         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3969
3970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3971
3972         rte_free(buf);
3973         HWRM_CHECK_RESULT();
3974         HWRM_UNLOCK();
3975
3976         return rc;
3977 }
3978
3979 static void
3980 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3981 {
3982         uint32_t *count = cbdata;
3983
3984         *count = *count + 1;
3985 }
3986
3987 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3988                                      struct bnxt_vnic_info *vnic __rte_unused)
3989 {
3990         return 0;
3991 }
3992
3993 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3994 {
3995         uint32_t count = 0;
3996
3997         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3998             &count, bnxt_vnic_count_hwrm_stub);
3999
4000         return count;
4001 }
4002
4003 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4004                                         uint16_t *vnic_ids)
4005 {
4006         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4007         struct hwrm_func_vf_vnic_ids_query_output *resp =
4008                                                 bp->hwrm_cmd_resp_addr;
4009         int rc;
4010
4011         /* First query all VNIC ids */
4012         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4013
4014         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4015         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4016         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4017
4018         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4019                 HWRM_UNLOCK();
4020                 PMD_DRV_LOG(ERR,
4021                 "unable to map VNIC ID table address to physical memory\n");
4022                 return -ENOMEM;
4023         }
4024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4025         HWRM_CHECK_RESULT();
4026         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4027
4028         HWRM_UNLOCK();
4029
4030         return rc;
4031 }
4032
4033 /*
4034  * This function queries the VNIC IDs  for a specified VF. It then calls
4035  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4036  * Then it calls the hwrm_cb function to program this new vnic configuration.
4037  */
4038 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4039         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4040         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4041 {
4042         struct bnxt_vnic_info vnic;
4043         int rc = 0;
4044         int i, num_vnic_ids;
4045         uint16_t *vnic_ids;
4046         size_t vnic_id_sz;
4047         size_t sz;
4048
4049         /* First query all VNIC ids */
4050         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4051         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4052                         RTE_CACHE_LINE_SIZE);
4053         if (vnic_ids == NULL)
4054                 return -ENOMEM;
4055
4056         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4057                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4058
4059         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4060
4061         if (num_vnic_ids < 0)
4062                 return num_vnic_ids;
4063
4064         /* Retrieve VNIC, update bd_stall then update */
4065
4066         for (i = 0; i < num_vnic_ids; i++) {
4067                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4068                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4069                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4070                 if (rc)
4071                         break;
4072                 if (vnic.mru <= 4)      /* Indicates unallocated */
4073                         continue;
4074
4075                 vnic_cb(&vnic, cbdata);
4076
4077                 rc = hwrm_cb(bp, &vnic);
4078                 if (rc)
4079                         break;
4080         }
4081
4082         rte_free(vnic_ids);
4083
4084         return rc;
4085 }
4086
4087 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4088                                               bool on)
4089 {
4090         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4091         struct hwrm_func_cfg_input req = {0};
4092         int rc;
4093
4094         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4095
4096         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4097         req.enables |= rte_cpu_to_le_32(
4098                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4099         req.vlan_antispoof_mode = on ?
4100                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4101                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4103
4104         HWRM_CHECK_RESULT();
4105         HWRM_UNLOCK();
4106
4107         return rc;
4108 }
4109
4110 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4111 {
4112         struct bnxt_vnic_info vnic;
4113         uint16_t *vnic_ids;
4114         size_t vnic_id_sz;
4115         int num_vnic_ids, i;
4116         size_t sz;
4117         int rc;
4118
4119         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4120         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4121                         RTE_CACHE_LINE_SIZE);
4122         if (vnic_ids == NULL)
4123                 return -ENOMEM;
4124
4125         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4126                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4127
4128         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4129         if (rc <= 0)
4130                 goto exit;
4131         num_vnic_ids = rc;
4132
4133         /*
4134          * Loop through to find the default VNIC ID.
4135          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4136          * by sending the hwrm_func_qcfg command to the firmware.
4137          */
4138         for (i = 0; i < num_vnic_ids; i++) {
4139                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4140                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4141                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4142                                         bp->pf.first_vf_id + vf);
4143                 if (rc)
4144                         goto exit;
4145                 if (vnic.func_default) {
4146                         rte_free(vnic_ids);
4147                         return vnic.fw_vnic_id;
4148                 }
4149         }
4150         /* Could not find a default VNIC. */
4151         PMD_DRV_LOG(ERR, "No default VNIC\n");
4152 exit:
4153         rte_free(vnic_ids);
4154         return rc;
4155 }
4156
4157 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4158                          uint16_t dst_id,
4159                          struct bnxt_filter_info *filter)
4160 {
4161         int rc = 0;
4162         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4163         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4164         uint32_t enables = 0;
4165
4166         if (filter->fw_em_filter_id != UINT64_MAX)
4167                 bnxt_hwrm_clear_em_filter(bp, filter);
4168
4169         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4170
4171         req.flags = rte_cpu_to_le_32(filter->flags);
4172
4173         enables = filter->enables |
4174               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4175         req.dst_id = rte_cpu_to_le_16(dst_id);
4176
4177         if (filter->ip_addr_type) {
4178                 req.ip_addr_type = filter->ip_addr_type;
4179                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4180         }
4181         if (enables &
4182             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4183                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4184         if (enables &
4185             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4186                 memcpy(req.src_macaddr, filter->src_macaddr,
4187                        RTE_ETHER_ADDR_LEN);
4188         if (enables &
4189             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4190                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4191                        RTE_ETHER_ADDR_LEN);
4192         if (enables &
4193             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4194                 req.ovlan_vid = filter->l2_ovlan;
4195         if (enables &
4196             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4197                 req.ivlan_vid = filter->l2_ivlan;
4198         if (enables &
4199             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4200                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4201         if (enables &
4202             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4203                 req.ip_protocol = filter->ip_protocol;
4204         if (enables &
4205             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4206                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4207         if (enables &
4208             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4209                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4210         if (enables &
4211             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4212                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4213         if (enables &
4214             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4215                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4216         if (enables &
4217             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4218                 req.mirror_vnic_id = filter->mirror_vnic_id;
4219
4220         req.enables = rte_cpu_to_le_32(enables);
4221
4222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4223
4224         HWRM_CHECK_RESULT();
4225
4226         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4227         HWRM_UNLOCK();
4228
4229         return rc;
4230 }
4231
4232 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4233 {
4234         int rc = 0;
4235         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4236         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4237
4238         if (filter->fw_em_filter_id == UINT64_MAX)
4239                 return 0;
4240
4241         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4242
4243         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4244
4245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4246
4247         HWRM_CHECK_RESULT();
4248         HWRM_UNLOCK();
4249
4250         filter->fw_em_filter_id = UINT64_MAX;
4251         filter->fw_l2_filter_id = UINT64_MAX;
4252
4253         return 0;
4254 }
4255
4256 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4257                          uint16_t dst_id,
4258                          struct bnxt_filter_info *filter)
4259 {
4260         int rc = 0;
4261         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4262         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4263                                                 bp->hwrm_cmd_resp_addr;
4264         uint32_t enables = 0;
4265
4266         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4267                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4268
4269         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4270
4271         req.flags = rte_cpu_to_le_32(filter->flags);
4272
4273         enables = filter->enables |
4274               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4275         req.dst_id = rte_cpu_to_le_16(dst_id);
4276
4277         if (filter->ip_addr_type) {
4278                 req.ip_addr_type = filter->ip_addr_type;
4279                 enables |=
4280                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4281         }
4282         if (enables &
4283             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4284                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4285         if (enables &
4286             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4287                 memcpy(req.src_macaddr, filter->src_macaddr,
4288                        RTE_ETHER_ADDR_LEN);
4289         if (enables &
4290             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4291                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4292         if (enables &
4293             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4294                 req.ip_protocol = filter->ip_protocol;
4295         if (enables &
4296             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4297                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4298         if (enables &
4299             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4300                 req.src_ipaddr_mask[0] =
4301                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4302         if (enables &
4303             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4304                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4305         if (enables &
4306             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4307                 req.dst_ipaddr_mask[0] =
4308                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4309         if (enables &
4310             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4311                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4312         if (enables &
4313             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4314                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4315         if (enables &
4316             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4317                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4318         if (enables &
4319             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4320                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4321         if (enables &
4322             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4323                 req.mirror_vnic_id = filter->mirror_vnic_id;
4324
4325         req.enables = rte_cpu_to_le_32(enables);
4326
4327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4328
4329         HWRM_CHECK_RESULT();
4330
4331         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4332         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4333         HWRM_UNLOCK();
4334
4335         return rc;
4336 }
4337
4338 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4339                                 struct bnxt_filter_info *filter)
4340 {
4341         int rc = 0;
4342         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4343         struct hwrm_cfa_ntuple_filter_free_output *resp =
4344                                                 bp->hwrm_cmd_resp_addr;
4345
4346         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4347                 return 0;
4348
4349         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4350
4351         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4352
4353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4354
4355         HWRM_CHECK_RESULT();
4356         HWRM_UNLOCK();
4357
4358         filter->fw_ntuple_filter_id = UINT64_MAX;
4359
4360         return 0;
4361 }
4362
4363 static int
4364 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4365 {
4366         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4367         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4368         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4369         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4370         uint16_t *ring_tbl = vnic->rss_table;
4371         int nr_ctxs = vnic->num_lb_ctxts;
4372         int max_rings = bp->rx_nr_rings;
4373         int i, j, k, cnt;
4374         int rc = 0;
4375
4376         for (i = 0, k = 0; i < nr_ctxs; i++) {
4377                 struct bnxt_rx_ring_info *rxr;
4378                 struct bnxt_cp_ring_info *cpr;
4379
4380                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4381
4382                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4383                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4384                 req.hash_mode_flags = vnic->hash_mode;
4385
4386                 req.ring_grp_tbl_addr =
4387                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4388                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4389                                      2 * sizeof(*ring_tbl));
4390                 req.hash_key_tbl_addr =
4391                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4392
4393                 req.ring_table_pair_index = i;
4394                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4395
4396                 for (j = 0; j < 64; j++) {
4397                         uint16_t ring_id;
4398
4399                         /* Find next active ring. */
4400                         for (cnt = 0; cnt < max_rings; cnt++) {
4401                                 if (rx_queue_state[k] !=
4402                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4403                                         break;
4404                                 if (++k == max_rings)
4405                                         k = 0;
4406                         }
4407
4408                         /* Return if no rings are active. */
4409                         if (cnt == max_rings) {
4410                                 HWRM_UNLOCK();
4411                                 return 0;
4412                         }
4413
4414                         /* Add rx/cp ring pair to RSS table. */
4415                         rxr = rxqs[k]->rx_ring;
4416                         cpr = rxqs[k]->cp_ring;
4417
4418                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4419                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4420                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4421                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4422
4423                         if (++k == max_rings)
4424                                 k = 0;
4425                 }
4426                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4427                                             BNXT_USE_CHIMP_MB);
4428
4429                 HWRM_CHECK_RESULT();
4430                 HWRM_UNLOCK();
4431         }
4432
4433         return rc;
4434 }
4435
4436 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4437 {
4438         unsigned int rss_idx, fw_idx, i;
4439
4440         if (!(vnic->rss_table && vnic->hash_type))
4441                 return 0;
4442
4443         if (BNXT_CHIP_THOR(bp))
4444                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4445
4446         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4447                 return 0;
4448
4449         if (vnic->rss_table && vnic->hash_type) {
4450                 /*
4451                  * Fill the RSS hash & redirection table with
4452                  * ring group ids for all VNICs
4453                  */
4454                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4455                         rss_idx++, fw_idx++) {
4456                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4457                                 fw_idx %= bp->rx_cp_nr_rings;
4458                                 if (vnic->fw_grp_ids[fw_idx] !=
4459                                     INVALID_HW_RING_ID)
4460                                         break;
4461                                 fw_idx++;
4462                         }
4463                         if (i == bp->rx_cp_nr_rings)
4464                                 return 0;
4465                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4466                 }
4467                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4468         }
4469
4470         return 0;
4471 }
4472
4473 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4474         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4475 {
4476         uint16_t flags;
4477
4478         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4479
4480         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4481         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4482
4483         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4484         req->num_cmpl_dma_aggr_during_int =
4485                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4486
4487         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4488
4489         /* min timer set to 1/2 of interrupt timer */
4490         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4491
4492         /* buf timer set to 1/4 of interrupt timer */
4493         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4494
4495         req->cmpl_aggr_dma_tmr_during_int =
4496                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4497
4498         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4499                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4500         req->flags = rte_cpu_to_le_16(flags);
4501 }
4502
4503 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4504                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4505 {
4506         struct hwrm_ring_aggint_qcaps_input req = {0};
4507         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4508         uint32_t enables;
4509         uint16_t flags;
4510         int rc;
4511
4512         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4513         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4514         HWRM_CHECK_RESULT();
4515
4516         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4517         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4518
4519         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4520                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4521         agg_req->flags = rte_cpu_to_le_16(flags);
4522         enables =
4523          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4524          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4525         agg_req->enables = rte_cpu_to_le_32(enables);
4526
4527         HWRM_UNLOCK();
4528         return rc;
4529 }
4530
4531 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4532                         struct bnxt_coal *coal, uint16_t ring_id)
4533 {
4534         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4535         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4536                                                 bp->hwrm_cmd_resp_addr;
4537         int rc;
4538
4539         /* Set ring coalesce parameters only for 100G NICs */
4540         if (BNXT_CHIP_THOR(bp)) {
4541                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4542                         return -1;
4543         } else if (bnxt_stratus_device(bp)) {
4544                 bnxt_hwrm_set_coal_params(coal, &req);
4545         } else {
4546                 return 0;
4547         }
4548
4549         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4550         req.ring_id = rte_cpu_to_le_16(ring_id);
4551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4552         HWRM_CHECK_RESULT();
4553         HWRM_UNLOCK();
4554         return 0;
4555 }
4556
4557 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4558 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4559 {
4560         struct hwrm_func_backing_store_qcaps_input req = {0};
4561         struct hwrm_func_backing_store_qcaps_output *resp =
4562                 bp->hwrm_cmd_resp_addr;
4563         struct bnxt_ctx_pg_info *ctx_pg;
4564         struct bnxt_ctx_mem_info *ctx;
4565         int total_alloc_len;
4566         int rc, i;
4567
4568         if (!BNXT_CHIP_THOR(bp) ||
4569             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4570             BNXT_VF(bp) ||
4571             bp->ctx)
4572                 return 0;
4573
4574         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4575         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4576         HWRM_CHECK_RESULT_SILENT();
4577
4578         total_alloc_len = sizeof(*ctx);
4579         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4580                           RTE_CACHE_LINE_SIZE);
4581         if (!ctx) {
4582                 rc = -ENOMEM;
4583                 goto ctx_err;
4584         }
4585
4586         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4587                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4588                             RTE_CACHE_LINE_SIZE);
4589         if (!ctx_pg) {
4590                 rc = -ENOMEM;
4591                 goto ctx_err;
4592         }
4593         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4594                 ctx->tqm_mem[i] = ctx_pg;
4595
4596         bp->ctx = ctx;
4597         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4598         ctx->qp_min_qp1_entries =
4599                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4600         ctx->qp_max_l2_entries =
4601                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4602         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4603         ctx->srq_max_l2_entries =
4604                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4605         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4606         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4607         ctx->cq_max_l2_entries =
4608                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4609         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4610         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4611         ctx->vnic_max_vnic_entries =
4612                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4613         ctx->vnic_max_ring_table_entries =
4614                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4615         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4616         ctx->stat_max_entries =
4617                 rte_le_to_cpu_32(resp->stat_max_entries);
4618         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4619         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4620         ctx->tqm_min_entries_per_ring =
4621                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4622         ctx->tqm_max_entries_per_ring =
4623                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4624         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4625         if (!ctx->tqm_entries_multiple)
4626                 ctx->tqm_entries_multiple = 1;
4627         ctx->mrav_max_entries =
4628                 rte_le_to_cpu_32(resp->mrav_max_entries);
4629         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4630         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4631         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4632 ctx_err:
4633         HWRM_UNLOCK();
4634         return rc;
4635 }
4636
4637 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4638 {
4639         struct hwrm_func_backing_store_cfg_input req = {0};
4640         struct hwrm_func_backing_store_cfg_output *resp =
4641                 bp->hwrm_cmd_resp_addr;
4642         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4643         struct bnxt_ctx_pg_info *ctx_pg;
4644         uint32_t *num_entries;
4645         uint64_t *pg_dir;
4646         uint8_t *pg_attr;
4647         uint32_t ena;
4648         int i, rc;
4649
4650         if (!ctx)
4651                 return 0;
4652
4653         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4654         req.enables = rte_cpu_to_le_32(enables);
4655
4656         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4657                 ctx_pg = &ctx->qp_mem;
4658                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4659                 req.qp_num_qp1_entries =
4660                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4661                 req.qp_num_l2_entries =
4662                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4663                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4664                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4665                                       &req.qpc_pg_size_qpc_lvl,
4666                                       &req.qpc_page_dir);
4667         }
4668
4669         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4670                 ctx_pg = &ctx->srq_mem;
4671                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4672                 req.srq_num_l2_entries =
4673                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4674                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4675                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4676                                       &req.srq_pg_size_srq_lvl,
4677                                       &req.srq_page_dir);
4678         }
4679
4680         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4681                 ctx_pg = &ctx->cq_mem;
4682                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4683                 req.cq_num_l2_entries =
4684                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4685                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4686                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4687                                       &req.cq_pg_size_cq_lvl,
4688                                       &req.cq_page_dir);
4689         }
4690
4691         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4692                 ctx_pg = &ctx->vnic_mem;
4693                 req.vnic_num_vnic_entries =
4694                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4695                 req.vnic_num_ring_table_entries =
4696                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4697                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4698                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4699                                       &req.vnic_pg_size_vnic_lvl,
4700                                       &req.vnic_page_dir);
4701         }
4702
4703         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4704                 ctx_pg = &ctx->stat_mem;
4705                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4706                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4707                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4708                                       &req.stat_pg_size_stat_lvl,
4709                                       &req.stat_page_dir);
4710         }
4711
4712         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4713         num_entries = &req.tqm_sp_num_entries;
4714         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4715         pg_dir = &req.tqm_sp_page_dir;
4716         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4717         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4718                 if (!(enables & ena))
4719                         continue;
4720
4721                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4722
4723                 ctx_pg = ctx->tqm_mem[i];
4724                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4725                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4726         }
4727
4728         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4729         HWRM_CHECK_RESULT();
4730         HWRM_UNLOCK();
4731
4732         return rc;
4733 }
4734
4735 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4736 {
4737         struct hwrm_port_qstats_ext_input req = {0};
4738         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4739         struct bnxt_pf_info *pf = &bp->pf;
4740         int rc;
4741
4742         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4743               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4744                 return 0;
4745
4746         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4747
4748         req.port_id = rte_cpu_to_le_16(pf->port_id);
4749         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4750                 req.tx_stat_host_addr =
4751                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4752                 req.tx_stat_size =
4753                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4754         }
4755         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4756                 req.rx_stat_host_addr =
4757                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4758                 req.rx_stat_size =
4759                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4760         }
4761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4762
4763         if (rc) {
4764                 bp->fw_rx_port_stats_ext_size = 0;
4765                 bp->fw_tx_port_stats_ext_size = 0;
4766         } else {
4767                 bp->fw_rx_port_stats_ext_size =
4768                         rte_le_to_cpu_16(resp->rx_stat_size);
4769                 bp->fw_tx_port_stats_ext_size =
4770                         rte_le_to_cpu_16(resp->tx_stat_size);
4771         }
4772
4773         HWRM_CHECK_RESULT();
4774         HWRM_UNLOCK();
4775
4776         return rc;
4777 }
4778
4779 int
4780 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4781 {
4782         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4783         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4784                 bp->hwrm_cmd_resp_addr;
4785         int rc = 0;
4786
4787         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4788         req.tunnel_type = type;
4789         req.dest_fid = bp->fw_fid;
4790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4791         HWRM_CHECK_RESULT();
4792
4793         HWRM_UNLOCK();
4794
4795         return rc;
4796 }
4797
4798 int
4799 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4800 {
4801         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4802         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4803                 bp->hwrm_cmd_resp_addr;
4804         int rc = 0;
4805
4806         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4807         req.tunnel_type = type;
4808         req.dest_fid = bp->fw_fid;
4809         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4810         HWRM_CHECK_RESULT();
4811
4812         HWRM_UNLOCK();
4813
4814         return rc;
4815 }
4816
4817 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4818 {
4819         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4820         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4821                 bp->hwrm_cmd_resp_addr;
4822         int rc = 0;
4823
4824         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4825         req.src_fid = bp->fw_fid;
4826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4827         HWRM_CHECK_RESULT();
4828
4829         if (type)
4830                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4831
4832         HWRM_UNLOCK();
4833
4834         return rc;
4835 }
4836
4837 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4838                                    uint16_t *dst_fid)
4839 {
4840         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4841         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4842                 bp->hwrm_cmd_resp_addr;
4843         int rc = 0;
4844
4845         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4846         req.src_fid = bp->fw_fid;
4847         req.tunnel_type = tun_type;
4848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4849         HWRM_CHECK_RESULT();
4850
4851         if (dst_fid)
4852                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4853
4854         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4855
4856         HWRM_UNLOCK();
4857
4858         return rc;
4859 }
4860
4861 int bnxt_hwrm_set_mac(struct bnxt *bp)
4862 {
4863         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4864         struct hwrm_func_vf_cfg_input req = {0};
4865         int rc = 0;
4866
4867         if (!BNXT_VF(bp))
4868                 return 0;
4869
4870         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4871
4872         req.enables =
4873                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4874         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4875
4876         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4877
4878         HWRM_CHECK_RESULT();
4879
4880         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4881         HWRM_UNLOCK();
4882
4883         return rc;
4884 }
4885
4886 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4887 {
4888         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4889         struct hwrm_func_drv_if_change_input req = {0};
4890         uint32_t flags;
4891         int rc;
4892
4893         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4894                 return 0;
4895
4896         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4897          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4898          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4899          */
4900         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4901                 return 0;
4902
4903         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4904
4905         if (up)
4906                 req.flags =
4907                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4908
4909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4910
4911         HWRM_CHECK_RESULT();
4912         flags = rte_le_to_cpu_32(resp->flags);
4913         HWRM_UNLOCK();
4914
4915         if (!up)
4916                 return 0;
4917
4918         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4919                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4920                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4921         }
4922
4923         return 0;
4924 }
4925
4926 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4927 {
4928         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4929         struct bnxt_error_recovery_info *info = bp->recovery_info;
4930         struct hwrm_error_recovery_qcfg_input req = {0};
4931         uint32_t flags = 0;
4932         unsigned int i;
4933         int rc;
4934
4935         /* Older FW does not have error recovery support */
4936         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4937                 return 0;
4938
4939         if (!info) {
4940                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4941                                    sizeof(*info), 0);
4942                 bp->recovery_info = info;
4943                 if (info == NULL)
4944                         return -ENOMEM;
4945         } else {
4946                 memset(info, 0, sizeof(*info));
4947         }
4948
4949         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4950
4951         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4952
4953         HWRM_CHECK_RESULT();
4954
4955         flags = rte_le_to_cpu_32(resp->flags);
4956         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4957                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4958         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4959                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4960
4961         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4962             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4963                 rc = -EINVAL;
4964                 goto err;
4965         }
4966
4967         /* FW returned values are in units of 100msec */
4968         info->driver_polling_freq =
4969                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4970         info->master_func_wait_period =
4971                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4972         info->normal_func_wait_period =
4973                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4974         info->master_func_wait_period_after_reset =
4975                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4976         info->max_bailout_time_after_reset =
4977                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4978         info->status_regs[BNXT_FW_STATUS_REG] =
4979                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4980         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4981                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4982         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4983                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4984         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4985                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4986         info->reg_array_cnt =
4987                 rte_le_to_cpu_32(resp->reg_array_cnt);
4988
4989         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4990                 rc = -EINVAL;
4991                 goto err;
4992         }
4993
4994         for (i = 0; i < info->reg_array_cnt; i++) {
4995                 info->reset_reg[i] =
4996                         rte_le_to_cpu_32(resp->reset_reg[i]);
4997                 info->reset_reg_val[i] =
4998                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4999                 info->delay_after_reset[i] =
5000                         resp->delay_after_reset[i];
5001         }
5002 err:
5003         HWRM_UNLOCK();
5004
5005         /* Map the FW status registers */
5006         if (!rc)
5007                 rc = bnxt_map_fw_health_status_regs(bp);
5008
5009         if (rc) {
5010                 rte_free(bp->recovery_info);
5011                 bp->recovery_info = NULL;
5012         }
5013         return rc;
5014 }
5015
5016 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5017 {
5018         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5019         struct hwrm_fw_reset_input req = {0};
5020         int rc;
5021
5022         if (!BNXT_PF(bp))
5023                 return -EOPNOTSUPP;
5024
5025         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5026
5027         req.embedded_proc_type =
5028                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5029         req.selfrst_status =
5030                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5031         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5032
5033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5034                                     BNXT_USE_KONG(bp));
5035
5036         HWRM_CHECK_RESULT();
5037         HWRM_UNLOCK();
5038
5039         return rc;
5040 }
5041
5042 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5043 {
5044         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5045         struct hwrm_port_ts_query_input req = {0};
5046         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5047         uint32_t flags = 0;
5048         int rc;
5049
5050         if (!ptp)
5051                 return 0;
5052
5053         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5054
5055         switch (path) {
5056         case BNXT_PTP_FLAGS_PATH_TX:
5057                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5058                 break;
5059         case BNXT_PTP_FLAGS_PATH_RX:
5060                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5061                 break;
5062         case BNXT_PTP_FLAGS_CURRENT_TIME:
5063                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5064                 break;
5065         }
5066
5067         req.flags = rte_cpu_to_le_32(flags);
5068         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5069
5070         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5071
5072         HWRM_CHECK_RESULT();
5073
5074         if (timestamp) {
5075                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5076                 *timestamp |=
5077                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5078         }
5079         HWRM_UNLOCK();
5080
5081         return rc;
5082 }
5083
5084 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5085 {
5086         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5087                                         bp->hwrm_cmd_resp_addr;
5088         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5089         uint32_t flags = 0;
5090         int rc = 0;
5091
5092         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5093                 return rc;
5094
5095         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5096                 PMD_DRV_LOG(DEBUG,
5097                             "Not a PF or trusted VF. Command not supported\n");
5098                 return 0;
5099         }
5100
5101         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5103
5104         HWRM_CHECK_RESULT();
5105         flags = rte_le_to_cpu_32(resp->flags);
5106         HWRM_UNLOCK();
5107
5108         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5109                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5110                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5111         }
5112
5113         return rc;
5114 }