drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 191                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 192         req.target_id = rte_cpu_to_le_16(0xffff); \
 193         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 194 } while (0)
 195
 196 #define HWRM_CHECK_RESULT_SILENT() do {\
 197         if (rc) { \
 198                 rte_spinlock_unlock(&bp->hwrm_lock); \
 199                 return rc; \
 200         } \
 201         if (resp->error_code) { \
 202                 rc = rte_le_to_cpu_16(resp->error_code); \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206 } while (0)
 207
 208 #define HWRM_CHECK_RESULT() do {\
 209         if (rc) { \
 210                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 213                         rc = -EACCES; \
 214                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 215                         rc = -ENOSPC; \
 216                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 217                         rc = -EINVAL; \
 218                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 219                         rc = -ENOTSUP; \
 220                 else if (rc > 0) \
 221                         rc = -EIO; \
 222                 return rc; \
 223         } \
 224         if (resp->error_code) { \
 225                 rc = rte_le_to_cpu_16(resp->error_code); \
 226                 if (resp->resp_len >= 16) { \
 227                         struct hwrm_err_output *tmp_hwrm_err_op = \
 228                                                 (void *)resp; \
 229                         PMD_DRV_LOG(ERR, \
 230                                 "error %d:%d:%08x:%04x\n", \
 231                                 rc, tmp_hwrm_err_op->cmd_err, \
 232                                 rte_le_to_cpu_32(\
 233                                         tmp_hwrm_err_op->opaque_0), \
 234                                 rte_le_to_cpu_16(\
 235                                         tmp_hwrm_err_op->opaque_1)); \
 236                 } else { \
 237                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 238                 } \
 239                 rte_spinlock_unlock(&bp->hwrm_lock); \
 240                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 241                         rc = -EACCES; \
 242                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 243                         rc = -ENOSPC; \
 244                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 245                         rc = -EINVAL; \
 246                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 247                         rc = -ENOTSUP; \
 248                 else if (rc > 0) \
 249                         rc = -EIO; \
 250                 return rc; \
 251         } \
 252 } while (0)
 253
 254 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 255
 256 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261
 262         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 263         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 264         req.mask = 0;
 265
 266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 267
 268         HWRM_CHECK_RESULT();
 269         HWRM_UNLOCK();
 270
 271         return rc;
 272 }
 273
 274 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 275                                  struct bnxt_vnic_info *vnic,
 276                                  uint16_t vlan_count,
 277                                  struct bnxt_vlan_table_entry *vlan_table)
 278 {
 279         int rc = 0;
 280         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 281         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 282         uint32_t mask = 0;
 283
 284         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 285                 return rc;
 286
 287         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 288         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 289
 290         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 291                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 292         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 293                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 294
 295         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 296                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 297
 298         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 299                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 300         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 301                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 302                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 303                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 304         }
 305         if (vlan_table) {
 306                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 307                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 308                 req.vlan_tag_tbl_addr =
 309                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 310                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 311         }
 312         req.mask = rte_cpu_to_le_32(mask);
 313
 314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 315
 316         HWRM_CHECK_RESULT();
 317         HWRM_UNLOCK();
 318
 319         return rc;
 320 }
 321
 322 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 323                         uint16_t vlan_count,
 324                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 325 {
 326         int rc = 0;
 327         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 328         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 329                                                 bp->hwrm_cmd_resp_addr;
 330
 331         /*
 332          * Older HWRM versions did not support this command, and the set_rx_mask
 333          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 334          * removed from set_rx_mask call, and this command was added.
 335          *
 336          * This command is also present from 1.7.8.11 and higher,
 337          * as well as 1.7.8.0
 338          */
 339         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 340                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 341                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 342                                         (11)))
 343                                 return 0;
 344                 }
 345         }
 346         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 347         req.fid = rte_cpu_to_le_16(fid);
 348
 349         req.vlan_tag_mask_tbl_addr =
 350                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 351         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 352
 353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 354
 355         HWRM_CHECK_RESULT();
 356         HWRM_UNLOCK();
 357
 358         return rc;
 359 }
 360
 361 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 362                              struct bnxt_filter_info *filter)
 363 {
 364         int rc = 0;
 365         struct bnxt_filter_info *l2_filter = filter;
 366         struct bnxt_vnic_info *vnic = NULL;
 367         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 368         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 369
 370         if (filter->fw_l2_filter_id == UINT64_MAX)
 371                 return 0;
 372
 373         if (filter->matching_l2_fltr_ptr)
 374                 l2_filter = filter->matching_l2_fltr_ptr;
 375
 376         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 377                     filter, l2_filter, l2_filter->l2_ref_cnt);
 378
 379         if (l2_filter->l2_ref_cnt == 0)
 380                 return 0;
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398         if (l2_filter->l2_ref_cnt == 0) {
 399                 vnic = l2_filter->vnic;
 400                 if (vnic) {
 401                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 402                                       bnxt_filter_info, next);
 403                         bnxt_free_filter(bp, l2_filter);
 404                 }
 405         }
 406
 407         return 0;
 408 }
 409
 410 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 411                          uint16_t dst_id,
 412                          struct bnxt_filter_info *filter)
 413 {
 414         int rc = 0;
 415         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 416         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 417         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 418         const struct rte_eth_vmdq_rx_conf *conf =
 419                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 420         uint32_t enables = 0;
 421         uint16_t j = dst_id - 1;
 422
 423         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 424         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 425             conf->pool_map[j].pools & (1UL << j)) {
 426                 PMD_DRV_LOG(DEBUG,
 427                         "Add vlan %u to vmdq pool %u\n",
 428                         conf->pool_map[j].vlan_id, j);
 429
 430                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 431                 filter->enables |=
 432                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 433                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 434         }
 435
 436         if (filter->fw_l2_filter_id != UINT64_MAX)
 437                 bnxt_hwrm_clear_l2_filter(bp, filter);
 438
 439         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 440
 441         req.flags = rte_cpu_to_le_32(filter->flags);
 442
 443         enables = filter->enables |
 444               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 445         req.dst_id = rte_cpu_to_le_16(dst_id);
 446
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 449                 memcpy(req.l2_addr, filter->l2_addr,
 450                        RTE_ETHER_ADDR_LEN);
 451         if (enables &
 452             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 453                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 454                        RTE_ETHER_ADDR_LEN);
 455         if (enables &
 456             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 457                 req.l2_ovlan = filter->l2_ovlan;
 458         if (enables &
 459             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 460                 req.l2_ivlan = filter->l2_ivlan;
 461         if (enables &
 462             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 463                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 464         if (enables &
 465             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 466                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 467         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 468                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 469         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 470                 req.src_type = filter->src_type;
 471         if (filter->pri_hint) {
 472                 req.pri_hint = filter->pri_hint;
 473                 req.l2_filter_id_hint =
 474                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 475         }
 476
 477         req.enables = rte_cpu_to_le_32(enables);
 478
 479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 480
 481         HWRM_CHECK_RESULT();
 482
 483         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 484         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 485         HWRM_UNLOCK();
 486
 487         filter->l2_ref_cnt++;
 488
 489         return rc;
 490 }
 491
 492 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 493 {
 494         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 495         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 496         uint32_t flags = 0;
 497         int rc;
 498
 499         if (!ptp)
 500                 return 0;
 501
 502         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 503
 504         if (ptp->rx_filter)
 505                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 506         else
 507                 flags |=
 508                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 509         if (ptp->tx_tstamp_en)
 510                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 511         else
 512                 flags |=
 513                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 514         req.flags = rte_cpu_to_le_32(flags);
 515         req.enables = rte_cpu_to_le_32
 516                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 517         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 518
 519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 520         HWRM_UNLOCK();
 521
 522         return rc;
 523 }
 524
 525 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 526 {
 527         int rc = 0;
 528         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 529         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 530         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 531
 532         if (ptp)
 533                 return 0;
 534
 535         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 536
 537         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 538
 539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 540
 541         HWRM_CHECK_RESULT();
 542
 543         if (!BNXT_CHIP_THOR(bp) &&
 544             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 545                 return 0;
 546
 547         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 548                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 549
 550         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 551         if (!ptp)
 552                 return -ENOMEM;
 553
 554         if (!BNXT_CHIP_THOR(bp)) {
 555                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 556                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 557                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 558                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 559                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 560                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 561                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 562                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 563                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 564                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 565                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 566                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 567                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 568                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 569                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 570                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 571                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 572                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 573         }
 574
 575         ptp->bp = bp;
 576         bp->ptp_cfg = ptp;
 577
 578         return 0;
 579 }
 580
 581 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 582 {
 583         int rc = 0;
 584         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 585         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 586         uint16_t new_max_vfs;
 587         uint32_t flags;
 588         int i;
 589
 590         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 591
 592         req.fid = rte_cpu_to_le_16(0xffff);
 593
 594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 595
 596         HWRM_CHECK_RESULT();
 597
 598         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 599         flags = rte_le_to_cpu_32(resp->flags);
 600         if (BNXT_PF(bp)) {
 601                 bp->pf.port_id = resp->port_id;
 602                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 603                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 604                 new_max_vfs = bp->pdev->max_vfs;
 605                 if (new_max_vfs != bp->pf.max_vfs) {
 606                         if (bp->pf.vf_info)
 607                                 rte_free(bp->pf.vf_info);
 608                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 609                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 610                         bp->pf.max_vfs = new_max_vfs;
 611                         for (i = 0; i < new_max_vfs; i++) {
 612                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 613                                 bp->pf.vf_info[i].vlan_table =
 614                                         rte_zmalloc("VF VLAN table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Fail to alloc VLAN table for VF %d\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                 bp->pf.vf_info[i].vlan_table);
 624                                 bp->pf.vf_info[i].vlan_as_table =
 625                                         rte_zmalloc("VF VLAN AS table",
 626                                                     getpagesize(),
 627                                                     getpagesize());
 628                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 629                                         PMD_DRV_LOG(ERR,
 630                                         "Alloc VLAN AS table for VF %d fail\n",
 631                                         i);
 632                                 else
 633                                         rte_mem_lock_page(
 634                                                bp->pf.vf_info[i].vlan_as_table);
 635                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 636                         }
 637                 }
 638         }
 639
 640         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 641         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 642         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 643         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 644         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 645         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 646         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 647         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 648         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 649         if (!BNXT_CHIP_THOR(bp))
 650                 bp->max_l2_ctx += bp->max_rx_em_flows;
 651         /* TODO: For now, do not support VMDq/RFS on VFs. */
 652         if (BNXT_PF(bp)) {
 653                 if (bp->pf.max_vfs)
 654                         bp->max_vnics = 1;
 655                 else
 656                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 657         } else {
 658                 bp->max_vnics = 1;
 659         }
 660         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 661         if (BNXT_PF(bp)) {
 662                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 663                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 664                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 665                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 666                         HWRM_UNLOCK();
 667                         bnxt_hwrm_ptp_qcfg(bp);
 668                 }
 669         }
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 672                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 673
 674         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 675                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 676                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 677         }
 678
 679         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 680                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 681
 682         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 683                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 684
 685         HWRM_UNLOCK();
 686
 687         return rc;
 688 }
 689
 690 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 691 {
 692         int rc;
 693
 694         rc = __bnxt_hwrm_func_qcaps(bp);
 695         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 696                 rc = bnxt_alloc_ctx_mem(bp);
 697                 if (rc)
 698                         return rc;
 699
 700                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 701                 if (!rc)
 702                         bp->flags |= BNXT_FLAG_NEW_RM;
 703         }
 704
 705         /* On older FW,
 706          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 707          * But the error can be ignored. Return success.
 708          */
 709
 710         return 0;
 711 }
 712
 713 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 714 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 715 {
 716         int rc = 0;
 717         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 718         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 719
 720         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 721
 722         req.target_id = rte_cpu_to_le_16(0xffff);
 723
 724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 725
 726         HWRM_CHECK_RESULT();
 727
 728         if (rte_le_to_cpu_32(resp->flags) &
 729             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 730                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 731                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 732         }
 733
 734         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 735
 736         HWRM_UNLOCK();
 737
 738         return rc;
 739 }
 740
 741 int bnxt_hwrm_func_reset(struct bnxt *bp)
 742 {
 743         int rc = 0;
 744         struct hwrm_func_reset_input req = {.req_type = 0 };
 745         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 746
 747         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 748
 749         req.enables = rte_cpu_to_le_32(0);
 750
 751         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 752
 753         HWRM_CHECK_RESULT();
 754         HWRM_UNLOCK();
 755
 756         return rc;
 757 }
 758
 759 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 760 {
 761         int rc;
 762         uint32_t flags = 0;
 763         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 764         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 765
 766         if (bp->flags & BNXT_FLAG_REGISTERED)
 767                 return 0;
 768
 769         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 770                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 771         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 772                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 773
 774         /* PFs and trusted VFs should indicate the support of the
 775          * Master capability on non Stingray platform
 776          */
 777         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 778                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 779
 780         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 781         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 782                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 783         req.ver_maj = RTE_VER_YEAR;
 784         req.ver_min = RTE_VER_MONTH;
 785         req.ver_upd = RTE_VER_MINOR;
 786
 787         if (BNXT_PF(bp)) {
 788                 req.enables |= rte_cpu_to_le_32(
 789                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 790                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 791                        RTE_MIN(sizeof(req.vf_req_fwd),
 792                                sizeof(bp->pf.vf_req_fwd)));
 793
 794                 /*
 795                  * PF can sniff HWRM API issued by VF. This can be set up by
 796                  * linux driver and inherited by the DPDK PF driver. Clear
 797                  * this HWRM sniffer list in FW because DPDK PF driver does
 798                  * not support this.
 799                  */
 800                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 801         }
 802
 803         req.flags = rte_cpu_to_le_32(flags);
 804
 805         req.async_event_fwd[0] |=
 806                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 807                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 808                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 809                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 810                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 811         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 812                 req.async_event_fwd[0] |=
 813                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 814         req.async_event_fwd[1] |=
 815                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 816                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 817         if (BNXT_PF(bp))
 818                 req.async_event_fwd[1] |=
 819                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 820
 821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 822
 823         HWRM_CHECK_RESULT();
 824
 825         flags = rte_le_to_cpu_32(resp->flags);
 826         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 827                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 828
 829         HWRM_UNLOCK();
 830
 831         bp->flags |= BNXT_FLAG_REGISTERED;
 832
 833         return rc;
 834 }
 835
 836 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 837 {
 838         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 839                 return 0;
 840
 841         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 842 }
 843
 844 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 845 {
 846         int rc;
 847         uint32_t flags = 0;
 848         uint32_t enables;
 849         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 850         struct hwrm_func_vf_cfg_input req = {0};
 851
 852         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 853
 854         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 855                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 856                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 857                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 858                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 859
 860         if (BNXT_HAS_RING_GRPS(bp)) {
 861                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 862                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 863         }
 864
 865         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 866         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 867                                             AGG_RING_MULTIPLIER);
 868         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 869         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 870                                               bp->tx_nr_rings +
 871                                               BNXT_NUM_ASYNC_CPR(bp));
 872         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 873         if (bp->vf_resv_strategy ==
 874             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 875                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 876                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 877                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 878                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 879                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 880                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 881         } else if (bp->vf_resv_strategy ==
 882                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 883                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 884                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 885         }
 886
 887         if (test)
 888                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 889                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 890                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 891                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 892                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 893                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 894
 895         if (test && BNXT_HAS_RING_GRPS(bp))
 896                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 897
 898         req.flags = rte_cpu_to_le_32(flags);
 899         req.enables |= rte_cpu_to_le_32(enables);
 900
 901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 902
 903         if (test)
 904                 HWRM_CHECK_RESULT_SILENT();
 905         else
 906                 HWRM_CHECK_RESULT();
 907
 908         HWRM_UNLOCK();
 909         return rc;
 910 }
 911
 912 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 913 {
 914         int rc;
 915         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 916         struct hwrm_func_resource_qcaps_input req = {0};
 917
 918         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 919         req.fid = rte_cpu_to_le_16(0xffff);
 920
 921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 922
 923         HWRM_CHECK_RESULT_SILENT();
 924
 925         if (BNXT_VF(bp)) {
 926                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 927                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 928                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 929                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 930                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 931                 /* func_resource_qcaps does not return max_rx_em_flows.
 932                  * So use the value provided by func_qcaps.
 933                  */
 934                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 935                 if (!BNXT_CHIP_THOR(bp))
 936                         bp->max_l2_ctx += bp->max_rx_em_flows;
 937                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 938                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 939         }
 940         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 941         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 942         if (bp->vf_resv_strategy >
 943             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 944                 bp->vf_resv_strategy =
 945                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 946
 947         HWRM_UNLOCK();
 948         return rc;
 949 }
 950
 951 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
 952 {
 953         int rc = 0;
 954         struct hwrm_ver_get_input req = {.req_type = 0 };
 955         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 956         uint32_t fw_version;
 957         uint16_t max_resp_len;
 958         char type[RTE_MEMZONE_NAMESIZE];
 959         uint32_t dev_caps_cfg;
 960
 961         bp->max_req_len = HWRM_MAX_REQ_LEN;
 962         bp->hwrm_cmd_timeout = timeout;
 963         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 964
 965         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 966         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 967         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 968
 969         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 970
 971         if (bp->flags & BNXT_FLAG_FW_RESET)
 972                 HWRM_CHECK_RESULT_SILENT();
 973         else
 974                 HWRM_CHECK_RESULT();
 975
 976         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 977                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 978                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 979                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 980         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 981                      (resp->hwrm_fw_min_8b << 16) |
 982                      (resp->hwrm_fw_bld_8b << 8) |
 983                      resp->hwrm_fw_rsvd_8b;
 984         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 985                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 986
 987         fw_version = resp->hwrm_intf_maj_8b << 16;
 988         fw_version |= resp->hwrm_intf_min_8b << 8;
 989         fw_version |= resp->hwrm_intf_upd_8b;
 990         bp->hwrm_spec_code = fw_version;
 991
 992         /* def_req_timeout value is in milliseconds */
 993         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 994         /* convert timeout to usec */
 995         bp->hwrm_cmd_timeout *= 1000;
 996         if (!bp->hwrm_cmd_timeout)
 997                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
 998
 999         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1000                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1001                 rc = -EINVAL;
1002                 goto error;
1003         }
1004
1005         if (bp->max_req_len > resp->max_req_win_len) {
1006                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1007                 rc = -EINVAL;
1008         }
1009         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1010         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1011         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1012                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1013
1014         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1015         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1016
1017         if (bp->max_resp_len != max_resp_len) {
1018                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1019                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1020                         bp->pdev->addr.devid, bp->pdev->addr.function);
1021
1022                 rte_free(bp->hwrm_cmd_resp_addr);
1023
1024                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1025                 if (bp->hwrm_cmd_resp_addr == NULL) {
1026                         rc = -ENOMEM;
1027                         goto error;
1028                 }
1029                 bp->hwrm_cmd_resp_dma_addr =
1030                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1031                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1032                         PMD_DRV_LOG(ERR,
1033                         "Unable to map response buffer to physical memory.\n");
1034                         rc = -ENOMEM;
1035                         goto error;
1036                 }
1037                 bp->max_resp_len = max_resp_len;
1038         }
1039
1040         if ((dev_caps_cfg &
1041                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1042             (dev_caps_cfg &
1043              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1044                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1045                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1046         }
1047
1048         if (((dev_caps_cfg &
1049               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1050              (dev_caps_cfg &
1051               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1052             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1053                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1054                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1055                         bp->pdev->addr.devid, bp->pdev->addr.function);
1056
1057                 rte_free(bp->hwrm_short_cmd_req_addr);
1058
1059                 bp->hwrm_short_cmd_req_addr =
1060                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1061                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1062                         rc = -ENOMEM;
1063                         goto error;
1064                 }
1065                 bp->hwrm_short_cmd_req_dma_addr =
1066                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1067                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1068                         rte_free(bp->hwrm_short_cmd_req_addr);
1069                         PMD_DRV_LOG(ERR,
1070                                 "Unable to map buffer to physical memory.\n");
1071                         rc = -ENOMEM;
1072                         goto error;
1073                 }
1074         }
1075         if (dev_caps_cfg &
1076             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1077                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1078                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1079         }
1080         if (dev_caps_cfg &
1081             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1082                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1083         if (dev_caps_cfg &
1084             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1085                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1086                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1087         }
1088
1089 error:
1090         HWRM_UNLOCK();
1091         return rc;
1092 }
1093
1094 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1095 {
1096         int rc;
1097         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1098         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1099
1100         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1101                 return 0;
1102
1103         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1104         req.flags = flags;
1105
1106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107
1108         HWRM_CHECK_RESULT();
1109         HWRM_UNLOCK();
1110
1111         return rc;
1112 }
1113
1114 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1115 {
1116         int rc = 0;
1117         struct hwrm_port_phy_cfg_input req = {0};
1118         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1119         uint32_t enables = 0;
1120
1121         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1122
1123         if (conf->link_up) {
1124                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1125                 if (bp->link_info.auto_mode && conf->link_speed) {
1126                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1127                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1128                 }
1129
1130                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1131                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1132                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1133                 /*
1134                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1135                  * any auto mode, even "none".
1136                  */
1137                 if (!conf->link_speed) {
1138                         /* No speeds specified. Enable AutoNeg - all speeds */
1139                         req.auto_mode =
1140                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1141                 }
1142                 /* AutoNeg - Advertise speeds specified. */
1143                 if (conf->auto_link_speed_mask &&
1144                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1145                         req.auto_mode =
1146                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1147                         req.auto_link_speed_mask =
1148                                 conf->auto_link_speed_mask;
1149                         enables |=
1150                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1151                 }
1152
1153                 req.auto_duplex = conf->duplex;
1154                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1155                 req.auto_pause = conf->auto_pause;
1156                 req.force_pause = conf->force_pause;
1157                 /* Set force_pause if there is no auto or if there is a force */
1158                 if (req.auto_pause && !req.force_pause)
1159                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1160                 else
1161                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1162
1163                 req.enables = rte_cpu_to_le_32(enables);
1164         } else {
1165                 req.flags =
1166                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1167                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1168         }
1169
1170         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1171
1172         HWRM_CHECK_RESULT();
1173         HWRM_UNLOCK();
1174
1175         return rc;
1176 }
1177
1178 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1179                                    struct bnxt_link_info *link_info)
1180 {
1181         int rc = 0;
1182         struct hwrm_port_phy_qcfg_input req = {0};
1183         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184
1185         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1186
1187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1188
1189         HWRM_CHECK_RESULT();
1190
1191         link_info->phy_link_status = resp->link;
1192         link_info->link_up =
1193                 (link_info->phy_link_status ==
1194                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1195         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1196         link_info->duplex = resp->duplex_cfg;
1197         link_info->pause = resp->pause;
1198         link_info->auto_pause = resp->auto_pause;
1199         link_info->force_pause = resp->force_pause;
1200         link_info->auto_mode = resp->auto_mode;
1201         link_info->phy_type = resp->phy_type;
1202         link_info->media_type = resp->media_type;
1203
1204         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1205         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1206         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1207         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1208         link_info->phy_ver[0] = resp->phy_maj;
1209         link_info->phy_ver[1] = resp->phy_min;
1210         link_info->phy_ver[2] = resp->phy_bld;
1211
1212         HWRM_UNLOCK();
1213
1214         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1215         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1216         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1217         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1218         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1219                     link_info->auto_link_speed_mask);
1220         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1221                     link_info->force_link_speed);
1222
1223         return rc;
1224 }
1225
1226 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1227 {
1228         int i = 0;
1229
1230         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1231                 if (bp->tx_cos_queue[i].profile ==
1232                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1233                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1234                         return true;
1235                 }
1236         }
1237         return false;
1238 }
1239
1240 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1241 {
1242         int i = 0;
1243
1244         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1245                 if (bp->tx_cos_queue[i].profile !=
1246                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1247                     bp->tx_cos_queue[i].id !=
1248                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1249                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1250                         break;
1251                 }
1252         }
1253 }
1254
1255 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1256 {
1257         int rc = 0;
1258         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1259         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1260         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1261         int i;
1262
1263 get_rx_info:
1264         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1265
1266         req.flags = rte_cpu_to_le_32(dir);
1267         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1268         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1269             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1270                 req.drv_qmap_cap =
1271                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1272         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1273
1274         HWRM_CHECK_RESULT();
1275
1276         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1277                 GET_TX_QUEUE_INFO(0);
1278                 GET_TX_QUEUE_INFO(1);
1279                 GET_TX_QUEUE_INFO(2);
1280                 GET_TX_QUEUE_INFO(3);
1281                 GET_TX_QUEUE_INFO(4);
1282                 GET_TX_QUEUE_INFO(5);
1283                 GET_TX_QUEUE_INFO(6);
1284                 GET_TX_QUEUE_INFO(7);
1285         } else  {
1286                 GET_RX_QUEUE_INFO(0);
1287                 GET_RX_QUEUE_INFO(1);
1288                 GET_RX_QUEUE_INFO(2);
1289                 GET_RX_QUEUE_INFO(3);
1290                 GET_RX_QUEUE_INFO(4);
1291                 GET_RX_QUEUE_INFO(5);
1292                 GET_RX_QUEUE_INFO(6);
1293                 GET_RX_QUEUE_INFO(7);
1294         }
1295
1296         HWRM_UNLOCK();
1297
1298         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1299                 goto done;
1300
1301         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1302                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1303         } else {
1304                 int j;
1305
1306                 /* iterate and find the COSq profile to use for Tx */
1307                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1308                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1309                                 if (bp->tx_cos_queue[i].id != 0xff)
1310                                         bp->tx_cosq_id[j++] =
1311                                                 bp->tx_cos_queue[i].id;
1312                         }
1313                 } else {
1314                         /* When CoS classification is disabled, for normal NIC
1315                          * operations, ideally we should look to use LOSSY.
1316                          * If not found, fallback to the first valid profile
1317                          */
1318                         if (!bnxt_find_lossy_profile(bp))
1319                                 bnxt_find_first_valid_profile(bp);
1320
1321                 }
1322         }
1323
1324         bp->max_tc = resp->max_configurable_queues;
1325         bp->max_lltc = resp->max_configurable_lossless_queues;
1326         if (bp->max_tc > BNXT_MAX_QUEUE)
1327                 bp->max_tc = BNXT_MAX_QUEUE;
1328         bp->max_q = bp->max_tc;
1329
1330         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1331                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1332                 goto get_rx_info;
1333         }
1334
1335 done:
1336         return rc;
1337 }
1338
1339 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1340                          struct bnxt_ring *ring,
1341                          uint32_t ring_type, uint32_t map_index,
1342                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1343                          uint16_t tx_cosq_id)
1344 {
1345         int rc = 0;
1346         uint32_t enables = 0;
1347         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1348         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1349         struct rte_mempool *mb_pool;
1350         uint16_t rx_buf_size;
1351
1352         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1353
1354         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1355         req.fbo = rte_cpu_to_le_32(0);
1356         /* Association of ring index with doorbell index */
1357         req.logical_id = rte_cpu_to_le_16(map_index);
1358         req.length = rte_cpu_to_le_32(ring->ring_size);
1359
1360         switch (ring_type) {
1361         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1362                 req.ring_type = ring_type;
1363                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1364                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1365                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1366                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1367                         enables |=
1368                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1369                 break;
1370         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1371                 req.ring_type = ring_type;
1372                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1373                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1374                 if (BNXT_CHIP_THOR(bp)) {
1375                         mb_pool = bp->rx_queues[0]->mb_pool;
1376                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1377                                       RTE_PKTMBUF_HEADROOM;
1378                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1379                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1380                         enables |=
1381                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1382                 }
1383                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1384                         enables |=
1385                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1386                 break;
1387         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1388                 req.ring_type = ring_type;
1389                 if (BNXT_HAS_NQ(bp)) {
1390                         /* Association of cp ring with nq */
1391                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1392                         enables |=
1393                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1394                 }
1395                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1396                 break;
1397         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1398                 req.ring_type = ring_type;
1399                 req.page_size = BNXT_PAGE_SHFT;
1400                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1401                 break;
1402         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1403                 req.ring_type = ring_type;
1404                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1405
1406                 mb_pool = bp->rx_queues[0]->mb_pool;
1407                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1408                               RTE_PKTMBUF_HEADROOM;
1409                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1410                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1411
1412                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1413                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1414                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1415                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1416                 break;
1417         default:
1418                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1419                         ring_type);
1420                 HWRM_UNLOCK();
1421                 return -EINVAL;
1422         }
1423         req.enables = rte_cpu_to_le_32(enables);
1424
1425         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1426
1427         if (rc || resp->error_code) {
1428                 if (rc == 0 && resp->error_code)
1429                         rc = rte_le_to_cpu_16(resp->error_code);
1430                 switch (ring_type) {
1431                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1432                         PMD_DRV_LOG(ERR,
1433                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1434                         HWRM_UNLOCK();
1435                         return rc;
1436                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1437                         PMD_DRV_LOG(ERR,
1438                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1439                         HWRM_UNLOCK();
1440                         return rc;
1441                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1442                         PMD_DRV_LOG(ERR,
1443                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1444                                     rc);
1445                         HWRM_UNLOCK();
1446                         return rc;
1447                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1448                         PMD_DRV_LOG(ERR,
1449                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1450                         HWRM_UNLOCK();
1451                         return rc;
1452                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1453                         PMD_DRV_LOG(ERR,
1454                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1455                         HWRM_UNLOCK();
1456                         return rc;
1457                 default:
1458                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1459                         HWRM_UNLOCK();
1460                         return rc;
1461                 }
1462         }
1463
1464         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1465         HWRM_UNLOCK();
1466         return rc;
1467 }
1468
1469 int bnxt_hwrm_ring_free(struct bnxt *bp,
1470                         struct bnxt_ring *ring, uint32_t ring_type)
1471 {
1472         int rc;
1473         struct hwrm_ring_free_input req = {.req_type = 0 };
1474         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1475
1476         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1477
1478         req.ring_type = ring_type;
1479         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1480
1481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482
1483         if (rc || resp->error_code) {
1484                 if (rc == 0 && resp->error_code)
1485                         rc = rte_le_to_cpu_16(resp->error_code);
1486                 HWRM_UNLOCK();
1487
1488                 switch (ring_type) {
1489                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1490                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1491                                 rc);
1492                         return rc;
1493                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1494                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1495                                 rc);
1496                         return rc;
1497                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1498                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1499                                 rc);
1500                         return rc;
1501                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1502                         PMD_DRV_LOG(ERR,
1503                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1504                         return rc;
1505                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1506                         PMD_DRV_LOG(ERR,
1507                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1508                         return rc;
1509                 default:
1510                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1511                         return rc;
1512                 }
1513         }
1514         HWRM_UNLOCK();
1515         return 0;
1516 }
1517
1518 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1519 {
1520         int rc = 0;
1521         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1522         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1523
1524         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1525
1526         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1527         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1528         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1529         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1530
1531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1532
1533         HWRM_CHECK_RESULT();
1534
1535         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1536
1537         HWRM_UNLOCK();
1538
1539         return rc;
1540 }
1541
1542 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1543 {
1544         int rc;
1545         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1546         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1547
1548         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1549
1550         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1551
1552         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1553
1554         HWRM_CHECK_RESULT();
1555         HWRM_UNLOCK();
1556
1557         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1558         return rc;
1559 }
1560
1561 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1562 {
1563         int rc = 0;
1564         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1565         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1566
1567         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1568                 return rc;
1569
1570         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1571
1572         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1573
1574         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1575
1576         HWRM_CHECK_RESULT();
1577         HWRM_UNLOCK();
1578
1579         return rc;
1580 }
1581
1582 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1583                                 unsigned int idx __rte_unused)
1584 {
1585         int rc;
1586         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1587         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1588
1589         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1590
1591         req.update_period_ms = rte_cpu_to_le_32(0);
1592
1593         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1594
1595         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1596
1597         HWRM_CHECK_RESULT();
1598
1599         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1600
1601         HWRM_UNLOCK();
1602
1603         return rc;
1604 }
1605
1606 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1607                                 unsigned int idx __rte_unused)
1608 {
1609         int rc;
1610         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1611         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1612
1613         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1614
1615         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1616
1617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618
1619         HWRM_CHECK_RESULT();
1620         HWRM_UNLOCK();
1621
1622         return rc;
1623 }
1624
1625 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1626 {
1627         int rc = 0, i, j;
1628         struct hwrm_vnic_alloc_input req = { 0 };
1629         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630
1631         if (!BNXT_HAS_RING_GRPS(bp))
1632                 goto skip_ring_grps;
1633
1634         /* map ring groups to this vnic */
1635         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1636                 vnic->start_grp_id, vnic->end_grp_id);
1637         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1638                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1639
1640         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1641         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1642         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1643         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1644
1645 skip_ring_grps:
1646         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1647         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1648
1649         if (vnic->func_default)
1650                 req.flags =
1651                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1653
1654         HWRM_CHECK_RESULT();
1655
1656         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1657         HWRM_UNLOCK();
1658         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1659         return rc;
1660 }
1661
1662 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1663                                         struct bnxt_vnic_info *vnic,
1664                                         struct bnxt_plcmodes_cfg *pmode)
1665 {
1666         int rc = 0;
1667         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1668         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1669
1670         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1671
1672         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1673
1674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1675
1676         HWRM_CHECK_RESULT();
1677
1678         pmode->flags = rte_le_to_cpu_32(resp->flags);
1679         /* dflt_vnic bit doesn't exist in the _cfg command */
1680         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1681         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1682         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1683         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1684
1685         HWRM_UNLOCK();
1686
1687         return rc;
1688 }
1689
1690 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1691                                        struct bnxt_vnic_info *vnic,
1692                                        struct bnxt_plcmodes_cfg *pmode)
1693 {
1694         int rc = 0;
1695         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1696         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1697
1698         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1699                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1700                 return rc;
1701         }
1702
1703         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1704
1705         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1706         req.flags = rte_cpu_to_le_32(pmode->flags);
1707         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1708         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1709         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1710         req.enables = rte_cpu_to_le_32(
1711             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1712             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1713             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1714         );
1715
1716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1717
1718         HWRM_CHECK_RESULT();
1719         HWRM_UNLOCK();
1720
1721         return rc;
1722 }
1723
1724 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1725 {
1726         int rc = 0;
1727         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1728         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1729         struct bnxt_plcmodes_cfg pmodes = { 0 };
1730         uint32_t ctx_enable_flag = 0;
1731         uint32_t enables = 0;
1732
1733         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1734                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1735                 return rc;
1736         }
1737
1738         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1739         if (rc)
1740                 return rc;
1741
1742         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1743
1744         if (BNXT_CHIP_THOR(bp)) {
1745                 int dflt_rxq = vnic->start_grp_id;
1746                 struct bnxt_rx_ring_info *rxr;
1747                 struct bnxt_cp_ring_info *cpr;
1748                 struct bnxt_rx_queue *rxq;
1749                 int i;
1750
1751                 /*
1752                  * The first active receive ring is used as the VNIC
1753                  * default receive ring. If there are no active receive
1754                  * rings (all corresponding receive queues are stopped),
1755                  * the first receive ring is used.
1756                  */
1757                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1758                         rxq = bp->eth_dev->data->rx_queues[i];
1759                         if (rxq->rx_started) {
1760                                 dflt_rxq = i;
1761                                 break;
1762                         }
1763                 }
1764
1765                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1766                 rxr = rxq->rx_ring;
1767                 cpr = rxq->cp_ring;
1768
1769                 req.default_rx_ring_id =
1770                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1771                 req.default_cmpl_ring_id =
1772                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1773                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1774                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1775                 goto config_mru;
1776         }
1777
1778         /* Only RSS support for now TBD: COS & LB */
1779         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1780         if (vnic->lb_rule != 0xffff)
1781                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1782         if (vnic->cos_rule != 0xffff)
1783                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1784         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1785                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1786                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1787         }
1788         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1789                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1790                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1791         }
1792
1793         enables |= ctx_enable_flag;
1794         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1795         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1796         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1797         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1798
1799 config_mru:
1800         req.enables = rte_cpu_to_le_32(enables);
1801         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1802         req.mru = rte_cpu_to_le_16(vnic->mru);
1803         /* Configure default VNIC only once. */
1804         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1805                 req.flags |=
1806                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1807                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1808         }
1809         if (vnic->vlan_strip)
1810                 req.flags |=
1811                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1812         if (vnic->bd_stall)
1813                 req.flags |=
1814                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1815         if (vnic->roce_dual)
1816                 req.flags |= rte_cpu_to_le_32(
1817                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1818         if (vnic->roce_only)
1819                 req.flags |= rte_cpu_to_le_32(
1820                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1821         if (vnic->rss_dflt_cr)
1822                 req.flags |= rte_cpu_to_le_32(
1823                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1824
1825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1826
1827         HWRM_CHECK_RESULT();
1828         HWRM_UNLOCK();
1829
1830         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1831
1832         return rc;
1833 }
1834
1835 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1836                 int16_t fw_vf_id)
1837 {
1838         int rc = 0;
1839         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1840         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1841
1842         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1843                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1844                 return rc;
1845         }
1846         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1847
1848         req.enables =
1849                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1850         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1851         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1852
1853         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1854
1855         HWRM_CHECK_RESULT();
1856
1857         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1858         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1859         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1860         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1861         vnic->mru = rte_le_to_cpu_16(resp->mru);
1862         vnic->func_default = rte_le_to_cpu_32(
1863                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1864         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1865                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1866         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1867                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1868         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1869                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1870         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1871                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1872         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1873                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1874
1875         HWRM_UNLOCK();
1876
1877         return rc;
1878 }
1879
1880 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1881                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1882 {
1883         int rc = 0;
1884         uint16_t ctx_id;
1885         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1886         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1887                                                 bp->hwrm_cmd_resp_addr;
1888
1889         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1890
1891         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1892         HWRM_CHECK_RESULT();
1893
1894         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1895         if (!BNXT_HAS_RING_GRPS(bp))
1896                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1897         else if (ctx_idx == 0)
1898                 vnic->rss_rule = ctx_id;
1899
1900         HWRM_UNLOCK();
1901
1902         return rc;
1903 }
1904
1905 static
1906 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1907                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1908 {
1909         int rc = 0;
1910         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1911         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1912                                                 bp->hwrm_cmd_resp_addr;
1913
1914         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1915                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1916                 return rc;
1917         }
1918         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1919
1920         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1921
1922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1923
1924         HWRM_CHECK_RESULT();
1925         HWRM_UNLOCK();
1926
1927         return rc;
1928 }
1929
1930 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1931 {
1932         int rc = 0;
1933
1934         if (BNXT_CHIP_THOR(bp)) {
1935                 int j;
1936
1937                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1938                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1939                                                       vnic,
1940                                                       vnic->fw_grp_ids[j]);
1941                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1942                 }
1943                 vnic->num_lb_ctxts = 0;
1944         } else {
1945                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1946                 vnic->rss_rule = INVALID_HW_RING_ID;
1947         }
1948
1949         return rc;
1950 }
1951
1952 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1953 {
1954         int rc = 0;
1955         struct hwrm_vnic_free_input req = {.req_type = 0 };
1956         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1957
1958         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1959                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1960                 return rc;
1961         }
1962
1963         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1964
1965         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1966
1967         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1968
1969         HWRM_CHECK_RESULT();
1970         HWRM_UNLOCK();
1971
1972         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1973         /* Configure default VNIC again if necessary. */
1974         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1975                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1976
1977         return rc;
1978 }
1979
1980 static int
1981 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1982 {
1983         int i;
1984         int rc = 0;
1985         int nr_ctxs = vnic->num_lb_ctxts;
1986         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1987         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1988
1989         for (i = 0; i < nr_ctxs; i++) {
1990                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1991
1992                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1994                 req.hash_mode_flags = vnic->hash_mode;
1995
1996                 req.hash_key_tbl_addr =
1997                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1998
1999                 req.ring_grp_tbl_addr =
2000                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2001                                          i * HW_HASH_INDEX_SIZE);
2002                 req.ring_table_pair_index = i;
2003                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2004
2005                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2006                                             BNXT_USE_CHIMP_MB);
2007
2008                 HWRM_CHECK_RESULT();
2009                 HWRM_UNLOCK();
2010         }
2011
2012         return rc;
2013 }
2014
2015 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2016                            struct bnxt_vnic_info *vnic)
2017 {
2018         int rc = 0;
2019         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2020         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2021
2022         if (!vnic->rss_table)
2023                 return 0;
2024
2025         if (BNXT_CHIP_THOR(bp))
2026                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2027
2028         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2029
2030         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2031         req.hash_mode_flags = vnic->hash_mode;
2032
2033         req.ring_grp_tbl_addr =
2034             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2035         req.hash_key_tbl_addr =
2036             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2037         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2038         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2039
2040         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2041
2042         HWRM_CHECK_RESULT();
2043         HWRM_UNLOCK();
2044
2045         return rc;
2046 }
2047
2048 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2049                         struct bnxt_vnic_info *vnic)
2050 {
2051         int rc = 0;
2052         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2053         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2054         uint16_t size;
2055
2056         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2058                 return rc;
2059         }
2060
2061         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2062
2063         req.flags = rte_cpu_to_le_32(
2064                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2065
2066         req.enables = rte_cpu_to_le_32(
2067                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2068
2069         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2070         size -= RTE_PKTMBUF_HEADROOM;
2071         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2072
2073         req.jumbo_thresh = rte_cpu_to_le_16(size);
2074         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077
2078         HWRM_CHECK_RESULT();
2079         HWRM_UNLOCK();
2080
2081         return rc;
2082 }
2083
2084 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2085                         struct bnxt_vnic_info *vnic, bool enable)
2086 {
2087         int rc = 0;
2088         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2089         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2090
2091         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2092                 if (enable)
2093                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2094                 return -ENOTSUP;
2095         }
2096
2097         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2099                 return 0;
2100         }
2101
2102         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2103
2104         if (enable) {
2105                 req.enables = rte_cpu_to_le_32(
2106                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2107                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2108                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2109                 req.flags = rte_cpu_to_le_32(
2110                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2111                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2112                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2113                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2114                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2115                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2116                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2117                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2118                 req.min_agg_len = rte_cpu_to_le_32(512);
2119         }
2120         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2121
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2123
2124         HWRM_CHECK_RESULT();
2125         HWRM_UNLOCK();
2126
2127         return rc;
2128 }
2129
2130 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2131 {
2132         struct hwrm_func_cfg_input req = {0};
2133         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2134         int rc;
2135
2136         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2137         req.enables = rte_cpu_to_le_32(
2138                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2139         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2140         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2141
2142         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2143
2144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2145         HWRM_CHECK_RESULT();
2146         HWRM_UNLOCK();
2147
2148         bp->pf.vf_info[vf].random_mac = false;
2149
2150         return rc;
2151 }
2152
2153 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2154                                   uint64_t *dropped)
2155 {
2156         int rc = 0;
2157         struct hwrm_func_qstats_input req = {.req_type = 0};
2158         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2159
2160         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2161
2162         req.fid = rte_cpu_to_le_16(fid);
2163
2164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2165
2166         HWRM_CHECK_RESULT();
2167
2168         if (dropped)
2169                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2170
2171         HWRM_UNLOCK();
2172
2173         return rc;
2174 }
2175
2176 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2177                           struct rte_eth_stats *stats)
2178 {
2179         int rc = 0;
2180         struct hwrm_func_qstats_input req = {.req_type = 0};
2181         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2182
2183         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2184
2185         req.fid = rte_cpu_to_le_16(fid);
2186
2187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2188
2189         HWRM_CHECK_RESULT();
2190
2191         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2192         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2193         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2194         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2195         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2196         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2197
2198         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2199         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2200         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2201         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2202         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2203         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2204
2205         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2206         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2207         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2208
2209         HWRM_UNLOCK();
2210
2211         return rc;
2212 }
2213
2214 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2215 {
2216         int rc = 0;
2217         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2218         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2219
2220         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2221
2222         req.fid = rte_cpu_to_le_16(fid);
2223
2224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2225
2226         HWRM_CHECK_RESULT();
2227         HWRM_UNLOCK();
2228
2229         return rc;
2230 }
2231
2232 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2233 {
2234         unsigned int i;
2235         int rc = 0;
2236
2237         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2238                 struct bnxt_tx_queue *txq;
2239                 struct bnxt_rx_queue *rxq;
2240                 struct bnxt_cp_ring_info *cpr;
2241
2242                 if (i >= bp->rx_cp_nr_rings) {
2243                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2244                         cpr = txq->cp_ring;
2245                 } else {
2246                         rxq = bp->rx_queues[i];
2247                         cpr = rxq->cp_ring;
2248                 }
2249
2250                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2251                 if (rc)
2252                         return rc;
2253         }
2254         return 0;
2255 }
2256
2257 static int
2258 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2259 {
2260         int rc;
2261         unsigned int i;
2262         struct bnxt_cp_ring_info *cpr;
2263
2264         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2265
2266                 if (i >= bp->rx_cp_nr_rings) {
2267                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2268                 } else {
2269                         cpr = bp->rx_queues[i]->cp_ring;
2270                         if (BNXT_HAS_RING_GRPS(bp))
2271                                 bp->grp_info[i].fw_stats_ctx = -1;
2272                 }
2273                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2274                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2275                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2276                         if (rc)
2277                                 return rc;
2278                 }
2279         }
2280         return 0;
2281 }
2282
2283 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2284 {
2285         unsigned int i;
2286         int rc = 0;
2287
2288         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2289                 struct bnxt_tx_queue *txq;
2290                 struct bnxt_rx_queue *rxq;
2291                 struct bnxt_cp_ring_info *cpr;
2292
2293                 if (i >= bp->rx_cp_nr_rings) {
2294                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2295                         cpr = txq->cp_ring;
2296                 } else {
2297                         rxq = bp->rx_queues[i];
2298                         cpr = rxq->cp_ring;
2299                 }
2300
2301                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2302
2303                 if (rc)
2304                         return rc;
2305         }
2306         return rc;
2307 }
2308
2309 static int
2310 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2311 {
2312         uint16_t idx;
2313         uint32_t rc = 0;
2314
2315         if (!BNXT_HAS_RING_GRPS(bp))
2316                 return 0;
2317
2318         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2319
2320                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2321                         continue;
2322
2323                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2324
2325                 if (rc)
2326                         return rc;
2327         }
2328         return rc;
2329 }
2330
2331 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2332 {
2333         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2334
2335         bnxt_hwrm_ring_free(bp, cp_ring,
2336                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2337         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2338         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2339                                      sizeof(*cpr->cp_desc_ring));
2340         cpr->cp_raw_cons = 0;
2341         cpr->valid = 0;
2342 }
2343
2344 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2345 {
2346         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2347
2348         bnxt_hwrm_ring_free(bp, cp_ring,
2349                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2350         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2351         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2352                         sizeof(*cpr->cp_desc_ring));
2353         cpr->cp_raw_cons = 0;
2354         cpr->valid = 0;
2355 }
2356
2357 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2358 {
2359         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2360         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2361         struct bnxt_ring *ring = rxr->rx_ring_struct;
2362         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2363
2364         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2365                 bnxt_hwrm_ring_free(bp, ring,
2366                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2367                 ring->fw_ring_id = INVALID_HW_RING_ID;
2368                 if (BNXT_HAS_RING_GRPS(bp))
2369                         bp->grp_info[queue_index].rx_fw_ring_id =
2370                                                         INVALID_HW_RING_ID;
2371                 memset(rxr->rx_desc_ring, 0,
2372                        rxr->rx_ring_struct->ring_size *
2373                        sizeof(*rxr->rx_desc_ring));
2374                 memset(rxr->rx_buf_ring, 0,
2375                        rxr->rx_ring_struct->ring_size *
2376                        sizeof(*rxr->rx_buf_ring));
2377                 rxr->rx_prod = 0;
2378         }
2379         ring = rxr->ag_ring_struct;
2380         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2381                 bnxt_hwrm_ring_free(bp, ring,
2382                                     BNXT_CHIP_THOR(bp) ?
2383                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2384                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2385                 ring->fw_ring_id = INVALID_HW_RING_ID;
2386                 memset(rxr->ag_buf_ring, 0,
2387                        rxr->ag_ring_struct->ring_size *
2388                        sizeof(*rxr->ag_buf_ring));
2389                 rxr->ag_prod = 0;
2390                 if (BNXT_HAS_RING_GRPS(bp))
2391                         bp->grp_info[queue_index].ag_fw_ring_id =
2392                                                         INVALID_HW_RING_ID;
2393         }
2394         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2395                 bnxt_free_cp_ring(bp, cpr);
2396
2397         if (BNXT_HAS_RING_GRPS(bp))
2398                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2399 }
2400
2401 static int
2402 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2403 {
2404         unsigned int i;
2405
2406         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2407                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2408                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2409                 struct bnxt_ring *ring = txr->tx_ring_struct;
2410                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2411
2412                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2413                         bnxt_hwrm_ring_free(bp, ring,
2414                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2415                         ring->fw_ring_id = INVALID_HW_RING_ID;
2416                         memset(txr->tx_desc_ring, 0,
2417                                         txr->tx_ring_struct->ring_size *
2418                                         sizeof(*txr->tx_desc_ring));
2419                         memset(txr->tx_buf_ring, 0,
2420                                         txr->tx_ring_struct->ring_size *
2421                                         sizeof(*txr->tx_buf_ring));
2422                         txr->tx_prod = 0;
2423                         txr->tx_cons = 0;
2424                 }
2425                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2426                         bnxt_free_cp_ring(bp, cpr);
2427                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2428                 }
2429         }
2430
2431         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2432                 bnxt_free_hwrm_rx_ring(bp, i);
2433
2434         return 0;
2435 }
2436
2437 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2438 {
2439         uint16_t i;
2440         uint32_t rc = 0;
2441
2442         if (!BNXT_HAS_RING_GRPS(bp))
2443                 return 0;
2444
2445         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2446                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2447                 if (rc)
2448                         return rc;
2449         }
2450         return rc;
2451 }
2452
2453 /*
2454  * HWRM utility functions
2455  */
2456
2457 void bnxt_free_hwrm_resources(struct bnxt *bp)
2458 {
2459         /* Release memzone */
2460         rte_free(bp->hwrm_cmd_resp_addr);
2461         rte_free(bp->hwrm_short_cmd_req_addr);
2462         bp->hwrm_cmd_resp_addr = NULL;
2463         bp->hwrm_short_cmd_req_addr = NULL;
2464         bp->hwrm_cmd_resp_dma_addr = 0;
2465         bp->hwrm_short_cmd_req_dma_addr = 0;
2466 }
2467
2468 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2469 {
2470         struct rte_pci_device *pdev = bp->pdev;
2471         char type[RTE_MEMZONE_NAMESIZE];
2472
2473         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2474                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2475         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2476         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2477         if (bp->hwrm_cmd_resp_addr == NULL)
2478                 return -ENOMEM;
2479         bp->hwrm_cmd_resp_dma_addr =
2480                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2481         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2482                 PMD_DRV_LOG(ERR,
2483                         "unable to map response address to physical memory\n");
2484                 return -ENOMEM;
2485         }
2486         rte_spinlock_init(&bp->hwrm_lock);
2487
2488         return 0;
2489 }
2490
2491 static int
2492 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2493 {
2494         struct bnxt_filter_info *filter;
2495         int rc = 0;
2496
2497         STAILQ_FOREACH(filter, &vnic->filter, next) {
2498                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2499                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2500                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2501                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2502                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2503                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2504                 bnxt_free_filter(bp, filter);
2505         }
2506         return rc;
2507 }
2508
2509 static int
2510 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2511 {
2512         struct bnxt_filter_info *filter;
2513         struct rte_flow *flow;
2514         int rc = 0;
2515
2516         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2517                 flow = STAILQ_FIRST(&vnic->flow_list);
2518                 filter = flow->filter;
2519                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2520                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2521                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2522                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2523                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2524                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2525
2526                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2527                 rte_free(flow);
2528         }
2529         return rc;
2530 }
2531
2532 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2533 {
2534         struct bnxt_filter_info *filter;
2535         int rc = 0;
2536
2537         STAILQ_FOREACH(filter, &vnic->filter, next) {
2538                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2539                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2540                                                      filter);
2541                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2542                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2543                                                          filter);
2544                 else
2545                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2546                                                      filter);
2547                 if (rc)
2548                         break;
2549         }
2550         return rc;
2551 }
2552
2553 static void
2554 bnxt_free_tunnel_ports(struct bnxt *bp)
2555 {
2556         if (bp->vxlan_port_cnt)
2557                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2558                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2559         bp->vxlan_port = 0;
2560         if (bp->geneve_port_cnt)
2561                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2562                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2563         bp->geneve_port = 0;
2564 }
2565
2566 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2567 {
2568         int i;
2569
2570         if (bp->vnic_info == NULL)
2571                 return;
2572
2573         /*
2574          * Cleanup VNICs in reverse order, to make sure the L2 filter
2575          * from vnic0 is last to be cleaned up.
2576          */
2577         for (i = bp->max_vnics - 1; i >= 0; i--) {
2578                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2579
2580                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2581                         continue;
2582
2583                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2584
2585                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2586
2587                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2588
2589                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2590
2591                 bnxt_hwrm_vnic_free(bp, vnic);
2592
2593                 rte_free(vnic->fw_grp_ids);
2594         }
2595         /* Ring resources */
2596         bnxt_free_all_hwrm_rings(bp);
2597         bnxt_free_all_hwrm_ring_grps(bp);
2598         bnxt_free_all_hwrm_stat_ctxs(bp);
2599         bnxt_free_tunnel_ports(bp);
2600 }
2601
2602 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2603 {
2604         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2605
2606         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2607                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2608
2609         switch (conf_link_speed) {
2610         case ETH_LINK_SPEED_10M_HD:
2611         case ETH_LINK_SPEED_100M_HD:
2612                 /* FALLTHROUGH */
2613                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2614         }
2615         return hw_link_duplex;
2616 }
2617
2618 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2619 {
2620         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2621 }
2622
2623 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2624 {
2625         uint16_t eth_link_speed = 0;
2626
2627         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2628                 return ETH_LINK_SPEED_AUTONEG;
2629
2630         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2631         case ETH_LINK_SPEED_100M:
2632         case ETH_LINK_SPEED_100M_HD:
2633                 /* FALLTHROUGH */
2634                 eth_link_speed =
2635                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2636                 break;
2637         case ETH_LINK_SPEED_1G:
2638                 eth_link_speed =
2639                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2640                 break;
2641         case ETH_LINK_SPEED_2_5G:
2642                 eth_link_speed =
2643                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2644                 break;
2645         case ETH_LINK_SPEED_10G:
2646                 eth_link_speed =
2647                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2648                 break;
2649         case ETH_LINK_SPEED_20G:
2650                 eth_link_speed =
2651                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2652                 break;
2653         case ETH_LINK_SPEED_25G:
2654                 eth_link_speed =
2655                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2656                 break;
2657         case ETH_LINK_SPEED_40G:
2658                 eth_link_speed =
2659                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2660                 break;
2661         case ETH_LINK_SPEED_50G:
2662                 eth_link_speed =
2663                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2664                 break;
2665         case ETH_LINK_SPEED_100G:
2666                 eth_link_speed =
2667                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2668                 break;
2669         default:
2670                 PMD_DRV_LOG(ERR,
2671                         "Unsupported link speed %d; default to AUTO\n",
2672                         conf_link_speed);
2673                 break;
2674         }
2675         return eth_link_speed;
2676 }
2677
2678 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2679                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2680                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2681                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2682
2683 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2684 {
2685         uint32_t one_speed;
2686
2687         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2688                 return 0;
2689
2690         if (link_speed & ETH_LINK_SPEED_FIXED) {
2691                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2692
2693                 if (one_speed & (one_speed - 1)) {
2694                         PMD_DRV_LOG(ERR,
2695                                 "Invalid advertised speeds (%u) for port %u\n",
2696                                 link_speed, port_id);
2697                         return -EINVAL;
2698                 }
2699                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2700                         PMD_DRV_LOG(ERR,
2701                                 "Unsupported advertised speed (%u) for port %u\n",
2702                                 link_speed, port_id);
2703                         return -EINVAL;
2704                 }
2705         } else {
2706                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2707                         PMD_DRV_LOG(ERR,
2708                                 "Unsupported advertised speeds (%u) for port %u\n",
2709                                 link_speed, port_id);
2710                         return -EINVAL;
2711                 }
2712         }
2713         return 0;
2714 }
2715
2716 static uint16_t
2717 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2718 {
2719         uint16_t ret = 0;
2720
2721         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2722                 if (bp->link_info.support_speeds)
2723                         return bp->link_info.support_speeds;
2724                 link_speed = BNXT_SUPPORTED_SPEEDS;
2725         }
2726
2727         if (link_speed & ETH_LINK_SPEED_100M)
2728                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2729         if (link_speed & ETH_LINK_SPEED_100M_HD)
2730                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2731         if (link_speed & ETH_LINK_SPEED_1G)
2732                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2733         if (link_speed & ETH_LINK_SPEED_2_5G)
2734                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2735         if (link_speed & ETH_LINK_SPEED_10G)
2736                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2737         if (link_speed & ETH_LINK_SPEED_20G)
2738                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2739         if (link_speed & ETH_LINK_SPEED_25G)
2740                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2741         if (link_speed & ETH_LINK_SPEED_40G)
2742                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2743         if (link_speed & ETH_LINK_SPEED_50G)
2744                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2745         if (link_speed & ETH_LINK_SPEED_100G)
2746                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2747         return ret;
2748 }
2749
2750 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2751 {
2752         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2753
2754         switch (hw_link_speed) {
2755         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2756                 eth_link_speed = ETH_SPEED_NUM_100M;
2757                 break;
2758         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2759                 eth_link_speed = ETH_SPEED_NUM_1G;
2760                 break;
2761         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2762                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2763                 break;
2764         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2765                 eth_link_speed = ETH_SPEED_NUM_10G;
2766                 break;
2767         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2768                 eth_link_speed = ETH_SPEED_NUM_20G;
2769                 break;
2770         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2771                 eth_link_speed = ETH_SPEED_NUM_25G;
2772                 break;
2773         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2774                 eth_link_speed = ETH_SPEED_NUM_40G;
2775                 break;
2776         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2777                 eth_link_speed = ETH_SPEED_NUM_50G;
2778                 break;
2779         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2780                 eth_link_speed = ETH_SPEED_NUM_100G;
2781                 break;
2782         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2783         default:
2784                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2785                         hw_link_speed);
2786                 break;
2787         }
2788         return eth_link_speed;
2789 }
2790
2791 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2792 {
2793         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2794
2795         switch (hw_link_duplex) {
2796         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2797         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2798                 /* FALLTHROUGH */
2799                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2800                 break;
2801         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2802                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2803                 break;
2804         default:
2805                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2806                         hw_link_duplex);
2807                 break;
2808         }
2809         return eth_link_duplex;
2810 }
2811
2812 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2813 {
2814         int rc = 0;
2815         struct bnxt_link_info *link_info = &bp->link_info;
2816
2817         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2818         if (rc) {
2819                 PMD_DRV_LOG(ERR,
2820                         "Get link config failed with rc %d\n", rc);
2821                 goto exit;
2822         }
2823         if (link_info->link_speed)
2824                 link->link_speed =
2825                         bnxt_parse_hw_link_speed(link_info->link_speed);
2826         else
2827                 link->link_speed = ETH_SPEED_NUM_NONE;
2828         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2829         link->link_status = link_info->link_up;
2830         link->link_autoneg = link_info->auto_mode ==
2831                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2832                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2833 exit:
2834         return rc;
2835 }
2836
2837 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2838 {
2839         int rc = 0;
2840         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2841         struct bnxt_link_info link_req;
2842         uint16_t speed, autoneg;
2843
2844         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2845                 return 0;
2846
2847         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2848                         bp->eth_dev->data->port_id);
2849         if (rc)
2850                 goto error;
2851
2852         memset(&link_req, 0, sizeof(link_req));
2853         link_req.link_up = link_up;
2854         if (!link_up)
2855                 goto port_phy_cfg;
2856
2857         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2858         if (BNXT_CHIP_THOR(bp) &&
2859             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2860                 /* 40G is not supported as part of media auto detect.
2861                  * The speed should be forced and autoneg disabled
2862                  * to configure 40G speed.
2863                  */
2864                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2865                 autoneg = 0;
2866         }
2867
2868         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2869         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2870         /* Autoneg can be done only when the FW allows.
2871          * When user configures fixed speed of 40G and later changes to
2872          * any other speed, auto_link_speed/force_link_speed is still set
2873          * to 40G until link comes up at new speed.
2874          */
2875         if (autoneg == 1 &&
2876             !(!BNXT_CHIP_THOR(bp) &&
2877               (bp->link_info.auto_link_speed ||
2878                bp->link_info.force_link_speed))) {
2879                 link_req.phy_flags |=
2880                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2881                 link_req.auto_link_speed_mask =
2882                         bnxt_parse_eth_link_speed_mask(bp,
2883                                                        dev_conf->link_speeds);
2884         } else {
2885                 if (bp->link_info.phy_type ==
2886                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2887                     bp->link_info.phy_type ==
2888                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2889                     bp->link_info.media_type ==
2890                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2891                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2892                         return -EINVAL;
2893                 }
2894
2895                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2896                 /* If user wants a particular speed try that first. */
2897                 if (speed)
2898                         link_req.link_speed = speed;
2899                 else if (bp->link_info.force_link_speed)
2900                         link_req.link_speed = bp->link_info.force_link_speed;
2901                 else
2902                         link_req.link_speed = bp->link_info.auto_link_speed;
2903         }
2904         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2905         link_req.auto_pause = bp->link_info.auto_pause;
2906         link_req.force_pause = bp->link_info.force_pause;
2907
2908 port_phy_cfg:
2909         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2910         if (rc) {
2911                 PMD_DRV_LOG(ERR,
2912                         "Set link config failed with rc %d\n", rc);
2913         }
2914
2915 error:
2916         return rc;
2917 }
2918
2919 /* JIRA 22088 */
2920 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2921 {
2922         struct hwrm_func_qcfg_input req = {0};
2923         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2924         uint16_t flags;
2925         int rc = 0;
2926
2927         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2928         req.fid = rte_cpu_to_le_16(0xffff);
2929
2930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2931
2932         HWRM_CHECK_RESULT();
2933
2934         /* Hard Coded.. 0xfff VLAN ID mask */
2935         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2936         flags = rte_le_to_cpu_16(resp->flags);
2937         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2938                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2939
2940         if (BNXT_VF(bp) &&
2941             !BNXT_VF_IS_TRUSTED(bp) &&
2942             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2943                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2944                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2945         } else if (BNXT_VF(bp) &&
2946                    BNXT_VF_IS_TRUSTED(bp) &&
2947                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2948                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2949                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2950         }
2951
2952         if (mtu)
2953                 *mtu = rte_le_to_cpu_16(resp->mtu);
2954
2955         switch (resp->port_partition_type) {
2956         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2957         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2958         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2959                 /* FALLTHROUGH */
2960                 bp->flags |= BNXT_FLAG_NPAR_PF;
2961                 break;
2962         default:
2963                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
2964                 break;
2965         }
2966
2967         HWRM_UNLOCK();
2968
2969         return rc;
2970 }
2971
2972 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2973                                    struct hwrm_func_qcaps_output *qcaps)
2974 {
2975         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2976         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2977                sizeof(qcaps->mac_address));
2978         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2979         qcaps->max_rx_rings = fcfg->num_rx_rings;
2980         qcaps->max_tx_rings = fcfg->num_tx_rings;
2981         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2982         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2983         qcaps->max_vfs = 0;
2984         qcaps->first_vf_id = 0;
2985         qcaps->max_vnics = fcfg->num_vnics;
2986         qcaps->max_decap_records = 0;
2987         qcaps->max_encap_records = 0;
2988         qcaps->max_tx_wm_flows = 0;
2989         qcaps->max_tx_em_flows = 0;
2990         qcaps->max_rx_wm_flows = 0;
2991         qcaps->max_rx_em_flows = 0;
2992         qcaps->max_flow_id = 0;
2993         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2994         qcaps->max_sp_tx_rings = 0;
2995         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2996 }
2997
2998 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2999 {
3000         struct hwrm_func_cfg_input req = {0};
3001         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3002         uint32_t enables;
3003         int rc;
3004
3005         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3006                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3007                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3008                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3009                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3010                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3011                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3012                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3013                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3014
3015         if (BNXT_HAS_RING_GRPS(bp)) {
3016                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3017                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3018         } else if (BNXT_HAS_NQ(bp)) {
3019                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3020                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3021         }
3022
3023         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3024         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3025         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3026         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3027         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3028         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3029         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3030         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3031         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3032         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3033         req.fid = rte_cpu_to_le_16(0xffff);
3034         req.enables = rte_cpu_to_le_32(enables);
3035
3036         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3037
3038         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3039
3040         HWRM_CHECK_RESULT();
3041         HWRM_UNLOCK();
3042
3043         return rc;
3044 }
3045
3046 static void populate_vf_func_cfg_req(struct bnxt *bp,
3047                                      struct hwrm_func_cfg_input *req,
3048                                      int num_vfs)
3049 {
3050         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3051                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3052                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3053                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3054                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3055                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3056                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3057                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3058                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3059                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3060
3061         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3062                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3063                                     BNXT_NUM_VLANS);
3064         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3065         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3066                                                 (num_vfs + 1));
3067         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3068         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3069                                                (num_vfs + 1));
3070         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3071         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3072         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3073         /* TODO: For now, do not support VMDq/RFS on VFs. */
3074         req->num_vnics = rte_cpu_to_le_16(1);
3075         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3076                                                  (num_vfs + 1));
3077 }
3078
3079 static void add_random_mac_if_needed(struct bnxt *bp,
3080                                      struct hwrm_func_cfg_input *cfg_req,
3081                                      int vf)
3082 {
3083         struct rte_ether_addr mac;
3084
3085         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3086                 return;
3087
3088         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3089                 cfg_req->enables |=
3090                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3091                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3092                 bp->pf.vf_info[vf].random_mac = true;
3093         } else {
3094                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3095                         RTE_ETHER_ADDR_LEN);
3096         }
3097 }
3098
3099 static void reserve_resources_from_vf(struct bnxt *bp,
3100                                       struct hwrm_func_cfg_input *cfg_req,
3101                                       int vf)
3102 {
3103         struct hwrm_func_qcaps_input req = {0};
3104         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3105         int rc;
3106
3107         /* Get the actual allocated values now */
3108         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3109         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3111
3112         if (rc) {
3113                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3114                 copy_func_cfg_to_qcaps(cfg_req, resp);
3115         } else if (resp->error_code) {
3116                 rc = rte_le_to_cpu_16(resp->error_code);
3117                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3118                 copy_func_cfg_to_qcaps(cfg_req, resp);
3119         }
3120
3121         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3122         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3123         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3124         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3125         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3126         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3127         /*
3128          * TODO: While not supporting VMDq with VFs, max_vnics is always
3129          * forced to 1 in this case
3130          */
3131         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3132         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3133
3134         HWRM_UNLOCK();
3135 }
3136
3137 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3138 {
3139         struct hwrm_func_qcfg_input req = {0};
3140         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3141         int rc;
3142
3143         /* Check for zero MAC address */
3144         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3145         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3147         HWRM_CHECK_RESULT();
3148         rc = rte_le_to_cpu_16(resp->vlan);
3149
3150         HWRM_UNLOCK();
3151
3152         return rc;
3153 }
3154
3155 static int update_pf_resource_max(struct bnxt *bp)
3156 {
3157         struct hwrm_func_qcfg_input req = {0};
3158         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3159         int rc;
3160
3161         /* And copy the allocated numbers into the pf struct */
3162         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3163         req.fid = rte_cpu_to_le_16(0xffff);
3164         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3165         HWRM_CHECK_RESULT();
3166
3167         /* Only TX ring value reflects actual allocation? TODO */
3168         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3169         bp->pf.evb_mode = resp->evb_mode;
3170
3171         HWRM_UNLOCK();
3172
3173         return rc;
3174 }
3175
3176 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3177 {
3178         int rc;
3179
3180         if (!BNXT_PF(bp)) {
3181                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3182                 return -EINVAL;
3183         }
3184
3185         rc = bnxt_hwrm_func_qcaps(bp);
3186         if (rc)
3187                 return rc;
3188
3189         bp->pf.func_cfg_flags &=
3190                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3191                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3192         bp->pf.func_cfg_flags |=
3193                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3194         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3195         rc = __bnxt_hwrm_func_qcaps(bp);
3196         return rc;
3197 }
3198
3199 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3200 {
3201         struct hwrm_func_cfg_input req = {0};
3202         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3203         int i;
3204         size_t sz;
3205         int rc = 0;
3206         size_t req_buf_sz;
3207
3208         if (!BNXT_PF(bp)) {
3209                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3210                 return -EINVAL;
3211         }
3212
3213         rc = bnxt_hwrm_func_qcaps(bp);
3214
3215         if (rc)
3216                 return rc;
3217
3218         bp->pf.active_vfs = num_vfs;
3219
3220         /*
3221          * First, configure the PF to only use one TX ring.  This ensures that
3222          * there are enough rings for all VFs.
3223          *
3224          * If we don't do this, when we call func_alloc() later, we will lock
3225          * extra rings to the PF that won't be available during func_cfg() of
3226          * the VFs.
3227          *
3228          * This has been fixed with firmware versions above 20.6.54
3229          */
3230         bp->pf.func_cfg_flags &=
3231                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3232                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3233         bp->pf.func_cfg_flags |=
3234                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3235         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3236         if (rc)
3237                 return rc;
3238
3239         /*
3240          * Now, create and register a buffer to hold forwarded VF requests
3241          */
3242         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3243         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3244                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3245         if (bp->pf.vf_req_buf == NULL) {
3246                 rc = -ENOMEM;
3247                 goto error_free;
3248         }
3249         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3250                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3251         for (i = 0; i < num_vfs; i++)
3252                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3253                                         (i * HWRM_MAX_REQ_LEN);
3254
3255         rc = bnxt_hwrm_func_buf_rgtr(bp);
3256         if (rc)
3257                 goto error_free;
3258
3259         populate_vf_func_cfg_req(bp, &req, num_vfs);
3260
3261         bp->pf.active_vfs = 0;
3262         for (i = 0; i < num_vfs; i++) {
3263                 add_random_mac_if_needed(bp, &req, i);
3264
3265                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3266                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3267                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3268                 rc = bnxt_hwrm_send_message(bp,
3269                                             &req,
3270                                             sizeof(req),
3271                                             BNXT_USE_CHIMP_MB);
3272
3273                 /* Clear enable flag for next pass */
3274                 req.enables &= ~rte_cpu_to_le_32(
3275                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3276
3277                 if (rc || resp->error_code) {
3278                         PMD_DRV_LOG(ERR,
3279                                 "Failed to initizlie VF %d\n", i);
3280                         PMD_DRV_LOG(ERR,
3281                                 "Not all VFs available. (%d, %d)\n",
3282                                 rc, resp->error_code);
3283                         HWRM_UNLOCK();
3284                         break;
3285                 }
3286
3287                 HWRM_UNLOCK();
3288
3289                 reserve_resources_from_vf(bp, &req, i);
3290                 bp->pf.active_vfs++;
3291                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3292         }
3293
3294         /*
3295          * Now configure the PF to use "the rest" of the resources
3296          * We're using STD_TX_RING_MODE here though which will limit the TX
3297          * rings.  This will allow QoS to function properly.  Not setting this
3298          * will cause PF rings to break bandwidth settings.
3299          */
3300         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3301         if (rc)
3302                 goto error_free;
3303
3304         rc = update_pf_resource_max(bp);
3305         if (rc)
3306                 goto error_free;
3307
3308         return rc;
3309
3310 error_free:
3311         bnxt_hwrm_func_buf_unrgtr(bp);
3312         return rc;
3313 }
3314
3315 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3316 {
3317         struct hwrm_func_cfg_input req = {0};
3318         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3319         int rc;
3320
3321         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3322
3323         req.fid = rte_cpu_to_le_16(0xffff);
3324         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3325         req.evb_mode = bp->pf.evb_mode;
3326
3327         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3328         HWRM_CHECK_RESULT();
3329         HWRM_UNLOCK();
3330
3331         return rc;
3332 }
3333
3334 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3335                                 uint8_t tunnel_type)
3336 {
3337         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3338         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3339         int rc = 0;
3340
3341         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3342         req.tunnel_type = tunnel_type;
3343         req.tunnel_dst_port_val = port;
3344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3345         HWRM_CHECK_RESULT();
3346
3347         switch (tunnel_type) {
3348         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3349                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3350                 bp->vxlan_port = port;
3351                 break;
3352         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3353                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3354                 bp->geneve_port = port;
3355                 break;
3356         default:
3357                 break;
3358         }
3359
3360         HWRM_UNLOCK();
3361
3362         return rc;
3363 }
3364
3365 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3366                                 uint8_t tunnel_type)
3367 {
3368         struct hwrm_tunnel_dst_port_free_input req = {0};
3369         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3370         int rc = 0;
3371
3372         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3373
3374         req.tunnel_type = tunnel_type;
3375         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3377
3378         HWRM_CHECK_RESULT();
3379         HWRM_UNLOCK();
3380
3381         return rc;
3382 }
3383
3384 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3385                                         uint32_t flags)
3386 {
3387         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3388         struct hwrm_func_cfg_input req = {0};
3389         int rc;
3390
3391         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3392
3393         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3394         req.flags = rte_cpu_to_le_32(flags);
3395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3396
3397         HWRM_CHECK_RESULT();
3398         HWRM_UNLOCK();
3399
3400         return rc;
3401 }
3402
3403 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3404 {
3405         uint32_t *flag = flagp;
3406
3407         vnic->flags = *flag;
3408 }
3409
3410 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3411 {
3412         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3413 }
3414
3415 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3416 {
3417         int rc = 0;
3418         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3419         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3420
3421         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3422
3423         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3424         req.req_buf_page_size = rte_cpu_to_le_16(
3425                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3426         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3427         req.req_buf_page_addr0 =
3428                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3429         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3430                 PMD_DRV_LOG(ERR,
3431                         "unable to map buffer address to physical memory\n");
3432                 return -ENOMEM;
3433         }
3434
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436
3437         HWRM_CHECK_RESULT();
3438         HWRM_UNLOCK();
3439
3440         return rc;
3441 }
3442
3443 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3444 {
3445         int rc = 0;
3446         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3447         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3448
3449         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3450                 return 0;
3451
3452         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3453
3454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3455
3456         HWRM_CHECK_RESULT();
3457         HWRM_UNLOCK();
3458
3459         return rc;
3460 }
3461
3462 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3463 {
3464         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3465         struct hwrm_func_cfg_input req = {0};
3466         int rc;
3467
3468         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3469
3470         req.fid = rte_cpu_to_le_16(0xffff);
3471         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3472         req.enables = rte_cpu_to_le_32(
3473                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3474         req.async_event_cr = rte_cpu_to_le_16(
3475                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3477
3478         HWRM_CHECK_RESULT();
3479         HWRM_UNLOCK();
3480
3481         return rc;
3482 }
3483
3484 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3485 {
3486         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3487         struct hwrm_func_vf_cfg_input req = {0};
3488         int rc;
3489
3490         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3491
3492         req.enables = rte_cpu_to_le_32(
3493                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3494         req.async_event_cr = rte_cpu_to_le_16(
3495                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3496         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3497
3498         HWRM_CHECK_RESULT();
3499         HWRM_UNLOCK();
3500
3501         return rc;
3502 }
3503
3504 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3505 {
3506         struct hwrm_func_cfg_input req = {0};
3507         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3508         uint16_t dflt_vlan, fid;
3509         uint32_t func_cfg_flags;
3510         int rc = 0;
3511
3512         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3513
3514         if (is_vf) {
3515                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3516                 fid = bp->pf.vf_info[vf].fid;
3517                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3518         } else {
3519                 fid = rte_cpu_to_le_16(0xffff);
3520                 func_cfg_flags = bp->pf.func_cfg_flags;
3521                 dflt_vlan = bp->vlan;
3522         }
3523
3524         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3525         req.fid = rte_cpu_to_le_16(fid);
3526         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3527         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3528
3529         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3530
3531         HWRM_CHECK_RESULT();
3532         HWRM_UNLOCK();
3533
3534         return rc;
3535 }
3536
3537 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3538                         uint16_t max_bw, uint16_t enables)
3539 {
3540         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3541         struct hwrm_func_cfg_input req = {0};
3542         int rc;
3543
3544         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3545
3546         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3547         req.enables |= rte_cpu_to_le_32(enables);
3548         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3549         req.max_bw = rte_cpu_to_le_32(max_bw);
3550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3551
3552         HWRM_CHECK_RESULT();
3553         HWRM_UNLOCK();
3554
3555         return rc;
3556 }
3557
3558 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3559 {
3560         struct hwrm_func_cfg_input req = {0};
3561         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3562         int rc = 0;
3563
3564         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3565
3566         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3567         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3568         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3569         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3570
3571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3572
3573         HWRM_CHECK_RESULT();
3574         HWRM_UNLOCK();
3575
3576         return rc;
3577 }
3578
3579 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3580 {
3581         int rc;
3582
3583         if (BNXT_PF(bp))
3584                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3585         else
3586                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3587
3588         return rc;
3589 }
3590
3591 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3592                               void *encaped, size_t ec_size)
3593 {
3594         int rc = 0;
3595         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3596         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3597
3598         if (ec_size > sizeof(req.encap_request))
3599                 return -1;
3600
3601         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3602
3603         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3604         memcpy(req.encap_request, encaped, ec_size);
3605
3606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3607
3608         HWRM_CHECK_RESULT();
3609         HWRM_UNLOCK();
3610
3611         return rc;
3612 }
3613
3614 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3615                                        struct rte_ether_addr *mac)
3616 {
3617         struct hwrm_func_qcfg_input req = {0};
3618         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3619         int rc;
3620
3621         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3622
3623         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3624         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625
3626         HWRM_CHECK_RESULT();
3627
3628         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3629
3630         HWRM_UNLOCK();
3631
3632         return rc;
3633 }
3634
3635 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3636                             void *encaped, size_t ec_size)
3637 {
3638         int rc = 0;
3639         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3640         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3641
3642         if (ec_size > sizeof(req.encap_request))
3643                 return -1;
3644
3645         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3646
3647         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3648         memcpy(req.encap_request, encaped, ec_size);
3649
3650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651
3652         HWRM_CHECK_RESULT();
3653         HWRM_UNLOCK();
3654
3655         return rc;
3656 }
3657
3658 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3659                          struct rte_eth_stats *stats, uint8_t rx)
3660 {
3661         int rc = 0;
3662         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3663         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3664
3665         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3666
3667         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3668
3669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3670
3671         HWRM_CHECK_RESULT();
3672
3673         if (rx) {
3674                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3675                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3676                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3677                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3678                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3679                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3680                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3681                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3682         } else {
3683                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3684                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3685                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3686                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3687                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3688                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3689         }
3690
3691         HWRM_UNLOCK();
3692
3693         return rc;
3694 }
3695
3696 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3697 {
3698         struct hwrm_port_qstats_input req = {0};
3699         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3700         struct bnxt_pf_info *pf = &bp->pf;
3701         int rc;
3702
3703         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3704
3705         req.port_id = rte_cpu_to_le_16(pf->port_id);
3706         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3707         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3708         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3709
3710         HWRM_CHECK_RESULT();
3711         HWRM_UNLOCK();
3712
3713         return rc;
3714 }
3715
3716 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3717 {
3718         struct hwrm_port_clr_stats_input req = {0};
3719         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3720         struct bnxt_pf_info *pf = &bp->pf;
3721         int rc;
3722
3723         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3724         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3725             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3726                 return 0;
3727
3728         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3729
3730         req.port_id = rte_cpu_to_le_16(pf->port_id);
3731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3732
3733         HWRM_CHECK_RESULT();
3734         HWRM_UNLOCK();
3735
3736         return rc;
3737 }
3738
3739 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3740 {
3741         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3742         struct hwrm_port_led_qcaps_input req = {0};
3743         int rc;
3744
3745         if (BNXT_VF(bp))
3746                 return 0;
3747
3748         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3749         req.port_id = bp->pf.port_id;
3750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3751
3752         HWRM_CHECK_RESULT();
3753
3754         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3755                 unsigned int i;
3756
3757                 bp->num_leds = resp->num_leds;
3758                 memcpy(bp->leds, &resp->led0_id,
3759                         sizeof(bp->leds[0]) * bp->num_leds);
3760                 for (i = 0; i < bp->num_leds; i++) {
3761                         struct bnxt_led_info *led = &bp->leds[i];
3762
3763                         uint16_t caps = led->led_state_caps;
3764
3765                         if (!led->led_group_id ||
3766                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3767                                 bp->num_leds = 0;
3768                                 break;
3769                         }
3770                 }
3771         }
3772
3773         HWRM_UNLOCK();
3774
3775         return rc;
3776 }
3777
3778 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3779 {
3780         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3781         struct hwrm_port_led_cfg_input req = {0};
3782         struct bnxt_led_cfg *led_cfg;
3783         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3784         uint16_t duration = 0;
3785         int rc, i;
3786
3787         if (!bp->num_leds || BNXT_VF(bp))
3788                 return -EOPNOTSUPP;
3789
3790         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3791
3792         if (led_on) {
3793                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3794                 duration = rte_cpu_to_le_16(500);
3795         }
3796         req.port_id = bp->pf.port_id;
3797         req.num_leds = bp->num_leds;
3798         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3799         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3800                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3801                 led_cfg->led_id = bp->leds[i].led_id;
3802                 led_cfg->led_state = led_state;
3803                 led_cfg->led_blink_on = duration;
3804                 led_cfg->led_blink_off = duration;
3805                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3806         }
3807
3808         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3809
3810         HWRM_CHECK_RESULT();
3811         HWRM_UNLOCK();
3812
3813         return rc;
3814 }
3815
3816 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3817                                uint32_t *length)
3818 {
3819         int rc;
3820         struct hwrm_nvm_get_dir_info_input req = {0};
3821         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3822
3823         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3824
3825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3826
3827         HWRM_CHECK_RESULT();
3828
3829         *entries = rte_le_to_cpu_32(resp->entries);
3830         *length = rte_le_to_cpu_32(resp->entry_length);
3831
3832         HWRM_UNLOCK();
3833         return rc;
3834 }
3835
3836 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3837 {
3838         int rc;
3839         uint32_t dir_entries;
3840         uint32_t entry_length;
3841         uint8_t *buf;
3842         size_t buflen;
3843         rte_iova_t dma_handle;
3844         struct hwrm_nvm_get_dir_entries_input req = {0};
3845         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3846
3847         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3848         if (rc != 0)
3849                 return rc;
3850
3851         *data++ = dir_entries;
3852         *data++ = entry_length;
3853         len -= 2;
3854         memset(data, 0xff, len);
3855
3856         buflen = dir_entries * entry_length;
3857         buf = rte_malloc("nvm_dir", buflen, 0);
3858         if (buf == NULL)
3859                 return -ENOMEM;
3860         dma_handle = rte_malloc_virt2iova(buf);
3861         if (dma_handle == RTE_BAD_IOVA) {
3862                 PMD_DRV_LOG(ERR,
3863                         "unable to map response address to physical memory\n");
3864                 return -ENOMEM;
3865         }
3866         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3867         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3869
3870         if (rc == 0)
3871                 memcpy(data, buf, len > buflen ? buflen : len);
3872
3873         rte_free(buf);
3874         HWRM_CHECK_RESULT();
3875         HWRM_UNLOCK();
3876
3877         return rc;
3878 }
3879
3880 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3881                              uint32_t offset, uint32_t length,
3882                              uint8_t *data)
3883 {
3884         int rc;
3885         uint8_t *buf;
3886         rte_iova_t dma_handle;
3887         struct hwrm_nvm_read_input req = {0};
3888         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3889
3890         buf = rte_malloc("nvm_item", length, 0);
3891         if (!buf)
3892                 return -ENOMEM;
3893
3894         dma_handle = rte_malloc_virt2iova(buf);
3895         if (dma_handle == RTE_BAD_IOVA) {
3896                 PMD_DRV_LOG(ERR,
3897                         "unable to map response address to physical memory\n");
3898                 return -ENOMEM;
3899         }
3900         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3901         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3902         req.dir_idx = rte_cpu_to_le_16(index);
3903         req.offset = rte_cpu_to_le_32(offset);
3904         req.len = rte_cpu_to_le_32(length);
3905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3906         if (rc == 0)
3907                 memcpy(data, buf, length);
3908
3909         rte_free(buf);
3910         HWRM_CHECK_RESULT();
3911         HWRM_UNLOCK();
3912
3913         return rc;
3914 }
3915
3916 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3917 {
3918         int rc;
3919         struct hwrm_nvm_erase_dir_entry_input req = {0};
3920         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3921
3922         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3923         req.dir_idx = rte_cpu_to_le_16(index);
3924         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3925         HWRM_CHECK_RESULT();
3926         HWRM_UNLOCK();
3927
3928         return rc;
3929 }
3930
3931
3932 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3933                           uint16_t dir_ordinal, uint16_t dir_ext,
3934                           uint16_t dir_attr, const uint8_t *data,
3935                           size_t data_len)
3936 {
3937         int rc;
3938         struct hwrm_nvm_write_input req = {0};
3939         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3940         rte_iova_t dma_handle;
3941         uint8_t *buf;
3942
3943         buf = rte_malloc("nvm_write", data_len, 0);
3944         if (!buf)
3945                 return -ENOMEM;
3946
3947         dma_handle = rte_malloc_virt2iova(buf);
3948         if (dma_handle == RTE_BAD_IOVA) {
3949                 PMD_DRV_LOG(ERR,
3950                         "unable to map response address to physical memory\n");
3951                 return -ENOMEM;
3952         }
3953         memcpy(buf, data, data_len);
3954
3955         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3956
3957         req.dir_type = rte_cpu_to_le_16(dir_type);
3958         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3959         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3960         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3961         req.dir_data_length = rte_cpu_to_le_32(data_len);
3962         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3963
3964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3965
3966         rte_free(buf);
3967         HWRM_CHECK_RESULT();
3968         HWRM_UNLOCK();
3969
3970         return rc;
3971 }
3972
3973 static void
3974 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3975 {
3976         uint32_t *count = cbdata;
3977
3978         *count = *count + 1;
3979 }
3980
3981 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3982                                      struct bnxt_vnic_info *vnic __rte_unused)
3983 {
3984         return 0;
3985 }
3986
3987 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3988 {
3989         uint32_t count = 0;
3990
3991         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3992             &count, bnxt_vnic_count_hwrm_stub);
3993
3994         return count;
3995 }
3996
3997 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3998                                         uint16_t *vnic_ids)
3999 {
4000         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4001         struct hwrm_func_vf_vnic_ids_query_output *resp =
4002                                                 bp->hwrm_cmd_resp_addr;
4003         int rc;
4004
4005         /* First query all VNIC ids */
4006         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4007
4008         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4009         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4010         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4011
4012         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4013                 HWRM_UNLOCK();
4014                 PMD_DRV_LOG(ERR,
4015                 "unable to map VNIC ID table address to physical memory\n");
4016                 return -ENOMEM;
4017         }
4018         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4019         HWRM_CHECK_RESULT();
4020         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4021
4022         HWRM_UNLOCK();
4023
4024         return rc;
4025 }
4026
4027 /*
4028  * This function queries the VNIC IDs  for a specified VF. It then calls
4029  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4030  * Then it calls the hwrm_cb function to program this new vnic configuration.
4031  */
4032 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4033         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4034         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4035 {
4036         struct bnxt_vnic_info vnic;
4037         int rc = 0;
4038         int i, num_vnic_ids;
4039         uint16_t *vnic_ids;
4040         size_t vnic_id_sz;
4041         size_t sz;
4042
4043         /* First query all VNIC ids */
4044         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4045         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4046                         RTE_CACHE_LINE_SIZE);
4047         if (vnic_ids == NULL)
4048                 return -ENOMEM;
4049
4050         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4051                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4052
4053         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4054
4055         if (num_vnic_ids < 0)
4056                 return num_vnic_ids;
4057
4058         /* Retrieve VNIC, update bd_stall then update */
4059
4060         for (i = 0; i < num_vnic_ids; i++) {
4061                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4062                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4063                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4064                 if (rc)
4065                         break;
4066                 if (vnic.mru <= 4)      /* Indicates unallocated */
4067                         continue;
4068
4069                 vnic_cb(&vnic, cbdata);
4070
4071                 rc = hwrm_cb(bp, &vnic);
4072                 if (rc)
4073                         break;
4074         }
4075
4076         rte_free(vnic_ids);
4077
4078         return rc;
4079 }
4080
4081 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4082                                               bool on)
4083 {
4084         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4085         struct hwrm_func_cfg_input req = {0};
4086         int rc;
4087
4088         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4089
4090         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4091         req.enables |= rte_cpu_to_le_32(
4092                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4093         req.vlan_antispoof_mode = on ?
4094                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4095                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4097
4098         HWRM_CHECK_RESULT();
4099         HWRM_UNLOCK();
4100
4101         return rc;
4102 }
4103
4104 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4105 {
4106         struct bnxt_vnic_info vnic;
4107         uint16_t *vnic_ids;
4108         size_t vnic_id_sz;
4109         int num_vnic_ids, i;
4110         size_t sz;
4111         int rc;
4112
4113         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4114         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4115                         RTE_CACHE_LINE_SIZE);
4116         if (vnic_ids == NULL)
4117                 return -ENOMEM;
4118
4119         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4120                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4121
4122         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4123         if (rc <= 0)
4124                 goto exit;
4125         num_vnic_ids = rc;
4126
4127         /*
4128          * Loop through to find the default VNIC ID.
4129          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4130          * by sending the hwrm_func_qcfg command to the firmware.
4131          */
4132         for (i = 0; i < num_vnic_ids; i++) {
4133                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4134                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4135                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4136                                         bp->pf.first_vf_id + vf);
4137                 if (rc)
4138                         goto exit;
4139                 if (vnic.func_default) {
4140                         rte_free(vnic_ids);
4141                         return vnic.fw_vnic_id;
4142                 }
4143         }
4144         /* Could not find a default VNIC. */
4145         PMD_DRV_LOG(ERR, "No default VNIC\n");
4146 exit:
4147         rte_free(vnic_ids);
4148         return rc;
4149 }
4150
4151 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4152                          uint16_t dst_id,
4153                          struct bnxt_filter_info *filter)
4154 {
4155         int rc = 0;
4156         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4157         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4158         uint32_t enables = 0;
4159
4160         if (filter->fw_em_filter_id != UINT64_MAX)
4161                 bnxt_hwrm_clear_em_filter(bp, filter);
4162
4163         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4164
4165         req.flags = rte_cpu_to_le_32(filter->flags);
4166
4167         enables = filter->enables |
4168               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4169         req.dst_id = rte_cpu_to_le_16(dst_id);
4170
4171         if (filter->ip_addr_type) {
4172                 req.ip_addr_type = filter->ip_addr_type;
4173                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4174         }
4175         if (enables &
4176             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4177                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4178         if (enables &
4179             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4180                 memcpy(req.src_macaddr, filter->src_macaddr,
4181                        RTE_ETHER_ADDR_LEN);
4182         if (enables &
4183             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4184                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4185                        RTE_ETHER_ADDR_LEN);
4186         if (enables &
4187             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4188                 req.ovlan_vid = filter->l2_ovlan;
4189         if (enables &
4190             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4191                 req.ivlan_vid = filter->l2_ivlan;
4192         if (enables &
4193             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4194                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4195         if (enables &
4196             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4197                 req.ip_protocol = filter->ip_protocol;
4198         if (enables &
4199             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4200                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4201         if (enables &
4202             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4203                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4204         if (enables &
4205             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4206                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4207         if (enables &
4208             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4209                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4210         if (enables &
4211             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4212                 req.mirror_vnic_id = filter->mirror_vnic_id;
4213
4214         req.enables = rte_cpu_to_le_32(enables);
4215
4216         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4217
4218         HWRM_CHECK_RESULT();
4219
4220         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4221         HWRM_UNLOCK();
4222
4223         return rc;
4224 }
4225
4226 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4227 {
4228         int rc = 0;
4229         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4230         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4231
4232         if (filter->fw_em_filter_id == UINT64_MAX)
4233                 return 0;
4234
4235         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4236
4237         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4238
4239         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4240
4241         HWRM_CHECK_RESULT();
4242         HWRM_UNLOCK();
4243
4244         filter->fw_em_filter_id = UINT64_MAX;
4245         filter->fw_l2_filter_id = UINT64_MAX;
4246
4247         return 0;
4248 }
4249
4250 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4251                          uint16_t dst_id,
4252                          struct bnxt_filter_info *filter)
4253 {
4254         int rc = 0;
4255         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4256         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4257                                                 bp->hwrm_cmd_resp_addr;
4258         uint32_t enables = 0;
4259
4260         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4261                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4262
4263         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4264
4265         req.flags = rte_cpu_to_le_32(filter->flags);
4266
4267         enables = filter->enables |
4268               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4269         req.dst_id = rte_cpu_to_le_16(dst_id);
4270
4271         if (filter->ip_addr_type) {
4272                 req.ip_addr_type = filter->ip_addr_type;
4273                 enables |=
4274                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4275         }
4276         if (enables &
4277             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4278                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4279         if (enables &
4280             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4281                 memcpy(req.src_macaddr, filter->src_macaddr,
4282                        RTE_ETHER_ADDR_LEN);
4283         if (enables &
4284             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4285                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4286         if (enables &
4287             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4288                 req.ip_protocol = filter->ip_protocol;
4289         if (enables &
4290             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4291                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4292         if (enables &
4293             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4294                 req.src_ipaddr_mask[0] =
4295                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4296         if (enables &
4297             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4298                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4299         if (enables &
4300             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4301                 req.dst_ipaddr_mask[0] =
4302                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4303         if (enables &
4304             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4305                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4306         if (enables &
4307             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4308                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4309         if (enables &
4310             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4311                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4312         if (enables &
4313             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4314                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4315         if (enables &
4316             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4317                 req.mirror_vnic_id = filter->mirror_vnic_id;
4318
4319         req.enables = rte_cpu_to_le_32(enables);
4320
4321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4322
4323         HWRM_CHECK_RESULT();
4324
4325         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4326         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4327         HWRM_UNLOCK();
4328
4329         return rc;
4330 }
4331
4332 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4333                                 struct bnxt_filter_info *filter)
4334 {
4335         int rc = 0;
4336         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4337         struct hwrm_cfa_ntuple_filter_free_output *resp =
4338                                                 bp->hwrm_cmd_resp_addr;
4339
4340         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4341                 return 0;
4342
4343         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4344
4345         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4346
4347         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4348
4349         HWRM_CHECK_RESULT();
4350         HWRM_UNLOCK();
4351
4352         filter->fw_ntuple_filter_id = UINT64_MAX;
4353
4354         return 0;
4355 }
4356
4357 static int
4358 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4359 {
4360         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4361         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4362         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4363         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4364         uint16_t *ring_tbl = vnic->rss_table;
4365         int nr_ctxs = vnic->num_lb_ctxts;
4366         int max_rings = bp->rx_nr_rings;
4367         int i, j, k, cnt;
4368         int rc = 0;
4369
4370         for (i = 0, k = 0; i < nr_ctxs; i++) {
4371                 struct bnxt_rx_ring_info *rxr;
4372                 struct bnxt_cp_ring_info *cpr;
4373
4374                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4375
4376                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4377                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4378                 req.hash_mode_flags = vnic->hash_mode;
4379
4380                 req.ring_grp_tbl_addr =
4381                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4382                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4383                                      2 * sizeof(*ring_tbl));
4384                 req.hash_key_tbl_addr =
4385                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4386
4387                 req.ring_table_pair_index = i;
4388                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4389
4390                 for (j = 0; j < 64; j++) {
4391                         uint16_t ring_id;
4392
4393                         /* Find next active ring. */
4394                         for (cnt = 0; cnt < max_rings; cnt++) {
4395                                 if (rx_queue_state[k] !=
4396                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4397                                         break;
4398                                 if (++k == max_rings)
4399                                         k = 0;
4400                         }
4401
4402                         /* Return if no rings are active. */
4403                         if (cnt == max_rings) {
4404                                 HWRM_UNLOCK();
4405                                 return 0;
4406                         }
4407
4408                         /* Add rx/cp ring pair to RSS table. */
4409                         rxr = rxqs[k]->rx_ring;
4410                         cpr = rxqs[k]->cp_ring;
4411
4412                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4413                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4414                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4415                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4416
4417                         if (++k == max_rings)
4418                                 k = 0;
4419                 }
4420                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4421                                             BNXT_USE_CHIMP_MB);
4422
4423                 HWRM_CHECK_RESULT();
4424                 HWRM_UNLOCK();
4425         }
4426
4427         return rc;
4428 }
4429
4430 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4431 {
4432         unsigned int rss_idx, fw_idx, i;
4433
4434         if (!(vnic->rss_table && vnic->hash_type))
4435                 return 0;
4436
4437         if (BNXT_CHIP_THOR(bp))
4438                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4439
4440         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4441                 return 0;
4442
4443         if (vnic->rss_table && vnic->hash_type) {
4444                 /*
4445                  * Fill the RSS hash & redirection table with
4446                  * ring group ids for all VNICs
4447                  */
4448                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4449                         rss_idx++, fw_idx++) {
4450                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4451                                 fw_idx %= bp->rx_cp_nr_rings;
4452                                 if (vnic->fw_grp_ids[fw_idx] !=
4453                                     INVALID_HW_RING_ID)
4454                                         break;
4455                                 fw_idx++;
4456                         }
4457                         if (i == bp->rx_cp_nr_rings)
4458                                 return 0;
4459                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4460                 }
4461                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4462         }
4463
4464         return 0;
4465 }
4466
4467 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4468         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4469 {
4470         uint16_t flags;
4471
4472         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4473
4474         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4475         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4476
4477         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4478         req->num_cmpl_dma_aggr_during_int =
4479                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4480
4481         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4482
4483         /* min timer set to 1/2 of interrupt timer */
4484         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4485
4486         /* buf timer set to 1/4 of interrupt timer */
4487         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4488
4489         req->cmpl_aggr_dma_tmr_during_int =
4490                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4491
4492         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4493                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4494         req->flags = rte_cpu_to_le_16(flags);
4495 }
4496
4497 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4498                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4499 {
4500         struct hwrm_ring_aggint_qcaps_input req = {0};
4501         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4502         uint32_t enables;
4503         uint16_t flags;
4504         int rc;
4505
4506         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4508         HWRM_CHECK_RESULT();
4509
4510         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4511         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4512
4513         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4514                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4515         agg_req->flags = rte_cpu_to_le_16(flags);
4516         enables =
4517          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4518          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4519         agg_req->enables = rte_cpu_to_le_32(enables);
4520
4521         HWRM_UNLOCK();
4522         return rc;
4523 }
4524
4525 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4526                         struct bnxt_coal *coal, uint16_t ring_id)
4527 {
4528         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4529         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4530                                                 bp->hwrm_cmd_resp_addr;
4531         int rc;
4532
4533         /* Set ring coalesce parameters only for 100G NICs */
4534         if (BNXT_CHIP_THOR(bp)) {
4535                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4536                         return -1;
4537         } else if (bnxt_stratus_device(bp)) {
4538                 bnxt_hwrm_set_coal_params(coal, &req);
4539         } else {
4540                 return 0;
4541         }
4542
4543         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4544         req.ring_id = rte_cpu_to_le_16(ring_id);
4545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4546         HWRM_CHECK_RESULT();
4547         HWRM_UNLOCK();
4548         return 0;
4549 }
4550
4551 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4552 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4553 {
4554         struct hwrm_func_backing_store_qcaps_input req = {0};
4555         struct hwrm_func_backing_store_qcaps_output *resp =
4556                 bp->hwrm_cmd_resp_addr;
4557         struct bnxt_ctx_pg_info *ctx_pg;
4558         struct bnxt_ctx_mem_info *ctx;
4559         int total_alloc_len;
4560         int rc, i;
4561
4562         if (!BNXT_CHIP_THOR(bp) ||
4563             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4564             BNXT_VF(bp) ||
4565             bp->ctx)
4566                 return 0;
4567
4568         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4569         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4570         HWRM_CHECK_RESULT_SILENT();
4571
4572         total_alloc_len = sizeof(*ctx);
4573         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4574                           RTE_CACHE_LINE_SIZE);
4575         if (!ctx) {
4576                 rc = -ENOMEM;
4577                 goto ctx_err;
4578         }
4579
4580         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4581                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4582                             RTE_CACHE_LINE_SIZE);
4583         if (!ctx_pg) {
4584                 rc = -ENOMEM;
4585                 goto ctx_err;
4586         }
4587         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4588                 ctx->tqm_mem[i] = ctx_pg;
4589
4590         bp->ctx = ctx;
4591         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4592         ctx->qp_min_qp1_entries =
4593                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4594         ctx->qp_max_l2_entries =
4595                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4596         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4597         ctx->srq_max_l2_entries =
4598                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4599         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4600         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4601         ctx->cq_max_l2_entries =
4602                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4603         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4604         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4605         ctx->vnic_max_vnic_entries =
4606                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4607         ctx->vnic_max_ring_table_entries =
4608                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4609         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4610         ctx->stat_max_entries =
4611                 rte_le_to_cpu_32(resp->stat_max_entries);
4612         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4613         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4614         ctx->tqm_min_entries_per_ring =
4615                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4616         ctx->tqm_max_entries_per_ring =
4617                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4618         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4619         if (!ctx->tqm_entries_multiple)
4620                 ctx->tqm_entries_multiple = 1;
4621         ctx->mrav_max_entries =
4622                 rte_le_to_cpu_32(resp->mrav_max_entries);
4623         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4624         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4625         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4626 ctx_err:
4627         HWRM_UNLOCK();
4628         return rc;
4629 }
4630
4631 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4632 {
4633         struct hwrm_func_backing_store_cfg_input req = {0};
4634         struct hwrm_func_backing_store_cfg_output *resp =
4635                 bp->hwrm_cmd_resp_addr;
4636         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4637         struct bnxt_ctx_pg_info *ctx_pg;
4638         uint32_t *num_entries;
4639         uint64_t *pg_dir;
4640         uint8_t *pg_attr;
4641         uint32_t ena;
4642         int i, rc;
4643
4644         if (!ctx)
4645                 return 0;
4646
4647         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4648         req.enables = rte_cpu_to_le_32(enables);
4649
4650         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4651                 ctx_pg = &ctx->qp_mem;
4652                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4653                 req.qp_num_qp1_entries =
4654                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4655                 req.qp_num_l2_entries =
4656                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4657                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4658                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4659                                       &req.qpc_pg_size_qpc_lvl,
4660                                       &req.qpc_page_dir);
4661         }
4662
4663         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4664                 ctx_pg = &ctx->srq_mem;
4665                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4666                 req.srq_num_l2_entries =
4667                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4668                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4669                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4670                                       &req.srq_pg_size_srq_lvl,
4671                                       &req.srq_page_dir);
4672         }
4673
4674         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4675                 ctx_pg = &ctx->cq_mem;
4676                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4677                 req.cq_num_l2_entries =
4678                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4679                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4680                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4681                                       &req.cq_pg_size_cq_lvl,
4682                                       &req.cq_page_dir);
4683         }
4684
4685         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4686                 ctx_pg = &ctx->vnic_mem;
4687                 req.vnic_num_vnic_entries =
4688                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4689                 req.vnic_num_ring_table_entries =
4690                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4691                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4692                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4693                                       &req.vnic_pg_size_vnic_lvl,
4694                                       &req.vnic_page_dir);
4695         }
4696
4697         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4698                 ctx_pg = &ctx->stat_mem;
4699                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4700                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4701                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4702                                       &req.stat_pg_size_stat_lvl,
4703                                       &req.stat_page_dir);
4704         }
4705
4706         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4707         num_entries = &req.tqm_sp_num_entries;
4708         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4709         pg_dir = &req.tqm_sp_page_dir;
4710         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4711         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4712                 if (!(enables & ena))
4713                         continue;
4714
4715                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4716
4717                 ctx_pg = ctx->tqm_mem[i];
4718                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4719                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4720         }
4721
4722         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4723         HWRM_CHECK_RESULT();
4724         HWRM_UNLOCK();
4725
4726         return rc;
4727 }
4728
4729 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4730 {
4731         struct hwrm_port_qstats_ext_input req = {0};
4732         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4733         struct bnxt_pf_info *pf = &bp->pf;
4734         int rc;
4735
4736         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4737               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4738                 return 0;
4739
4740         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4741
4742         req.port_id = rte_cpu_to_le_16(pf->port_id);
4743         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4744                 req.tx_stat_host_addr =
4745                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4746                 req.tx_stat_size =
4747                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4748         }
4749         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4750                 req.rx_stat_host_addr =
4751                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4752                 req.rx_stat_size =
4753                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4754         }
4755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4756
4757         if (rc) {
4758                 bp->fw_rx_port_stats_ext_size = 0;
4759                 bp->fw_tx_port_stats_ext_size = 0;
4760         } else {
4761                 bp->fw_rx_port_stats_ext_size =
4762                         rte_le_to_cpu_16(resp->rx_stat_size);
4763                 bp->fw_tx_port_stats_ext_size =
4764                         rte_le_to_cpu_16(resp->tx_stat_size);
4765         }
4766
4767         HWRM_CHECK_RESULT();
4768         HWRM_UNLOCK();
4769
4770         return rc;
4771 }
4772
4773 int
4774 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4775 {
4776         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4777         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4778                 bp->hwrm_cmd_resp_addr;
4779         int rc = 0;
4780
4781         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4782         req.tunnel_type = type;
4783         req.dest_fid = bp->fw_fid;
4784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4785         HWRM_CHECK_RESULT();
4786
4787         HWRM_UNLOCK();
4788
4789         return rc;
4790 }
4791
4792 int
4793 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4794 {
4795         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4796         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4797                 bp->hwrm_cmd_resp_addr;
4798         int rc = 0;
4799
4800         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4801         req.tunnel_type = type;
4802         req.dest_fid = bp->fw_fid;
4803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4804         HWRM_CHECK_RESULT();
4805
4806         HWRM_UNLOCK();
4807
4808         return rc;
4809 }
4810
4811 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4812 {
4813         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4814         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4815                 bp->hwrm_cmd_resp_addr;
4816         int rc = 0;
4817
4818         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4819         req.src_fid = bp->fw_fid;
4820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4821         HWRM_CHECK_RESULT();
4822
4823         if (type)
4824                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4825
4826         HWRM_UNLOCK();
4827
4828         return rc;
4829 }
4830
4831 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4832                                    uint16_t *dst_fid)
4833 {
4834         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4835         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4836                 bp->hwrm_cmd_resp_addr;
4837         int rc = 0;
4838
4839         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4840         req.src_fid = bp->fw_fid;
4841         req.tunnel_type = tun_type;
4842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4843         HWRM_CHECK_RESULT();
4844
4845         if (dst_fid)
4846                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4847
4848         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4849
4850         HWRM_UNLOCK();
4851
4852         return rc;
4853 }
4854
4855 int bnxt_hwrm_set_mac(struct bnxt *bp)
4856 {
4857         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4858         struct hwrm_func_vf_cfg_input req = {0};
4859         int rc = 0;
4860
4861         if (!BNXT_VF(bp))
4862                 return 0;
4863
4864         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4865
4866         req.enables =
4867                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4868         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4869
4870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4871
4872         HWRM_CHECK_RESULT();
4873
4874         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4875         HWRM_UNLOCK();
4876
4877         return rc;
4878 }
4879
4880 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4881 {
4882         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4883         struct hwrm_func_drv_if_change_input req = {0};
4884         uint32_t flags;
4885         int rc;
4886
4887         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4888                 return 0;
4889
4890         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4891          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4892          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4893          */
4894         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4895                 return 0;
4896
4897         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4898
4899         if (up)
4900                 req.flags =
4901                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4902
4903         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4904
4905         HWRM_CHECK_RESULT();
4906         flags = rte_le_to_cpu_32(resp->flags);
4907         HWRM_UNLOCK();
4908
4909         if (!up)
4910                 return 0;
4911
4912         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4913                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4914                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4915         }
4916
4917         return 0;
4918 }
4919
4920 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4921 {
4922         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4923         struct bnxt_error_recovery_info *info = bp->recovery_info;
4924         struct hwrm_error_recovery_qcfg_input req = {0};
4925         uint32_t flags = 0;
4926         unsigned int i;
4927         int rc;
4928
4929         /* Older FW does not have error recovery support */
4930         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4931                 return 0;
4932
4933         if (!info) {
4934                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4935                                    sizeof(*info), 0);
4936                 bp->recovery_info = info;
4937                 if (info == NULL)
4938                         return -ENOMEM;
4939         } else {
4940                 memset(info, 0, sizeof(*info));
4941         }
4942
4943         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4944
4945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4946
4947         HWRM_CHECK_RESULT();
4948
4949         flags = rte_le_to_cpu_32(resp->flags);
4950         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4951                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4952         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4953                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4954
4955         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4956             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4957                 rc = -EINVAL;
4958                 goto err;
4959         }
4960
4961         /* FW returned values are in units of 100msec */
4962         info->driver_polling_freq =
4963                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4964         info->master_func_wait_period =
4965                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4966         info->normal_func_wait_period =
4967                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4968         info->master_func_wait_period_after_reset =
4969                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4970         info->max_bailout_time_after_reset =
4971                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4972         info->status_regs[BNXT_FW_STATUS_REG] =
4973                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4974         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4975                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4976         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4977                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4978         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4979                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4980         info->reg_array_cnt =
4981                 rte_le_to_cpu_32(resp->reg_array_cnt);
4982
4983         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4984                 rc = -EINVAL;
4985                 goto err;
4986         }
4987
4988         for (i = 0; i < info->reg_array_cnt; i++) {
4989                 info->reset_reg[i] =
4990                         rte_le_to_cpu_32(resp->reset_reg[i]);
4991                 info->reset_reg_val[i] =
4992                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4993                 info->delay_after_reset[i] =
4994                         resp->delay_after_reset[i];
4995         }
4996 err:
4997         HWRM_UNLOCK();
4998
4999         /* Map the FW status registers */
5000         if (!rc)
5001                 rc = bnxt_map_fw_health_status_regs(bp);
5002
5003         if (rc) {
5004                 rte_free(bp->recovery_info);
5005                 bp->recovery_info = NULL;
5006         }
5007         return rc;
5008 }
5009
5010 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5011 {
5012         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5013         struct hwrm_fw_reset_input req = {0};
5014         int rc;
5015
5016         if (!BNXT_PF(bp))
5017                 return -EOPNOTSUPP;
5018
5019         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5020
5021         req.embedded_proc_type =
5022                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5023         req.selfrst_status =
5024                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5025         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5026
5027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5028                                     BNXT_USE_KONG(bp));
5029
5030         HWRM_CHECK_RESULT();
5031         HWRM_UNLOCK();
5032
5033         return rc;
5034 }
5035
5036 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5037 {
5038         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5039         struct hwrm_port_ts_query_input req = {0};
5040         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5041         uint32_t flags = 0;
5042         int rc;
5043
5044         if (!ptp)
5045                 return 0;
5046
5047         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5048
5049         switch (path) {
5050         case BNXT_PTP_FLAGS_PATH_TX:
5051                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5052                 break;
5053         case BNXT_PTP_FLAGS_PATH_RX:
5054                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5055                 break;
5056         case BNXT_PTP_FLAGS_CURRENT_TIME:
5057                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5058                 break;
5059         }
5060
5061         req.flags = rte_cpu_to_le_32(flags);
5062         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5063
5064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5065
5066         HWRM_CHECK_RESULT();
5067
5068         if (timestamp) {
5069                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5070                 *timestamp |=
5071                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5072         }
5073         HWRM_UNLOCK();
5074
5075         return rc;
5076 }
5077
5078 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5079 {
5080         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5081                                         bp->hwrm_cmd_resp_addr;
5082         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5083         uint32_t flags = 0;
5084         int rc = 0;
5085
5086         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5087                 return rc;
5088
5089         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5090                 PMD_DRV_LOG(DEBUG,
5091                             "Not a PF or trusted VF. Command not supported\n");
5092                 return 0;
5093         }
5094
5095         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5097
5098         HWRM_CHECK_RESULT();
5099         flags = rte_le_to_cpu_32(resp->flags);
5100         HWRM_UNLOCK();
5101
5102         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5103                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5104                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5105         }
5106
5107         return rc;
5108 }