drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         }
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 669                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 672                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 673
 674         HWRM_UNLOCK();
 675
 676         return rc;
 677 }
 678
 679 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 680 {
 681         int rc;
 682
 683         rc = __bnxt_hwrm_func_qcaps(bp);
 684         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 685                 rc = bnxt_alloc_ctx_mem(bp);
 686                 if (rc)
 687                         return rc;
 688
 689                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 690                 if (!rc)
 691                         bp->flags |= BNXT_FLAG_NEW_RM;
 692         }
 693
 694         /* On older FW,
 695          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 696          * But the error can be ignored. Return success.
 697          */
 698
 699         return 0;
 700 }
 701
 702 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 703 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 704 {
 705         int rc = 0;
 706         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 707         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 708
 709         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 710
 711         req.target_id = rte_cpu_to_le_16(0xffff);
 712
 713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 714
 715         HWRM_CHECK_RESULT();
 716
 717         if (rte_le_to_cpu_32(resp->flags) &
 718             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 719                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 720                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 721         }
 722
 723         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 724
 725         HWRM_UNLOCK();
 726
 727         return rc;
 728 }
 729
 730 int bnxt_hwrm_func_reset(struct bnxt *bp)
 731 {
 732         int rc = 0;
 733         struct hwrm_func_reset_input req = {.req_type = 0 };
 734         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 735
 736         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 737
 738         req.enables = rte_cpu_to_le_32(0);
 739
 740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 741
 742         HWRM_CHECK_RESULT();
 743         HWRM_UNLOCK();
 744
 745         return rc;
 746 }
 747
 748 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 749 {
 750         int rc;
 751         uint32_t flags = 0;
 752         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 753         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 754
 755         if (bp->flags & BNXT_FLAG_REGISTERED)
 756                 return 0;
 757
 758         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 759                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 760         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 761                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 762
 763         /* PFs and trusted VFs should indicate the support of the
 764          * Master capability on non Stingray platform
 765          */
 766         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 767                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 768
 769         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 770         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 771                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 772         req.ver_maj = RTE_VER_YEAR;
 773         req.ver_min = RTE_VER_MONTH;
 774         req.ver_upd = RTE_VER_MINOR;
 775
 776         if (BNXT_PF(bp)) {
 777                 req.enables |= rte_cpu_to_le_32(
 778                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 779                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 780                        RTE_MIN(sizeof(req.vf_req_fwd),
 781                                sizeof(bp->pf.vf_req_fwd)));
 782
 783                 /*
 784                  * PF can sniff HWRM API issued by VF. This can be set up by
 785                  * linux driver and inherited by the DPDK PF driver. Clear
 786                  * this HWRM sniffer list in FW because DPDK PF driver does
 787                  * not support this.
 788                  */
 789                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 790         }
 791
 792         req.flags = rte_cpu_to_le_32(flags);
 793
 794         req.async_event_fwd[0] |=
 795                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 796                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 797                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 798                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 799                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 800         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 801                 req.async_event_fwd[0] |=
 802                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 803         req.async_event_fwd[1] |=
 804                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 805                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 806
 807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 808
 809         HWRM_CHECK_RESULT();
 810
 811         flags = rte_le_to_cpu_32(resp->flags);
 812         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 813                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 814
 815         HWRM_UNLOCK();
 816
 817         bp->flags |= BNXT_FLAG_REGISTERED;
 818
 819         return rc;
 820 }
 821
 822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 823 {
 824         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 825                 return 0;
 826
 827         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 828 }
 829
 830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 831 {
 832         int rc;
 833         uint32_t flags = 0;
 834         uint32_t enables;
 835         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 836         struct hwrm_func_vf_cfg_input req = {0};
 837
 838         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 839
 840         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 841                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 842                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 843                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 844                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 845
 846         if (BNXT_HAS_RING_GRPS(bp)) {
 847                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 848                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 849         }
 850
 851         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 852         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 853                                             AGG_RING_MULTIPLIER);
 854         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 855         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 856                                               bp->tx_nr_rings +
 857                                               BNXT_NUM_ASYNC_CPR(bp));
 858         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 859         if (bp->vf_resv_strategy ==
 860             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 861                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 862                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 863                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 864                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 865                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 866                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 867         } else if (bp->vf_resv_strategy ==
 868                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 869                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 870                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 871         }
 872
 873         if (test)
 874                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 875                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 876                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 877                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 878                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 879                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 880
 881         if (test && BNXT_HAS_RING_GRPS(bp))
 882                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 883
 884         req.flags = rte_cpu_to_le_32(flags);
 885         req.enables |= rte_cpu_to_le_32(enables);
 886
 887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 888
 889         if (test)
 890                 HWRM_CHECK_RESULT_SILENT();
 891         else
 892                 HWRM_CHECK_RESULT();
 893
 894         HWRM_UNLOCK();
 895         return rc;
 896 }
 897
 898 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 899 {
 900         int rc;
 901         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 902         struct hwrm_func_resource_qcaps_input req = {0};
 903
 904         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 905         req.fid = rte_cpu_to_le_16(0xffff);
 906
 907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 908
 909         HWRM_CHECK_RESULT_SILENT();
 910
 911         if (BNXT_VF(bp)) {
 912                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 913                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 914                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 915                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 916                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 917                 /* func_resource_qcaps does not return max_rx_em_flows.
 918                  * So use the value provided by func_qcaps.
 919                  */
 920                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 921                 if (!BNXT_CHIP_THOR(bp))
 922                         bp->max_l2_ctx += bp->max_rx_em_flows;
 923                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 924                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 925         }
 926         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 927         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 928         if (bp->vf_resv_strategy >
 929             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 930                 bp->vf_resv_strategy =
 931                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 932
 933         HWRM_UNLOCK();
 934         return rc;
 935 }
 936
 937 int bnxt_hwrm_ver_get(struct bnxt *bp)
 938 {
 939         int rc = 0;
 940         struct hwrm_ver_get_input req = {.req_type = 0 };
 941         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 942         uint32_t fw_version;
 943         uint16_t max_resp_len;
 944         char type[RTE_MEMZONE_NAMESIZE];
 945         uint32_t dev_caps_cfg;
 946
 947         bp->max_req_len = HWRM_MAX_REQ_LEN;
 948         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 949
 950         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 951         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 952         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 953
 954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 955
 956         if (bp->flags & BNXT_FLAG_FW_RESET)
 957                 HWRM_CHECK_RESULT_SILENT();
 958         else
 959                 HWRM_CHECK_RESULT();
 960
 961         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 962                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 963                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 964                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 965         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 966                      (resp->hwrm_fw_min_8b << 16) |
 967                      (resp->hwrm_fw_bld_8b << 8) |
 968                      resp->hwrm_fw_rsvd_8b;
 969         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 970                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 971
 972         fw_version = resp->hwrm_intf_maj_8b << 16;
 973         fw_version |= resp->hwrm_intf_min_8b << 8;
 974         fw_version |= resp->hwrm_intf_upd_8b;
 975         bp->hwrm_spec_code = fw_version;
 976
 977         /* def_req_timeout value is in milliseconds */
 978         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 979         /* convert timeout to usec */
 980         bp->hwrm_cmd_timeout *= 1000;
 981         if (!bp->hwrm_cmd_timeout)
 982                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 983
 984         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 985                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 986                 rc = -EINVAL;
 987                 goto error;
 988         }
 989
 990         if (bp->max_req_len > resp->max_req_win_len) {
 991                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 992                 rc = -EINVAL;
 993         }
 994         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 995         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 996         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 997                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 998
 999         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1000         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1001
1002         if (bp->max_resp_len != max_resp_len) {
1003                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1004                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1005                         bp->pdev->addr.devid, bp->pdev->addr.function);
1006
1007                 rte_free(bp->hwrm_cmd_resp_addr);
1008
1009                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1010                 if (bp->hwrm_cmd_resp_addr == NULL) {
1011                         rc = -ENOMEM;
1012                         goto error;
1013                 }
1014                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1015                 bp->hwrm_cmd_resp_dma_addr =
1016                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1017                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1018                         PMD_DRV_LOG(ERR,
1019                         "Unable to map response buffer to physical memory.\n");
1020                         rc = -ENOMEM;
1021                         goto error;
1022                 }
1023                 bp->max_resp_len = max_resp_len;
1024         }
1025
1026         if ((dev_caps_cfg &
1027                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1028             (dev_caps_cfg &
1029              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1030                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1031                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1032         }
1033
1034         if (((dev_caps_cfg &
1035               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1036              (dev_caps_cfg &
1037               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1038             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1039                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1040                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1041                         bp->pdev->addr.devid, bp->pdev->addr.function);
1042
1043                 rte_free(bp->hwrm_short_cmd_req_addr);
1044
1045                 bp->hwrm_short_cmd_req_addr =
1046                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1047                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1048                         rc = -ENOMEM;
1049                         goto error;
1050                 }
1051                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1052                 bp->hwrm_short_cmd_req_dma_addr =
1053                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1054                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1055                         rte_free(bp->hwrm_short_cmd_req_addr);
1056                         PMD_DRV_LOG(ERR,
1057                                 "Unable to map buffer to physical memory.\n");
1058                         rc = -ENOMEM;
1059                         goto error;
1060                 }
1061         }
1062         if (dev_caps_cfg &
1063             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1064                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1065                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1066         }
1067         if (dev_caps_cfg &
1068             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1069                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1070         if (dev_caps_cfg &
1071             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1072                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1073                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1074         }
1075
1076 error:
1077         HWRM_UNLOCK();
1078         return rc;
1079 }
1080
1081 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1082 {
1083         int rc;
1084         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1085         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1086
1087         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1088                 return 0;
1089
1090         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1091         req.flags = flags;
1092
1093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1094
1095         HWRM_CHECK_RESULT();
1096         HWRM_UNLOCK();
1097
1098         return rc;
1099 }
1100
1101 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1102 {
1103         int rc = 0;
1104         struct hwrm_port_phy_cfg_input req = {0};
1105         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1106         uint32_t enables = 0;
1107
1108         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1109
1110         if (conf->link_up) {
1111                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1112                 if (bp->link_info.auto_mode && conf->link_speed) {
1113                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1114                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1115                 }
1116
1117                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1118                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1119                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1120                 /*
1121                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1122                  * any auto mode, even "none".
1123                  */
1124                 if (!conf->link_speed) {
1125                         /* No speeds specified. Enable AutoNeg - all speeds */
1126                         req.auto_mode =
1127                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1128                 }
1129                 /* AutoNeg - Advertise speeds specified. */
1130                 if (conf->auto_link_speed_mask &&
1131                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1132                         req.auto_mode =
1133                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1134                         req.auto_link_speed_mask =
1135                                 conf->auto_link_speed_mask;
1136                         enables |=
1137                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1138                 }
1139
1140                 req.auto_duplex = conf->duplex;
1141                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1142                 req.auto_pause = conf->auto_pause;
1143                 req.force_pause = conf->force_pause;
1144                 /* Set force_pause if there is no auto or if there is a force */
1145                 if (req.auto_pause && !req.force_pause)
1146                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1147                 else
1148                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1149
1150                 req.enables = rte_cpu_to_le_32(enables);
1151         } else {
1152                 req.flags =
1153                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1154                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1155         }
1156
1157         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1158
1159         HWRM_CHECK_RESULT();
1160         HWRM_UNLOCK();
1161
1162         return rc;
1163 }
1164
1165 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1166                                    struct bnxt_link_info *link_info)
1167 {
1168         int rc = 0;
1169         struct hwrm_port_phy_qcfg_input req = {0};
1170         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1171
1172         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1173
1174         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1175
1176         HWRM_CHECK_RESULT();
1177
1178         link_info->phy_link_status = resp->link;
1179         link_info->link_up =
1180                 (link_info->phy_link_status ==
1181                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1182         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1183         link_info->duplex = resp->duplex_cfg;
1184         link_info->pause = resp->pause;
1185         link_info->auto_pause = resp->auto_pause;
1186         link_info->force_pause = resp->force_pause;
1187         link_info->auto_mode = resp->auto_mode;
1188         link_info->phy_type = resp->phy_type;
1189         link_info->media_type = resp->media_type;
1190
1191         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1192         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1193         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1194         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1195         link_info->phy_ver[0] = resp->phy_maj;
1196         link_info->phy_ver[1] = resp->phy_min;
1197         link_info->phy_ver[2] = resp->phy_bld;
1198
1199         HWRM_UNLOCK();
1200
1201         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1202         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1203         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1204         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1205         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1206                     link_info->auto_link_speed_mask);
1207         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1208                     link_info->force_link_speed);
1209
1210         return rc;
1211 }
1212
1213 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1214 {
1215         int i = 0;
1216
1217         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1218                 if (bp->tx_cos_queue[i].profile ==
1219                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1220                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1221                         return true;
1222                 }
1223         }
1224         return false;
1225 }
1226
1227 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1228 {
1229         int i = 0;
1230
1231         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1232                 if (bp->tx_cos_queue[i].profile !=
1233                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1234                     bp->tx_cos_queue[i].id !=
1235                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1236                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1237                         break;
1238                 }
1239         }
1240 }
1241
1242 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1243 {
1244         int rc = 0;
1245         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1246         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1247         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1248         int i;
1249
1250 get_rx_info:
1251         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1252
1253         req.flags = rte_cpu_to_le_32(dir);
1254         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1255         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1256             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1257                 req.drv_qmap_cap =
1258                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1259         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1260
1261         HWRM_CHECK_RESULT();
1262
1263         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1264                 GET_TX_QUEUE_INFO(0);
1265                 GET_TX_QUEUE_INFO(1);
1266                 GET_TX_QUEUE_INFO(2);
1267                 GET_TX_QUEUE_INFO(3);
1268                 GET_TX_QUEUE_INFO(4);
1269                 GET_TX_QUEUE_INFO(5);
1270                 GET_TX_QUEUE_INFO(6);
1271                 GET_TX_QUEUE_INFO(7);
1272         } else  {
1273                 GET_RX_QUEUE_INFO(0);
1274                 GET_RX_QUEUE_INFO(1);
1275                 GET_RX_QUEUE_INFO(2);
1276                 GET_RX_QUEUE_INFO(3);
1277                 GET_RX_QUEUE_INFO(4);
1278                 GET_RX_QUEUE_INFO(5);
1279                 GET_RX_QUEUE_INFO(6);
1280                 GET_RX_QUEUE_INFO(7);
1281         }
1282
1283         HWRM_UNLOCK();
1284
1285         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1286                 goto done;
1287
1288         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1289                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1290         } else {
1291                 int j;
1292
1293                 /* iterate and find the COSq profile to use for Tx */
1294                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1295                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1296                                 if (bp->tx_cos_queue[i].id != 0xff)
1297                                         bp->tx_cosq_id[j++] =
1298                                                 bp->tx_cos_queue[i].id;
1299                         }
1300                 } else {
1301                         /* When CoS classification is disabled, for normal NIC
1302                          * operations, ideally we should look to use LOSSY.
1303                          * If not found, fallback to the first valid profile
1304                          */
1305                         if (!bnxt_find_lossy_profile(bp))
1306                                 bnxt_find_first_valid_profile(bp);
1307
1308                 }
1309         }
1310
1311         bp->max_tc = resp->max_configurable_queues;
1312         bp->max_lltc = resp->max_configurable_lossless_queues;
1313         if (bp->max_tc > BNXT_MAX_QUEUE)
1314                 bp->max_tc = BNXT_MAX_QUEUE;
1315         bp->max_q = bp->max_tc;
1316
1317         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1318                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1319                 goto get_rx_info;
1320         }
1321
1322 done:
1323         return rc;
1324 }
1325
1326 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1327                          struct bnxt_ring *ring,
1328                          uint32_t ring_type, uint32_t map_index,
1329                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1330                          uint16_t tx_cosq_id)
1331 {
1332         int rc = 0;
1333         uint32_t enables = 0;
1334         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1335         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1336         struct rte_mempool *mb_pool;
1337         uint16_t rx_buf_size;
1338
1339         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1340
1341         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1342         req.fbo = rte_cpu_to_le_32(0);
1343         /* Association of ring index with doorbell index */
1344         req.logical_id = rte_cpu_to_le_16(map_index);
1345         req.length = rte_cpu_to_le_32(ring->ring_size);
1346
1347         switch (ring_type) {
1348         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1349                 req.ring_type = ring_type;
1350                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1351                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1352                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1353                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1354                         enables |=
1355                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1356                 break;
1357         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1358                 req.ring_type = ring_type;
1359                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1360                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1361                 if (BNXT_CHIP_THOR(bp)) {
1362                         mb_pool = bp->rx_queues[0]->mb_pool;
1363                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1364                                       RTE_PKTMBUF_HEADROOM;
1365                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1366                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1367                         enables |=
1368                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1369                 }
1370                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1371                         enables |=
1372                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1373                 break;
1374         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1375                 req.ring_type = ring_type;
1376                 if (BNXT_HAS_NQ(bp)) {
1377                         /* Association of cp ring with nq */
1378                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1379                         enables |=
1380                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1381                 }
1382                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1383                 break;
1384         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1385                 req.ring_type = ring_type;
1386                 req.page_size = BNXT_PAGE_SHFT;
1387                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1388                 break;
1389         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1390                 req.ring_type = ring_type;
1391                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1392
1393                 mb_pool = bp->rx_queues[0]->mb_pool;
1394                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1395                               RTE_PKTMBUF_HEADROOM;
1396                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1397                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1398
1399                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1400                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1401                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1402                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1403                 break;
1404         default:
1405                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1406                         ring_type);
1407                 HWRM_UNLOCK();
1408                 return -EINVAL;
1409         }
1410         req.enables = rte_cpu_to_le_32(enables);
1411
1412         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1413
1414         if (rc || resp->error_code) {
1415                 if (rc == 0 && resp->error_code)
1416                         rc = rte_le_to_cpu_16(resp->error_code);
1417                 switch (ring_type) {
1418                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1419                         PMD_DRV_LOG(ERR,
1420                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1421                         HWRM_UNLOCK();
1422                         return rc;
1423                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1424                         PMD_DRV_LOG(ERR,
1425                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1426                         HWRM_UNLOCK();
1427                         return rc;
1428                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1429                         PMD_DRV_LOG(ERR,
1430                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1431                                     rc);
1432                         HWRM_UNLOCK();
1433                         return rc;
1434                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1435                         PMD_DRV_LOG(ERR,
1436                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1437                         HWRM_UNLOCK();
1438                         return rc;
1439                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1440                         PMD_DRV_LOG(ERR,
1441                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1442                         HWRM_UNLOCK();
1443                         return rc;
1444                 default:
1445                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1446                         HWRM_UNLOCK();
1447                         return rc;
1448                 }
1449         }
1450
1451         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1452         HWRM_UNLOCK();
1453         return rc;
1454 }
1455
1456 int bnxt_hwrm_ring_free(struct bnxt *bp,
1457                         struct bnxt_ring *ring, uint32_t ring_type)
1458 {
1459         int rc;
1460         struct hwrm_ring_free_input req = {.req_type = 0 };
1461         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1462
1463         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1464
1465         req.ring_type = ring_type;
1466         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1467
1468         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1469
1470         if (rc || resp->error_code) {
1471                 if (rc == 0 && resp->error_code)
1472                         rc = rte_le_to_cpu_16(resp->error_code);
1473                 HWRM_UNLOCK();
1474
1475                 switch (ring_type) {
1476                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1477                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1478                                 rc);
1479                         return rc;
1480                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1481                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1482                                 rc);
1483                         return rc;
1484                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1485                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1486                                 rc);
1487                         return rc;
1488                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1489                         PMD_DRV_LOG(ERR,
1490                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1491                         return rc;
1492                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1493                         PMD_DRV_LOG(ERR,
1494                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1495                         return rc;
1496                 default:
1497                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1498                         return rc;
1499                 }
1500         }
1501         HWRM_UNLOCK();
1502         return 0;
1503 }
1504
1505 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1506 {
1507         int rc = 0;
1508         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1509         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1510
1511         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1512
1513         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1514         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1515         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1516         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1517
1518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1519
1520         HWRM_CHECK_RESULT();
1521
1522         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1523
1524         HWRM_UNLOCK();
1525
1526         return rc;
1527 }
1528
1529 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1530 {
1531         int rc;
1532         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1533         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1534
1535         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1536
1537         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1538
1539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1540
1541         HWRM_CHECK_RESULT();
1542         HWRM_UNLOCK();
1543
1544         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1545         return rc;
1546 }
1547
1548 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1549 {
1550         int rc = 0;
1551         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1552         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1553
1554         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1555                 return rc;
1556
1557         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1558
1559         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1560
1561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1562
1563         HWRM_CHECK_RESULT();
1564         HWRM_UNLOCK();
1565
1566         return rc;
1567 }
1568
1569 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1570                                 unsigned int idx __rte_unused)
1571 {
1572         int rc;
1573         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1574         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1575
1576         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1577
1578         req.update_period_ms = rte_cpu_to_le_32(0);
1579
1580         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1581
1582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1583
1584         HWRM_CHECK_RESULT();
1585
1586         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1587
1588         HWRM_UNLOCK();
1589
1590         return rc;
1591 }
1592
1593 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1594                                 unsigned int idx __rte_unused)
1595 {
1596         int rc;
1597         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1598         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1599
1600         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1601
1602         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1603
1604         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1605
1606         HWRM_CHECK_RESULT();
1607         HWRM_UNLOCK();
1608
1609         return rc;
1610 }
1611
1612 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1613 {
1614         int rc = 0, i, j;
1615         struct hwrm_vnic_alloc_input req = { 0 };
1616         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1617
1618         if (!BNXT_HAS_RING_GRPS(bp))
1619                 goto skip_ring_grps;
1620
1621         /* map ring groups to this vnic */
1622         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1623                 vnic->start_grp_id, vnic->end_grp_id);
1624         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1625                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1626
1627         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1628         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1629         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1630         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1631
1632 skip_ring_grps:
1633         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1634         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1635
1636         if (vnic->func_default)
1637                 req.flags =
1638                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1640
1641         HWRM_CHECK_RESULT();
1642
1643         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1644         HWRM_UNLOCK();
1645         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1646         return rc;
1647 }
1648
1649 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1650                                         struct bnxt_vnic_info *vnic,
1651                                         struct bnxt_plcmodes_cfg *pmode)
1652 {
1653         int rc = 0;
1654         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1655         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1656
1657         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1658
1659         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1660
1661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1662
1663         HWRM_CHECK_RESULT();
1664
1665         pmode->flags = rte_le_to_cpu_32(resp->flags);
1666         /* dflt_vnic bit doesn't exist in the _cfg command */
1667         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1668         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1669         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1670         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1671
1672         HWRM_UNLOCK();
1673
1674         return rc;
1675 }
1676
1677 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1678                                        struct bnxt_vnic_info *vnic,
1679                                        struct bnxt_plcmodes_cfg *pmode)
1680 {
1681         int rc = 0;
1682         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1683         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1684
1685         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1686                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1687                 return rc;
1688         }
1689
1690         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1691
1692         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1693         req.flags = rte_cpu_to_le_32(pmode->flags);
1694         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1695         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1696         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1697         req.enables = rte_cpu_to_le_32(
1698             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1699             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1700             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1701         );
1702
1703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1704
1705         HWRM_CHECK_RESULT();
1706         HWRM_UNLOCK();
1707
1708         return rc;
1709 }
1710
1711 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1712 {
1713         int rc = 0;
1714         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1715         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1716         struct bnxt_plcmodes_cfg pmodes = { 0 };
1717         uint32_t ctx_enable_flag = 0;
1718         uint32_t enables = 0;
1719
1720         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1721                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1722                 return rc;
1723         }
1724
1725         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1726         if (rc)
1727                 return rc;
1728
1729         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1730
1731         if (BNXT_CHIP_THOR(bp)) {
1732                 int dflt_rxq = vnic->start_grp_id;
1733                 struct bnxt_rx_ring_info *rxr;
1734                 struct bnxt_cp_ring_info *cpr;
1735                 struct bnxt_rx_queue *rxq;
1736                 int i;
1737
1738                 /*
1739                  * The first active receive ring is used as the VNIC
1740                  * default receive ring. If there are no active receive
1741                  * rings (all corresponding receive queues are stopped),
1742                  * the first receive ring is used.
1743                  */
1744                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1745                         rxq = bp->eth_dev->data->rx_queues[i];
1746                         if (rxq->rx_started) {
1747                                 dflt_rxq = i;
1748                                 break;
1749                         }
1750                 }
1751
1752                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1753                 rxr = rxq->rx_ring;
1754                 cpr = rxq->cp_ring;
1755
1756                 req.default_rx_ring_id =
1757                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1758                 req.default_cmpl_ring_id =
1759                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1760                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1761                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1762                 goto config_mru;
1763         }
1764
1765         /* Only RSS support for now TBD: COS & LB */
1766         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1767         if (vnic->lb_rule != 0xffff)
1768                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1769         if (vnic->cos_rule != 0xffff)
1770                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1771         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1772                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1773                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1774         }
1775         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1776                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1777                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1778         }
1779
1780         enables |= ctx_enable_flag;
1781         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1782         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1783         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1784         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1785
1786 config_mru:
1787         req.enables = rte_cpu_to_le_32(enables);
1788         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1789         req.mru = rte_cpu_to_le_16(vnic->mru);
1790         /* Configure default VNIC only once. */
1791         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1792                 req.flags |=
1793                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1794                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1795         }
1796         if (vnic->vlan_strip)
1797                 req.flags |=
1798                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1799         if (vnic->bd_stall)
1800                 req.flags |=
1801                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1802         if (vnic->roce_dual)
1803                 req.flags |= rte_cpu_to_le_32(
1804                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1805         if (vnic->roce_only)
1806                 req.flags |= rte_cpu_to_le_32(
1807                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1808         if (vnic->rss_dflt_cr)
1809                 req.flags |= rte_cpu_to_le_32(
1810                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1811
1812         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1813
1814         HWRM_CHECK_RESULT();
1815         HWRM_UNLOCK();
1816
1817         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1818
1819         return rc;
1820 }
1821
1822 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1823                 int16_t fw_vf_id)
1824 {
1825         int rc = 0;
1826         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1827         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1828
1829         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1830                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1831                 return rc;
1832         }
1833         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1834
1835         req.enables =
1836                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1837         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1838         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1839
1840         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1841
1842         HWRM_CHECK_RESULT();
1843
1844         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1845         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1846         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1847         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1848         vnic->mru = rte_le_to_cpu_16(resp->mru);
1849         vnic->func_default = rte_le_to_cpu_32(
1850                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1851         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1852                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1853         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1854                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1855         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1856                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1857         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1858                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1859         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1860                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1861
1862         HWRM_UNLOCK();
1863
1864         return rc;
1865 }
1866
1867 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1868                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1869 {
1870         int rc = 0;
1871         uint16_t ctx_id;
1872         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1873         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1874                                                 bp->hwrm_cmd_resp_addr;
1875
1876         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1877
1878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1879         HWRM_CHECK_RESULT();
1880
1881         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1882         if (!BNXT_HAS_RING_GRPS(bp))
1883                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1884         else if (ctx_idx == 0)
1885                 vnic->rss_rule = ctx_id;
1886
1887         HWRM_UNLOCK();
1888
1889         return rc;
1890 }
1891
1892 static
1893 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1894                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1895 {
1896         int rc = 0;
1897         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1898         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1899                                                 bp->hwrm_cmd_resp_addr;
1900
1901         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1902                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1903                 return rc;
1904         }
1905         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1906
1907         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1908
1909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910
1911         HWRM_CHECK_RESULT();
1912         HWRM_UNLOCK();
1913
1914         return rc;
1915 }
1916
1917 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1918 {
1919         int rc = 0;
1920
1921         if (BNXT_CHIP_THOR(bp)) {
1922                 int j;
1923
1924                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1925                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1926                                                       vnic,
1927                                                       vnic->fw_grp_ids[j]);
1928                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1929                 }
1930                 vnic->num_lb_ctxts = 0;
1931         } else {
1932                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1933                 vnic->rss_rule = INVALID_HW_RING_ID;
1934         }
1935
1936         return rc;
1937 }
1938
1939 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1940 {
1941         int rc = 0;
1942         struct hwrm_vnic_free_input req = {.req_type = 0 };
1943         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1944
1945         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1946                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1947                 return rc;
1948         }
1949
1950         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1951
1952         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1953
1954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1955
1956         HWRM_CHECK_RESULT();
1957         HWRM_UNLOCK();
1958
1959         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1960         /* Configure default VNIC again if necessary. */
1961         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1962                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1963
1964         return rc;
1965 }
1966
1967 static int
1968 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1969 {
1970         int i;
1971         int rc = 0;
1972         int nr_ctxs = vnic->num_lb_ctxts;
1973         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1974         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1975
1976         for (i = 0; i < nr_ctxs; i++) {
1977                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1978
1979                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1980                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1981                 req.hash_mode_flags = vnic->hash_mode;
1982
1983                 req.hash_key_tbl_addr =
1984                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1985
1986                 req.ring_grp_tbl_addr =
1987                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1988                                          i * HW_HASH_INDEX_SIZE);
1989                 req.ring_table_pair_index = i;
1990                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1991
1992                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1993                                             BNXT_USE_CHIMP_MB);
1994
1995                 HWRM_CHECK_RESULT();
1996                 HWRM_UNLOCK();
1997         }
1998
1999         return rc;
2000 }
2001
2002 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2003                            struct bnxt_vnic_info *vnic)
2004 {
2005         int rc = 0;
2006         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2007         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2008
2009         if (!vnic->rss_table)
2010                 return 0;
2011
2012         if (BNXT_CHIP_THOR(bp))
2013                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2014
2015         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2016
2017         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2018         req.hash_mode_flags = vnic->hash_mode;
2019
2020         req.ring_grp_tbl_addr =
2021             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2022         req.hash_key_tbl_addr =
2023             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2024         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2025         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2026
2027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2028
2029         HWRM_CHECK_RESULT();
2030         HWRM_UNLOCK();
2031
2032         return rc;
2033 }
2034
2035 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2036                         struct bnxt_vnic_info *vnic)
2037 {
2038         int rc = 0;
2039         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2040         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2041         uint16_t size;
2042
2043         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2044                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2045                 return rc;
2046         }
2047
2048         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2049
2050         req.flags = rte_cpu_to_le_32(
2051                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2052
2053         req.enables = rte_cpu_to_le_32(
2054                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2055
2056         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2057         size -= RTE_PKTMBUF_HEADROOM;
2058         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2059
2060         req.jumbo_thresh = rte_cpu_to_le_16(size);
2061         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2062
2063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2064
2065         HWRM_CHECK_RESULT();
2066         HWRM_UNLOCK();
2067
2068         return rc;
2069 }
2070
2071 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2072                         struct bnxt_vnic_info *vnic, bool enable)
2073 {
2074         int rc = 0;
2075         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2076         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2077
2078         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2079                 if (enable)
2080                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2081                 return -ENOTSUP;
2082         }
2083
2084         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2085                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2086                 return 0;
2087         }
2088
2089         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2090
2091         if (enable) {
2092                 req.enables = rte_cpu_to_le_32(
2093                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2094                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2095                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2096                 req.flags = rte_cpu_to_le_32(
2097                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2098                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2099                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2100                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2101                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2102                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2103                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2104                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2105                 req.min_agg_len = rte_cpu_to_le_32(512);
2106         }
2107         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2108
2109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2110
2111         HWRM_CHECK_RESULT();
2112         HWRM_UNLOCK();
2113
2114         return rc;
2115 }
2116
2117 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2118 {
2119         struct hwrm_func_cfg_input req = {0};
2120         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2121         int rc;
2122
2123         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2124         req.enables = rte_cpu_to_le_32(
2125                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2126         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2127         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2128
2129         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2130
2131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2132         HWRM_CHECK_RESULT();
2133         HWRM_UNLOCK();
2134
2135         bp->pf.vf_info[vf].random_mac = false;
2136
2137         return rc;
2138 }
2139
2140 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2141                                   uint64_t *dropped)
2142 {
2143         int rc = 0;
2144         struct hwrm_func_qstats_input req = {.req_type = 0};
2145         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2146
2147         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2148
2149         req.fid = rte_cpu_to_le_16(fid);
2150
2151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2152
2153         HWRM_CHECK_RESULT();
2154
2155         if (dropped)
2156                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2157
2158         HWRM_UNLOCK();
2159
2160         return rc;
2161 }
2162
2163 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2164                           struct rte_eth_stats *stats)
2165 {
2166         int rc = 0;
2167         struct hwrm_func_qstats_input req = {.req_type = 0};
2168         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2169
2170         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2171
2172         req.fid = rte_cpu_to_le_16(fid);
2173
2174         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2175
2176         HWRM_CHECK_RESULT();
2177
2178         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2179         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2180         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2181         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2182         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2183         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2184
2185         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2186         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2187         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2188         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2189         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2190         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2191
2192         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2193         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2194         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2195
2196         HWRM_UNLOCK();
2197
2198         return rc;
2199 }
2200
2201 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2202 {
2203         int rc = 0;
2204         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2205         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2206
2207         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2208
2209         req.fid = rte_cpu_to_le_16(fid);
2210
2211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2212
2213         HWRM_CHECK_RESULT();
2214         HWRM_UNLOCK();
2215
2216         return rc;
2217 }
2218
2219 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2220 {
2221         unsigned int i;
2222         int rc = 0;
2223
2224         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2225                 struct bnxt_tx_queue *txq;
2226                 struct bnxt_rx_queue *rxq;
2227                 struct bnxt_cp_ring_info *cpr;
2228
2229                 if (i >= bp->rx_cp_nr_rings) {
2230                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2231                         cpr = txq->cp_ring;
2232                 } else {
2233                         rxq = bp->rx_queues[i];
2234                         cpr = rxq->cp_ring;
2235                 }
2236
2237                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2238                 if (rc)
2239                         return rc;
2240         }
2241         return 0;
2242 }
2243
2244 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2245 {
2246         int rc;
2247         unsigned int i;
2248         struct bnxt_cp_ring_info *cpr;
2249
2250         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2251
2252                 if (i >= bp->rx_cp_nr_rings) {
2253                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2254                 } else {
2255                         cpr = bp->rx_queues[i]->cp_ring;
2256                         if (BNXT_HAS_RING_GRPS(bp))
2257                                 bp->grp_info[i].fw_stats_ctx = -1;
2258                 }
2259                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2260                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2261                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2262                         if (rc)
2263                                 return rc;
2264                 }
2265         }
2266         return 0;
2267 }
2268
2269 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2270 {
2271         unsigned int i;
2272         int rc = 0;
2273
2274         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2275                 struct bnxt_tx_queue *txq;
2276                 struct bnxt_rx_queue *rxq;
2277                 struct bnxt_cp_ring_info *cpr;
2278
2279                 if (i >= bp->rx_cp_nr_rings) {
2280                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2281                         cpr = txq->cp_ring;
2282                 } else {
2283                         rxq = bp->rx_queues[i];
2284                         cpr = rxq->cp_ring;
2285                 }
2286
2287                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2288
2289                 if (rc)
2290                         return rc;
2291         }
2292         return rc;
2293 }
2294
2295 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2296 {
2297         uint16_t idx;
2298         uint32_t rc = 0;
2299
2300         if (!BNXT_HAS_RING_GRPS(bp))
2301                 return 0;
2302
2303         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2304
2305                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2306                         continue;
2307
2308                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2309
2310                 if (rc)
2311                         return rc;
2312         }
2313         return rc;
2314 }
2315
2316 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2317 {
2318         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2319
2320         bnxt_hwrm_ring_free(bp, cp_ring,
2321                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2322         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2323         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2324                                      sizeof(*cpr->cp_desc_ring));
2325         cpr->cp_raw_cons = 0;
2326         cpr->valid = 0;
2327 }
2328
2329 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2330 {
2331         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2332
2333         bnxt_hwrm_ring_free(bp, cp_ring,
2334                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2335         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2336         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2337                         sizeof(*cpr->cp_desc_ring));
2338         cpr->cp_raw_cons = 0;
2339         cpr->valid = 0;
2340 }
2341
2342 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2343 {
2344         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2345         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2346         struct bnxt_ring *ring = rxr->rx_ring_struct;
2347         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2348
2349         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2350                 bnxt_hwrm_ring_free(bp, ring,
2351                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2352                 ring->fw_ring_id = INVALID_HW_RING_ID;
2353                 if (BNXT_HAS_RING_GRPS(bp))
2354                         bp->grp_info[queue_index].rx_fw_ring_id =
2355                                                         INVALID_HW_RING_ID;
2356                 memset(rxr->rx_desc_ring, 0,
2357                        rxr->rx_ring_struct->ring_size *
2358                        sizeof(*rxr->rx_desc_ring));
2359                 memset(rxr->rx_buf_ring, 0,
2360                        rxr->rx_ring_struct->ring_size *
2361                        sizeof(*rxr->rx_buf_ring));
2362                 rxr->rx_prod = 0;
2363         }
2364         ring = rxr->ag_ring_struct;
2365         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2366                 bnxt_hwrm_ring_free(bp, ring,
2367                                     BNXT_CHIP_THOR(bp) ?
2368                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2369                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2370                 ring->fw_ring_id = INVALID_HW_RING_ID;
2371                 memset(rxr->ag_buf_ring, 0,
2372                        rxr->ag_ring_struct->ring_size *
2373                        sizeof(*rxr->ag_buf_ring));
2374                 rxr->ag_prod = 0;
2375                 if (BNXT_HAS_RING_GRPS(bp))
2376                         bp->grp_info[queue_index].ag_fw_ring_id =
2377                                                         INVALID_HW_RING_ID;
2378         }
2379         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2380                 bnxt_free_cp_ring(bp, cpr);
2381
2382         if (BNXT_HAS_RING_GRPS(bp))
2383                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2384 }
2385
2386 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2387 {
2388         unsigned int i;
2389
2390         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2391                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2392                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2393                 struct bnxt_ring *ring = txr->tx_ring_struct;
2394                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2395
2396                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2397                         bnxt_hwrm_ring_free(bp, ring,
2398                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2399                         ring->fw_ring_id = INVALID_HW_RING_ID;
2400                         memset(txr->tx_desc_ring, 0,
2401                                         txr->tx_ring_struct->ring_size *
2402                                         sizeof(*txr->tx_desc_ring));
2403                         memset(txr->tx_buf_ring, 0,
2404                                         txr->tx_ring_struct->ring_size *
2405                                         sizeof(*txr->tx_buf_ring));
2406                         txr->tx_prod = 0;
2407                         txr->tx_cons = 0;
2408                 }
2409                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2410                         bnxt_free_cp_ring(bp, cpr);
2411                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2412                 }
2413         }
2414
2415         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2416                 bnxt_free_hwrm_rx_ring(bp, i);
2417
2418         return 0;
2419 }
2420
2421 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2422 {
2423         uint16_t i;
2424         uint32_t rc = 0;
2425
2426         if (!BNXT_HAS_RING_GRPS(bp))
2427                 return 0;
2428
2429         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2430                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2431                 if (rc)
2432                         return rc;
2433         }
2434         return rc;
2435 }
2436
2437 /*
2438  * HWRM utility functions
2439  */
2440
2441 void bnxt_free_hwrm_resources(struct bnxt *bp)
2442 {
2443         /* Release memzone */
2444         rte_free(bp->hwrm_cmd_resp_addr);
2445         rte_free(bp->hwrm_short_cmd_req_addr);
2446         bp->hwrm_cmd_resp_addr = NULL;
2447         bp->hwrm_short_cmd_req_addr = NULL;
2448         bp->hwrm_cmd_resp_dma_addr = 0;
2449         bp->hwrm_short_cmd_req_dma_addr = 0;
2450 }
2451
2452 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2453 {
2454         struct rte_pci_device *pdev = bp->pdev;
2455         char type[RTE_MEMZONE_NAMESIZE];
2456
2457         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2458                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2459         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2460         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2461         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2462         if (bp->hwrm_cmd_resp_addr == NULL)
2463                 return -ENOMEM;
2464         bp->hwrm_cmd_resp_dma_addr =
2465                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2466         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2467                 PMD_DRV_LOG(ERR,
2468                         "unable to map response address to physical memory\n");
2469                 return -ENOMEM;
2470         }
2471         rte_spinlock_init(&bp->hwrm_lock);
2472
2473         return 0;
2474 }
2475
2476 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2477 {
2478         struct bnxt_filter_info *filter;
2479         int rc = 0;
2480
2481         STAILQ_FOREACH(filter, &vnic->filter, next) {
2482                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2483                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2484                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2485                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2486                 else
2487                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2488                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2489                 bnxt_free_filter(bp, filter);
2490         }
2491         return rc;
2492 }
2493
2494 static int
2495 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2496 {
2497         struct bnxt_filter_info *filter;
2498         struct rte_flow *flow;
2499         int rc = 0;
2500
2501         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2502                 flow = STAILQ_FIRST(&vnic->flow_list);
2503                 filter = flow->filter;
2504                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2505                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2506                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2507                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2508                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2509                 else
2510                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2511
2512                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2513                 rte_free(flow);
2514         }
2515         return rc;
2516 }
2517
2518 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2519 {
2520         struct bnxt_filter_info *filter;
2521         int rc = 0;
2522
2523         STAILQ_FOREACH(filter, &vnic->filter, next) {
2524                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2525                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2526                                                      filter);
2527                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2528                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2529                                                          filter);
2530                 else
2531                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2532                                                      filter);
2533                 if (rc)
2534                         break;
2535         }
2536         return rc;
2537 }
2538
2539 void bnxt_free_tunnel_ports(struct bnxt *bp)
2540 {
2541         if (bp->vxlan_port_cnt)
2542                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2543                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2544         bp->vxlan_port = 0;
2545         if (bp->geneve_port_cnt)
2546                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2547                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2548         bp->geneve_port = 0;
2549 }
2550
2551 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2552 {
2553         int i;
2554
2555         if (bp->vnic_info == NULL)
2556                 return;
2557
2558         /*
2559          * Cleanup VNICs in reverse order, to make sure the L2 filter
2560          * from vnic0 is last to be cleaned up.
2561          */
2562         for (i = bp->max_vnics - 1; i >= 0; i--) {
2563                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2564
2565                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2566                         continue;
2567
2568                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2569
2570                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2571
2572                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2573
2574                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2575
2576                 bnxt_hwrm_vnic_free(bp, vnic);
2577
2578                 rte_free(vnic->fw_grp_ids);
2579         }
2580         /* Ring resources */
2581         bnxt_free_all_hwrm_rings(bp);
2582         bnxt_free_all_hwrm_ring_grps(bp);
2583         bnxt_free_all_hwrm_stat_ctxs(bp);
2584         bnxt_free_tunnel_ports(bp);
2585 }
2586
2587 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2588 {
2589         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2590
2591         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2592                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2593
2594         switch (conf_link_speed) {
2595         case ETH_LINK_SPEED_10M_HD:
2596         case ETH_LINK_SPEED_100M_HD:
2597                 /* FALLTHROUGH */
2598                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2599         }
2600         return hw_link_duplex;
2601 }
2602
2603 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2604 {
2605         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2606 }
2607
2608 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2609 {
2610         uint16_t eth_link_speed = 0;
2611
2612         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2613                 return ETH_LINK_SPEED_AUTONEG;
2614
2615         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2616         case ETH_LINK_SPEED_100M:
2617         case ETH_LINK_SPEED_100M_HD:
2618                 /* FALLTHROUGH */
2619                 eth_link_speed =
2620                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2621                 break;
2622         case ETH_LINK_SPEED_1G:
2623                 eth_link_speed =
2624                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2625                 break;
2626         case ETH_LINK_SPEED_2_5G:
2627                 eth_link_speed =
2628                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2629                 break;
2630         case ETH_LINK_SPEED_10G:
2631                 eth_link_speed =
2632                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2633                 break;
2634         case ETH_LINK_SPEED_20G:
2635                 eth_link_speed =
2636                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2637                 break;
2638         case ETH_LINK_SPEED_25G:
2639                 eth_link_speed =
2640                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2641                 break;
2642         case ETH_LINK_SPEED_40G:
2643                 eth_link_speed =
2644                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2645                 break;
2646         case ETH_LINK_SPEED_50G:
2647                 eth_link_speed =
2648                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2649                 break;
2650         case ETH_LINK_SPEED_100G:
2651                 eth_link_speed =
2652                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2653                 break;
2654         default:
2655                 PMD_DRV_LOG(ERR,
2656                         "Unsupported link speed %d; default to AUTO\n",
2657                         conf_link_speed);
2658                 break;
2659         }
2660         return eth_link_speed;
2661 }
2662
2663 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2664                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2665                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2666                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2667
2668 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2669 {
2670         uint32_t one_speed;
2671
2672         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2673                 return 0;
2674
2675         if (link_speed & ETH_LINK_SPEED_FIXED) {
2676                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2677
2678                 if (one_speed & (one_speed - 1)) {
2679                         PMD_DRV_LOG(ERR,
2680                                 "Invalid advertised speeds (%u) for port %u\n",
2681                                 link_speed, port_id);
2682                         return -EINVAL;
2683                 }
2684                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2685                         PMD_DRV_LOG(ERR,
2686                                 "Unsupported advertised speed (%u) for port %u\n",
2687                                 link_speed, port_id);
2688                         return -EINVAL;
2689                 }
2690         } else {
2691                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2692                         PMD_DRV_LOG(ERR,
2693                                 "Unsupported advertised speeds (%u) for port %u\n",
2694                                 link_speed, port_id);
2695                         return -EINVAL;
2696                 }
2697         }
2698         return 0;
2699 }
2700
2701 static uint16_t
2702 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2703 {
2704         uint16_t ret = 0;
2705
2706         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2707                 if (bp->link_info.support_speeds)
2708                         return bp->link_info.support_speeds;
2709                 link_speed = BNXT_SUPPORTED_SPEEDS;
2710         }
2711
2712         if (link_speed & ETH_LINK_SPEED_100M)
2713                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2714         if (link_speed & ETH_LINK_SPEED_100M_HD)
2715                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2716         if (link_speed & ETH_LINK_SPEED_1G)
2717                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2718         if (link_speed & ETH_LINK_SPEED_2_5G)
2719                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2720         if (link_speed & ETH_LINK_SPEED_10G)
2721                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2722         if (link_speed & ETH_LINK_SPEED_20G)
2723                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2724         if (link_speed & ETH_LINK_SPEED_25G)
2725                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2726         if (link_speed & ETH_LINK_SPEED_40G)
2727                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2728         if (link_speed & ETH_LINK_SPEED_50G)
2729                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2730         if (link_speed & ETH_LINK_SPEED_100G)
2731                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2732         return ret;
2733 }
2734
2735 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2736 {
2737         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2738
2739         switch (hw_link_speed) {
2740         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2741                 eth_link_speed = ETH_SPEED_NUM_100M;
2742                 break;
2743         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2744                 eth_link_speed = ETH_SPEED_NUM_1G;
2745                 break;
2746         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2747                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2748                 break;
2749         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2750                 eth_link_speed = ETH_SPEED_NUM_10G;
2751                 break;
2752         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2753                 eth_link_speed = ETH_SPEED_NUM_20G;
2754                 break;
2755         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2756                 eth_link_speed = ETH_SPEED_NUM_25G;
2757                 break;
2758         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2759                 eth_link_speed = ETH_SPEED_NUM_40G;
2760                 break;
2761         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2762                 eth_link_speed = ETH_SPEED_NUM_50G;
2763                 break;
2764         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2765                 eth_link_speed = ETH_SPEED_NUM_100G;
2766                 break;
2767         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2768         default:
2769                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2770                         hw_link_speed);
2771                 break;
2772         }
2773         return eth_link_speed;
2774 }
2775
2776 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2777 {
2778         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2779
2780         switch (hw_link_duplex) {
2781         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2782         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2783                 /* FALLTHROUGH */
2784                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2785                 break;
2786         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2787                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2788                 break;
2789         default:
2790                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2791                         hw_link_duplex);
2792                 break;
2793         }
2794         return eth_link_duplex;
2795 }
2796
2797 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2798 {
2799         int rc = 0;
2800         struct bnxt_link_info *link_info = &bp->link_info;
2801
2802         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2803         if (rc) {
2804                 PMD_DRV_LOG(ERR,
2805                         "Get link config failed with rc %d\n", rc);
2806                 goto exit;
2807         }
2808         if (link_info->link_speed)
2809                 link->link_speed =
2810                         bnxt_parse_hw_link_speed(link_info->link_speed);
2811         else
2812                 link->link_speed = ETH_SPEED_NUM_NONE;
2813         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2814         link->link_status = link_info->link_up;
2815         link->link_autoneg = link_info->auto_mode ==
2816                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2817                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2818 exit:
2819         return rc;
2820 }
2821
2822 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2823 {
2824         int rc = 0;
2825         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2826         struct bnxt_link_info link_req;
2827         uint16_t speed, autoneg;
2828
2829         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2830                 return 0;
2831
2832         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2833                         bp->eth_dev->data->port_id);
2834         if (rc)
2835                 goto error;
2836
2837         memset(&link_req, 0, sizeof(link_req));
2838         link_req.link_up = link_up;
2839         if (!link_up)
2840                 goto port_phy_cfg;
2841
2842         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2843         if (BNXT_CHIP_THOR(bp) &&
2844             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2845                 /* 40G is not supported as part of media auto detect.
2846                  * The speed should be forced and autoneg disabled
2847                  * to configure 40G speed.
2848                  */
2849                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2850                 autoneg = 0;
2851         }
2852
2853         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2854         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2855         /* Autoneg can be done only when the FW allows.
2856          * When user configures fixed speed of 40G and later changes to
2857          * any other speed, auto_link_speed/force_link_speed is still set
2858          * to 40G until link comes up at new speed.
2859          */
2860         if (autoneg == 1 &&
2861             !(!BNXT_CHIP_THOR(bp) &&
2862               (bp->link_info.auto_link_speed ||
2863                bp->link_info.force_link_speed))) {
2864                 link_req.phy_flags |=
2865                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2866                 link_req.auto_link_speed_mask =
2867                         bnxt_parse_eth_link_speed_mask(bp,
2868                                                        dev_conf->link_speeds);
2869         } else {
2870                 if (bp->link_info.phy_type ==
2871                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2872                     bp->link_info.phy_type ==
2873                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2874                     bp->link_info.media_type ==
2875                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2876                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2877                         return -EINVAL;
2878                 }
2879
2880                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2881                 /* If user wants a particular speed try that first. */
2882                 if (speed)
2883                         link_req.link_speed = speed;
2884                 else if (bp->link_info.force_link_speed)
2885                         link_req.link_speed = bp->link_info.force_link_speed;
2886                 else
2887                         link_req.link_speed = bp->link_info.auto_link_speed;
2888         }
2889         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2890         link_req.auto_pause = bp->link_info.auto_pause;
2891         link_req.force_pause = bp->link_info.force_pause;
2892
2893 port_phy_cfg:
2894         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2895         if (rc) {
2896                 PMD_DRV_LOG(ERR,
2897                         "Set link config failed with rc %d\n", rc);
2898         }
2899
2900 error:
2901         return rc;
2902 }
2903
2904 /* JIRA 22088 */
2905 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2906 {
2907         struct hwrm_func_qcfg_input req = {0};
2908         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2909         uint16_t flags;
2910         int rc = 0;
2911
2912         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2913         req.fid = rte_cpu_to_le_16(0xffff);
2914
2915         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2916
2917         HWRM_CHECK_RESULT();
2918
2919         /* Hard Coded.. 0xfff VLAN ID mask */
2920         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2921         flags = rte_le_to_cpu_16(resp->flags);
2922         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2923                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2924
2925         if (BNXT_VF(bp) &&
2926             !BNXT_VF_IS_TRUSTED(bp) &&
2927             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2928                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2929                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2930         } else if (BNXT_VF(bp) &&
2931                    BNXT_VF_IS_TRUSTED(bp) &&
2932                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2933                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2934                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2935         }
2936
2937         if (mtu)
2938                 *mtu = rte_le_to_cpu_16(resp->mtu);
2939
2940         switch (resp->port_partition_type) {
2941         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2942         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2943         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2944                 /* FALLTHROUGH */
2945                 bp->port_partition_type = resp->port_partition_type;
2946                 break;
2947         default:
2948                 bp->port_partition_type = 0;
2949                 break;
2950         }
2951
2952         HWRM_UNLOCK();
2953
2954         return rc;
2955 }
2956
2957 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2958                                    struct hwrm_func_qcaps_output *qcaps)
2959 {
2960         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2961         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2962                sizeof(qcaps->mac_address));
2963         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2964         qcaps->max_rx_rings = fcfg->num_rx_rings;
2965         qcaps->max_tx_rings = fcfg->num_tx_rings;
2966         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2967         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2968         qcaps->max_vfs = 0;
2969         qcaps->first_vf_id = 0;
2970         qcaps->max_vnics = fcfg->num_vnics;
2971         qcaps->max_decap_records = 0;
2972         qcaps->max_encap_records = 0;
2973         qcaps->max_tx_wm_flows = 0;
2974         qcaps->max_tx_em_flows = 0;
2975         qcaps->max_rx_wm_flows = 0;
2976         qcaps->max_rx_em_flows = 0;
2977         qcaps->max_flow_id = 0;
2978         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2979         qcaps->max_sp_tx_rings = 0;
2980         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2981 }
2982
2983 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2984 {
2985         struct hwrm_func_cfg_input req = {0};
2986         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2987         uint32_t enables;
2988         int rc;
2989
2990         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2991                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2992                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2993                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2994                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2995                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2996                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2997                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2998                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2999
3000         if (BNXT_HAS_RING_GRPS(bp)) {
3001                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3002                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3003         } else if (BNXT_HAS_NQ(bp)) {
3004                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3005                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3006         }
3007
3008         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3009         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3010         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3011         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3012         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3013         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3014         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3015         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3016         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3017         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3018         req.fid = rte_cpu_to_le_16(0xffff);
3019         req.enables = rte_cpu_to_le_32(enables);
3020
3021         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3022
3023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3024
3025         HWRM_CHECK_RESULT();
3026         HWRM_UNLOCK();
3027
3028         return rc;
3029 }
3030
3031 static void populate_vf_func_cfg_req(struct bnxt *bp,
3032                                      struct hwrm_func_cfg_input *req,
3033                                      int num_vfs)
3034 {
3035         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3036                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3037                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3038                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3039                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3040                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3041                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3042                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3043                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3044                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3045
3046         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3047                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3048                                     BNXT_NUM_VLANS);
3049         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3050         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3051                                                 (num_vfs + 1));
3052         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3053         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3054                                                (num_vfs + 1));
3055         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3056         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3057         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3058         /* TODO: For now, do not support VMDq/RFS on VFs. */
3059         req->num_vnics = rte_cpu_to_le_16(1);
3060         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3061                                                  (num_vfs + 1));
3062 }
3063
3064 static void add_random_mac_if_needed(struct bnxt *bp,
3065                                      struct hwrm_func_cfg_input *cfg_req,
3066                                      int vf)
3067 {
3068         struct rte_ether_addr mac;
3069
3070         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3071                 return;
3072
3073         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3074                 cfg_req->enables |=
3075                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3076                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3077                 bp->pf.vf_info[vf].random_mac = true;
3078         } else {
3079                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3080                         RTE_ETHER_ADDR_LEN);
3081         }
3082 }
3083
3084 static void reserve_resources_from_vf(struct bnxt *bp,
3085                                       struct hwrm_func_cfg_input *cfg_req,
3086                                       int vf)
3087 {
3088         struct hwrm_func_qcaps_input req = {0};
3089         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3090         int rc;
3091
3092         /* Get the actual allocated values now */
3093         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3094         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3096
3097         if (rc) {
3098                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3099                 copy_func_cfg_to_qcaps(cfg_req, resp);
3100         } else if (resp->error_code) {
3101                 rc = rte_le_to_cpu_16(resp->error_code);
3102                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3103                 copy_func_cfg_to_qcaps(cfg_req, resp);
3104         }
3105
3106         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3107         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3108         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3109         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3110         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3111         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3112         /*
3113          * TODO: While not supporting VMDq with VFs, max_vnics is always
3114          * forced to 1 in this case
3115          */
3116         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3117         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3118
3119         HWRM_UNLOCK();
3120 }
3121
3122 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3123 {
3124         struct hwrm_func_qcfg_input req = {0};
3125         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3126         int rc;
3127
3128         /* Check for zero MAC address */
3129         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3130         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3132         HWRM_CHECK_RESULT();
3133         rc = rte_le_to_cpu_16(resp->vlan);
3134
3135         HWRM_UNLOCK();
3136
3137         return rc;
3138 }
3139
3140 static int update_pf_resource_max(struct bnxt *bp)
3141 {
3142         struct hwrm_func_qcfg_input req = {0};
3143         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3144         int rc;
3145
3146         /* And copy the allocated numbers into the pf struct */
3147         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3148         req.fid = rte_cpu_to_le_16(0xffff);
3149         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3150         HWRM_CHECK_RESULT();
3151
3152         /* Only TX ring value reflects actual allocation? TODO */
3153         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3154         bp->pf.evb_mode = resp->evb_mode;
3155
3156         HWRM_UNLOCK();
3157
3158         return rc;
3159 }
3160
3161 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3162 {
3163         int rc;
3164
3165         if (!BNXT_PF(bp)) {
3166                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3167                 return -EINVAL;
3168         }
3169
3170         rc = bnxt_hwrm_func_qcaps(bp);
3171         if (rc)
3172                 return rc;
3173
3174         bp->pf.func_cfg_flags &=
3175                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3176                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3177         bp->pf.func_cfg_flags |=
3178                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3179         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3180         rc = __bnxt_hwrm_func_qcaps(bp);
3181         return rc;
3182 }
3183
3184 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3185 {
3186         struct hwrm_func_cfg_input req = {0};
3187         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3188         int i;
3189         size_t sz;
3190         int rc = 0;
3191         size_t req_buf_sz;
3192
3193         if (!BNXT_PF(bp)) {
3194                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3195                 return -EINVAL;
3196         }
3197
3198         rc = bnxt_hwrm_func_qcaps(bp);
3199
3200         if (rc)
3201                 return rc;
3202
3203         bp->pf.active_vfs = num_vfs;
3204
3205         /*
3206          * First, configure the PF to only use one TX ring.  This ensures that
3207          * there are enough rings for all VFs.
3208          *
3209          * If we don't do this, when we call func_alloc() later, we will lock
3210          * extra rings to the PF that won't be available during func_cfg() of
3211          * the VFs.
3212          *
3213          * This has been fixed with firmware versions above 20.6.54
3214          */
3215         bp->pf.func_cfg_flags &=
3216                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3217                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3218         bp->pf.func_cfg_flags |=
3219                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3220         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3221         if (rc)
3222                 return rc;
3223
3224         /*
3225          * Now, create and register a buffer to hold forwarded VF requests
3226          */
3227         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3228         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3229                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3230         if (bp->pf.vf_req_buf == NULL) {
3231                 rc = -ENOMEM;
3232                 goto error_free;
3233         }
3234         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3235                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3236         for (i = 0; i < num_vfs; i++)
3237                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3238                                         (i * HWRM_MAX_REQ_LEN);
3239
3240         rc = bnxt_hwrm_func_buf_rgtr(bp);
3241         if (rc)
3242                 goto error_free;
3243
3244         populate_vf_func_cfg_req(bp, &req, num_vfs);
3245
3246         bp->pf.active_vfs = 0;
3247         for (i = 0; i < num_vfs; i++) {
3248                 add_random_mac_if_needed(bp, &req, i);
3249
3250                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3251                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3252                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3253                 rc = bnxt_hwrm_send_message(bp,
3254                                             &req,
3255                                             sizeof(req),
3256                                             BNXT_USE_CHIMP_MB);
3257
3258                 /* Clear enable flag for next pass */
3259                 req.enables &= ~rte_cpu_to_le_32(
3260                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3261
3262                 if (rc || resp->error_code) {
3263                         PMD_DRV_LOG(ERR,
3264                                 "Failed to initizlie VF %d\n", i);
3265                         PMD_DRV_LOG(ERR,
3266                                 "Not all VFs available. (%d, %d)\n",
3267                                 rc, resp->error_code);
3268                         HWRM_UNLOCK();
3269                         break;
3270                 }
3271
3272                 HWRM_UNLOCK();
3273
3274                 reserve_resources_from_vf(bp, &req, i);
3275                 bp->pf.active_vfs++;
3276                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3277         }
3278
3279         /*
3280          * Now configure the PF to use "the rest" of the resources
3281          * We're using STD_TX_RING_MODE here though which will limit the TX
3282          * rings.  This will allow QoS to function properly.  Not setting this
3283          * will cause PF rings to break bandwidth settings.
3284          */
3285         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3286         if (rc)
3287                 goto error_free;
3288
3289         rc = update_pf_resource_max(bp);
3290         if (rc)
3291                 goto error_free;
3292
3293         return rc;
3294
3295 error_free:
3296         bnxt_hwrm_func_buf_unrgtr(bp);
3297         return rc;
3298 }
3299
3300 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3301 {
3302         struct hwrm_func_cfg_input req = {0};
3303         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3304         int rc;
3305
3306         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3307
3308         req.fid = rte_cpu_to_le_16(0xffff);
3309         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3310         req.evb_mode = bp->pf.evb_mode;
3311
3312         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3313         HWRM_CHECK_RESULT();
3314         HWRM_UNLOCK();
3315
3316         return rc;
3317 }
3318
3319 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3320                                 uint8_t tunnel_type)
3321 {
3322         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3323         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3324         int rc = 0;
3325
3326         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3327         req.tunnel_type = tunnel_type;
3328         req.tunnel_dst_port_val = port;
3329         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330         HWRM_CHECK_RESULT();
3331
3332         switch (tunnel_type) {
3333         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3334                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3335                 bp->vxlan_port = port;
3336                 break;
3337         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3338                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3339                 bp->geneve_port = port;
3340                 break;
3341         default:
3342                 break;
3343         }
3344
3345         HWRM_UNLOCK();
3346
3347         return rc;
3348 }
3349
3350 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3351                                 uint8_t tunnel_type)
3352 {
3353         struct hwrm_tunnel_dst_port_free_input req = {0};
3354         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3355         int rc = 0;
3356
3357         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3358
3359         req.tunnel_type = tunnel_type;
3360         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3362
3363         HWRM_CHECK_RESULT();
3364         HWRM_UNLOCK();
3365
3366         return rc;
3367 }
3368
3369 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3370                                         uint32_t flags)
3371 {
3372         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3373         struct hwrm_func_cfg_input req = {0};
3374         int rc;
3375
3376         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3377
3378         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3379         req.flags = rte_cpu_to_le_32(flags);
3380         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3381
3382         HWRM_CHECK_RESULT();
3383         HWRM_UNLOCK();
3384
3385         return rc;
3386 }
3387
3388 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3389 {
3390         uint32_t *flag = flagp;
3391
3392         vnic->flags = *flag;
3393 }
3394
3395 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3396 {
3397         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3398 }
3399
3400 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3401 {
3402         int rc = 0;
3403         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3404         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3405
3406         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3407
3408         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3409         req.req_buf_page_size = rte_cpu_to_le_16(
3410                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3411         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3412         req.req_buf_page_addr0 =
3413                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3414         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3415                 PMD_DRV_LOG(ERR,
3416                         "unable to map buffer address to physical memory\n");
3417                 return -ENOMEM;
3418         }
3419
3420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3421
3422         HWRM_CHECK_RESULT();
3423         HWRM_UNLOCK();
3424
3425         return rc;
3426 }
3427
3428 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3429 {
3430         int rc = 0;
3431         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3432         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3433
3434         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3435                 return 0;
3436
3437         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3438
3439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3440
3441         HWRM_CHECK_RESULT();
3442         HWRM_UNLOCK();
3443
3444         return rc;
3445 }
3446
3447 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3448 {
3449         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3450         struct hwrm_func_cfg_input req = {0};
3451         int rc;
3452
3453         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3454
3455         req.fid = rte_cpu_to_le_16(0xffff);
3456         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3457         req.enables = rte_cpu_to_le_32(
3458                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3459         req.async_event_cr = rte_cpu_to_le_16(
3460                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3462
3463         HWRM_CHECK_RESULT();
3464         HWRM_UNLOCK();
3465
3466         return rc;
3467 }
3468
3469 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3470 {
3471         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3472         struct hwrm_func_vf_cfg_input req = {0};
3473         int rc;
3474
3475         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3476
3477         req.enables = rte_cpu_to_le_32(
3478                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3479         req.async_event_cr = rte_cpu_to_le_16(
3480                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3482
3483         HWRM_CHECK_RESULT();
3484         HWRM_UNLOCK();
3485
3486         return rc;
3487 }
3488
3489 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3490 {
3491         struct hwrm_func_cfg_input req = {0};
3492         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3493         uint16_t dflt_vlan, fid;
3494         uint32_t func_cfg_flags;
3495         int rc = 0;
3496
3497         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3498
3499         if (is_vf) {
3500                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3501                 fid = bp->pf.vf_info[vf].fid;
3502                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3503         } else {
3504                 fid = rte_cpu_to_le_16(0xffff);
3505                 func_cfg_flags = bp->pf.func_cfg_flags;
3506                 dflt_vlan = bp->vlan;
3507         }
3508
3509         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3510         req.fid = rte_cpu_to_le_16(fid);
3511         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3512         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3513
3514         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3515
3516         HWRM_CHECK_RESULT();
3517         HWRM_UNLOCK();
3518
3519         return rc;
3520 }
3521
3522 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3523                         uint16_t max_bw, uint16_t enables)
3524 {
3525         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3526         struct hwrm_func_cfg_input req = {0};
3527         int rc;
3528
3529         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3530
3531         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3532         req.enables |= rte_cpu_to_le_32(enables);
3533         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3534         req.max_bw = rte_cpu_to_le_32(max_bw);
3535         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3536
3537         HWRM_CHECK_RESULT();
3538         HWRM_UNLOCK();
3539
3540         return rc;
3541 }
3542
3543 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3544 {
3545         struct hwrm_func_cfg_input req = {0};
3546         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3547         int rc = 0;
3548
3549         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3550
3551         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3552         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3553         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3554         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3555
3556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3557
3558         HWRM_CHECK_RESULT();
3559         HWRM_UNLOCK();
3560
3561         return rc;
3562 }
3563
3564 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3565 {
3566         int rc;
3567
3568         if (BNXT_PF(bp))
3569                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3570         else
3571                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3572
3573         return rc;
3574 }
3575
3576 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3577                               void *encaped, size_t ec_size)
3578 {
3579         int rc = 0;
3580         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3581         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3582
3583         if (ec_size > sizeof(req.encap_request))
3584                 return -1;
3585
3586         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3587
3588         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3589         memcpy(req.encap_request, encaped, ec_size);
3590
3591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3592
3593         HWRM_CHECK_RESULT();
3594         HWRM_UNLOCK();
3595
3596         return rc;
3597 }
3598
3599 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3600                                        struct rte_ether_addr *mac)
3601 {
3602         struct hwrm_func_qcfg_input req = {0};
3603         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3604         int rc;
3605
3606         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3607
3608         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3609         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3610
3611         HWRM_CHECK_RESULT();
3612
3613         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3614
3615         HWRM_UNLOCK();
3616
3617         return rc;
3618 }
3619
3620 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3621                             void *encaped, size_t ec_size)
3622 {
3623         int rc = 0;
3624         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3625         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3626
3627         if (ec_size > sizeof(req.encap_request))
3628                 return -1;
3629
3630         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3631
3632         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3633         memcpy(req.encap_request, encaped, ec_size);
3634
3635         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3636
3637         HWRM_CHECK_RESULT();
3638         HWRM_UNLOCK();
3639
3640         return rc;
3641 }
3642
3643 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3644                          struct rte_eth_stats *stats, uint8_t rx)
3645 {
3646         int rc = 0;
3647         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3648         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3649
3650         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3651
3652         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3653
3654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3655
3656         HWRM_CHECK_RESULT();
3657
3658         if (rx) {
3659                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3660                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3661                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3662                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3663                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3664                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3665                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3666                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3667         } else {
3668                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3669                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3670                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3671                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3672                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3673                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3674         }
3675
3676         HWRM_UNLOCK();
3677
3678         return rc;
3679 }
3680
3681 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3682 {
3683         struct hwrm_port_qstats_input req = {0};
3684         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3685         struct bnxt_pf_info *pf = &bp->pf;
3686         int rc;
3687
3688         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3689
3690         req.port_id = rte_cpu_to_le_16(pf->port_id);
3691         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3692         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3694
3695         HWRM_CHECK_RESULT();
3696         HWRM_UNLOCK();
3697
3698         return rc;
3699 }
3700
3701 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3702 {
3703         struct hwrm_port_clr_stats_input req = {0};
3704         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3705         struct bnxt_pf_info *pf = &bp->pf;
3706         int rc;
3707
3708         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3709         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3710             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3711                 return 0;
3712
3713         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3714
3715         req.port_id = rte_cpu_to_le_16(pf->port_id);
3716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3717
3718         HWRM_CHECK_RESULT();
3719         HWRM_UNLOCK();
3720
3721         return rc;
3722 }
3723
3724 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3725 {
3726         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3727         struct hwrm_port_led_qcaps_input req = {0};
3728         int rc;
3729
3730         if (BNXT_VF(bp))
3731                 return 0;
3732
3733         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3734         req.port_id = bp->pf.port_id;
3735         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3736
3737         HWRM_CHECK_RESULT();
3738
3739         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3740                 unsigned int i;
3741
3742                 bp->num_leds = resp->num_leds;
3743                 memcpy(bp->leds, &resp->led0_id,
3744                         sizeof(bp->leds[0]) * bp->num_leds);
3745                 for (i = 0; i < bp->num_leds; i++) {
3746                         struct bnxt_led_info *led = &bp->leds[i];
3747
3748                         uint16_t caps = led->led_state_caps;
3749
3750                         if (!led->led_group_id ||
3751                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3752                                 bp->num_leds = 0;
3753                                 break;
3754                         }
3755                 }
3756         }
3757
3758         HWRM_UNLOCK();
3759
3760         return rc;
3761 }
3762
3763 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3764 {
3765         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3766         struct hwrm_port_led_cfg_input req = {0};
3767         struct bnxt_led_cfg *led_cfg;
3768         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3769         uint16_t duration = 0;
3770         int rc, i;
3771
3772         if (!bp->num_leds || BNXT_VF(bp))
3773                 return -EOPNOTSUPP;
3774
3775         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3776
3777         if (led_on) {
3778                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3779                 duration = rte_cpu_to_le_16(500);
3780         }
3781         req.port_id = bp->pf.port_id;
3782         req.num_leds = bp->num_leds;
3783         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3784         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3785                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3786                 led_cfg->led_id = bp->leds[i].led_id;
3787                 led_cfg->led_state = led_state;
3788                 led_cfg->led_blink_on = duration;
3789                 led_cfg->led_blink_off = duration;
3790                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3791         }
3792
3793         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3794
3795         HWRM_CHECK_RESULT();
3796         HWRM_UNLOCK();
3797
3798         return rc;
3799 }
3800
3801 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3802                                uint32_t *length)
3803 {
3804         int rc;
3805         struct hwrm_nvm_get_dir_info_input req = {0};
3806         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3807
3808         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3809
3810         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3811
3812         HWRM_CHECK_RESULT();
3813
3814         *entries = rte_le_to_cpu_32(resp->entries);
3815         *length = rte_le_to_cpu_32(resp->entry_length);
3816
3817         HWRM_UNLOCK();
3818         return rc;
3819 }
3820
3821 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3822 {
3823         int rc;
3824         uint32_t dir_entries;
3825         uint32_t entry_length;
3826         uint8_t *buf;
3827         size_t buflen;
3828         rte_iova_t dma_handle;
3829         struct hwrm_nvm_get_dir_entries_input req = {0};
3830         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3831
3832         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3833         if (rc != 0)
3834                 return rc;
3835
3836         *data++ = dir_entries;
3837         *data++ = entry_length;
3838         len -= 2;
3839         memset(data, 0xff, len);
3840
3841         buflen = dir_entries * entry_length;
3842         buf = rte_malloc("nvm_dir", buflen, 0);
3843         rte_mem_lock_page(buf);
3844         if (buf == NULL)
3845                 return -ENOMEM;
3846         dma_handle = rte_mem_virt2iova(buf);
3847         if (dma_handle == RTE_BAD_IOVA) {
3848                 PMD_DRV_LOG(ERR,
3849                         "unable to map response address to physical memory\n");
3850                 return -ENOMEM;
3851         }
3852         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3853         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3855
3856         if (rc == 0)
3857                 memcpy(data, buf, len > buflen ? buflen : len);
3858
3859         rte_free(buf);
3860         HWRM_CHECK_RESULT();
3861         HWRM_UNLOCK();
3862
3863         return rc;
3864 }
3865
3866 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3867                              uint32_t offset, uint32_t length,
3868                              uint8_t *data)
3869 {
3870         int rc;
3871         uint8_t *buf;
3872         rte_iova_t dma_handle;
3873         struct hwrm_nvm_read_input req = {0};
3874         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3875
3876         buf = rte_malloc("nvm_item", length, 0);
3877         rte_mem_lock_page(buf);
3878         if (!buf)
3879                 return -ENOMEM;
3880
3881         dma_handle = rte_mem_virt2iova(buf);
3882         if (dma_handle == RTE_BAD_IOVA) {
3883                 PMD_DRV_LOG(ERR,
3884                         "unable to map response address to physical memory\n");
3885                 return -ENOMEM;
3886         }
3887         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3888         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3889         req.dir_idx = rte_cpu_to_le_16(index);
3890         req.offset = rte_cpu_to_le_32(offset);
3891         req.len = rte_cpu_to_le_32(length);
3892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3893         if (rc == 0)
3894                 memcpy(data, buf, length);
3895
3896         rte_free(buf);
3897         HWRM_CHECK_RESULT();
3898         HWRM_UNLOCK();
3899
3900         return rc;
3901 }
3902
3903 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3904 {
3905         int rc;
3906         struct hwrm_nvm_erase_dir_entry_input req = {0};
3907         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3908
3909         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3910         req.dir_idx = rte_cpu_to_le_16(index);
3911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3912         HWRM_CHECK_RESULT();
3913         HWRM_UNLOCK();
3914
3915         return rc;
3916 }
3917
3918
3919 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3920                           uint16_t dir_ordinal, uint16_t dir_ext,
3921                           uint16_t dir_attr, const uint8_t *data,
3922                           size_t data_len)
3923 {
3924         int rc;
3925         struct hwrm_nvm_write_input req = {0};
3926         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3927         rte_iova_t dma_handle;
3928         uint8_t *buf;
3929
3930         buf = rte_malloc("nvm_write", data_len, 0);
3931         rte_mem_lock_page(buf);
3932         if (!buf)
3933                 return -ENOMEM;
3934
3935         dma_handle = rte_mem_virt2iova(buf);
3936         if (dma_handle == RTE_BAD_IOVA) {
3937                 PMD_DRV_LOG(ERR,
3938                         "unable to map response address to physical memory\n");
3939                 return -ENOMEM;
3940         }
3941         memcpy(buf, data, data_len);
3942
3943         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3944
3945         req.dir_type = rte_cpu_to_le_16(dir_type);
3946         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3947         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3948         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3949         req.dir_data_length = rte_cpu_to_le_32(data_len);
3950         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3951
3952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3953
3954         rte_free(buf);
3955         HWRM_CHECK_RESULT();
3956         HWRM_UNLOCK();
3957
3958         return rc;
3959 }
3960
3961 static void
3962 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3963 {
3964         uint32_t *count = cbdata;
3965
3966         *count = *count + 1;
3967 }
3968
3969 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3970                                      struct bnxt_vnic_info *vnic __rte_unused)
3971 {
3972         return 0;
3973 }
3974
3975 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3976 {
3977         uint32_t count = 0;
3978
3979         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3980             &count, bnxt_vnic_count_hwrm_stub);
3981
3982         return count;
3983 }
3984
3985 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3986                                         uint16_t *vnic_ids)
3987 {
3988         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3989         struct hwrm_func_vf_vnic_ids_query_output *resp =
3990                                                 bp->hwrm_cmd_resp_addr;
3991         int rc;
3992
3993         /* First query all VNIC ids */
3994         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3995
3996         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3997         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3998         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3999
4000         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4001                 HWRM_UNLOCK();
4002                 PMD_DRV_LOG(ERR,
4003                 "unable to map VNIC ID table address to physical memory\n");
4004                 return -ENOMEM;
4005         }
4006         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4007         HWRM_CHECK_RESULT();
4008         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4009
4010         HWRM_UNLOCK();
4011
4012         return rc;
4013 }
4014
4015 /*
4016  * This function queries the VNIC IDs  for a specified VF. It then calls
4017  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4018  * Then it calls the hwrm_cb function to program this new vnic configuration.
4019  */
4020 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4021         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4022         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4023 {
4024         struct bnxt_vnic_info vnic;
4025         int rc = 0;
4026         int i, num_vnic_ids;
4027         uint16_t *vnic_ids;
4028         size_t vnic_id_sz;
4029         size_t sz;
4030
4031         /* First query all VNIC ids */
4032         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4033         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4034                         RTE_CACHE_LINE_SIZE);
4035         if (vnic_ids == NULL)
4036                 return -ENOMEM;
4037
4038         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4039                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4040
4041         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4042
4043         if (num_vnic_ids < 0)
4044                 return num_vnic_ids;
4045
4046         /* Retrieve VNIC, update bd_stall then update */
4047
4048         for (i = 0; i < num_vnic_ids; i++) {
4049                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4050                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4051                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4052                 if (rc)
4053                         break;
4054                 if (vnic.mru <= 4)      /* Indicates unallocated */
4055                         continue;
4056
4057                 vnic_cb(&vnic, cbdata);
4058
4059                 rc = hwrm_cb(bp, &vnic);
4060                 if (rc)
4061                         break;
4062         }
4063
4064         rte_free(vnic_ids);
4065
4066         return rc;
4067 }
4068
4069 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4070                                               bool on)
4071 {
4072         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4073         struct hwrm_func_cfg_input req = {0};
4074         int rc;
4075
4076         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4077
4078         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4079         req.enables |= rte_cpu_to_le_32(
4080                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4081         req.vlan_antispoof_mode = on ?
4082                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4083                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4084         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4085
4086         HWRM_CHECK_RESULT();
4087         HWRM_UNLOCK();
4088
4089         return rc;
4090 }
4091
4092 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4093 {
4094         struct bnxt_vnic_info vnic;
4095         uint16_t *vnic_ids;
4096         size_t vnic_id_sz;
4097         int num_vnic_ids, i;
4098         size_t sz;
4099         int rc;
4100
4101         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4102         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4103                         RTE_CACHE_LINE_SIZE);
4104         if (vnic_ids == NULL)
4105                 return -ENOMEM;
4106
4107         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4108                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4109
4110         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4111         if (rc <= 0)
4112                 goto exit;
4113         num_vnic_ids = rc;
4114
4115         /*
4116          * Loop through to find the default VNIC ID.
4117          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4118          * by sending the hwrm_func_qcfg command to the firmware.
4119          */
4120         for (i = 0; i < num_vnic_ids; i++) {
4121                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4122                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4123                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4124                                         bp->pf.first_vf_id + vf);
4125                 if (rc)
4126                         goto exit;
4127                 if (vnic.func_default) {
4128                         rte_free(vnic_ids);
4129                         return vnic.fw_vnic_id;
4130                 }
4131         }
4132         /* Could not find a default VNIC. */
4133         PMD_DRV_LOG(ERR, "No default VNIC\n");
4134 exit:
4135         rte_free(vnic_ids);
4136         return rc;
4137 }
4138
4139 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4140                          uint16_t dst_id,
4141                          struct bnxt_filter_info *filter)
4142 {
4143         int rc = 0;
4144         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4145         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4146         uint32_t enables = 0;
4147
4148         if (filter->fw_em_filter_id != UINT64_MAX)
4149                 bnxt_hwrm_clear_em_filter(bp, filter);
4150
4151         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4152
4153         req.flags = rte_cpu_to_le_32(filter->flags);
4154
4155         enables = filter->enables |
4156               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4157         req.dst_id = rte_cpu_to_le_16(dst_id);
4158
4159         if (filter->ip_addr_type) {
4160                 req.ip_addr_type = filter->ip_addr_type;
4161                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4162         }
4163         if (enables &
4164             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4165                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4166         if (enables &
4167             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4168                 memcpy(req.src_macaddr, filter->src_macaddr,
4169                        RTE_ETHER_ADDR_LEN);
4170         if (enables &
4171             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4172                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4173                        RTE_ETHER_ADDR_LEN);
4174         if (enables &
4175             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4176                 req.ovlan_vid = filter->l2_ovlan;
4177         if (enables &
4178             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4179                 req.ivlan_vid = filter->l2_ivlan;
4180         if (enables &
4181             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4182                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4183         if (enables &
4184             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4185                 req.ip_protocol = filter->ip_protocol;
4186         if (enables &
4187             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4188                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4189         if (enables &
4190             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4191                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4192         if (enables &
4193             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4194                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4195         if (enables &
4196             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4197                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4198         if (enables &
4199             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4200                 req.mirror_vnic_id = filter->mirror_vnic_id;
4201
4202         req.enables = rte_cpu_to_le_32(enables);
4203
4204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4205
4206         HWRM_CHECK_RESULT();
4207
4208         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4209         HWRM_UNLOCK();
4210
4211         return rc;
4212 }
4213
4214 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4215 {
4216         int rc = 0;
4217         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4218         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4219
4220         if (filter->fw_em_filter_id == UINT64_MAX)
4221                 return 0;
4222
4223         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4224
4225         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4226
4227         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4228
4229         HWRM_CHECK_RESULT();
4230         HWRM_UNLOCK();
4231
4232         filter->fw_em_filter_id = UINT64_MAX;
4233         filter->fw_l2_filter_id = UINT64_MAX;
4234
4235         return 0;
4236 }
4237
4238 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4239                          uint16_t dst_id,
4240                          struct bnxt_filter_info *filter)
4241 {
4242         int rc = 0;
4243         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4244         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4245                                                 bp->hwrm_cmd_resp_addr;
4246         uint32_t enables = 0;
4247
4248         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4249                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4250
4251         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4252
4253         req.flags = rte_cpu_to_le_32(filter->flags);
4254
4255         enables = filter->enables |
4256               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4257         req.dst_id = rte_cpu_to_le_16(dst_id);
4258
4259         if (filter->ip_addr_type) {
4260                 req.ip_addr_type = filter->ip_addr_type;
4261                 enables |=
4262                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4263         }
4264         if (enables &
4265             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4266                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4267         if (enables &
4268             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4269                 memcpy(req.src_macaddr, filter->src_macaddr,
4270                        RTE_ETHER_ADDR_LEN);
4271         if (enables &
4272             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4273                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4274         if (enables &
4275             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4276                 req.ip_protocol = filter->ip_protocol;
4277         if (enables &
4278             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4279                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4280         if (enables &
4281             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4282                 req.src_ipaddr_mask[0] =
4283                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4284         if (enables &
4285             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4286                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4287         if (enables &
4288             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4289                 req.dst_ipaddr_mask[0] =
4290                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4291         if (enables &
4292             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4293                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4294         if (enables &
4295             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4296                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4297         if (enables &
4298             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4299                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4300         if (enables &
4301             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4302                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4303         if (enables &
4304             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4305                 req.mirror_vnic_id = filter->mirror_vnic_id;
4306
4307         req.enables = rte_cpu_to_le_32(enables);
4308
4309         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4310
4311         HWRM_CHECK_RESULT();
4312
4313         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4314         HWRM_UNLOCK();
4315
4316         return rc;
4317 }
4318
4319 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4320                                 struct bnxt_filter_info *filter)
4321 {
4322         int rc = 0;
4323         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4324         struct hwrm_cfa_ntuple_filter_free_output *resp =
4325                                                 bp->hwrm_cmd_resp_addr;
4326
4327         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4328                 return 0;
4329
4330         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4331
4332         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4333
4334         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4335
4336         HWRM_CHECK_RESULT();
4337         HWRM_UNLOCK();
4338
4339         filter->fw_ntuple_filter_id = UINT64_MAX;
4340
4341         return 0;
4342 }
4343
4344 static int
4345 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4346 {
4347         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4348         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4349         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4350         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4351         uint16_t *ring_tbl = vnic->rss_table;
4352         int nr_ctxs = vnic->num_lb_ctxts;
4353         int max_rings = bp->rx_nr_rings;
4354         int i, j, k, cnt;
4355         int rc = 0;
4356
4357         for (i = 0, k = 0; i < nr_ctxs; i++) {
4358                 struct bnxt_rx_ring_info *rxr;
4359                 struct bnxt_cp_ring_info *cpr;
4360
4361                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4362
4363                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4364                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4365                 req.hash_mode_flags = vnic->hash_mode;
4366
4367                 req.ring_grp_tbl_addr =
4368                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4369                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4370                                      2 * sizeof(*ring_tbl));
4371                 req.hash_key_tbl_addr =
4372                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4373
4374                 req.ring_table_pair_index = i;
4375                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4376
4377                 for (j = 0; j < 64; j++) {
4378                         uint16_t ring_id;
4379
4380                         /* Find next active ring. */
4381                         for (cnt = 0; cnt < max_rings; cnt++) {
4382                                 if (rx_queue_state[k] !=
4383                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4384                                         break;
4385                                 if (++k == max_rings)
4386                                         k = 0;
4387                         }
4388
4389                         /* Return if no rings are active. */
4390                         if (cnt == max_rings) {
4391                                 HWRM_UNLOCK();
4392                                 return 0;
4393                         }
4394
4395                         /* Add rx/cp ring pair to RSS table. */
4396                         rxr = rxqs[k]->rx_ring;
4397                         cpr = rxqs[k]->cp_ring;
4398
4399                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4400                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4401                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4402                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4403
4404                         if (++k == max_rings)
4405                                 k = 0;
4406                 }
4407                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4408                                             BNXT_USE_CHIMP_MB);
4409
4410                 HWRM_CHECK_RESULT();
4411                 HWRM_UNLOCK();
4412         }
4413
4414         return rc;
4415 }
4416
4417 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4418 {
4419         unsigned int rss_idx, fw_idx, i;
4420
4421         if (!(vnic->rss_table && vnic->hash_type))
4422                 return 0;
4423
4424         if (BNXT_CHIP_THOR(bp))
4425                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4426
4427         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4428                 return 0;
4429
4430         if (vnic->rss_table && vnic->hash_type) {
4431                 /*
4432                  * Fill the RSS hash & redirection table with
4433                  * ring group ids for all VNICs
4434                  */
4435                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4436                         rss_idx++, fw_idx++) {
4437                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4438                                 fw_idx %= bp->rx_cp_nr_rings;
4439                                 if (vnic->fw_grp_ids[fw_idx] !=
4440                                     INVALID_HW_RING_ID)
4441                                         break;
4442                                 fw_idx++;
4443                         }
4444                         if (i == bp->rx_cp_nr_rings)
4445                                 return 0;
4446                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4447                 }
4448                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4449         }
4450
4451         return 0;
4452 }
4453
4454 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4455         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4456 {
4457         uint16_t flags;
4458
4459         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4460
4461         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4462         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4463
4464         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4465         req->num_cmpl_dma_aggr_during_int =
4466                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4467
4468         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4469
4470         /* min timer set to 1/2 of interrupt timer */
4471         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4472
4473         /* buf timer set to 1/4 of interrupt timer */
4474         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4475
4476         req->cmpl_aggr_dma_tmr_during_int =
4477                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4478
4479         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4480                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4481         req->flags = rte_cpu_to_le_16(flags);
4482 }
4483
4484 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4485                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4486 {
4487         struct hwrm_ring_aggint_qcaps_input req = {0};
4488         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4489         uint32_t enables;
4490         uint16_t flags;
4491         int rc;
4492
4493         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4495         HWRM_CHECK_RESULT();
4496
4497         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4498         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4499
4500         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4501                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4502         agg_req->flags = rte_cpu_to_le_16(flags);
4503         enables =
4504          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4505          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4506         agg_req->enables = rte_cpu_to_le_32(enables);
4507
4508         HWRM_UNLOCK();
4509         return rc;
4510 }
4511
4512 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4513                         struct bnxt_coal *coal, uint16_t ring_id)
4514 {
4515         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4516         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4517                                                 bp->hwrm_cmd_resp_addr;
4518         int rc;
4519
4520         /* Set ring coalesce parameters only for 100G NICs */
4521         if (BNXT_CHIP_THOR(bp)) {
4522                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4523                         return -1;
4524         } else if (bnxt_stratus_device(bp)) {
4525                 bnxt_hwrm_set_coal_params(coal, &req);
4526         } else {
4527                 return 0;
4528         }
4529
4530         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4531         req.ring_id = rte_cpu_to_le_16(ring_id);
4532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4533         HWRM_CHECK_RESULT();
4534         HWRM_UNLOCK();
4535         return 0;
4536 }
4537
4538 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4539 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4540 {
4541         struct hwrm_func_backing_store_qcaps_input req = {0};
4542         struct hwrm_func_backing_store_qcaps_output *resp =
4543                 bp->hwrm_cmd_resp_addr;
4544         struct bnxt_ctx_pg_info *ctx_pg;
4545         struct bnxt_ctx_mem_info *ctx;
4546         int total_alloc_len;
4547         int rc, i;
4548
4549         if (!BNXT_CHIP_THOR(bp) ||
4550             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4551             BNXT_VF(bp) ||
4552             bp->ctx)
4553                 return 0;
4554
4555         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4556         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4557         HWRM_CHECK_RESULT_SILENT();
4558
4559         total_alloc_len = sizeof(*ctx);
4560         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4561                           RTE_CACHE_LINE_SIZE);
4562         if (!ctx) {
4563                 rc = -ENOMEM;
4564                 goto ctx_err;
4565         }
4566
4567         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4568                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4569                             RTE_CACHE_LINE_SIZE);
4570         if (!ctx_pg) {
4571                 rc = -ENOMEM;
4572                 goto ctx_err;
4573         }
4574         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4575                 ctx->tqm_mem[i] = ctx_pg;
4576
4577         bp->ctx = ctx;
4578         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4579         ctx->qp_min_qp1_entries =
4580                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4581         ctx->qp_max_l2_entries =
4582                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4583         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4584         ctx->srq_max_l2_entries =
4585                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4586         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4587         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4588         ctx->cq_max_l2_entries =
4589                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4590         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4591         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4592         ctx->vnic_max_vnic_entries =
4593                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4594         ctx->vnic_max_ring_table_entries =
4595                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4596         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4597         ctx->stat_max_entries =
4598                 rte_le_to_cpu_32(resp->stat_max_entries);
4599         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4600         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4601         ctx->tqm_min_entries_per_ring =
4602                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4603         ctx->tqm_max_entries_per_ring =
4604                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4605         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4606         if (!ctx->tqm_entries_multiple)
4607                 ctx->tqm_entries_multiple = 1;
4608         ctx->mrav_max_entries =
4609                 rte_le_to_cpu_32(resp->mrav_max_entries);
4610         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4611         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4612         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4613 ctx_err:
4614         HWRM_UNLOCK();
4615         return rc;
4616 }
4617
4618 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4619 {
4620         struct hwrm_func_backing_store_cfg_input req = {0};
4621         struct hwrm_func_backing_store_cfg_output *resp =
4622                 bp->hwrm_cmd_resp_addr;
4623         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4624         struct bnxt_ctx_pg_info *ctx_pg;
4625         uint32_t *num_entries;
4626         uint64_t *pg_dir;
4627         uint8_t *pg_attr;
4628         uint32_t ena;
4629         int i, rc;
4630
4631         if (!ctx)
4632                 return 0;
4633
4634         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4635         req.enables = rte_cpu_to_le_32(enables);
4636
4637         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4638                 ctx_pg = &ctx->qp_mem;
4639                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4640                 req.qp_num_qp1_entries =
4641                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4642                 req.qp_num_l2_entries =
4643                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4644                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4645                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4646                                       &req.qpc_pg_size_qpc_lvl,
4647                                       &req.qpc_page_dir);
4648         }
4649
4650         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4651                 ctx_pg = &ctx->srq_mem;
4652                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4653                 req.srq_num_l2_entries =
4654                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4655                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4656                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4657                                       &req.srq_pg_size_srq_lvl,
4658                                       &req.srq_page_dir);
4659         }
4660
4661         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4662                 ctx_pg = &ctx->cq_mem;
4663                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4664                 req.cq_num_l2_entries =
4665                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4666                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4667                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4668                                       &req.cq_pg_size_cq_lvl,
4669                                       &req.cq_page_dir);
4670         }
4671
4672         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4673                 ctx_pg = &ctx->vnic_mem;
4674                 req.vnic_num_vnic_entries =
4675                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4676                 req.vnic_num_ring_table_entries =
4677                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4678                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4679                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4680                                       &req.vnic_pg_size_vnic_lvl,
4681                                       &req.vnic_page_dir);
4682         }
4683
4684         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4685                 ctx_pg = &ctx->stat_mem;
4686                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4687                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4688                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4689                                       &req.stat_pg_size_stat_lvl,
4690                                       &req.stat_page_dir);
4691         }
4692
4693         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4694         num_entries = &req.tqm_sp_num_entries;
4695         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4696         pg_dir = &req.tqm_sp_page_dir;
4697         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4698         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4699                 if (!(enables & ena))
4700                         continue;
4701
4702                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4703
4704                 ctx_pg = ctx->tqm_mem[i];
4705                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4706                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4707         }
4708
4709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4710         HWRM_CHECK_RESULT();
4711         HWRM_UNLOCK();
4712
4713         return rc;
4714 }
4715
4716 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4717 {
4718         struct hwrm_port_qstats_ext_input req = {0};
4719         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4720         struct bnxt_pf_info *pf = &bp->pf;
4721         int rc;
4722
4723         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4724               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4725                 return 0;
4726
4727         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4728
4729         req.port_id = rte_cpu_to_le_16(pf->port_id);
4730         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4731                 req.tx_stat_host_addr =
4732                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4733                 req.tx_stat_size =
4734                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4735         }
4736         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4737                 req.rx_stat_host_addr =
4738                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4739                 req.rx_stat_size =
4740                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4741         }
4742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4743
4744         if (rc) {
4745                 bp->fw_rx_port_stats_ext_size = 0;
4746                 bp->fw_tx_port_stats_ext_size = 0;
4747         } else {
4748                 bp->fw_rx_port_stats_ext_size =
4749                         rte_le_to_cpu_16(resp->rx_stat_size);
4750                 bp->fw_tx_port_stats_ext_size =
4751                         rte_le_to_cpu_16(resp->tx_stat_size);
4752         }
4753
4754         HWRM_CHECK_RESULT();
4755         HWRM_UNLOCK();
4756
4757         return rc;
4758 }
4759
4760 int
4761 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4762 {
4763         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4764         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4765                 bp->hwrm_cmd_resp_addr;
4766         int rc = 0;
4767
4768         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4769         req.tunnel_type = type;
4770         req.dest_fid = bp->fw_fid;
4771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4772         HWRM_CHECK_RESULT();
4773
4774         HWRM_UNLOCK();
4775
4776         return rc;
4777 }
4778
4779 int
4780 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4781 {
4782         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4783         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4784                 bp->hwrm_cmd_resp_addr;
4785         int rc = 0;
4786
4787         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4788         req.tunnel_type = type;
4789         req.dest_fid = bp->fw_fid;
4790         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4791         HWRM_CHECK_RESULT();
4792
4793         HWRM_UNLOCK();
4794
4795         return rc;
4796 }
4797
4798 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4799 {
4800         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4801         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4802                 bp->hwrm_cmd_resp_addr;
4803         int rc = 0;
4804
4805         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4806         req.src_fid = bp->fw_fid;
4807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4808         HWRM_CHECK_RESULT();
4809
4810         if (type)
4811                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4812
4813         HWRM_UNLOCK();
4814
4815         return rc;
4816 }
4817
4818 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4819                                    uint16_t *dst_fid)
4820 {
4821         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4822         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4823                 bp->hwrm_cmd_resp_addr;
4824         int rc = 0;
4825
4826         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4827         req.src_fid = bp->fw_fid;
4828         req.tunnel_type = tun_type;
4829         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4830         HWRM_CHECK_RESULT();
4831
4832         if (dst_fid)
4833                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4834
4835         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4836
4837         HWRM_UNLOCK();
4838
4839         return rc;
4840 }
4841
4842 int bnxt_hwrm_set_mac(struct bnxt *bp)
4843 {
4844         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4845         struct hwrm_func_vf_cfg_input req = {0};
4846         int rc = 0;
4847
4848         if (!BNXT_VF(bp))
4849                 return 0;
4850
4851         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4852
4853         req.enables =
4854                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4855         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4856
4857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4858
4859         HWRM_CHECK_RESULT();
4860
4861         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4862         HWRM_UNLOCK();
4863
4864         return rc;
4865 }
4866
4867 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4868 {
4869         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4870         struct hwrm_func_drv_if_change_input req = {0};
4871         uint32_t flags;
4872         int rc;
4873
4874         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4875                 return 0;
4876
4877         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4878          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4879          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4880          */
4881         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4882                 return 0;
4883
4884         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4885
4886         if (up)
4887                 req.flags =
4888                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4889
4890         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4891
4892         HWRM_CHECK_RESULT();
4893         flags = rte_le_to_cpu_32(resp->flags);
4894         HWRM_UNLOCK();
4895
4896         if (!up)
4897                 return 0;
4898
4899         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4900                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4901                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4902         }
4903
4904         return 0;
4905 }
4906
4907 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4908 {
4909         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4910         struct bnxt_error_recovery_info *info = bp->recovery_info;
4911         struct hwrm_error_recovery_qcfg_input req = {0};
4912         uint32_t flags = 0;
4913         unsigned int i;
4914         int rc;
4915
4916         /* Older FW does not have error recovery support */
4917         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4918                 return 0;
4919
4920         if (!info) {
4921                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4922                                    sizeof(*info), 0);
4923                 bp->recovery_info = info;
4924                 if (info == NULL)
4925                         return -ENOMEM;
4926         } else {
4927                 memset(info, 0, sizeof(*info));
4928         }
4929
4930         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4931
4932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4933
4934         HWRM_CHECK_RESULT();
4935
4936         flags = rte_le_to_cpu_32(resp->flags);
4937         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4938                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4939         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4940                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4941
4942         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4943             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4944                 rc = -EINVAL;
4945                 goto err;
4946         }
4947
4948         /* FW returned values are in units of 100msec */
4949         info->driver_polling_freq =
4950                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4951         info->master_func_wait_period =
4952                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4953         info->normal_func_wait_period =
4954                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4955         info->master_func_wait_period_after_reset =
4956                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4957         info->max_bailout_time_after_reset =
4958                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4959         info->status_regs[BNXT_FW_STATUS_REG] =
4960                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4961         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4962                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4963         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4964                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4965         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4966                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4967         info->reg_array_cnt =
4968                 rte_le_to_cpu_32(resp->reg_array_cnt);
4969
4970         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4971                 rc = -EINVAL;
4972                 goto err;
4973         }
4974
4975         for (i = 0; i < info->reg_array_cnt; i++) {
4976                 info->reset_reg[i] =
4977                         rte_le_to_cpu_32(resp->reset_reg[i]);
4978                 info->reset_reg_val[i] =
4979                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4980                 info->delay_after_reset[i] =
4981                         resp->delay_after_reset[i];
4982         }
4983 err:
4984         HWRM_UNLOCK();
4985
4986         /* Map the FW status registers */
4987         if (!rc)
4988                 rc = bnxt_map_fw_health_status_regs(bp);
4989
4990         if (rc) {
4991                 rte_free(bp->recovery_info);
4992                 bp->recovery_info = NULL;
4993         }
4994         return rc;
4995 }
4996
4997 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4998 {
4999         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5000         struct hwrm_fw_reset_input req = {0};
5001         int rc;
5002
5003         if (!BNXT_PF(bp))
5004                 return -EOPNOTSUPP;
5005
5006         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
5007
5008         req.embedded_proc_type =
5009                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5010         req.selfrst_status =
5011                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5012         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5013
5014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5015                                     BNXT_USE_KONG(bp));
5016
5017         HWRM_CHECK_RESULT();
5018         HWRM_UNLOCK();
5019
5020         return rc;
5021 }
5022
5023 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5024 {
5025         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5026         struct hwrm_port_ts_query_input req = {0};
5027         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5028         uint32_t flags = 0;
5029         int rc;
5030
5031         if (!ptp)
5032                 return 0;
5033
5034         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5035
5036         switch (path) {
5037         case BNXT_PTP_FLAGS_PATH_TX:
5038                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5039                 break;
5040         case BNXT_PTP_FLAGS_PATH_RX:
5041                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5042                 break;
5043         case BNXT_PTP_FLAGS_CURRENT_TIME:
5044                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5045                 break;
5046         }
5047
5048         req.flags = rte_cpu_to_le_32(flags);
5049         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5050
5051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5052
5053         HWRM_CHECK_RESULT();
5054
5055         if (timestamp) {
5056                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5057                 *timestamp |=
5058                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5059         }
5060         HWRM_UNLOCK();
5061
5062         return rc;
5063 }
5064
5065 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5066 {
5067         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5068                                         bp->hwrm_cmd_resp_addr;
5069         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5070         uint32_t flags = 0;
5071         int rc = 0;
5072
5073         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5074                 return rc;
5075
5076         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5077                 PMD_DRV_LOG(DEBUG,
5078                             "Not a PF or trusted VF. Command not supported\n");
5079                 return 0;
5080         }
5081
5082         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5084
5085         HWRM_CHECK_RESULT();
5086         flags = rte_le_to_cpu_32(resp->flags);
5087         HWRM_UNLOCK();
5088
5089         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5090                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5091                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5092         }
5093
5094         return rc;
5095 }