drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc > 0) \
 223                         rc = -EINVAL; \
 224                 return rc; \
 225         } \
 226         if (resp->error_code) { \
 227                 rc = rte_le_to_cpu_16(resp->error_code); \
 228                 if (resp->resp_len >= 16) { \
 229                         struct hwrm_err_output *tmp_hwrm_err_op = \
 230                                                 (void *)resp; \
 231                         PMD_DRV_LOG(ERR, \
 232                                 "error %d:%d:%08x:%04x\n", \
 233                                 rc, tmp_hwrm_err_op->cmd_err, \
 234                                 rte_le_to_cpu_32(\
 235                                         tmp_hwrm_err_op->opaque_0), \
 236                                 rte_le_to_cpu_16(\
 237                                         tmp_hwrm_err_op->opaque_1)); \
 238                 } else { \
 239                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 240                 } \
 241                 rte_spinlock_unlock(&bp->hwrm_lock); \
 242                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 243                         rc = -EACCES; \
 244                 else if (rc > 0) \
 245                         rc = -EINVAL; \
 246                 return rc; \
 247         } \
 248 } while (0)
 249
 250 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 251
 252 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 253 {
 254         int rc = 0;
 255         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 256         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 257
 258         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 259         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 260         req.mask = 0;
 261
 262         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 263
 264         HWRM_CHECK_RESULT();
 265         HWRM_UNLOCK();
 266
 267         return rc;
 268 }
 269
 270 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 271                                  struct bnxt_vnic_info *vnic,
 272                                  uint16_t vlan_count,
 273                                  struct bnxt_vlan_table_entry *vlan_table)
 274 {
 275         int rc = 0;
 276         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 277         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 278         uint32_t mask = 0;
 279
 280         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 281                 return rc;
 282
 283         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 284         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 285
 286         /* FIXME add multicast flag, when multicast adding options is supported
 287          * by ethtool.
 288          */
 289         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 290                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 291         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 292                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 293         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 294                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 295         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 296                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 297         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 298                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 299         if (vnic->mc_addr_cnt) {
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 301                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 302                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 303         }
 304         if (vlan_table) {
 305                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 306                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 307                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 308                          rte_mem_virt2iova(vlan_table));
 309                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 310         }
 311         req.mask = rte_cpu_to_le_32(mask);
 312
 313         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 314
 315         HWRM_CHECK_RESULT();
 316         HWRM_UNLOCK();
 317
 318         return rc;
 319 }
 320
 321 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 322                         uint16_t vlan_count,
 323                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 324 {
 325         int rc = 0;
 326         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 327         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 328                                                 bp->hwrm_cmd_resp_addr;
 329
 330         /*
 331          * Older HWRM versions did not support this command, and the set_rx_mask
 332          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 333          * removed from set_rx_mask call, and this command was added.
 334          *
 335          * This command is also present from 1.7.8.11 and higher,
 336          * as well as 1.7.8.0
 337          */
 338         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 339                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 340                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 341                                         (11)))
 342                                 return 0;
 343                 }
 344         }
 345         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 346         req.fid = rte_cpu_to_le_16(fid);
 347
 348         req.vlan_tag_mask_tbl_addr =
 349                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 350         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 351
 352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 353
 354         HWRM_CHECK_RESULT();
 355         HWRM_UNLOCK();
 356
 357         return rc;
 358 }
 359
 360 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 361                            struct bnxt_filter_info *filter)
 362 {
 363         int rc = 0;
 364         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 365         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 366
 367         if (filter->fw_l2_filter_id == UINT64_MAX)
 368                 return 0;
 369
 370         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 371
 372         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 373
 374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 375
 376         HWRM_CHECK_RESULT();
 377         HWRM_UNLOCK();
 378
 379         filter->fw_l2_filter_id = UINT64_MAX;
 380
 381         return 0;
 382 }
 383
 384 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 385                          uint16_t dst_id,
 386                          struct bnxt_filter_info *filter)
 387 {
 388         int rc = 0;
 389         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 390         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 391         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 392         const struct rte_eth_vmdq_rx_conf *conf =
 393                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 394         uint32_t enables = 0;
 395         uint16_t j = dst_id - 1;
 396
 397         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 398         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 399             conf->pool_map[j].pools & (1UL << j)) {
 400                 PMD_DRV_LOG(DEBUG,
 401                         "Add vlan %u to vmdq pool %u\n",
 402                         conf->pool_map[j].vlan_id, j);
 403
 404                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 405                 filter->enables |=
 406                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 407                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 408         }
 409
 410         if (filter->fw_l2_filter_id != UINT64_MAX)
 411                 bnxt_hwrm_clear_l2_filter(bp, filter);
 412
 413         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 414
 415         req.flags = rte_cpu_to_le_32(filter->flags);
 416         req.flags |=
 417         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 418
 419         enables = filter->enables |
 420               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 421         req.dst_id = rte_cpu_to_le_16(dst_id);
 422
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 425                 memcpy(req.l2_addr, filter->l2_addr,
 426                        RTE_ETHER_ADDR_LEN);
 427         if (enables &
 428             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 429                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 430                        RTE_ETHER_ADDR_LEN);
 431         if (enables &
 432             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 433                 req.l2_ovlan = filter->l2_ovlan;
 434         if (enables &
 435             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 436                 req.l2_ivlan = filter->l2_ivlan;
 437         if (enables &
 438             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 439                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 440         if (enables &
 441             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 442                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 443         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 444                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 445         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 446                 req.src_type = filter->src_type;
 447
 448         req.enables = rte_cpu_to_le_32(enables);
 449
 450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 451
 452         HWRM_CHECK_RESULT();
 453
 454         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 455         HWRM_UNLOCK();
 456
 457         return rc;
 458 }
 459
 460 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 461 {
 462         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 463         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 464         uint32_t flags = 0;
 465         int rc;
 466
 467         if (!ptp)
 468                 return 0;
 469
 470         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 471
 472         if (ptp->rx_filter)
 473                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 474         else
 475                 flags |=
 476                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 477         if (ptp->tx_tstamp_en)
 478                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 479         else
 480                 flags |=
 481                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 482         req.flags = rte_cpu_to_le_32(flags);
 483         req.enables = rte_cpu_to_le_32
 484                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 485         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 486
 487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 488         HWRM_UNLOCK();
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 494 {
 495         int rc = 0;
 496         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 497         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 498         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 499
 500 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 501         if (ptp)
 502                 return 0;
 503
 504         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 505
 506         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509
 510         HWRM_CHECK_RESULT();
 511
 512         if (!BNXT_CHIP_THOR(bp) &&
 513             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 514                 return 0;
 515
 516         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 517                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 518
 519         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 520         if (!ptp)
 521                 return -ENOMEM;
 522
 523         if (!BNXT_CHIP_THOR(bp)) {
 524                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 525                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 526                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 527                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 528                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 529                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 530                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 531                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 532                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 533                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 534                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 535                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 536                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 537                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 538                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 539                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 540                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 541                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 542         }
 543
 544         ptp->bp = bp;
 545         bp->ptp_cfg = ptp;
 546
 547         return 0;
 548 }
 549
 550 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 551 {
 552         int rc = 0;
 553         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 554         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 555         uint16_t new_max_vfs;
 556         uint32_t flags;
 557         int i;
 558
 559         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 560
 561         req.fid = rte_cpu_to_le_16(0xffff);
 562
 563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 564
 565         HWRM_CHECK_RESULT();
 566
 567         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 568         flags = rte_le_to_cpu_32(resp->flags);
 569         if (BNXT_PF(bp)) {
 570                 bp->pf.port_id = resp->port_id;
 571                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 572                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 573                 new_max_vfs = bp->pdev->max_vfs;
 574                 if (new_max_vfs != bp->pf.max_vfs) {
 575                         if (bp->pf.vf_info)
 576                                 rte_free(bp->pf.vf_info);
 577                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 578                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 579                         bp->pf.max_vfs = new_max_vfs;
 580                         for (i = 0; i < new_max_vfs; i++) {
 581                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 582                                 bp->pf.vf_info[i].vlan_table =
 583                                         rte_zmalloc("VF VLAN table",
 584                                                     getpagesize(),
 585                                                     getpagesize());
 586                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 587                                         PMD_DRV_LOG(ERR,
 588                                         "Fail to alloc VLAN table for VF %d\n",
 589                                         i);
 590                                 else
 591                                         rte_mem_lock_page(
 592                                                 bp->pf.vf_info[i].vlan_table);
 593                                 bp->pf.vf_info[i].vlan_as_table =
 594                                         rte_zmalloc("VF VLAN AS table",
 595                                                     getpagesize(),
 596                                                     getpagesize());
 597                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 598                                         PMD_DRV_LOG(ERR,
 599                                         "Alloc VLAN AS table for VF %d fail\n",
 600                                         i);
 601                                 else
 602                                         rte_mem_lock_page(
 603                                                bp->pf.vf_info[i].vlan_as_table);
 604                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 605                         }
 606                 }
 607         }
 608
 609         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 610         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 611         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 612         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 613         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 614         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 615         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 616         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 617         bp->max_l2_ctx =
 618                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 619         /* TODO: For now, do not support VMDq/RFS on VFs. */
 620         if (BNXT_PF(bp)) {
 621                 if (bp->pf.max_vfs)
 622                         bp->max_vnics = 1;
 623                 else
 624                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 625         } else {
 626                 bp->max_vnics = 1;
 627         }
 628         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 629         if (BNXT_PF(bp)) {
 630                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 631                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 632                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 633                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 634                         HWRM_UNLOCK();
 635                         bnxt_hwrm_ptp_qcfg(bp);
 636                 }
 637         }
 638
 639         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 640                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 641
 642         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 643                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 644                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 645         } else {
 646                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 647         }
 648
 649         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 650                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 651         else
 652                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 653
 654         HWRM_UNLOCK();
 655
 656         return rc;
 657 }
 658
 659 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 660 {
 661         int rc;
 662
 663         rc = __bnxt_hwrm_func_qcaps(bp);
 664         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 665                 rc = bnxt_alloc_ctx_mem(bp);
 666                 if (rc)
 667                         return rc;
 668
 669                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 670                 if (!rc)
 671                         bp->flags |= BNXT_FLAG_NEW_RM;
 672         }
 673
 674         return rc;
 675 }
 676
 677 int bnxt_hwrm_func_reset(struct bnxt *bp)
 678 {
 679         int rc = 0;
 680         struct hwrm_func_reset_input req = {.req_type = 0 };
 681         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 682
 683         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 684
 685         req.enables = rte_cpu_to_le_32(0);
 686
 687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 688
 689         HWRM_CHECK_RESULT();
 690         HWRM_UNLOCK();
 691
 692         return rc;
 693 }
 694
 695 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 696 {
 697         int rc;
 698         uint32_t flags = 0;
 699         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 700         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 701
 702         if (bp->flags & BNXT_FLAG_REGISTERED)
 703                 return 0;
 704
 705         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 706         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 707                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 708
 709         /* PFs and trusted VFs should indicate the support of the
 710          * Master capability on non Stingray platform
 711          */
 712         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 713                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 714
 715         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 716         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 717                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 718         req.ver_maj = RTE_VER_YEAR;
 719         req.ver_min = RTE_VER_MONTH;
 720         req.ver_upd = RTE_VER_MINOR;
 721
 722         if (BNXT_PF(bp)) {
 723                 req.enables |= rte_cpu_to_le_32(
 724                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 725                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 726                        RTE_MIN(sizeof(req.vf_req_fwd),
 727                                sizeof(bp->pf.vf_req_fwd)));
 728
 729                 /*
 730                  * PF can sniff HWRM API issued by VF. This can be set up by
 731                  * linux driver and inherited by the DPDK PF driver. Clear
 732                  * this HWRM sniffer list in FW because DPDK PF driver does
 733                  * not support this.
 734                  */
 735                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 736         }
 737
 738         req.flags = rte_cpu_to_le_32(flags);
 739
 740         req.async_event_fwd[0] |=
 741                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 742                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 743                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 744                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 745         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 746                 req.async_event_fwd[0] |=
 747                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 748         req.async_event_fwd[1] |=
 749                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 750                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 751
 752         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 753
 754         HWRM_CHECK_RESULT();
 755
 756         flags = rte_le_to_cpu_32(resp->flags);
 757         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 758                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 759
 760         HWRM_UNLOCK();
 761
 762         bp->flags |= BNXT_FLAG_REGISTERED;
 763
 764         return rc;
 765 }
 766
 767 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 768 {
 769         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 770                 return 0;
 771
 772         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 773 }
 774
 775 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 776 {
 777         int rc;
 778         uint32_t flags = 0;
 779         uint32_t enables;
 780         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 781         struct hwrm_func_vf_cfg_input req = {0};
 782
 783         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 784
 785         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 786                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 787                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 788                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 789                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 790
 791         if (BNXT_HAS_RING_GRPS(bp)) {
 792                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 793                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 794         }
 795
 796         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 797         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 798                                             AGG_RING_MULTIPLIER);
 799         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 800                                              bp->tx_nr_rings +
 801                                              BNXT_NUM_ASYNC_CPR(bp));
 802         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 803                                               bp->tx_nr_rings +
 804                                               BNXT_NUM_ASYNC_CPR(bp));
 805         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 806         if (bp->vf_resv_strategy ==
 807             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 808                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 809                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 810                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 811                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 812                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 813                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 814         }
 815
 816         if (test)
 817                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 818                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 819                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 820                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 821                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 822                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 823
 824         if (test && BNXT_HAS_RING_GRPS(bp))
 825                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 826
 827         req.flags = rte_cpu_to_le_32(flags);
 828         req.enables |= rte_cpu_to_le_32(enables);
 829
 830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 831
 832         if (test)
 833                 HWRM_CHECK_RESULT_SILENT();
 834         else
 835                 HWRM_CHECK_RESULT();
 836
 837         HWRM_UNLOCK();
 838         return rc;
 839 }
 840
 841 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 842 {
 843         int rc;
 844         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 845         struct hwrm_func_resource_qcaps_input req = {0};
 846
 847         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 848         req.fid = rte_cpu_to_le_16(0xffff);
 849
 850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 851
 852         HWRM_CHECK_RESULT();
 853
 854         if (BNXT_VF(bp)) {
 855                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 856                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 857                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 858                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 859                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 860                 /* func_resource_qcaps does not return max_rx_em_flows.
 861                  * So use the value provided by func_qcaps.
 862                  */
 863                 bp->max_l2_ctx =
 864                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 865                         bp->max_rx_em_flows;
 866                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 867                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 868         }
 869         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 870         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 871         if (bp->vf_resv_strategy >
 872             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 873                 bp->vf_resv_strategy =
 874                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 875
 876         HWRM_UNLOCK();
 877         return rc;
 878 }
 879
 880 int bnxt_hwrm_ver_get(struct bnxt *bp)
 881 {
 882         int rc = 0;
 883         struct hwrm_ver_get_input req = {.req_type = 0 };
 884         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 885         uint32_t fw_version;
 886         uint16_t max_resp_len;
 887         char type[RTE_MEMZONE_NAMESIZE];
 888         uint32_t dev_caps_cfg;
 889
 890         bp->max_req_len = HWRM_MAX_REQ_LEN;
 891         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 892
 893         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 894         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 895         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 896
 897         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 898
 899         if (bp->flags & BNXT_FLAG_FW_RESET)
 900                 HWRM_CHECK_RESULT_SILENT();
 901         else
 902                 HWRM_CHECK_RESULT();
 903
 904         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 905                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 906                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 907                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 908         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 909                      (resp->hwrm_fw_min_8b << 16) |
 910                      (resp->hwrm_fw_bld_8b << 8) |
 911                      resp->hwrm_fw_rsvd_8b;
 912         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 913                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 914
 915         fw_version = resp->hwrm_intf_maj_8b << 16;
 916         fw_version |= resp->hwrm_intf_min_8b << 8;
 917         fw_version |= resp->hwrm_intf_upd_8b;
 918         bp->hwrm_spec_code = fw_version;
 919
 920         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 921                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 922                 rc = -EINVAL;
 923                 goto error;
 924         }
 925
 926         if (bp->max_req_len > resp->max_req_win_len) {
 927                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 928                 rc = -EINVAL;
 929         }
 930         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 931         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 932         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 933                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 934
 935         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 936         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 937
 938         if (bp->max_resp_len != max_resp_len) {
 939                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 940                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 941                         bp->pdev->addr.devid, bp->pdev->addr.function);
 942
 943                 rte_free(bp->hwrm_cmd_resp_addr);
 944
 945                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 946                 if (bp->hwrm_cmd_resp_addr == NULL) {
 947                         rc = -ENOMEM;
 948                         goto error;
 949                 }
 950                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 951                 bp->hwrm_cmd_resp_dma_addr =
 952                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 953                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 954                         PMD_DRV_LOG(ERR,
 955                         "Unable to map response buffer to physical memory.\n");
 956                         rc = -ENOMEM;
 957                         goto error;
 958                 }
 959                 bp->max_resp_len = max_resp_len;
 960         }
 961
 962         if ((dev_caps_cfg &
 963                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 964             (dev_caps_cfg &
 965              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 966                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 967                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 968         }
 969
 970         if (((dev_caps_cfg &
 971               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 972              (dev_caps_cfg &
 973               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 974             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 975                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 976                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 977                         bp->pdev->addr.devid, bp->pdev->addr.function);
 978
 979                 rte_free(bp->hwrm_short_cmd_req_addr);
 980
 981                 bp->hwrm_short_cmd_req_addr =
 982                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 983                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 984                         rc = -ENOMEM;
 985                         goto error;
 986                 }
 987                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 988                 bp->hwrm_short_cmd_req_dma_addr =
 989                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 990                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 991                         rte_free(bp->hwrm_short_cmd_req_addr);
 992                         PMD_DRV_LOG(ERR,
 993                                 "Unable to map buffer to physical memory.\n");
 994                         rc = -ENOMEM;
 995                         goto error;
 996                 }
 997         }
 998         if (dev_caps_cfg &
 999             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1000                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1001                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1002         }
1003         if (dev_caps_cfg &
1004             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1005                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1006
1007 error:
1008         HWRM_UNLOCK();
1009         return rc;
1010 }
1011
1012 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1013 {
1014         int rc;
1015         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1016         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1017
1018         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1019                 return 0;
1020
1021         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1022         req.flags = flags;
1023
1024         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1025
1026         HWRM_CHECK_RESULT();
1027         HWRM_UNLOCK();
1028
1029         return rc;
1030 }
1031
1032 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1033 {
1034         int rc = 0;
1035         struct hwrm_port_phy_cfg_input req = {0};
1036         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1037         uint32_t enables = 0;
1038
1039         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1040
1041         if (conf->link_up) {
1042                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1043                 if (bp->link_info.auto_mode && conf->link_speed) {
1044                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1045                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1046                 }
1047
1048                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1049                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1050                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1051                 /*
1052                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1053                  * any auto mode, even "none".
1054                  */
1055                 if (!conf->link_speed) {
1056                         /* No speeds specified. Enable AutoNeg - all speeds */
1057                         req.auto_mode =
1058                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1059                 }
1060                 /* AutoNeg - Advertise speeds specified. */
1061                 if (conf->auto_link_speed_mask &&
1062                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1063                         req.auto_mode =
1064                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1065                         req.auto_link_speed_mask =
1066                                 conf->auto_link_speed_mask;
1067                         enables |=
1068                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1069                 }
1070
1071                 req.auto_duplex = conf->duplex;
1072                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1073                 req.auto_pause = conf->auto_pause;
1074                 req.force_pause = conf->force_pause;
1075                 /* Set force_pause if there is no auto or if there is a force */
1076                 if (req.auto_pause && !req.force_pause)
1077                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1078                 else
1079                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1080
1081                 req.enables = rte_cpu_to_le_32(enables);
1082         } else {
1083                 req.flags =
1084                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1085                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1086         }
1087
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1089
1090         HWRM_CHECK_RESULT();
1091         HWRM_UNLOCK();
1092
1093         return rc;
1094 }
1095
1096 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1097                                    struct bnxt_link_info *link_info)
1098 {
1099         int rc = 0;
1100         struct hwrm_port_phy_qcfg_input req = {0};
1101         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1102
1103         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1104
1105         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1106
1107         HWRM_CHECK_RESULT();
1108
1109         link_info->phy_link_status = resp->link;
1110         link_info->link_up =
1111                 (link_info->phy_link_status ==
1112                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1113         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1114         link_info->duplex = resp->duplex_cfg;
1115         link_info->pause = resp->pause;
1116         link_info->auto_pause = resp->auto_pause;
1117         link_info->force_pause = resp->force_pause;
1118         link_info->auto_mode = resp->auto_mode;
1119         link_info->phy_type = resp->phy_type;
1120         link_info->media_type = resp->media_type;
1121
1122         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1123         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1124         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1125         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1126         link_info->phy_ver[0] = resp->phy_maj;
1127         link_info->phy_ver[1] = resp->phy_min;
1128         link_info->phy_ver[2] = resp->phy_bld;
1129
1130         HWRM_UNLOCK();
1131
1132         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1133         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1134         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1135         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1136         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1137                     link_info->auto_link_speed_mask);
1138         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1139                     link_info->force_link_speed);
1140
1141         return rc;
1142 }
1143
1144 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1145 {
1146         int rc = 0;
1147         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1148         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1149         int i;
1150
1151         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1152
1153         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1154         /* HWRM Version >= 1.9.1 */
1155         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1156                 req.drv_qmap_cap =
1157                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1158         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1159
1160         HWRM_CHECK_RESULT();
1161
1162 #define GET_QUEUE_INFO(x) \
1163         bp->cos_queue[x].id = resp->queue_id##x; \
1164         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1165
1166         GET_QUEUE_INFO(0);
1167         GET_QUEUE_INFO(1);
1168         GET_QUEUE_INFO(2);
1169         GET_QUEUE_INFO(3);
1170         GET_QUEUE_INFO(4);
1171         GET_QUEUE_INFO(5);
1172         GET_QUEUE_INFO(6);
1173         GET_QUEUE_INFO(7);
1174
1175         HWRM_UNLOCK();
1176
1177         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1178                 bp->tx_cosq_id = bp->cos_queue[0].id;
1179         } else {
1180                 /* iterate and find the COSq profile to use for Tx */
1181                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1182                         if (bp->cos_queue[i].profile ==
1183                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1184                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1185                                 break;
1186                         }
1187                 }
1188         }
1189
1190         bp->max_tc = resp->max_configurable_queues;
1191         bp->max_lltc = resp->max_configurable_lossless_queues;
1192         if (bp->max_tc > BNXT_MAX_QUEUE)
1193                 bp->max_tc = BNXT_MAX_QUEUE;
1194         bp->max_q = bp->max_tc;
1195
1196         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1197
1198         return rc;
1199 }
1200
1201 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1202                          struct bnxt_ring *ring,
1203                          uint32_t ring_type, uint32_t map_index,
1204                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1205 {
1206         int rc = 0;
1207         uint32_t enables = 0;
1208         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1209         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1210         struct rte_mempool *mb_pool;
1211         uint16_t rx_buf_size;
1212
1213         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1214
1215         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1216         req.fbo = rte_cpu_to_le_32(0);
1217         /* Association of ring index with doorbell index */
1218         req.logical_id = rte_cpu_to_le_16(map_index);
1219         req.length = rte_cpu_to_le_32(ring->ring_size);
1220
1221         switch (ring_type) {
1222         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1223                 req.ring_type = ring_type;
1224                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1225                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1226                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1227                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1228                         enables |=
1229                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1230                 break;
1231         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1232                 req.ring_type = ring_type;
1233                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1234                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1235                 if (BNXT_CHIP_THOR(bp)) {
1236                         mb_pool = bp->rx_queues[0]->mb_pool;
1237                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1238                                       RTE_PKTMBUF_HEADROOM;
1239                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1240                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1241                         enables |=
1242                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1243                 }
1244                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1245                         enables |=
1246                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1247                 break;
1248         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1249                 req.ring_type = ring_type;
1250                 if (BNXT_HAS_NQ(bp)) {
1251                         /* Association of cp ring with nq */
1252                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1253                         enables |=
1254                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1255                 }
1256                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1257                 break;
1258         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1259                 req.ring_type = ring_type;
1260                 req.page_size = BNXT_PAGE_SHFT;
1261                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1262                 break;
1263         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1264                 req.ring_type = ring_type;
1265                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1266
1267                 mb_pool = bp->rx_queues[0]->mb_pool;
1268                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1269                               RTE_PKTMBUF_HEADROOM;
1270                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1271                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1272
1273                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1274                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1275                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1276                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1277                 break;
1278         default:
1279                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1280                         ring_type);
1281                 HWRM_UNLOCK();
1282                 return -EINVAL;
1283         }
1284         req.enables = rte_cpu_to_le_32(enables);
1285
1286         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1287
1288         if (rc || resp->error_code) {
1289                 if (rc == 0 && resp->error_code)
1290                         rc = rte_le_to_cpu_16(resp->error_code);
1291                 switch (ring_type) {
1292                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1293                         PMD_DRV_LOG(ERR,
1294                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1295                         HWRM_UNLOCK();
1296                         return rc;
1297                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1298                         PMD_DRV_LOG(ERR,
1299                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1300                         HWRM_UNLOCK();
1301                         return rc;
1302                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1303                         PMD_DRV_LOG(ERR,
1304                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1305                                     rc);
1306                         HWRM_UNLOCK();
1307                         return rc;
1308                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1309                         PMD_DRV_LOG(ERR,
1310                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1311                         HWRM_UNLOCK();
1312                         return rc;
1313                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1314                         PMD_DRV_LOG(ERR,
1315                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1316                         HWRM_UNLOCK();
1317                         return rc;
1318                 default:
1319                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1320                         HWRM_UNLOCK();
1321                         return rc;
1322                 }
1323         }
1324
1325         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1326         HWRM_UNLOCK();
1327         return rc;
1328 }
1329
1330 int bnxt_hwrm_ring_free(struct bnxt *bp,
1331                         struct bnxt_ring *ring, uint32_t ring_type)
1332 {
1333         int rc;
1334         struct hwrm_ring_free_input req = {.req_type = 0 };
1335         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1336
1337         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1338
1339         req.ring_type = ring_type;
1340         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1341
1342         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1343
1344         if (rc || resp->error_code) {
1345                 if (rc == 0 && resp->error_code)
1346                         rc = rte_le_to_cpu_16(resp->error_code);
1347                 HWRM_UNLOCK();
1348
1349                 switch (ring_type) {
1350                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1351                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1352                                 rc);
1353                         return rc;
1354                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1355                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1356                                 rc);
1357                         return rc;
1358                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1359                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1360                                 rc);
1361                         return rc;
1362                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1363                         PMD_DRV_LOG(ERR,
1364                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1365                         return rc;
1366                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1367                         PMD_DRV_LOG(ERR,
1368                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1369                         return rc;
1370                 default:
1371                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1372                         return rc;
1373                 }
1374         }
1375         HWRM_UNLOCK();
1376         return 0;
1377 }
1378
1379 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1380 {
1381         int rc = 0;
1382         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1383         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1384
1385         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1386
1387         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1388         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1389         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1390         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1391
1392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1393
1394         HWRM_CHECK_RESULT();
1395
1396         bp->grp_info[idx].fw_grp_id =
1397             rte_le_to_cpu_16(resp->ring_group_id);
1398
1399         HWRM_UNLOCK();
1400
1401         return rc;
1402 }
1403
1404 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1405 {
1406         int rc;
1407         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1408         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1409
1410         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1411
1412         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1413
1414         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1415
1416         HWRM_CHECK_RESULT();
1417         HWRM_UNLOCK();
1418
1419         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1420         return rc;
1421 }
1422
1423 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1424 {
1425         int rc = 0;
1426         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1427         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1428
1429         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1430                 return rc;
1431
1432         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1433
1434         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1435
1436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1437
1438         HWRM_CHECK_RESULT();
1439         HWRM_UNLOCK();
1440
1441         return rc;
1442 }
1443
1444 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1445                                 unsigned int idx __rte_unused)
1446 {
1447         int rc;
1448         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1449         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1450
1451         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1452
1453         req.update_period_ms = rte_cpu_to_le_32(0);
1454
1455         req.stats_dma_addr =
1456             rte_cpu_to_le_64(cpr->hw_stats_map);
1457
1458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1459
1460         HWRM_CHECK_RESULT();
1461
1462         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1463
1464         HWRM_UNLOCK();
1465
1466         return rc;
1467 }
1468
1469 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1470                                 unsigned int idx __rte_unused)
1471 {
1472         int rc;
1473         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1474         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1475
1476         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1477
1478         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1479
1480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1481
1482         HWRM_CHECK_RESULT();
1483         HWRM_UNLOCK();
1484
1485         return rc;
1486 }
1487
1488 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1489 {
1490         int rc = 0, i, j;
1491         struct hwrm_vnic_alloc_input req = { 0 };
1492         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1493
1494         if (!BNXT_HAS_RING_GRPS(bp))
1495                 goto skip_ring_grps;
1496
1497         /* map ring groups to this vnic */
1498         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1499                 vnic->start_grp_id, vnic->end_grp_id);
1500         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1501                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1502
1503         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1504         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1505         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1506         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1507
1508 skip_ring_grps:
1509         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1510                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1511         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1512
1513         if (vnic->func_default)
1514                 req.flags =
1515                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1517
1518         HWRM_CHECK_RESULT();
1519
1520         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1521         HWRM_UNLOCK();
1522         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1523         return rc;
1524 }
1525
1526 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1527                                         struct bnxt_vnic_info *vnic,
1528                                         struct bnxt_plcmodes_cfg *pmode)
1529 {
1530         int rc = 0;
1531         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1532         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1533
1534         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1535
1536         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1537
1538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1539
1540         HWRM_CHECK_RESULT();
1541
1542         pmode->flags = rte_le_to_cpu_32(resp->flags);
1543         /* dflt_vnic bit doesn't exist in the _cfg command */
1544         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1545         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1546         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1547         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1548
1549         HWRM_UNLOCK();
1550
1551         return rc;
1552 }
1553
1554 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1555                                        struct bnxt_vnic_info *vnic,
1556                                        struct bnxt_plcmodes_cfg *pmode)
1557 {
1558         int rc = 0;
1559         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1560         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1561
1562         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1563                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1564                 return rc;
1565         }
1566
1567         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1568
1569         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1570         req.flags = rte_cpu_to_le_32(pmode->flags);
1571         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1572         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1573         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1574         req.enables = rte_cpu_to_le_32(
1575             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1576             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1577             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1578         );
1579
1580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1581
1582         HWRM_CHECK_RESULT();
1583         HWRM_UNLOCK();
1584
1585         return rc;
1586 }
1587
1588 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1589 {
1590         int rc = 0;
1591         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1592         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1593         struct bnxt_plcmodes_cfg pmodes = { 0 };
1594         uint32_t ctx_enable_flag = 0;
1595         uint32_t enables = 0;
1596
1597         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1598                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1599                 return rc;
1600         }
1601
1602         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1603         if (rc)
1604                 return rc;
1605
1606         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1607
1608         if (BNXT_CHIP_THOR(bp)) {
1609                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1610                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1611                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1612
1613                 req.default_rx_ring_id =
1614                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1615                 req.default_cmpl_ring_id =
1616                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1617                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1618                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1619                 goto config_mru;
1620         }
1621
1622         /* Only RSS support for now TBD: COS & LB */
1623         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1624         if (vnic->lb_rule != 0xffff)
1625                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1626         if (vnic->cos_rule != 0xffff)
1627                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1628         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1629                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1630                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1631         }
1632         enables |= ctx_enable_flag;
1633         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1634         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1635         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1636         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1637
1638 config_mru:
1639         req.enables = rte_cpu_to_le_32(enables);
1640         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1641         req.mru = rte_cpu_to_le_16(vnic->mru);
1642         /* Configure default VNIC only once. */
1643         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1644                 req.flags |=
1645                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1646                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1647         }
1648         if (vnic->vlan_strip)
1649                 req.flags |=
1650                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1651         if (vnic->bd_stall)
1652                 req.flags |=
1653                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1654         if (vnic->roce_dual)
1655                 req.flags |= rte_cpu_to_le_32(
1656                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1657         if (vnic->roce_only)
1658                 req.flags |= rte_cpu_to_le_32(
1659                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1660         if (vnic->rss_dflt_cr)
1661                 req.flags |= rte_cpu_to_le_32(
1662                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1663
1664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1665
1666         HWRM_CHECK_RESULT();
1667         HWRM_UNLOCK();
1668
1669         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1670
1671         return rc;
1672 }
1673
1674 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1675                 int16_t fw_vf_id)
1676 {
1677         int rc = 0;
1678         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1679         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1680
1681         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1682                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1683                 return rc;
1684         }
1685         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1686
1687         req.enables =
1688                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1689         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1690         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1691
1692         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1693
1694         HWRM_CHECK_RESULT();
1695
1696         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1697         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1698         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1699         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1700         vnic->mru = rte_le_to_cpu_16(resp->mru);
1701         vnic->func_default = rte_le_to_cpu_32(
1702                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1703         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1704                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1705         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1706                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1707         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1708                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1709         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1710                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1711         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1712                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1713
1714         HWRM_UNLOCK();
1715
1716         return rc;
1717 }
1718
1719 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1720                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1721 {
1722         int rc = 0;
1723         uint16_t ctx_id;
1724         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1725         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1726                                                 bp->hwrm_cmd_resp_addr;
1727
1728         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1729
1730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1731         HWRM_CHECK_RESULT();
1732
1733         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1734         if (!BNXT_HAS_RING_GRPS(bp))
1735                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1736         else if (ctx_idx == 0)
1737                 vnic->rss_rule = ctx_id;
1738
1739         HWRM_UNLOCK();
1740
1741         return rc;
1742 }
1743
1744 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1745                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1746 {
1747         int rc = 0;
1748         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1749         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1750                                                 bp->hwrm_cmd_resp_addr;
1751
1752         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1753                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1754                 return rc;
1755         }
1756         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1757
1758         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1759
1760         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761
1762         HWRM_CHECK_RESULT();
1763         HWRM_UNLOCK();
1764
1765         return rc;
1766 }
1767
1768 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1769 {
1770         int rc = 0;
1771         struct hwrm_vnic_free_input req = {.req_type = 0 };
1772         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1773
1774         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1775                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1776                 return rc;
1777         }
1778
1779         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1780
1781         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1782
1783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1784
1785         HWRM_CHECK_RESULT();
1786         HWRM_UNLOCK();
1787
1788         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1789         /* Configure default VNIC again if necessary. */
1790         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1791                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1792
1793         return rc;
1794 }
1795
1796 static int
1797 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1798 {
1799         int i;
1800         int rc = 0;
1801         int nr_ctxs = vnic->num_lb_ctxts;
1802         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1803         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1804
1805         for (i = 0; i < nr_ctxs; i++) {
1806                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1807
1808                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1809                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1810                 req.hash_mode_flags = vnic->hash_mode;
1811
1812                 req.hash_key_tbl_addr =
1813                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1814
1815                 req.ring_grp_tbl_addr =
1816                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1817                                          i * HW_HASH_INDEX_SIZE);
1818                 req.ring_table_pair_index = i;
1819                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1820
1821                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1822                                             BNXT_USE_CHIMP_MB);
1823
1824                 HWRM_CHECK_RESULT();
1825                 HWRM_UNLOCK();
1826         }
1827
1828         return rc;
1829 }
1830
1831 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1832                            struct bnxt_vnic_info *vnic)
1833 {
1834         int rc = 0;
1835         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1836         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1837
1838         if (!vnic->rss_table)
1839                 return 0;
1840
1841         if (BNXT_CHIP_THOR(bp))
1842                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1843
1844         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1845
1846         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1847         req.hash_mode_flags = vnic->hash_mode;
1848
1849         req.ring_grp_tbl_addr =
1850             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1851         req.hash_key_tbl_addr =
1852             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1853         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1854         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1855
1856         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1857
1858         HWRM_CHECK_RESULT();
1859         HWRM_UNLOCK();
1860
1861         return rc;
1862 }
1863
1864 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1865                         struct bnxt_vnic_info *vnic)
1866 {
1867         int rc = 0;
1868         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1869         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1870         uint16_t size;
1871
1872         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1873                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1874                 return rc;
1875         }
1876
1877         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1878
1879         req.flags = rte_cpu_to_le_32(
1880                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1881
1882         req.enables = rte_cpu_to_le_32(
1883                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1884
1885         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1886         size -= RTE_PKTMBUF_HEADROOM;
1887         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1888
1889         req.jumbo_thresh = rte_cpu_to_le_16(size);
1890         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1891
1892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1893
1894         HWRM_CHECK_RESULT();
1895         HWRM_UNLOCK();
1896
1897         return rc;
1898 }
1899
1900 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1901                         struct bnxt_vnic_info *vnic, bool enable)
1902 {
1903         int rc = 0;
1904         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1905         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1906
1907         if (BNXT_CHIP_THOR(bp))
1908                 return 0;
1909
1910         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1911
1912         if (enable) {
1913                 req.enables = rte_cpu_to_le_32(
1914                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1915                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1916                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1917                 req.flags = rte_cpu_to_le_32(
1918                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1919                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1920                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1921                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1922                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1923                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1924                 req.max_agg_segs = rte_cpu_to_le_16(5);
1925                 req.max_aggs =
1926                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1927                 req.min_agg_len = rte_cpu_to_le_32(512);
1928         }
1929         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1930
1931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1932
1933         HWRM_CHECK_RESULT();
1934         HWRM_UNLOCK();
1935
1936         return rc;
1937 }
1938
1939 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1940 {
1941         struct hwrm_func_cfg_input req = {0};
1942         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1943         int rc;
1944
1945         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1946         req.enables = rte_cpu_to_le_32(
1947                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1948         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1949         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1950
1951         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1952
1953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1954         HWRM_CHECK_RESULT();
1955         HWRM_UNLOCK();
1956
1957         bp->pf.vf_info[vf].random_mac = false;
1958
1959         return rc;
1960 }
1961
1962 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1963                                   uint64_t *dropped)
1964 {
1965         int rc = 0;
1966         struct hwrm_func_qstats_input req = {.req_type = 0};
1967         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1968
1969         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1970
1971         req.fid = rte_cpu_to_le_16(fid);
1972
1973         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1974
1975         HWRM_CHECK_RESULT();
1976
1977         if (dropped)
1978                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1979
1980         HWRM_UNLOCK();
1981
1982         return rc;
1983 }
1984
1985 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1986                           struct rte_eth_stats *stats)
1987 {
1988         int rc = 0;
1989         struct hwrm_func_qstats_input req = {.req_type = 0};
1990         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1991
1992         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1993
1994         req.fid = rte_cpu_to_le_16(fid);
1995
1996         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1997
1998         HWRM_CHECK_RESULT();
1999
2000         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2001         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2002         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2003         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2004         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2005         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2006
2007         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2008         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2009         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2010         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2011         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2012         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2013
2014         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2015         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2016         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2017
2018         HWRM_UNLOCK();
2019
2020         return rc;
2021 }
2022
2023 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2024 {
2025         int rc = 0;
2026         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2027         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2028
2029         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2030
2031         req.fid = rte_cpu_to_le_16(fid);
2032
2033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2034
2035         HWRM_CHECK_RESULT();
2036         HWRM_UNLOCK();
2037
2038         return rc;
2039 }
2040
2041 /*
2042  * HWRM utility functions
2043  */
2044
2045 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2046 {
2047         unsigned int i;
2048         int rc = 0;
2049
2050         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2051                 struct bnxt_tx_queue *txq;
2052                 struct bnxt_rx_queue *rxq;
2053                 struct bnxt_cp_ring_info *cpr;
2054
2055                 if (i >= bp->rx_cp_nr_rings) {
2056                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2057                         cpr = txq->cp_ring;
2058                 } else {
2059                         rxq = bp->rx_queues[i];
2060                         cpr = rxq->cp_ring;
2061                 }
2062
2063                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2064                 if (rc)
2065                         return rc;
2066         }
2067         return 0;
2068 }
2069
2070 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2071 {
2072         int rc;
2073         unsigned int i;
2074         struct bnxt_cp_ring_info *cpr;
2075
2076         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2077
2078                 if (i >= bp->rx_cp_nr_rings) {
2079                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2080                 } else {
2081                         cpr = bp->rx_queues[i]->cp_ring;
2082                         if (BNXT_HAS_RING_GRPS(bp))
2083                                 bp->grp_info[i].fw_stats_ctx = -1;
2084                 }
2085                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2086                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2087                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2088                         if (rc)
2089                                 return rc;
2090                 }
2091         }
2092         return 0;
2093 }
2094
2095 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2096 {
2097         unsigned int i;
2098         int rc = 0;
2099
2100         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2101                 struct bnxt_tx_queue *txq;
2102                 struct bnxt_rx_queue *rxq;
2103                 struct bnxt_cp_ring_info *cpr;
2104
2105                 if (i >= bp->rx_cp_nr_rings) {
2106                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2107                         cpr = txq->cp_ring;
2108                 } else {
2109                         rxq = bp->rx_queues[i];
2110                         cpr = rxq->cp_ring;
2111                 }
2112
2113                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2114
2115                 if (rc)
2116                         return rc;
2117         }
2118         return rc;
2119 }
2120
2121 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2122 {
2123         uint16_t idx;
2124         uint32_t rc = 0;
2125
2126         if (!BNXT_HAS_RING_GRPS(bp))
2127                 return 0;
2128
2129         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2130
2131                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2132                         continue;
2133
2134                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2135
2136                 if (rc)
2137                         return rc;
2138         }
2139         return rc;
2140 }
2141
2142 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2143 {
2144         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2145
2146         bnxt_hwrm_ring_free(bp, cp_ring,
2147                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2148         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2149         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2150                                      sizeof(*cpr->cp_desc_ring));
2151         cpr->cp_raw_cons = 0;
2152         cpr->valid = 0;
2153 }
2154
2155 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2156 {
2157         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2158
2159         bnxt_hwrm_ring_free(bp, cp_ring,
2160                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2161         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2162         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2163                         sizeof(*cpr->cp_desc_ring));
2164         cpr->cp_raw_cons = 0;
2165         cpr->valid = 0;
2166 }
2167
2168 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2169 {
2170         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2171         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2172         struct bnxt_ring *ring = rxr->rx_ring_struct;
2173         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2174
2175         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2176                 bnxt_hwrm_ring_free(bp, ring,
2177                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2178                 ring->fw_ring_id = INVALID_HW_RING_ID;
2179                 if (BNXT_HAS_RING_GRPS(bp))
2180                         bp->grp_info[queue_index].rx_fw_ring_id =
2181                                                         INVALID_HW_RING_ID;
2182                 memset(rxr->rx_desc_ring, 0,
2183                        rxr->rx_ring_struct->ring_size *
2184                        sizeof(*rxr->rx_desc_ring));
2185                 memset(rxr->rx_buf_ring, 0,
2186                        rxr->rx_ring_struct->ring_size *
2187                        sizeof(*rxr->rx_buf_ring));
2188                 rxr->rx_prod = 0;
2189         }
2190         ring = rxr->ag_ring_struct;
2191         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2192                 bnxt_hwrm_ring_free(bp, ring,
2193                                     BNXT_CHIP_THOR(bp) ?
2194                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2195                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2196                 ring->fw_ring_id = INVALID_HW_RING_ID;
2197                 memset(rxr->ag_buf_ring, 0,
2198                        rxr->ag_ring_struct->ring_size *
2199                        sizeof(*rxr->ag_buf_ring));
2200                 rxr->ag_prod = 0;
2201                 if (BNXT_HAS_RING_GRPS(bp))
2202                         bp->grp_info[queue_index].ag_fw_ring_id =
2203                                                         INVALID_HW_RING_ID;
2204         }
2205         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2206                 bnxt_free_cp_ring(bp, cpr);
2207                 if (rxq->nq_ring)
2208                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2209         }
2210
2211         if (BNXT_HAS_RING_GRPS(bp))
2212                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2213 }
2214
2215 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2216 {
2217         unsigned int i;
2218
2219         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2220                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2221                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2222                 struct bnxt_ring *ring = txr->tx_ring_struct;
2223                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2224
2225                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2226                         bnxt_hwrm_ring_free(bp, ring,
2227                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2228                         ring->fw_ring_id = INVALID_HW_RING_ID;
2229                         memset(txr->tx_desc_ring, 0,
2230                                         txr->tx_ring_struct->ring_size *
2231                                         sizeof(*txr->tx_desc_ring));
2232                         memset(txr->tx_buf_ring, 0,
2233                                         txr->tx_ring_struct->ring_size *
2234                                         sizeof(*txr->tx_buf_ring));
2235                         txr->tx_prod = 0;
2236                         txr->tx_cons = 0;
2237                 }
2238                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2239                         bnxt_free_cp_ring(bp, cpr);
2240                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2241                         if (txq->nq_ring)
2242                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2243                 }
2244         }
2245
2246         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2247                 bnxt_free_hwrm_rx_ring(bp, i);
2248
2249         return 0;
2250 }
2251
2252 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2253 {
2254         uint16_t i;
2255         uint32_t rc = 0;
2256
2257         if (!BNXT_HAS_RING_GRPS(bp))
2258                 return 0;
2259
2260         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2261                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2262                 if (rc)
2263                         return rc;
2264         }
2265         return rc;
2266 }
2267
2268 void bnxt_free_hwrm_resources(struct bnxt *bp)
2269 {
2270         /* Release memzone */
2271         rte_free(bp->hwrm_cmd_resp_addr);
2272         rte_free(bp->hwrm_short_cmd_req_addr);
2273         bp->hwrm_cmd_resp_addr = NULL;
2274         bp->hwrm_short_cmd_req_addr = NULL;
2275         bp->hwrm_cmd_resp_dma_addr = 0;
2276         bp->hwrm_short_cmd_req_dma_addr = 0;
2277 }
2278
2279 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2280 {
2281         struct rte_pci_device *pdev = bp->pdev;
2282         char type[RTE_MEMZONE_NAMESIZE];
2283
2284         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2285                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2286         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2287         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2288         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2289         if (bp->hwrm_cmd_resp_addr == NULL)
2290                 return -ENOMEM;
2291         bp->hwrm_cmd_resp_dma_addr =
2292                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2293         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2294                 PMD_DRV_LOG(ERR,
2295                         "unable to map response address to physical memory\n");
2296                 return -ENOMEM;
2297         }
2298         rte_spinlock_init(&bp->hwrm_lock);
2299
2300         return 0;
2301 }
2302
2303 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2304 {
2305         struct bnxt_filter_info *filter;
2306         int rc = 0;
2307
2308         STAILQ_FOREACH(filter, &vnic->filter, next) {
2309                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2310                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2311                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2312                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2313                 else
2314                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2315                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2316                 //if (rc)
2317                         //break;
2318         }
2319         return rc;
2320 }
2321
2322 static int
2323 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2324 {
2325         struct bnxt_filter_info *filter;
2326         struct rte_flow *flow;
2327         int rc = 0;
2328
2329         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2330                 filter = flow->filter;
2331                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2332                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2333                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2334                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2335                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2336                 else
2337                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2338
2339                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2340                 rte_free(flow);
2341                 //if (rc)
2342                         //break;
2343         }
2344         return rc;
2345 }
2346
2347 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2348 {
2349         struct bnxt_filter_info *filter;
2350         int rc = 0;
2351
2352         STAILQ_FOREACH(filter, &vnic->filter, next) {
2353                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2354                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2355                                                      filter);
2356                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2357                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2358                                                          filter);
2359                 else
2360                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2361                                                      filter);
2362                 if (rc)
2363                         break;
2364         }
2365         return rc;
2366 }
2367
2368 void bnxt_free_tunnel_ports(struct bnxt *bp)
2369 {
2370         if (bp->vxlan_port_cnt)
2371                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2372                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2373         bp->vxlan_port = 0;
2374         if (bp->geneve_port_cnt)
2375                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2376                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2377         bp->geneve_port = 0;
2378 }
2379
2380 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2381 {
2382         int i, j;
2383
2384         if (bp->vnic_info == NULL)
2385                 return;
2386
2387         /*
2388          * Cleanup VNICs in reverse order, to make sure the L2 filter
2389          * from vnic0 is last to be cleaned up.
2390          */
2391         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2392                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2393
2394                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2395                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2396                         return;
2397                 }
2398
2399                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2400
2401                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2402
2403                 if (BNXT_CHIP_THOR(bp)) {
2404                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2405                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2406                                                         vnic->fw_grp_ids[j]);
2407                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2408                         }
2409                         vnic->num_lb_ctxts = 0;
2410                 } else {
2411                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2412                         vnic->rss_rule = INVALID_HW_RING_ID;
2413                 }
2414
2415                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2416
2417                 bnxt_hwrm_vnic_free(bp, vnic);
2418
2419                 rte_free(vnic->fw_grp_ids);
2420         }
2421         /* Ring resources */
2422         bnxt_free_all_hwrm_rings(bp);
2423         bnxt_free_all_hwrm_ring_grps(bp);
2424         bnxt_free_all_hwrm_stat_ctxs(bp);
2425         bnxt_free_tunnel_ports(bp);
2426 }
2427
2428 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2429 {
2430         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2431
2432         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2433                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2434
2435         switch (conf_link_speed) {
2436         case ETH_LINK_SPEED_10M_HD:
2437         case ETH_LINK_SPEED_100M_HD:
2438                 /* FALLTHROUGH */
2439                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2440         }
2441         return hw_link_duplex;
2442 }
2443
2444 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2445 {
2446         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2447 }
2448
2449 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2450 {
2451         uint16_t eth_link_speed = 0;
2452
2453         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2454                 return ETH_LINK_SPEED_AUTONEG;
2455
2456         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2457         case ETH_LINK_SPEED_100M:
2458         case ETH_LINK_SPEED_100M_HD:
2459                 /* FALLTHROUGH */
2460                 eth_link_speed =
2461                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2462                 break;
2463         case ETH_LINK_SPEED_1G:
2464                 eth_link_speed =
2465                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2466                 break;
2467         case ETH_LINK_SPEED_2_5G:
2468                 eth_link_speed =
2469                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2470                 break;
2471         case ETH_LINK_SPEED_10G:
2472                 eth_link_speed =
2473                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2474                 break;
2475         case ETH_LINK_SPEED_20G:
2476                 eth_link_speed =
2477                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2478                 break;
2479         case ETH_LINK_SPEED_25G:
2480                 eth_link_speed =
2481                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2482                 break;
2483         case ETH_LINK_SPEED_40G:
2484                 eth_link_speed =
2485                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2486                 break;
2487         case ETH_LINK_SPEED_50G:
2488                 eth_link_speed =
2489                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2490                 break;
2491         case ETH_LINK_SPEED_100G:
2492                 eth_link_speed =
2493                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2494                 break;
2495         default:
2496                 PMD_DRV_LOG(ERR,
2497                         "Unsupported link speed %d; default to AUTO\n",
2498                         conf_link_speed);
2499                 break;
2500         }
2501         return eth_link_speed;
2502 }
2503
2504 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2505                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2506                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2507                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2508
2509 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2510 {
2511         uint32_t one_speed;
2512
2513         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2514                 return 0;
2515
2516         if (link_speed & ETH_LINK_SPEED_FIXED) {
2517                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2518
2519                 if (one_speed & (one_speed - 1)) {
2520                         PMD_DRV_LOG(ERR,
2521                                 "Invalid advertised speeds (%u) for port %u\n",
2522                                 link_speed, port_id);
2523                         return -EINVAL;
2524                 }
2525                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2526                         PMD_DRV_LOG(ERR,
2527                                 "Unsupported advertised speed (%u) for port %u\n",
2528                                 link_speed, port_id);
2529                         return -EINVAL;
2530                 }
2531         } else {
2532                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2533                         PMD_DRV_LOG(ERR,
2534                                 "Unsupported advertised speeds (%u) for port %u\n",
2535                                 link_speed, port_id);
2536                         return -EINVAL;
2537                 }
2538         }
2539         return 0;
2540 }
2541
2542 static uint16_t
2543 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2544 {
2545         uint16_t ret = 0;
2546
2547         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2548                 if (bp->link_info.support_speeds)
2549                         return bp->link_info.support_speeds;
2550                 link_speed = BNXT_SUPPORTED_SPEEDS;
2551         }
2552
2553         if (link_speed & ETH_LINK_SPEED_100M)
2554                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2555         if (link_speed & ETH_LINK_SPEED_100M_HD)
2556                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2557         if (link_speed & ETH_LINK_SPEED_1G)
2558                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2559         if (link_speed & ETH_LINK_SPEED_2_5G)
2560                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2561         if (link_speed & ETH_LINK_SPEED_10G)
2562                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2563         if (link_speed & ETH_LINK_SPEED_20G)
2564                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2565         if (link_speed & ETH_LINK_SPEED_25G)
2566                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2567         if (link_speed & ETH_LINK_SPEED_40G)
2568                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2569         if (link_speed & ETH_LINK_SPEED_50G)
2570                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2571         if (link_speed & ETH_LINK_SPEED_100G)
2572                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2573         return ret;
2574 }
2575
2576 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2577 {
2578         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2579
2580         switch (hw_link_speed) {
2581         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2582                 eth_link_speed = ETH_SPEED_NUM_100M;
2583                 break;
2584         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2585                 eth_link_speed = ETH_SPEED_NUM_1G;
2586                 break;
2587         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2588                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2589                 break;
2590         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2591                 eth_link_speed = ETH_SPEED_NUM_10G;
2592                 break;
2593         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2594                 eth_link_speed = ETH_SPEED_NUM_20G;
2595                 break;
2596         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2597                 eth_link_speed = ETH_SPEED_NUM_25G;
2598                 break;
2599         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2600                 eth_link_speed = ETH_SPEED_NUM_40G;
2601                 break;
2602         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2603                 eth_link_speed = ETH_SPEED_NUM_50G;
2604                 break;
2605         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2606                 eth_link_speed = ETH_SPEED_NUM_100G;
2607                 break;
2608         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2609         default:
2610                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2611                         hw_link_speed);
2612                 break;
2613         }
2614         return eth_link_speed;
2615 }
2616
2617 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2618 {
2619         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2620
2621         switch (hw_link_duplex) {
2622         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2623         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2624                 /* FALLTHROUGH */
2625                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2626                 break;
2627         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2628                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2629                 break;
2630         default:
2631                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2632                         hw_link_duplex);
2633                 break;
2634         }
2635         return eth_link_duplex;
2636 }
2637
2638 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2639 {
2640         int rc = 0;
2641         struct bnxt_link_info *link_info = &bp->link_info;
2642
2643         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2644         if (rc) {
2645                 PMD_DRV_LOG(ERR,
2646                         "Get link config failed with rc %d\n", rc);
2647                 goto exit;
2648         }
2649         if (link_info->link_speed)
2650                 link->link_speed =
2651                         bnxt_parse_hw_link_speed(link_info->link_speed);
2652         else
2653                 link->link_speed = ETH_SPEED_NUM_NONE;
2654         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2655         link->link_status = link_info->link_up;
2656         link->link_autoneg = link_info->auto_mode ==
2657                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2658                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2659 exit:
2660         return rc;
2661 }
2662
2663 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2664 {
2665         int rc = 0;
2666         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2667         struct bnxt_link_info link_req;
2668         uint16_t speed, autoneg;
2669
2670         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2671                 return 0;
2672
2673         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2674                         bp->eth_dev->data->port_id);
2675         if (rc)
2676                 goto error;
2677
2678         memset(&link_req, 0, sizeof(link_req));
2679         link_req.link_up = link_up;
2680         if (!link_up)
2681                 goto port_phy_cfg;
2682
2683         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2684         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2685         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2686         /* Autoneg can be done only when the FW allows */
2687         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2688                                 bp->link_info.force_link_speed)) {
2689                 link_req.phy_flags |=
2690                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2691                 link_req.auto_link_speed_mask =
2692                         bnxt_parse_eth_link_speed_mask(bp,
2693                                                        dev_conf->link_speeds);
2694         } else {
2695                 if (bp->link_info.phy_type ==
2696                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2697                     bp->link_info.phy_type ==
2698                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2699                     bp->link_info.media_type ==
2700                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2701                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2702                         return -EINVAL;
2703                 }
2704
2705                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2706                 /* If user wants a particular speed try that first. */
2707                 if (speed)
2708                         link_req.link_speed = speed;
2709                 else if (bp->link_info.force_link_speed)
2710                         link_req.link_speed = bp->link_info.force_link_speed;
2711                 else
2712                         link_req.link_speed = bp->link_info.auto_link_speed;
2713         }
2714         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2715         link_req.auto_pause = bp->link_info.auto_pause;
2716         link_req.force_pause = bp->link_info.force_pause;
2717
2718 port_phy_cfg:
2719         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2720         if (rc) {
2721                 PMD_DRV_LOG(ERR,
2722                         "Set link config failed with rc %d\n", rc);
2723         }
2724
2725 error:
2726         return rc;
2727 }
2728
2729 /* JIRA 22088 */
2730 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2731 {
2732         struct hwrm_func_qcfg_input req = {0};
2733         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2734         uint16_t flags;
2735         int rc = 0;
2736
2737         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2738         req.fid = rte_cpu_to_le_16(0xffff);
2739
2740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2741
2742         HWRM_CHECK_RESULT();
2743
2744         /* Hard Coded.. 0xfff VLAN ID mask */
2745         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2746         flags = rte_le_to_cpu_16(resp->flags);
2747         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2748                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2749
2750         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2751                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2752                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2753         } else if (BNXT_VF(bp) &&
2754                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2755                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2756                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2757         }
2758
2759         if (mtu)
2760                 *mtu = resp->mtu;
2761
2762         switch (resp->port_partition_type) {
2763         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2764         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2765         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2766                 /* FALLTHROUGH */
2767                 bp->port_partition_type = resp->port_partition_type;
2768                 break;
2769         default:
2770                 bp->port_partition_type = 0;
2771                 break;
2772         }
2773
2774         HWRM_UNLOCK();
2775
2776         return rc;
2777 }
2778
2779 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2780                                    struct hwrm_func_qcaps_output *qcaps)
2781 {
2782         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2783         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2784                sizeof(qcaps->mac_address));
2785         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2786         qcaps->max_rx_rings = fcfg->num_rx_rings;
2787         qcaps->max_tx_rings = fcfg->num_tx_rings;
2788         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2789         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2790         qcaps->max_vfs = 0;
2791         qcaps->first_vf_id = 0;
2792         qcaps->max_vnics = fcfg->num_vnics;
2793         qcaps->max_decap_records = 0;
2794         qcaps->max_encap_records = 0;
2795         qcaps->max_tx_wm_flows = 0;
2796         qcaps->max_tx_em_flows = 0;
2797         qcaps->max_rx_wm_flows = 0;
2798         qcaps->max_rx_em_flows = 0;
2799         qcaps->max_flow_id = 0;
2800         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2801         qcaps->max_sp_tx_rings = 0;
2802         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2803 }
2804
2805 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2806 {
2807         struct hwrm_func_cfg_input req = {0};
2808         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2809         uint32_t enables;
2810         int rc;
2811
2812         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2813                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2814                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2815                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2816                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2817                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2818                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2819                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2820                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2821
2822         if (BNXT_HAS_RING_GRPS(bp)) {
2823                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2824                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2825         } else if (BNXT_HAS_NQ(bp)) {
2826                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2827                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2828         }
2829
2830         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2831         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2832         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2833                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2834                                    BNXT_NUM_VLANS);
2835         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2836         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2837         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2838         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2839         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2840         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2841         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2842         req.fid = rte_cpu_to_le_16(0xffff);
2843         req.enables = rte_cpu_to_le_32(enables);
2844
2845         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2846
2847         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2848
2849         HWRM_CHECK_RESULT();
2850         HWRM_UNLOCK();
2851
2852         return rc;
2853 }
2854
2855 static void populate_vf_func_cfg_req(struct bnxt *bp,
2856                                      struct hwrm_func_cfg_input *req,
2857                                      int num_vfs)
2858 {
2859         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2860                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2861                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2862                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2863                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2864                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2865                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2866                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2867                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2868                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2869
2870         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2871                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2872                                     BNXT_NUM_VLANS);
2873         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2874                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2875                                     BNXT_NUM_VLANS);
2876         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2877                                                 (num_vfs + 1));
2878         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2879         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2880                                                (num_vfs + 1));
2881         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2882         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2883         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2884         /* TODO: For now, do not support VMDq/RFS on VFs. */
2885         req->num_vnics = rte_cpu_to_le_16(1);
2886         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2887                                                  (num_vfs + 1));
2888 }
2889
2890 static void add_random_mac_if_needed(struct bnxt *bp,
2891                                      struct hwrm_func_cfg_input *cfg_req,
2892                                      int vf)
2893 {
2894         struct rte_ether_addr mac;
2895
2896         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2897                 return;
2898
2899         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2900                 cfg_req->enables |=
2901                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2902                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2903                 bp->pf.vf_info[vf].random_mac = true;
2904         } else {
2905                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2906                         RTE_ETHER_ADDR_LEN);
2907         }
2908 }
2909
2910 static void reserve_resources_from_vf(struct bnxt *bp,
2911                                       struct hwrm_func_cfg_input *cfg_req,
2912                                       int vf)
2913 {
2914         struct hwrm_func_qcaps_input req = {0};
2915         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2916         int rc;
2917
2918         /* Get the actual allocated values now */
2919         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2920         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2922
2923         if (rc) {
2924                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2925                 copy_func_cfg_to_qcaps(cfg_req, resp);
2926         } else if (resp->error_code) {
2927                 rc = rte_le_to_cpu_16(resp->error_code);
2928                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2929                 copy_func_cfg_to_qcaps(cfg_req, resp);
2930         }
2931
2932         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2933         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2934         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2935         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2936         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2937         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2938         /*
2939          * TODO: While not supporting VMDq with VFs, max_vnics is always
2940          * forced to 1 in this case
2941          */
2942         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2943         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2944
2945         HWRM_UNLOCK();
2946 }
2947
2948 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2949 {
2950         struct hwrm_func_qcfg_input req = {0};
2951         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2952         int rc;
2953
2954         /* Check for zero MAC address */
2955         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2956         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2957         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2958         HWRM_CHECK_RESULT();
2959         rc = rte_le_to_cpu_16(resp->vlan);
2960
2961         HWRM_UNLOCK();
2962
2963         return rc;
2964 }
2965
2966 static int update_pf_resource_max(struct bnxt *bp)
2967 {
2968         struct hwrm_func_qcfg_input req = {0};
2969         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2970         int rc;
2971
2972         /* And copy the allocated numbers into the pf struct */
2973         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2974         req.fid = rte_cpu_to_le_16(0xffff);
2975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2976         HWRM_CHECK_RESULT();
2977
2978         /* Only TX ring value reflects actual allocation? TODO */
2979         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2980         bp->pf.evb_mode = resp->evb_mode;
2981
2982         HWRM_UNLOCK();
2983
2984         return rc;
2985 }
2986
2987 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2988 {
2989         int rc;
2990
2991         if (!BNXT_PF(bp)) {
2992                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2993                 return -EINVAL;
2994         }
2995
2996         rc = bnxt_hwrm_func_qcaps(bp);
2997         if (rc)
2998                 return rc;
2999
3000         bp->pf.func_cfg_flags &=
3001                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3002                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3003         bp->pf.func_cfg_flags |=
3004                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3005         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3006         rc = __bnxt_hwrm_func_qcaps(bp);
3007         return rc;
3008 }
3009
3010 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3011 {
3012         struct hwrm_func_cfg_input req = {0};
3013         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3014         int i;
3015         size_t sz;
3016         int rc = 0;
3017         size_t req_buf_sz;
3018
3019         if (!BNXT_PF(bp)) {
3020                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3021                 return -EINVAL;
3022         }
3023
3024         rc = bnxt_hwrm_func_qcaps(bp);
3025
3026         if (rc)
3027                 return rc;
3028
3029         bp->pf.active_vfs = num_vfs;
3030
3031         /*
3032          * First, configure the PF to only use one TX ring.  This ensures that
3033          * there are enough rings for all VFs.
3034          *
3035          * If we don't do this, when we call func_alloc() later, we will lock
3036          * extra rings to the PF that won't be available during func_cfg() of
3037          * the VFs.
3038          *
3039          * This has been fixed with firmware versions above 20.6.54
3040          */
3041         bp->pf.func_cfg_flags &=
3042                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3043                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3044         bp->pf.func_cfg_flags |=
3045                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3046         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3047         if (rc)
3048                 return rc;
3049
3050         /*
3051          * Now, create and register a buffer to hold forwarded VF requests
3052          */
3053         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3054         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3055                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3056         if (bp->pf.vf_req_buf == NULL) {
3057                 rc = -ENOMEM;
3058                 goto error_free;
3059         }
3060         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3061                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3062         for (i = 0; i < num_vfs; i++)
3063                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3064                                         (i * HWRM_MAX_REQ_LEN);
3065
3066         rc = bnxt_hwrm_func_buf_rgtr(bp);
3067         if (rc)
3068                 goto error_free;
3069
3070         populate_vf_func_cfg_req(bp, &req, num_vfs);
3071
3072         bp->pf.active_vfs = 0;
3073         for (i = 0; i < num_vfs; i++) {
3074                 add_random_mac_if_needed(bp, &req, i);
3075
3076                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3077                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3078                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3079                 rc = bnxt_hwrm_send_message(bp,
3080                                             &req,
3081                                             sizeof(req),
3082                                             BNXT_USE_CHIMP_MB);
3083
3084                 /* Clear enable flag for next pass */
3085                 req.enables &= ~rte_cpu_to_le_32(
3086                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3087
3088                 if (rc || resp->error_code) {
3089                         PMD_DRV_LOG(ERR,
3090                                 "Failed to initizlie VF %d\n", i);
3091                         PMD_DRV_LOG(ERR,
3092                                 "Not all VFs available. (%d, %d)\n",
3093                                 rc, resp->error_code);
3094                         HWRM_UNLOCK();
3095                         break;
3096                 }
3097
3098                 HWRM_UNLOCK();
3099
3100                 reserve_resources_from_vf(bp, &req, i);
3101                 bp->pf.active_vfs++;
3102                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3103         }
3104
3105         /*
3106          * Now configure the PF to use "the rest" of the resources
3107          * We're using STD_TX_RING_MODE here though which will limit the TX
3108          * rings.  This will allow QoS to function properly.  Not setting this
3109          * will cause PF rings to break bandwidth settings.
3110          */
3111         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3112         if (rc)
3113                 goto error_free;
3114
3115         rc = update_pf_resource_max(bp);
3116         if (rc)
3117                 goto error_free;
3118
3119         return rc;
3120
3121 error_free:
3122         bnxt_hwrm_func_buf_unrgtr(bp);
3123         return rc;
3124 }
3125
3126 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3127 {
3128         struct hwrm_func_cfg_input req = {0};
3129         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3130         int rc;
3131
3132         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3133
3134         req.fid = rte_cpu_to_le_16(0xffff);
3135         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3136         req.evb_mode = bp->pf.evb_mode;
3137
3138         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3139         HWRM_CHECK_RESULT();
3140         HWRM_UNLOCK();
3141
3142         return rc;
3143 }
3144
3145 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3146                                 uint8_t tunnel_type)
3147 {
3148         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3149         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3150         int rc = 0;
3151
3152         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3153         req.tunnel_type = tunnel_type;
3154         req.tunnel_dst_port_val = port;
3155         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3156         HWRM_CHECK_RESULT();
3157
3158         switch (tunnel_type) {
3159         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3160                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3161                 bp->vxlan_port = port;
3162                 break;
3163         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3164                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3165                 bp->geneve_port = port;
3166                 break;
3167         default:
3168                 break;
3169         }
3170
3171         HWRM_UNLOCK();
3172
3173         return rc;
3174 }
3175
3176 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3177                                 uint8_t tunnel_type)
3178 {
3179         struct hwrm_tunnel_dst_port_free_input req = {0};
3180         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3181         int rc = 0;
3182
3183         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3184
3185         req.tunnel_type = tunnel_type;
3186         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3188
3189         HWRM_CHECK_RESULT();
3190         HWRM_UNLOCK();
3191
3192         return rc;
3193 }
3194
3195 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3196                                         uint32_t flags)
3197 {
3198         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3199         struct hwrm_func_cfg_input req = {0};
3200         int rc;
3201
3202         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3203
3204         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3205         req.flags = rte_cpu_to_le_32(flags);
3206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3207
3208         HWRM_CHECK_RESULT();
3209         HWRM_UNLOCK();
3210
3211         return rc;
3212 }
3213
3214 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3215 {
3216         uint32_t *flag = flagp;
3217
3218         vnic->flags = *flag;
3219 }
3220
3221 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3222 {
3223         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3224 }
3225
3226 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3227 {
3228         int rc = 0;
3229         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3230         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3231
3232         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3233
3234         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3235         req.req_buf_page_size = rte_cpu_to_le_16(
3236                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3237         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3238         req.req_buf_page_addr0 =
3239                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3240         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3241                 PMD_DRV_LOG(ERR,
3242                         "unable to map buffer address to physical memory\n");
3243                 return -ENOMEM;
3244         }
3245
3246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3247
3248         HWRM_CHECK_RESULT();
3249         HWRM_UNLOCK();
3250
3251         return rc;
3252 }
3253
3254 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3255 {
3256         int rc = 0;
3257         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3258         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3259
3260         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3261                 return 0;
3262
3263         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3264
3265         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3266
3267         HWRM_CHECK_RESULT();
3268         HWRM_UNLOCK();
3269
3270         return rc;
3271 }
3272
3273 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3274 {
3275         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3276         struct hwrm_func_cfg_input req = {0};
3277         int rc;
3278
3279         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3280
3281         req.fid = rte_cpu_to_le_16(0xffff);
3282         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3283         req.enables = rte_cpu_to_le_32(
3284                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3285         req.async_event_cr = rte_cpu_to_le_16(
3286                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3288
3289         HWRM_CHECK_RESULT();
3290         HWRM_UNLOCK();
3291
3292         return rc;
3293 }
3294
3295 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3296 {
3297         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3298         struct hwrm_func_vf_cfg_input req = {0};
3299         int rc;
3300
3301         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3302
3303         req.enables = rte_cpu_to_le_32(
3304                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3305         req.async_event_cr = rte_cpu_to_le_16(
3306                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3308
3309         HWRM_CHECK_RESULT();
3310         HWRM_UNLOCK();
3311
3312         return rc;
3313 }
3314
3315 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3316 {
3317         struct hwrm_func_cfg_input req = {0};
3318         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3319         uint16_t dflt_vlan, fid;
3320         uint32_t func_cfg_flags;
3321         int rc = 0;
3322
3323         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3324
3325         if (is_vf) {
3326                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3327                 fid = bp->pf.vf_info[vf].fid;
3328                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3329         } else {
3330                 fid = rte_cpu_to_le_16(0xffff);
3331                 func_cfg_flags = bp->pf.func_cfg_flags;
3332                 dflt_vlan = bp->vlan;
3333         }
3334
3335         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3336         req.fid = rte_cpu_to_le_16(fid);
3337         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3338         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3339
3340         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3341
3342         HWRM_CHECK_RESULT();
3343         HWRM_UNLOCK();
3344
3345         return rc;
3346 }
3347
3348 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3349                         uint16_t max_bw, uint16_t enables)
3350 {
3351         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3352         struct hwrm_func_cfg_input req = {0};
3353         int rc;
3354
3355         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3356
3357         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3358         req.enables |= rte_cpu_to_le_32(enables);
3359         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3360         req.max_bw = rte_cpu_to_le_32(max_bw);
3361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3362
3363         HWRM_CHECK_RESULT();
3364         HWRM_UNLOCK();
3365
3366         return rc;
3367 }
3368
3369 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3370 {
3371         struct hwrm_func_cfg_input req = {0};
3372         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3373         int rc = 0;
3374
3375         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3376
3377         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3378         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3379         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3380         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3381
3382         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3383
3384         HWRM_CHECK_RESULT();
3385         HWRM_UNLOCK();
3386
3387         return rc;
3388 }
3389
3390 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3391 {
3392         int rc;
3393
3394         if (BNXT_PF(bp))
3395                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3396         else
3397                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3398
3399         return rc;
3400 }
3401
3402 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3403                               void *encaped, size_t ec_size)
3404 {
3405         int rc = 0;
3406         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3407         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3408
3409         if (ec_size > sizeof(req.encap_request))
3410                 return -1;
3411
3412         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3413
3414         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3415         memcpy(req.encap_request, encaped, ec_size);
3416
3417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3418
3419         HWRM_CHECK_RESULT();
3420         HWRM_UNLOCK();
3421
3422         return rc;
3423 }
3424
3425 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3426                                        struct rte_ether_addr *mac)
3427 {
3428         struct hwrm_func_qcfg_input req = {0};
3429         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3430         int rc;
3431
3432         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3433
3434         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436
3437         HWRM_CHECK_RESULT();
3438
3439         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3440
3441         HWRM_UNLOCK();
3442
3443         return rc;
3444 }
3445
3446 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3447                             void *encaped, size_t ec_size)
3448 {
3449         int rc = 0;
3450         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3451         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3452
3453         if (ec_size > sizeof(req.encap_request))
3454                 return -1;
3455
3456         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3457
3458         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3459         memcpy(req.encap_request, encaped, ec_size);
3460
3461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3462
3463         HWRM_CHECK_RESULT();
3464         HWRM_UNLOCK();
3465
3466         return rc;
3467 }
3468
3469 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3470                          struct rte_eth_stats *stats, uint8_t rx)
3471 {
3472         int rc = 0;
3473         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3474         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3475
3476         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3477
3478         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3479
3480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3481
3482         HWRM_CHECK_RESULT();
3483
3484         if (rx) {
3485                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3486                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3487                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3488                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3489                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3490                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3491                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3492                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3493         } else {
3494                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3495                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3496                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3497                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3498                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3499                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3500         }
3501
3502
3503         HWRM_UNLOCK();
3504
3505         return rc;
3506 }
3507
3508 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3509 {
3510         struct hwrm_port_qstats_input req = {0};
3511         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3512         struct bnxt_pf_info *pf = &bp->pf;
3513         int rc;
3514
3515         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3516
3517         req.port_id = rte_cpu_to_le_16(pf->port_id);
3518         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3519         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3521
3522         HWRM_CHECK_RESULT();
3523         HWRM_UNLOCK();
3524
3525         return rc;
3526 }
3527
3528 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3529 {
3530         struct hwrm_port_clr_stats_input req = {0};
3531         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3532         struct bnxt_pf_info *pf = &bp->pf;
3533         int rc;
3534
3535         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3536         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3537             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3538                 return 0;
3539
3540         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3541
3542         req.port_id = rte_cpu_to_le_16(pf->port_id);
3543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3544
3545         HWRM_CHECK_RESULT();
3546         HWRM_UNLOCK();
3547
3548         return rc;
3549 }
3550
3551 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3552 {
3553         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3554         struct hwrm_port_led_qcaps_input req = {0};
3555         int rc;
3556
3557         if (BNXT_VF(bp))
3558                 return 0;
3559
3560         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3561         req.port_id = bp->pf.port_id;
3562         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3563
3564         HWRM_CHECK_RESULT();
3565
3566         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3567                 unsigned int i;
3568
3569                 bp->num_leds = resp->num_leds;
3570                 memcpy(bp->leds, &resp->led0_id,
3571                         sizeof(bp->leds[0]) * bp->num_leds);
3572                 for (i = 0; i < bp->num_leds; i++) {
3573                         struct bnxt_led_info *led = &bp->leds[i];
3574
3575                         uint16_t caps = led->led_state_caps;
3576
3577                         if (!led->led_group_id ||
3578                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3579                                 bp->num_leds = 0;
3580                                 break;
3581                         }
3582                 }
3583         }
3584
3585         HWRM_UNLOCK();
3586
3587         return rc;
3588 }
3589
3590 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3591 {
3592         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3593         struct hwrm_port_led_cfg_input req = {0};
3594         struct bnxt_led_cfg *led_cfg;
3595         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3596         uint16_t duration = 0;
3597         int rc, i;
3598
3599         if (!bp->num_leds || BNXT_VF(bp))
3600                 return -EOPNOTSUPP;
3601
3602         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3603
3604         if (led_on) {
3605                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3606                 duration = rte_cpu_to_le_16(500);
3607         }
3608         req.port_id = bp->pf.port_id;
3609         req.num_leds = bp->num_leds;
3610         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3611         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3612                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3613                 led_cfg->led_id = bp->leds[i].led_id;
3614                 led_cfg->led_state = led_state;
3615                 led_cfg->led_blink_on = duration;
3616                 led_cfg->led_blink_off = duration;
3617                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3618         }
3619
3620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3621
3622         HWRM_CHECK_RESULT();
3623         HWRM_UNLOCK();
3624
3625         return rc;
3626 }
3627
3628 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3629                                uint32_t *length)
3630 {
3631         int rc;
3632         struct hwrm_nvm_get_dir_info_input req = {0};
3633         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3634
3635         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3636
3637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3638
3639         HWRM_CHECK_RESULT();
3640
3641         *entries = rte_le_to_cpu_32(resp->entries);
3642         *length = rte_le_to_cpu_32(resp->entry_length);
3643
3644         HWRM_UNLOCK();
3645         return rc;
3646 }
3647
3648 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3649 {
3650         int rc;
3651         uint32_t dir_entries;
3652         uint32_t entry_length;
3653         uint8_t *buf;
3654         size_t buflen;
3655         rte_iova_t dma_handle;
3656         struct hwrm_nvm_get_dir_entries_input req = {0};
3657         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3658
3659         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3660         if (rc != 0)
3661                 return rc;
3662
3663         *data++ = dir_entries;
3664         *data++ = entry_length;
3665         len -= 2;
3666         memset(data, 0xff, len);
3667
3668         buflen = dir_entries * entry_length;
3669         buf = rte_malloc("nvm_dir", buflen, 0);
3670         rte_mem_lock_page(buf);
3671         if (buf == NULL)
3672                 return -ENOMEM;
3673         dma_handle = rte_mem_virt2iova(buf);
3674         if (dma_handle == RTE_BAD_IOVA) {
3675                 PMD_DRV_LOG(ERR,
3676                         "unable to map response address to physical memory\n");
3677                 return -ENOMEM;
3678         }
3679         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3680         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3682
3683         if (rc == 0)
3684                 memcpy(data, buf, len > buflen ? buflen : len);
3685
3686         rte_free(buf);
3687         HWRM_CHECK_RESULT();
3688         HWRM_UNLOCK();
3689
3690         return rc;
3691 }
3692
3693 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3694                              uint32_t offset, uint32_t length,
3695                              uint8_t *data)
3696 {
3697         int rc;
3698         uint8_t *buf;
3699         rte_iova_t dma_handle;
3700         struct hwrm_nvm_read_input req = {0};
3701         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3702
3703         buf = rte_malloc("nvm_item", length, 0);
3704         rte_mem_lock_page(buf);
3705         if (!buf)
3706                 return -ENOMEM;
3707
3708         dma_handle = rte_mem_virt2iova(buf);
3709         if (dma_handle == RTE_BAD_IOVA) {
3710                 PMD_DRV_LOG(ERR,
3711                         "unable to map response address to physical memory\n");
3712                 return -ENOMEM;
3713         }
3714         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3715         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3716         req.dir_idx = rte_cpu_to_le_16(index);
3717         req.offset = rte_cpu_to_le_32(offset);
3718         req.len = rte_cpu_to_le_32(length);
3719         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3720         if (rc == 0)
3721                 memcpy(data, buf, length);
3722
3723         rte_free(buf);
3724         HWRM_CHECK_RESULT();
3725         HWRM_UNLOCK();
3726
3727         return rc;
3728 }
3729
3730 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3731 {
3732         int rc;
3733         struct hwrm_nvm_erase_dir_entry_input req = {0};
3734         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3735
3736         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3737         req.dir_idx = rte_cpu_to_le_16(index);
3738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3739         HWRM_CHECK_RESULT();
3740         HWRM_UNLOCK();
3741
3742         return rc;
3743 }
3744
3745
3746 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3747                           uint16_t dir_ordinal, uint16_t dir_ext,
3748                           uint16_t dir_attr, const uint8_t *data,
3749                           size_t data_len)
3750 {
3751         int rc;
3752         struct hwrm_nvm_write_input req = {0};
3753         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3754         rte_iova_t dma_handle;
3755         uint8_t *buf;
3756
3757         buf = rte_malloc("nvm_write", data_len, 0);
3758         rte_mem_lock_page(buf);
3759         if (!buf)
3760                 return -ENOMEM;
3761
3762         dma_handle = rte_mem_virt2iova(buf);
3763         if (dma_handle == RTE_BAD_IOVA) {
3764                 PMD_DRV_LOG(ERR,
3765                         "unable to map response address to physical memory\n");
3766                 return -ENOMEM;
3767         }
3768         memcpy(buf, data, data_len);
3769
3770         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3771
3772         req.dir_type = rte_cpu_to_le_16(dir_type);
3773         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3774         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3775         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3776         req.dir_data_length = rte_cpu_to_le_32(data_len);
3777         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3778
3779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3780
3781         rte_free(buf);
3782         HWRM_CHECK_RESULT();
3783         HWRM_UNLOCK();
3784
3785         return rc;
3786 }
3787
3788 static void
3789 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3790 {
3791         uint32_t *count = cbdata;
3792
3793         *count = *count + 1;
3794 }
3795
3796 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3797                                      struct bnxt_vnic_info *vnic __rte_unused)
3798 {
3799         return 0;
3800 }
3801
3802 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3803 {
3804         uint32_t count = 0;
3805
3806         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3807             &count, bnxt_vnic_count_hwrm_stub);
3808
3809         return count;
3810 }
3811
3812 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3813                                         uint16_t *vnic_ids)
3814 {
3815         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3816         struct hwrm_func_vf_vnic_ids_query_output *resp =
3817                                                 bp->hwrm_cmd_resp_addr;
3818         int rc;
3819
3820         /* First query all VNIC ids */
3821         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3822
3823         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3824         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3825         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3826
3827         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3828                 HWRM_UNLOCK();
3829                 PMD_DRV_LOG(ERR,
3830                 "unable to map VNIC ID table address to physical memory\n");
3831                 return -ENOMEM;
3832         }
3833         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3834         HWRM_CHECK_RESULT();
3835         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3836
3837         HWRM_UNLOCK();
3838
3839         return rc;
3840 }
3841
3842 /*
3843  * This function queries the VNIC IDs  for a specified VF. It then calls
3844  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3845  * Then it calls the hwrm_cb function to program this new vnic configuration.
3846  */
3847 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3848         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3849         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3850 {
3851         struct bnxt_vnic_info vnic;
3852         int rc = 0;
3853         int i, num_vnic_ids;
3854         uint16_t *vnic_ids;
3855         size_t vnic_id_sz;
3856         size_t sz;
3857
3858         /* First query all VNIC ids */
3859         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3860         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3861                         RTE_CACHE_LINE_SIZE);
3862         if (vnic_ids == NULL)
3863                 return -ENOMEM;
3864
3865         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3866                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3867
3868         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3869
3870         if (num_vnic_ids < 0)
3871                 return num_vnic_ids;
3872
3873         /* Retrieve VNIC, update bd_stall then update */
3874
3875         for (i = 0; i < num_vnic_ids; i++) {
3876                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3877                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3878                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3879                 if (rc)
3880                         break;
3881                 if (vnic.mru <= 4)      /* Indicates unallocated */
3882                         continue;
3883
3884                 vnic_cb(&vnic, cbdata);
3885
3886                 rc = hwrm_cb(bp, &vnic);
3887                 if (rc)
3888                         break;
3889         }
3890
3891         rte_free(vnic_ids);
3892
3893         return rc;
3894 }
3895
3896 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3897                                               bool on)
3898 {
3899         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3900         struct hwrm_func_cfg_input req = {0};
3901         int rc;
3902
3903         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3904
3905         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3906         req.enables |= rte_cpu_to_le_32(
3907                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3908         req.vlan_antispoof_mode = on ?
3909                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3910                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3912
3913         HWRM_CHECK_RESULT();
3914         HWRM_UNLOCK();
3915
3916         return rc;
3917 }
3918
3919 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3920 {
3921         struct bnxt_vnic_info vnic;
3922         uint16_t *vnic_ids;
3923         size_t vnic_id_sz;
3924         int num_vnic_ids, i;
3925         size_t sz;
3926         int rc;
3927
3928         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3929         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3930                         RTE_CACHE_LINE_SIZE);
3931         if (vnic_ids == NULL)
3932                 return -ENOMEM;
3933
3934         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3935                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3936
3937         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3938         if (rc <= 0)
3939                 goto exit;
3940         num_vnic_ids = rc;
3941
3942         /*
3943          * Loop through to find the default VNIC ID.
3944          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3945          * by sending the hwrm_func_qcfg command to the firmware.
3946          */
3947         for (i = 0; i < num_vnic_ids; i++) {
3948                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3949                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3950                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3951                                         bp->pf.first_vf_id + vf);
3952                 if (rc)
3953                         goto exit;
3954                 if (vnic.func_default) {
3955                         rte_free(vnic_ids);
3956                         return vnic.fw_vnic_id;
3957                 }
3958         }
3959         /* Could not find a default VNIC. */
3960         PMD_DRV_LOG(ERR, "No default VNIC\n");
3961 exit:
3962         rte_free(vnic_ids);
3963         return rc;
3964 }
3965
3966 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3967                          uint16_t dst_id,
3968                          struct bnxt_filter_info *filter)
3969 {
3970         int rc = 0;
3971         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3972         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3973         uint32_t enables = 0;
3974
3975         if (filter->fw_em_filter_id != UINT64_MAX)
3976                 bnxt_hwrm_clear_em_filter(bp, filter);
3977
3978         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3979
3980         req.flags = rte_cpu_to_le_32(filter->flags);
3981
3982         enables = filter->enables |
3983               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3984         req.dst_id = rte_cpu_to_le_16(dst_id);
3985
3986         if (filter->ip_addr_type) {
3987                 req.ip_addr_type = filter->ip_addr_type;
3988                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3989         }
3990         if (enables &
3991             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3992                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3993         if (enables &
3994             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3995                 memcpy(req.src_macaddr, filter->src_macaddr,
3996                        RTE_ETHER_ADDR_LEN);
3997         if (enables &
3998             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3999                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4000                        RTE_ETHER_ADDR_LEN);
4001         if (enables &
4002             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4003                 req.ovlan_vid = filter->l2_ovlan;
4004         if (enables &
4005             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4006                 req.ivlan_vid = filter->l2_ivlan;
4007         if (enables &
4008             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4009                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4010         if (enables &
4011             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4012                 req.ip_protocol = filter->ip_protocol;
4013         if (enables &
4014             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4015                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4016         if (enables &
4017             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4018                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4019         if (enables &
4020             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4021                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4022         if (enables &
4023             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4024                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4025         if (enables &
4026             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4027                 req.mirror_vnic_id = filter->mirror_vnic_id;
4028
4029         req.enables = rte_cpu_to_le_32(enables);
4030
4031         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4032
4033         HWRM_CHECK_RESULT();
4034
4035         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4036         HWRM_UNLOCK();
4037
4038         return rc;
4039 }
4040
4041 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4042 {
4043         int rc = 0;
4044         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4045         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4046
4047         if (filter->fw_em_filter_id == UINT64_MAX)
4048                 return 0;
4049
4050         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4051         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4052
4053         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4054
4055         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4056
4057         HWRM_CHECK_RESULT();
4058         HWRM_UNLOCK();
4059
4060         filter->fw_em_filter_id = UINT64_MAX;
4061         filter->fw_l2_filter_id = UINT64_MAX;
4062
4063         return 0;
4064 }
4065
4066 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4067                          uint16_t dst_id,
4068                          struct bnxt_filter_info *filter)
4069 {
4070         int rc = 0;
4071         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4072         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4073                                                 bp->hwrm_cmd_resp_addr;
4074         uint32_t enables = 0;
4075
4076         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4077                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4078
4079         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4080
4081         req.flags = rte_cpu_to_le_32(filter->flags);
4082
4083         enables = filter->enables |
4084               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4085         req.dst_id = rte_cpu_to_le_16(dst_id);
4086
4087
4088         if (filter->ip_addr_type) {
4089                 req.ip_addr_type = filter->ip_addr_type;
4090                 enables |=
4091                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4092         }
4093         if (enables &
4094             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4095                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4096         if (enables &
4097             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4098                 memcpy(req.src_macaddr, filter->src_macaddr,
4099                        RTE_ETHER_ADDR_LEN);
4100         //if (enables &
4101             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4102                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4103                        //RTE_ETHER_ADDR_LEN);
4104         if (enables &
4105             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4106                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4107         if (enables &
4108             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4109                 req.ip_protocol = filter->ip_protocol;
4110         if (enables &
4111             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4112                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4113         if (enables &
4114             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4115                 req.src_ipaddr_mask[0] =
4116                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4117         if (enables &
4118             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4119                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4120         if (enables &
4121             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4122                 req.dst_ipaddr_mask[0] =
4123                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4124         if (enables &
4125             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4126                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4127         if (enables &
4128             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4129                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4130         if (enables &
4131             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4132                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4133         if (enables &
4134             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4135                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4136         if (enables &
4137             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4138                 req.mirror_vnic_id = filter->mirror_vnic_id;
4139
4140         req.enables = rte_cpu_to_le_32(enables);
4141
4142         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4143
4144         HWRM_CHECK_RESULT();
4145
4146         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4147         HWRM_UNLOCK();
4148
4149         return rc;
4150 }
4151
4152 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4153                                 struct bnxt_filter_info *filter)
4154 {
4155         int rc = 0;
4156         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4157         struct hwrm_cfa_ntuple_filter_free_output *resp =
4158                                                 bp->hwrm_cmd_resp_addr;
4159
4160         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4161                 return 0;
4162
4163         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4164
4165         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4166
4167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4168
4169         HWRM_CHECK_RESULT();
4170         HWRM_UNLOCK();
4171
4172         filter->fw_ntuple_filter_id = UINT64_MAX;
4173
4174         return 0;
4175 }
4176
4177 static int
4178 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4179 {
4180         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4181         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4182         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4183         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4184         uint16_t *ring_tbl = vnic->rss_table;
4185         int nr_ctxs = vnic->num_lb_ctxts;
4186         int max_rings = bp->rx_nr_rings;
4187         int i, j, k, cnt;
4188         int rc = 0;
4189
4190         for (i = 0, k = 0; i < nr_ctxs; i++) {
4191                 struct bnxt_rx_ring_info *rxr;
4192                 struct bnxt_cp_ring_info *cpr;
4193
4194                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4195
4196                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4197                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4198                 req.hash_mode_flags = vnic->hash_mode;
4199
4200                 req.ring_grp_tbl_addr =
4201                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4202                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4203                                      2 * sizeof(*ring_tbl));
4204                 req.hash_key_tbl_addr =
4205                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4206
4207                 req.ring_table_pair_index = i;
4208                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4209
4210                 for (j = 0; j < 64; j++) {
4211                         uint16_t ring_id;
4212
4213                         /* Find next active ring. */
4214                         for (cnt = 0; cnt < max_rings; cnt++) {
4215                                 if (rx_queue_state[k] !=
4216                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4217                                         break;
4218                                 if (++k == max_rings)
4219                                         k = 0;
4220                         }
4221
4222                         /* Return if no rings are active. */
4223                         if (cnt == max_rings)
4224                                 return 0;
4225
4226                         /* Add rx/cp ring pair to RSS table. */
4227                         rxr = rxqs[k]->rx_ring;
4228                         cpr = rxqs[k]->cp_ring;
4229
4230                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4231                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4232                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4233                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4234
4235                         if (++k == max_rings)
4236                                 k = 0;
4237                 }
4238                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4239                                             BNXT_USE_CHIMP_MB);
4240
4241                 HWRM_CHECK_RESULT();
4242                 HWRM_UNLOCK();
4243         }
4244
4245         return rc;
4246 }
4247
4248 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4249 {
4250         unsigned int rss_idx, fw_idx, i;
4251
4252         if (!(vnic->rss_table && vnic->hash_type))
4253                 return 0;
4254
4255         if (BNXT_CHIP_THOR(bp))
4256                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4257
4258         /*
4259          * Fill the RSS hash & redirection table with
4260          * ring group ids for all VNICs
4261          */
4262         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4263                 rss_idx++, fw_idx++) {
4264                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4265                         fw_idx %= bp->rx_cp_nr_rings;
4266                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4267                                 break;
4268                         fw_idx++;
4269                 }
4270                 if (i == bp->rx_cp_nr_rings)
4271                         return 0;
4272                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4273         }
4274         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4275 }
4276
4277 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4278         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4279 {
4280         uint16_t flags;
4281
4282         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4283
4284         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4285         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4286
4287         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4288         req->num_cmpl_dma_aggr_during_int =
4289                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4290
4291         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4292
4293         /* min timer set to 1/2 of interrupt timer */
4294         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4295
4296         /* buf timer set to 1/4 of interrupt timer */
4297         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4298
4299         req->cmpl_aggr_dma_tmr_during_int =
4300                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4301
4302         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4303                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4304         req->flags = rte_cpu_to_le_16(flags);
4305 }
4306
4307 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4308                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4309 {
4310         struct hwrm_ring_aggint_qcaps_input req = {0};
4311         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4312         uint32_t enables;
4313         uint16_t flags;
4314         int rc;
4315
4316         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4317         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4318         HWRM_CHECK_RESULT();
4319
4320         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4321         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4322
4323         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4324                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4325         agg_req->flags = rte_cpu_to_le_16(flags);
4326         enables =
4327          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4328          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4329         agg_req->enables = rte_cpu_to_le_32(enables);
4330
4331         HWRM_UNLOCK();
4332         return rc;
4333 }
4334
4335 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4336                         struct bnxt_coal *coal, uint16_t ring_id)
4337 {
4338         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4339         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4340                                                 bp->hwrm_cmd_resp_addr;
4341         int rc;
4342
4343         /* Set ring coalesce parameters only for 100G NICs */
4344         if (BNXT_CHIP_THOR(bp)) {
4345                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4346                         return -1;
4347         } else if (bnxt_stratus_device(bp)) {
4348                 bnxt_hwrm_set_coal_params(coal, &req);
4349         } else {
4350                 return 0;
4351         }
4352
4353         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4354         req.ring_id = rte_cpu_to_le_16(ring_id);
4355         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4356         HWRM_CHECK_RESULT();
4357         HWRM_UNLOCK();
4358         return 0;
4359 }
4360
4361 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4362 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4363 {
4364         struct hwrm_func_backing_store_qcaps_input req = {0};
4365         struct hwrm_func_backing_store_qcaps_output *resp =
4366                 bp->hwrm_cmd_resp_addr;
4367         int rc;
4368
4369         if (!BNXT_CHIP_THOR(bp) ||
4370             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4371             BNXT_VF(bp) ||
4372             bp->ctx)
4373                 return 0;
4374
4375         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4376         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4377         HWRM_CHECK_RESULT_SILENT();
4378
4379         if (!rc) {
4380                 struct bnxt_ctx_pg_info *ctx_pg;
4381                 struct bnxt_ctx_mem_info *ctx;
4382                 int total_alloc_len;
4383                 int i;
4384
4385                 total_alloc_len = sizeof(*ctx);
4386                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4387                                  RTE_CACHE_LINE_SIZE);
4388                 if (!ctx) {
4389                         rc = -ENOMEM;
4390                         goto ctx_err;
4391                 }
4392                 memset(ctx, 0, total_alloc_len);
4393
4394                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4395                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4396                                     RTE_CACHE_LINE_SIZE);
4397                 if (!ctx_pg) {
4398                         rc = -ENOMEM;
4399                         goto ctx_err;
4400                 }
4401                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4402                         ctx->tqm_mem[i] = ctx_pg;
4403
4404                 bp->ctx = ctx;
4405                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4406                 ctx->qp_min_qp1_entries =
4407                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4408                 ctx->qp_max_l2_entries =
4409                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4410                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4411                 ctx->srq_max_l2_entries =
4412                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4413                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4414                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4415                 ctx->cq_max_l2_entries =
4416                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4417                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4418                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4419                 ctx->vnic_max_vnic_entries =
4420                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4421                 ctx->vnic_max_ring_table_entries =
4422                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4423                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4424                 ctx->stat_max_entries =
4425                         rte_le_to_cpu_32(resp->stat_max_entries);
4426                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4427                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4428                 ctx->tqm_min_entries_per_ring =
4429                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4430                 ctx->tqm_max_entries_per_ring =
4431                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4432                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4433                 if (!ctx->tqm_entries_multiple)
4434                         ctx->tqm_entries_multiple = 1;
4435                 ctx->mrav_max_entries =
4436                         rte_le_to_cpu_32(resp->mrav_max_entries);
4437                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4438                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4439                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4440         } else {
4441                 rc = 0;
4442         }
4443 ctx_err:
4444         HWRM_UNLOCK();
4445         return rc;
4446 }
4447
4448 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4449 {
4450         struct hwrm_func_backing_store_cfg_input req = {0};
4451         struct hwrm_func_backing_store_cfg_output *resp =
4452                 bp->hwrm_cmd_resp_addr;
4453         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4454         struct bnxt_ctx_pg_info *ctx_pg;
4455         uint32_t *num_entries;
4456         uint64_t *pg_dir;
4457         uint8_t *pg_attr;
4458         uint32_t ena;
4459         int i, rc;
4460
4461         if (!ctx)
4462                 return 0;
4463
4464         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4465         req.enables = rte_cpu_to_le_32(enables);
4466
4467         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4468                 ctx_pg = &ctx->qp_mem;
4469                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4470                 req.qp_num_qp1_entries =
4471                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4472                 req.qp_num_l2_entries =
4473                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4474                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4475                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4476                                       &req.qpc_pg_size_qpc_lvl,
4477                                       &req.qpc_page_dir);
4478         }
4479
4480         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4481                 ctx_pg = &ctx->srq_mem;
4482                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4483                 req.srq_num_l2_entries =
4484                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4485                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4486                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4487                                       &req.srq_pg_size_srq_lvl,
4488                                       &req.srq_page_dir);
4489         }
4490
4491         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4492                 ctx_pg = &ctx->cq_mem;
4493                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4494                 req.cq_num_l2_entries =
4495                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4496                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4497                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4498                                       &req.cq_pg_size_cq_lvl,
4499                                       &req.cq_page_dir);
4500         }
4501
4502         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4503                 ctx_pg = &ctx->vnic_mem;
4504                 req.vnic_num_vnic_entries =
4505                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4506                 req.vnic_num_ring_table_entries =
4507                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4508                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4509                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4510                                       &req.vnic_pg_size_vnic_lvl,
4511                                       &req.vnic_page_dir);
4512         }
4513
4514         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4515                 ctx_pg = &ctx->stat_mem;
4516                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4517                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4518                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4519                                       &req.stat_pg_size_stat_lvl,
4520                                       &req.stat_page_dir);
4521         }
4522
4523         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4524         num_entries = &req.tqm_sp_num_entries;
4525         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4526         pg_dir = &req.tqm_sp_page_dir;
4527         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4528         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4529                 if (!(enables & ena))
4530                         continue;
4531
4532                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4533
4534                 ctx_pg = ctx->tqm_mem[i];
4535                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4536                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4537         }
4538
4539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4540         HWRM_CHECK_RESULT();
4541         HWRM_UNLOCK();
4542
4543         return rc;
4544 }
4545
4546 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4547 {
4548         struct hwrm_port_qstats_ext_input req = {0};
4549         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4550         struct bnxt_pf_info *pf = &bp->pf;
4551         int rc;
4552
4553         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4554               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4555                 return 0;
4556
4557         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4558
4559         req.port_id = rte_cpu_to_le_16(pf->port_id);
4560         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4561                 req.tx_stat_host_addr =
4562                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4563                 req.tx_stat_size =
4564                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4565         }
4566         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4567                 req.rx_stat_host_addr =
4568                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4569                 req.rx_stat_size =
4570                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4571         }
4572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4573
4574         if (rc) {
4575                 bp->fw_rx_port_stats_ext_size = 0;
4576                 bp->fw_tx_port_stats_ext_size = 0;
4577         } else {
4578                 bp->fw_rx_port_stats_ext_size =
4579                         rte_le_to_cpu_16(resp->rx_stat_size);
4580                 bp->fw_tx_port_stats_ext_size =
4581                         rte_le_to_cpu_16(resp->tx_stat_size);
4582         }
4583
4584         HWRM_CHECK_RESULT();
4585         HWRM_UNLOCK();
4586
4587         return rc;
4588 }
4589
4590 int
4591 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4592 {
4593         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4594         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4595                 bp->hwrm_cmd_resp_addr;
4596         int rc = 0;
4597
4598         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4599         req.tunnel_type = type;
4600         req.dest_fid = bp->fw_fid;
4601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4602         HWRM_CHECK_RESULT();
4603
4604         HWRM_UNLOCK();
4605
4606         return rc;
4607 }
4608
4609 int
4610 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4611 {
4612         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4613         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4614                 bp->hwrm_cmd_resp_addr;
4615         int rc = 0;
4616
4617         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4618         req.tunnel_type = type;
4619         req.dest_fid = bp->fw_fid;
4620         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4621         HWRM_CHECK_RESULT();
4622
4623         HWRM_UNLOCK();
4624
4625         return rc;
4626 }
4627
4628 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4629 {
4630         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4631         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4632                 bp->hwrm_cmd_resp_addr;
4633         int rc = 0;
4634
4635         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4636         req.src_fid = bp->fw_fid;
4637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4638         HWRM_CHECK_RESULT();
4639
4640         if (type)
4641                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4642
4643         HWRM_UNLOCK();
4644
4645         return rc;
4646 }
4647
4648 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4649                                    uint16_t *dst_fid)
4650 {
4651         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4652         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4653                 bp->hwrm_cmd_resp_addr;
4654         int rc = 0;
4655
4656         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4657         req.src_fid = bp->fw_fid;
4658         req.tunnel_type = tun_type;
4659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4660         HWRM_CHECK_RESULT();
4661
4662         if (dst_fid)
4663                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4664
4665         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4666
4667         HWRM_UNLOCK();
4668
4669         return rc;
4670 }
4671
4672 int bnxt_hwrm_set_mac(struct bnxt *bp)
4673 {
4674         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4675         struct hwrm_func_vf_cfg_input req = {0};
4676         int rc = 0;
4677
4678         if (!BNXT_VF(bp))
4679                 return 0;
4680
4681         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4682
4683         req.enables =
4684                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4685         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4686
4687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4688
4689         HWRM_CHECK_RESULT();
4690
4691         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4692         HWRM_UNLOCK();
4693
4694         return rc;
4695 }
4696
4697 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4698 {
4699         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4700         struct hwrm_func_drv_if_change_input req = {0};
4701         uint32_t flags;
4702         int rc;
4703
4704         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4705                 return 0;
4706
4707         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4708          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4709          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4710          */
4711         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4712                 return 0;
4713
4714         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4715
4716         if (up)
4717                 req.flags =
4718                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4719
4720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4721
4722         HWRM_CHECK_RESULT();
4723         flags = rte_le_to_cpu_32(resp->flags);
4724         HWRM_UNLOCK();
4725
4726         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4727                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4728                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4729         }
4730
4731         return 0;
4732 }
4733
4734 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4735 {
4736         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4737         struct bnxt_error_recovery_info *info = bp->recovery_info;
4738         struct hwrm_error_recovery_qcfg_input req = {0};
4739         uint32_t flags = 0;
4740         unsigned int i;
4741         int rc;
4742
4743         /* Older FW does not have error recovery support */
4744         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4745                 return 0;
4746
4747         if (!info) {
4748                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4749                                    sizeof(*info), 0);
4750                 bp->recovery_info = info;
4751                 if (info == NULL)
4752                         return -ENOMEM;
4753         } else {
4754                 memset(info, 0, sizeof(*info));
4755         }
4756
4757         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4758
4759         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4760
4761         HWRM_CHECK_RESULT();
4762
4763         flags = rte_le_to_cpu_32(resp->flags);
4764         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4765                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4766         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4767                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4768
4769         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4770             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4771                 rc = -EINVAL;
4772                 goto err;
4773         }
4774
4775         /* FW returned values are in units of 100msec */
4776         info->driver_polling_freq =
4777                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4778         info->master_func_wait_period =
4779                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4780         info->normal_func_wait_period =
4781                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4782         info->master_func_wait_period_after_reset =
4783                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4784         info->max_bailout_time_after_reset =
4785                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4786         info->status_regs[BNXT_FW_STATUS_REG] =
4787                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4788         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4789                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4790         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4791                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4792         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4793                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4794         info->reg_array_cnt =
4795                 rte_le_to_cpu_32(resp->reg_array_cnt);
4796
4797         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4798                 rc = -EINVAL;
4799                 goto err;
4800         }
4801
4802         for (i = 0; i < info->reg_array_cnt; i++) {
4803                 info->reset_reg[i] =
4804                         rte_le_to_cpu_32(resp->reset_reg[i]);
4805                 info->reset_reg_val[i] =
4806                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4807                 info->delay_after_reset[i] =
4808                         resp->delay_after_reset[i];
4809         }
4810 err:
4811         HWRM_UNLOCK();
4812
4813         /* Map the FW status registers */
4814         if (!rc)
4815                 rc = bnxt_map_fw_health_status_regs(bp);
4816
4817         if (rc) {
4818                 rte_free(bp->recovery_info);
4819                 bp->recovery_info = NULL;
4820         }
4821         return rc;
4822 }
4823
4824 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4825 {
4826         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4827         struct hwrm_fw_reset_input req = {0};
4828         int rc;
4829
4830         if (!BNXT_PF(bp))
4831                 return -EOPNOTSUPP;
4832
4833         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4834
4835         req.embedded_proc_type =
4836                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4837         req.selfrst_status =
4838                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4839         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4840
4841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4842                                     BNXT_USE_KONG(bp));
4843
4844         HWRM_CHECK_RESULT();
4845         HWRM_UNLOCK();
4846
4847         return rc;
4848 }
4849
4850 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4851 {
4852         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4853         struct hwrm_port_ts_query_input req = {0};
4854         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4855         uint32_t flags = 0;
4856         int rc;
4857
4858         if (!ptp)
4859                 return 0;
4860
4861         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4862
4863         switch (path) {
4864         case BNXT_PTP_FLAGS_PATH_TX:
4865                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4866                 break;
4867         case BNXT_PTP_FLAGS_PATH_RX:
4868                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4869                 break;
4870         case BNXT_PTP_FLAGS_CURRENT_TIME:
4871                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4872                 break;
4873         }
4874
4875         req.flags = rte_cpu_to_le_32(flags);
4876         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4877
4878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4879
4880         HWRM_CHECK_RESULT();
4881
4882         if (timestamp) {
4883                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4884                 *timestamp |=
4885                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4886         }
4887         HWRM_UNLOCK();
4888
4889         return rc;
4890 }