drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30 #define HWRM_VERSION_1_10_2_13          0x10a020d
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(int) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages == 0)
  68                 return;
  69
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 static struct bnxt_cp_ring_info*
  79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
  80 {
  81         struct bnxt_cp_ring_info *cp_ring = NULL;
  82         uint16_t i;
  83
  84         switch (type) {
  85         case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
  86         case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
  87                 /* FALLTHROUGH */
  88                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
  89                         struct bnxt_rx_queue *rxq = bp->rx_queues[i];
  90
  91                         if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
  92                             rte_cpu_to_le_16(rid)) {
  93                                 return rxq->cp_ring;
  94                         }
  95                 }
  96                 break;
  97         case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
  98                 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
  99                         struct bnxt_tx_queue *txq = bp->tx_queues[i];
 100
 101                         if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
 102                             rte_cpu_to_le_16(rid)) {
 103                                 return txq->cp_ring;
 104                         }
 105                 }
 106                 break;
 107         default:
 108                 return cp_ring;
 109         }
 110         return cp_ring;
 111 }
 112
 113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
 114  * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
 115  * before timeout, we force the done bit for the cleanup to proceed.
 116  * Also if cpr is null, do nothing.. The HWRM command is  not for a
 117  * Tx/Rx/AGG ring cleanup.
 118  */
 119 static int
 120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
 121                         bool tx, bool rx, bool timeout)
 122 {
 123         int done = 0;
 124
 125         if (cpr != NULL) {
 126                 if (tx)
 127                         done = bnxt_flush_tx_cmp(cpr);
 128
 129                 if (rx)
 130                         done = bnxt_flush_rx_cmp(cpr);
 131
 132                 if (done)
 133                         PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
 134                                     rx ? "Rx" : "Tx");
 135
 136                 /* We are about to timeout and still haven't seen the
 137                  * HWRM done for the Ring free. Force the cleanup.
 138                  */
 139                 if (!done && timeout) {
 140                         done = 1;
 141                         PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
 142                                     rx ? "Rx" : "Tx");
 143                 }
 144         } else {
 145                 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
 146                  * Otherwise the cpr would have been valid. So do nothing.
 147                  */
 148                 done = 1;
 149         }
 150
 151         return done;
 152 }
 153
 154 /*
 155  * HWRM Functions (sent to HWRM)
 156  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
 157  * HWRM command times out, or a negative error code if the HWRM
 158  * command was failed by the FW.
 159  */
 160
 161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
 162                                   uint32_t msg_len, bool use_kong_mb)
 163 {
 164         unsigned int i;
 165         struct input *req = msg;
 166         struct output *resp = bp->hwrm_cmd_resp_addr;
 167         uint32_t *data = msg;
 168         uint8_t *bar;
 169         uint8_t *valid;
 170         uint16_t max_req_len = bp->max_req_len;
 171         struct hwrm_short_input short_input = { 0 };
 172         uint16_t bar_offset = use_kong_mb ?
 173                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
 174         uint16_t mb_trigger_offset = use_kong_mb ?
 175                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 176         struct bnxt_cp_ring_info *cpr = NULL;
 177         bool is_rx = false;
 178         bool is_tx = false;
 179         uint32_t timeout;
 180
 181         /* Do not send HWRM commands to firmware in error state */
 182         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 183                 return 0;
 184
 185         timeout = bp->hwrm_cmd_timeout;
 186
 187         /* Update the message length for backing store config for new FW. */
 188         if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
 189             rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
 190                 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
 191
 192         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 193             msg_len > bp->max_req_len) {
 194                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 195
 196                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 197                 memcpy(short_cmd_req, req, msg_len);
 198
 199                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 200                 short_input.signature = rte_cpu_to_le_16(
 201                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 202                 short_input.size = rte_cpu_to_le_16(msg_len);
 203                 short_input.req_addr =
 204                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 205
 206                 data = (uint32_t *)&short_input;
 207                 msg_len = sizeof(short_input);
 208
 209                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 210         }
 211
 212         /* Write request msg to hwrm channel */
 213         for (i = 0; i < msg_len; i += 4) {
 214                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 215                 rte_write32(*data, bar);
 216                 data++;
 217         }
 218
 219         /* Zero the rest of the request space */
 220         for (; i < max_req_len; i += 4) {
 221                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 222                 rte_write32(0, bar);
 223         }
 224
 225         /* Ring channel doorbell */
 226         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 227         rte_write32(1, bar);
 228         /*
 229          * Make sure the channel doorbell ring command complete before
 230          * reading the response to avoid getting stale or invalid
 231          * responses.
 232          */
 233         rte_io_mb();
 234
 235         /* Check ring flush is done.
 236          * This is valid only for Tx and Rx rings (including AGG rings).
 237          * The Tx and Rx rings should be freed once the HW confirms all
 238          * the internal buffers and BDs associated with the rings are
 239          * consumed and the corresponding DMA is handled.
 240          */
 241         if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
 242                 /* Check if the TxCQ matches. If that fails check if RxCQ
 243                  * matches. And if neither match, is_rx = false, is_tx = false.
 244                  */
 245                 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 246                                                HWRM_RING_FREE_INPUT_RING_TYPE_TX);
 247                 if (cpr == NULL) {
 248                         /* Not a TxCQ. Check if the RxCQ matches. */
 249                         cpr =
 250                         bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
 251                                                  HWRM_RING_FREE_INPUT_RING_TYPE_RX);
 252                         if (cpr != NULL)
 253                                 is_rx = true;
 254                 } else {
 255                         is_tx = true;
 256                 }
 257         }
 258
 259         /* Poll for the valid bit */
 260         for (i = 0; i < timeout; i++) {
 261                 int done;
 262
 263                 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
 264                                                i == timeout - 1);
 265                 /* Sanity check on the resp->resp_len */
 266                 rte_io_rmb();
 267                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 268                         /* Last byte of resp contains the valid key */
 269                         valid = (uint8_t *)resp + resp->resp_len - 1;
 270                         if (*valid == HWRM_RESP_VALID_KEY && done)
 271                                 break;
 272                 }
 273                 rte_delay_us(1);
 274         }
 275
 276         if (i >= timeout) {
 277                 /* Suppress VER_GET timeout messages during reset recovery */
 278                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 279                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 280                         return -ETIMEDOUT;
 281
 282                 PMD_DRV_LOG(ERR,
 283                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 284                             req->req_type, req->seq_id);
 285                 return -ETIMEDOUT;
 286         }
 287         return 0;
 288 }
 289
 290 /*
 291  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 292  * spinlock, and does initial processing.
 293  *
 294  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 295  * releases the spinlock only if it returns. If the regular int return codes
 296  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 297  * directly, rather it should be copied and modified to suit the function.
 298  *
 299  * HWRM_UNLOCK() must be called after all response processing is completed.
 300  */
 301 #define HWRM_PREP(req, type, kong) do { \
 302         rte_spinlock_lock(&bp->hwrm_lock); \
 303         if (bp->hwrm_cmd_resp_addr == NULL) { \
 304                 rte_spinlock_unlock(&bp->hwrm_lock); \
 305                 return -EACCES; \
 306         } \
 307         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 308         (req)->req_type = rte_cpu_to_le_16(type); \
 309         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 310         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 311                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 312         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 313         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 314 } while (0)
 315
 316 #define HWRM_CHECK_RESULT_SILENT() do {\
 317         if (rc) { \
 318                 rte_spinlock_unlock(&bp->hwrm_lock); \
 319                 return rc; \
 320         } \
 321         if (resp->error_code) { \
 322                 rc = rte_le_to_cpu_16(resp->error_code); \
 323                 rte_spinlock_unlock(&bp->hwrm_lock); \
 324                 return rc; \
 325         } \
 326 } while (0)
 327
 328 #define HWRM_CHECK_RESULT() do {\
 329         if (rc) { \
 330                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 331                 rte_spinlock_unlock(&bp->hwrm_lock); \
 332                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 333                         rc = -EACCES; \
 334                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 335                         rc = -ENOSPC; \
 336                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 337                         rc = -EINVAL; \
 338                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 339                         rc = -ENOTSUP; \
 340                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 341                         rc = -EAGAIN; \
 342                 else if (rc > 0) \
 343                         rc = -EIO; \
 344                 return rc; \
 345         } \
 346         if (resp->error_code) { \
 347                 rc = rte_le_to_cpu_16(resp->error_code); \
 348                 if (resp->resp_len >= 16) { \
 349                         struct hwrm_err_output *tmp_hwrm_err_op = \
 350                                                 (void *)resp; \
 351                         PMD_DRV_LOG(ERR, \
 352                                 "error %d:%d:%08x:%04x\n", \
 353                                 rc, tmp_hwrm_err_op->cmd_err, \
 354                                 rte_le_to_cpu_32(\
 355                                         tmp_hwrm_err_op->opaque_0), \
 356                                 rte_le_to_cpu_16(\
 357                                         tmp_hwrm_err_op->opaque_1)); \
 358                 } else { \
 359                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 360                 } \
 361                 rte_spinlock_unlock(&bp->hwrm_lock); \
 362                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 363                         rc = -EACCES; \
 364                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 365                         rc = -ENOSPC; \
 366                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 367                         rc = -EINVAL; \
 368                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 369                         rc = -ENOTSUP; \
 370                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 371                         rc = -EAGAIN; \
 372                 else if (rc > 0) \
 373                         rc = -EIO; \
 374                 return rc; \
 375         } \
 376 } while (0)
 377
 378 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 379
 380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 381                                 bool use_kong_mb,
 382                                 uint16_t msg_type,
 383                                 void *msg,
 384                                 uint32_t msg_len,
 385                                 void *resp_msg,
 386                                 uint32_t resp_len)
 387 {
 388         int rc = 0;
 389         bool mailbox = BNXT_USE_CHIMP_MB;
 390         struct input *req = msg;
 391         struct output *resp = bp->hwrm_cmd_resp_addr;
 392
 393         if (use_kong_mb)
 394                 mailbox = BNXT_USE_KONG(bp);
 395
 396         HWRM_PREP(req, msg_type, mailbox);
 397
 398         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 399
 400         HWRM_CHECK_RESULT();
 401
 402         if (resp_msg)
 403                 memcpy(resp_msg, resp, resp_len);
 404
 405         HWRM_UNLOCK();
 406
 407         return rc;
 408 }
 409
 410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 411                                   bool use_kong_mb,
 412                                   uint16_t tf_type,
 413                                   uint16_t tf_subtype,
 414                                   uint32_t *tf_response_code,
 415                                   void *msg,
 416                                   uint32_t msg_len,
 417                                   void *response,
 418                                   uint32_t response_len)
 419 {
 420         int rc = 0;
 421         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 422         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 423         bool mailbox = BNXT_USE_CHIMP_MB;
 424
 425         if (msg_len > sizeof(req.tf_req))
 426                 return -ENOMEM;
 427
 428         if (use_kong_mb)
 429                 mailbox = BNXT_USE_KONG(bp);
 430
 431         HWRM_PREP(&req, HWRM_TF, mailbox);
 432         /* Build request using the user supplied request payload.
 433          * TLV request size is checked at build time against HWRM
 434          * request max size, thus no checking required.
 435          */
 436         req.tf_type = tf_type;
 437         req.tf_subtype = tf_subtype;
 438         memcpy(req.tf_req, msg, msg_len);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 441         HWRM_CHECK_RESULT();
 442
 443         /* Copy the resp to user provided response buffer */
 444         if (response != NULL)
 445                 /* Post process response data. We need to copy only
 446                  * the 'payload' as the HWRM data structure really is
 447                  * HWRM header + msg header + payload and the TFLIB
 448                  * only provided a payload place holder.
 449                  */
 450                 if (response_len != 0) {
 451                         memcpy(response,
 452                                resp->tf_resp,
 453                                response_len);
 454                 }
 455
 456         /* Extract the internal tflib response code */
 457         *tf_response_code = resp->tf_resp_code;
 458         HWRM_UNLOCK();
 459
 460         return rc;
 461 }
 462
 463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 464 {
 465         int rc = 0;
 466         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 467         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 468
 469         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 470         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 471         req.mask = 0;
 472
 473         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 474
 475         HWRM_CHECK_RESULT();
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 482                                  struct bnxt_vnic_info *vnic,
 483                                  uint16_t vlan_count,
 484                                  struct bnxt_vlan_table_entry *vlan_table)
 485 {
 486         int rc = 0;
 487         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 488         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 489         uint32_t mask = 0;
 490
 491         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 492                 return rc;
 493
 494         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 496
 497         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 498                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 499         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 500                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 501
 502         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 503                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 504
 505         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 506                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 507         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 508                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 509                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 510                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 511         }
 512         if (vlan_table) {
 513                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 514                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 515                 req.vlan_tag_tbl_addr =
 516                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 517                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 518         }
 519         req.mask = rte_cpu_to_le_32(mask);
 520
 521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 522
 523         HWRM_CHECK_RESULT();
 524         HWRM_UNLOCK();
 525
 526         return rc;
 527 }
 528
 529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 530                         uint16_t vlan_count,
 531                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 532 {
 533         int rc = 0;
 534         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 535         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 536                                                 bp->hwrm_cmd_resp_addr;
 537
 538         /*
 539          * Older HWRM versions did not support this command, and the set_rx_mask
 540          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 541          * removed from set_rx_mask call, and this command was added.
 542          *
 543          * This command is also present from 1.7.8.11 and higher,
 544          * as well as 1.7.8.0
 545          */
 546         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 547                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 548                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 549                                         (11)))
 550                                 return 0;
 551                 }
 552         }
 553         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 554         req.fid = rte_cpu_to_le_16(fid);
 555
 556         req.vlan_tag_mask_tbl_addr =
 557                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 558         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 559
 560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 561
 562         HWRM_CHECK_RESULT();
 563         HWRM_UNLOCK();
 564
 565         return rc;
 566 }
 567
 568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 569                              struct bnxt_filter_info *filter)
 570 {
 571         int rc = 0;
 572         struct bnxt_filter_info *l2_filter = filter;
 573         struct bnxt_vnic_info *vnic = NULL;
 574         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 575         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         if (filter->fw_l2_filter_id == UINT64_MAX)
 578                 return 0;
 579
 580         if (filter->matching_l2_fltr_ptr)
 581                 l2_filter = filter->matching_l2_fltr_ptr;
 582
 583         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 584                     filter, l2_filter, l2_filter->l2_ref_cnt);
 585
 586         if (l2_filter->l2_ref_cnt == 0)
 587                 return 0;
 588
 589         if (l2_filter->l2_ref_cnt > 0)
 590                 l2_filter->l2_ref_cnt--;
 591
 592         if (l2_filter->l2_ref_cnt > 0)
 593                 return 0;
 594
 595         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 596
 597         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 598
 599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 600
 601         HWRM_CHECK_RESULT();
 602         HWRM_UNLOCK();
 603
 604         filter->fw_l2_filter_id = UINT64_MAX;
 605         if (l2_filter->l2_ref_cnt == 0) {
 606                 vnic = l2_filter->vnic;
 607                 if (vnic) {
 608                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 609                                       bnxt_filter_info, next);
 610                         bnxt_free_filter(bp, l2_filter);
 611                 }
 612         }
 613
 614         return 0;
 615 }
 616
 617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 618                          uint16_t dst_id,
 619                          struct bnxt_filter_info *filter)
 620 {
 621         int rc = 0;
 622         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 623         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 624         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 625         const struct rte_eth_vmdq_rx_conf *conf =
 626                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 627         uint32_t enables = 0;
 628         uint16_t j = dst_id - 1;
 629
 630         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 631         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 632             conf->pool_map[j].pools & (1UL << j)) {
 633                 PMD_DRV_LOG(DEBUG,
 634                         "Add vlan %u to vmdq pool %u\n",
 635                         conf->pool_map[j].vlan_id, j);
 636
 637                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 638                 filter->enables |=
 639                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 640                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 641         }
 642
 643         if (filter->fw_l2_filter_id != UINT64_MAX)
 644                 bnxt_hwrm_clear_l2_filter(bp, filter);
 645
 646         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 647
 648         /* PMD does not support XDP and RoCE */
 649         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
 650                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
 651         req.flags = rte_cpu_to_le_32(filter->flags);
 652
 653         enables = filter->enables |
 654               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 655         req.dst_id = rte_cpu_to_le_16(dst_id);
 656
 657         if (enables &
 658             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 659                 memcpy(req.l2_addr, filter->l2_addr,
 660                        RTE_ETHER_ADDR_LEN);
 661         if (enables &
 662             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 663                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 664                        RTE_ETHER_ADDR_LEN);
 665         if (enables &
 666             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 667                 req.l2_ovlan = filter->l2_ovlan;
 668         if (enables &
 669             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 670                 req.l2_ivlan = filter->l2_ivlan;
 671         if (enables &
 672             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 673                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 674         if (enables &
 675             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 676                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 677         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 678                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 679         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 680                 req.src_type = filter->src_type;
 681         if (filter->pri_hint) {
 682                 req.pri_hint = filter->pri_hint;
 683                 req.l2_filter_id_hint =
 684                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 685         }
 686
 687         req.enables = rte_cpu_to_le_32(enables);
 688
 689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 690
 691         HWRM_CHECK_RESULT();
 692
 693         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 694         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 695         HWRM_UNLOCK();
 696
 697         filter->l2_ref_cnt++;
 698
 699         return rc;
 700 }
 701
 702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 703 {
 704         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 705         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 706         uint32_t flags = 0;
 707         int rc;
 708
 709         if (!ptp)
 710                 return 0;
 711
 712         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 713
 714         if (ptp->rx_filter)
 715                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 716         else
 717                 flags |=
 718                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 719         if (ptp->tx_tstamp_en)
 720                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 721         else
 722                 flags |=
 723                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 724         req.flags = rte_cpu_to_le_32(flags);
 725         req.enables = rte_cpu_to_le_32
 726                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 727         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 730         HWRM_UNLOCK();
 731
 732         return rc;
 733 }
 734
 735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 736 {
 737         int rc = 0;
 738         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 739         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 740         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 741
 742         if (ptp)
 743                 return 0;
 744
 745         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 746
 747         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 748
 749         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 750
 751         HWRM_CHECK_RESULT();
 752
 753         if (!BNXT_CHIP_P5(bp) &&
 754             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 755                 return 0;
 756
 757         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 758                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 759
 760         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 761         if (!ptp)
 762                 return -ENOMEM;
 763
 764         if (!BNXT_CHIP_P5(bp)) {
 765                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 766                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 767                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 768                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 769                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 770                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 771                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 772                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 773                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 774                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 775                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 776                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 777                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 778                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 779                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 780                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 781                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 782                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 783         }
 784
 785         ptp->bp = bp;
 786         bp->ptp_cfg = ptp;
 787
 788         return 0;
 789 }
 790
 791 void bnxt_free_vf_info(struct bnxt *bp)
 792 {
 793         int i;
 794
 795         if (bp->pf == NULL)
 796                 return;
 797
 798         if (bp->pf->vf_info == NULL)
 799                 return;
 800
 801         for (i = 0; i < bp->pf->max_vfs; i++) {
 802                 rte_free(bp->pf->vf_info[i].vlan_table);
 803                 bp->pf->vf_info[i].vlan_table = NULL;
 804                 rte_free(bp->pf->vf_info[i].vlan_as_table);
 805                 bp->pf->vf_info[i].vlan_as_table = NULL;
 806         }
 807         rte_free(bp->pf->vf_info);
 808         bp->pf->vf_info = NULL;
 809 }
 810
 811 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
 812 {
 813         struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
 814         int i;
 815
 816         if (vf_info)
 817                 bnxt_free_vf_info(bp);
 818
 819         vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
 820         if (vf_info == NULL) {
 821                 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
 822                 return -ENOMEM;
 823         }
 824
 825         bp->pf->max_vfs = max_vfs;
 826         for (i = 0; i < max_vfs; i++) {
 827                 vf_info[i].fid = bp->pf->first_vf_id + i;
 828                 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
 829                                                     getpagesize(), getpagesize());
 830                 if (vf_info[i].vlan_table == NULL) {
 831                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
 832                         goto err;
 833                 }
 834                 rte_mem_lock_page(vf_info[i].vlan_table);
 835
 836                 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
 837                                                        getpagesize(), getpagesize());
 838                 if (vf_info[i].vlan_as_table == NULL) {
 839                         PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
 840                         goto err;
 841                 }
 842                 rte_mem_lock_page(vf_info[i].vlan_as_table);
 843
 844                 STAILQ_INIT(&vf_info[i].filter);
 845         }
 846
 847         bp->pf->vf_info = vf_info;
 848
 849         return 0;
 850 err:
 851         bnxt_free_vf_info(bp);
 852         return -ENOMEM;
 853 }
 854
 855 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 856 {
 857         int rc = 0;
 858         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 859         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 860         uint16_t new_max_vfs;
 861         uint32_t flags;
 862
 863         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 864
 865         req.fid = rte_cpu_to_le_16(0xffff);
 866
 867         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 868
 869         HWRM_CHECK_RESULT();
 870
 871         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 872         flags = rte_le_to_cpu_32(resp->flags);
 873         if (BNXT_PF(bp)) {
 874                 bp->pf->port_id = resp->port_id;
 875                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 876                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 877                 new_max_vfs = bp->pdev->max_vfs;
 878                 if (new_max_vfs != bp->pf->max_vfs) {
 879                         rc = bnxt_alloc_vf_info(bp, new_max_vfs);
 880                         if (rc)
 881                                 goto unlock;
 882                 }
 883         }
 884
 885         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 886         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 887                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 888                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 889         } else {
 890                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 891         }
 892         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 893         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 894         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 895         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 896         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 897         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 898         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 899         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
 900                 bp->max_l2_ctx += bp->max_rx_em_flows;
 901         /* TODO: For now, do not support VMDq/RFS on VFs. */
 902         if (BNXT_PF(bp)) {
 903                 if (bp->pf->max_vfs)
 904                         bp->max_vnics = 1;
 905                 else
 906                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 907         } else {
 908                 bp->max_vnics = 1;
 909         }
 910         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 911                     bp->max_l2_ctx, bp->max_vnics);
 912         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 913         if (BNXT_PF(bp)) {
 914                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 915                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 916                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 917                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 918                         HWRM_UNLOCK();
 919                         bnxt_hwrm_ptp_qcfg(bp);
 920                 }
 921         }
 922
 923         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 924                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 925
 926         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 927                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 928                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 929         }
 930
 931         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 932                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 933
 934         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 935                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 936
 937         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
 938                 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
 939
 940 unlock:
 941         HWRM_UNLOCK();
 942
 943         return rc;
 944 }
 945
 946 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 947 {
 948         int rc;
 949
 950         rc = __bnxt_hwrm_func_qcaps(bp);
 951         if (rc == -ENOMEM)
 952                 return rc;
 953
 954         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 955                 rc = bnxt_alloc_ctx_mem(bp);
 956                 if (rc)
 957                         return rc;
 958
 959                 /* On older FW,
 960                  * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 961                  * But the error can be ignored. Return success.
 962                  */
 963                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 964                 if (!rc)
 965                         bp->flags |= BNXT_FLAG_NEW_RM;
 966         }
 967
 968         return 0;
 969 }
 970
 971 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 972 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 973 {
 974         int rc = 0;
 975         uint32_t flags;
 976         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 977         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 978
 979         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 980
 981         req.target_id = rte_cpu_to_le_16(0xffff);
 982
 983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 984
 985         HWRM_CHECK_RESULT();
 986
 987         flags = rte_le_to_cpu_32(resp->flags);
 988
 989         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 990                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 991                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 992         }
 993
 994         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
 995                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
 996
 997         if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
 998                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
 999
1000         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1001
1002         HWRM_UNLOCK();
1003
1004         return rc;
1005 }
1006
1007 int bnxt_hwrm_func_reset(struct bnxt *bp)
1008 {
1009         int rc = 0;
1010         struct hwrm_func_reset_input req = {.req_type = 0 };
1011         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1012
1013         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1014
1015         req.enables = rte_cpu_to_le_32(0);
1016
1017         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1018
1019         HWRM_CHECK_RESULT();
1020         HWRM_UNLOCK();
1021
1022         return rc;
1023 }
1024
1025 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1026 {
1027         int rc;
1028         uint32_t flags = 0;
1029         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1030         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1031
1032         if (bp->flags & BNXT_FLAG_REGISTERED)
1033                 return 0;
1034
1035         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1036                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1037         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1038                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1039
1040         /* PFs and trusted VFs should indicate the support of the
1041          * Master capability on non Stingray platform
1042          */
1043         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1044                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1045
1046         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1047         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1048                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1049         req.ver_maj = RTE_VER_YEAR;
1050         req.ver_min = RTE_VER_MONTH;
1051         req.ver_upd = RTE_VER_MINOR;
1052
1053         if (BNXT_PF(bp)) {
1054                 req.enables |= rte_cpu_to_le_32(
1055                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1056                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1057                        RTE_MIN(sizeof(req.vf_req_fwd),
1058                                sizeof(bp->pf->vf_req_fwd)));
1059         }
1060
1061         req.flags = rte_cpu_to_le_32(flags);
1062
1063         req.async_event_fwd[0] |=
1064                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1065                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1066                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1067                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1068                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1069         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1070                 req.async_event_fwd[0] |=
1071                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1072         req.async_event_fwd[1] |=
1073                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1074                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1075         if (BNXT_PF(bp))
1076                 req.async_event_fwd[1] |=
1077                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1078
1079         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1080                 req.async_event_fwd[1] |=
1081                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1082
1083         req.async_event_fwd[2] |=
1084                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST);
1085
1086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1087
1088         HWRM_CHECK_RESULT();
1089
1090         flags = rte_le_to_cpu_32(resp->flags);
1091         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1092                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1093
1094         HWRM_UNLOCK();
1095
1096         bp->flags |= BNXT_FLAG_REGISTERED;
1097
1098         return rc;
1099 }
1100
1101 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1102 {
1103         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1104                 return 0;
1105
1106         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1107 }
1108
1109 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1110 {
1111         int rc;
1112         uint32_t flags = 0;
1113         uint32_t enables;
1114         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1115         struct hwrm_func_vf_cfg_input req = {0};
1116
1117         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1118
1119         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
1120                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
1121                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
1122                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1123                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1124
1125         if (BNXT_HAS_RING_GRPS(bp)) {
1126                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1127                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1128         }
1129
1130         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1131         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1132                                             AGG_RING_MULTIPLIER);
1133         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1134         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1135                                               bp->tx_nr_rings +
1136                                               BNXT_NUM_ASYNC_CPR(bp));
1137         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1138         if (bp->vf_resv_strategy ==
1139             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1140                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1141                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1142                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1143                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1144                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1145                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1146         } else if (bp->vf_resv_strategy ==
1147                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1148                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1149                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1150         }
1151
1152         if (test)
1153                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1154                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1155                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1156                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1157                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1158                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1159
1160         if (test && BNXT_HAS_RING_GRPS(bp))
1161                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1162
1163         req.flags = rte_cpu_to_le_32(flags);
1164         req.enables |= rte_cpu_to_le_32(enables);
1165
1166         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1167
1168         if (test)
1169                 HWRM_CHECK_RESULT_SILENT();
1170         else
1171                 HWRM_CHECK_RESULT();
1172
1173         HWRM_UNLOCK();
1174         return rc;
1175 }
1176
1177 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1178 {
1179         int rc;
1180         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1181         struct hwrm_func_resource_qcaps_input req = {0};
1182
1183         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1184         req.fid = rte_cpu_to_le_16(0xffff);
1185
1186         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1187
1188         HWRM_CHECK_RESULT_SILENT();
1189
1190         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1191         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1192         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1193         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1194         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1195         /* func_resource_qcaps does not return max_rx_em_flows.
1196          * So use the value provided by func_qcaps.
1197          */
1198         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1199         if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1200                 bp->max_l2_ctx += bp->max_rx_em_flows;
1201         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1202         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1203         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1204         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1205         if (bp->vf_resv_strategy >
1206             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1207                 bp->vf_resv_strategy =
1208                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1209
1210         HWRM_UNLOCK();
1211         return rc;
1212 }
1213
1214 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1215 {
1216         int rc = 0;
1217         struct hwrm_ver_get_input req = {.req_type = 0 };
1218         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1219         uint32_t fw_version;
1220         uint16_t max_resp_len;
1221         char type[RTE_MEMZONE_NAMESIZE];
1222         uint32_t dev_caps_cfg;
1223
1224         bp->max_req_len = HWRM_MAX_REQ_LEN;
1225         bp->hwrm_cmd_timeout = timeout;
1226         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1227
1228         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1229         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1230         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1231
1232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1233
1234         if (bp->flags & BNXT_FLAG_FW_RESET)
1235                 HWRM_CHECK_RESULT_SILENT();
1236         else
1237                 HWRM_CHECK_RESULT();
1238
1239         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1240                 rc = -EAGAIN;
1241                 goto error;
1242         }
1243
1244         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1245                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1246                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1247                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1248                 resp->hwrm_fw_rsvd_8b);
1249         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1250                      (resp->hwrm_fw_min_8b << 16) |
1251                      (resp->hwrm_fw_bld_8b << 8) |
1252                      resp->hwrm_fw_rsvd_8b;
1253         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1254                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1255
1256         fw_version = resp->hwrm_intf_maj_8b << 16;
1257         fw_version |= resp->hwrm_intf_min_8b << 8;
1258         fw_version |= resp->hwrm_intf_upd_8b;
1259         bp->hwrm_spec_code = fw_version;
1260
1261         /* def_req_timeout value is in milliseconds */
1262         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1263         /* convert timeout to usec */
1264         bp->hwrm_cmd_timeout *= 1000;
1265         if (!bp->hwrm_cmd_timeout)
1266                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1267
1268         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1269                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1270                 rc = -EINVAL;
1271                 goto error;
1272         }
1273
1274         if (bp->max_req_len > resp->max_req_win_len) {
1275                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1276                 rc = -EINVAL;
1277                 goto error;
1278         }
1279
1280         bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1281
1282         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1283         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1284         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1285                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1286
1287         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1288         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1289
1290         RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1291         bp->max_resp_len = max_resp_len;
1292
1293         if ((dev_caps_cfg &
1294                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1295             (dev_caps_cfg &
1296              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1297                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1298                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1299         }
1300
1301         if (((dev_caps_cfg &
1302               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1303              (dev_caps_cfg &
1304               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1305             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1306                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1307                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1308                         bp->pdev->addr.devid, bp->pdev->addr.function);
1309
1310                 rte_free(bp->hwrm_short_cmd_req_addr);
1311
1312                 bp->hwrm_short_cmd_req_addr =
1313                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1314                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1315                         rc = -ENOMEM;
1316                         goto error;
1317                 }
1318                 bp->hwrm_short_cmd_req_dma_addr =
1319                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1320                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1321                         rte_free(bp->hwrm_short_cmd_req_addr);
1322                         PMD_DRV_LOG(ERR,
1323                                 "Unable to map buffer to physical memory.\n");
1324                         rc = -ENOMEM;
1325                         goto error;
1326                 }
1327         }
1328         if (dev_caps_cfg &
1329             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1330                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1331                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1332         }
1333         if (dev_caps_cfg &
1334             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1335                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1336         if (dev_caps_cfg &
1337             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1338                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1339                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1340         }
1341
1342         if (dev_caps_cfg &
1343             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1344                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1345                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1346         }
1347
1348 error:
1349         HWRM_UNLOCK();
1350         return rc;
1351 }
1352
1353 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1354 {
1355         int rc;
1356         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1357         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1358
1359         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1360                 return 0;
1361
1362         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1363         req.flags = flags;
1364
1365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1366
1367         HWRM_CHECK_RESULT();
1368         HWRM_UNLOCK();
1369
1370         PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1371                     bp->eth_dev->data->port_id);
1372
1373         return rc;
1374 }
1375
1376 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1377 {
1378         int rc = 0;
1379         struct hwrm_port_phy_cfg_input req = {0};
1380         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1381         uint32_t enables = 0;
1382
1383         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1384
1385         if (conf->link_up) {
1386                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1387                 if (bp->link_info->auto_mode && conf->link_speed) {
1388                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1389                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1390                 }
1391
1392                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1393                 /*
1394                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1395                  * any auto mode, even "none".
1396                  */
1397                 if (!conf->link_speed) {
1398                         /* No speeds specified. Enable AutoNeg - all speeds */
1399                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1400                         req.auto_mode =
1401                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1402                 } else {
1403                         if (bp->link_info->link_signal_mode) {
1404                                 enables |=
1405                                 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1406                                 req.force_pam4_link_speed =
1407                                         rte_cpu_to_le_16(conf->link_speed);
1408                         } else {
1409                                 req.force_link_speed =
1410                                         rte_cpu_to_le_16(conf->link_speed);
1411                         }
1412                 }
1413                 /* AutoNeg - Advertise speeds specified. */
1414                 if (conf->auto_link_speed_mask &&
1415                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1416                         req.auto_mode =
1417                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1418                         req.auto_link_speed_mask =
1419                                 conf->auto_link_speed_mask;
1420                         if (conf->auto_pam4_link_speeds) {
1421                                 enables |=
1422                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1423                                 req.auto_link_pam4_speed_mask =
1424                                         conf->auto_pam4_link_speeds;
1425                         } else {
1426                                 enables |=
1427                                 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1428                         }
1429                 }
1430                 if (conf->auto_link_speed &&
1431                 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1432                         enables |=
1433                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1434
1435                 req.auto_duplex = conf->duplex;
1436                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1437                 req.auto_pause = conf->auto_pause;
1438                 req.force_pause = conf->force_pause;
1439                 /* Set force_pause if there is no auto or if there is a force */
1440                 if (req.auto_pause && !req.force_pause)
1441                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1442                 else
1443                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1444
1445                 req.enables = rte_cpu_to_le_32(enables);
1446         } else {
1447                 req.flags =
1448                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1449                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1450         }
1451
1452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1453
1454         HWRM_CHECK_RESULT();
1455         HWRM_UNLOCK();
1456
1457         return rc;
1458 }
1459
1460 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1461                                    struct bnxt_link_info *link_info)
1462 {
1463         int rc = 0;
1464         struct hwrm_port_phy_qcfg_input req = {0};
1465         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1466
1467         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1468
1469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1470
1471         HWRM_CHECK_RESULT();
1472
1473         link_info->phy_link_status = resp->link;
1474         link_info->link_up =
1475                 (link_info->phy_link_status ==
1476                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1477         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1478         link_info->duplex = resp->duplex_cfg;
1479         link_info->pause = resp->pause;
1480         link_info->auto_pause = resp->auto_pause;
1481         link_info->force_pause = resp->force_pause;
1482         link_info->auto_mode = resp->auto_mode;
1483         link_info->phy_type = resp->phy_type;
1484         link_info->media_type = resp->media_type;
1485
1486         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1487         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1488         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1489         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1490         link_info->phy_ver[0] = resp->phy_maj;
1491         link_info->phy_ver[1] = resp->phy_min;
1492         link_info->phy_ver[2] = resp->phy_bld;
1493         link_info->link_signal_mode =
1494                 rte_le_to_cpu_16(resp->active_fec_signal_mode);
1495         link_info->force_pam4_link_speed =
1496                         rte_le_to_cpu_16(resp->force_pam4_link_speed);
1497         link_info->support_pam4_speeds =
1498                         rte_le_to_cpu_16(resp->support_pam4_speeds);
1499         link_info->auto_pam4_link_speeds =
1500                         rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1501         HWRM_UNLOCK();
1502
1503         PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1504                     link_info->link_speed, link_info->auto_mode,
1505                     link_info->auto_link_speed, link_info->auto_link_speed_mask,
1506                     link_info->support_speeds, link_info->force_link_speed);
1507         PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1508                     link_info->link_signal_mode,
1509                     link_info->auto_pam4_link_speeds,
1510                     link_info->support_pam4_speeds,
1511                     link_info->force_pam4_link_speed);
1512         return rc;
1513 }
1514
1515 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1516 {
1517         int rc = 0;
1518         struct hwrm_port_phy_qcaps_input req = {0};
1519         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1520         struct bnxt_link_info *link_info = bp->link_info;
1521
1522         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1523                 return 0;
1524
1525         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1526
1527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1528
1529         HWRM_CHECK_RESULT_SILENT();
1530
1531         bp->port_cnt = resp->port_cnt;
1532         if (resp->supported_speeds_auto_mode)
1533                 link_info->support_auto_speeds =
1534                         rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1535         if (resp->supported_pam4_speeds_auto_mode)
1536                 link_info->support_pam4_auto_speeds =
1537                         rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1538
1539         HWRM_UNLOCK();
1540
1541         return 0;
1542 }
1543
1544 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1545 {
1546         int i = 0;
1547
1548         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1549                 if (bp->tx_cos_queue[i].profile ==
1550                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1551                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1552                         return true;
1553                 }
1554         }
1555         return false;
1556 }
1557
1558 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1559 {
1560         int i = 0;
1561
1562         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1563                 if (bp->tx_cos_queue[i].profile !=
1564                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1565                     bp->tx_cos_queue[i].id !=
1566                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1567                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1568                         break;
1569                 }
1570         }
1571 }
1572
1573 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1574 {
1575         int rc = 0;
1576         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1577         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1578         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1579         int i;
1580
1581 get_rx_info:
1582         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1583
1584         req.flags = rte_cpu_to_le_32(dir);
1585         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1586         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1587             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1588                 req.drv_qmap_cap =
1589                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1591
1592         HWRM_CHECK_RESULT();
1593
1594         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1595                 GET_TX_QUEUE_INFO(0);
1596                 GET_TX_QUEUE_INFO(1);
1597                 GET_TX_QUEUE_INFO(2);
1598                 GET_TX_QUEUE_INFO(3);
1599                 GET_TX_QUEUE_INFO(4);
1600                 GET_TX_QUEUE_INFO(5);
1601                 GET_TX_QUEUE_INFO(6);
1602                 GET_TX_QUEUE_INFO(7);
1603         } else  {
1604                 GET_RX_QUEUE_INFO(0);
1605                 GET_RX_QUEUE_INFO(1);
1606                 GET_RX_QUEUE_INFO(2);
1607                 GET_RX_QUEUE_INFO(3);
1608                 GET_RX_QUEUE_INFO(4);
1609                 GET_RX_QUEUE_INFO(5);
1610                 GET_RX_QUEUE_INFO(6);
1611                 GET_RX_QUEUE_INFO(7);
1612         }
1613
1614         HWRM_UNLOCK();
1615
1616         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1617                 goto done;
1618
1619         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1620                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1621         } else {
1622                 int j;
1623
1624                 /* iterate and find the COSq profile to use for Tx */
1625                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1626                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1627                                 if (bp->tx_cos_queue[i].id != 0xff)
1628                                         bp->tx_cosq_id[j++] =
1629                                                 bp->tx_cos_queue[i].id;
1630                         }
1631                 } else {
1632                         /* When CoS classification is disabled, for normal NIC
1633                          * operations, ideally we should look to use LOSSY.
1634                          * If not found, fallback to the first valid profile
1635                          */
1636                         if (!bnxt_find_lossy_profile(bp))
1637                                 bnxt_find_first_valid_profile(bp);
1638
1639                 }
1640         }
1641
1642         bp->max_tc = resp->max_configurable_queues;
1643         bp->max_lltc = resp->max_configurable_lossless_queues;
1644         if (bp->max_tc > BNXT_MAX_QUEUE)
1645                 bp->max_tc = BNXT_MAX_QUEUE;
1646         bp->max_q = bp->max_tc;
1647
1648         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1649                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1650                 goto get_rx_info;
1651         }
1652
1653 done:
1654         return rc;
1655 }
1656
1657 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1658                          struct bnxt_ring *ring,
1659                          uint32_t ring_type, uint32_t map_index,
1660                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1661                          uint16_t tx_cosq_id)
1662 {
1663         int rc = 0;
1664         uint32_t enables = 0;
1665         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1666         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1667         struct rte_mempool *mb_pool;
1668         uint16_t rx_buf_size;
1669
1670         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1671
1672         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1673         req.fbo = rte_cpu_to_le_32(0);
1674         /* Association of ring index with doorbell index */
1675         req.logical_id = rte_cpu_to_le_16(map_index);
1676         req.length = rte_cpu_to_le_32(ring->ring_size);
1677
1678         switch (ring_type) {
1679         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1680                 req.ring_type = ring_type;
1681                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1682                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1683                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1684                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1685                         enables |=
1686                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1687                 break;
1688         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1689                 req.ring_type = ring_type;
1690                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1691                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1692                 if (BNXT_CHIP_P5(bp)) {
1693                         mb_pool = bp->rx_queues[0]->mb_pool;
1694                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1695                                       RTE_PKTMBUF_HEADROOM;
1696                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1697                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1698                         enables |=
1699                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1700                 }
1701                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1702                         enables |=
1703                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1704                 break;
1705         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1706                 req.ring_type = ring_type;
1707                 if (BNXT_HAS_NQ(bp)) {
1708                         /* Association of cp ring with nq */
1709                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1710                         enables |=
1711                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1712                 }
1713                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1714                 break;
1715         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1716                 req.ring_type = ring_type;
1717                 req.page_size = BNXT_PAGE_SHFT;
1718                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1719                 break;
1720         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1721                 req.ring_type = ring_type;
1722                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1723
1724                 mb_pool = bp->rx_queues[0]->mb_pool;
1725                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1726                               RTE_PKTMBUF_HEADROOM;
1727                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1728                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1729
1730                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1731                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1732                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1733                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1734                 break;
1735         default:
1736                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1737                         ring_type);
1738                 HWRM_UNLOCK();
1739                 return -EINVAL;
1740         }
1741         req.enables = rte_cpu_to_le_32(enables);
1742
1743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1744
1745         if (rc || resp->error_code) {
1746                 if (rc == 0 && resp->error_code)
1747                         rc = rte_le_to_cpu_16(resp->error_code);
1748                 switch (ring_type) {
1749                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1750                         PMD_DRV_LOG(ERR,
1751                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1752                         HWRM_UNLOCK();
1753                         return rc;
1754                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1755                         PMD_DRV_LOG(ERR,
1756                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1757                         HWRM_UNLOCK();
1758                         return rc;
1759                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1760                         PMD_DRV_LOG(ERR,
1761                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1762                                     rc);
1763                         HWRM_UNLOCK();
1764                         return rc;
1765                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1766                         PMD_DRV_LOG(ERR,
1767                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1768                         HWRM_UNLOCK();
1769                         return rc;
1770                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1771                         PMD_DRV_LOG(ERR,
1772                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1773                         HWRM_UNLOCK();
1774                         return rc;
1775                 default:
1776                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1777                         HWRM_UNLOCK();
1778                         return rc;
1779                 }
1780         }
1781
1782         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1783         HWRM_UNLOCK();
1784         return rc;
1785 }
1786
1787 int bnxt_hwrm_ring_free(struct bnxt *bp,
1788                         struct bnxt_ring *ring, uint32_t ring_type,
1789                         uint16_t cp_ring_id)
1790 {
1791         int rc;
1792         struct hwrm_ring_free_input req = {.req_type = 0 };
1793         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1794
1795         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1796
1797         req.ring_type = ring_type;
1798         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1799         req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1800
1801         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1802
1803         if (rc || resp->error_code) {
1804                 if (rc == 0 && resp->error_code)
1805                         rc = rte_le_to_cpu_16(resp->error_code);
1806                 HWRM_UNLOCK();
1807
1808                 switch (ring_type) {
1809                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1810                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1811                                 rc);
1812                         return rc;
1813                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1814                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1815                                 rc);
1816                         return rc;
1817                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1818                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1819                                 rc);
1820                         return rc;
1821                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1822                         PMD_DRV_LOG(ERR,
1823                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1824                         return rc;
1825                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1826                         PMD_DRV_LOG(ERR,
1827                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1828                         return rc;
1829                 default:
1830                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1831                         return rc;
1832                 }
1833         }
1834         HWRM_UNLOCK();
1835         return 0;
1836 }
1837
1838 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1839 {
1840         int rc = 0;
1841         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1842         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1843
1844         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1845
1846         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1847         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1848         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1849         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1850
1851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1852
1853         HWRM_CHECK_RESULT();
1854
1855         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1856
1857         HWRM_UNLOCK();
1858
1859         return rc;
1860 }
1861
1862 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1863 {
1864         int rc;
1865         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1866         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1867
1868         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1869
1870         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1871
1872         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1873
1874         HWRM_CHECK_RESULT();
1875         HWRM_UNLOCK();
1876
1877         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1878         return rc;
1879 }
1880
1881 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1882 {
1883         int rc = 0;
1884         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1885         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1886
1887         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1888                 return rc;
1889
1890         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1891
1892         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1893
1894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1895
1896         HWRM_CHECK_RESULT();
1897         HWRM_UNLOCK();
1898
1899         return rc;
1900 }
1901
1902 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1903                                 unsigned int idx __rte_unused)
1904 {
1905         int rc;
1906         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1907         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1908
1909         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1910
1911         req.update_period_ms = rte_cpu_to_le_32(0);
1912
1913         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1914
1915         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1916
1917         HWRM_CHECK_RESULT();
1918
1919         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1920
1921         HWRM_UNLOCK();
1922
1923         return rc;
1924 }
1925
1926 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1927                                 unsigned int idx __rte_unused)
1928 {
1929         int rc;
1930         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1931         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1932
1933         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1934
1935         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1936
1937         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1938
1939         HWRM_CHECK_RESULT();
1940         HWRM_UNLOCK();
1941
1942         return rc;
1943 }
1944
1945 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1946 {
1947         int rc = 0, i, j;
1948         struct hwrm_vnic_alloc_input req = { 0 };
1949         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1950
1951         if (!BNXT_HAS_RING_GRPS(bp))
1952                 goto skip_ring_grps;
1953
1954         /* map ring groups to this vnic */
1955         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1956                 vnic->start_grp_id, vnic->end_grp_id);
1957         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1958                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1959
1960         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1961         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1962         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1963         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1964
1965 skip_ring_grps:
1966         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1967         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1968
1969         if (vnic->func_default)
1970                 req.flags =
1971                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1973
1974         HWRM_CHECK_RESULT();
1975
1976         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1977         HWRM_UNLOCK();
1978         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1979         return rc;
1980 }
1981
1982 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1983                                         struct bnxt_vnic_info *vnic,
1984                                         struct bnxt_plcmodes_cfg *pmode)
1985 {
1986         int rc = 0;
1987         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1988         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1989
1990         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1991
1992         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993
1994         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1995
1996         HWRM_CHECK_RESULT();
1997
1998         pmode->flags = rte_le_to_cpu_32(resp->flags);
1999         /* dflt_vnic bit doesn't exist in the _cfg command */
2000         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2001         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2002         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2003         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2004
2005         HWRM_UNLOCK();
2006
2007         return rc;
2008 }
2009
2010 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2011                                        struct bnxt_vnic_info *vnic,
2012                                        struct bnxt_plcmodes_cfg *pmode)
2013 {
2014         int rc = 0;
2015         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2016         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2017
2018         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2019                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2020                 return rc;
2021         }
2022
2023         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2024
2025         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2026         req.flags = rte_cpu_to_le_32(pmode->flags);
2027         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2028         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2029         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2030         req.enables = rte_cpu_to_le_32(
2031             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2032             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2033             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2034         );
2035
2036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2037
2038         HWRM_CHECK_RESULT();
2039         HWRM_UNLOCK();
2040
2041         return rc;
2042 }
2043
2044 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2045 {
2046         int rc = 0;
2047         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2048         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2049         struct bnxt_plcmodes_cfg pmodes = { 0 };
2050         uint32_t ctx_enable_flag = 0;
2051         uint32_t enables = 0;
2052
2053         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2054                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2055                 return rc;
2056         }
2057
2058         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2059         if (rc)
2060                 return rc;
2061
2062         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2063
2064         if (BNXT_CHIP_P5(bp)) {
2065                 int dflt_rxq = vnic->start_grp_id;
2066                 struct bnxt_rx_ring_info *rxr;
2067                 struct bnxt_cp_ring_info *cpr;
2068                 struct bnxt_rx_queue *rxq;
2069                 int i;
2070
2071                 /*
2072                  * The first active receive ring is used as the VNIC
2073                  * default receive ring. If there are no active receive
2074                  * rings (all corresponding receive queues are stopped),
2075                  * the first receive ring is used.
2076                  */
2077                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2078                         rxq = bp->eth_dev->data->rx_queues[i];
2079                         if (rxq->rx_started) {
2080                                 dflt_rxq = i;
2081                                 break;
2082                         }
2083                 }
2084
2085                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2086                 rxr = rxq->rx_ring;
2087                 cpr = rxq->cp_ring;
2088
2089                 req.default_rx_ring_id =
2090                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2091                 req.default_cmpl_ring_id =
2092                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2093                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2094                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2095                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2096                         enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2097                         req.rx_csum_v2_mode =
2098                                 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2099                 }
2100                 goto config_mru;
2101         }
2102
2103         /* Only RSS support for now TBD: COS & LB */
2104         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2105         if (vnic->lb_rule != 0xffff)
2106                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2107         if (vnic->cos_rule != 0xffff)
2108                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2109         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2110                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2111                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2112         }
2113         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2114                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2115                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2116         }
2117
2118         enables |= ctx_enable_flag;
2119         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2120         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2121         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2122         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2123
2124 config_mru:
2125         req.enables = rte_cpu_to_le_32(enables);
2126         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2127         req.mru = rte_cpu_to_le_16(vnic->mru);
2128         /* Configure default VNIC only once. */
2129         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2130                 req.flags |=
2131                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2132                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2133         }
2134         if (vnic->vlan_strip)
2135                 req.flags |=
2136                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2137         if (vnic->bd_stall)
2138                 req.flags |=
2139                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2140         if (vnic->rss_dflt_cr)
2141                 req.flags |= rte_cpu_to_le_32(
2142                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2143
2144         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2145
2146         HWRM_CHECK_RESULT();
2147         HWRM_UNLOCK();
2148
2149         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2150
2151         return rc;
2152 }
2153
2154 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2155                 int16_t fw_vf_id)
2156 {
2157         int rc = 0;
2158         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2159         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2160
2161         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2162                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2163                 return rc;
2164         }
2165         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2166
2167         req.enables =
2168                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2169         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2170         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2171
2172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2173
2174         HWRM_CHECK_RESULT();
2175
2176         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2177         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2178         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2179         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2180         vnic->mru = rte_le_to_cpu_16(resp->mru);
2181         vnic->func_default = rte_le_to_cpu_32(
2182                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2183         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2184                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2185         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2186                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2187         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2188                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2189
2190         HWRM_UNLOCK();
2191
2192         return rc;
2193 }
2194
2195 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2196                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2197 {
2198         int rc = 0;
2199         uint16_t ctx_id;
2200         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2201         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2202                                                 bp->hwrm_cmd_resp_addr;
2203
2204         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2205
2206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2207         HWRM_CHECK_RESULT();
2208
2209         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2210         if (!BNXT_HAS_RING_GRPS(bp))
2211                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2212         else if (ctx_idx == 0)
2213                 vnic->rss_rule = ctx_id;
2214
2215         HWRM_UNLOCK();
2216
2217         return rc;
2218 }
2219
2220 static
2221 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2222                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2223 {
2224         int rc = 0;
2225         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2226         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2227                                                 bp->hwrm_cmd_resp_addr;
2228
2229         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2230                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2231                 return rc;
2232         }
2233         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2234
2235         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2236
2237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2238
2239         HWRM_CHECK_RESULT();
2240         HWRM_UNLOCK();
2241
2242         return rc;
2243 }
2244
2245 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2246 {
2247         int rc = 0;
2248
2249         if (BNXT_CHIP_P5(bp)) {
2250                 int j;
2251
2252                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2253                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2254                                                       vnic,
2255                                                       vnic->fw_grp_ids[j]);
2256                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2257                 }
2258                 vnic->num_lb_ctxts = 0;
2259         } else {
2260                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2261                 vnic->rss_rule = INVALID_HW_RING_ID;
2262         }
2263
2264         return rc;
2265 }
2266
2267 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2268 {
2269         int rc = 0;
2270         struct hwrm_vnic_free_input req = {.req_type = 0 };
2271         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2272
2273         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2274                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2275                 return rc;
2276         }
2277
2278         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2279
2280         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2281
2282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2283
2284         HWRM_CHECK_RESULT();
2285         HWRM_UNLOCK();
2286
2287         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2288         /* Configure default VNIC again if necessary. */
2289         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2290                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2291
2292         return rc;
2293 }
2294
2295 static int
2296 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2297 {
2298         int i;
2299         int rc = 0;
2300         int nr_ctxs = vnic->num_lb_ctxts;
2301         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2302         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2303
2304         for (i = 0; i < nr_ctxs; i++) {
2305                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2306
2307                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2308                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2309                 req.hash_mode_flags = vnic->hash_mode;
2310
2311                 req.hash_key_tbl_addr =
2312                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2313
2314                 req.ring_grp_tbl_addr =
2315                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2316                                          i * HW_HASH_INDEX_SIZE);
2317                 req.ring_table_pair_index = i;
2318                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2319
2320                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2321                                             BNXT_USE_CHIMP_MB);
2322
2323                 HWRM_CHECK_RESULT();
2324                 HWRM_UNLOCK();
2325         }
2326
2327         return rc;
2328 }
2329
2330 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2331                            struct bnxt_vnic_info *vnic)
2332 {
2333         int rc = 0;
2334         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2335         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2336
2337         if (!vnic->rss_table)
2338                 return 0;
2339
2340         if (BNXT_CHIP_P5(bp))
2341                 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2342
2343         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2344
2345         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2346         req.hash_mode_flags = vnic->hash_mode;
2347
2348         req.ring_grp_tbl_addr =
2349             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2350         req.hash_key_tbl_addr =
2351             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2352         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2353         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2354
2355         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2356
2357         HWRM_CHECK_RESULT();
2358         HWRM_UNLOCK();
2359
2360         return rc;
2361 }
2362
2363 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2364                         struct bnxt_vnic_info *vnic)
2365 {
2366         int rc = 0;
2367         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2368         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2369         uint16_t size;
2370
2371         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2372                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2373                 return rc;
2374         }
2375
2376         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2377
2378         req.flags = rte_cpu_to_le_32(
2379                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2380
2381         req.enables = rte_cpu_to_le_32(
2382                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2383
2384         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2385         size -= RTE_PKTMBUF_HEADROOM;
2386         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2387
2388         req.jumbo_thresh = rte_cpu_to_le_16(size);
2389         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2390
2391         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2392
2393         HWRM_CHECK_RESULT();
2394         HWRM_UNLOCK();
2395
2396         return rc;
2397 }
2398
2399 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2400                         struct bnxt_vnic_info *vnic, bool enable)
2401 {
2402         int rc = 0;
2403         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2404         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2405
2406         if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2407                 if (enable)
2408                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2409                 return -ENOTSUP;
2410         }
2411
2412         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2413                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2414                 return 0;
2415         }
2416
2417         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2418
2419         if (enable) {
2420                 req.enables = rte_cpu_to_le_32(
2421                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2422                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2423                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2424                 req.flags = rte_cpu_to_le_32(
2425                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2426                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2427                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2428                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2429                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2430                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2431                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2432                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2433                 req.min_agg_len = rte_cpu_to_le_32(512);
2434         }
2435         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2436
2437         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2438
2439         HWRM_CHECK_RESULT();
2440         HWRM_UNLOCK();
2441
2442         return rc;
2443 }
2444
2445 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2446 {
2447         struct hwrm_func_cfg_input req = {0};
2448         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2449         int rc;
2450
2451         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2452         req.enables = rte_cpu_to_le_32(
2453                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2454         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2455         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2456
2457         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2458
2459         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2460         HWRM_CHECK_RESULT();
2461         HWRM_UNLOCK();
2462
2463         bp->pf->vf_info[vf].random_mac = false;
2464
2465         return rc;
2466 }
2467
2468 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2469                                   uint64_t *dropped)
2470 {
2471         int rc = 0;
2472         struct hwrm_func_qstats_input req = {.req_type = 0};
2473         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2474
2475         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2476
2477         req.fid = rte_cpu_to_le_16(fid);
2478
2479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2480
2481         HWRM_CHECK_RESULT();
2482
2483         if (dropped)
2484                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2485
2486         HWRM_UNLOCK();
2487
2488         return rc;
2489 }
2490
2491 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2492                           struct rte_eth_stats *stats,
2493                           struct hwrm_func_qstats_output *func_qstats)
2494 {
2495         int rc = 0;
2496         struct hwrm_func_qstats_input req = {.req_type = 0};
2497         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2498
2499         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2500
2501         req.fid = rte_cpu_to_le_16(fid);
2502
2503         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2504
2505         HWRM_CHECK_RESULT();
2506         if (func_qstats)
2507                 memcpy(func_qstats, resp,
2508                        sizeof(struct hwrm_func_qstats_output));
2509
2510         if (!stats)
2511                 goto exit;
2512
2513         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2514         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2515         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2516         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2517         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2518         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2519
2520         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2521         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2522         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2523         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2524         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2525         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2526
2527         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2528         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2529         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2530
2531 exit:
2532         HWRM_UNLOCK();
2533
2534         return rc;
2535 }
2536
2537 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2538 {
2539         int rc = 0;
2540         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2541         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2542
2543         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2544
2545         req.fid = rte_cpu_to_le_16(fid);
2546
2547         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2548
2549         HWRM_CHECK_RESULT();
2550         HWRM_UNLOCK();
2551
2552         return rc;
2553 }
2554
2555 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2556 {
2557         unsigned int i;
2558         int rc = 0;
2559
2560         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2561                 struct bnxt_tx_queue *txq;
2562                 struct bnxt_rx_queue *rxq;
2563                 struct bnxt_cp_ring_info *cpr;
2564
2565                 if (i >= bp->rx_cp_nr_rings) {
2566                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2567                         cpr = txq->cp_ring;
2568                 } else {
2569                         rxq = bp->rx_queues[i];
2570                         cpr = rxq->cp_ring;
2571                 }
2572
2573                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2574                 if (rc)
2575                         return rc;
2576         }
2577         return 0;
2578 }
2579
2580 static int
2581 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2582 {
2583         int rc;
2584         unsigned int i;
2585         struct bnxt_cp_ring_info *cpr;
2586
2587         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2588
2589                 if (i >= bp->rx_cp_nr_rings) {
2590                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2591                 } else {
2592                         cpr = bp->rx_queues[i]->cp_ring;
2593                         if (BNXT_HAS_RING_GRPS(bp))
2594                                 bp->grp_info[i].fw_stats_ctx = -1;
2595                 }
2596                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2597                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2598                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2599                         if (rc)
2600                                 return rc;
2601                 }
2602         }
2603         return 0;
2604 }
2605
2606 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2607 {
2608         unsigned int i;
2609         int rc = 0;
2610
2611         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2612                 struct bnxt_tx_queue *txq;
2613                 struct bnxt_rx_queue *rxq;
2614                 struct bnxt_cp_ring_info *cpr;
2615
2616                 if (i >= bp->rx_cp_nr_rings) {
2617                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2618                         cpr = txq->cp_ring;
2619                 } else {
2620                         rxq = bp->rx_queues[i];
2621                         cpr = rxq->cp_ring;
2622                 }
2623
2624                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2625
2626                 if (rc)
2627                         return rc;
2628         }
2629         return rc;
2630 }
2631
2632 static int
2633 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2634 {
2635         uint16_t idx;
2636         uint32_t rc = 0;
2637
2638         if (!BNXT_HAS_RING_GRPS(bp))
2639                 return 0;
2640
2641         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2642
2643                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2644                         continue;
2645
2646                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2647
2648                 if (rc)
2649                         return rc;
2650         }
2651         return rc;
2652 }
2653
2654 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2655 {
2656         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2657
2658         bnxt_hwrm_ring_free(bp, cp_ring,
2659                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2660                             INVALID_HW_RING_ID);
2661         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2662         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2663                                      sizeof(*cpr->cp_desc_ring));
2664         cpr->cp_raw_cons = 0;
2665         cpr->valid = 0;
2666 }
2667
2668 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2669 {
2670         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2671
2672         bnxt_hwrm_ring_free(bp, cp_ring,
2673                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2674                         INVALID_HW_RING_ID);
2675         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2676         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2677                         sizeof(*cpr->cp_desc_ring));
2678         cpr->cp_raw_cons = 0;
2679         cpr->valid = 0;
2680 }
2681
2682 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2683 {
2684         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2685         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2686         struct bnxt_ring *ring = rxr->rx_ring_struct;
2687         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2688
2689         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2690                 bnxt_hwrm_ring_free(bp, ring,
2691                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2692                                     cpr->cp_ring_struct->fw_ring_id);
2693                 ring->fw_ring_id = INVALID_HW_RING_ID;
2694                 if (BNXT_HAS_RING_GRPS(bp))
2695                         bp->grp_info[queue_index].rx_fw_ring_id =
2696                                                         INVALID_HW_RING_ID;
2697         }
2698         ring = rxr->ag_ring_struct;
2699         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2700                 bnxt_hwrm_ring_free(bp, ring,
2701                                     BNXT_CHIP_P5(bp) ?
2702                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2703                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2704                                     cpr->cp_ring_struct->fw_ring_id);
2705                 if (BNXT_HAS_RING_GRPS(bp))
2706                         bp->grp_info[queue_index].ag_fw_ring_id =
2707                                                         INVALID_HW_RING_ID;
2708         }
2709         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2710                 bnxt_free_cp_ring(bp, cpr);
2711
2712         if (BNXT_HAS_RING_GRPS(bp))
2713                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2714 }
2715
2716 static int
2717 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2718 {
2719         unsigned int i;
2720
2721         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2722                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2723                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2724                 struct bnxt_ring *ring = txr->tx_ring_struct;
2725                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2726
2727                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2728                         bnxt_hwrm_ring_free(bp, ring,
2729                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX,
2730                                         cpr->cp_ring_struct->fw_ring_id);
2731                         ring->fw_ring_id = INVALID_HW_RING_ID;
2732                         memset(txr->tx_desc_ring, 0,
2733                                         txr->tx_ring_struct->ring_size *
2734                                         sizeof(*txr->tx_desc_ring));
2735                         memset(txr->tx_buf_ring, 0,
2736                                         txr->tx_ring_struct->ring_size *
2737                                         sizeof(*txr->tx_buf_ring));
2738                         txr->tx_raw_prod = 0;
2739                         txr->tx_raw_cons = 0;
2740                 }
2741                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2742                         bnxt_free_cp_ring(bp, cpr);
2743                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2744                 }
2745         }
2746
2747         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2748                 bnxt_free_hwrm_rx_ring(bp, i);
2749
2750         return 0;
2751 }
2752
2753 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2754 {
2755         uint16_t i;
2756         uint32_t rc = 0;
2757
2758         if (!BNXT_HAS_RING_GRPS(bp))
2759                 return 0;
2760
2761         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2762                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2763                 if (rc)
2764                         return rc;
2765         }
2766         return rc;
2767 }
2768
2769 /*
2770  * HWRM utility functions
2771  */
2772
2773 void bnxt_free_hwrm_resources(struct bnxt *bp)
2774 {
2775         /* Release memzone */
2776         rte_free(bp->hwrm_cmd_resp_addr);
2777         rte_free(bp->hwrm_short_cmd_req_addr);
2778         bp->hwrm_cmd_resp_addr = NULL;
2779         bp->hwrm_short_cmd_req_addr = NULL;
2780         bp->hwrm_cmd_resp_dma_addr = 0;
2781         bp->hwrm_short_cmd_req_dma_addr = 0;
2782 }
2783
2784 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2785 {
2786         struct rte_pci_device *pdev = bp->pdev;
2787         char type[RTE_MEMZONE_NAMESIZE];
2788
2789         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2790                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2791         bp->max_resp_len = BNXT_PAGE_SIZE;
2792         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2793         if (bp->hwrm_cmd_resp_addr == NULL)
2794                 return -ENOMEM;
2795         bp->hwrm_cmd_resp_dma_addr =
2796                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2797         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2798                 PMD_DRV_LOG(ERR,
2799                         "unable to map response address to physical memory\n");
2800                 return -ENOMEM;
2801         }
2802         rte_spinlock_init(&bp->hwrm_lock);
2803
2804         return 0;
2805 }
2806
2807 int
2808 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2809 {
2810         int rc = 0;
2811
2812         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2813                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2814                 if (rc)
2815                         return rc;
2816         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2817                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2818                 if (rc)
2819                         return rc;
2820         }
2821
2822         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2823         return rc;
2824 }
2825
2826 static int
2827 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2828 {
2829         struct bnxt_filter_info *filter;
2830         int rc = 0;
2831
2832         STAILQ_FOREACH(filter, &vnic->filter, next) {
2833                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2834                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2835                 bnxt_free_filter(bp, filter);
2836         }
2837         return rc;
2838 }
2839
2840 static int
2841 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2842 {
2843         struct bnxt_filter_info *filter;
2844         struct rte_flow *flow;
2845         int rc = 0;
2846
2847         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2848                 flow = STAILQ_FIRST(&vnic->flow_list);
2849                 filter = flow->filter;
2850                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2851                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2852
2853                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2854                 rte_free(flow);
2855         }
2856         return rc;
2857 }
2858
2859 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2860 {
2861         struct bnxt_filter_info *filter;
2862         int rc = 0;
2863
2864         STAILQ_FOREACH(filter, &vnic->filter, next) {
2865                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2866                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2867                                                      filter);
2868                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2869                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2870                                                          filter);
2871                 else
2872                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2873                                                      filter);
2874                 if (rc)
2875                         break;
2876         }
2877         return rc;
2878 }
2879
2880 static void
2881 bnxt_free_tunnel_ports(struct bnxt *bp)
2882 {
2883         if (bp->vxlan_port_cnt)
2884                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2885                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2886
2887         if (bp->geneve_port_cnt)
2888                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2889                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2890 }
2891
2892 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2893 {
2894         int i;
2895
2896         if (bp->vnic_info == NULL)
2897                 return;
2898
2899         /*
2900          * Cleanup VNICs in reverse order, to make sure the L2 filter
2901          * from vnic0 is last to be cleaned up.
2902          */
2903         for (i = bp->max_vnics - 1; i >= 0; i--) {
2904                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2905
2906                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2907                         continue;
2908
2909                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2910
2911                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2912
2913                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2914
2915                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2916
2917                 bnxt_hwrm_vnic_free(bp, vnic);
2918
2919                 rte_free(vnic->fw_grp_ids);
2920         }
2921         /* Ring resources */
2922         bnxt_free_all_hwrm_rings(bp);
2923         bnxt_free_all_hwrm_ring_grps(bp);
2924         bnxt_free_all_hwrm_stat_ctxs(bp);
2925         bnxt_free_tunnel_ports(bp);
2926 }
2927
2928 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2929 {
2930         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2931
2932         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2933                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2934
2935         switch (conf_link_speed) {
2936         case ETH_LINK_SPEED_10M_HD:
2937         case ETH_LINK_SPEED_100M_HD:
2938                 /* FALLTHROUGH */
2939                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2940         }
2941         return hw_link_duplex;
2942 }
2943
2944 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2945 {
2946         return !conf_link;
2947 }
2948
2949 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2950                                           uint16_t pam4_link)
2951 {
2952         uint16_t eth_link_speed = 0;
2953
2954         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2955                 return ETH_LINK_SPEED_AUTONEG;
2956
2957         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2958         case ETH_LINK_SPEED_100M:
2959         case ETH_LINK_SPEED_100M_HD:
2960                 /* FALLTHROUGH */
2961                 eth_link_speed =
2962                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2963                 break;
2964         case ETH_LINK_SPEED_1G:
2965                 eth_link_speed =
2966                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2967                 break;
2968         case ETH_LINK_SPEED_2_5G:
2969                 eth_link_speed =
2970                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2971                 break;
2972         case ETH_LINK_SPEED_10G:
2973                 eth_link_speed =
2974                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2975                 break;
2976         case ETH_LINK_SPEED_20G:
2977                 eth_link_speed =
2978                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2979                 break;
2980         case ETH_LINK_SPEED_25G:
2981                 eth_link_speed =
2982                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2983                 break;
2984         case ETH_LINK_SPEED_40G:
2985                 eth_link_speed =
2986                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2987                 break;
2988         case ETH_LINK_SPEED_50G:
2989                 eth_link_speed = pam4_link ?
2990                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
2991                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2992                 break;
2993         case ETH_LINK_SPEED_100G:
2994                 eth_link_speed = pam4_link ?
2995                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
2996                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2997                 break;
2998         case ETH_LINK_SPEED_200G:
2999                 eth_link_speed =
3000                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3001                 break;
3002         default:
3003                 PMD_DRV_LOG(ERR,
3004                         "Unsupported link speed %d; default to AUTO\n",
3005                         conf_link_speed);
3006                 break;
3007         }
3008         return eth_link_speed;
3009 }
3010
3011 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
3012                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
3013                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
3014                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
3015                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
3016
3017 static int bnxt_validate_link_speed(struct bnxt *bp)
3018 {
3019         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3020         uint16_t port_id = bp->eth_dev->data->port_id;
3021         uint32_t link_speed_capa;
3022         uint32_t one_speed;
3023
3024         if (link_speed == ETH_LINK_SPEED_AUTONEG)
3025                 return 0;
3026
3027         link_speed_capa = bnxt_get_speed_capabilities(bp);
3028
3029         if (link_speed & ETH_LINK_SPEED_FIXED) {
3030                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
3031
3032                 if (one_speed & (one_speed - 1)) {
3033                         PMD_DRV_LOG(ERR,
3034                                 "Invalid advertised speeds (%u) for port %u\n",
3035                                 link_speed, port_id);
3036                         return -EINVAL;
3037                 }
3038                 if ((one_speed & link_speed_capa) != one_speed) {
3039                         PMD_DRV_LOG(ERR,
3040                                 "Unsupported advertised speed (%u) for port %u\n",
3041                                 link_speed, port_id);
3042                         return -EINVAL;
3043                 }
3044         } else {
3045                 if (!(link_speed & link_speed_capa)) {
3046                         PMD_DRV_LOG(ERR,
3047                                 "Unsupported advertised speeds (%u) for port %u\n",
3048                                 link_speed, port_id);
3049                         return -EINVAL;
3050                 }
3051         }
3052         return 0;
3053 }
3054
3055 static uint16_t
3056 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3057 {
3058         uint16_t ret = 0;
3059
3060         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
3061                 if (bp->link_info->support_speeds)
3062                         return bp->link_info->support_speeds;
3063                 link_speed = BNXT_SUPPORTED_SPEEDS;
3064         }
3065
3066         if (link_speed & ETH_LINK_SPEED_100M)
3067                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3068         if (link_speed & ETH_LINK_SPEED_100M_HD)
3069                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3070         if (link_speed & ETH_LINK_SPEED_1G)
3071                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3072         if (link_speed & ETH_LINK_SPEED_2_5G)
3073                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3074         if (link_speed & ETH_LINK_SPEED_10G)
3075                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3076         if (link_speed & ETH_LINK_SPEED_20G)
3077                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3078         if (link_speed & ETH_LINK_SPEED_25G)
3079                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3080         if (link_speed & ETH_LINK_SPEED_40G)
3081                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3082         if (link_speed & ETH_LINK_SPEED_50G)
3083                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3084         if (link_speed & ETH_LINK_SPEED_100G)
3085                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3086         if (link_speed & ETH_LINK_SPEED_200G)
3087                 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3088         return ret;
3089 }
3090
3091 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3092 {
3093         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
3094
3095         switch (hw_link_speed) {
3096         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3097                 eth_link_speed = ETH_SPEED_NUM_100M;
3098                 break;
3099         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3100                 eth_link_speed = ETH_SPEED_NUM_1G;
3101                 break;
3102         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3103                 eth_link_speed = ETH_SPEED_NUM_2_5G;
3104                 break;
3105         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3106                 eth_link_speed = ETH_SPEED_NUM_10G;
3107                 break;
3108         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3109                 eth_link_speed = ETH_SPEED_NUM_20G;
3110                 break;
3111         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3112                 eth_link_speed = ETH_SPEED_NUM_25G;
3113                 break;
3114         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3115                 eth_link_speed = ETH_SPEED_NUM_40G;
3116                 break;
3117         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3118                 eth_link_speed = ETH_SPEED_NUM_50G;
3119                 break;
3120         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3121                 eth_link_speed = ETH_SPEED_NUM_100G;
3122                 break;
3123         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3124                 eth_link_speed = ETH_SPEED_NUM_200G;
3125                 break;
3126         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3127         default:
3128                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3129                         hw_link_speed);
3130                 break;
3131         }
3132         return eth_link_speed;
3133 }
3134
3135 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3136 {
3137         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3138
3139         switch (hw_link_duplex) {
3140         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3141         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3142                 /* FALLTHROUGH */
3143                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
3144                 break;
3145         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3146                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
3147                 break;
3148         default:
3149                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3150                         hw_link_duplex);
3151                 break;
3152         }
3153         return eth_link_duplex;
3154 }
3155
3156 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3157 {
3158         int rc = 0;
3159         struct bnxt_link_info *link_info = bp->link_info;
3160
3161         rc = bnxt_hwrm_port_phy_qcaps(bp);
3162         if (rc)
3163                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3164
3165         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3166         if (rc) {
3167                 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3168                 goto exit;
3169         }
3170
3171         if (link_info->link_speed)
3172                 link->link_speed =
3173                         bnxt_parse_hw_link_speed(link_info->link_speed);
3174         else
3175                 link->link_speed = ETH_SPEED_NUM_NONE;
3176         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3177         link->link_status = link_info->link_up;
3178         link->link_autoneg = link_info->auto_mode ==
3179                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3180                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
3181 exit:
3182         return rc;
3183 }
3184
3185 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3186 {
3187         int rc = 0;
3188         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3189         struct bnxt_link_info link_req;
3190         uint16_t speed, autoneg;
3191
3192         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3193                 return 0;
3194
3195         rc = bnxt_validate_link_speed(bp);
3196         if (rc)
3197                 goto error;
3198
3199         memset(&link_req, 0, sizeof(link_req));
3200         link_req.link_up = link_up;
3201         if (!link_up)
3202                 goto port_phy_cfg;
3203
3204         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3205         if (BNXT_CHIP_P5(bp) &&
3206             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3207                 /* 40G is not supported as part of media auto detect.
3208                  * The speed should be forced and autoneg disabled
3209                  * to configure 40G speed.
3210                  */
3211                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3212                 autoneg = 0;
3213         }
3214
3215         /* No auto speeds and no auto_pam4_link. Disable autoneg */
3216         if (bp->link_info->auto_link_speed == 0 &&
3217             bp->link_info->link_signal_mode &&
3218             bp->link_info->auto_pam4_link_speeds == 0)
3219                 autoneg = 0;
3220
3221         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3222                                           bp->link_info->link_signal_mode);
3223         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3224         /* Autoneg can be done only when the FW allows.
3225          * When user configures fixed speed of 40G and later changes to
3226          * any other speed, auto_link_speed/force_link_speed is still set
3227          * to 40G until link comes up at new speed.
3228          */
3229         if (autoneg == 1 &&
3230             !(!BNXT_CHIP_P5(bp) &&
3231               (bp->link_info->auto_link_speed ||
3232                bp->link_info->force_link_speed))) {
3233                 link_req.phy_flags |=
3234                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3235                 link_req.auto_link_speed_mask =
3236                         bnxt_parse_eth_link_speed_mask(bp,
3237                                                        dev_conf->link_speeds);
3238         } else {
3239                 if (bp->link_info->phy_type ==
3240                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3241                     bp->link_info->phy_type ==
3242                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3243                     bp->link_info->media_type ==
3244                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3245                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3246                         return -EINVAL;
3247                 }
3248
3249                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3250                 /* If user wants a particular speed try that first. */
3251                 if (speed)
3252                         link_req.link_speed = speed;
3253                 else if (bp->link_info->force_pam4_link_speed)
3254                         link_req.link_speed =
3255                                 bp->link_info->force_pam4_link_speed;
3256                 else if (bp->link_info->auto_pam4_link_speeds)
3257                         link_req.link_speed =
3258                                 bp->link_info->auto_pam4_link_speeds;
3259                 else if (bp->link_info->support_pam4_speeds)
3260                         link_req.link_speed =
3261                                 bp->link_info->support_pam4_speeds;
3262                 else if (bp->link_info->force_link_speed)
3263                         link_req.link_speed = bp->link_info->force_link_speed;
3264                 else
3265                         link_req.link_speed = bp->link_info->auto_link_speed;
3266                 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3267                  * zero. Use the auto_link_speed.
3268                  */
3269                 if (bp->link_info->auto_link_speed != 0 &&
3270                     bp->link_info->auto_pam4_link_speeds == 0)
3271                         link_req.link_speed = bp->link_info->auto_link_speed;
3272         }
3273         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3274         link_req.auto_pause = bp->link_info->auto_pause;
3275         link_req.force_pause = bp->link_info->force_pause;
3276
3277 port_phy_cfg:
3278         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3279         if (rc) {
3280                 PMD_DRV_LOG(ERR,
3281                         "Set link config failed with rc %d\n", rc);
3282         }
3283
3284 error:
3285         return rc;
3286 }
3287
3288 /* JIRA 22088 */
3289 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3290 {
3291         struct hwrm_func_qcfg_input req = {0};
3292         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3293         uint16_t flags;
3294         int rc = 0;
3295         bp->func_svif = BNXT_SVIF_INVALID;
3296         uint16_t svif_info;
3297
3298         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3299         req.fid = rte_cpu_to_le_16(0xffff);
3300
3301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3302
3303         HWRM_CHECK_RESULT();
3304
3305         /* Hard Coded.. 0xfff VLAN ID mask */
3306         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3307
3308         svif_info = rte_le_to_cpu_16(resp->svif_info);
3309         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3310                 bp->func_svif = svif_info &
3311                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3312
3313         flags = rte_le_to_cpu_16(resp->flags);
3314         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3315                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3316
3317         if (BNXT_VF(bp) &&
3318             !BNXT_VF_IS_TRUSTED(bp) &&
3319             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3320                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3321                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3322         } else if (BNXT_VF(bp) &&
3323                    BNXT_VF_IS_TRUSTED(bp) &&
3324                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3325                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3326                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3327         }
3328
3329         if (mtu)
3330                 *mtu = rte_le_to_cpu_16(resp->mtu);
3331
3332         switch (resp->port_partition_type) {
3333         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3334         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3335         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3336                 /* FALLTHROUGH */
3337                 bp->flags |= BNXT_FLAG_NPAR_PF;
3338                 break;
3339         default:
3340                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3341                 break;
3342         }
3343
3344         bp->legacy_db_size =
3345                 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3346
3347         HWRM_UNLOCK();
3348
3349         return rc;
3350 }
3351
3352 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3353 {
3354         struct hwrm_func_qcfg_input req = {0};
3355         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3356         int rc;
3357
3358         if (!BNXT_VF_IS_TRUSTED(bp))
3359                 return 0;
3360
3361         if (!bp->parent)
3362                 return -EINVAL;
3363
3364         bp->parent->fid = BNXT_PF_FID_INVALID;
3365
3366         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3367
3368         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3369
3370         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3371
3372         HWRM_CHECK_RESULT_SILENT();
3373
3374         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3375         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3376         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3377         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3378
3379         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3380         if (bp->parent->vnic == 0) {
3381                 PMD_DRV_LOG(DEBUG, "parent VNIC unavailable.\n");
3382                 /* Use hard-coded values appropriate for current Wh+ fw. */
3383                 if (bp->parent->fid == 2)
3384                         bp->parent->vnic = 0x100;
3385                 else
3386                         bp->parent->vnic = 1;
3387         }
3388
3389         HWRM_UNLOCK();
3390
3391         return 0;
3392 }
3393
3394 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3395                                  uint16_t *vnic_id, uint16_t *svif)
3396 {
3397         struct hwrm_func_qcfg_input req = {0};
3398         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3399         uint16_t svif_info;
3400         int rc = 0;
3401
3402         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3403         req.fid = rte_cpu_to_le_16(fid);
3404
3405         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3406
3407         HWRM_CHECK_RESULT();
3408
3409         if (vnic_id)
3410                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3411
3412         svif_info = rte_le_to_cpu_16(resp->svif_info);
3413         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3414                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3415
3416         HWRM_UNLOCK();
3417
3418         return rc;
3419 }
3420
3421 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3422 {
3423         struct hwrm_port_mac_qcfg_input req = {0};
3424         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3425         uint16_t port_svif_info;
3426         int rc;
3427
3428         bp->port_svif = BNXT_SVIF_INVALID;
3429
3430         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3431                 return 0;
3432
3433         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3434
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436
3437         HWRM_CHECK_RESULT_SILENT();
3438
3439         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3440         if (port_svif_info &
3441             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3442                 bp->port_svif = port_svif_info &
3443                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3444
3445         HWRM_UNLOCK();
3446
3447         return 0;
3448 }
3449
3450 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3451                                  struct bnxt_pf_resource_info *pf_resc)
3452 {
3453         struct hwrm_func_cfg_input req = {0};
3454         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3455         uint32_t enables;
3456         int rc;
3457
3458         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3459                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3460                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3461                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3462                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3463                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3464                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3465                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3466                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3467
3468         if (BNXT_HAS_RING_GRPS(bp)) {
3469                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3470                 req.num_hw_ring_grps =
3471                         rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3472         } else if (BNXT_HAS_NQ(bp)) {
3473                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3474                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3475         }
3476
3477         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3478         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3479         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3480         req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3481         req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3482         req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3483         req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3484         req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3485         req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3486         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3487         req.fid = rte_cpu_to_le_16(0xffff);
3488         req.enables = rte_cpu_to_le_32(enables);
3489
3490         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3491
3492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493
3494         HWRM_CHECK_RESULT();
3495         HWRM_UNLOCK();
3496
3497         return rc;
3498 }
3499
3500 /* min values are the guaranteed resources and max values are subject
3501  * to availability. The strategy for now is to keep both min & max
3502  * values the same.
3503  */
3504 static void
3505 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3506                               struct hwrm_func_vf_resource_cfg_input *req,
3507                               int num_vfs)
3508 {
3509         req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3510                                                (num_vfs + 1));
3511         req->min_rsscos_ctx = req->max_rsscos_ctx;
3512         req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3513         req->min_stat_ctx = req->max_stat_ctx;
3514         req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3515                                                (num_vfs + 1));
3516         req->min_cmpl_rings = req->max_cmpl_rings;
3517         req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3518         req->min_tx_rings = req->max_tx_rings;
3519         req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3520         req->min_rx_rings = req->max_rx_rings;
3521         req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3522         req->min_l2_ctxs = req->max_l2_ctxs;
3523         /* TODO: For now, do not support VMDq/RFS on VFs. */
3524         req->max_vnics = rte_cpu_to_le_16(1);
3525         req->min_vnics = req->max_vnics;
3526         req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3527                                                  (num_vfs + 1));
3528         req->min_hw_ring_grps = req->max_hw_ring_grps;
3529         req->flags =
3530          rte_cpu_to_le_16(HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED);
3531 }
3532
3533 static void
3534 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3535                               struct hwrm_func_cfg_input *req,
3536                               int num_vfs)
3537 {
3538         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3539                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3540                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3541                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3542                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3543                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3544                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3545                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3546                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3547                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3548
3549         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3550                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3551                                     BNXT_NUM_VLANS);
3552         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3553         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3554                                                 (num_vfs + 1));
3555         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3556         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3557                                                (num_vfs + 1));
3558         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3559         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3560         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3561         /* TODO: For now, do not support VMDq/RFS on VFs. */
3562         req->num_vnics = rte_cpu_to_le_16(1);
3563         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3564                                                  (num_vfs + 1));
3565 }
3566
3567 /* Update the port wide resource values based on how many resources
3568  * got allocated to the VF.
3569  */
3570 static int bnxt_update_max_resources(struct bnxt *bp,
3571                                      int vf)
3572 {
3573         struct hwrm_func_qcfg_input req = {0};
3574         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3575         int rc;
3576
3577         /* Get the actual allocated values now */
3578         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3579         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3581         HWRM_CHECK_RESULT();
3582
3583         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3584         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3585         bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3586         bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3587         bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3588         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3589         bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3590
3591         HWRM_UNLOCK();
3592
3593         return 0;
3594 }
3595
3596 /* Update the PF resource values based on how many resources
3597  * got allocated to it.
3598  */
3599 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3600 {
3601         struct hwrm_func_qcfg_input req = {0};
3602         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3603         int rc;
3604
3605         /* Get the actual allocated values now */
3606         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3607         req.fid = rte_cpu_to_le_16(0xffff);
3608         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3609         HWRM_CHECK_RESULT();
3610
3611         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3612         bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3613         bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3614         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3615         bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3616         bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3617         bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3618         bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3619
3620         HWRM_UNLOCK();
3621
3622         return 0;
3623 }
3624
3625 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3626 {
3627         struct hwrm_func_qcfg_input req = {0};
3628         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3629         int rc;
3630
3631         /* Check for zero MAC address */
3632         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3633         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3635         HWRM_CHECK_RESULT();
3636         rc = rte_le_to_cpu_16(resp->vlan);
3637
3638         HWRM_UNLOCK();
3639
3640         return rc;
3641 }
3642
3643 static int bnxt_query_pf_resources(struct bnxt *bp,
3644                                    struct bnxt_pf_resource_info *pf_resc)
3645 {
3646         struct hwrm_func_qcfg_input req = {0};
3647         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3648         int rc;
3649
3650         /* And copy the allocated numbers into the pf struct */
3651         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3652         req.fid = rte_cpu_to_le_16(0xffff);
3653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3654         HWRM_CHECK_RESULT();
3655
3656         pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3657         pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3658         pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3659         pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3660         pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3661         pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3662         pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3663         bp->pf->evb_mode = resp->evb_mode;
3664
3665         HWRM_UNLOCK();
3666
3667         return rc;
3668 }
3669
3670 static void
3671 bnxt_calculate_pf_resources(struct bnxt *bp,
3672                             struct bnxt_pf_resource_info *pf_resc,
3673                             int num_vfs)
3674 {
3675         if (!num_vfs) {
3676                 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3677                 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3678                 pf_resc->num_cp_rings = bp->max_cp_rings;
3679                 pf_resc->num_tx_rings = bp->max_tx_rings;
3680                 pf_resc->num_rx_rings = bp->max_rx_rings;
3681                 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3682                 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3683
3684                 return;
3685         }
3686
3687         pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3688                                    bp->max_rsscos_ctx % (num_vfs + 1);
3689         pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3690                                  bp->max_stat_ctx % (num_vfs + 1);
3691         pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3692                                 bp->max_cp_rings % (num_vfs + 1);
3693         pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3694                                 bp->max_tx_rings % (num_vfs + 1);
3695         pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3696                                 bp->max_rx_rings % (num_vfs + 1);
3697         pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3698                                bp->max_l2_ctx % (num_vfs + 1);
3699         pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3700                                     bp->max_ring_grps % (num_vfs + 1);
3701 }
3702
3703 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3704 {
3705         struct bnxt_pf_resource_info pf_resc = { 0 };
3706         int rc;
3707
3708         if (!BNXT_PF(bp)) {
3709                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3710                 return -EINVAL;
3711         }
3712
3713         rc = bnxt_hwrm_func_qcaps(bp);
3714         if (rc)
3715                 return rc;
3716
3717         bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3718
3719         bp->pf->func_cfg_flags &=
3720                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3721                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3722         bp->pf->func_cfg_flags |=
3723                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3724
3725         rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3726         if (rc)
3727                 return rc;
3728
3729         rc = bnxt_update_max_resources_pf_only(bp);
3730
3731         return rc;
3732 }
3733
3734 static int
3735 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3736 {
3737         size_t req_buf_sz, sz;
3738         int i, rc;
3739
3740         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3741         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3742                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3743         if (bp->pf->vf_req_buf == NULL) {
3744                 return -ENOMEM;
3745         }
3746
3747         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3748                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3749
3750         for (i = 0; i < num_vfs; i++)
3751                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3752                                              (i * HWRM_MAX_REQ_LEN);
3753
3754         rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3755         if (rc)
3756                 rte_free(bp->pf->vf_req_buf);
3757
3758         return rc;
3759 }
3760
3761 static int
3762 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3763 {
3764         struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3765         struct hwrm_func_vf_resource_cfg_input req = {0};
3766         int i, rc = 0;
3767
3768         bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3769         bp->pf->active_vfs = 0;
3770         for (i = 0; i < num_vfs; i++) {
3771                 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3772                 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3773                 rc = bnxt_hwrm_send_message(bp,
3774                                             &req,
3775                                             sizeof(req),
3776                                             BNXT_USE_CHIMP_MB);
3777                 if (rc || resp->error_code) {
3778                         PMD_DRV_LOG(ERR,
3779                                 "Failed to initialize VF %d\n", i);
3780                         PMD_DRV_LOG(ERR,
3781                                 "Not all VFs available. (%d, %d)\n",
3782                                 rc, resp->error_code);
3783                         HWRM_UNLOCK();
3784
3785                         /* If the first VF configuration itself fails,
3786                          * unregister the vf_fwd_request buffer.
3787                          */
3788                         if (i == 0)
3789                                 bnxt_hwrm_func_buf_unrgtr(bp);
3790                         break;
3791                 }
3792                 HWRM_UNLOCK();
3793
3794                 /* Update the max resource values based on the resource values
3795                  * allocated to the VF.
3796                  */
3797                 bnxt_update_max_resources(bp, i);
3798                 bp->pf->active_vfs++;
3799                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3800         }
3801
3802         return 0;
3803 }
3804
3805 static int
3806 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3807 {
3808         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3809         struct hwrm_func_cfg_input req = {0};
3810         int i, rc;
3811
3812         bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3813
3814         bp->pf->active_vfs = 0;
3815         for (i = 0; i < num_vfs; i++) {
3816                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3817                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3818                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3819                 rc = bnxt_hwrm_send_message(bp,
3820                                             &req,
3821                                             sizeof(req),
3822                                             BNXT_USE_CHIMP_MB);
3823
3824                 /* Clear enable flag for next pass */
3825                 req.enables &= ~rte_cpu_to_le_32(
3826                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3827
3828                 if (rc || resp->error_code) {
3829                         PMD_DRV_LOG(ERR,
3830                                 "Failed to initialize VF %d\n", i);
3831                         PMD_DRV_LOG(ERR,
3832                                 "Not all VFs available. (%d, %d)\n",
3833                                 rc, resp->error_code);
3834                         HWRM_UNLOCK();
3835
3836                         /* If the first VF configuration itself fails,
3837                          * unregister the vf_fwd_request buffer.
3838                          */
3839                         if (i == 0)
3840                                 bnxt_hwrm_func_buf_unrgtr(bp);
3841                         break;
3842                 }
3843
3844                 HWRM_UNLOCK();
3845
3846                 /* Update the max resource values based on the resource values
3847                  * allocated to the VF.
3848                  */
3849                 bnxt_update_max_resources(bp, i);
3850                 bp->pf->active_vfs++;
3851                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3852         }
3853
3854         return 0;
3855 }
3856
3857 static void
3858 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3859 {
3860         if (bp->flags & BNXT_FLAG_NEW_RM)
3861                 bnxt_process_vf_resc_config_new(bp, num_vfs);
3862         else
3863                 bnxt_process_vf_resc_config_old(bp, num_vfs);
3864 }
3865
3866 static void
3867 bnxt_update_pf_resources(struct bnxt *bp,
3868                          struct bnxt_pf_resource_info *pf_resc)
3869 {
3870         bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3871         bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3872         bp->max_cp_rings = pf_resc->num_cp_rings;
3873         bp->max_tx_rings = pf_resc->num_tx_rings;
3874         bp->max_rx_rings = pf_resc->num_rx_rings;
3875         bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3876 }
3877
3878 static int32_t
3879 bnxt_configure_pf_resources(struct bnxt *bp,
3880                             struct bnxt_pf_resource_info *pf_resc)
3881 {
3882         /*
3883          * We're using STD_TX_RING_MODE here which will limit the TX
3884          * rings. This will allow QoS to function properly. Not setting this
3885          * will cause PF rings to break bandwidth settings.
3886          */
3887         bp->pf->func_cfg_flags &=
3888                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3889                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3890         bp->pf->func_cfg_flags |=
3891                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3892         return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3893 }
3894
3895 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3896 {
3897         struct bnxt_pf_resource_info pf_resc = { 0 };
3898         int rc;
3899
3900         if (!BNXT_PF(bp)) {
3901                 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3902                 return -EINVAL;
3903         }
3904
3905         rc = bnxt_hwrm_func_qcaps(bp);
3906         if (rc)
3907                 return rc;
3908
3909         bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3910
3911         rc = bnxt_configure_pf_resources(bp, &pf_resc);
3912         if (rc)
3913                 return rc;
3914
3915         rc = bnxt_query_pf_resources(bp, &pf_resc);
3916         if (rc)
3917                 return rc;
3918
3919         /*
3920          * Now, create and register a buffer to hold forwarded VF requests
3921          */
3922         rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3923         if (rc)
3924                 return rc;
3925
3926         bnxt_configure_vf_resources(bp, num_vfs);
3927
3928         bnxt_update_pf_resources(bp, &pf_resc);
3929
3930         return 0;
3931 }
3932
3933 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3934 {
3935         struct hwrm_func_cfg_input req = {0};
3936         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3937         int rc;
3938
3939         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3940
3941         req.fid = rte_cpu_to_le_16(0xffff);
3942         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3943         req.evb_mode = bp->pf->evb_mode;
3944
3945         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3946         HWRM_CHECK_RESULT();
3947         HWRM_UNLOCK();
3948
3949         return rc;
3950 }
3951
3952 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3953                                 uint8_t tunnel_type)
3954 {
3955         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3956         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3957         int rc = 0;
3958
3959         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3960         req.tunnel_type = tunnel_type;
3961         req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3963         HWRM_CHECK_RESULT();
3964
3965         switch (tunnel_type) {
3966         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3967                 bp->vxlan_fw_dst_port_id =
3968                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3969                 bp->vxlan_port = port;
3970                 break;
3971         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3972                 bp->geneve_fw_dst_port_id =
3973                         rte_le_to_cpu_16(resp->tunnel_dst_port_id);
3974                 bp->geneve_port = port;
3975                 break;
3976         default:
3977                 break;
3978         }
3979
3980         HWRM_UNLOCK();
3981
3982         return rc;
3983 }
3984
3985 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3986                                 uint8_t tunnel_type)
3987 {
3988         struct hwrm_tunnel_dst_port_free_input req = {0};
3989         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3990         int rc = 0;
3991
3992         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3993
3994         req.tunnel_type = tunnel_type;
3995         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3996         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3997
3998         HWRM_CHECK_RESULT();
3999         HWRM_UNLOCK();
4000
4001         if (tunnel_type ==
4002             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4003                 bp->vxlan_port = 0;
4004                 bp->vxlan_port_cnt = 0;
4005         }
4006
4007         if (tunnel_type ==
4008             HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4009                 bp->geneve_port = 0;
4010                 bp->geneve_port_cnt = 0;
4011         }
4012
4013         return rc;
4014 }
4015
4016 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4017                                         uint32_t flags)
4018 {
4019         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4020         struct hwrm_func_cfg_input req = {0};
4021         int rc;
4022
4023         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4024
4025         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4026         req.flags = rte_cpu_to_le_32(flags);
4027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4028
4029         HWRM_CHECK_RESULT();
4030         HWRM_UNLOCK();
4031
4032         return rc;
4033 }
4034
4035 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4036 {
4037         uint32_t *flag = flagp;
4038
4039         vnic->flags = *flag;
4040 }
4041
4042 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4043 {
4044         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4045 }
4046
4047 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4048 {
4049         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4050         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4051         int rc;
4052
4053         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4054
4055         req.req_buf_num_pages = rte_cpu_to_le_16(1);
4056         req.req_buf_page_size =
4057                 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4058         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4059         req.req_buf_page_addr0 =
4060                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4061         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4062                 PMD_DRV_LOG(ERR,
4063                         "unable to map buffer address to physical memory\n");
4064                 HWRM_UNLOCK();
4065                 return -ENOMEM;
4066         }
4067
4068         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4069
4070         HWRM_CHECK_RESULT();
4071         HWRM_UNLOCK();
4072
4073         return rc;
4074 }
4075
4076 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4077 {
4078         int rc = 0;
4079         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4080         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4081
4082         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4083                 return 0;
4084
4085         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4086
4087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4088
4089         HWRM_CHECK_RESULT();
4090         HWRM_UNLOCK();
4091
4092         return rc;
4093 }
4094
4095 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4096 {
4097         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4098         struct hwrm_func_cfg_input req = {0};
4099         int rc;
4100
4101         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4102
4103         req.fid = rte_cpu_to_le_16(0xffff);
4104         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4105         req.enables = rte_cpu_to_le_32(
4106                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4107         req.async_event_cr = rte_cpu_to_le_16(
4108                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4110
4111         HWRM_CHECK_RESULT();
4112         HWRM_UNLOCK();
4113
4114         return rc;
4115 }
4116
4117 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4118 {
4119         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4120         struct hwrm_func_vf_cfg_input req = {0};
4121         int rc;
4122
4123         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4124
4125         req.enables = rte_cpu_to_le_32(
4126                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4127         req.async_event_cr = rte_cpu_to_le_16(
4128                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4129         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4130
4131         HWRM_CHECK_RESULT();
4132         HWRM_UNLOCK();
4133
4134         return rc;
4135 }
4136
4137 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4138 {
4139         struct hwrm_func_cfg_input req = {0};
4140         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4141         uint16_t dflt_vlan, fid;
4142         uint32_t func_cfg_flags;
4143         int rc = 0;
4144
4145         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4146
4147         if (is_vf) {
4148                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4149                 fid = bp->pf->vf_info[vf].fid;
4150                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4151         } else {
4152                 fid = rte_cpu_to_le_16(0xffff);
4153                 func_cfg_flags = bp->pf->func_cfg_flags;
4154                 dflt_vlan = bp->vlan;
4155         }
4156
4157         req.flags = rte_cpu_to_le_32(func_cfg_flags);
4158         req.fid = rte_cpu_to_le_16(fid);
4159         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4160         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4161
4162         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4163
4164         HWRM_CHECK_RESULT();
4165         HWRM_UNLOCK();
4166
4167         return rc;
4168 }
4169
4170 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4171                         uint16_t max_bw, uint16_t enables)
4172 {
4173         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4174         struct hwrm_func_cfg_input req = {0};
4175         int rc;
4176
4177         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4178
4179         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4180         req.enables |= rte_cpu_to_le_32(enables);
4181         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4182         req.max_bw = rte_cpu_to_le_32(max_bw);
4183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4184
4185         HWRM_CHECK_RESULT();
4186         HWRM_UNLOCK();
4187
4188         return rc;
4189 }
4190
4191 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4192 {
4193         struct hwrm_func_cfg_input req = {0};
4194         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4195         int rc = 0;
4196
4197         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4198
4199         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4200         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4201         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4202         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4203
4204         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4205
4206         HWRM_CHECK_RESULT();
4207         HWRM_UNLOCK();
4208
4209         return rc;
4210 }
4211
4212 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4213 {
4214         int rc;
4215
4216         if (BNXT_PF(bp))
4217                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4218         else
4219                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4220
4221         return rc;
4222 }
4223
4224 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4225                               void *encaped, size_t ec_size)
4226 {
4227         int rc = 0;
4228         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4229         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4230
4231         if (ec_size > sizeof(req.encap_request))
4232                 return -1;
4233
4234         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4235
4236         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4237         memcpy(req.encap_request, encaped, ec_size);
4238
4239         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4240
4241         HWRM_CHECK_RESULT();
4242         HWRM_UNLOCK();
4243
4244         return rc;
4245 }
4246
4247 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4248                                        struct rte_ether_addr *mac)
4249 {
4250         struct hwrm_func_qcfg_input req = {0};
4251         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4252         int rc;
4253
4254         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4255
4256         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4258
4259         HWRM_CHECK_RESULT();
4260
4261         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4262
4263         HWRM_UNLOCK();
4264
4265         return rc;
4266 }
4267
4268 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4269                             void *encaped, size_t ec_size)
4270 {
4271         int rc = 0;
4272         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4273         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4274
4275         if (ec_size > sizeof(req.encap_request))
4276                 return -1;
4277
4278         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4279
4280         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4281         memcpy(req.encap_request, encaped, ec_size);
4282
4283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4284
4285         HWRM_CHECK_RESULT();
4286         HWRM_UNLOCK();
4287
4288         return rc;
4289 }
4290
4291 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
4292                          struct rte_eth_stats *stats, uint8_t rx)
4293 {
4294         int rc = 0;
4295         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4296         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4297
4298         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4299
4300         req.stat_ctx_id = rte_cpu_to_le_32(cid);
4301
4302         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4303
4304         HWRM_CHECK_RESULT();
4305
4306         if (rx) {
4307                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4308                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
4309                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
4310                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4311                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
4312                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
4313                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_discard_pkts);
4314                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_error_pkts);
4315         } else {
4316                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4317                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
4318                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
4319                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4320                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
4321                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
4322         }
4323
4324         HWRM_UNLOCK();
4325
4326         return rc;
4327 }
4328
4329 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4330 {
4331         struct hwrm_port_qstats_input req = {0};
4332         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4333         struct bnxt_pf_info *pf = bp->pf;
4334         int rc;
4335
4336         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4337
4338         req.port_id = rte_cpu_to_le_16(pf->port_id);
4339         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4340         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4342
4343         HWRM_CHECK_RESULT();
4344         HWRM_UNLOCK();
4345
4346         return rc;
4347 }
4348
4349 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4350 {
4351         struct hwrm_port_clr_stats_input req = {0};
4352         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4353         struct bnxt_pf_info *pf = bp->pf;
4354         int rc;
4355
4356         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4357         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4358             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4359                 return 0;
4360
4361         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4362
4363         req.port_id = rte_cpu_to_le_16(pf->port_id);
4364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4365
4366         HWRM_CHECK_RESULT();
4367         HWRM_UNLOCK();
4368
4369         return rc;
4370 }
4371
4372 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4373 {
4374         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4375         struct hwrm_port_led_qcaps_input req = {0};
4376         int rc;
4377
4378         if (BNXT_VF(bp))
4379                 return 0;
4380
4381         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4382         req.port_id = bp->pf->port_id;
4383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4384
4385         HWRM_CHECK_RESULT_SILENT();
4386
4387         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4388                 unsigned int i;
4389
4390                 bp->leds->num_leds = resp->num_leds;
4391                 memcpy(bp->leds, &resp->led0_id,
4392                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4393                 for (i = 0; i < bp->leds->num_leds; i++) {
4394                         struct bnxt_led_info *led = &bp->leds[i];
4395
4396                         uint16_t caps = led->led_state_caps;
4397
4398                         if (!led->led_group_id ||
4399                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4400                                 bp->leds->num_leds = 0;
4401                                 break;
4402                         }
4403                 }
4404         }
4405
4406         HWRM_UNLOCK();
4407
4408         return rc;
4409 }
4410
4411 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4412 {
4413         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4414         struct hwrm_port_led_cfg_input req = {0};
4415         struct bnxt_led_cfg *led_cfg;
4416         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4417         uint16_t duration = 0;
4418         int rc, i;
4419
4420         if (!bp->leds->num_leds || BNXT_VF(bp))
4421                 return -EOPNOTSUPP;
4422
4423         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4424
4425         if (led_on) {
4426                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4427                 duration = rte_cpu_to_le_16(500);
4428         }
4429         req.port_id = bp->pf->port_id;
4430         req.num_leds = bp->leds->num_leds;
4431         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4432         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4433                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4434                 led_cfg->led_id = bp->leds[i].led_id;
4435                 led_cfg->led_state = led_state;
4436                 led_cfg->led_blink_on = duration;
4437                 led_cfg->led_blink_off = duration;
4438                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4439         }
4440
4441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4442
4443         HWRM_CHECK_RESULT();
4444         HWRM_UNLOCK();
4445
4446         return rc;
4447 }
4448
4449 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4450                                uint32_t *length)
4451 {
4452         int rc;
4453         struct hwrm_nvm_get_dir_info_input req = {0};
4454         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4455
4456         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4457
4458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4459
4460         HWRM_CHECK_RESULT();
4461
4462         *entries = rte_le_to_cpu_32(resp->entries);
4463         *length = rte_le_to_cpu_32(resp->entry_length);
4464
4465         HWRM_UNLOCK();
4466         return rc;
4467 }
4468
4469 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4470 {
4471         int rc;
4472         uint32_t dir_entries;
4473         uint32_t entry_length;
4474         uint8_t *buf;
4475         size_t buflen;
4476         rte_iova_t dma_handle;
4477         struct hwrm_nvm_get_dir_entries_input req = {0};
4478         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4479
4480         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4481         if (rc != 0)
4482                 return rc;
4483
4484         *data++ = dir_entries;
4485         *data++ = entry_length;
4486         len -= 2;
4487         memset(data, 0xff, len);
4488
4489         buflen = dir_entries * entry_length;
4490         buf = rte_malloc("nvm_dir", buflen, 0);
4491         if (buf == NULL)
4492                 return -ENOMEM;
4493         dma_handle = rte_malloc_virt2iova(buf);
4494         if (dma_handle == RTE_BAD_IOVA) {
4495                 rte_free(buf);
4496                 PMD_DRV_LOG(ERR,
4497                         "unable to map response address to physical memory\n");
4498                 return -ENOMEM;
4499         }
4500         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4501         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4503
4504         if (rc == 0)
4505                 memcpy(data, buf, len > buflen ? buflen : len);
4506
4507         rte_free(buf);
4508         HWRM_CHECK_RESULT();
4509         HWRM_UNLOCK();
4510
4511         return rc;
4512 }
4513
4514 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4515                              uint32_t offset, uint32_t length,
4516                              uint8_t *data)
4517 {
4518         int rc;
4519         uint8_t *buf;
4520         rte_iova_t dma_handle;
4521         struct hwrm_nvm_read_input req = {0};
4522         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4523
4524         buf = rte_malloc("nvm_item", length, 0);
4525         if (!buf)
4526                 return -ENOMEM;
4527
4528         dma_handle = rte_malloc_virt2iova(buf);
4529         if (dma_handle == RTE_BAD_IOVA) {
4530                 rte_free(buf);
4531                 PMD_DRV_LOG(ERR,
4532                         "unable to map response address to physical memory\n");
4533                 return -ENOMEM;
4534         }
4535         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4536         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4537         req.dir_idx = rte_cpu_to_le_16(index);
4538         req.offset = rte_cpu_to_le_32(offset);
4539         req.len = rte_cpu_to_le_32(length);
4540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4541         if (rc == 0)
4542                 memcpy(data, buf, length);
4543
4544         rte_free(buf);
4545         HWRM_CHECK_RESULT();
4546         HWRM_UNLOCK();
4547
4548         return rc;
4549 }
4550
4551 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4552 {
4553         int rc;
4554         struct hwrm_nvm_erase_dir_entry_input req = {0};
4555         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4556
4557         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4558         req.dir_idx = rte_cpu_to_le_16(index);
4559         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4560         HWRM_CHECK_RESULT();
4561         HWRM_UNLOCK();
4562
4563         return rc;
4564 }
4565
4566
4567 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4568                           uint16_t dir_ordinal, uint16_t dir_ext,
4569                           uint16_t dir_attr, const uint8_t *data,
4570                           size_t data_len)
4571 {
4572         int rc;
4573         struct hwrm_nvm_write_input req = {0};
4574         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4575         rte_iova_t dma_handle;
4576         uint8_t *buf;
4577
4578         buf = rte_malloc("nvm_write", data_len, 0);
4579         if (!buf)
4580                 return -ENOMEM;
4581
4582         dma_handle = rte_malloc_virt2iova(buf);
4583         if (dma_handle == RTE_BAD_IOVA) {
4584                 rte_free(buf);
4585                 PMD_DRV_LOG(ERR,
4586                         "unable to map response address to physical memory\n");
4587                 return -ENOMEM;
4588         }
4589         memcpy(buf, data, data_len);
4590
4591         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4592
4593         req.dir_type = rte_cpu_to_le_16(dir_type);
4594         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4595         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4596         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4597         req.dir_data_length = rte_cpu_to_le_32(data_len);
4598         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4599
4600         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4601
4602         rte_free(buf);
4603         HWRM_CHECK_RESULT();
4604         HWRM_UNLOCK();
4605
4606         return rc;
4607 }
4608
4609 static void
4610 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4611 {
4612         uint32_t *count = cbdata;
4613
4614         *count = *count + 1;
4615 }
4616
4617 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4618                                      struct bnxt_vnic_info *vnic __rte_unused)
4619 {
4620         return 0;
4621 }
4622
4623 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4624 {
4625         uint32_t count = 0;
4626
4627         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4628             &count, bnxt_vnic_count_hwrm_stub);
4629
4630         return count;
4631 }
4632
4633 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4634                                         uint16_t *vnic_ids)
4635 {
4636         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4637         struct hwrm_func_vf_vnic_ids_query_output *resp =
4638                                                 bp->hwrm_cmd_resp_addr;
4639         int rc;
4640
4641         /* First query all VNIC ids */
4642         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4643
4644         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4645         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4646         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4647
4648         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4649                 HWRM_UNLOCK();
4650                 PMD_DRV_LOG(ERR,
4651                 "unable to map VNIC ID table address to physical memory\n");
4652                 return -ENOMEM;
4653         }
4654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4655         HWRM_CHECK_RESULT();
4656         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4657
4658         HWRM_UNLOCK();
4659
4660         return rc;
4661 }
4662
4663 /*
4664  * This function queries the VNIC IDs  for a specified VF. It then calls
4665  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4666  * Then it calls the hwrm_cb function to program this new vnic configuration.
4667  */
4668 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4669         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4670         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4671 {
4672         struct bnxt_vnic_info vnic;
4673         int rc = 0;
4674         int i, num_vnic_ids;
4675         uint16_t *vnic_ids;
4676         size_t vnic_id_sz;
4677         size_t sz;
4678
4679         /* First query all VNIC ids */
4680         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4681         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4682                         RTE_CACHE_LINE_SIZE);
4683         if (vnic_ids == NULL)
4684                 return -ENOMEM;
4685
4686         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4687                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4688
4689         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4690
4691         if (num_vnic_ids < 0)
4692                 return num_vnic_ids;
4693
4694         /* Retrieve VNIC, update bd_stall then update */
4695
4696         for (i = 0; i < num_vnic_ids; i++) {
4697                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4698                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4699                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4700                 if (rc)
4701                         break;
4702                 if (vnic.mru <= 4)      /* Indicates unallocated */
4703                         continue;
4704
4705                 vnic_cb(&vnic, cbdata);
4706
4707                 rc = hwrm_cb(bp, &vnic);
4708                 if (rc)
4709                         break;
4710         }
4711
4712         rte_free(vnic_ids);
4713
4714         return rc;
4715 }
4716
4717 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4718                                               bool on)
4719 {
4720         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4721         struct hwrm_func_cfg_input req = {0};
4722         int rc;
4723
4724         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4725
4726         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4727         req.enables |= rte_cpu_to_le_32(
4728                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4729         req.vlan_antispoof_mode = on ?
4730                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4731                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4733
4734         HWRM_CHECK_RESULT();
4735         HWRM_UNLOCK();
4736
4737         return rc;
4738 }
4739
4740 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4741 {
4742         struct bnxt_vnic_info vnic;
4743         uint16_t *vnic_ids;
4744         size_t vnic_id_sz;
4745         int num_vnic_ids, i;
4746         size_t sz;
4747         int rc;
4748
4749         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4750         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4751                         RTE_CACHE_LINE_SIZE);
4752         if (vnic_ids == NULL)
4753                 return -ENOMEM;
4754
4755         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4756                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4757
4758         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4759         if (rc <= 0)
4760                 goto exit;
4761         num_vnic_ids = rc;
4762
4763         /*
4764          * Loop through to find the default VNIC ID.
4765          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4766          * by sending the hwrm_func_qcfg command to the firmware.
4767          */
4768         for (i = 0; i < num_vnic_ids; i++) {
4769                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4770                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4771                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4772                                         bp->pf->first_vf_id + vf);
4773                 if (rc)
4774                         goto exit;
4775                 if (vnic.func_default) {
4776                         rte_free(vnic_ids);
4777                         return vnic.fw_vnic_id;
4778                 }
4779         }
4780         /* Could not find a default VNIC. */
4781         PMD_DRV_LOG(ERR, "No default VNIC\n");
4782 exit:
4783         rte_free(vnic_ids);
4784         return rc;
4785 }
4786
4787 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4788                          uint16_t dst_id,
4789                          struct bnxt_filter_info *filter)
4790 {
4791         int rc = 0;
4792         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4793         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4794         uint32_t enables = 0;
4795
4796         if (filter->fw_em_filter_id != UINT64_MAX)
4797                 bnxt_hwrm_clear_em_filter(bp, filter);
4798
4799         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4800
4801         req.flags = rte_cpu_to_le_32(filter->flags);
4802
4803         enables = filter->enables |
4804               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4805         req.dst_id = rte_cpu_to_le_16(dst_id);
4806
4807         if (filter->ip_addr_type) {
4808                 req.ip_addr_type = filter->ip_addr_type;
4809                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4810         }
4811         if (enables &
4812             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4813                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4814         if (enables &
4815             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4816                 memcpy(req.src_macaddr, filter->src_macaddr,
4817                        RTE_ETHER_ADDR_LEN);
4818         if (enables &
4819             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4820                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4821                        RTE_ETHER_ADDR_LEN);
4822         if (enables &
4823             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4824                 req.ovlan_vid = filter->l2_ovlan;
4825         if (enables &
4826             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4827                 req.ivlan_vid = filter->l2_ivlan;
4828         if (enables &
4829             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4830                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4831         if (enables &
4832             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4833                 req.ip_protocol = filter->ip_protocol;
4834         if (enables &
4835             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4836                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4837         if (enables &
4838             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4839                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4840         if (enables &
4841             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4842                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4843         if (enables &
4844             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4845                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4846         if (enables &
4847             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4848                 req.mirror_vnic_id = filter->mirror_vnic_id;
4849
4850         req.enables = rte_cpu_to_le_32(enables);
4851
4852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4853
4854         HWRM_CHECK_RESULT();
4855
4856         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4857         HWRM_UNLOCK();
4858
4859         return rc;
4860 }
4861
4862 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4863 {
4864         int rc = 0;
4865         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4866         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4867
4868         if (filter->fw_em_filter_id == UINT64_MAX)
4869                 return 0;
4870
4871         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4872
4873         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4874
4875         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4876
4877         HWRM_CHECK_RESULT();
4878         HWRM_UNLOCK();
4879
4880         filter->fw_em_filter_id = UINT64_MAX;
4881         filter->fw_l2_filter_id = UINT64_MAX;
4882
4883         return 0;
4884 }
4885
4886 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4887                          uint16_t dst_id,
4888                          struct bnxt_filter_info *filter)
4889 {
4890         int rc = 0;
4891         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4892         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4893                                                 bp->hwrm_cmd_resp_addr;
4894         uint32_t enables = 0;
4895
4896         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4897                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4898
4899         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4900
4901         req.flags = rte_cpu_to_le_32(filter->flags);
4902
4903         enables = filter->enables |
4904               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4905         req.dst_id = rte_cpu_to_le_16(dst_id);
4906
4907         if (filter->ip_addr_type) {
4908                 req.ip_addr_type = filter->ip_addr_type;
4909                 enables |=
4910                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4911         }
4912         if (enables &
4913             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4914                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4915         if (enables &
4916             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4917                 memcpy(req.src_macaddr, filter->src_macaddr,
4918                        RTE_ETHER_ADDR_LEN);
4919         if (enables &
4920             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4921                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4922         if (enables &
4923             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4924                 req.ip_protocol = filter->ip_protocol;
4925         if (enables &
4926             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4927                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4928         if (enables &
4929             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4930                 req.src_ipaddr_mask[0] =
4931                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4932         if (enables &
4933             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4934                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4935         if (enables &
4936             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4937                 req.dst_ipaddr_mask[0] =
4938                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4939         if (enables &
4940             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4941                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4942         if (enables &
4943             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4944                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4945         if (enables &
4946             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4947                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4948         if (enables &
4949             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4950                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4951         if (enables &
4952             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4953                 req.mirror_vnic_id = filter->mirror_vnic_id;
4954
4955         req.enables = rte_cpu_to_le_32(enables);
4956
4957         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4958
4959         HWRM_CHECK_RESULT();
4960
4961         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4962         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4963         HWRM_UNLOCK();
4964
4965         return rc;
4966 }
4967
4968 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4969                                 struct bnxt_filter_info *filter)
4970 {
4971         int rc = 0;
4972         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4973         struct hwrm_cfa_ntuple_filter_free_output *resp =
4974                                                 bp->hwrm_cmd_resp_addr;
4975
4976         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4977                 return 0;
4978
4979         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4980
4981         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4982
4983         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4984
4985         HWRM_CHECK_RESULT();
4986         HWRM_UNLOCK();
4987
4988         filter->fw_ntuple_filter_id = UINT64_MAX;
4989
4990         return 0;
4991 }
4992
4993 static int
4994 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4995 {
4996         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4997         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4998         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4999         struct bnxt_rx_queue **rxqs = bp->rx_queues;
5000         uint16_t *ring_tbl = vnic->rss_table;
5001         int nr_ctxs = vnic->num_lb_ctxts;
5002         int max_rings = bp->rx_nr_rings;
5003         int i, j, k, cnt;
5004         int rc = 0;
5005
5006         for (i = 0, k = 0; i < nr_ctxs; i++) {
5007                 struct bnxt_rx_ring_info *rxr;
5008                 struct bnxt_cp_ring_info *cpr;
5009
5010                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5011
5012                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5013                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5014                 req.hash_mode_flags = vnic->hash_mode;
5015
5016                 req.ring_grp_tbl_addr =
5017                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5018                                      i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5019                                      2 * sizeof(*ring_tbl));
5020                 req.hash_key_tbl_addr =
5021                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5022
5023                 req.ring_table_pair_index = i;
5024                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5025
5026                 for (j = 0; j < 64; j++) {
5027                         uint16_t ring_id;
5028
5029                         /* Find next active ring. */
5030                         for (cnt = 0; cnt < max_rings; cnt++) {
5031                                 if (rx_queue_state[k] !=
5032                                                 RTE_ETH_QUEUE_STATE_STOPPED)
5033                                         break;
5034                                 if (++k == max_rings)
5035                                         k = 0;
5036                         }
5037
5038                         /* Return if no rings are active. */
5039                         if (cnt == max_rings) {
5040                                 HWRM_UNLOCK();
5041                                 return 0;
5042                         }
5043
5044                         /* Add rx/cp ring pair to RSS table. */
5045                         rxr = rxqs[k]->rx_ring;
5046                         cpr = rxqs[k]->cp_ring;
5047
5048                         ring_id = rxr->rx_ring_struct->fw_ring_id;
5049                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5050                         ring_id = cpr->cp_ring_struct->fw_ring_id;
5051                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5052
5053                         if (++k == max_rings)
5054                                 k = 0;
5055                 }
5056                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5057                                             BNXT_USE_CHIMP_MB);
5058
5059                 HWRM_CHECK_RESULT();
5060                 HWRM_UNLOCK();
5061         }
5062
5063         return rc;
5064 }
5065
5066 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5067 {
5068         unsigned int rss_idx, fw_idx, i;
5069
5070         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5071                 return 0;
5072
5073         if (!(vnic->rss_table && vnic->hash_type))
5074                 return 0;
5075
5076         if (BNXT_CHIP_P5(bp))
5077                 return bnxt_vnic_rss_configure_p5(bp, vnic);
5078
5079         /*
5080          * Fill the RSS hash & redirection table with
5081          * ring group ids for all VNICs
5082          */
5083         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5084              rss_idx++, fw_idx++) {
5085                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5086                         fw_idx %= bp->rx_cp_nr_rings;
5087                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5088                                 break;
5089                         fw_idx++;
5090                 }
5091
5092                 if (i == bp->rx_cp_nr_rings)
5093                         return 0;
5094
5095                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5096         }
5097
5098         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5099 }
5100
5101 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5102         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5103 {
5104         uint16_t flags;
5105
5106         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5107
5108         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5109         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5110
5111         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5112         req->num_cmpl_dma_aggr_during_int =
5113                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5114
5115         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5116
5117         /* min timer set to 1/2 of interrupt timer */
5118         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5119
5120         /* buf timer set to 1/4 of interrupt timer */
5121         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5122
5123         req->cmpl_aggr_dma_tmr_during_int =
5124                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5125
5126         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5127                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5128         req->flags = rte_cpu_to_le_16(flags);
5129 }
5130
5131 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5132                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5133 {
5134         struct hwrm_ring_aggint_qcaps_input req = {0};
5135         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5136         uint32_t enables;
5137         uint16_t flags;
5138         int rc;
5139
5140         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5141         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5142         HWRM_CHECK_RESULT();
5143
5144         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5145         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5146
5147         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5148                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5149         agg_req->flags = rte_cpu_to_le_16(flags);
5150         enables =
5151          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5152          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5153         agg_req->enables = rte_cpu_to_le_32(enables);
5154
5155         HWRM_UNLOCK();
5156         return rc;
5157 }
5158
5159 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5160                         struct bnxt_coal *coal, uint16_t ring_id)
5161 {
5162         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5163         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5164                                                 bp->hwrm_cmd_resp_addr;
5165         int rc;
5166
5167         /* Set ring coalesce parameters only for 100G NICs */
5168         if (BNXT_CHIP_P5(bp)) {
5169                 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5170                         return -1;
5171         } else if (bnxt_stratus_device(bp)) {
5172                 bnxt_hwrm_set_coal_params(coal, &req);
5173         } else {
5174                 return 0;
5175         }
5176
5177         HWRM_PREP(&req,
5178                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5179                   BNXT_USE_CHIMP_MB);
5180         req.ring_id = rte_cpu_to_le_16(ring_id);
5181         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5182         HWRM_CHECK_RESULT();
5183         HWRM_UNLOCK();
5184         return 0;
5185 }
5186
5187 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
5188 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5189 {
5190         struct hwrm_func_backing_store_qcaps_input req = {0};
5191         struct hwrm_func_backing_store_qcaps_output *resp =
5192                 bp->hwrm_cmd_resp_addr;
5193         struct bnxt_ctx_pg_info *ctx_pg;
5194         struct bnxt_ctx_mem_info *ctx;
5195         int total_alloc_len;
5196         int rc, i, tqm_rings;
5197
5198         if (!BNXT_CHIP_P5(bp) ||
5199             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5200             BNXT_VF(bp) ||
5201             bp->ctx)
5202                 return 0;
5203
5204         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5206         HWRM_CHECK_RESULT_SILENT();
5207
5208         total_alloc_len = sizeof(*ctx);
5209         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5210                           RTE_CACHE_LINE_SIZE);
5211         if (!ctx) {
5212                 rc = -ENOMEM;
5213                 goto ctx_err;
5214         }
5215
5216         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5217         ctx->qp_min_qp1_entries =
5218                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5219         ctx->qp_max_l2_entries =
5220                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5221         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5222         ctx->srq_max_l2_entries =
5223                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5224         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5225         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5226         ctx->cq_max_l2_entries =
5227                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5228         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5229         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5230         ctx->vnic_max_vnic_entries =
5231                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5232         ctx->vnic_max_ring_table_entries =
5233                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5234         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5235         ctx->stat_max_entries =
5236                 rte_le_to_cpu_32(resp->stat_max_entries);
5237         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5238         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5239         ctx->tqm_min_entries_per_ring =
5240                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5241         ctx->tqm_max_entries_per_ring =
5242                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5243         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5244         if (!ctx->tqm_entries_multiple)
5245                 ctx->tqm_entries_multiple = 1;
5246         ctx->mrav_max_entries =
5247                 rte_le_to_cpu_32(resp->mrav_max_entries);
5248         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5249         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5250         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5251         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5252
5253         ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5254                                   RTE_MIN(ctx->tqm_fp_rings_count,
5255                                           BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5256                                   bp->max_q;
5257
5258         /* Check if the ext ring count needs to be counted.
5259          * Ext ring count is available only with new FW so we should not
5260          * look at the field on older FW.
5261          */
5262         if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5263             bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5264                 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5265                 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5266                                                   ctx->tqm_fp_rings_count);
5267         }
5268
5269         tqm_rings = ctx->tqm_fp_rings_count + 1;
5270
5271         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5272                             sizeof(*ctx_pg) * tqm_rings,
5273                             RTE_CACHE_LINE_SIZE);
5274         if (!ctx_pg) {
5275                 rc = -ENOMEM;
5276                 goto ctx_err;
5277         }
5278         for (i = 0; i < tqm_rings; i++, ctx_pg++)
5279                 ctx->tqm_mem[i] = ctx_pg;
5280
5281         bp->ctx = ctx;
5282 ctx_err:
5283         HWRM_UNLOCK();
5284         return rc;
5285 }
5286
5287 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5288 {
5289         struct hwrm_func_backing_store_cfg_input req = {0};
5290         struct hwrm_func_backing_store_cfg_output *resp =
5291                 bp->hwrm_cmd_resp_addr;
5292         struct bnxt_ctx_mem_info *ctx = bp->ctx;
5293         struct bnxt_ctx_pg_info *ctx_pg;
5294         uint32_t *num_entries;
5295         uint64_t *pg_dir;
5296         uint8_t *pg_attr;
5297         uint32_t ena;
5298         int i, rc;
5299
5300         if (!ctx)
5301                 return 0;
5302
5303         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5304         req.enables = rte_cpu_to_le_32(enables);
5305
5306         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5307                 ctx_pg = &ctx->qp_mem;
5308                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5309                 req.qp_num_qp1_entries =
5310                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5311                 req.qp_num_l2_entries =
5312                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5313                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5314                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5315                                       &req.qpc_pg_size_qpc_lvl,
5316                                       &req.qpc_page_dir);
5317         }
5318
5319         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5320                 ctx_pg = &ctx->srq_mem;
5321                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5322                 req.srq_num_l2_entries =
5323                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5324                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5325                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5326                                       &req.srq_pg_size_srq_lvl,
5327                                       &req.srq_page_dir);
5328         }
5329
5330         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5331                 ctx_pg = &ctx->cq_mem;
5332                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5333                 req.cq_num_l2_entries =
5334                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5335                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5336                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5337                                       &req.cq_pg_size_cq_lvl,
5338                                       &req.cq_page_dir);
5339         }
5340
5341         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5342                 ctx_pg = &ctx->vnic_mem;
5343                 req.vnic_num_vnic_entries =
5344                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5345                 req.vnic_num_ring_table_entries =
5346                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5347                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5348                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5349                                       &req.vnic_pg_size_vnic_lvl,
5350                                       &req.vnic_page_dir);
5351         }
5352
5353         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5354                 ctx_pg = &ctx->stat_mem;
5355                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5356                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5357                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5358                                       &req.stat_pg_size_stat_lvl,
5359                                       &req.stat_page_dir);
5360         }
5361
5362         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5363         num_entries = &req.tqm_sp_num_entries;
5364         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5365         pg_dir = &req.tqm_sp_page_dir;
5366         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5367         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5368                 if (!(enables & ena))
5369                         continue;
5370
5371                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5372
5373                 ctx_pg = ctx->tqm_mem[i];
5374                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5375                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5376         }
5377
5378         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5379                 /* DPDK does not need to configure MRAV and TIM type.
5380                  * So we are skipping over MRAV and TIM. Skip to configure
5381                  * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5382                  */
5383                 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5384                 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5385                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5386                                       &req.tqm_ring8_pg_size_tqm_ring_lvl,
5387                                       &req.tqm_ring8_page_dir);
5388         }
5389
5390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5391         HWRM_CHECK_RESULT();
5392         HWRM_UNLOCK();
5393
5394         return rc;
5395 }
5396
5397 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5398 {
5399         struct hwrm_port_qstats_ext_input req = {0};
5400         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5401         struct bnxt_pf_info *pf = bp->pf;
5402         int rc;
5403
5404         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5405               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5406                 return 0;
5407
5408         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5409
5410         req.port_id = rte_cpu_to_le_16(pf->port_id);
5411         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5412                 req.tx_stat_host_addr =
5413                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5414                 req.tx_stat_size =
5415                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5416         }
5417         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5418                 req.rx_stat_host_addr =
5419                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5420                 req.rx_stat_size =
5421                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5422         }
5423         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5424
5425         if (rc) {
5426                 bp->fw_rx_port_stats_ext_size = 0;
5427                 bp->fw_tx_port_stats_ext_size = 0;
5428         } else {
5429                 bp->fw_rx_port_stats_ext_size =
5430                         rte_le_to_cpu_16(resp->rx_stat_size);
5431                 bp->fw_tx_port_stats_ext_size =
5432                         rte_le_to_cpu_16(resp->tx_stat_size);
5433         }
5434
5435         HWRM_CHECK_RESULT();
5436         HWRM_UNLOCK();
5437
5438         return rc;
5439 }
5440
5441 int
5442 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5443 {
5444         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5445         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5446                 bp->hwrm_cmd_resp_addr;
5447         int rc = 0;
5448
5449         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5450         req.tunnel_type = type;
5451         req.dest_fid = bp->fw_fid;
5452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5453         HWRM_CHECK_RESULT();
5454
5455         HWRM_UNLOCK();
5456
5457         return rc;
5458 }
5459
5460 int
5461 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5462 {
5463         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5464         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5465                 bp->hwrm_cmd_resp_addr;
5466         int rc = 0;
5467
5468         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5469         req.tunnel_type = type;
5470         req.dest_fid = bp->fw_fid;
5471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5472         HWRM_CHECK_RESULT();
5473
5474         HWRM_UNLOCK();
5475
5476         return rc;
5477 }
5478
5479 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5480 {
5481         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5482         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5483                 bp->hwrm_cmd_resp_addr;
5484         int rc = 0;
5485
5486         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5487         req.src_fid = bp->fw_fid;
5488         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5489         HWRM_CHECK_RESULT();
5490
5491         if (type)
5492                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5493
5494         HWRM_UNLOCK();
5495
5496         return rc;
5497 }
5498
5499 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5500                                    uint16_t *dst_fid)
5501 {
5502         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5503         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5504                 bp->hwrm_cmd_resp_addr;
5505         int rc = 0;
5506
5507         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5508         req.src_fid = bp->fw_fid;
5509         req.tunnel_type = tun_type;
5510         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5511         HWRM_CHECK_RESULT();
5512
5513         if (dst_fid)
5514                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5515
5516         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5517
5518         HWRM_UNLOCK();
5519
5520         return rc;
5521 }
5522
5523 int bnxt_hwrm_set_mac(struct bnxt *bp)
5524 {
5525         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5526         struct hwrm_func_vf_cfg_input req = {0};
5527         int rc = 0;
5528
5529         if (!BNXT_VF(bp))
5530                 return 0;
5531
5532         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5533
5534         req.enables =
5535                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5536         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5537
5538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5539
5540         HWRM_CHECK_RESULT();
5541
5542         HWRM_UNLOCK();
5543
5544         return rc;
5545 }
5546
5547 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5548 {
5549         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5550         struct hwrm_func_drv_if_change_input req = {0};
5551         uint32_t flags;
5552         int rc;
5553
5554         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5555                 return 0;
5556
5557         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5558          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5559          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5560          */
5561         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5562                 return 0;
5563
5564         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5565
5566         if (up)
5567                 req.flags =
5568                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5569
5570         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5571
5572         HWRM_CHECK_RESULT();
5573         flags = rte_le_to_cpu_32(resp->flags);
5574         HWRM_UNLOCK();
5575
5576         if (!up)
5577                 return 0;
5578
5579         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5580                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5581                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5582         }
5583
5584         return 0;
5585 }
5586
5587 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5588 {
5589         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5590         struct bnxt_error_recovery_info *info = bp->recovery_info;
5591         struct hwrm_error_recovery_qcfg_input req = {0};
5592         uint32_t flags = 0;
5593         unsigned int i;
5594         int rc;
5595
5596         /* Older FW does not have error recovery support */
5597         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5598                 return 0;
5599
5600         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5601
5602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5603
5604         HWRM_CHECK_RESULT();
5605
5606         flags = rte_le_to_cpu_32(resp->flags);
5607         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5608                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5609         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5610                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5611
5612         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5613             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5614                 rc = -EINVAL;
5615                 goto err;
5616         }
5617
5618         /* FW returned values are in units of 100msec */
5619         info->driver_polling_freq =
5620                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5621         info->master_func_wait_period =
5622                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5623         info->normal_func_wait_period =
5624                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5625         info->master_func_wait_period_after_reset =
5626                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5627         info->max_bailout_time_after_reset =
5628                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5629         info->status_regs[BNXT_FW_STATUS_REG] =
5630                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5631         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5632                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5633         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5634                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5635         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5636                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5637         info->reg_array_cnt =
5638                 rte_le_to_cpu_32(resp->reg_array_cnt);
5639
5640         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5641                 rc = -EINVAL;
5642                 goto err;
5643         }
5644
5645         for (i = 0; i < info->reg_array_cnt; i++) {
5646                 info->reset_reg[i] =
5647                         rte_le_to_cpu_32(resp->reset_reg[i]);
5648                 info->reset_reg_val[i] =
5649                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5650                 info->delay_after_reset[i] =
5651                         resp->delay_after_reset[i];
5652         }
5653 err:
5654         HWRM_UNLOCK();
5655
5656         /* Map the FW status registers */
5657         if (!rc)
5658                 rc = bnxt_map_fw_health_status_regs(bp);
5659
5660         if (rc) {
5661                 rte_free(bp->recovery_info);
5662                 bp->recovery_info = NULL;
5663         }
5664         return rc;
5665 }
5666
5667 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5668 {
5669         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5670         struct hwrm_fw_reset_input req = {0};
5671         int rc;
5672
5673         if (!BNXT_PF(bp))
5674                 return -EOPNOTSUPP;
5675
5676         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5677
5678         req.embedded_proc_type =
5679                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5680         req.selfrst_status =
5681                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5682         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5683
5684         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5685                                     BNXT_USE_KONG(bp));
5686
5687         HWRM_CHECK_RESULT();
5688         HWRM_UNLOCK();
5689
5690         return rc;
5691 }
5692
5693 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5694 {
5695         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5696         struct hwrm_port_ts_query_input req = {0};
5697         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5698         uint32_t flags = 0;
5699         int rc;
5700
5701         if (!ptp)
5702                 return 0;
5703
5704         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5705
5706         switch (path) {
5707         case BNXT_PTP_FLAGS_PATH_TX:
5708                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5709                 break;
5710         case BNXT_PTP_FLAGS_PATH_RX:
5711                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5712                 break;
5713         case BNXT_PTP_FLAGS_CURRENT_TIME:
5714                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5715                 break;
5716         }
5717
5718         req.flags = rte_cpu_to_le_32(flags);
5719         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5720
5721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5722
5723         HWRM_CHECK_RESULT();
5724
5725         if (timestamp) {
5726                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5727                 *timestamp |=
5728                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5729         }
5730         HWRM_UNLOCK();
5731
5732         return rc;
5733 }
5734
5735 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5736 {
5737         int rc = 0;
5738
5739         struct hwrm_cfa_counter_qcaps_input req = {0};
5740         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5741
5742         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5743                 PMD_DRV_LOG(DEBUG,
5744                             "Not a PF or trusted VF. Command not supported\n");
5745                 return 0;
5746         }
5747
5748         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5749         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5751
5752         HWRM_CHECK_RESULT();
5753         if (max_fc)
5754                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5755         HWRM_UNLOCK();
5756
5757         return 0;
5758 }
5759
5760 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5761 {
5762         int rc = 0;
5763         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5764         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5765
5766         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5767                 PMD_DRV_LOG(DEBUG,
5768                             "Not a PF or trusted VF. Command not supported\n");
5769                 return 0;
5770         }
5771
5772         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5773
5774         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5775         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5776         req.page_dir = rte_cpu_to_le_64(dma_addr);
5777
5778         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5779
5780         HWRM_CHECK_RESULT();
5781         if (ctx_id) {
5782                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5783                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5784         }
5785         HWRM_UNLOCK();
5786
5787         return 0;
5788 }
5789
5790 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5791 {
5792         int rc = 0;
5793         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5794         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5795
5796         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5797                 PMD_DRV_LOG(DEBUG,
5798                             "Not a PF or trusted VF. Command not supported\n");
5799                 return 0;
5800         }
5801
5802         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5803
5804         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5805
5806         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5807
5808         HWRM_CHECK_RESULT();
5809         HWRM_UNLOCK();
5810
5811         return rc;
5812 }
5813
5814 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5815                               uint16_t cntr, uint16_t ctx_id,
5816                               uint32_t num_entries, bool enable)
5817 {
5818         struct hwrm_cfa_counter_cfg_input req = {0};
5819         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5820         uint16_t flags = 0;
5821         int rc;
5822
5823         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5824                 PMD_DRV_LOG(DEBUG,
5825                             "Not a PF or trusted VF. Command not supported\n");
5826                 return 0;
5827         }
5828
5829         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5830
5831         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5832         req.counter_type = rte_cpu_to_le_16(cntr);
5833         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5834                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5835         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5836         if (dir == BNXT_DIR_RX)
5837                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5838         else if (dir == BNXT_DIR_TX)
5839                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5840         req.flags = rte_cpu_to_le_16(flags);
5841         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5842         req.num_entries = rte_cpu_to_le_32(num_entries);
5843
5844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5845         HWRM_CHECK_RESULT();
5846         HWRM_UNLOCK();
5847
5848         return 0;
5849 }
5850
5851 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5852                                  enum bnxt_flow_dir dir,
5853                                  uint16_t cntr,
5854                                  uint16_t num_entries)
5855 {
5856         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5857         struct hwrm_cfa_counter_qstats_input req = {0};
5858         uint16_t flow_ctx_id = 0;
5859         uint16_t flags = 0;
5860         int rc = 0;
5861
5862         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5863                 PMD_DRV_LOG(DEBUG,
5864                             "Not a PF or trusted VF. Command not supported\n");
5865                 return 0;
5866         }
5867
5868         if (dir == BNXT_DIR_RX) {
5869                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5870                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5871         } else if (dir == BNXT_DIR_TX) {
5872                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5873                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5874         }
5875
5876         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5877         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5878         req.counter_type = rte_cpu_to_le_16(cntr);
5879         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5880         req.num_entries = rte_cpu_to_le_16(num_entries);
5881         req.flags = rte_cpu_to_le_16(flags);
5882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5883
5884         HWRM_CHECK_RESULT();
5885         HWRM_UNLOCK();
5886
5887         return 0;
5888 }
5889
5890 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5891                                 uint16_t *first_vf_id)
5892 {
5893         int rc = 0;
5894         struct hwrm_func_qcaps_input req = {.req_type = 0 };
5895         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5896
5897         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
5898
5899         req.fid = rte_cpu_to_le_16(fid);
5900
5901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5902
5903         HWRM_CHECK_RESULT();
5904
5905         if (first_vf_id)
5906                 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
5907
5908         HWRM_UNLOCK();
5909
5910         return rc;
5911 }
5912
5913 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
5914 {
5915         struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5916         struct hwrm_cfa_pair_alloc_input req = {0};
5917         int rc;
5918
5919         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5920                 PMD_DRV_LOG(DEBUG,
5921                             "Not a PF or trusted VF. Command not supported\n");
5922                 return 0;
5923         }
5924
5925         HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
5926         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5927         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5928                  bp->eth_dev->data->name, rep_bp->vf_id);
5929
5930         req.pf_b_id = rep_bp->parent_pf_idx;
5931         req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5932                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5933         req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
5934         req.host_b_id = 1; /* TBD - Confirm if this is OK */
5935
5936         req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
5937                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
5938         req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
5939                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
5940         req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
5941                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
5942         req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
5943                         HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
5944
5945         req.q_ab = rep_bp->rep_q_r2f;
5946         req.q_ba = rep_bp->rep_q_f2r;
5947         req.fc_ab = rep_bp->rep_fc_r2f;
5948         req.fc_ba = rep_bp->rep_fc_f2r;
5949
5950         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5951         HWRM_CHECK_RESULT();
5952
5953         HWRM_UNLOCK();
5954         PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
5955                     BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
5956         return rc;
5957 }
5958
5959 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
5960 {
5961         struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
5962         struct hwrm_cfa_pair_free_input req = {0};
5963         int rc;
5964
5965         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5966                 PMD_DRV_LOG(DEBUG,
5967                             "Not a PF or trusted VF. Command not supported\n");
5968                 return 0;
5969         }
5970
5971         HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
5972         snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
5973                  bp->eth_dev->data->name, rep_bp->vf_id);
5974         req.pf_b_id = rep_bp->parent_pf_idx;
5975         req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
5976         req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
5977                                                 rte_cpu_to_le_16(rep_bp->vf_id);
5978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5979         HWRM_CHECK_RESULT();
5980         HWRM_UNLOCK();
5981         PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
5982                     rep_bp->vf_id);
5983         return rc;
5984 }
5985
5986 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5987 {
5988         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5989                                         bp->hwrm_cmd_resp_addr;
5990         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5991         uint32_t flags = 0;
5992         int rc = 0;
5993
5994         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5995                 return 0;
5996
5997         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5998                 PMD_DRV_LOG(DEBUG,
5999                             "Not a PF or trusted VF. Command not supported\n");
6000                 return 0;
6001         }
6002
6003         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_CHIMP_MB);
6004         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6005
6006         HWRM_CHECK_RESULT();
6007         flags = rte_le_to_cpu_32(resp->flags);
6008         HWRM_UNLOCK();
6009
6010         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_RFS_RING_TBL_IDX_V2_SUPPORTED)
6011                 bp->flags |= BNXT_FLAG_FLOW_CFA_RFS_RING_TBL_IDX_V2;
6012         else
6013                 bp->flags |= BNXT_FLAG_RFS_NEEDS_VNIC;
6014
6015         return rc;
6016 }
6017
6018 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6019                             uint32_t echo_req_data2)
6020 {
6021         struct hwrm_func_echo_response_input req = {0};
6022         struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6023         int rc;
6024
6025         HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6026         req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6027         req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6028
6029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6030
6031         HWRM_CHECK_RESULT();
6032         HWRM_UNLOCK();
6033
6034         return rc;
6035 }
6036
6037 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6038 {
6039         struct hwrm_ver_get_input req = {.req_type = 0 };
6040         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6041         int rc = 0;
6042
6043         bp->max_req_len = HWRM_MAX_REQ_LEN;
6044         bp->max_resp_len = BNXT_PAGE_SIZE;
6045         bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6046
6047         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6048         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6049         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6050         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6051
6052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6053
6054         HWRM_CHECK_RESULT_SILENT();
6055
6056         if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6057                 rc = -EAGAIN;
6058
6059         HWRM_UNLOCK();
6060
6061         return rc;
6062 }