drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc > 0) \
 223                         rc = -EINVAL; \
 224                 return rc; \
 225         } \
 226         if (resp->error_code) { \
 227                 rc = rte_le_to_cpu_16(resp->error_code); \
 228                 if (resp->resp_len >= 16) { \
 229                         struct hwrm_err_output *tmp_hwrm_err_op = \
 230                                                 (void *)resp; \
 231                         PMD_DRV_LOG(ERR, \
 232                                 "error %d:%d:%08x:%04x\n", \
 233                                 rc, tmp_hwrm_err_op->cmd_err, \
 234                                 rte_le_to_cpu_32(\
 235                                         tmp_hwrm_err_op->opaque_0), \
 236                                 rte_le_to_cpu_16(\
 237                                         tmp_hwrm_err_op->opaque_1)); \
 238                 } else { \
 239                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 240                 } \
 241                 rte_spinlock_unlock(&bp->hwrm_lock); \
 242                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 243                         rc = -EACCES; \
 244                 else if (rc > 0) \
 245                         rc = -EINVAL; \
 246                 return rc; \
 247         } \
 248 } while (0)
 249
 250 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 251
 252 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 253 {
 254         int rc = 0;
 255         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 256         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 257
 258         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 259         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 260         req.mask = 0;
 261
 262         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 263
 264         HWRM_CHECK_RESULT();
 265         HWRM_UNLOCK();
 266
 267         return rc;
 268 }
 269
 270 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 271                                  struct bnxt_vnic_info *vnic,
 272                                  uint16_t vlan_count,
 273                                  struct bnxt_vlan_table_entry *vlan_table)
 274 {
 275         int rc = 0;
 276         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 277         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 278         uint32_t mask = 0;
 279
 280         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 281                 return rc;
 282
 283         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 284         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 285
 286         /* FIXME add multicast flag, when multicast adding options is supported
 287          * by ethtool.
 288          */
 289         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 290                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 291         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 292                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 293         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 294                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 295         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 296                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 297         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 298                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 299         if (vnic->mc_addr_cnt) {
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 301                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 302                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 303         }
 304         if (vlan_table) {
 305                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 306                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 307                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 308                          rte_mem_virt2iova(vlan_table));
 309                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 310         }
 311         req.mask = rte_cpu_to_le_32(mask);
 312
 313         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 314
 315         HWRM_CHECK_RESULT();
 316         HWRM_UNLOCK();
 317
 318         return rc;
 319 }
 320
 321 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 322                         uint16_t vlan_count,
 323                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 324 {
 325         int rc = 0;
 326         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 327         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 328                                                 bp->hwrm_cmd_resp_addr;
 329
 330         /*
 331          * Older HWRM versions did not support this command, and the set_rx_mask
 332          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 333          * removed from set_rx_mask call, and this command was added.
 334          *
 335          * This command is also present from 1.7.8.11 and higher,
 336          * as well as 1.7.8.0
 337          */
 338         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 339                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 340                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 341                                         (11)))
 342                                 return 0;
 343                 }
 344         }
 345         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 346         req.fid = rte_cpu_to_le_16(fid);
 347
 348         req.vlan_tag_mask_tbl_addr =
 349                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 350         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 351
 352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 353
 354         HWRM_CHECK_RESULT();
 355         HWRM_UNLOCK();
 356
 357         return rc;
 358 }
 359
 360 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 361                            struct bnxt_filter_info *filter)
 362 {
 363         int rc = 0;
 364         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 365         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 366
 367         if (filter->fw_l2_filter_id == UINT64_MAX)
 368                 return 0;
 369
 370         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 371
 372         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 373
 374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 375
 376         HWRM_CHECK_RESULT();
 377         HWRM_UNLOCK();
 378
 379         filter->fw_l2_filter_id = UINT64_MAX;
 380
 381         return 0;
 382 }
 383
 384 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 385                          uint16_t dst_id,
 386                          struct bnxt_filter_info *filter)
 387 {
 388         int rc = 0;
 389         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 390         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 391         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 392         const struct rte_eth_vmdq_rx_conf *conf =
 393                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 394         uint32_t enables = 0;
 395         uint16_t j = dst_id - 1;
 396
 397         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 398         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 399             conf->pool_map[j].pools & (1UL << j)) {
 400                 PMD_DRV_LOG(DEBUG,
 401                         "Add vlan %u to vmdq pool %u\n",
 402                         conf->pool_map[j].vlan_id, j);
 403
 404                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 405                 filter->enables |=
 406                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 407                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 408         }
 409
 410         if (filter->fw_l2_filter_id != UINT64_MAX)
 411                 bnxt_hwrm_clear_l2_filter(bp, filter);
 412
 413         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 414
 415         req.flags = rte_cpu_to_le_32(filter->flags);
 416         req.flags |=
 417         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 418
 419         enables = filter->enables |
 420               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 421         req.dst_id = rte_cpu_to_le_16(dst_id);
 422
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 425                 memcpy(req.l2_addr, filter->l2_addr,
 426                        RTE_ETHER_ADDR_LEN);
 427         if (enables &
 428             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 429                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 430                        RTE_ETHER_ADDR_LEN);
 431         if (enables &
 432             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 433                 req.l2_ovlan = filter->l2_ovlan;
 434         if (enables &
 435             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 436                 req.l2_ivlan = filter->l2_ivlan;
 437         if (enables &
 438             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 439                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 440         if (enables &
 441             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 442                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 443         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 444                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 445         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 446                 req.src_type = filter->src_type;
 447
 448         req.enables = rte_cpu_to_le_32(enables);
 449
 450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 451
 452         HWRM_CHECK_RESULT();
 453
 454         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 455         HWRM_UNLOCK();
 456
 457         return rc;
 458 }
 459
 460 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 461 {
 462         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 463         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 464         uint32_t flags = 0;
 465         int rc;
 466
 467         if (!ptp)
 468                 return 0;
 469
 470         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 471
 472         if (ptp->rx_filter)
 473                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 474         else
 475                 flags |=
 476                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 477         if (ptp->tx_tstamp_en)
 478                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 479         else
 480                 flags |=
 481                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 482         req.flags = rte_cpu_to_le_32(flags);
 483         req.enables = rte_cpu_to_le_32
 484                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 485         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 486
 487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 488         HWRM_UNLOCK();
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 494 {
 495         int rc = 0;
 496         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 497         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 498         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 499
 500 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 501         if (ptp)
 502                 return 0;
 503
 504         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 505
 506         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509
 510         HWRM_CHECK_RESULT();
 511
 512         if (!BNXT_CHIP_THOR(bp) &&
 513             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 514                 return 0;
 515
 516         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 517                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 518
 519         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 520         if (!ptp)
 521                 return -ENOMEM;
 522
 523         if (!BNXT_CHIP_THOR(bp)) {
 524                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 525                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 526                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 527                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 528                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 529                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 530                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 531                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 532                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 533                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 534                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 535                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 536                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 537                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 538                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 539                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 540                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 541                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 542         }
 543
 544         ptp->bp = bp;
 545         bp->ptp_cfg = ptp;
 546
 547         return 0;
 548 }
 549
 550 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 551 {
 552         int rc = 0;
 553         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 554         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 555         uint16_t new_max_vfs;
 556         uint32_t flags;
 557         int i;
 558
 559         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 560
 561         req.fid = rte_cpu_to_le_16(0xffff);
 562
 563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 564
 565         HWRM_CHECK_RESULT();
 566
 567         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 568         flags = rte_le_to_cpu_32(resp->flags);
 569         if (BNXT_PF(bp)) {
 570                 bp->pf.port_id = resp->port_id;
 571                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 572                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 573                 new_max_vfs = bp->pdev->max_vfs;
 574                 if (new_max_vfs != bp->pf.max_vfs) {
 575                         if (bp->pf.vf_info)
 576                                 rte_free(bp->pf.vf_info);
 577                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 578                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 579                         bp->pf.max_vfs = new_max_vfs;
 580                         for (i = 0; i < new_max_vfs; i++) {
 581                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 582                                 bp->pf.vf_info[i].vlan_table =
 583                                         rte_zmalloc("VF VLAN table",
 584                                                     getpagesize(),
 585                                                     getpagesize());
 586                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 587                                         PMD_DRV_LOG(ERR,
 588                                         "Fail to alloc VLAN table for VF %d\n",
 589                                         i);
 590                                 else
 591                                         rte_mem_lock_page(
 592                                                 bp->pf.vf_info[i].vlan_table);
 593                                 bp->pf.vf_info[i].vlan_as_table =
 594                                         rte_zmalloc("VF VLAN AS table",
 595                                                     getpagesize(),
 596                                                     getpagesize());
 597                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 598                                         PMD_DRV_LOG(ERR,
 599                                         "Alloc VLAN AS table for VF %d fail\n",
 600                                         i);
 601                                 else
 602                                         rte_mem_lock_page(
 603                                                bp->pf.vf_info[i].vlan_as_table);
 604                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 605                         }
 606                 }
 607         }
 608
 609         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 610         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 611         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 612         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 613         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 614         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 615         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 616         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 617         bp->max_l2_ctx =
 618                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 619         /* TODO: For now, do not support VMDq/RFS on VFs. */
 620         if (BNXT_PF(bp)) {
 621                 if (bp->pf.max_vfs)
 622                         bp->max_vnics = 1;
 623                 else
 624                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 625         } else {
 626                 bp->max_vnics = 1;
 627         }
 628         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 629         if (BNXT_PF(bp)) {
 630                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 631                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 632                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 633                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 634                         HWRM_UNLOCK();
 635                         bnxt_hwrm_ptp_qcfg(bp);
 636                 }
 637         }
 638
 639         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 640                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 641
 642         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 643                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 644                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 645         } else {
 646                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 647         }
 648
 649         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 650                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 651         else
 652                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 653
 654         HWRM_UNLOCK();
 655
 656         return rc;
 657 }
 658
 659 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 660 {
 661         int rc;
 662
 663         rc = __bnxt_hwrm_func_qcaps(bp);
 664         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 665                 rc = bnxt_alloc_ctx_mem(bp);
 666                 if (rc)
 667                         return rc;
 668
 669                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 670                 if (!rc)
 671                         bp->flags |= BNXT_FLAG_NEW_RM;
 672         }
 673
 674         return rc;
 675 }
 676
 677 int bnxt_hwrm_func_reset(struct bnxt *bp)
 678 {
 679         int rc = 0;
 680         struct hwrm_func_reset_input req = {.req_type = 0 };
 681         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 682
 683         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 684
 685         req.enables = rte_cpu_to_le_32(0);
 686
 687         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 688
 689         HWRM_CHECK_RESULT();
 690         HWRM_UNLOCK();
 691
 692         return rc;
 693 }
 694
 695 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 696 {
 697         int rc;
 698         uint32_t flags = 0;
 699         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 700         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 701
 702         if (bp->flags & BNXT_FLAG_REGISTERED)
 703                 return 0;
 704
 705         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 706         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 707                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 708
 709         /* PFs and trusted VFs should indicate the support of the
 710          * Master capability on non Stingray platform
 711          */
 712         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 713                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 714
 715         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 716         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 717                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 718         req.ver_maj = RTE_VER_YEAR;
 719         req.ver_min = RTE_VER_MONTH;
 720         req.ver_upd = RTE_VER_MINOR;
 721
 722         if (BNXT_PF(bp)) {
 723                 req.enables |= rte_cpu_to_le_32(
 724                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 725                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 726                        RTE_MIN(sizeof(req.vf_req_fwd),
 727                                sizeof(bp->pf.vf_req_fwd)));
 728
 729                 /*
 730                  * PF can sniff HWRM API issued by VF. This can be set up by
 731                  * linux driver and inherited by the DPDK PF driver. Clear
 732                  * this HWRM sniffer list in FW because DPDK PF driver does
 733                  * not support this.
 734                  */
 735                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 736         }
 737
 738         req.flags = rte_cpu_to_le_32(flags);
 739
 740         req.async_event_fwd[0] |=
 741                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 742                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 743                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 744                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 745                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 746         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 747                 req.async_event_fwd[0] |=
 748                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 749         req.async_event_fwd[1] |=
 750                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 751                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 752
 753         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 754
 755         HWRM_CHECK_RESULT();
 756
 757         flags = rte_le_to_cpu_32(resp->flags);
 758         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 759                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 760
 761         HWRM_UNLOCK();
 762
 763         bp->flags |= BNXT_FLAG_REGISTERED;
 764
 765         return rc;
 766 }
 767
 768 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 769 {
 770         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 771                 return 0;
 772
 773         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 774 }
 775
 776 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 777 {
 778         int rc;
 779         uint32_t flags = 0;
 780         uint32_t enables;
 781         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 782         struct hwrm_func_vf_cfg_input req = {0};
 783
 784         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 785
 786         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 787                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 788                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 789                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 790                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 791
 792         if (BNXT_HAS_RING_GRPS(bp)) {
 793                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 794                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 795         }
 796
 797         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 798         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 799                                             AGG_RING_MULTIPLIER);
 800         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 801                                              bp->tx_nr_rings +
 802                                              BNXT_NUM_ASYNC_CPR(bp));
 803         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 804                                               bp->tx_nr_rings +
 805                                               BNXT_NUM_ASYNC_CPR(bp));
 806         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 807         if (bp->vf_resv_strategy ==
 808             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 809                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 810                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 811                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 812                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 813                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 814                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 815         }
 816
 817         if (test)
 818                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 819                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 820                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 821                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 822                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 823                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 824
 825         if (test && BNXT_HAS_RING_GRPS(bp))
 826                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 827
 828         req.flags = rte_cpu_to_le_32(flags);
 829         req.enables |= rte_cpu_to_le_32(enables);
 830
 831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 832
 833         if (test)
 834                 HWRM_CHECK_RESULT_SILENT();
 835         else
 836                 HWRM_CHECK_RESULT();
 837
 838         HWRM_UNLOCK();
 839         return rc;
 840 }
 841
 842 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 843 {
 844         int rc;
 845         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 846         struct hwrm_func_resource_qcaps_input req = {0};
 847
 848         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 849         req.fid = rte_cpu_to_le_16(0xffff);
 850
 851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 852
 853         HWRM_CHECK_RESULT();
 854
 855         if (BNXT_VF(bp)) {
 856                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 857                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 858                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 859                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 860                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 861                 /* func_resource_qcaps does not return max_rx_em_flows.
 862                  * So use the value provided by func_qcaps.
 863                  */
 864                 bp->max_l2_ctx =
 865                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 866                         bp->max_rx_em_flows;
 867                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 868                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 869         }
 870         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 871         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 872         if (bp->vf_resv_strategy >
 873             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 874                 bp->vf_resv_strategy =
 875                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 876
 877         HWRM_UNLOCK();
 878         return rc;
 879 }
 880
 881 int bnxt_hwrm_ver_get(struct bnxt *bp)
 882 {
 883         int rc = 0;
 884         struct hwrm_ver_get_input req = {.req_type = 0 };
 885         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 886         uint32_t fw_version;
 887         uint16_t max_resp_len;
 888         char type[RTE_MEMZONE_NAMESIZE];
 889         uint32_t dev_caps_cfg;
 890
 891         bp->max_req_len = HWRM_MAX_REQ_LEN;
 892         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 893
 894         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 895         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 896         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 897
 898         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 899
 900         if (bp->flags & BNXT_FLAG_FW_RESET)
 901                 HWRM_CHECK_RESULT_SILENT();
 902         else
 903                 HWRM_CHECK_RESULT();
 904
 905         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 906                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 907                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 908                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 909         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 910                      (resp->hwrm_fw_min_8b << 16) |
 911                      (resp->hwrm_fw_bld_8b << 8) |
 912                      resp->hwrm_fw_rsvd_8b;
 913         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 914                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 915
 916         fw_version = resp->hwrm_intf_maj_8b << 16;
 917         fw_version |= resp->hwrm_intf_min_8b << 8;
 918         fw_version |= resp->hwrm_intf_upd_8b;
 919         bp->hwrm_spec_code = fw_version;
 920
 921         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 922                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 923                 rc = -EINVAL;
 924                 goto error;
 925         }
 926
 927         if (bp->max_req_len > resp->max_req_win_len) {
 928                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 929                 rc = -EINVAL;
 930         }
 931         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 932         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 933         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 934                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 935
 936         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 937         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 938
 939         if (bp->max_resp_len != max_resp_len) {
 940                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 941                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 942                         bp->pdev->addr.devid, bp->pdev->addr.function);
 943
 944                 rte_free(bp->hwrm_cmd_resp_addr);
 945
 946                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 947                 if (bp->hwrm_cmd_resp_addr == NULL) {
 948                         rc = -ENOMEM;
 949                         goto error;
 950                 }
 951                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 952                 bp->hwrm_cmd_resp_dma_addr =
 953                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 954                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 955                         PMD_DRV_LOG(ERR,
 956                         "Unable to map response buffer to physical memory.\n");
 957                         rc = -ENOMEM;
 958                         goto error;
 959                 }
 960                 bp->max_resp_len = max_resp_len;
 961         }
 962
 963         if ((dev_caps_cfg &
 964                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 965             (dev_caps_cfg &
 966              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 967                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 968                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 969         }
 970
 971         if (((dev_caps_cfg &
 972               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 973              (dev_caps_cfg &
 974               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 975             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 976                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 977                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 978                         bp->pdev->addr.devid, bp->pdev->addr.function);
 979
 980                 rte_free(bp->hwrm_short_cmd_req_addr);
 981
 982                 bp->hwrm_short_cmd_req_addr =
 983                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 984                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 985                         rc = -ENOMEM;
 986                         goto error;
 987                 }
 988                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 989                 bp->hwrm_short_cmd_req_dma_addr =
 990                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 991                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 992                         rte_free(bp->hwrm_short_cmd_req_addr);
 993                         PMD_DRV_LOG(ERR,
 994                                 "Unable to map buffer to physical memory.\n");
 995                         rc = -ENOMEM;
 996                         goto error;
 997                 }
 998         }
 999         if (dev_caps_cfg &
1000             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1001                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1002                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1003         }
1004         if (dev_caps_cfg &
1005             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1006                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1007
1008 error:
1009         HWRM_UNLOCK();
1010         return rc;
1011 }
1012
1013 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1014 {
1015         int rc;
1016         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1017         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1018
1019         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1020                 return 0;
1021
1022         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1023         req.flags = flags;
1024
1025         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1026
1027         HWRM_CHECK_RESULT();
1028         HWRM_UNLOCK();
1029
1030         return rc;
1031 }
1032
1033 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1034 {
1035         int rc = 0;
1036         struct hwrm_port_phy_cfg_input req = {0};
1037         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1038         uint32_t enables = 0;
1039
1040         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1041
1042         if (conf->link_up) {
1043                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1044                 if (bp->link_info.auto_mode && conf->link_speed) {
1045                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1046                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1047                 }
1048
1049                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1050                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1051                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1052                 /*
1053                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1054                  * any auto mode, even "none".
1055                  */
1056                 if (!conf->link_speed) {
1057                         /* No speeds specified. Enable AutoNeg - all speeds */
1058                         req.auto_mode =
1059                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1060                 }
1061                 /* AutoNeg - Advertise speeds specified. */
1062                 if (conf->auto_link_speed_mask &&
1063                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1064                         req.auto_mode =
1065                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1066                         req.auto_link_speed_mask =
1067                                 conf->auto_link_speed_mask;
1068                         enables |=
1069                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1070                 }
1071
1072                 req.auto_duplex = conf->duplex;
1073                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1074                 req.auto_pause = conf->auto_pause;
1075                 req.force_pause = conf->force_pause;
1076                 /* Set force_pause if there is no auto or if there is a force */
1077                 if (req.auto_pause && !req.force_pause)
1078                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1079                 else
1080                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1081
1082                 req.enables = rte_cpu_to_le_32(enables);
1083         } else {
1084                 req.flags =
1085                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1086                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1087         }
1088
1089         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1090
1091         HWRM_CHECK_RESULT();
1092         HWRM_UNLOCK();
1093
1094         return rc;
1095 }
1096
1097 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1098                                    struct bnxt_link_info *link_info)
1099 {
1100         int rc = 0;
1101         struct hwrm_port_phy_qcfg_input req = {0};
1102         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1103
1104         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1105
1106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1107
1108         HWRM_CHECK_RESULT();
1109
1110         link_info->phy_link_status = resp->link;
1111         link_info->link_up =
1112                 (link_info->phy_link_status ==
1113                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1114         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1115         link_info->duplex = resp->duplex_cfg;
1116         link_info->pause = resp->pause;
1117         link_info->auto_pause = resp->auto_pause;
1118         link_info->force_pause = resp->force_pause;
1119         link_info->auto_mode = resp->auto_mode;
1120         link_info->phy_type = resp->phy_type;
1121         link_info->media_type = resp->media_type;
1122
1123         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1124         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1125         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1126         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1127         link_info->phy_ver[0] = resp->phy_maj;
1128         link_info->phy_ver[1] = resp->phy_min;
1129         link_info->phy_ver[2] = resp->phy_bld;
1130
1131         HWRM_UNLOCK();
1132
1133         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1134         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1135         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1136         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1137         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1138                     link_info->auto_link_speed_mask);
1139         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1140                     link_info->force_link_speed);
1141
1142         return rc;
1143 }
1144
1145 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1146 {
1147         int rc = 0;
1148         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1149         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1150         int i;
1151
1152         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1153
1154         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1155         /* HWRM Version >= 1.9.1 */
1156         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1157                 req.drv_qmap_cap =
1158                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1159         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1160
1161         HWRM_CHECK_RESULT();
1162
1163 #define GET_QUEUE_INFO(x) \
1164         bp->cos_queue[x].id = resp->queue_id##x; \
1165         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1166
1167         GET_QUEUE_INFO(0);
1168         GET_QUEUE_INFO(1);
1169         GET_QUEUE_INFO(2);
1170         GET_QUEUE_INFO(3);
1171         GET_QUEUE_INFO(4);
1172         GET_QUEUE_INFO(5);
1173         GET_QUEUE_INFO(6);
1174         GET_QUEUE_INFO(7);
1175
1176         HWRM_UNLOCK();
1177
1178         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1179                 bp->tx_cosq_id = bp->cos_queue[0].id;
1180         } else {
1181                 /* iterate and find the COSq profile to use for Tx */
1182                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1183                         if (bp->cos_queue[i].profile ==
1184                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1185                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1186                                 break;
1187                         }
1188                 }
1189         }
1190
1191         bp->max_tc = resp->max_configurable_queues;
1192         bp->max_lltc = resp->max_configurable_lossless_queues;
1193         if (bp->max_tc > BNXT_MAX_QUEUE)
1194                 bp->max_tc = BNXT_MAX_QUEUE;
1195         bp->max_q = bp->max_tc;
1196
1197         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1198
1199         return rc;
1200 }
1201
1202 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1203                          struct bnxt_ring *ring,
1204                          uint32_t ring_type, uint32_t map_index,
1205                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1206 {
1207         int rc = 0;
1208         uint32_t enables = 0;
1209         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1210         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1211         struct rte_mempool *mb_pool;
1212         uint16_t rx_buf_size;
1213
1214         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1215
1216         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1217         req.fbo = rte_cpu_to_le_32(0);
1218         /* Association of ring index with doorbell index */
1219         req.logical_id = rte_cpu_to_le_16(map_index);
1220         req.length = rte_cpu_to_le_32(ring->ring_size);
1221
1222         switch (ring_type) {
1223         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1224                 req.ring_type = ring_type;
1225                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1226                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1227                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1228                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1229                         enables |=
1230                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1231                 break;
1232         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1233                 req.ring_type = ring_type;
1234                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1235                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1236                 if (BNXT_CHIP_THOR(bp)) {
1237                         mb_pool = bp->rx_queues[0]->mb_pool;
1238                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1239                                       RTE_PKTMBUF_HEADROOM;
1240                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1241                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1242                         enables |=
1243                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1244                 }
1245                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1246                         enables |=
1247                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1248                 break;
1249         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1250                 req.ring_type = ring_type;
1251                 if (BNXT_HAS_NQ(bp)) {
1252                         /* Association of cp ring with nq */
1253                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1254                         enables |=
1255                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1256                 }
1257                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1258                 break;
1259         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1260                 req.ring_type = ring_type;
1261                 req.page_size = BNXT_PAGE_SHFT;
1262                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1263                 break;
1264         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1265                 req.ring_type = ring_type;
1266                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1267
1268                 mb_pool = bp->rx_queues[0]->mb_pool;
1269                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1270                               RTE_PKTMBUF_HEADROOM;
1271                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1272                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1273
1274                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1275                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1276                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1277                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1278                 break;
1279         default:
1280                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1281                         ring_type);
1282                 HWRM_UNLOCK();
1283                 return -EINVAL;
1284         }
1285         req.enables = rte_cpu_to_le_32(enables);
1286
1287         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1288
1289         if (rc || resp->error_code) {
1290                 if (rc == 0 && resp->error_code)
1291                         rc = rte_le_to_cpu_16(resp->error_code);
1292                 switch (ring_type) {
1293                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1294                         PMD_DRV_LOG(ERR,
1295                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1296                         HWRM_UNLOCK();
1297                         return rc;
1298                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1299                         PMD_DRV_LOG(ERR,
1300                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1301                         HWRM_UNLOCK();
1302                         return rc;
1303                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1304                         PMD_DRV_LOG(ERR,
1305                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1306                                     rc);
1307                         HWRM_UNLOCK();
1308                         return rc;
1309                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1310                         PMD_DRV_LOG(ERR,
1311                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1312                         HWRM_UNLOCK();
1313                         return rc;
1314                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1315                         PMD_DRV_LOG(ERR,
1316                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1317                         HWRM_UNLOCK();
1318                         return rc;
1319                 default:
1320                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1321                         HWRM_UNLOCK();
1322                         return rc;
1323                 }
1324         }
1325
1326         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1327         HWRM_UNLOCK();
1328         return rc;
1329 }
1330
1331 int bnxt_hwrm_ring_free(struct bnxt *bp,
1332                         struct bnxt_ring *ring, uint32_t ring_type)
1333 {
1334         int rc;
1335         struct hwrm_ring_free_input req = {.req_type = 0 };
1336         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1337
1338         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1339
1340         req.ring_type = ring_type;
1341         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1342
1343         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1344
1345         if (rc || resp->error_code) {
1346                 if (rc == 0 && resp->error_code)
1347                         rc = rte_le_to_cpu_16(resp->error_code);
1348                 HWRM_UNLOCK();
1349
1350                 switch (ring_type) {
1351                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1352                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1353                                 rc);
1354                         return rc;
1355                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1356                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1357                                 rc);
1358                         return rc;
1359                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1360                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1361                                 rc);
1362                         return rc;
1363                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1364                         PMD_DRV_LOG(ERR,
1365                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1366                         return rc;
1367                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1368                         PMD_DRV_LOG(ERR,
1369                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1370                         return rc;
1371                 default:
1372                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1373                         return rc;
1374                 }
1375         }
1376         HWRM_UNLOCK();
1377         return 0;
1378 }
1379
1380 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1381 {
1382         int rc = 0;
1383         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1384         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1385
1386         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1387
1388         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1389         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1390         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1391         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1392
1393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1394
1395         HWRM_CHECK_RESULT();
1396
1397         bp->grp_info[idx].fw_grp_id =
1398             rte_le_to_cpu_16(resp->ring_group_id);
1399
1400         HWRM_UNLOCK();
1401
1402         return rc;
1403 }
1404
1405 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1406 {
1407         int rc;
1408         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1409         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1410
1411         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1412
1413         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1414
1415         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1416
1417         HWRM_CHECK_RESULT();
1418         HWRM_UNLOCK();
1419
1420         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1421         return rc;
1422 }
1423
1424 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1425 {
1426         int rc = 0;
1427         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1428         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1429
1430         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1431                 return rc;
1432
1433         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1434
1435         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1436
1437         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1438
1439         HWRM_CHECK_RESULT();
1440         HWRM_UNLOCK();
1441
1442         return rc;
1443 }
1444
1445 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1446                                 unsigned int idx __rte_unused)
1447 {
1448         int rc;
1449         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1450         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1451
1452         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1453
1454         req.update_period_ms = rte_cpu_to_le_32(0);
1455
1456         req.stats_dma_addr =
1457             rte_cpu_to_le_64(cpr->hw_stats_map);
1458
1459         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1460
1461         HWRM_CHECK_RESULT();
1462
1463         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1464
1465         HWRM_UNLOCK();
1466
1467         return rc;
1468 }
1469
1470 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1471                                 unsigned int idx __rte_unused)
1472 {
1473         int rc;
1474         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1475         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1476
1477         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1478
1479         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1480
1481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482
1483         HWRM_CHECK_RESULT();
1484         HWRM_UNLOCK();
1485
1486         return rc;
1487 }
1488
1489 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1490 {
1491         int rc = 0, i, j;
1492         struct hwrm_vnic_alloc_input req = { 0 };
1493         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1494
1495         if (!BNXT_HAS_RING_GRPS(bp))
1496                 goto skip_ring_grps;
1497
1498         /* map ring groups to this vnic */
1499         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1500                 vnic->start_grp_id, vnic->end_grp_id);
1501         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1502                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1503
1504         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1505         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1506         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1507         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1508
1509 skip_ring_grps:
1510         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1511                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1512         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1513
1514         if (vnic->func_default)
1515                 req.flags =
1516                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1518
1519         HWRM_CHECK_RESULT();
1520
1521         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1522         HWRM_UNLOCK();
1523         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1524         return rc;
1525 }
1526
1527 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1528                                         struct bnxt_vnic_info *vnic,
1529                                         struct bnxt_plcmodes_cfg *pmode)
1530 {
1531         int rc = 0;
1532         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1533         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1534
1535         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1536
1537         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1538
1539         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1540
1541         HWRM_CHECK_RESULT();
1542
1543         pmode->flags = rte_le_to_cpu_32(resp->flags);
1544         /* dflt_vnic bit doesn't exist in the _cfg command */
1545         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1546         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1547         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1548         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1549
1550         HWRM_UNLOCK();
1551
1552         return rc;
1553 }
1554
1555 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1556                                        struct bnxt_vnic_info *vnic,
1557                                        struct bnxt_plcmodes_cfg *pmode)
1558 {
1559         int rc = 0;
1560         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1561         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1562
1563         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1564                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1565                 return rc;
1566         }
1567
1568         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1569
1570         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1571         req.flags = rte_cpu_to_le_32(pmode->flags);
1572         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1573         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1574         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1575         req.enables = rte_cpu_to_le_32(
1576             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1577             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1578             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1579         );
1580
1581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1582
1583         HWRM_CHECK_RESULT();
1584         HWRM_UNLOCK();
1585
1586         return rc;
1587 }
1588
1589 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1590 {
1591         int rc = 0;
1592         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1593         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1594         struct bnxt_plcmodes_cfg pmodes = { 0 };
1595         uint32_t ctx_enable_flag = 0;
1596         uint32_t enables = 0;
1597
1598         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1599                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1600                 return rc;
1601         }
1602
1603         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1604         if (rc)
1605                 return rc;
1606
1607         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1608
1609         if (BNXT_CHIP_THOR(bp)) {
1610                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1611                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1612                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1613
1614                 req.default_rx_ring_id =
1615                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1616                 req.default_cmpl_ring_id =
1617                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1618                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1619                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1620                 goto config_mru;
1621         }
1622
1623         /* Only RSS support for now TBD: COS & LB */
1624         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1625         if (vnic->lb_rule != 0xffff)
1626                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1627         if (vnic->cos_rule != 0xffff)
1628                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1629         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1630                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1631                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1632         }
1633         enables |= ctx_enable_flag;
1634         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1635         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1636         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1637         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1638
1639 config_mru:
1640         req.enables = rte_cpu_to_le_32(enables);
1641         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1642         req.mru = rte_cpu_to_le_16(vnic->mru);
1643         /* Configure default VNIC only once. */
1644         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1645                 req.flags |=
1646                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1647                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1648         }
1649         if (vnic->vlan_strip)
1650                 req.flags |=
1651                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1652         if (vnic->bd_stall)
1653                 req.flags |=
1654                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1655         if (vnic->roce_dual)
1656                 req.flags |= rte_cpu_to_le_32(
1657                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1658         if (vnic->roce_only)
1659                 req.flags |= rte_cpu_to_le_32(
1660                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1661         if (vnic->rss_dflt_cr)
1662                 req.flags |= rte_cpu_to_le_32(
1663                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1664
1665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1666
1667         HWRM_CHECK_RESULT();
1668         HWRM_UNLOCK();
1669
1670         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1671
1672         return rc;
1673 }
1674
1675 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1676                 int16_t fw_vf_id)
1677 {
1678         int rc = 0;
1679         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1680         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1681
1682         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1683                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1684                 return rc;
1685         }
1686         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1687
1688         req.enables =
1689                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1690         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1691         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1692
1693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1694
1695         HWRM_CHECK_RESULT();
1696
1697         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1698         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1699         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1700         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1701         vnic->mru = rte_le_to_cpu_16(resp->mru);
1702         vnic->func_default = rte_le_to_cpu_32(
1703                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1704         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1705                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1706         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1707                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1708         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1709                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1710         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1711                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1712         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1713                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1714
1715         HWRM_UNLOCK();
1716
1717         return rc;
1718 }
1719
1720 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1721                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1722 {
1723         int rc = 0;
1724         uint16_t ctx_id;
1725         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1726         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1727                                                 bp->hwrm_cmd_resp_addr;
1728
1729         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1730
1731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1732         HWRM_CHECK_RESULT();
1733
1734         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1735         if (!BNXT_HAS_RING_GRPS(bp))
1736                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1737         else if (ctx_idx == 0)
1738                 vnic->rss_rule = ctx_id;
1739
1740         HWRM_UNLOCK();
1741
1742         return rc;
1743 }
1744
1745 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1746                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1747 {
1748         int rc = 0;
1749         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1750         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1751                                                 bp->hwrm_cmd_resp_addr;
1752
1753         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1754                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1755                 return rc;
1756         }
1757         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1758
1759         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         HWRM_CHECK_RESULT();
1764         HWRM_UNLOCK();
1765
1766         return rc;
1767 }
1768
1769 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1770 {
1771         int rc = 0;
1772         struct hwrm_vnic_free_input req = {.req_type = 0 };
1773         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1774
1775         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1776                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1777                 return rc;
1778         }
1779
1780         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1781
1782         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1783
1784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1785
1786         HWRM_CHECK_RESULT();
1787         HWRM_UNLOCK();
1788
1789         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1790         /* Configure default VNIC again if necessary. */
1791         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1792                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1793
1794         return rc;
1795 }
1796
1797 static int
1798 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1799 {
1800         int i;
1801         int rc = 0;
1802         int nr_ctxs = vnic->num_lb_ctxts;
1803         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1804         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1805
1806         for (i = 0; i < nr_ctxs; i++) {
1807                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1808
1809                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1810                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1811                 req.hash_mode_flags = vnic->hash_mode;
1812
1813                 req.hash_key_tbl_addr =
1814                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1815
1816                 req.ring_grp_tbl_addr =
1817                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1818                                          i * HW_HASH_INDEX_SIZE);
1819                 req.ring_table_pair_index = i;
1820                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1821
1822                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1823                                             BNXT_USE_CHIMP_MB);
1824
1825                 HWRM_CHECK_RESULT();
1826                 HWRM_UNLOCK();
1827         }
1828
1829         return rc;
1830 }
1831
1832 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1833                            struct bnxt_vnic_info *vnic)
1834 {
1835         int rc = 0;
1836         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1837         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1838
1839         if (!vnic->rss_table)
1840                 return 0;
1841
1842         if (BNXT_CHIP_THOR(bp))
1843                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1844
1845         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1846
1847         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1848         req.hash_mode_flags = vnic->hash_mode;
1849
1850         req.ring_grp_tbl_addr =
1851             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1852         req.hash_key_tbl_addr =
1853             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1854         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1855         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1856
1857         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1858
1859         HWRM_CHECK_RESULT();
1860         HWRM_UNLOCK();
1861
1862         return rc;
1863 }
1864
1865 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1866                         struct bnxt_vnic_info *vnic)
1867 {
1868         int rc = 0;
1869         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1870         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1871         uint16_t size;
1872
1873         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1874                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1875                 return rc;
1876         }
1877
1878         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1879
1880         req.flags = rte_cpu_to_le_32(
1881                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1882
1883         req.enables = rte_cpu_to_le_32(
1884                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1885
1886         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1887         size -= RTE_PKTMBUF_HEADROOM;
1888         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1889
1890         req.jumbo_thresh = rte_cpu_to_le_16(size);
1891         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1892
1893         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1894
1895         HWRM_CHECK_RESULT();
1896         HWRM_UNLOCK();
1897
1898         return rc;
1899 }
1900
1901 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1902                         struct bnxt_vnic_info *vnic, bool enable)
1903 {
1904         int rc = 0;
1905         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1906         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1907
1908         if (BNXT_CHIP_THOR(bp))
1909                 return 0;
1910
1911         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1912
1913         if (enable) {
1914                 req.enables = rte_cpu_to_le_32(
1915                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1916                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1917                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1918                 req.flags = rte_cpu_to_le_32(
1919                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1920                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1921                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1922                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1923                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1924                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1925                 req.max_agg_segs = rte_cpu_to_le_16(5);
1926                 req.max_aggs =
1927                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1928                 req.min_agg_len = rte_cpu_to_le_32(512);
1929         }
1930         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1931
1932         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934         HWRM_CHECK_RESULT();
1935         HWRM_UNLOCK();
1936
1937         return rc;
1938 }
1939
1940 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1941 {
1942         struct hwrm_func_cfg_input req = {0};
1943         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1944         int rc;
1945
1946         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1947         req.enables = rte_cpu_to_le_32(
1948                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1949         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1950         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1951
1952         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1953
1954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1955         HWRM_CHECK_RESULT();
1956         HWRM_UNLOCK();
1957
1958         bp->pf.vf_info[vf].random_mac = false;
1959
1960         return rc;
1961 }
1962
1963 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1964                                   uint64_t *dropped)
1965 {
1966         int rc = 0;
1967         struct hwrm_func_qstats_input req = {.req_type = 0};
1968         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1969
1970         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1971
1972         req.fid = rte_cpu_to_le_16(fid);
1973
1974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1975
1976         HWRM_CHECK_RESULT();
1977
1978         if (dropped)
1979                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1980
1981         HWRM_UNLOCK();
1982
1983         return rc;
1984 }
1985
1986 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1987                           struct rte_eth_stats *stats)
1988 {
1989         int rc = 0;
1990         struct hwrm_func_qstats_input req = {.req_type = 0};
1991         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1992
1993         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1994
1995         req.fid = rte_cpu_to_le_16(fid);
1996
1997         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1998
1999         HWRM_CHECK_RESULT();
2000
2001         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2002         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2003         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2004         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2005         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2006         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2007
2008         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2009         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2010         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2011         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2012         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2013         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2014
2015         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2016         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2017         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2018
2019         HWRM_UNLOCK();
2020
2021         return rc;
2022 }
2023
2024 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2025 {
2026         int rc = 0;
2027         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2028         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2029
2030         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2031
2032         req.fid = rte_cpu_to_le_16(fid);
2033
2034         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2035
2036         HWRM_CHECK_RESULT();
2037         HWRM_UNLOCK();
2038
2039         return rc;
2040 }
2041
2042 /*
2043  * HWRM utility functions
2044  */
2045
2046 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2047 {
2048         unsigned int i;
2049         int rc = 0;
2050
2051         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2052                 struct bnxt_tx_queue *txq;
2053                 struct bnxt_rx_queue *rxq;
2054                 struct bnxt_cp_ring_info *cpr;
2055
2056                 if (i >= bp->rx_cp_nr_rings) {
2057                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2058                         cpr = txq->cp_ring;
2059                 } else {
2060                         rxq = bp->rx_queues[i];
2061                         cpr = rxq->cp_ring;
2062                 }
2063
2064                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2065                 if (rc)
2066                         return rc;
2067         }
2068         return 0;
2069 }
2070
2071 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2072 {
2073         int rc;
2074         unsigned int i;
2075         struct bnxt_cp_ring_info *cpr;
2076
2077         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2078
2079                 if (i >= bp->rx_cp_nr_rings) {
2080                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2081                 } else {
2082                         cpr = bp->rx_queues[i]->cp_ring;
2083                         if (BNXT_HAS_RING_GRPS(bp))
2084                                 bp->grp_info[i].fw_stats_ctx = -1;
2085                 }
2086                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2087                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2088                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2089                         if (rc)
2090                                 return rc;
2091                 }
2092         }
2093         return 0;
2094 }
2095
2096 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2097 {
2098         unsigned int i;
2099         int rc = 0;
2100
2101         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2102                 struct bnxt_tx_queue *txq;
2103                 struct bnxt_rx_queue *rxq;
2104                 struct bnxt_cp_ring_info *cpr;
2105
2106                 if (i >= bp->rx_cp_nr_rings) {
2107                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2108                         cpr = txq->cp_ring;
2109                 } else {
2110                         rxq = bp->rx_queues[i];
2111                         cpr = rxq->cp_ring;
2112                 }
2113
2114                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2115
2116                 if (rc)
2117                         return rc;
2118         }
2119         return rc;
2120 }
2121
2122 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2123 {
2124         uint16_t idx;
2125         uint32_t rc = 0;
2126
2127         if (!BNXT_HAS_RING_GRPS(bp))
2128                 return 0;
2129
2130         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2131
2132                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2133                         continue;
2134
2135                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2136
2137                 if (rc)
2138                         return rc;
2139         }
2140         return rc;
2141 }
2142
2143 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2144 {
2145         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2146
2147         bnxt_hwrm_ring_free(bp, cp_ring,
2148                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2149         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2150         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2151                                      sizeof(*cpr->cp_desc_ring));
2152         cpr->cp_raw_cons = 0;
2153         cpr->valid = 0;
2154 }
2155
2156 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2157 {
2158         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2159
2160         bnxt_hwrm_ring_free(bp, cp_ring,
2161                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2162         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2163         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2164                         sizeof(*cpr->cp_desc_ring));
2165         cpr->cp_raw_cons = 0;
2166         cpr->valid = 0;
2167 }
2168
2169 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2170 {
2171         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2172         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2173         struct bnxt_ring *ring = rxr->rx_ring_struct;
2174         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2175
2176         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2177                 bnxt_hwrm_ring_free(bp, ring,
2178                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2179                 ring->fw_ring_id = INVALID_HW_RING_ID;
2180                 if (BNXT_HAS_RING_GRPS(bp))
2181                         bp->grp_info[queue_index].rx_fw_ring_id =
2182                                                         INVALID_HW_RING_ID;
2183                 memset(rxr->rx_desc_ring, 0,
2184                        rxr->rx_ring_struct->ring_size *
2185                        sizeof(*rxr->rx_desc_ring));
2186                 memset(rxr->rx_buf_ring, 0,
2187                        rxr->rx_ring_struct->ring_size *
2188                        sizeof(*rxr->rx_buf_ring));
2189                 rxr->rx_prod = 0;
2190         }
2191         ring = rxr->ag_ring_struct;
2192         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2193                 bnxt_hwrm_ring_free(bp, ring,
2194                                     BNXT_CHIP_THOR(bp) ?
2195                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2196                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2197                 ring->fw_ring_id = INVALID_HW_RING_ID;
2198                 memset(rxr->ag_buf_ring, 0,
2199                        rxr->ag_ring_struct->ring_size *
2200                        sizeof(*rxr->ag_buf_ring));
2201                 rxr->ag_prod = 0;
2202                 if (BNXT_HAS_RING_GRPS(bp))
2203                         bp->grp_info[queue_index].ag_fw_ring_id =
2204                                                         INVALID_HW_RING_ID;
2205         }
2206         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2207                 bnxt_free_cp_ring(bp, cpr);
2208                 if (rxq->nq_ring)
2209                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2210         }
2211
2212         if (BNXT_HAS_RING_GRPS(bp))
2213                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2214 }
2215
2216 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2217 {
2218         unsigned int i;
2219
2220         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2221                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2222                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2223                 struct bnxt_ring *ring = txr->tx_ring_struct;
2224                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2225
2226                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2227                         bnxt_hwrm_ring_free(bp, ring,
2228                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2229                         ring->fw_ring_id = INVALID_HW_RING_ID;
2230                         memset(txr->tx_desc_ring, 0,
2231                                         txr->tx_ring_struct->ring_size *
2232                                         sizeof(*txr->tx_desc_ring));
2233                         memset(txr->tx_buf_ring, 0,
2234                                         txr->tx_ring_struct->ring_size *
2235                                         sizeof(*txr->tx_buf_ring));
2236                         txr->tx_prod = 0;
2237                         txr->tx_cons = 0;
2238                 }
2239                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2240                         bnxt_free_cp_ring(bp, cpr);
2241                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2242                         if (txq->nq_ring)
2243                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2244                 }
2245         }
2246
2247         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2248                 bnxt_free_hwrm_rx_ring(bp, i);
2249
2250         return 0;
2251 }
2252
2253 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2254 {
2255         uint16_t i;
2256         uint32_t rc = 0;
2257
2258         if (!BNXT_HAS_RING_GRPS(bp))
2259                 return 0;
2260
2261         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2262                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2263                 if (rc)
2264                         return rc;
2265         }
2266         return rc;
2267 }
2268
2269 void bnxt_free_hwrm_resources(struct bnxt *bp)
2270 {
2271         /* Release memzone */
2272         rte_free(bp->hwrm_cmd_resp_addr);
2273         rte_free(bp->hwrm_short_cmd_req_addr);
2274         bp->hwrm_cmd_resp_addr = NULL;
2275         bp->hwrm_short_cmd_req_addr = NULL;
2276         bp->hwrm_cmd_resp_dma_addr = 0;
2277         bp->hwrm_short_cmd_req_dma_addr = 0;
2278 }
2279
2280 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2281 {
2282         struct rte_pci_device *pdev = bp->pdev;
2283         char type[RTE_MEMZONE_NAMESIZE];
2284
2285         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2286                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2287         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2288         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2289         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2290         if (bp->hwrm_cmd_resp_addr == NULL)
2291                 return -ENOMEM;
2292         bp->hwrm_cmd_resp_dma_addr =
2293                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2294         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2295                 PMD_DRV_LOG(ERR,
2296                         "unable to map response address to physical memory\n");
2297                 return -ENOMEM;
2298         }
2299         rte_spinlock_init(&bp->hwrm_lock);
2300
2301         return 0;
2302 }
2303
2304 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2305 {
2306         struct bnxt_filter_info *filter;
2307         int rc = 0;
2308
2309         STAILQ_FOREACH(filter, &vnic->filter, next) {
2310                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2311                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2312                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2313                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2314                 else
2315                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2316                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2317                 //if (rc)
2318                         //break;
2319         }
2320         return rc;
2321 }
2322
2323 static int
2324 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2325 {
2326         struct bnxt_filter_info *filter;
2327         struct rte_flow *flow;
2328         int rc = 0;
2329
2330         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2331                 filter = flow->filter;
2332                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2333                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2334                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2335                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2336                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2337                 else
2338                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2339
2340                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2341                 rte_free(flow);
2342                 //if (rc)
2343                         //break;
2344         }
2345         return rc;
2346 }
2347
2348 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2349 {
2350         struct bnxt_filter_info *filter;
2351         int rc = 0;
2352
2353         STAILQ_FOREACH(filter, &vnic->filter, next) {
2354                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2355                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2356                                                      filter);
2357                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2358                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2359                                                          filter);
2360                 else
2361                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2362                                                      filter);
2363                 if (rc)
2364                         break;
2365         }
2366         return rc;
2367 }
2368
2369 void bnxt_free_tunnel_ports(struct bnxt *bp)
2370 {
2371         if (bp->vxlan_port_cnt)
2372                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2373                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2374         bp->vxlan_port = 0;
2375         if (bp->geneve_port_cnt)
2376                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2377                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2378         bp->geneve_port = 0;
2379 }
2380
2381 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2382 {
2383         int i, j;
2384
2385         if (bp->vnic_info == NULL)
2386                 return;
2387
2388         /*
2389          * Cleanup VNICs in reverse order, to make sure the L2 filter
2390          * from vnic0 is last to be cleaned up.
2391          */
2392         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2393                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2394
2395                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2396                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2397                         return;
2398                 }
2399
2400                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2401
2402                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2403
2404                 if (BNXT_CHIP_THOR(bp)) {
2405                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2406                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2407                                                         vnic->fw_grp_ids[j]);
2408                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2409                         }
2410                         vnic->num_lb_ctxts = 0;
2411                 } else {
2412                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2413                         vnic->rss_rule = INVALID_HW_RING_ID;
2414                 }
2415
2416                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2417
2418                 bnxt_hwrm_vnic_free(bp, vnic);
2419
2420                 rte_free(vnic->fw_grp_ids);
2421         }
2422         /* Ring resources */
2423         bnxt_free_all_hwrm_rings(bp);
2424         bnxt_free_all_hwrm_ring_grps(bp);
2425         bnxt_free_all_hwrm_stat_ctxs(bp);
2426         bnxt_free_tunnel_ports(bp);
2427 }
2428
2429 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2430 {
2431         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2432
2433         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2434                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2435
2436         switch (conf_link_speed) {
2437         case ETH_LINK_SPEED_10M_HD:
2438         case ETH_LINK_SPEED_100M_HD:
2439                 /* FALLTHROUGH */
2440                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2441         }
2442         return hw_link_duplex;
2443 }
2444
2445 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2446 {
2447         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2448 }
2449
2450 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2451 {
2452         uint16_t eth_link_speed = 0;
2453
2454         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2455                 return ETH_LINK_SPEED_AUTONEG;
2456
2457         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2458         case ETH_LINK_SPEED_100M:
2459         case ETH_LINK_SPEED_100M_HD:
2460                 /* FALLTHROUGH */
2461                 eth_link_speed =
2462                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2463                 break;
2464         case ETH_LINK_SPEED_1G:
2465                 eth_link_speed =
2466                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2467                 break;
2468         case ETH_LINK_SPEED_2_5G:
2469                 eth_link_speed =
2470                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2471                 break;
2472         case ETH_LINK_SPEED_10G:
2473                 eth_link_speed =
2474                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2475                 break;
2476         case ETH_LINK_SPEED_20G:
2477                 eth_link_speed =
2478                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2479                 break;
2480         case ETH_LINK_SPEED_25G:
2481                 eth_link_speed =
2482                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2483                 break;
2484         case ETH_LINK_SPEED_40G:
2485                 eth_link_speed =
2486                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2487                 break;
2488         case ETH_LINK_SPEED_50G:
2489                 eth_link_speed =
2490                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2491                 break;
2492         case ETH_LINK_SPEED_100G:
2493                 eth_link_speed =
2494                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2495                 break;
2496         default:
2497                 PMD_DRV_LOG(ERR,
2498                         "Unsupported link speed %d; default to AUTO\n",
2499                         conf_link_speed);
2500                 break;
2501         }
2502         return eth_link_speed;
2503 }
2504
2505 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2506                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2507                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2508                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2509
2510 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2511 {
2512         uint32_t one_speed;
2513
2514         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2515                 return 0;
2516
2517         if (link_speed & ETH_LINK_SPEED_FIXED) {
2518                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2519
2520                 if (one_speed & (one_speed - 1)) {
2521                         PMD_DRV_LOG(ERR,
2522                                 "Invalid advertised speeds (%u) for port %u\n",
2523                                 link_speed, port_id);
2524                         return -EINVAL;
2525                 }
2526                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2527                         PMD_DRV_LOG(ERR,
2528                                 "Unsupported advertised speed (%u) for port %u\n",
2529                                 link_speed, port_id);
2530                         return -EINVAL;
2531                 }
2532         } else {
2533                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2534                         PMD_DRV_LOG(ERR,
2535                                 "Unsupported advertised speeds (%u) for port %u\n",
2536                                 link_speed, port_id);
2537                         return -EINVAL;
2538                 }
2539         }
2540         return 0;
2541 }
2542
2543 static uint16_t
2544 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2545 {
2546         uint16_t ret = 0;
2547
2548         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2549                 if (bp->link_info.support_speeds)
2550                         return bp->link_info.support_speeds;
2551                 link_speed = BNXT_SUPPORTED_SPEEDS;
2552         }
2553
2554         if (link_speed & ETH_LINK_SPEED_100M)
2555                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2556         if (link_speed & ETH_LINK_SPEED_100M_HD)
2557                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2558         if (link_speed & ETH_LINK_SPEED_1G)
2559                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2560         if (link_speed & ETH_LINK_SPEED_2_5G)
2561                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2562         if (link_speed & ETH_LINK_SPEED_10G)
2563                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2564         if (link_speed & ETH_LINK_SPEED_20G)
2565                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2566         if (link_speed & ETH_LINK_SPEED_25G)
2567                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2568         if (link_speed & ETH_LINK_SPEED_40G)
2569                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2570         if (link_speed & ETH_LINK_SPEED_50G)
2571                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2572         if (link_speed & ETH_LINK_SPEED_100G)
2573                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2574         return ret;
2575 }
2576
2577 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2578 {
2579         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2580
2581         switch (hw_link_speed) {
2582         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2583                 eth_link_speed = ETH_SPEED_NUM_100M;
2584                 break;
2585         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2586                 eth_link_speed = ETH_SPEED_NUM_1G;
2587                 break;
2588         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2589                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2590                 break;
2591         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2592                 eth_link_speed = ETH_SPEED_NUM_10G;
2593                 break;
2594         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2595                 eth_link_speed = ETH_SPEED_NUM_20G;
2596                 break;
2597         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2598                 eth_link_speed = ETH_SPEED_NUM_25G;
2599                 break;
2600         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2601                 eth_link_speed = ETH_SPEED_NUM_40G;
2602                 break;
2603         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2604                 eth_link_speed = ETH_SPEED_NUM_50G;
2605                 break;
2606         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2607                 eth_link_speed = ETH_SPEED_NUM_100G;
2608                 break;
2609         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2610         default:
2611                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2612                         hw_link_speed);
2613                 break;
2614         }
2615         return eth_link_speed;
2616 }
2617
2618 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2619 {
2620         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2621
2622         switch (hw_link_duplex) {
2623         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2624         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2625                 /* FALLTHROUGH */
2626                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2627                 break;
2628         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2629                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2630                 break;
2631         default:
2632                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2633                         hw_link_duplex);
2634                 break;
2635         }
2636         return eth_link_duplex;
2637 }
2638
2639 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2640 {
2641         int rc = 0;
2642         struct bnxt_link_info *link_info = &bp->link_info;
2643
2644         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2645         if (rc) {
2646                 PMD_DRV_LOG(ERR,
2647                         "Get link config failed with rc %d\n", rc);
2648                 goto exit;
2649         }
2650         if (link_info->link_speed)
2651                 link->link_speed =
2652                         bnxt_parse_hw_link_speed(link_info->link_speed);
2653         else
2654                 link->link_speed = ETH_SPEED_NUM_NONE;
2655         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2656         link->link_status = link_info->link_up;
2657         link->link_autoneg = link_info->auto_mode ==
2658                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2659                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2660 exit:
2661         return rc;
2662 }
2663
2664 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2665 {
2666         int rc = 0;
2667         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2668         struct bnxt_link_info link_req;
2669         uint16_t speed, autoneg;
2670
2671         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2672                 return 0;
2673
2674         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2675                         bp->eth_dev->data->port_id);
2676         if (rc)
2677                 goto error;
2678
2679         memset(&link_req, 0, sizeof(link_req));
2680         link_req.link_up = link_up;
2681         if (!link_up)
2682                 goto port_phy_cfg;
2683
2684         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2685         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2686         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2687         /* Autoneg can be done only when the FW allows */
2688         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2689                                 bp->link_info.force_link_speed)) {
2690                 link_req.phy_flags |=
2691                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2692                 link_req.auto_link_speed_mask =
2693                         bnxt_parse_eth_link_speed_mask(bp,
2694                                                        dev_conf->link_speeds);
2695         } else {
2696                 if (bp->link_info.phy_type ==
2697                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2698                     bp->link_info.phy_type ==
2699                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2700                     bp->link_info.media_type ==
2701                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2702                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2703                         return -EINVAL;
2704                 }
2705
2706                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2707                 /* If user wants a particular speed try that first. */
2708                 if (speed)
2709                         link_req.link_speed = speed;
2710                 else if (bp->link_info.force_link_speed)
2711                         link_req.link_speed = bp->link_info.force_link_speed;
2712                 else
2713                         link_req.link_speed = bp->link_info.auto_link_speed;
2714         }
2715         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2716         link_req.auto_pause = bp->link_info.auto_pause;
2717         link_req.force_pause = bp->link_info.force_pause;
2718
2719 port_phy_cfg:
2720         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2721         if (rc) {
2722                 PMD_DRV_LOG(ERR,
2723                         "Set link config failed with rc %d\n", rc);
2724         }
2725
2726 error:
2727         return rc;
2728 }
2729
2730 /* JIRA 22088 */
2731 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2732 {
2733         struct hwrm_func_qcfg_input req = {0};
2734         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2735         uint16_t flags;
2736         int rc = 0;
2737
2738         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2739         req.fid = rte_cpu_to_le_16(0xffff);
2740
2741         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2742
2743         HWRM_CHECK_RESULT();
2744
2745         /* Hard Coded.. 0xfff VLAN ID mask */
2746         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2747         flags = rte_le_to_cpu_16(resp->flags);
2748         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2749                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2750
2751         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2752                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2753                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2754         } else if (BNXT_VF(bp) &&
2755                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2756                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2757                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2758         }
2759
2760         if (mtu)
2761                 *mtu = resp->mtu;
2762
2763         switch (resp->port_partition_type) {
2764         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2765         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2766         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2767                 /* FALLTHROUGH */
2768                 bp->port_partition_type = resp->port_partition_type;
2769                 break;
2770         default:
2771                 bp->port_partition_type = 0;
2772                 break;
2773         }
2774
2775         HWRM_UNLOCK();
2776
2777         return rc;
2778 }
2779
2780 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2781                                    struct hwrm_func_qcaps_output *qcaps)
2782 {
2783         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2784         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2785                sizeof(qcaps->mac_address));
2786         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2787         qcaps->max_rx_rings = fcfg->num_rx_rings;
2788         qcaps->max_tx_rings = fcfg->num_tx_rings;
2789         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2790         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2791         qcaps->max_vfs = 0;
2792         qcaps->first_vf_id = 0;
2793         qcaps->max_vnics = fcfg->num_vnics;
2794         qcaps->max_decap_records = 0;
2795         qcaps->max_encap_records = 0;
2796         qcaps->max_tx_wm_flows = 0;
2797         qcaps->max_tx_em_flows = 0;
2798         qcaps->max_rx_wm_flows = 0;
2799         qcaps->max_rx_em_flows = 0;
2800         qcaps->max_flow_id = 0;
2801         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2802         qcaps->max_sp_tx_rings = 0;
2803         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2804 }
2805
2806 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2807 {
2808         struct hwrm_func_cfg_input req = {0};
2809         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2810         uint32_t enables;
2811         int rc;
2812
2813         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2814                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2815                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2816                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2817                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2818                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2819                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2820                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2821                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2822
2823         if (BNXT_HAS_RING_GRPS(bp)) {
2824                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2825                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2826         } else if (BNXT_HAS_NQ(bp)) {
2827                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2828                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2829         }
2830
2831         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2832         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2833         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2834                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2835                                    BNXT_NUM_VLANS);
2836         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2837         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2838         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2839         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2840         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2841         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2842         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2843         req.fid = rte_cpu_to_le_16(0xffff);
2844         req.enables = rte_cpu_to_le_32(enables);
2845
2846         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2847
2848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2849
2850         HWRM_CHECK_RESULT();
2851         HWRM_UNLOCK();
2852
2853         return rc;
2854 }
2855
2856 static void populate_vf_func_cfg_req(struct bnxt *bp,
2857                                      struct hwrm_func_cfg_input *req,
2858                                      int num_vfs)
2859 {
2860         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2861                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2862                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2863                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2864                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2865                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2866                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2867                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2868                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2869                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2870
2871         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2872                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2873                                     BNXT_NUM_VLANS);
2874         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2875                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2876                                     BNXT_NUM_VLANS);
2877         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2878                                                 (num_vfs + 1));
2879         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2880         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2881                                                (num_vfs + 1));
2882         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2883         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2884         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2885         /* TODO: For now, do not support VMDq/RFS on VFs. */
2886         req->num_vnics = rte_cpu_to_le_16(1);
2887         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2888                                                  (num_vfs + 1));
2889 }
2890
2891 static void add_random_mac_if_needed(struct bnxt *bp,
2892                                      struct hwrm_func_cfg_input *cfg_req,
2893                                      int vf)
2894 {
2895         struct rte_ether_addr mac;
2896
2897         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2898                 return;
2899
2900         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2901                 cfg_req->enables |=
2902                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2903                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2904                 bp->pf.vf_info[vf].random_mac = true;
2905         } else {
2906                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2907                         RTE_ETHER_ADDR_LEN);
2908         }
2909 }
2910
2911 static void reserve_resources_from_vf(struct bnxt *bp,
2912                                       struct hwrm_func_cfg_input *cfg_req,
2913                                       int vf)
2914 {
2915         struct hwrm_func_qcaps_input req = {0};
2916         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2917         int rc;
2918
2919         /* Get the actual allocated values now */
2920         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2921         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2922         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2923
2924         if (rc) {
2925                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2926                 copy_func_cfg_to_qcaps(cfg_req, resp);
2927         } else if (resp->error_code) {
2928                 rc = rte_le_to_cpu_16(resp->error_code);
2929                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2930                 copy_func_cfg_to_qcaps(cfg_req, resp);
2931         }
2932
2933         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2934         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2935         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2936         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2937         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2938         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2939         /*
2940          * TODO: While not supporting VMDq with VFs, max_vnics is always
2941          * forced to 1 in this case
2942          */
2943         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2944         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2945
2946         HWRM_UNLOCK();
2947 }
2948
2949 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2950 {
2951         struct hwrm_func_qcfg_input req = {0};
2952         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2953         int rc;
2954
2955         /* Check for zero MAC address */
2956         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2957         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2958         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2959         HWRM_CHECK_RESULT();
2960         rc = rte_le_to_cpu_16(resp->vlan);
2961
2962         HWRM_UNLOCK();
2963
2964         return rc;
2965 }
2966
2967 static int update_pf_resource_max(struct bnxt *bp)
2968 {
2969         struct hwrm_func_qcfg_input req = {0};
2970         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2971         int rc;
2972
2973         /* And copy the allocated numbers into the pf struct */
2974         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2975         req.fid = rte_cpu_to_le_16(0xffff);
2976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2977         HWRM_CHECK_RESULT();
2978
2979         /* Only TX ring value reflects actual allocation? TODO */
2980         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2981         bp->pf.evb_mode = resp->evb_mode;
2982
2983         HWRM_UNLOCK();
2984
2985         return rc;
2986 }
2987
2988 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2989 {
2990         int rc;
2991
2992         if (!BNXT_PF(bp)) {
2993                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2994                 return -EINVAL;
2995         }
2996
2997         rc = bnxt_hwrm_func_qcaps(bp);
2998         if (rc)
2999                 return rc;
3000
3001         bp->pf.func_cfg_flags &=
3002                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3003                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3004         bp->pf.func_cfg_flags |=
3005                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3006         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3007         rc = __bnxt_hwrm_func_qcaps(bp);
3008         return rc;
3009 }
3010
3011 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3012 {
3013         struct hwrm_func_cfg_input req = {0};
3014         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3015         int i;
3016         size_t sz;
3017         int rc = 0;
3018         size_t req_buf_sz;
3019
3020         if (!BNXT_PF(bp)) {
3021                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3022                 return -EINVAL;
3023         }
3024
3025         rc = bnxt_hwrm_func_qcaps(bp);
3026
3027         if (rc)
3028                 return rc;
3029
3030         bp->pf.active_vfs = num_vfs;
3031
3032         /*
3033          * First, configure the PF to only use one TX ring.  This ensures that
3034          * there are enough rings for all VFs.
3035          *
3036          * If we don't do this, when we call func_alloc() later, we will lock
3037          * extra rings to the PF that won't be available during func_cfg() of
3038          * the VFs.
3039          *
3040          * This has been fixed with firmware versions above 20.6.54
3041          */
3042         bp->pf.func_cfg_flags &=
3043                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3044                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3045         bp->pf.func_cfg_flags |=
3046                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3047         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3048         if (rc)
3049                 return rc;
3050
3051         /*
3052          * Now, create and register a buffer to hold forwarded VF requests
3053          */
3054         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3055         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3056                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3057         if (bp->pf.vf_req_buf == NULL) {
3058                 rc = -ENOMEM;
3059                 goto error_free;
3060         }
3061         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3062                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3063         for (i = 0; i < num_vfs; i++)
3064                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3065                                         (i * HWRM_MAX_REQ_LEN);
3066
3067         rc = bnxt_hwrm_func_buf_rgtr(bp);
3068         if (rc)
3069                 goto error_free;
3070
3071         populate_vf_func_cfg_req(bp, &req, num_vfs);
3072
3073         bp->pf.active_vfs = 0;
3074         for (i = 0; i < num_vfs; i++) {
3075                 add_random_mac_if_needed(bp, &req, i);
3076
3077                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3078                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3079                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3080                 rc = bnxt_hwrm_send_message(bp,
3081                                             &req,
3082                                             sizeof(req),
3083                                             BNXT_USE_CHIMP_MB);
3084
3085                 /* Clear enable flag for next pass */
3086                 req.enables &= ~rte_cpu_to_le_32(
3087                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3088
3089                 if (rc || resp->error_code) {
3090                         PMD_DRV_LOG(ERR,
3091                                 "Failed to initizlie VF %d\n", i);
3092                         PMD_DRV_LOG(ERR,
3093                                 "Not all VFs available. (%d, %d)\n",
3094                                 rc, resp->error_code);
3095                         HWRM_UNLOCK();
3096                         break;
3097                 }
3098
3099                 HWRM_UNLOCK();
3100
3101                 reserve_resources_from_vf(bp, &req, i);
3102                 bp->pf.active_vfs++;
3103                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3104         }
3105
3106         /*
3107          * Now configure the PF to use "the rest" of the resources
3108          * We're using STD_TX_RING_MODE here though which will limit the TX
3109          * rings.  This will allow QoS to function properly.  Not setting this
3110          * will cause PF rings to break bandwidth settings.
3111          */
3112         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3113         if (rc)
3114                 goto error_free;
3115
3116         rc = update_pf_resource_max(bp);
3117         if (rc)
3118                 goto error_free;
3119
3120         return rc;
3121
3122 error_free:
3123         bnxt_hwrm_func_buf_unrgtr(bp);
3124         return rc;
3125 }
3126
3127 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3128 {
3129         struct hwrm_func_cfg_input req = {0};
3130         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3131         int rc;
3132
3133         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3134
3135         req.fid = rte_cpu_to_le_16(0xffff);
3136         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3137         req.evb_mode = bp->pf.evb_mode;
3138
3139         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3140         HWRM_CHECK_RESULT();
3141         HWRM_UNLOCK();
3142
3143         return rc;
3144 }
3145
3146 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3147                                 uint8_t tunnel_type)
3148 {
3149         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3150         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3151         int rc = 0;
3152
3153         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3154         req.tunnel_type = tunnel_type;
3155         req.tunnel_dst_port_val = port;
3156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3157         HWRM_CHECK_RESULT();
3158
3159         switch (tunnel_type) {
3160         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3161                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3162                 bp->vxlan_port = port;
3163                 break;
3164         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3165                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3166                 bp->geneve_port = port;
3167                 break;
3168         default:
3169                 break;
3170         }
3171
3172         HWRM_UNLOCK();
3173
3174         return rc;
3175 }
3176
3177 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3178                                 uint8_t tunnel_type)
3179 {
3180         struct hwrm_tunnel_dst_port_free_input req = {0};
3181         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3182         int rc = 0;
3183
3184         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3185
3186         req.tunnel_type = tunnel_type;
3187         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3189
3190         HWRM_CHECK_RESULT();
3191         HWRM_UNLOCK();
3192
3193         return rc;
3194 }
3195
3196 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3197                                         uint32_t flags)
3198 {
3199         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3200         struct hwrm_func_cfg_input req = {0};
3201         int rc;
3202
3203         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3204
3205         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3206         req.flags = rte_cpu_to_le_32(flags);
3207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3208
3209         HWRM_CHECK_RESULT();
3210         HWRM_UNLOCK();
3211
3212         return rc;
3213 }
3214
3215 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3216 {
3217         uint32_t *flag = flagp;
3218
3219         vnic->flags = *flag;
3220 }
3221
3222 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3223 {
3224         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3225 }
3226
3227 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3228 {
3229         int rc = 0;
3230         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3231         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3232
3233         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3234
3235         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3236         req.req_buf_page_size = rte_cpu_to_le_16(
3237                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3238         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3239         req.req_buf_page_addr0 =
3240                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3241         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3242                 PMD_DRV_LOG(ERR,
3243                         "unable to map buffer address to physical memory\n");
3244                 return -ENOMEM;
3245         }
3246
3247         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3248
3249         HWRM_CHECK_RESULT();
3250         HWRM_UNLOCK();
3251
3252         return rc;
3253 }
3254
3255 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3256 {
3257         int rc = 0;
3258         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3259         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3260
3261         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3262                 return 0;
3263
3264         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3265
3266         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3267
3268         HWRM_CHECK_RESULT();
3269         HWRM_UNLOCK();
3270
3271         return rc;
3272 }
3273
3274 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3275 {
3276         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3277         struct hwrm_func_cfg_input req = {0};
3278         int rc;
3279
3280         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3281
3282         req.fid = rte_cpu_to_le_16(0xffff);
3283         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3284         req.enables = rte_cpu_to_le_32(
3285                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3286         req.async_event_cr = rte_cpu_to_le_16(
3287                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3289
3290         HWRM_CHECK_RESULT();
3291         HWRM_UNLOCK();
3292
3293         return rc;
3294 }
3295
3296 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3297 {
3298         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3299         struct hwrm_func_vf_cfg_input req = {0};
3300         int rc;
3301
3302         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3303
3304         req.enables = rte_cpu_to_le_32(
3305                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3306         req.async_event_cr = rte_cpu_to_le_16(
3307                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3308         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3309
3310         HWRM_CHECK_RESULT();
3311         HWRM_UNLOCK();
3312
3313         return rc;
3314 }
3315
3316 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3317 {
3318         struct hwrm_func_cfg_input req = {0};
3319         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3320         uint16_t dflt_vlan, fid;
3321         uint32_t func_cfg_flags;
3322         int rc = 0;
3323
3324         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3325
3326         if (is_vf) {
3327                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3328                 fid = bp->pf.vf_info[vf].fid;
3329                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3330         } else {
3331                 fid = rte_cpu_to_le_16(0xffff);
3332                 func_cfg_flags = bp->pf.func_cfg_flags;
3333                 dflt_vlan = bp->vlan;
3334         }
3335
3336         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3337         req.fid = rte_cpu_to_le_16(fid);
3338         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3339         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3340
3341         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3342
3343         HWRM_CHECK_RESULT();
3344         HWRM_UNLOCK();
3345
3346         return rc;
3347 }
3348
3349 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3350                         uint16_t max_bw, uint16_t enables)
3351 {
3352         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3353         struct hwrm_func_cfg_input req = {0};
3354         int rc;
3355
3356         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3357
3358         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3359         req.enables |= rte_cpu_to_le_32(enables);
3360         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3361         req.max_bw = rte_cpu_to_le_32(max_bw);
3362         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3363
3364         HWRM_CHECK_RESULT();
3365         HWRM_UNLOCK();
3366
3367         return rc;
3368 }
3369
3370 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3371 {
3372         struct hwrm_func_cfg_input req = {0};
3373         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3374         int rc = 0;
3375
3376         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3377
3378         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3379         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3380         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3381         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3382
3383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3384
3385         HWRM_CHECK_RESULT();
3386         HWRM_UNLOCK();
3387
3388         return rc;
3389 }
3390
3391 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3392 {
3393         int rc;
3394
3395         if (BNXT_PF(bp))
3396                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3397         else
3398                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3399
3400         return rc;
3401 }
3402
3403 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3404                               void *encaped, size_t ec_size)
3405 {
3406         int rc = 0;
3407         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3408         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3409
3410         if (ec_size > sizeof(req.encap_request))
3411                 return -1;
3412
3413         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3414
3415         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3416         memcpy(req.encap_request, encaped, ec_size);
3417
3418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3419
3420         HWRM_CHECK_RESULT();
3421         HWRM_UNLOCK();
3422
3423         return rc;
3424 }
3425
3426 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3427                                        struct rte_ether_addr *mac)
3428 {
3429         struct hwrm_func_qcfg_input req = {0};
3430         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3431         int rc;
3432
3433         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3434
3435         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3437
3438         HWRM_CHECK_RESULT();
3439
3440         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3441
3442         HWRM_UNLOCK();
3443
3444         return rc;
3445 }
3446
3447 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3448                             void *encaped, size_t ec_size)
3449 {
3450         int rc = 0;
3451         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3452         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3453
3454         if (ec_size > sizeof(req.encap_request))
3455                 return -1;
3456
3457         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3458
3459         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3460         memcpy(req.encap_request, encaped, ec_size);
3461
3462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3463
3464         HWRM_CHECK_RESULT();
3465         HWRM_UNLOCK();
3466
3467         return rc;
3468 }
3469
3470 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3471                          struct rte_eth_stats *stats, uint8_t rx)
3472 {
3473         int rc = 0;
3474         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3475         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3476
3477         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3478
3479         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3480
3481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3482
3483         HWRM_CHECK_RESULT();
3484
3485         if (rx) {
3486                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3487                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3488                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3489                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3490                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3491                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3492                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3493                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3494         } else {
3495                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3496                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3497                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3498                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3499                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3500                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3501         }
3502
3503
3504         HWRM_UNLOCK();
3505
3506         return rc;
3507 }
3508
3509 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3510 {
3511         struct hwrm_port_qstats_input req = {0};
3512         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3513         struct bnxt_pf_info *pf = &bp->pf;
3514         int rc;
3515
3516         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3517
3518         req.port_id = rte_cpu_to_le_16(pf->port_id);
3519         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3520         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3522
3523         HWRM_CHECK_RESULT();
3524         HWRM_UNLOCK();
3525
3526         return rc;
3527 }
3528
3529 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3530 {
3531         struct hwrm_port_clr_stats_input req = {0};
3532         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3533         struct bnxt_pf_info *pf = &bp->pf;
3534         int rc;
3535
3536         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3537         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3538             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3539                 return 0;
3540
3541         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3542
3543         req.port_id = rte_cpu_to_le_16(pf->port_id);
3544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3545
3546         HWRM_CHECK_RESULT();
3547         HWRM_UNLOCK();
3548
3549         return rc;
3550 }
3551
3552 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3553 {
3554         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3555         struct hwrm_port_led_qcaps_input req = {0};
3556         int rc;
3557
3558         if (BNXT_VF(bp))
3559                 return 0;
3560
3561         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3562         req.port_id = bp->pf.port_id;
3563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3564
3565         HWRM_CHECK_RESULT();
3566
3567         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3568                 unsigned int i;
3569
3570                 bp->num_leds = resp->num_leds;
3571                 memcpy(bp->leds, &resp->led0_id,
3572                         sizeof(bp->leds[0]) * bp->num_leds);
3573                 for (i = 0; i < bp->num_leds; i++) {
3574                         struct bnxt_led_info *led = &bp->leds[i];
3575
3576                         uint16_t caps = led->led_state_caps;
3577
3578                         if (!led->led_group_id ||
3579                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3580                                 bp->num_leds = 0;
3581                                 break;
3582                         }
3583                 }
3584         }
3585
3586         HWRM_UNLOCK();
3587
3588         return rc;
3589 }
3590
3591 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3592 {
3593         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3594         struct hwrm_port_led_cfg_input req = {0};
3595         struct bnxt_led_cfg *led_cfg;
3596         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3597         uint16_t duration = 0;
3598         int rc, i;
3599
3600         if (!bp->num_leds || BNXT_VF(bp))
3601                 return -EOPNOTSUPP;
3602
3603         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3604
3605         if (led_on) {
3606                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3607                 duration = rte_cpu_to_le_16(500);
3608         }
3609         req.port_id = bp->pf.port_id;
3610         req.num_leds = bp->num_leds;
3611         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3612         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3613                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3614                 led_cfg->led_id = bp->leds[i].led_id;
3615                 led_cfg->led_state = led_state;
3616                 led_cfg->led_blink_on = duration;
3617                 led_cfg->led_blink_off = duration;
3618                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3619         }
3620
3621         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3622
3623         HWRM_CHECK_RESULT();
3624         HWRM_UNLOCK();
3625
3626         return rc;
3627 }
3628
3629 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3630                                uint32_t *length)
3631 {
3632         int rc;
3633         struct hwrm_nvm_get_dir_info_input req = {0};
3634         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3635
3636         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3637
3638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3639
3640         HWRM_CHECK_RESULT();
3641
3642         *entries = rte_le_to_cpu_32(resp->entries);
3643         *length = rte_le_to_cpu_32(resp->entry_length);
3644
3645         HWRM_UNLOCK();
3646         return rc;
3647 }
3648
3649 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3650 {
3651         int rc;
3652         uint32_t dir_entries;
3653         uint32_t entry_length;
3654         uint8_t *buf;
3655         size_t buflen;
3656         rte_iova_t dma_handle;
3657         struct hwrm_nvm_get_dir_entries_input req = {0};
3658         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3659
3660         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3661         if (rc != 0)
3662                 return rc;
3663
3664         *data++ = dir_entries;
3665         *data++ = entry_length;
3666         len -= 2;
3667         memset(data, 0xff, len);
3668
3669         buflen = dir_entries * entry_length;
3670         buf = rte_malloc("nvm_dir", buflen, 0);
3671         rte_mem_lock_page(buf);
3672         if (buf == NULL)
3673                 return -ENOMEM;
3674         dma_handle = rte_mem_virt2iova(buf);
3675         if (dma_handle == RTE_BAD_IOVA) {
3676                 PMD_DRV_LOG(ERR,
3677                         "unable to map response address to physical memory\n");
3678                 return -ENOMEM;
3679         }
3680         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3681         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3683
3684         if (rc == 0)
3685                 memcpy(data, buf, len > buflen ? buflen : len);
3686
3687         rte_free(buf);
3688         HWRM_CHECK_RESULT();
3689         HWRM_UNLOCK();
3690
3691         return rc;
3692 }
3693
3694 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3695                              uint32_t offset, uint32_t length,
3696                              uint8_t *data)
3697 {
3698         int rc;
3699         uint8_t *buf;
3700         rte_iova_t dma_handle;
3701         struct hwrm_nvm_read_input req = {0};
3702         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3703
3704         buf = rte_malloc("nvm_item", length, 0);
3705         rte_mem_lock_page(buf);
3706         if (!buf)
3707                 return -ENOMEM;
3708
3709         dma_handle = rte_mem_virt2iova(buf);
3710         if (dma_handle == RTE_BAD_IOVA) {
3711                 PMD_DRV_LOG(ERR,
3712                         "unable to map response address to physical memory\n");
3713                 return -ENOMEM;
3714         }
3715         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3716         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3717         req.dir_idx = rte_cpu_to_le_16(index);
3718         req.offset = rte_cpu_to_le_32(offset);
3719         req.len = rte_cpu_to_le_32(length);
3720         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3721         if (rc == 0)
3722                 memcpy(data, buf, length);
3723
3724         rte_free(buf);
3725         HWRM_CHECK_RESULT();
3726         HWRM_UNLOCK();
3727
3728         return rc;
3729 }
3730
3731 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3732 {
3733         int rc;
3734         struct hwrm_nvm_erase_dir_entry_input req = {0};
3735         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3736
3737         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3738         req.dir_idx = rte_cpu_to_le_16(index);
3739         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3740         HWRM_CHECK_RESULT();
3741         HWRM_UNLOCK();
3742
3743         return rc;
3744 }
3745
3746
3747 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3748                           uint16_t dir_ordinal, uint16_t dir_ext,
3749                           uint16_t dir_attr, const uint8_t *data,
3750                           size_t data_len)
3751 {
3752         int rc;
3753         struct hwrm_nvm_write_input req = {0};
3754         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3755         rte_iova_t dma_handle;
3756         uint8_t *buf;
3757
3758         buf = rte_malloc("nvm_write", data_len, 0);
3759         rte_mem_lock_page(buf);
3760         if (!buf)
3761                 return -ENOMEM;
3762
3763         dma_handle = rte_mem_virt2iova(buf);
3764         if (dma_handle == RTE_BAD_IOVA) {
3765                 PMD_DRV_LOG(ERR,
3766                         "unable to map response address to physical memory\n");
3767                 return -ENOMEM;
3768         }
3769         memcpy(buf, data, data_len);
3770
3771         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3772
3773         req.dir_type = rte_cpu_to_le_16(dir_type);
3774         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3775         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3776         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3777         req.dir_data_length = rte_cpu_to_le_32(data_len);
3778         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3779
3780         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3781
3782         rte_free(buf);
3783         HWRM_CHECK_RESULT();
3784         HWRM_UNLOCK();
3785
3786         return rc;
3787 }
3788
3789 static void
3790 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3791 {
3792         uint32_t *count = cbdata;
3793
3794         *count = *count + 1;
3795 }
3796
3797 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3798                                      struct bnxt_vnic_info *vnic __rte_unused)
3799 {
3800         return 0;
3801 }
3802
3803 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3804 {
3805         uint32_t count = 0;
3806
3807         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3808             &count, bnxt_vnic_count_hwrm_stub);
3809
3810         return count;
3811 }
3812
3813 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3814                                         uint16_t *vnic_ids)
3815 {
3816         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3817         struct hwrm_func_vf_vnic_ids_query_output *resp =
3818                                                 bp->hwrm_cmd_resp_addr;
3819         int rc;
3820
3821         /* First query all VNIC ids */
3822         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3823
3824         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3825         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3826         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3827
3828         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3829                 HWRM_UNLOCK();
3830                 PMD_DRV_LOG(ERR,
3831                 "unable to map VNIC ID table address to physical memory\n");
3832                 return -ENOMEM;
3833         }
3834         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3835         HWRM_CHECK_RESULT();
3836         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3837
3838         HWRM_UNLOCK();
3839
3840         return rc;
3841 }
3842
3843 /*
3844  * This function queries the VNIC IDs  for a specified VF. It then calls
3845  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3846  * Then it calls the hwrm_cb function to program this new vnic configuration.
3847  */
3848 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3849         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3850         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3851 {
3852         struct bnxt_vnic_info vnic;
3853         int rc = 0;
3854         int i, num_vnic_ids;
3855         uint16_t *vnic_ids;
3856         size_t vnic_id_sz;
3857         size_t sz;
3858
3859         /* First query all VNIC ids */
3860         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3861         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3862                         RTE_CACHE_LINE_SIZE);
3863         if (vnic_ids == NULL)
3864                 return -ENOMEM;
3865
3866         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3867                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3868
3869         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3870
3871         if (num_vnic_ids < 0)
3872                 return num_vnic_ids;
3873
3874         /* Retrieve VNIC, update bd_stall then update */
3875
3876         for (i = 0; i < num_vnic_ids; i++) {
3877                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3878                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3879                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3880                 if (rc)
3881                         break;
3882                 if (vnic.mru <= 4)      /* Indicates unallocated */
3883                         continue;
3884
3885                 vnic_cb(&vnic, cbdata);
3886
3887                 rc = hwrm_cb(bp, &vnic);
3888                 if (rc)
3889                         break;
3890         }
3891
3892         rte_free(vnic_ids);
3893
3894         return rc;
3895 }
3896
3897 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3898                                               bool on)
3899 {
3900         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3901         struct hwrm_func_cfg_input req = {0};
3902         int rc;
3903
3904         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3905
3906         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3907         req.enables |= rte_cpu_to_le_32(
3908                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3909         req.vlan_antispoof_mode = on ?
3910                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3911                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3913
3914         HWRM_CHECK_RESULT();
3915         HWRM_UNLOCK();
3916
3917         return rc;
3918 }
3919
3920 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3921 {
3922         struct bnxt_vnic_info vnic;
3923         uint16_t *vnic_ids;
3924         size_t vnic_id_sz;
3925         int num_vnic_ids, i;
3926         size_t sz;
3927         int rc;
3928
3929         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3930         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3931                         RTE_CACHE_LINE_SIZE);
3932         if (vnic_ids == NULL)
3933                 return -ENOMEM;
3934
3935         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3936                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3937
3938         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3939         if (rc <= 0)
3940                 goto exit;
3941         num_vnic_ids = rc;
3942
3943         /*
3944          * Loop through to find the default VNIC ID.
3945          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3946          * by sending the hwrm_func_qcfg command to the firmware.
3947          */
3948         for (i = 0; i < num_vnic_ids; i++) {
3949                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3950                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3951                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3952                                         bp->pf.first_vf_id + vf);
3953                 if (rc)
3954                         goto exit;
3955                 if (vnic.func_default) {
3956                         rte_free(vnic_ids);
3957                         return vnic.fw_vnic_id;
3958                 }
3959         }
3960         /* Could not find a default VNIC. */
3961         PMD_DRV_LOG(ERR, "No default VNIC\n");
3962 exit:
3963         rte_free(vnic_ids);
3964         return rc;
3965 }
3966
3967 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3968                          uint16_t dst_id,
3969                          struct bnxt_filter_info *filter)
3970 {
3971         int rc = 0;
3972         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3973         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3974         uint32_t enables = 0;
3975
3976         if (filter->fw_em_filter_id != UINT64_MAX)
3977                 bnxt_hwrm_clear_em_filter(bp, filter);
3978
3979         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3980
3981         req.flags = rte_cpu_to_le_32(filter->flags);
3982
3983         enables = filter->enables |
3984               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3985         req.dst_id = rte_cpu_to_le_16(dst_id);
3986
3987         if (filter->ip_addr_type) {
3988                 req.ip_addr_type = filter->ip_addr_type;
3989                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3990         }
3991         if (enables &
3992             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3993                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3994         if (enables &
3995             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3996                 memcpy(req.src_macaddr, filter->src_macaddr,
3997                        RTE_ETHER_ADDR_LEN);
3998         if (enables &
3999             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4000                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4001                        RTE_ETHER_ADDR_LEN);
4002         if (enables &
4003             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4004                 req.ovlan_vid = filter->l2_ovlan;
4005         if (enables &
4006             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4007                 req.ivlan_vid = filter->l2_ivlan;
4008         if (enables &
4009             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4010                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4011         if (enables &
4012             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4013                 req.ip_protocol = filter->ip_protocol;
4014         if (enables &
4015             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4016                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4017         if (enables &
4018             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4019                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4020         if (enables &
4021             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4022                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4023         if (enables &
4024             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4025                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4026         if (enables &
4027             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4028                 req.mirror_vnic_id = filter->mirror_vnic_id;
4029
4030         req.enables = rte_cpu_to_le_32(enables);
4031
4032         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4033
4034         HWRM_CHECK_RESULT();
4035
4036         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4037         HWRM_UNLOCK();
4038
4039         return rc;
4040 }
4041
4042 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4043 {
4044         int rc = 0;
4045         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4046         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4047
4048         if (filter->fw_em_filter_id == UINT64_MAX)
4049                 return 0;
4050
4051         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4052         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4053
4054         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4055
4056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4057
4058         HWRM_CHECK_RESULT();
4059         HWRM_UNLOCK();
4060
4061         filter->fw_em_filter_id = UINT64_MAX;
4062         filter->fw_l2_filter_id = UINT64_MAX;
4063
4064         return 0;
4065 }
4066
4067 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4068                          uint16_t dst_id,
4069                          struct bnxt_filter_info *filter)
4070 {
4071         int rc = 0;
4072         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4073         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4074                                                 bp->hwrm_cmd_resp_addr;
4075         uint32_t enables = 0;
4076
4077         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4078                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4079
4080         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4081
4082         req.flags = rte_cpu_to_le_32(filter->flags);
4083
4084         enables = filter->enables |
4085               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4086         req.dst_id = rte_cpu_to_le_16(dst_id);
4087
4088
4089         if (filter->ip_addr_type) {
4090                 req.ip_addr_type = filter->ip_addr_type;
4091                 enables |=
4092                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4093         }
4094         if (enables &
4095             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4096                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4097         if (enables &
4098             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4099                 memcpy(req.src_macaddr, filter->src_macaddr,
4100                        RTE_ETHER_ADDR_LEN);
4101         //if (enables &
4102             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4103                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4104                        //RTE_ETHER_ADDR_LEN);
4105         if (enables &
4106             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4107                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4108         if (enables &
4109             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4110                 req.ip_protocol = filter->ip_protocol;
4111         if (enables &
4112             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4113                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4114         if (enables &
4115             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4116                 req.src_ipaddr_mask[0] =
4117                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4118         if (enables &
4119             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4120                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4121         if (enables &
4122             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4123                 req.dst_ipaddr_mask[0] =
4124                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4125         if (enables &
4126             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4127                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4128         if (enables &
4129             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4130                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4131         if (enables &
4132             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4133                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4134         if (enables &
4135             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4136                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4137         if (enables &
4138             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4139                 req.mirror_vnic_id = filter->mirror_vnic_id;
4140
4141         req.enables = rte_cpu_to_le_32(enables);
4142
4143         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4144
4145         HWRM_CHECK_RESULT();
4146
4147         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4148         HWRM_UNLOCK();
4149
4150         return rc;
4151 }
4152
4153 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4154                                 struct bnxt_filter_info *filter)
4155 {
4156         int rc = 0;
4157         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4158         struct hwrm_cfa_ntuple_filter_free_output *resp =
4159                                                 bp->hwrm_cmd_resp_addr;
4160
4161         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4162                 return 0;
4163
4164         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4165
4166         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4167
4168         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4169
4170         HWRM_CHECK_RESULT();
4171         HWRM_UNLOCK();
4172
4173         filter->fw_ntuple_filter_id = UINT64_MAX;
4174
4175         return 0;
4176 }
4177
4178 static int
4179 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4180 {
4181         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4182         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4183         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4184         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4185         uint16_t *ring_tbl = vnic->rss_table;
4186         int nr_ctxs = vnic->num_lb_ctxts;
4187         int max_rings = bp->rx_nr_rings;
4188         int i, j, k, cnt;
4189         int rc = 0;
4190
4191         for (i = 0, k = 0; i < nr_ctxs; i++) {
4192                 struct bnxt_rx_ring_info *rxr;
4193                 struct bnxt_cp_ring_info *cpr;
4194
4195                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4196
4197                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4198                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4199                 req.hash_mode_flags = vnic->hash_mode;
4200
4201                 req.ring_grp_tbl_addr =
4202                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4203                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4204                                      2 * sizeof(*ring_tbl));
4205                 req.hash_key_tbl_addr =
4206                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4207
4208                 req.ring_table_pair_index = i;
4209                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4210
4211                 for (j = 0; j < 64; j++) {
4212                         uint16_t ring_id;
4213
4214                         /* Find next active ring. */
4215                         for (cnt = 0; cnt < max_rings; cnt++) {
4216                                 if (rx_queue_state[k] !=
4217                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4218                                         break;
4219                                 if (++k == max_rings)
4220                                         k = 0;
4221                         }
4222
4223                         /* Return if no rings are active. */
4224                         if (cnt == max_rings)
4225                                 return 0;
4226
4227                         /* Add rx/cp ring pair to RSS table. */
4228                         rxr = rxqs[k]->rx_ring;
4229                         cpr = rxqs[k]->cp_ring;
4230
4231                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4232                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4233                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4234                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4235
4236                         if (++k == max_rings)
4237                                 k = 0;
4238                 }
4239                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4240                                             BNXT_USE_CHIMP_MB);
4241
4242                 HWRM_CHECK_RESULT();
4243                 HWRM_UNLOCK();
4244         }
4245
4246         return rc;
4247 }
4248
4249 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4250 {
4251         unsigned int rss_idx, fw_idx, i;
4252
4253         if (!(vnic->rss_table && vnic->hash_type))
4254                 return 0;
4255
4256         if (BNXT_CHIP_THOR(bp))
4257                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4258
4259         /*
4260          * Fill the RSS hash & redirection table with
4261          * ring group ids for all VNICs
4262          */
4263         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4264                 rss_idx++, fw_idx++) {
4265                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4266                         fw_idx %= bp->rx_cp_nr_rings;
4267                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4268                                 break;
4269                         fw_idx++;
4270                 }
4271                 if (i == bp->rx_cp_nr_rings)
4272                         return 0;
4273                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4274         }
4275         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4276 }
4277
4278 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4279         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4280 {
4281         uint16_t flags;
4282
4283         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4284
4285         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4286         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4287
4288         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4289         req->num_cmpl_dma_aggr_during_int =
4290                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4291
4292         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4293
4294         /* min timer set to 1/2 of interrupt timer */
4295         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4296
4297         /* buf timer set to 1/4 of interrupt timer */
4298         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4299
4300         req->cmpl_aggr_dma_tmr_during_int =
4301                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4302
4303         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4304                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4305         req->flags = rte_cpu_to_le_16(flags);
4306 }
4307
4308 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4309                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4310 {
4311         struct hwrm_ring_aggint_qcaps_input req = {0};
4312         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4313         uint32_t enables;
4314         uint16_t flags;
4315         int rc;
4316
4317         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4319         HWRM_CHECK_RESULT();
4320
4321         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4322         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4323
4324         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4325                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4326         agg_req->flags = rte_cpu_to_le_16(flags);
4327         enables =
4328          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4329          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4330         agg_req->enables = rte_cpu_to_le_32(enables);
4331
4332         HWRM_UNLOCK();
4333         return rc;
4334 }
4335
4336 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4337                         struct bnxt_coal *coal, uint16_t ring_id)
4338 {
4339         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4340         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4341                                                 bp->hwrm_cmd_resp_addr;
4342         int rc;
4343
4344         /* Set ring coalesce parameters only for 100G NICs */
4345         if (BNXT_CHIP_THOR(bp)) {
4346                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4347                         return -1;
4348         } else if (bnxt_stratus_device(bp)) {
4349                 bnxt_hwrm_set_coal_params(coal, &req);
4350         } else {
4351                 return 0;
4352         }
4353
4354         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4355         req.ring_id = rte_cpu_to_le_16(ring_id);
4356         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4357         HWRM_CHECK_RESULT();
4358         HWRM_UNLOCK();
4359         return 0;
4360 }
4361
4362 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4363 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4364 {
4365         struct hwrm_func_backing_store_qcaps_input req = {0};
4366         struct hwrm_func_backing_store_qcaps_output *resp =
4367                 bp->hwrm_cmd_resp_addr;
4368         int rc;
4369
4370         if (!BNXT_CHIP_THOR(bp) ||
4371             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4372             BNXT_VF(bp) ||
4373             bp->ctx)
4374                 return 0;
4375
4376         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4378         HWRM_CHECK_RESULT_SILENT();
4379
4380         if (!rc) {
4381                 struct bnxt_ctx_pg_info *ctx_pg;
4382                 struct bnxt_ctx_mem_info *ctx;
4383                 int total_alloc_len;
4384                 int i;
4385
4386                 total_alloc_len = sizeof(*ctx);
4387                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4388                                  RTE_CACHE_LINE_SIZE);
4389                 if (!ctx) {
4390                         rc = -ENOMEM;
4391                         goto ctx_err;
4392                 }
4393                 memset(ctx, 0, total_alloc_len);
4394
4395                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4396                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4397                                     RTE_CACHE_LINE_SIZE);
4398                 if (!ctx_pg) {
4399                         rc = -ENOMEM;
4400                         goto ctx_err;
4401                 }
4402                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4403                         ctx->tqm_mem[i] = ctx_pg;
4404
4405                 bp->ctx = ctx;
4406                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4407                 ctx->qp_min_qp1_entries =
4408                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4409                 ctx->qp_max_l2_entries =
4410                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4411                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4412                 ctx->srq_max_l2_entries =
4413                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4414                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4415                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4416                 ctx->cq_max_l2_entries =
4417                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4418                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4419                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4420                 ctx->vnic_max_vnic_entries =
4421                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4422                 ctx->vnic_max_ring_table_entries =
4423                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4424                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4425                 ctx->stat_max_entries =
4426                         rte_le_to_cpu_32(resp->stat_max_entries);
4427                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4428                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4429                 ctx->tqm_min_entries_per_ring =
4430                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4431                 ctx->tqm_max_entries_per_ring =
4432                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4433                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4434                 if (!ctx->tqm_entries_multiple)
4435                         ctx->tqm_entries_multiple = 1;
4436                 ctx->mrav_max_entries =
4437                         rte_le_to_cpu_32(resp->mrav_max_entries);
4438                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4439                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4440                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4441         } else {
4442                 rc = 0;
4443         }
4444 ctx_err:
4445         HWRM_UNLOCK();
4446         return rc;
4447 }
4448
4449 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4450 {
4451         struct hwrm_func_backing_store_cfg_input req = {0};
4452         struct hwrm_func_backing_store_cfg_output *resp =
4453                 bp->hwrm_cmd_resp_addr;
4454         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4455         struct bnxt_ctx_pg_info *ctx_pg;
4456         uint32_t *num_entries;
4457         uint64_t *pg_dir;
4458         uint8_t *pg_attr;
4459         uint32_t ena;
4460         int i, rc;
4461
4462         if (!ctx)
4463                 return 0;
4464
4465         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4466         req.enables = rte_cpu_to_le_32(enables);
4467
4468         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4469                 ctx_pg = &ctx->qp_mem;
4470                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4471                 req.qp_num_qp1_entries =
4472                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4473                 req.qp_num_l2_entries =
4474                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4475                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4476                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4477                                       &req.qpc_pg_size_qpc_lvl,
4478                                       &req.qpc_page_dir);
4479         }
4480
4481         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4482                 ctx_pg = &ctx->srq_mem;
4483                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4484                 req.srq_num_l2_entries =
4485                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4486                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4487                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4488                                       &req.srq_pg_size_srq_lvl,
4489                                       &req.srq_page_dir);
4490         }
4491
4492         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4493                 ctx_pg = &ctx->cq_mem;
4494                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4495                 req.cq_num_l2_entries =
4496                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4497                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4498                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4499                                       &req.cq_pg_size_cq_lvl,
4500                                       &req.cq_page_dir);
4501         }
4502
4503         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4504                 ctx_pg = &ctx->vnic_mem;
4505                 req.vnic_num_vnic_entries =
4506                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4507                 req.vnic_num_ring_table_entries =
4508                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4509                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4510                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4511                                       &req.vnic_pg_size_vnic_lvl,
4512                                       &req.vnic_page_dir);
4513         }
4514
4515         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4516                 ctx_pg = &ctx->stat_mem;
4517                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4518                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4519                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4520                                       &req.stat_pg_size_stat_lvl,
4521                                       &req.stat_page_dir);
4522         }
4523
4524         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4525         num_entries = &req.tqm_sp_num_entries;
4526         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4527         pg_dir = &req.tqm_sp_page_dir;
4528         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4529         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4530                 if (!(enables & ena))
4531                         continue;
4532
4533                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4534
4535                 ctx_pg = ctx->tqm_mem[i];
4536                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4537                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4538         }
4539
4540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4541         HWRM_CHECK_RESULT();
4542         HWRM_UNLOCK();
4543
4544         return rc;
4545 }
4546
4547 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4548 {
4549         struct hwrm_port_qstats_ext_input req = {0};
4550         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4551         struct bnxt_pf_info *pf = &bp->pf;
4552         int rc;
4553
4554         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4555               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4556                 return 0;
4557
4558         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4559
4560         req.port_id = rte_cpu_to_le_16(pf->port_id);
4561         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4562                 req.tx_stat_host_addr =
4563                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4564                 req.tx_stat_size =
4565                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4566         }
4567         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4568                 req.rx_stat_host_addr =
4569                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4570                 req.rx_stat_size =
4571                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4572         }
4573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4574
4575         if (rc) {
4576                 bp->fw_rx_port_stats_ext_size = 0;
4577                 bp->fw_tx_port_stats_ext_size = 0;
4578         } else {
4579                 bp->fw_rx_port_stats_ext_size =
4580                         rte_le_to_cpu_16(resp->rx_stat_size);
4581                 bp->fw_tx_port_stats_ext_size =
4582                         rte_le_to_cpu_16(resp->tx_stat_size);
4583         }
4584
4585         HWRM_CHECK_RESULT();
4586         HWRM_UNLOCK();
4587
4588         return rc;
4589 }
4590
4591 int
4592 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4593 {
4594         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4595         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4596                 bp->hwrm_cmd_resp_addr;
4597         int rc = 0;
4598
4599         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4600         req.tunnel_type = type;
4601         req.dest_fid = bp->fw_fid;
4602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4603         HWRM_CHECK_RESULT();
4604
4605         HWRM_UNLOCK();
4606
4607         return rc;
4608 }
4609
4610 int
4611 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4612 {
4613         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4614         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4615                 bp->hwrm_cmd_resp_addr;
4616         int rc = 0;
4617
4618         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4619         req.tunnel_type = type;
4620         req.dest_fid = bp->fw_fid;
4621         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4622         HWRM_CHECK_RESULT();
4623
4624         HWRM_UNLOCK();
4625
4626         return rc;
4627 }
4628
4629 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4630 {
4631         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4632         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4633                 bp->hwrm_cmd_resp_addr;
4634         int rc = 0;
4635
4636         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4637         req.src_fid = bp->fw_fid;
4638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4639         HWRM_CHECK_RESULT();
4640
4641         if (type)
4642                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4643
4644         HWRM_UNLOCK();
4645
4646         return rc;
4647 }
4648
4649 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4650                                    uint16_t *dst_fid)
4651 {
4652         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4653         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4654                 bp->hwrm_cmd_resp_addr;
4655         int rc = 0;
4656
4657         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4658         req.src_fid = bp->fw_fid;
4659         req.tunnel_type = tun_type;
4660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4661         HWRM_CHECK_RESULT();
4662
4663         if (dst_fid)
4664                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4665
4666         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4667
4668         HWRM_UNLOCK();
4669
4670         return rc;
4671 }
4672
4673 int bnxt_hwrm_set_mac(struct bnxt *bp)
4674 {
4675         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4676         struct hwrm_func_vf_cfg_input req = {0};
4677         int rc = 0;
4678
4679         if (!BNXT_VF(bp))
4680                 return 0;
4681
4682         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4683
4684         req.enables =
4685                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4686         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4687
4688         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4689
4690         HWRM_CHECK_RESULT();
4691
4692         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4693         HWRM_UNLOCK();
4694
4695         return rc;
4696 }
4697
4698 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4699 {
4700         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4701         struct hwrm_func_drv_if_change_input req = {0};
4702         uint32_t flags;
4703         int rc;
4704
4705         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4706                 return 0;
4707
4708         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4709          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4710          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4711          */
4712         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4713                 return 0;
4714
4715         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4716
4717         if (up)
4718                 req.flags =
4719                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4720
4721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4722
4723         HWRM_CHECK_RESULT();
4724         flags = rte_le_to_cpu_32(resp->flags);
4725         HWRM_UNLOCK();
4726
4727         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4728                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4729                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4730         }
4731
4732         return 0;
4733 }
4734
4735 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4736 {
4737         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4738         struct bnxt_error_recovery_info *info = bp->recovery_info;
4739         struct hwrm_error_recovery_qcfg_input req = {0};
4740         uint32_t flags = 0;
4741         unsigned int i;
4742         int rc;
4743
4744         /* Older FW does not have error recovery support */
4745         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4746                 return 0;
4747
4748         if (!info) {
4749                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4750                                    sizeof(*info), 0);
4751                 bp->recovery_info = info;
4752                 if (info == NULL)
4753                         return -ENOMEM;
4754         } else {
4755                 memset(info, 0, sizeof(*info));
4756         }
4757
4758         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4759
4760         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4761
4762         HWRM_CHECK_RESULT();
4763
4764         flags = rte_le_to_cpu_32(resp->flags);
4765         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4766                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4767         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4768                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4769
4770         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4771             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4772                 rc = -EINVAL;
4773                 goto err;
4774         }
4775
4776         /* FW returned values are in units of 100msec */
4777         info->driver_polling_freq =
4778                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4779         info->master_func_wait_period =
4780                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4781         info->normal_func_wait_period =
4782                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4783         info->master_func_wait_period_after_reset =
4784                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4785         info->max_bailout_time_after_reset =
4786                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4787         info->status_regs[BNXT_FW_STATUS_REG] =
4788                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4789         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4790                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4791         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4792                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4793         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4794                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4795         info->reg_array_cnt =
4796                 rte_le_to_cpu_32(resp->reg_array_cnt);
4797
4798         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4799                 rc = -EINVAL;
4800                 goto err;
4801         }
4802
4803         for (i = 0; i < info->reg_array_cnt; i++) {
4804                 info->reset_reg[i] =
4805                         rte_le_to_cpu_32(resp->reset_reg[i]);
4806                 info->reset_reg_val[i] =
4807                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4808                 info->delay_after_reset[i] =
4809                         resp->delay_after_reset[i];
4810         }
4811 err:
4812         HWRM_UNLOCK();
4813
4814         /* Map the FW status registers */
4815         if (!rc)
4816                 rc = bnxt_map_fw_health_status_regs(bp);
4817
4818         if (rc) {
4819                 rte_free(bp->recovery_info);
4820                 bp->recovery_info = NULL;
4821         }
4822         return rc;
4823 }
4824
4825 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4826 {
4827         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4828         struct hwrm_fw_reset_input req = {0};
4829         int rc;
4830
4831         if (!BNXT_PF(bp))
4832                 return -EOPNOTSUPP;
4833
4834         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4835
4836         req.embedded_proc_type =
4837                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4838         req.selfrst_status =
4839                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4840         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4841
4842         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4843                                     BNXT_USE_KONG(bp));
4844
4845         HWRM_CHECK_RESULT();
4846         HWRM_UNLOCK();
4847
4848         return rc;
4849 }
4850
4851 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4852 {
4853         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4854         struct hwrm_port_ts_query_input req = {0};
4855         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4856         uint32_t flags = 0;
4857         int rc;
4858
4859         if (!ptp)
4860                 return 0;
4861
4862         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4863
4864         switch (path) {
4865         case BNXT_PTP_FLAGS_PATH_TX:
4866                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4867                 break;
4868         case BNXT_PTP_FLAGS_PATH_RX:
4869                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4870                 break;
4871         case BNXT_PTP_FLAGS_CURRENT_TIME:
4872                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4873                 break;
4874         }
4875
4876         req.flags = rte_cpu_to_le_32(flags);
4877         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4878
4879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4880
4881         HWRM_CHECK_RESULT();
4882
4883         if (timestamp) {
4884                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4885                 *timestamp |=
4886                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4887         }
4888         HWRM_UNLOCK();
4889
4890         return rc;
4891 }