drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns. If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521         if (ptp)
 522                 return 0;
 523
 524         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 525
 526         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 527
 528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 529
 530         HWRM_CHECK_RESULT();
 531
 532         if (!BNXT_CHIP_THOR(bp) &&
 533             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 534                 return 0;
 535
 536         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 537                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 538
 539         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 540         if (!ptp)
 541                 return -ENOMEM;
 542
 543         if (!BNXT_CHIP_THOR(bp)) {
 544                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 545                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 546                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 547                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 548                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 549                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 550                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 551                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 552                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 554                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 555                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 556                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 557                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 558                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 559                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 560                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 561                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 562         }
 563
 564         ptp->bp = bp;
 565         bp->ptp_cfg = ptp;
 566
 567         return 0;
 568 }
 569
 570 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 571 {
 572         int rc = 0;
 573         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 574         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 575         uint16_t new_max_vfs;
 576         uint32_t flags;
 577         int i;
 578
 579         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 580
 581         req.fid = rte_cpu_to_le_16(0xffff);
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 584
 585         HWRM_CHECK_RESULT();
 586
 587         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 588         flags = rte_le_to_cpu_32(resp->flags);
 589         if (BNXT_PF(bp)) {
 590                 bp->pf.port_id = resp->port_id;
 591                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 592                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 593                 new_max_vfs = bp->pdev->max_vfs;
 594                 if (new_max_vfs != bp->pf.max_vfs) {
 595                         if (bp->pf.vf_info)
 596                                 rte_free(bp->pf.vf_info);
 597                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 598                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 599                         bp->pf.max_vfs = new_max_vfs;
 600                         for (i = 0; i < new_max_vfs; i++) {
 601                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 602                                 bp->pf.vf_info[i].vlan_table =
 603                                         rte_zmalloc("VF VLAN table",
 604                                                     getpagesize(),
 605                                                     getpagesize());
 606                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 607                                         PMD_DRV_LOG(ERR,
 608                                         "Fail to alloc VLAN table for VF %d\n",
 609                                         i);
 610                                 else
 611                                         rte_mem_lock_page(
 612                                                 bp->pf.vf_info[i].vlan_table);
 613                                 bp->pf.vf_info[i].vlan_as_table =
 614                                         rte_zmalloc("VF VLAN AS table",
 615                                                     getpagesize(),
 616                                                     getpagesize());
 617                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 618                                         PMD_DRV_LOG(ERR,
 619                                         "Alloc VLAN AS table for VF %d fail\n",
 620                                         i);
 621                                 else
 622                                         rte_mem_lock_page(
 623                                                bp->pf.vf_info[i].vlan_as_table);
 624                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 625                         }
 626                 }
 627         }
 628
 629         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 630         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 631         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 632         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 633         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 634         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 635         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 636         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 637         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 638         if (!BNXT_CHIP_THOR(bp))
 639                 bp->max_l2_ctx += bp->max_rx_em_flows;
 640         /* TODO: For now, do not support VMDq/RFS on VFs. */
 641         if (BNXT_PF(bp)) {
 642                 if (bp->pf.max_vfs)
 643                         bp->max_vnics = 1;
 644                 else
 645                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 646         } else {
 647                 bp->max_vnics = 1;
 648         }
 649         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 650         if (BNXT_PF(bp)) {
 651                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 652                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 653                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 654                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 655                         HWRM_UNLOCK();
 656                         bnxt_hwrm_ptp_qcfg(bp);
 657                 }
 658         }
 659
 660         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 661                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 662
 663         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 664                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 665                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 666         }
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 669                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 672                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 673
 674         HWRM_UNLOCK();
 675
 676         return rc;
 677 }
 678
 679 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 680 {
 681         int rc;
 682
 683         rc = __bnxt_hwrm_func_qcaps(bp);
 684         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 685                 rc = bnxt_alloc_ctx_mem(bp);
 686                 if (rc)
 687                         return rc;
 688
 689                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 690                 if (!rc)
 691                         bp->flags |= BNXT_FLAG_NEW_RM;
 692         }
 693
 694         /* On older FW,
 695          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 696          * But the error can be ignored. Return success.
 697          */
 698
 699         return 0;
 700 }
 701
 702 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 703 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 704 {
 705         int rc = 0;
 706         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 707         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 708
 709         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 710
 711         req.target_id = rte_cpu_to_le_16(0xffff);
 712
 713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 714
 715         HWRM_CHECK_RESULT();
 716
 717         if (rte_le_to_cpu_32(resp->flags) &
 718             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 719                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 720                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 721         }
 722
 723         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 724
 725         HWRM_UNLOCK();
 726
 727         return rc;
 728 }
 729
 730 int bnxt_hwrm_func_reset(struct bnxt *bp)
 731 {
 732         int rc = 0;
 733         struct hwrm_func_reset_input req = {.req_type = 0 };
 734         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 735
 736         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 737
 738         req.enables = rte_cpu_to_le_32(0);
 739
 740         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 741
 742         HWRM_CHECK_RESULT();
 743         HWRM_UNLOCK();
 744
 745         return rc;
 746 }
 747
 748 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 749 {
 750         int rc;
 751         uint32_t flags = 0;
 752         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 753         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 754
 755         if (bp->flags & BNXT_FLAG_REGISTERED)
 756                 return 0;
 757
 758         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 759                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 760         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 761                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 762
 763         /* PFs and trusted VFs should indicate the support of the
 764          * Master capability on non Stingray platform
 765          */
 766         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 767                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 768
 769         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 770         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 771                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 772         req.ver_maj = RTE_VER_YEAR;
 773         req.ver_min = RTE_VER_MONTH;
 774         req.ver_upd = RTE_VER_MINOR;
 775
 776         if (BNXT_PF(bp)) {
 777                 req.enables |= rte_cpu_to_le_32(
 778                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 779                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 780                        RTE_MIN(sizeof(req.vf_req_fwd),
 781                                sizeof(bp->pf.vf_req_fwd)));
 782
 783                 /*
 784                  * PF can sniff HWRM API issued by VF. This can be set up by
 785                  * linux driver and inherited by the DPDK PF driver. Clear
 786                  * this HWRM sniffer list in FW because DPDK PF driver does
 787                  * not support this.
 788                  */
 789                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 790         }
 791
 792         req.flags = rte_cpu_to_le_32(flags);
 793
 794         req.async_event_fwd[0] |=
 795                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 796                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 797                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 798                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 799                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 800         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 801                 req.async_event_fwd[0] |=
 802                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 803         req.async_event_fwd[1] |=
 804                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 805                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 806
 807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 808
 809         HWRM_CHECK_RESULT();
 810
 811         flags = rte_le_to_cpu_32(resp->flags);
 812         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 813                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 814
 815         HWRM_UNLOCK();
 816
 817         bp->flags |= BNXT_FLAG_REGISTERED;
 818
 819         return rc;
 820 }
 821
 822 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 823 {
 824         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 825                 return 0;
 826
 827         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 828 }
 829
 830 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 831 {
 832         int rc;
 833         uint32_t flags = 0;
 834         uint32_t enables;
 835         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 836         struct hwrm_func_vf_cfg_input req = {0};
 837
 838         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 839
 840         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 841                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 842                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 843                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 844                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 845
 846         if (BNXT_HAS_RING_GRPS(bp)) {
 847                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 848                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 849         }
 850
 851         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 852         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 853                                             AGG_RING_MULTIPLIER);
 854         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 855         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 856                                               bp->tx_nr_rings +
 857                                               BNXT_NUM_ASYNC_CPR(bp));
 858         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 859         if (bp->vf_resv_strategy ==
 860             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 861                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 862                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 863                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 864                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 865                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 866                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 867         } else if (bp->vf_resv_strategy ==
 868                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 869                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 870                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 871         }
 872
 873         if (test)
 874                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 875                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 876                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 877                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 878                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 879                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 880
 881         if (test && BNXT_HAS_RING_GRPS(bp))
 882                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 883
 884         req.flags = rte_cpu_to_le_32(flags);
 885         req.enables |= rte_cpu_to_le_32(enables);
 886
 887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 888
 889         if (test)
 890                 HWRM_CHECK_RESULT_SILENT();
 891         else
 892                 HWRM_CHECK_RESULT();
 893
 894         HWRM_UNLOCK();
 895         return rc;
 896 }
 897
 898 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 899 {
 900         int rc;
 901         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 902         struct hwrm_func_resource_qcaps_input req = {0};
 903
 904         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 905         req.fid = rte_cpu_to_le_16(0xffff);
 906
 907         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 908
 909         HWRM_CHECK_RESULT_SILENT();
 910
 911         if (BNXT_VF(bp)) {
 912                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 913                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 914                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 915                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 916                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 917                 /* func_resource_qcaps does not return max_rx_em_flows.
 918                  * So use the value provided by func_qcaps.
 919                  */
 920                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 921                 if (!BNXT_CHIP_THOR(bp))
 922                         bp->max_l2_ctx += bp->max_rx_em_flows;
 923                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 924                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 925         }
 926         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 927         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 928         if (bp->vf_resv_strategy >
 929             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 930                 bp->vf_resv_strategy =
 931                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 932
 933         HWRM_UNLOCK();
 934         return rc;
 935 }
 936
 937 int bnxt_hwrm_ver_get(struct bnxt *bp)
 938 {
 939         int rc = 0;
 940         struct hwrm_ver_get_input req = {.req_type = 0 };
 941         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 942         uint32_t fw_version;
 943         uint16_t max_resp_len;
 944         char type[RTE_MEMZONE_NAMESIZE];
 945         uint32_t dev_caps_cfg;
 946
 947         bp->max_req_len = HWRM_MAX_REQ_LEN;
 948         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 949
 950         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 951         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 952         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 953
 954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 955
 956         if (bp->flags & BNXT_FLAG_FW_RESET)
 957                 HWRM_CHECK_RESULT_SILENT();
 958         else
 959                 HWRM_CHECK_RESULT();
 960
 961         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 962                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 963                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 964                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 965         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 966                      (resp->hwrm_fw_min_8b << 16) |
 967                      (resp->hwrm_fw_bld_8b << 8) |
 968                      resp->hwrm_fw_rsvd_8b;
 969         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 970                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 971
 972         fw_version = resp->hwrm_intf_maj_8b << 16;
 973         fw_version |= resp->hwrm_intf_min_8b << 8;
 974         fw_version |= resp->hwrm_intf_upd_8b;
 975         bp->hwrm_spec_code = fw_version;
 976
 977         /* def_req_timeout value is in milliseconds */
 978         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 979         /* convert timeout to usec */
 980         bp->hwrm_cmd_timeout *= 1000;
 981         if (!bp->hwrm_cmd_timeout)
 982                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 983
 984         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 985                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 986                 rc = -EINVAL;
 987                 goto error;
 988         }
 989
 990         if (bp->max_req_len > resp->max_req_win_len) {
 991                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 992                 rc = -EINVAL;
 993         }
 994         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 995         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 996         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 997                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 998
 999         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1000         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1001
1002         if (bp->max_resp_len != max_resp_len) {
1003                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1004                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1005                         bp->pdev->addr.devid, bp->pdev->addr.function);
1006
1007                 rte_free(bp->hwrm_cmd_resp_addr);
1008
1009                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1010                 if (bp->hwrm_cmd_resp_addr == NULL) {
1011                         rc = -ENOMEM;
1012                         goto error;
1013                 }
1014                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1015                 bp->hwrm_cmd_resp_dma_addr =
1016                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1017                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1018                         PMD_DRV_LOG(ERR,
1019                         "Unable to map response buffer to physical memory.\n");
1020                         rc = -ENOMEM;
1021                         goto error;
1022                 }
1023                 bp->max_resp_len = max_resp_len;
1024         }
1025
1026         if ((dev_caps_cfg &
1027                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1028             (dev_caps_cfg &
1029              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1030                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1031                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1032         }
1033
1034         if (((dev_caps_cfg &
1035               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1036              (dev_caps_cfg &
1037               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1038             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1039                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1040                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1041                         bp->pdev->addr.devid, bp->pdev->addr.function);
1042
1043                 rte_free(bp->hwrm_short_cmd_req_addr);
1044
1045                 bp->hwrm_short_cmd_req_addr =
1046                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1047                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1048                         rc = -ENOMEM;
1049                         goto error;
1050                 }
1051                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1052                 bp->hwrm_short_cmd_req_dma_addr =
1053                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1054                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1055                         rte_free(bp->hwrm_short_cmd_req_addr);
1056                         PMD_DRV_LOG(ERR,
1057                                 "Unable to map buffer to physical memory.\n");
1058                         rc = -ENOMEM;
1059                         goto error;
1060                 }
1061         }
1062         if (dev_caps_cfg &
1063             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1064                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1065                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1066         }
1067         if (dev_caps_cfg &
1068             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1069                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1070         if (dev_caps_cfg &
1071             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1072                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1073                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1074         }
1075
1076 error:
1077         HWRM_UNLOCK();
1078         return rc;
1079 }
1080
1081 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1082 {
1083         int rc;
1084         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1085         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1086
1087         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1088                 return 0;
1089
1090         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1091         req.flags = flags;
1092
1093         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1094
1095         HWRM_CHECK_RESULT();
1096         HWRM_UNLOCK();
1097
1098         return rc;
1099 }
1100
1101 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1102 {
1103         int rc = 0;
1104         struct hwrm_port_phy_cfg_input req = {0};
1105         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1106         uint32_t enables = 0;
1107
1108         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1109
1110         if (conf->link_up) {
1111                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1112                 if (bp->link_info.auto_mode && conf->link_speed) {
1113                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1114                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1115                 }
1116
1117                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1118                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1119                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1120                 /*
1121                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1122                  * any auto mode, even "none".
1123                  */
1124                 if (!conf->link_speed) {
1125                         /* No speeds specified. Enable AutoNeg - all speeds */
1126                         req.auto_mode =
1127                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1128                 }
1129                 /* AutoNeg - Advertise speeds specified. */
1130                 if (conf->auto_link_speed_mask &&
1131                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1132                         req.auto_mode =
1133                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1134                         req.auto_link_speed_mask =
1135                                 conf->auto_link_speed_mask;
1136                         enables |=
1137                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1138                 }
1139
1140                 req.auto_duplex = conf->duplex;
1141                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1142                 req.auto_pause = conf->auto_pause;
1143                 req.force_pause = conf->force_pause;
1144                 /* Set force_pause if there is no auto or if there is a force */
1145                 if (req.auto_pause && !req.force_pause)
1146                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1147                 else
1148                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1149
1150                 req.enables = rte_cpu_to_le_32(enables);
1151         } else {
1152                 req.flags =
1153                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1154                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1155         }
1156
1157         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1158
1159         HWRM_CHECK_RESULT();
1160         HWRM_UNLOCK();
1161
1162         return rc;
1163 }
1164
1165 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1166                                    struct bnxt_link_info *link_info)
1167 {
1168         int rc = 0;
1169         struct hwrm_port_phy_qcfg_input req = {0};
1170         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1171
1172         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1173
1174         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1175
1176         HWRM_CHECK_RESULT();
1177
1178         link_info->phy_link_status = resp->link;
1179         link_info->link_up =
1180                 (link_info->phy_link_status ==
1181                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1182         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1183         link_info->duplex = resp->duplex_cfg;
1184         link_info->pause = resp->pause;
1185         link_info->auto_pause = resp->auto_pause;
1186         link_info->force_pause = resp->force_pause;
1187         link_info->auto_mode = resp->auto_mode;
1188         link_info->phy_type = resp->phy_type;
1189         link_info->media_type = resp->media_type;
1190
1191         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1192         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1193         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1194         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1195         link_info->phy_ver[0] = resp->phy_maj;
1196         link_info->phy_ver[1] = resp->phy_min;
1197         link_info->phy_ver[2] = resp->phy_bld;
1198
1199         HWRM_UNLOCK();
1200
1201         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1202         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1203         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1204         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1205         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1206                     link_info->auto_link_speed_mask);
1207         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1208                     link_info->force_link_speed);
1209
1210         return rc;
1211 }
1212
1213 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1214 {
1215         int rc = 0;
1216         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1217         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1218         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1219         int i;
1220
1221 get_rx_info:
1222         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1223
1224         req.flags = rte_cpu_to_le_32(dir);
1225         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1226         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1227             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1228                 req.drv_qmap_cap =
1229                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1230         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1231
1232         HWRM_CHECK_RESULT();
1233
1234         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1235                 GET_TX_QUEUE_INFO(0);
1236                 GET_TX_QUEUE_INFO(1);
1237                 GET_TX_QUEUE_INFO(2);
1238                 GET_TX_QUEUE_INFO(3);
1239                 GET_TX_QUEUE_INFO(4);
1240                 GET_TX_QUEUE_INFO(5);
1241                 GET_TX_QUEUE_INFO(6);
1242                 GET_TX_QUEUE_INFO(7);
1243         } else  {
1244                 GET_RX_QUEUE_INFO(0);
1245                 GET_RX_QUEUE_INFO(1);
1246                 GET_RX_QUEUE_INFO(2);
1247                 GET_RX_QUEUE_INFO(3);
1248                 GET_RX_QUEUE_INFO(4);
1249                 GET_RX_QUEUE_INFO(5);
1250                 GET_RX_QUEUE_INFO(6);
1251                 GET_RX_QUEUE_INFO(7);
1252         }
1253
1254         HWRM_UNLOCK();
1255
1256         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1257                 goto done;
1258
1259         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1260                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1261         } else {
1262                 int j;
1263
1264                 /* iterate and find the COSq profile to use for Tx */
1265                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1266                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1267                                 if (bp->tx_cos_queue[i].id != 0xff)
1268                                         bp->tx_cosq_id[j++] =
1269                                                 bp->tx_cos_queue[i].id;
1270                         }
1271                 } else {
1272                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1273                                 if (bp->tx_cos_queue[i].profile ==
1274                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1275                                         bp->tx_cosq_id[0] =
1276                                                 bp->tx_cos_queue[i].id;
1277                                         break;
1278                                 }
1279                         }
1280                 }
1281         }
1282
1283         bp->max_tc = resp->max_configurable_queues;
1284         bp->max_lltc = resp->max_configurable_lossless_queues;
1285         if (bp->max_tc > BNXT_MAX_QUEUE)
1286                 bp->max_tc = BNXT_MAX_QUEUE;
1287         bp->max_q = bp->max_tc;
1288
1289         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1290                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1291                 goto get_rx_info;
1292         }
1293
1294 done:
1295         return rc;
1296 }
1297
1298 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1299                          struct bnxt_ring *ring,
1300                          uint32_t ring_type, uint32_t map_index,
1301                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1302                          uint16_t tx_cosq_id)
1303 {
1304         int rc = 0;
1305         uint32_t enables = 0;
1306         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1307         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1308         struct rte_mempool *mb_pool;
1309         uint16_t rx_buf_size;
1310
1311         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1312
1313         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1314         req.fbo = rte_cpu_to_le_32(0);
1315         /* Association of ring index with doorbell index */
1316         req.logical_id = rte_cpu_to_le_16(map_index);
1317         req.length = rte_cpu_to_le_32(ring->ring_size);
1318
1319         switch (ring_type) {
1320         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1321                 req.ring_type = ring_type;
1322                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1323                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1324                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1325                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1326                         enables |=
1327                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1328                 break;
1329         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1330                 req.ring_type = ring_type;
1331                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1332                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1333                 if (BNXT_CHIP_THOR(bp)) {
1334                         mb_pool = bp->rx_queues[0]->mb_pool;
1335                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1336                                       RTE_PKTMBUF_HEADROOM;
1337                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1338                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1339                         enables |=
1340                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1341                 }
1342                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1343                         enables |=
1344                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1345                 break;
1346         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1347                 req.ring_type = ring_type;
1348                 if (BNXT_HAS_NQ(bp)) {
1349                         /* Association of cp ring with nq */
1350                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1351                         enables |=
1352                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1353                 }
1354                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1355                 break;
1356         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1357                 req.ring_type = ring_type;
1358                 req.page_size = BNXT_PAGE_SHFT;
1359                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1360                 break;
1361         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1362                 req.ring_type = ring_type;
1363                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1364
1365                 mb_pool = bp->rx_queues[0]->mb_pool;
1366                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1367                               RTE_PKTMBUF_HEADROOM;
1368                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1369                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1370
1371                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1372                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1373                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1374                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1375                 break;
1376         default:
1377                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1378                         ring_type);
1379                 HWRM_UNLOCK();
1380                 return -EINVAL;
1381         }
1382         req.enables = rte_cpu_to_le_32(enables);
1383
1384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1385
1386         if (rc || resp->error_code) {
1387                 if (rc == 0 && resp->error_code)
1388                         rc = rte_le_to_cpu_16(resp->error_code);
1389                 switch (ring_type) {
1390                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1391                         PMD_DRV_LOG(ERR,
1392                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1393                         HWRM_UNLOCK();
1394                         return rc;
1395                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1396                         PMD_DRV_LOG(ERR,
1397                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1398                         HWRM_UNLOCK();
1399                         return rc;
1400                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1401                         PMD_DRV_LOG(ERR,
1402                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1403                                     rc);
1404                         HWRM_UNLOCK();
1405                         return rc;
1406                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1407                         PMD_DRV_LOG(ERR,
1408                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1409                         HWRM_UNLOCK();
1410                         return rc;
1411                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1412                         PMD_DRV_LOG(ERR,
1413                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1414                         HWRM_UNLOCK();
1415                         return rc;
1416                 default:
1417                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1418                         HWRM_UNLOCK();
1419                         return rc;
1420                 }
1421         }
1422
1423         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1424         HWRM_UNLOCK();
1425         return rc;
1426 }
1427
1428 int bnxt_hwrm_ring_free(struct bnxt *bp,
1429                         struct bnxt_ring *ring, uint32_t ring_type)
1430 {
1431         int rc;
1432         struct hwrm_ring_free_input req = {.req_type = 0 };
1433         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1434
1435         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1436
1437         req.ring_type = ring_type;
1438         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1439
1440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1441
1442         if (rc || resp->error_code) {
1443                 if (rc == 0 && resp->error_code)
1444                         rc = rte_le_to_cpu_16(resp->error_code);
1445                 HWRM_UNLOCK();
1446
1447                 switch (ring_type) {
1448                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1449                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1450                                 rc);
1451                         return rc;
1452                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1453                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1454                                 rc);
1455                         return rc;
1456                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1457                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1458                                 rc);
1459                         return rc;
1460                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1461                         PMD_DRV_LOG(ERR,
1462                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1463                         return rc;
1464                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1465                         PMD_DRV_LOG(ERR,
1466                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1467                         return rc;
1468                 default:
1469                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1470                         return rc;
1471                 }
1472         }
1473         HWRM_UNLOCK();
1474         return 0;
1475 }
1476
1477 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1478 {
1479         int rc = 0;
1480         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1481         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1482
1483         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1484
1485         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1486         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1487         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1488         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1489
1490         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1491
1492         HWRM_CHECK_RESULT();
1493
1494         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1495
1496         HWRM_UNLOCK();
1497
1498         return rc;
1499 }
1500
1501 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1502 {
1503         int rc;
1504         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1505         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1506
1507         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1508
1509         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1510
1511         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1512
1513         HWRM_CHECK_RESULT();
1514         HWRM_UNLOCK();
1515
1516         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1517         return rc;
1518 }
1519
1520 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1521 {
1522         int rc = 0;
1523         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1524         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1525
1526         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1527                 return rc;
1528
1529         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1530
1531         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1532
1533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1534
1535         HWRM_CHECK_RESULT();
1536         HWRM_UNLOCK();
1537
1538         return rc;
1539 }
1540
1541 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1542                                 unsigned int idx __rte_unused)
1543 {
1544         int rc;
1545         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1546         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1547
1548         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1549
1550         req.update_period_ms = rte_cpu_to_le_32(0);
1551
1552         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1553
1554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1555
1556         HWRM_CHECK_RESULT();
1557
1558         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1559
1560         HWRM_UNLOCK();
1561
1562         return rc;
1563 }
1564
1565 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1566                                 unsigned int idx __rte_unused)
1567 {
1568         int rc;
1569         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1570         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1571
1572         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1573
1574         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1575
1576         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1577
1578         HWRM_CHECK_RESULT();
1579         HWRM_UNLOCK();
1580
1581         return rc;
1582 }
1583
1584 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1585 {
1586         int rc = 0, i, j;
1587         struct hwrm_vnic_alloc_input req = { 0 };
1588         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1589
1590         if (!BNXT_HAS_RING_GRPS(bp))
1591                 goto skip_ring_grps;
1592
1593         /* map ring groups to this vnic */
1594         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1595                 vnic->start_grp_id, vnic->end_grp_id);
1596         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1597                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1598
1599         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1600         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1601         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1602         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1603
1604 skip_ring_grps:
1605         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1606         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1607
1608         if (vnic->func_default)
1609                 req.flags =
1610                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1612
1613         HWRM_CHECK_RESULT();
1614
1615         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1616         HWRM_UNLOCK();
1617         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1618         return rc;
1619 }
1620
1621 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1622                                         struct bnxt_vnic_info *vnic,
1623                                         struct bnxt_plcmodes_cfg *pmode)
1624 {
1625         int rc = 0;
1626         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1627         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1628
1629         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1630
1631         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1632
1633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1634
1635         HWRM_CHECK_RESULT();
1636
1637         pmode->flags = rte_le_to_cpu_32(resp->flags);
1638         /* dflt_vnic bit doesn't exist in the _cfg command */
1639         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1640         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1641         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1642         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1643
1644         HWRM_UNLOCK();
1645
1646         return rc;
1647 }
1648
1649 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1650                                        struct bnxt_vnic_info *vnic,
1651                                        struct bnxt_plcmodes_cfg *pmode)
1652 {
1653         int rc = 0;
1654         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1655         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1656
1657         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1658                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1659                 return rc;
1660         }
1661
1662         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1663
1664         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1665         req.flags = rte_cpu_to_le_32(pmode->flags);
1666         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1667         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1668         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1669         req.enables = rte_cpu_to_le_32(
1670             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1671             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1672             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1673         );
1674
1675         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1676
1677         HWRM_CHECK_RESULT();
1678         HWRM_UNLOCK();
1679
1680         return rc;
1681 }
1682
1683 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1684 {
1685         int rc = 0;
1686         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1687         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1688         struct bnxt_plcmodes_cfg pmodes = { 0 };
1689         uint32_t ctx_enable_flag = 0;
1690         uint32_t enables = 0;
1691
1692         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1693                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1694                 return rc;
1695         }
1696
1697         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1698         if (rc)
1699                 return rc;
1700
1701         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1702
1703         if (BNXT_CHIP_THOR(bp)) {
1704                 int dflt_rxq = vnic->start_grp_id;
1705                 struct bnxt_rx_ring_info *rxr;
1706                 struct bnxt_cp_ring_info *cpr;
1707                 struct bnxt_rx_queue *rxq;
1708                 int i;
1709
1710                 /*
1711                  * The first active receive ring is used as the VNIC
1712                  * default receive ring. If there are no active receive
1713                  * rings (all corresponding receive queues are stopped),
1714                  * the first receive ring is used.
1715                  */
1716                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1717                         rxq = bp->eth_dev->data->rx_queues[i];
1718                         if (rxq->rx_started) {
1719                                 dflt_rxq = i;
1720                                 break;
1721                         }
1722                 }
1723
1724                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1725                 rxr = rxq->rx_ring;
1726                 cpr = rxq->cp_ring;
1727
1728                 req.default_rx_ring_id =
1729                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1730                 req.default_cmpl_ring_id =
1731                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1732                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1733                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1734                 goto config_mru;
1735         }
1736
1737         /* Only RSS support for now TBD: COS & LB */
1738         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1739         if (vnic->lb_rule != 0xffff)
1740                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1741         if (vnic->cos_rule != 0xffff)
1742                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1743         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1744                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1745                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1746         }
1747         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1748                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1749                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1750         }
1751
1752         enables |= ctx_enable_flag;
1753         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1754         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1755         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1756         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1757
1758 config_mru:
1759         req.enables = rte_cpu_to_le_32(enables);
1760         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1761         req.mru = rte_cpu_to_le_16(vnic->mru);
1762         /* Configure default VNIC only once. */
1763         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1764                 req.flags |=
1765                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1766                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1767         }
1768         if (vnic->vlan_strip)
1769                 req.flags |=
1770                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1771         if (vnic->bd_stall)
1772                 req.flags |=
1773                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1774         if (vnic->roce_dual)
1775                 req.flags |= rte_cpu_to_le_32(
1776                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1777         if (vnic->roce_only)
1778                 req.flags |= rte_cpu_to_le_32(
1779                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1780         if (vnic->rss_dflt_cr)
1781                 req.flags |= rte_cpu_to_le_32(
1782                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1783
1784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1785
1786         HWRM_CHECK_RESULT();
1787         HWRM_UNLOCK();
1788
1789         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1790
1791         return rc;
1792 }
1793
1794 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1795                 int16_t fw_vf_id)
1796 {
1797         int rc = 0;
1798         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1799         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1800
1801         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1802                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1803                 return rc;
1804         }
1805         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1806
1807         req.enables =
1808                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1809         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1810         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1811
1812         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1813
1814         HWRM_CHECK_RESULT();
1815
1816         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1817         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1818         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1819         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1820         vnic->mru = rte_le_to_cpu_16(resp->mru);
1821         vnic->func_default = rte_le_to_cpu_32(
1822                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1823         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1824                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1825         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1826                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1827         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1828                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1829         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1830                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1831         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1832                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1833
1834         HWRM_UNLOCK();
1835
1836         return rc;
1837 }
1838
1839 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1840                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1841 {
1842         int rc = 0;
1843         uint16_t ctx_id;
1844         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1845         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1846                                                 bp->hwrm_cmd_resp_addr;
1847
1848         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1849
1850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1851         HWRM_CHECK_RESULT();
1852
1853         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1854         if (!BNXT_HAS_RING_GRPS(bp))
1855                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1856         else if (ctx_idx == 0)
1857                 vnic->rss_rule = ctx_id;
1858
1859         HWRM_UNLOCK();
1860
1861         return rc;
1862 }
1863
1864 static
1865 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1866                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1867 {
1868         int rc = 0;
1869         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1870         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1871                                                 bp->hwrm_cmd_resp_addr;
1872
1873         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1874                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1875                 return rc;
1876         }
1877         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1878
1879         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1880
1881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1882
1883         HWRM_CHECK_RESULT();
1884         HWRM_UNLOCK();
1885
1886         return rc;
1887 }
1888
1889 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1890 {
1891         int rc = 0;
1892
1893         if (BNXT_CHIP_THOR(bp)) {
1894                 int j;
1895
1896                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1897                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1898                                                       vnic,
1899                                                       vnic->fw_grp_ids[j]);
1900                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1901                 }
1902                 vnic->num_lb_ctxts = 0;
1903         } else {
1904                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1905                 vnic->rss_rule = INVALID_HW_RING_ID;
1906         }
1907
1908         return rc;
1909 }
1910
1911 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1912 {
1913         int rc = 0;
1914         struct hwrm_vnic_free_input req = {.req_type = 0 };
1915         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1916
1917         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1918                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1919                 return rc;
1920         }
1921
1922         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1923
1924         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1925
1926         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1927
1928         HWRM_CHECK_RESULT();
1929         HWRM_UNLOCK();
1930
1931         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1932         /* Configure default VNIC again if necessary. */
1933         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1934                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1935
1936         return rc;
1937 }
1938
1939 static int
1940 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1941 {
1942         int i;
1943         int rc = 0;
1944         int nr_ctxs = vnic->num_lb_ctxts;
1945         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1946         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1947
1948         for (i = 0; i < nr_ctxs; i++) {
1949                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1950
1951                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1952                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1953                 req.hash_mode_flags = vnic->hash_mode;
1954
1955                 req.hash_key_tbl_addr =
1956                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1957
1958                 req.ring_grp_tbl_addr =
1959                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1960                                          i * HW_HASH_INDEX_SIZE);
1961                 req.ring_table_pair_index = i;
1962                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1963
1964                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1965                                             BNXT_USE_CHIMP_MB);
1966
1967                 HWRM_CHECK_RESULT();
1968                 HWRM_UNLOCK();
1969         }
1970
1971         return rc;
1972 }
1973
1974 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1975                            struct bnxt_vnic_info *vnic)
1976 {
1977         int rc = 0;
1978         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1979         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1980
1981         if (!vnic->rss_table)
1982                 return 0;
1983
1984         if (BNXT_CHIP_THOR(bp))
1985                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1986
1987         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1988
1989         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1990         req.hash_mode_flags = vnic->hash_mode;
1991
1992         req.ring_grp_tbl_addr =
1993             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1994         req.hash_key_tbl_addr =
1995             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1996         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1997         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1998
1999         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2000
2001         HWRM_CHECK_RESULT();
2002         HWRM_UNLOCK();
2003
2004         return rc;
2005 }
2006
2007 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2008                         struct bnxt_vnic_info *vnic)
2009 {
2010         int rc = 0;
2011         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2012         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2013         uint16_t size;
2014
2015         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2016                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2017                 return rc;
2018         }
2019
2020         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2021
2022         req.flags = rte_cpu_to_le_32(
2023                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2024
2025         req.enables = rte_cpu_to_le_32(
2026                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2027
2028         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2029         size -= RTE_PKTMBUF_HEADROOM;
2030         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2031
2032         req.jumbo_thresh = rte_cpu_to_le_16(size);
2033         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2034
2035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2036
2037         HWRM_CHECK_RESULT();
2038         HWRM_UNLOCK();
2039
2040         return rc;
2041 }
2042
2043 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2044                         struct bnxt_vnic_info *vnic, bool enable)
2045 {
2046         int rc = 0;
2047         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2048         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2049
2050         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2051                 if (enable)
2052                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2053                 return -ENOTSUP;
2054         }
2055
2056         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2057                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2058                 return 0;
2059         }
2060
2061         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2062
2063         if (enable) {
2064                 req.enables = rte_cpu_to_le_32(
2065                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2066                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2067                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2068                 req.flags = rte_cpu_to_le_32(
2069                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2070                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2071                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2072                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2073                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2074                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2075                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2076                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2077                 req.min_agg_len = rte_cpu_to_le_32(512);
2078         }
2079         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2080
2081         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2082
2083         HWRM_CHECK_RESULT();
2084         HWRM_UNLOCK();
2085
2086         return rc;
2087 }
2088
2089 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2090 {
2091         struct hwrm_func_cfg_input req = {0};
2092         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2093         int rc;
2094
2095         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2096         req.enables = rte_cpu_to_le_32(
2097                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2098         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2099         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2100
2101         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2102
2103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2104         HWRM_CHECK_RESULT();
2105         HWRM_UNLOCK();
2106
2107         bp->pf.vf_info[vf].random_mac = false;
2108
2109         return rc;
2110 }
2111
2112 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2113                                   uint64_t *dropped)
2114 {
2115         int rc = 0;
2116         struct hwrm_func_qstats_input req = {.req_type = 0};
2117         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2118
2119         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2120
2121         req.fid = rte_cpu_to_le_16(fid);
2122
2123         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2124
2125         HWRM_CHECK_RESULT();
2126
2127         if (dropped)
2128                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2129
2130         HWRM_UNLOCK();
2131
2132         return rc;
2133 }
2134
2135 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2136                           struct rte_eth_stats *stats)
2137 {
2138         int rc = 0;
2139         struct hwrm_func_qstats_input req = {.req_type = 0};
2140         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2141
2142         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2143
2144         req.fid = rte_cpu_to_le_16(fid);
2145
2146         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2147
2148         HWRM_CHECK_RESULT();
2149
2150         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2151         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2152         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2153         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2154         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2155         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2156
2157         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2158         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2159         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2160         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2161         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2162         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2163
2164         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2165         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2166         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2167
2168         HWRM_UNLOCK();
2169
2170         return rc;
2171 }
2172
2173 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2174 {
2175         int rc = 0;
2176         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2177         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2178
2179         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2180
2181         req.fid = rte_cpu_to_le_16(fid);
2182
2183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2184
2185         HWRM_CHECK_RESULT();
2186         HWRM_UNLOCK();
2187
2188         return rc;
2189 }
2190
2191 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2192 {
2193         unsigned int i;
2194         int rc = 0;
2195
2196         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2197                 struct bnxt_tx_queue *txq;
2198                 struct bnxt_rx_queue *rxq;
2199                 struct bnxt_cp_ring_info *cpr;
2200
2201                 if (i >= bp->rx_cp_nr_rings) {
2202                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2203                         cpr = txq->cp_ring;
2204                 } else {
2205                         rxq = bp->rx_queues[i];
2206                         cpr = rxq->cp_ring;
2207                 }
2208
2209                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2210                 if (rc)
2211                         return rc;
2212         }
2213         return 0;
2214 }
2215
2216 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2217 {
2218         int rc;
2219         unsigned int i;
2220         struct bnxt_cp_ring_info *cpr;
2221
2222         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2223
2224                 if (i >= bp->rx_cp_nr_rings) {
2225                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2226                 } else {
2227                         cpr = bp->rx_queues[i]->cp_ring;
2228                         if (BNXT_HAS_RING_GRPS(bp))
2229                                 bp->grp_info[i].fw_stats_ctx = -1;
2230                 }
2231                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2232                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2233                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2234                         if (rc)
2235                                 return rc;
2236                 }
2237         }
2238         return 0;
2239 }
2240
2241 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2242 {
2243         unsigned int i;
2244         int rc = 0;
2245
2246         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2247                 struct bnxt_tx_queue *txq;
2248                 struct bnxt_rx_queue *rxq;
2249                 struct bnxt_cp_ring_info *cpr;
2250
2251                 if (i >= bp->rx_cp_nr_rings) {
2252                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2253                         cpr = txq->cp_ring;
2254                 } else {
2255                         rxq = bp->rx_queues[i];
2256                         cpr = rxq->cp_ring;
2257                 }
2258
2259                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2260
2261                 if (rc)
2262                         return rc;
2263         }
2264         return rc;
2265 }
2266
2267 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2268 {
2269         uint16_t idx;
2270         uint32_t rc = 0;
2271
2272         if (!BNXT_HAS_RING_GRPS(bp))
2273                 return 0;
2274
2275         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2276
2277                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2278                         continue;
2279
2280                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2281
2282                 if (rc)
2283                         return rc;
2284         }
2285         return rc;
2286 }
2287
2288 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2289 {
2290         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2291
2292         bnxt_hwrm_ring_free(bp, cp_ring,
2293                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2294         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2295         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2296                                      sizeof(*cpr->cp_desc_ring));
2297         cpr->cp_raw_cons = 0;
2298         cpr->valid = 0;
2299 }
2300
2301 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2302 {
2303         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2304
2305         bnxt_hwrm_ring_free(bp, cp_ring,
2306                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2307         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2308         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2309                         sizeof(*cpr->cp_desc_ring));
2310         cpr->cp_raw_cons = 0;
2311         cpr->valid = 0;
2312 }
2313
2314 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2315 {
2316         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2317         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2318         struct bnxt_ring *ring = rxr->rx_ring_struct;
2319         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2320
2321         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2322                 bnxt_hwrm_ring_free(bp, ring,
2323                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2324                 ring->fw_ring_id = INVALID_HW_RING_ID;
2325                 if (BNXT_HAS_RING_GRPS(bp))
2326                         bp->grp_info[queue_index].rx_fw_ring_id =
2327                                                         INVALID_HW_RING_ID;
2328                 memset(rxr->rx_desc_ring, 0,
2329                        rxr->rx_ring_struct->ring_size *
2330                        sizeof(*rxr->rx_desc_ring));
2331                 memset(rxr->rx_buf_ring, 0,
2332                        rxr->rx_ring_struct->ring_size *
2333                        sizeof(*rxr->rx_buf_ring));
2334                 rxr->rx_prod = 0;
2335         }
2336         ring = rxr->ag_ring_struct;
2337         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2338                 bnxt_hwrm_ring_free(bp, ring,
2339                                     BNXT_CHIP_THOR(bp) ?
2340                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2341                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2342                 ring->fw_ring_id = INVALID_HW_RING_ID;
2343                 memset(rxr->ag_buf_ring, 0,
2344                        rxr->ag_ring_struct->ring_size *
2345                        sizeof(*rxr->ag_buf_ring));
2346                 rxr->ag_prod = 0;
2347                 if (BNXT_HAS_RING_GRPS(bp))
2348                         bp->grp_info[queue_index].ag_fw_ring_id =
2349                                                         INVALID_HW_RING_ID;
2350         }
2351         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2352                 bnxt_free_cp_ring(bp, cpr);
2353
2354         if (BNXT_HAS_RING_GRPS(bp))
2355                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2356 }
2357
2358 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2359 {
2360         unsigned int i;
2361
2362         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2363                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2364                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2365                 struct bnxt_ring *ring = txr->tx_ring_struct;
2366                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2367
2368                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2369                         bnxt_hwrm_ring_free(bp, ring,
2370                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2371                         ring->fw_ring_id = INVALID_HW_RING_ID;
2372                         memset(txr->tx_desc_ring, 0,
2373                                         txr->tx_ring_struct->ring_size *
2374                                         sizeof(*txr->tx_desc_ring));
2375                         memset(txr->tx_buf_ring, 0,
2376                                         txr->tx_ring_struct->ring_size *
2377                                         sizeof(*txr->tx_buf_ring));
2378                         txr->tx_prod = 0;
2379                         txr->tx_cons = 0;
2380                 }
2381                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2382                         bnxt_free_cp_ring(bp, cpr);
2383                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2384                 }
2385         }
2386
2387         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2388                 bnxt_free_hwrm_rx_ring(bp, i);
2389
2390         return 0;
2391 }
2392
2393 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2394 {
2395         uint16_t i;
2396         uint32_t rc = 0;
2397
2398         if (!BNXT_HAS_RING_GRPS(bp))
2399                 return 0;
2400
2401         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2402                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2403                 if (rc)
2404                         return rc;
2405         }
2406         return rc;
2407 }
2408
2409 /*
2410  * HWRM utility functions
2411  */
2412
2413 void bnxt_free_hwrm_resources(struct bnxt *bp)
2414 {
2415         /* Release memzone */
2416         rte_free(bp->hwrm_cmd_resp_addr);
2417         rte_free(bp->hwrm_short_cmd_req_addr);
2418         bp->hwrm_cmd_resp_addr = NULL;
2419         bp->hwrm_short_cmd_req_addr = NULL;
2420         bp->hwrm_cmd_resp_dma_addr = 0;
2421         bp->hwrm_short_cmd_req_dma_addr = 0;
2422 }
2423
2424 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2425 {
2426         struct rte_pci_device *pdev = bp->pdev;
2427         char type[RTE_MEMZONE_NAMESIZE];
2428
2429         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2430                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2431         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2432         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2433         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2434         if (bp->hwrm_cmd_resp_addr == NULL)
2435                 return -ENOMEM;
2436         bp->hwrm_cmd_resp_dma_addr =
2437                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2438         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2439                 PMD_DRV_LOG(ERR,
2440                         "unable to map response address to physical memory\n");
2441                 return -ENOMEM;
2442         }
2443         rte_spinlock_init(&bp->hwrm_lock);
2444
2445         return 0;
2446 }
2447
2448 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2449 {
2450         struct bnxt_filter_info *filter;
2451         int rc = 0;
2452
2453         STAILQ_FOREACH(filter, &vnic->filter, next) {
2454                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2455                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2456                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2457                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2458                 else
2459                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2460                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2461                 bnxt_free_filter(bp, filter);
2462         }
2463         return rc;
2464 }
2465
2466 static int
2467 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2468 {
2469         struct bnxt_filter_info *filter;
2470         struct rte_flow *flow;
2471         int rc = 0;
2472
2473         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2474                 flow = STAILQ_FIRST(&vnic->flow_list);
2475                 filter = flow->filter;
2476                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2477                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2478                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2479                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2480                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2481                 else
2482                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2483
2484                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2485                 rte_free(flow);
2486         }
2487         return rc;
2488 }
2489
2490 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2491 {
2492         struct bnxt_filter_info *filter;
2493         int rc = 0;
2494
2495         STAILQ_FOREACH(filter, &vnic->filter, next) {
2496                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2497                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2498                                                      filter);
2499                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2500                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2501                                                          filter);
2502                 else
2503                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2504                                                      filter);
2505                 if (rc)
2506                         break;
2507         }
2508         return rc;
2509 }
2510
2511 void bnxt_free_tunnel_ports(struct bnxt *bp)
2512 {
2513         if (bp->vxlan_port_cnt)
2514                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2515                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2516         bp->vxlan_port = 0;
2517         if (bp->geneve_port_cnt)
2518                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2519                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2520         bp->geneve_port = 0;
2521 }
2522
2523 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2524 {
2525         int i;
2526
2527         if (bp->vnic_info == NULL)
2528                 return;
2529
2530         /*
2531          * Cleanup VNICs in reverse order, to make sure the L2 filter
2532          * from vnic0 is last to be cleaned up.
2533          */
2534         for (i = bp->max_vnics - 1; i >= 0; i--) {
2535                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2536
2537                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2538                         continue;
2539
2540                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2541
2542                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2543
2544                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2545
2546                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2547
2548                 bnxt_hwrm_vnic_free(bp, vnic);
2549
2550                 rte_free(vnic->fw_grp_ids);
2551         }
2552         /* Ring resources */
2553         bnxt_free_all_hwrm_rings(bp);
2554         bnxt_free_all_hwrm_ring_grps(bp);
2555         bnxt_free_all_hwrm_stat_ctxs(bp);
2556         bnxt_free_tunnel_ports(bp);
2557 }
2558
2559 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2560 {
2561         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2562
2563         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2564                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2565
2566         switch (conf_link_speed) {
2567         case ETH_LINK_SPEED_10M_HD:
2568         case ETH_LINK_SPEED_100M_HD:
2569                 /* FALLTHROUGH */
2570                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2571         }
2572         return hw_link_duplex;
2573 }
2574
2575 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2576 {
2577         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2578 }
2579
2580 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2581 {
2582         uint16_t eth_link_speed = 0;
2583
2584         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2585                 return ETH_LINK_SPEED_AUTONEG;
2586
2587         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2588         case ETH_LINK_SPEED_100M:
2589         case ETH_LINK_SPEED_100M_HD:
2590                 /* FALLTHROUGH */
2591                 eth_link_speed =
2592                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2593                 break;
2594         case ETH_LINK_SPEED_1G:
2595                 eth_link_speed =
2596                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2597                 break;
2598         case ETH_LINK_SPEED_2_5G:
2599                 eth_link_speed =
2600                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2601                 break;
2602         case ETH_LINK_SPEED_10G:
2603                 eth_link_speed =
2604                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2605                 break;
2606         case ETH_LINK_SPEED_20G:
2607                 eth_link_speed =
2608                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2609                 break;
2610         case ETH_LINK_SPEED_25G:
2611                 eth_link_speed =
2612                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2613                 break;
2614         case ETH_LINK_SPEED_40G:
2615                 eth_link_speed =
2616                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2617                 break;
2618         case ETH_LINK_SPEED_50G:
2619                 eth_link_speed =
2620                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2621                 break;
2622         case ETH_LINK_SPEED_100G:
2623                 eth_link_speed =
2624                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2625                 break;
2626         default:
2627                 PMD_DRV_LOG(ERR,
2628                         "Unsupported link speed %d; default to AUTO\n",
2629                         conf_link_speed);
2630                 break;
2631         }
2632         return eth_link_speed;
2633 }
2634
2635 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2636                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2637                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2638                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2639
2640 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2641 {
2642         uint32_t one_speed;
2643
2644         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2645                 return 0;
2646
2647         if (link_speed & ETH_LINK_SPEED_FIXED) {
2648                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2649
2650                 if (one_speed & (one_speed - 1)) {
2651                         PMD_DRV_LOG(ERR,
2652                                 "Invalid advertised speeds (%u) for port %u\n",
2653                                 link_speed, port_id);
2654                         return -EINVAL;
2655                 }
2656                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2657                         PMD_DRV_LOG(ERR,
2658                                 "Unsupported advertised speed (%u) for port %u\n",
2659                                 link_speed, port_id);
2660                         return -EINVAL;
2661                 }
2662         } else {
2663                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2664                         PMD_DRV_LOG(ERR,
2665                                 "Unsupported advertised speeds (%u) for port %u\n",
2666                                 link_speed, port_id);
2667                         return -EINVAL;
2668                 }
2669         }
2670         return 0;
2671 }
2672
2673 static uint16_t
2674 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2675 {
2676         uint16_t ret = 0;
2677
2678         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2679                 if (bp->link_info.support_speeds)
2680                         return bp->link_info.support_speeds;
2681                 link_speed = BNXT_SUPPORTED_SPEEDS;
2682         }
2683
2684         if (link_speed & ETH_LINK_SPEED_100M)
2685                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2686         if (link_speed & ETH_LINK_SPEED_100M_HD)
2687                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2688         if (link_speed & ETH_LINK_SPEED_1G)
2689                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2690         if (link_speed & ETH_LINK_SPEED_2_5G)
2691                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2692         if (link_speed & ETH_LINK_SPEED_10G)
2693                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2694         if (link_speed & ETH_LINK_SPEED_20G)
2695                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2696         if (link_speed & ETH_LINK_SPEED_25G)
2697                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2698         if (link_speed & ETH_LINK_SPEED_40G)
2699                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2700         if (link_speed & ETH_LINK_SPEED_50G)
2701                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2702         if (link_speed & ETH_LINK_SPEED_100G)
2703                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2704         return ret;
2705 }
2706
2707 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2708 {
2709         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2710
2711         switch (hw_link_speed) {
2712         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2713                 eth_link_speed = ETH_SPEED_NUM_100M;
2714                 break;
2715         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2716                 eth_link_speed = ETH_SPEED_NUM_1G;
2717                 break;
2718         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2719                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2720                 break;
2721         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2722                 eth_link_speed = ETH_SPEED_NUM_10G;
2723                 break;
2724         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2725                 eth_link_speed = ETH_SPEED_NUM_20G;
2726                 break;
2727         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2728                 eth_link_speed = ETH_SPEED_NUM_25G;
2729                 break;
2730         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2731                 eth_link_speed = ETH_SPEED_NUM_40G;
2732                 break;
2733         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2734                 eth_link_speed = ETH_SPEED_NUM_50G;
2735                 break;
2736         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2737                 eth_link_speed = ETH_SPEED_NUM_100G;
2738                 break;
2739         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2740         default:
2741                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2742                         hw_link_speed);
2743                 break;
2744         }
2745         return eth_link_speed;
2746 }
2747
2748 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2749 {
2750         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2751
2752         switch (hw_link_duplex) {
2753         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2754         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2755                 /* FALLTHROUGH */
2756                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2757                 break;
2758         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2759                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2760                 break;
2761         default:
2762                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2763                         hw_link_duplex);
2764                 break;
2765         }
2766         return eth_link_duplex;
2767 }
2768
2769 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2770 {
2771         int rc = 0;
2772         struct bnxt_link_info *link_info = &bp->link_info;
2773
2774         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2775         if (rc) {
2776                 PMD_DRV_LOG(ERR,
2777                         "Get link config failed with rc %d\n", rc);
2778                 goto exit;
2779         }
2780         if (link_info->link_speed)
2781                 link->link_speed =
2782                         bnxt_parse_hw_link_speed(link_info->link_speed);
2783         else
2784                 link->link_speed = ETH_SPEED_NUM_NONE;
2785         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2786         link->link_status = link_info->link_up;
2787         link->link_autoneg = link_info->auto_mode ==
2788                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2789                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2790 exit:
2791         return rc;
2792 }
2793
2794 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2795 {
2796         int rc = 0;
2797         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2798         struct bnxt_link_info link_req;
2799         uint16_t speed, autoneg;
2800
2801         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2802                 return 0;
2803
2804         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2805                         bp->eth_dev->data->port_id);
2806         if (rc)
2807                 goto error;
2808
2809         memset(&link_req, 0, sizeof(link_req));
2810         link_req.link_up = link_up;
2811         if (!link_up)
2812                 goto port_phy_cfg;
2813
2814         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2815         if (BNXT_CHIP_THOR(bp) &&
2816             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2817                 /* 40G is not supported as part of media auto detect.
2818                  * The speed should be forced and autoneg disabled
2819                  * to configure 40G speed.
2820                  */
2821                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2822                 autoneg = 0;
2823         }
2824
2825         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2826         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2827         /* Autoneg can be done only when the FW allows.
2828          * When user configures fixed speed of 40G and later changes to
2829          * any other speed, auto_link_speed/force_link_speed is still set
2830          * to 40G until link comes up at new speed.
2831          */
2832         if (autoneg == 1 &&
2833             !(!BNXT_CHIP_THOR(bp) &&
2834               (bp->link_info.auto_link_speed ||
2835                bp->link_info.force_link_speed))) {
2836                 link_req.phy_flags |=
2837                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2838                 link_req.auto_link_speed_mask =
2839                         bnxt_parse_eth_link_speed_mask(bp,
2840                                                        dev_conf->link_speeds);
2841         } else {
2842                 if (bp->link_info.phy_type ==
2843                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2844                     bp->link_info.phy_type ==
2845                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2846                     bp->link_info.media_type ==
2847                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2848                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2849                         return -EINVAL;
2850                 }
2851
2852                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2853                 /* If user wants a particular speed try that first. */
2854                 if (speed)
2855                         link_req.link_speed = speed;
2856                 else if (bp->link_info.force_link_speed)
2857                         link_req.link_speed = bp->link_info.force_link_speed;
2858                 else
2859                         link_req.link_speed = bp->link_info.auto_link_speed;
2860         }
2861         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2862         link_req.auto_pause = bp->link_info.auto_pause;
2863         link_req.force_pause = bp->link_info.force_pause;
2864
2865 port_phy_cfg:
2866         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2867         if (rc) {
2868                 PMD_DRV_LOG(ERR,
2869                         "Set link config failed with rc %d\n", rc);
2870         }
2871
2872 error:
2873         return rc;
2874 }
2875
2876 /* JIRA 22088 */
2877 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2878 {
2879         struct hwrm_func_qcfg_input req = {0};
2880         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2881         uint16_t flags;
2882         int rc = 0;
2883
2884         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2885         req.fid = rte_cpu_to_le_16(0xffff);
2886
2887         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2888
2889         HWRM_CHECK_RESULT();
2890
2891         /* Hard Coded.. 0xfff VLAN ID mask */
2892         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2893         flags = rte_le_to_cpu_16(resp->flags);
2894         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2895                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2896
2897         if (BNXT_VF(bp) &&
2898             !BNXT_VF_IS_TRUSTED(bp) &&
2899             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2900                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2901                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2902         } else if (BNXT_VF(bp) &&
2903                    BNXT_VF_IS_TRUSTED(bp) &&
2904                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2905                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2906                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2907         }
2908
2909         if (mtu)
2910                 *mtu = rte_le_to_cpu_16(resp->mtu);
2911
2912         switch (resp->port_partition_type) {
2913         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2914         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2915         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2916                 /* FALLTHROUGH */
2917                 bp->port_partition_type = resp->port_partition_type;
2918                 break;
2919         default:
2920                 bp->port_partition_type = 0;
2921                 break;
2922         }
2923
2924         HWRM_UNLOCK();
2925
2926         return rc;
2927 }
2928
2929 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2930                                    struct hwrm_func_qcaps_output *qcaps)
2931 {
2932         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2933         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2934                sizeof(qcaps->mac_address));
2935         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2936         qcaps->max_rx_rings = fcfg->num_rx_rings;
2937         qcaps->max_tx_rings = fcfg->num_tx_rings;
2938         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2939         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2940         qcaps->max_vfs = 0;
2941         qcaps->first_vf_id = 0;
2942         qcaps->max_vnics = fcfg->num_vnics;
2943         qcaps->max_decap_records = 0;
2944         qcaps->max_encap_records = 0;
2945         qcaps->max_tx_wm_flows = 0;
2946         qcaps->max_tx_em_flows = 0;
2947         qcaps->max_rx_wm_flows = 0;
2948         qcaps->max_rx_em_flows = 0;
2949         qcaps->max_flow_id = 0;
2950         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2951         qcaps->max_sp_tx_rings = 0;
2952         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2953 }
2954
2955 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2956 {
2957         struct hwrm_func_cfg_input req = {0};
2958         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2959         uint32_t enables;
2960         int rc;
2961
2962         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2963                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2964                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2965                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2966                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2967                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2968                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2969                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2970                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2971
2972         if (BNXT_HAS_RING_GRPS(bp)) {
2973                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2974                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2975         } else if (BNXT_HAS_NQ(bp)) {
2976                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2977                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2978         }
2979
2980         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2981         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2982         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
2983         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2984         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2985         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2986         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2987         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2988         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2989         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2990         req.fid = rte_cpu_to_le_16(0xffff);
2991         req.enables = rte_cpu_to_le_32(enables);
2992
2993         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2994
2995         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2996
2997         HWRM_CHECK_RESULT();
2998         HWRM_UNLOCK();
2999
3000         return rc;
3001 }
3002
3003 static void populate_vf_func_cfg_req(struct bnxt *bp,
3004                                      struct hwrm_func_cfg_input *req,
3005                                      int num_vfs)
3006 {
3007         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3008                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3009                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3010                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3011                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3012                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3013                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3014                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3015                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3016                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3017
3018         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3019                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3020                                     BNXT_NUM_VLANS);
3021         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3022         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3023                                                 (num_vfs + 1));
3024         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3025         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3026                                                (num_vfs + 1));
3027         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3028         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3029         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3030         /* TODO: For now, do not support VMDq/RFS on VFs. */
3031         req->num_vnics = rte_cpu_to_le_16(1);
3032         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3033                                                  (num_vfs + 1));
3034 }
3035
3036 static void add_random_mac_if_needed(struct bnxt *bp,
3037                                      struct hwrm_func_cfg_input *cfg_req,
3038                                      int vf)
3039 {
3040         struct rte_ether_addr mac;
3041
3042         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3043                 return;
3044
3045         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3046                 cfg_req->enables |=
3047                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3048                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3049                 bp->pf.vf_info[vf].random_mac = true;
3050         } else {
3051                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3052                         RTE_ETHER_ADDR_LEN);
3053         }
3054 }
3055
3056 static void reserve_resources_from_vf(struct bnxt *bp,
3057                                       struct hwrm_func_cfg_input *cfg_req,
3058                                       int vf)
3059 {
3060         struct hwrm_func_qcaps_input req = {0};
3061         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3062         int rc;
3063
3064         /* Get the actual allocated values now */
3065         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3066         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3067         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3068
3069         if (rc) {
3070                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3071                 copy_func_cfg_to_qcaps(cfg_req, resp);
3072         } else if (resp->error_code) {
3073                 rc = rte_le_to_cpu_16(resp->error_code);
3074                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3075                 copy_func_cfg_to_qcaps(cfg_req, resp);
3076         }
3077
3078         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3079         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3080         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3081         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3082         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3083         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3084         /*
3085          * TODO: While not supporting VMDq with VFs, max_vnics is always
3086          * forced to 1 in this case
3087          */
3088         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3089         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3090
3091         HWRM_UNLOCK();
3092 }
3093
3094 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3095 {
3096         struct hwrm_func_qcfg_input req = {0};
3097         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3098         int rc;
3099
3100         /* Check for zero MAC address */
3101         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3102         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3103         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3104         HWRM_CHECK_RESULT();
3105         rc = rte_le_to_cpu_16(resp->vlan);
3106
3107         HWRM_UNLOCK();
3108
3109         return rc;
3110 }
3111
3112 static int update_pf_resource_max(struct bnxt *bp)
3113 {
3114         struct hwrm_func_qcfg_input req = {0};
3115         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3116         int rc;
3117
3118         /* And copy the allocated numbers into the pf struct */
3119         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3120         req.fid = rte_cpu_to_le_16(0xffff);
3121         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3122         HWRM_CHECK_RESULT();
3123
3124         /* Only TX ring value reflects actual allocation? TODO */
3125         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3126         bp->pf.evb_mode = resp->evb_mode;
3127
3128         HWRM_UNLOCK();
3129
3130         return rc;
3131 }
3132
3133 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3134 {
3135         int rc;
3136
3137         if (!BNXT_PF(bp)) {
3138                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3139                 return -EINVAL;
3140         }
3141
3142         rc = bnxt_hwrm_func_qcaps(bp);
3143         if (rc)
3144                 return rc;
3145
3146         bp->pf.func_cfg_flags &=
3147                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3148                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3149         bp->pf.func_cfg_flags |=
3150                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3151         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3152         rc = __bnxt_hwrm_func_qcaps(bp);
3153         return rc;
3154 }
3155
3156 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3157 {
3158         struct hwrm_func_cfg_input req = {0};
3159         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3160         int i;
3161         size_t sz;
3162         int rc = 0;
3163         size_t req_buf_sz;
3164
3165         if (!BNXT_PF(bp)) {
3166                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3167                 return -EINVAL;
3168         }
3169
3170         rc = bnxt_hwrm_func_qcaps(bp);
3171
3172         if (rc)
3173                 return rc;
3174
3175         bp->pf.active_vfs = num_vfs;
3176
3177         /*
3178          * First, configure the PF to only use one TX ring.  This ensures that
3179          * there are enough rings for all VFs.
3180          *
3181          * If we don't do this, when we call func_alloc() later, we will lock
3182          * extra rings to the PF that won't be available during func_cfg() of
3183          * the VFs.
3184          *
3185          * This has been fixed with firmware versions above 20.6.54
3186          */
3187         bp->pf.func_cfg_flags &=
3188                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3189                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3190         bp->pf.func_cfg_flags |=
3191                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3192         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3193         if (rc)
3194                 return rc;
3195
3196         /*
3197          * Now, create and register a buffer to hold forwarded VF requests
3198          */
3199         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3200         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3201                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3202         if (bp->pf.vf_req_buf == NULL) {
3203                 rc = -ENOMEM;
3204                 goto error_free;
3205         }
3206         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3207                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3208         for (i = 0; i < num_vfs; i++)
3209                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3210                                         (i * HWRM_MAX_REQ_LEN);
3211
3212         rc = bnxt_hwrm_func_buf_rgtr(bp);
3213         if (rc)
3214                 goto error_free;
3215
3216         populate_vf_func_cfg_req(bp, &req, num_vfs);
3217
3218         bp->pf.active_vfs = 0;
3219         for (i = 0; i < num_vfs; i++) {
3220                 add_random_mac_if_needed(bp, &req, i);
3221
3222                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3223                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3224                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3225                 rc = bnxt_hwrm_send_message(bp,
3226                                             &req,
3227                                             sizeof(req),
3228                                             BNXT_USE_CHIMP_MB);
3229
3230                 /* Clear enable flag for next pass */
3231                 req.enables &= ~rte_cpu_to_le_32(
3232                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3233
3234                 if (rc || resp->error_code) {
3235                         PMD_DRV_LOG(ERR,
3236                                 "Failed to initizlie VF %d\n", i);
3237                         PMD_DRV_LOG(ERR,
3238                                 "Not all VFs available. (%d, %d)\n",
3239                                 rc, resp->error_code);
3240                         HWRM_UNLOCK();
3241                         break;
3242                 }
3243
3244                 HWRM_UNLOCK();
3245
3246                 reserve_resources_from_vf(bp, &req, i);
3247                 bp->pf.active_vfs++;
3248                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3249         }
3250
3251         /*
3252          * Now configure the PF to use "the rest" of the resources
3253          * We're using STD_TX_RING_MODE here though which will limit the TX
3254          * rings.  This will allow QoS to function properly.  Not setting this
3255          * will cause PF rings to break bandwidth settings.
3256          */
3257         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3258         if (rc)
3259                 goto error_free;
3260
3261         rc = update_pf_resource_max(bp);
3262         if (rc)
3263                 goto error_free;
3264
3265         return rc;
3266
3267 error_free:
3268         bnxt_hwrm_func_buf_unrgtr(bp);
3269         return rc;
3270 }
3271
3272 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3273 {
3274         struct hwrm_func_cfg_input req = {0};
3275         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3276         int rc;
3277
3278         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3279
3280         req.fid = rte_cpu_to_le_16(0xffff);
3281         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3282         req.evb_mode = bp->pf.evb_mode;
3283
3284         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3285         HWRM_CHECK_RESULT();
3286         HWRM_UNLOCK();
3287
3288         return rc;
3289 }
3290
3291 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3292                                 uint8_t tunnel_type)
3293 {
3294         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3295         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3296         int rc = 0;
3297
3298         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3299         req.tunnel_type = tunnel_type;
3300         req.tunnel_dst_port_val = port;
3301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3302         HWRM_CHECK_RESULT();
3303
3304         switch (tunnel_type) {
3305         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3306                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3307                 bp->vxlan_port = port;
3308                 break;
3309         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3310                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3311                 bp->geneve_port = port;
3312                 break;
3313         default:
3314                 break;
3315         }
3316
3317         HWRM_UNLOCK();
3318
3319         return rc;
3320 }
3321
3322 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3323                                 uint8_t tunnel_type)
3324 {
3325         struct hwrm_tunnel_dst_port_free_input req = {0};
3326         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3327         int rc = 0;
3328
3329         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3330
3331         req.tunnel_type = tunnel_type;
3332         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3334
3335         HWRM_CHECK_RESULT();
3336         HWRM_UNLOCK();
3337
3338         return rc;
3339 }
3340
3341 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3342                                         uint32_t flags)
3343 {
3344         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3345         struct hwrm_func_cfg_input req = {0};
3346         int rc;
3347
3348         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3349
3350         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3351         req.flags = rte_cpu_to_le_32(flags);
3352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3353
3354         HWRM_CHECK_RESULT();
3355         HWRM_UNLOCK();
3356
3357         return rc;
3358 }
3359
3360 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3361 {
3362         uint32_t *flag = flagp;
3363
3364         vnic->flags = *flag;
3365 }
3366
3367 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3368 {
3369         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3370 }
3371
3372 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3373 {
3374         int rc = 0;
3375         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3376         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3377
3378         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3379
3380         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3381         req.req_buf_page_size = rte_cpu_to_le_16(
3382                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3383         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3384         req.req_buf_page_addr0 =
3385                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3386         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3387                 PMD_DRV_LOG(ERR,
3388                         "unable to map buffer address to physical memory\n");
3389                 return -ENOMEM;
3390         }
3391
3392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3393
3394         HWRM_CHECK_RESULT();
3395         HWRM_UNLOCK();
3396
3397         return rc;
3398 }
3399
3400 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3401 {
3402         int rc = 0;
3403         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3404         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3405
3406         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3407                 return 0;
3408
3409         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3410
3411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3412
3413         HWRM_CHECK_RESULT();
3414         HWRM_UNLOCK();
3415
3416         return rc;
3417 }
3418
3419 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3420 {
3421         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3422         struct hwrm_func_cfg_input req = {0};
3423         int rc;
3424
3425         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3426
3427         req.fid = rte_cpu_to_le_16(0xffff);
3428         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3429         req.enables = rte_cpu_to_le_32(
3430                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3431         req.async_event_cr = rte_cpu_to_le_16(
3432                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3434
3435         HWRM_CHECK_RESULT();
3436         HWRM_UNLOCK();
3437
3438         return rc;
3439 }
3440
3441 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3442 {
3443         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3444         struct hwrm_func_vf_cfg_input req = {0};
3445         int rc;
3446
3447         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3448
3449         req.enables = rte_cpu_to_le_32(
3450                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3451         req.async_event_cr = rte_cpu_to_le_16(
3452                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3454
3455         HWRM_CHECK_RESULT();
3456         HWRM_UNLOCK();
3457
3458         return rc;
3459 }
3460
3461 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3462 {
3463         struct hwrm_func_cfg_input req = {0};
3464         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3465         uint16_t dflt_vlan, fid;
3466         uint32_t func_cfg_flags;
3467         int rc = 0;
3468
3469         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3470
3471         if (is_vf) {
3472                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3473                 fid = bp->pf.vf_info[vf].fid;
3474                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3475         } else {
3476                 fid = rte_cpu_to_le_16(0xffff);
3477                 func_cfg_flags = bp->pf.func_cfg_flags;
3478                 dflt_vlan = bp->vlan;
3479         }
3480
3481         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3482         req.fid = rte_cpu_to_le_16(fid);
3483         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3484         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3485
3486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3487
3488         HWRM_CHECK_RESULT();
3489         HWRM_UNLOCK();
3490
3491         return rc;
3492 }
3493
3494 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3495                         uint16_t max_bw, uint16_t enables)
3496 {
3497         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3498         struct hwrm_func_cfg_input req = {0};
3499         int rc;
3500
3501         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3502
3503         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3504         req.enables |= rte_cpu_to_le_32(enables);
3505         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3506         req.max_bw = rte_cpu_to_le_32(max_bw);
3507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3508
3509         HWRM_CHECK_RESULT();
3510         HWRM_UNLOCK();
3511
3512         return rc;
3513 }
3514
3515 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3516 {
3517         struct hwrm_func_cfg_input req = {0};
3518         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3519         int rc = 0;
3520
3521         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3522
3523         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3524         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3525         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3526         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3527
3528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3529
3530         HWRM_CHECK_RESULT();
3531         HWRM_UNLOCK();
3532
3533         return rc;
3534 }
3535
3536 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3537 {
3538         int rc;
3539
3540         if (BNXT_PF(bp))
3541                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3542         else
3543                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3544
3545         return rc;
3546 }
3547
3548 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3549                               void *encaped, size_t ec_size)
3550 {
3551         int rc = 0;
3552         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3553         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3554
3555         if (ec_size > sizeof(req.encap_request))
3556                 return -1;
3557
3558         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3559
3560         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3561         memcpy(req.encap_request, encaped, ec_size);
3562
3563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3564
3565         HWRM_CHECK_RESULT();
3566         HWRM_UNLOCK();
3567
3568         return rc;
3569 }
3570
3571 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3572                                        struct rte_ether_addr *mac)
3573 {
3574         struct hwrm_func_qcfg_input req = {0};
3575         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3576         int rc;
3577
3578         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3579
3580         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3582
3583         HWRM_CHECK_RESULT();
3584
3585         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3586
3587         HWRM_UNLOCK();
3588
3589         return rc;
3590 }
3591
3592 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3593                             void *encaped, size_t ec_size)
3594 {
3595         int rc = 0;
3596         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3597         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3598
3599         if (ec_size > sizeof(req.encap_request))
3600                 return -1;
3601
3602         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3603
3604         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3605         memcpy(req.encap_request, encaped, ec_size);
3606
3607         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3608
3609         HWRM_CHECK_RESULT();
3610         HWRM_UNLOCK();
3611
3612         return rc;
3613 }
3614
3615 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3616                          struct rte_eth_stats *stats, uint8_t rx)
3617 {
3618         int rc = 0;
3619         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3620         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3621
3622         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3623
3624         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3625
3626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3627
3628         HWRM_CHECK_RESULT();
3629
3630         if (rx) {
3631                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3632                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3633                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3634                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3635                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3636                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3637                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3638                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3639         } else {
3640                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3641                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3642                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3643                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3644                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3645                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3646         }
3647
3648         HWRM_UNLOCK();
3649
3650         return rc;
3651 }
3652
3653 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3654 {
3655         struct hwrm_port_qstats_input req = {0};
3656         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3657         struct bnxt_pf_info *pf = &bp->pf;
3658         int rc;
3659
3660         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3661
3662         req.port_id = rte_cpu_to_le_16(pf->port_id);
3663         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3664         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3666
3667         HWRM_CHECK_RESULT();
3668         HWRM_UNLOCK();
3669
3670         return rc;
3671 }
3672
3673 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3674 {
3675         struct hwrm_port_clr_stats_input req = {0};
3676         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3677         struct bnxt_pf_info *pf = &bp->pf;
3678         int rc;
3679
3680         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3681         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3682             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3683                 return 0;
3684
3685         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3686
3687         req.port_id = rte_cpu_to_le_16(pf->port_id);
3688         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3689
3690         HWRM_CHECK_RESULT();
3691         HWRM_UNLOCK();
3692
3693         return rc;
3694 }
3695
3696 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3697 {
3698         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3699         struct hwrm_port_led_qcaps_input req = {0};
3700         int rc;
3701
3702         if (BNXT_VF(bp))
3703                 return 0;
3704
3705         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3706         req.port_id = bp->pf.port_id;
3707         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3708
3709         HWRM_CHECK_RESULT();
3710
3711         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3712                 unsigned int i;
3713
3714                 bp->num_leds = resp->num_leds;
3715                 memcpy(bp->leds, &resp->led0_id,
3716                         sizeof(bp->leds[0]) * bp->num_leds);
3717                 for (i = 0; i < bp->num_leds; i++) {
3718                         struct bnxt_led_info *led = &bp->leds[i];
3719
3720                         uint16_t caps = led->led_state_caps;
3721
3722                         if (!led->led_group_id ||
3723                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3724                                 bp->num_leds = 0;
3725                                 break;
3726                         }
3727                 }
3728         }
3729
3730         HWRM_UNLOCK();
3731
3732         return rc;
3733 }
3734
3735 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3736 {
3737         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3738         struct hwrm_port_led_cfg_input req = {0};
3739         struct bnxt_led_cfg *led_cfg;
3740         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3741         uint16_t duration = 0;
3742         int rc, i;
3743
3744         if (!bp->num_leds || BNXT_VF(bp))
3745                 return -EOPNOTSUPP;
3746
3747         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3748
3749         if (led_on) {
3750                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3751                 duration = rte_cpu_to_le_16(500);
3752         }
3753         req.port_id = bp->pf.port_id;
3754         req.num_leds = bp->num_leds;
3755         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3756         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3757                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3758                 led_cfg->led_id = bp->leds[i].led_id;
3759                 led_cfg->led_state = led_state;
3760                 led_cfg->led_blink_on = duration;
3761                 led_cfg->led_blink_off = duration;
3762                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3763         }
3764
3765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3766
3767         HWRM_CHECK_RESULT();
3768         HWRM_UNLOCK();
3769
3770         return rc;
3771 }
3772
3773 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3774                                uint32_t *length)
3775 {
3776         int rc;
3777         struct hwrm_nvm_get_dir_info_input req = {0};
3778         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3779
3780         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3781
3782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3783
3784         HWRM_CHECK_RESULT();
3785
3786         *entries = rte_le_to_cpu_32(resp->entries);
3787         *length = rte_le_to_cpu_32(resp->entry_length);
3788
3789         HWRM_UNLOCK();
3790         return rc;
3791 }
3792
3793 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3794 {
3795         int rc;
3796         uint32_t dir_entries;
3797         uint32_t entry_length;
3798         uint8_t *buf;
3799         size_t buflen;
3800         rte_iova_t dma_handle;
3801         struct hwrm_nvm_get_dir_entries_input req = {0};
3802         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3803
3804         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3805         if (rc != 0)
3806                 return rc;
3807
3808         *data++ = dir_entries;
3809         *data++ = entry_length;
3810         len -= 2;
3811         memset(data, 0xff, len);
3812
3813         buflen = dir_entries * entry_length;
3814         buf = rte_malloc("nvm_dir", buflen, 0);
3815         rte_mem_lock_page(buf);
3816         if (buf == NULL)
3817                 return -ENOMEM;
3818         dma_handle = rte_mem_virt2iova(buf);
3819         if (dma_handle == RTE_BAD_IOVA) {
3820                 PMD_DRV_LOG(ERR,
3821                         "unable to map response address to physical memory\n");
3822                 return -ENOMEM;
3823         }
3824         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3825         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3826         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3827
3828         if (rc == 0)
3829                 memcpy(data, buf, len > buflen ? buflen : len);
3830
3831         rte_free(buf);
3832         HWRM_CHECK_RESULT();
3833         HWRM_UNLOCK();
3834
3835         return rc;
3836 }
3837
3838 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3839                              uint32_t offset, uint32_t length,
3840                              uint8_t *data)
3841 {
3842         int rc;
3843         uint8_t *buf;
3844         rte_iova_t dma_handle;
3845         struct hwrm_nvm_read_input req = {0};
3846         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3847
3848         buf = rte_malloc("nvm_item", length, 0);
3849         rte_mem_lock_page(buf);
3850         if (!buf)
3851                 return -ENOMEM;
3852
3853         dma_handle = rte_mem_virt2iova(buf);
3854         if (dma_handle == RTE_BAD_IOVA) {
3855                 PMD_DRV_LOG(ERR,
3856                         "unable to map response address to physical memory\n");
3857                 return -ENOMEM;
3858         }
3859         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3860         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3861         req.dir_idx = rte_cpu_to_le_16(index);
3862         req.offset = rte_cpu_to_le_32(offset);
3863         req.len = rte_cpu_to_le_32(length);
3864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3865         if (rc == 0)
3866                 memcpy(data, buf, length);
3867
3868         rte_free(buf);
3869         HWRM_CHECK_RESULT();
3870         HWRM_UNLOCK();
3871
3872         return rc;
3873 }
3874
3875 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3876 {
3877         int rc;
3878         struct hwrm_nvm_erase_dir_entry_input req = {0};
3879         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3880
3881         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3882         req.dir_idx = rte_cpu_to_le_16(index);
3883         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3884         HWRM_CHECK_RESULT();
3885         HWRM_UNLOCK();
3886
3887         return rc;
3888 }
3889
3890
3891 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3892                           uint16_t dir_ordinal, uint16_t dir_ext,
3893                           uint16_t dir_attr, const uint8_t *data,
3894                           size_t data_len)
3895 {
3896         int rc;
3897         struct hwrm_nvm_write_input req = {0};
3898         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3899         rte_iova_t dma_handle;
3900         uint8_t *buf;
3901
3902         buf = rte_malloc("nvm_write", data_len, 0);
3903         rte_mem_lock_page(buf);
3904         if (!buf)
3905                 return -ENOMEM;
3906
3907         dma_handle = rte_mem_virt2iova(buf);
3908         if (dma_handle == RTE_BAD_IOVA) {
3909                 PMD_DRV_LOG(ERR,
3910                         "unable to map response address to physical memory\n");
3911                 return -ENOMEM;
3912         }
3913         memcpy(buf, data, data_len);
3914
3915         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3916
3917         req.dir_type = rte_cpu_to_le_16(dir_type);
3918         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3919         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3920         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3921         req.dir_data_length = rte_cpu_to_le_32(data_len);
3922         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3923
3924         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3925
3926         rte_free(buf);
3927         HWRM_CHECK_RESULT();
3928         HWRM_UNLOCK();
3929
3930         return rc;
3931 }
3932
3933 static void
3934 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3935 {
3936         uint32_t *count = cbdata;
3937
3938         *count = *count + 1;
3939 }
3940
3941 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3942                                      struct bnxt_vnic_info *vnic __rte_unused)
3943 {
3944         return 0;
3945 }
3946
3947 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3948 {
3949         uint32_t count = 0;
3950
3951         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3952             &count, bnxt_vnic_count_hwrm_stub);
3953
3954         return count;
3955 }
3956
3957 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3958                                         uint16_t *vnic_ids)
3959 {
3960         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3961         struct hwrm_func_vf_vnic_ids_query_output *resp =
3962                                                 bp->hwrm_cmd_resp_addr;
3963         int rc;
3964
3965         /* First query all VNIC ids */
3966         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3967
3968         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3969         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3970         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3971
3972         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3973                 HWRM_UNLOCK();
3974                 PMD_DRV_LOG(ERR,
3975                 "unable to map VNIC ID table address to physical memory\n");
3976                 return -ENOMEM;
3977         }
3978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3979         HWRM_CHECK_RESULT();
3980         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3981
3982         HWRM_UNLOCK();
3983
3984         return rc;
3985 }
3986
3987 /*
3988  * This function queries the VNIC IDs  for a specified VF. It then calls
3989  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3990  * Then it calls the hwrm_cb function to program this new vnic configuration.
3991  */
3992 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3993         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3994         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3995 {
3996         struct bnxt_vnic_info vnic;
3997         int rc = 0;
3998         int i, num_vnic_ids;
3999         uint16_t *vnic_ids;
4000         size_t vnic_id_sz;
4001         size_t sz;
4002
4003         /* First query all VNIC ids */
4004         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4005         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4006                         RTE_CACHE_LINE_SIZE);
4007         if (vnic_ids == NULL)
4008                 return -ENOMEM;
4009
4010         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4011                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4012
4013         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4014
4015         if (num_vnic_ids < 0)
4016                 return num_vnic_ids;
4017
4018         /* Retrieve VNIC, update bd_stall then update */
4019
4020         for (i = 0; i < num_vnic_ids; i++) {
4021                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4022                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4023                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4024                 if (rc)
4025                         break;
4026                 if (vnic.mru <= 4)      /* Indicates unallocated */
4027                         continue;
4028
4029                 vnic_cb(&vnic, cbdata);
4030
4031                 rc = hwrm_cb(bp, &vnic);
4032                 if (rc)
4033                         break;
4034         }
4035
4036         rte_free(vnic_ids);
4037
4038         return rc;
4039 }
4040
4041 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4042                                               bool on)
4043 {
4044         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4045         struct hwrm_func_cfg_input req = {0};
4046         int rc;
4047
4048         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4049
4050         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4051         req.enables |= rte_cpu_to_le_32(
4052                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4053         req.vlan_antispoof_mode = on ?
4054                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4055                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4057
4058         HWRM_CHECK_RESULT();
4059         HWRM_UNLOCK();
4060
4061         return rc;
4062 }
4063
4064 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4065 {
4066         struct bnxt_vnic_info vnic;
4067         uint16_t *vnic_ids;
4068         size_t vnic_id_sz;
4069         int num_vnic_ids, i;
4070         size_t sz;
4071         int rc;
4072
4073         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4074         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4075                         RTE_CACHE_LINE_SIZE);
4076         if (vnic_ids == NULL)
4077                 return -ENOMEM;
4078
4079         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4080                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4081
4082         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4083         if (rc <= 0)
4084                 goto exit;
4085         num_vnic_ids = rc;
4086
4087         /*
4088          * Loop through to find the default VNIC ID.
4089          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4090          * by sending the hwrm_func_qcfg command to the firmware.
4091          */
4092         for (i = 0; i < num_vnic_ids; i++) {
4093                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4094                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4095                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4096                                         bp->pf.first_vf_id + vf);
4097                 if (rc)
4098                         goto exit;
4099                 if (vnic.func_default) {
4100                         rte_free(vnic_ids);
4101                         return vnic.fw_vnic_id;
4102                 }
4103         }
4104         /* Could not find a default VNIC. */
4105         PMD_DRV_LOG(ERR, "No default VNIC\n");
4106 exit:
4107         rte_free(vnic_ids);
4108         return rc;
4109 }
4110
4111 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4112                          uint16_t dst_id,
4113                          struct bnxt_filter_info *filter)
4114 {
4115         int rc = 0;
4116         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4117         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4118         uint32_t enables = 0;
4119
4120         if (filter->fw_em_filter_id != UINT64_MAX)
4121                 bnxt_hwrm_clear_em_filter(bp, filter);
4122
4123         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4124
4125         req.flags = rte_cpu_to_le_32(filter->flags);
4126
4127         enables = filter->enables |
4128               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4129         req.dst_id = rte_cpu_to_le_16(dst_id);
4130
4131         if (filter->ip_addr_type) {
4132                 req.ip_addr_type = filter->ip_addr_type;
4133                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4134         }
4135         if (enables &
4136             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4137                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4138         if (enables &
4139             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4140                 memcpy(req.src_macaddr, filter->src_macaddr,
4141                        RTE_ETHER_ADDR_LEN);
4142         if (enables &
4143             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4144                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4145                        RTE_ETHER_ADDR_LEN);
4146         if (enables &
4147             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4148                 req.ovlan_vid = filter->l2_ovlan;
4149         if (enables &
4150             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4151                 req.ivlan_vid = filter->l2_ivlan;
4152         if (enables &
4153             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4154                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4155         if (enables &
4156             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4157                 req.ip_protocol = filter->ip_protocol;
4158         if (enables &
4159             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4160                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4161         if (enables &
4162             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4163                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4164         if (enables &
4165             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4166                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4167         if (enables &
4168             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4169                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4170         if (enables &
4171             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4172                 req.mirror_vnic_id = filter->mirror_vnic_id;
4173
4174         req.enables = rte_cpu_to_le_32(enables);
4175
4176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4177
4178         HWRM_CHECK_RESULT();
4179
4180         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4181         HWRM_UNLOCK();
4182
4183         return rc;
4184 }
4185
4186 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4187 {
4188         int rc = 0;
4189         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4190         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4191
4192         if (filter->fw_em_filter_id == UINT64_MAX)
4193                 return 0;
4194
4195         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4196
4197         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4198
4199         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4200
4201         HWRM_CHECK_RESULT();
4202         HWRM_UNLOCK();
4203
4204         filter->fw_em_filter_id = UINT64_MAX;
4205         filter->fw_l2_filter_id = UINT64_MAX;
4206
4207         return 0;
4208 }
4209
4210 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4211                          uint16_t dst_id,
4212                          struct bnxt_filter_info *filter)
4213 {
4214         int rc = 0;
4215         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4216         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4217                                                 bp->hwrm_cmd_resp_addr;
4218         uint32_t enables = 0;
4219
4220         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4221                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4222
4223         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4224
4225         req.flags = rte_cpu_to_le_32(filter->flags);
4226
4227         enables = filter->enables |
4228               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4229         req.dst_id = rte_cpu_to_le_16(dst_id);
4230
4231         if (filter->ip_addr_type) {
4232                 req.ip_addr_type = filter->ip_addr_type;
4233                 enables |=
4234                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4235         }
4236         if (enables &
4237             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4238                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4239         if (enables &
4240             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4241                 memcpy(req.src_macaddr, filter->src_macaddr,
4242                        RTE_ETHER_ADDR_LEN);
4243         if (enables &
4244             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4245                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4246         if (enables &
4247             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4248                 req.ip_protocol = filter->ip_protocol;
4249         if (enables &
4250             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4251                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4252         if (enables &
4253             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4254                 req.src_ipaddr_mask[0] =
4255                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4256         if (enables &
4257             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4258                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4259         if (enables &
4260             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4261                 req.dst_ipaddr_mask[0] =
4262                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4263         if (enables &
4264             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4265                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4266         if (enables &
4267             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4268                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4269         if (enables &
4270             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4271                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4272         if (enables &
4273             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4274                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4275         if (enables &
4276             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4277                 req.mirror_vnic_id = filter->mirror_vnic_id;
4278
4279         req.enables = rte_cpu_to_le_32(enables);
4280
4281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4282
4283         HWRM_CHECK_RESULT();
4284
4285         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4286         HWRM_UNLOCK();
4287
4288         return rc;
4289 }
4290
4291 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4292                                 struct bnxt_filter_info *filter)
4293 {
4294         int rc = 0;
4295         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4296         struct hwrm_cfa_ntuple_filter_free_output *resp =
4297                                                 bp->hwrm_cmd_resp_addr;
4298
4299         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4300                 return 0;
4301
4302         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4303
4304         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4305
4306         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4307
4308         HWRM_CHECK_RESULT();
4309         HWRM_UNLOCK();
4310
4311         filter->fw_ntuple_filter_id = UINT64_MAX;
4312
4313         return 0;
4314 }
4315
4316 static int
4317 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4318 {
4319         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4320         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4321         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4322         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4323         uint16_t *ring_tbl = vnic->rss_table;
4324         int nr_ctxs = vnic->num_lb_ctxts;
4325         int max_rings = bp->rx_nr_rings;
4326         int i, j, k, cnt;
4327         int rc = 0;
4328
4329         for (i = 0, k = 0; i < nr_ctxs; i++) {
4330                 struct bnxt_rx_ring_info *rxr;
4331                 struct bnxt_cp_ring_info *cpr;
4332
4333                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4334
4335                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4336                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4337                 req.hash_mode_flags = vnic->hash_mode;
4338
4339                 req.ring_grp_tbl_addr =
4340                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4341                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4342                                      2 * sizeof(*ring_tbl));
4343                 req.hash_key_tbl_addr =
4344                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4345
4346                 req.ring_table_pair_index = i;
4347                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4348
4349                 for (j = 0; j < 64; j++) {
4350                         uint16_t ring_id;
4351
4352                         /* Find next active ring. */
4353                         for (cnt = 0; cnt < max_rings; cnt++) {
4354                                 if (rx_queue_state[k] !=
4355                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4356                                         break;
4357                                 if (++k == max_rings)
4358                                         k = 0;
4359                         }
4360
4361                         /* Return if no rings are active. */
4362                         if (cnt == max_rings) {
4363                                 HWRM_UNLOCK();
4364                                 return 0;
4365                         }
4366
4367                         /* Add rx/cp ring pair to RSS table. */
4368                         rxr = rxqs[k]->rx_ring;
4369                         cpr = rxqs[k]->cp_ring;
4370
4371                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4372                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4373                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4374                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4375
4376                         if (++k == max_rings)
4377                                 k = 0;
4378                 }
4379                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4380                                             BNXT_USE_CHIMP_MB);
4381
4382                 HWRM_CHECK_RESULT();
4383                 HWRM_UNLOCK();
4384         }
4385
4386         return rc;
4387 }
4388
4389 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4390 {
4391         unsigned int rss_idx, fw_idx, i;
4392
4393         if (!(vnic->rss_table && vnic->hash_type))
4394                 return 0;
4395
4396         if (BNXT_CHIP_THOR(bp))
4397                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4398
4399         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4400                 return 0;
4401
4402         if (vnic->rss_table && vnic->hash_type) {
4403                 /*
4404                  * Fill the RSS hash & redirection table with
4405                  * ring group ids for all VNICs
4406                  */
4407                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4408                         rss_idx++, fw_idx++) {
4409                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4410                                 fw_idx %= bp->rx_cp_nr_rings;
4411                                 if (vnic->fw_grp_ids[fw_idx] !=
4412                                     INVALID_HW_RING_ID)
4413                                         break;
4414                                 fw_idx++;
4415                         }
4416                         if (i == bp->rx_cp_nr_rings)
4417                                 return 0;
4418                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4419                 }
4420                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4421         }
4422
4423         return 0;
4424 }
4425
4426 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4427         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4428 {
4429         uint16_t flags;
4430
4431         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4432
4433         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4434         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4435
4436         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4437         req->num_cmpl_dma_aggr_during_int =
4438                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4439
4440         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4441
4442         /* min timer set to 1/2 of interrupt timer */
4443         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4444
4445         /* buf timer set to 1/4 of interrupt timer */
4446         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4447
4448         req->cmpl_aggr_dma_tmr_during_int =
4449                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4450
4451         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4452                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4453         req->flags = rte_cpu_to_le_16(flags);
4454 }
4455
4456 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4457                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4458 {
4459         struct hwrm_ring_aggint_qcaps_input req = {0};
4460         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4461         uint32_t enables;
4462         uint16_t flags;
4463         int rc;
4464
4465         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4467         HWRM_CHECK_RESULT();
4468
4469         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4470         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4471
4472         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4473                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4474         agg_req->flags = rte_cpu_to_le_16(flags);
4475         enables =
4476          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4477          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4478         agg_req->enables = rte_cpu_to_le_32(enables);
4479
4480         HWRM_UNLOCK();
4481         return rc;
4482 }
4483
4484 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4485                         struct bnxt_coal *coal, uint16_t ring_id)
4486 {
4487         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4488         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4489                                                 bp->hwrm_cmd_resp_addr;
4490         int rc;
4491
4492         /* Set ring coalesce parameters only for 100G NICs */
4493         if (BNXT_CHIP_THOR(bp)) {
4494                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4495                         return -1;
4496         } else if (bnxt_stratus_device(bp)) {
4497                 bnxt_hwrm_set_coal_params(coal, &req);
4498         } else {
4499                 return 0;
4500         }
4501
4502         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4503         req.ring_id = rte_cpu_to_le_16(ring_id);
4504         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4505         HWRM_CHECK_RESULT();
4506         HWRM_UNLOCK();
4507         return 0;
4508 }
4509
4510 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4511 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4512 {
4513         struct hwrm_func_backing_store_qcaps_input req = {0};
4514         struct hwrm_func_backing_store_qcaps_output *resp =
4515                 bp->hwrm_cmd_resp_addr;
4516         struct bnxt_ctx_pg_info *ctx_pg;
4517         struct bnxt_ctx_mem_info *ctx;
4518         int total_alloc_len;
4519         int rc, i;
4520
4521         if (!BNXT_CHIP_THOR(bp) ||
4522             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4523             BNXT_VF(bp) ||
4524             bp->ctx)
4525                 return 0;
4526
4527         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4529         HWRM_CHECK_RESULT_SILENT();
4530
4531         total_alloc_len = sizeof(*ctx);
4532         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4533                           RTE_CACHE_LINE_SIZE);
4534         if (!ctx) {
4535                 rc = -ENOMEM;
4536                 goto ctx_err;
4537         }
4538
4539         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4540                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4541                             RTE_CACHE_LINE_SIZE);
4542         if (!ctx_pg) {
4543                 rc = -ENOMEM;
4544                 goto ctx_err;
4545         }
4546         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4547                 ctx->tqm_mem[i] = ctx_pg;
4548
4549         bp->ctx = ctx;
4550         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4551         ctx->qp_min_qp1_entries =
4552                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4553         ctx->qp_max_l2_entries =
4554                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4555         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4556         ctx->srq_max_l2_entries =
4557                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4558         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4559         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4560         ctx->cq_max_l2_entries =
4561                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4562         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4563         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4564         ctx->vnic_max_vnic_entries =
4565                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4566         ctx->vnic_max_ring_table_entries =
4567                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4568         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4569         ctx->stat_max_entries =
4570                 rte_le_to_cpu_32(resp->stat_max_entries);
4571         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4572         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4573         ctx->tqm_min_entries_per_ring =
4574                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4575         ctx->tqm_max_entries_per_ring =
4576                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4577         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4578         if (!ctx->tqm_entries_multiple)
4579                 ctx->tqm_entries_multiple = 1;
4580         ctx->mrav_max_entries =
4581                 rte_le_to_cpu_32(resp->mrav_max_entries);
4582         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4583         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4584         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4585 ctx_err:
4586         HWRM_UNLOCK();
4587         return rc;
4588 }
4589
4590 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4591 {
4592         struct hwrm_func_backing_store_cfg_input req = {0};
4593         struct hwrm_func_backing_store_cfg_output *resp =
4594                 bp->hwrm_cmd_resp_addr;
4595         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4596         struct bnxt_ctx_pg_info *ctx_pg;
4597         uint32_t *num_entries;
4598         uint64_t *pg_dir;
4599         uint8_t *pg_attr;
4600         uint32_t ena;
4601         int i, rc;
4602
4603         if (!ctx)
4604                 return 0;
4605
4606         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4607         req.enables = rte_cpu_to_le_32(enables);
4608
4609         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4610                 ctx_pg = &ctx->qp_mem;
4611                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4612                 req.qp_num_qp1_entries =
4613                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4614                 req.qp_num_l2_entries =
4615                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4616                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4617                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4618                                       &req.qpc_pg_size_qpc_lvl,
4619                                       &req.qpc_page_dir);
4620         }
4621
4622         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4623                 ctx_pg = &ctx->srq_mem;
4624                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4625                 req.srq_num_l2_entries =
4626                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4627                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4628                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4629                                       &req.srq_pg_size_srq_lvl,
4630                                       &req.srq_page_dir);
4631         }
4632
4633         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4634                 ctx_pg = &ctx->cq_mem;
4635                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4636                 req.cq_num_l2_entries =
4637                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4638                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4639                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4640                                       &req.cq_pg_size_cq_lvl,
4641                                       &req.cq_page_dir);
4642         }
4643
4644         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4645                 ctx_pg = &ctx->vnic_mem;
4646                 req.vnic_num_vnic_entries =
4647                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4648                 req.vnic_num_ring_table_entries =
4649                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4650                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4651                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4652                                       &req.vnic_pg_size_vnic_lvl,
4653                                       &req.vnic_page_dir);
4654         }
4655
4656         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4657                 ctx_pg = &ctx->stat_mem;
4658                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4659                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4660                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4661                                       &req.stat_pg_size_stat_lvl,
4662                                       &req.stat_page_dir);
4663         }
4664
4665         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4666         num_entries = &req.tqm_sp_num_entries;
4667         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4668         pg_dir = &req.tqm_sp_page_dir;
4669         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4670         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4671                 if (!(enables & ena))
4672                         continue;
4673
4674                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4675
4676                 ctx_pg = ctx->tqm_mem[i];
4677                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4678                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4679         }
4680
4681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4682         HWRM_CHECK_RESULT();
4683         HWRM_UNLOCK();
4684
4685         return rc;
4686 }
4687
4688 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4689 {
4690         struct hwrm_port_qstats_ext_input req = {0};
4691         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4692         struct bnxt_pf_info *pf = &bp->pf;
4693         int rc;
4694
4695         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4696               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4697                 return 0;
4698
4699         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4700
4701         req.port_id = rte_cpu_to_le_16(pf->port_id);
4702         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4703                 req.tx_stat_host_addr =
4704                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4705                 req.tx_stat_size =
4706                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4707         }
4708         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4709                 req.rx_stat_host_addr =
4710                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4711                 req.rx_stat_size =
4712                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4713         }
4714         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4715
4716         if (rc) {
4717                 bp->fw_rx_port_stats_ext_size = 0;
4718                 bp->fw_tx_port_stats_ext_size = 0;
4719         } else {
4720                 bp->fw_rx_port_stats_ext_size =
4721                         rte_le_to_cpu_16(resp->rx_stat_size);
4722                 bp->fw_tx_port_stats_ext_size =
4723                         rte_le_to_cpu_16(resp->tx_stat_size);
4724         }
4725
4726         HWRM_CHECK_RESULT();
4727         HWRM_UNLOCK();
4728
4729         return rc;
4730 }
4731
4732 int
4733 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4734 {
4735         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4736         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4737                 bp->hwrm_cmd_resp_addr;
4738         int rc = 0;
4739
4740         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4741         req.tunnel_type = type;
4742         req.dest_fid = bp->fw_fid;
4743         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4744         HWRM_CHECK_RESULT();
4745
4746         HWRM_UNLOCK();
4747
4748         return rc;
4749 }
4750
4751 int
4752 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4753 {
4754         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4755         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4756                 bp->hwrm_cmd_resp_addr;
4757         int rc = 0;
4758
4759         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4760         req.tunnel_type = type;
4761         req.dest_fid = bp->fw_fid;
4762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4763         HWRM_CHECK_RESULT();
4764
4765         HWRM_UNLOCK();
4766
4767         return rc;
4768 }
4769
4770 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4771 {
4772         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4773         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4774                 bp->hwrm_cmd_resp_addr;
4775         int rc = 0;
4776
4777         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4778         req.src_fid = bp->fw_fid;
4779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4780         HWRM_CHECK_RESULT();
4781
4782         if (type)
4783                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4784
4785         HWRM_UNLOCK();
4786
4787         return rc;
4788 }
4789
4790 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4791                                    uint16_t *dst_fid)
4792 {
4793         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4794         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4795                 bp->hwrm_cmd_resp_addr;
4796         int rc = 0;
4797
4798         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4799         req.src_fid = bp->fw_fid;
4800         req.tunnel_type = tun_type;
4801         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4802         HWRM_CHECK_RESULT();
4803
4804         if (dst_fid)
4805                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4806
4807         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4808
4809         HWRM_UNLOCK();
4810
4811         return rc;
4812 }
4813
4814 int bnxt_hwrm_set_mac(struct bnxt *bp)
4815 {
4816         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4817         struct hwrm_func_vf_cfg_input req = {0};
4818         int rc = 0;
4819
4820         if (!BNXT_VF(bp))
4821                 return 0;
4822
4823         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4824
4825         req.enables =
4826                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4827         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4828
4829         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4830
4831         HWRM_CHECK_RESULT();
4832
4833         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4834         HWRM_UNLOCK();
4835
4836         return rc;
4837 }
4838
4839 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4840 {
4841         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4842         struct hwrm_func_drv_if_change_input req = {0};
4843         uint32_t flags;
4844         int rc;
4845
4846         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
4847                 return 0;
4848
4849         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4850          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4851          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4852          */
4853         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4854                 return 0;
4855
4856         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4857
4858         if (up)
4859                 req.flags =
4860                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4861
4862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4863
4864         HWRM_CHECK_RESULT();
4865         flags = rte_le_to_cpu_32(resp->flags);
4866         HWRM_UNLOCK();
4867
4868         if (!up)
4869                 return 0;
4870
4871         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4872                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4873                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4874         }
4875
4876         return 0;
4877 }
4878
4879 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4880 {
4881         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4882         struct bnxt_error_recovery_info *info = bp->recovery_info;
4883         struct hwrm_error_recovery_qcfg_input req = {0};
4884         uint32_t flags = 0;
4885         unsigned int i;
4886         int rc;
4887
4888         /* Older FW does not have error recovery support */
4889         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4890                 return 0;
4891
4892         if (!info) {
4893                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4894                                    sizeof(*info), 0);
4895                 bp->recovery_info = info;
4896                 if (info == NULL)
4897                         return -ENOMEM;
4898         } else {
4899                 memset(info, 0, sizeof(*info));
4900         }
4901
4902         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4903
4904         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4905
4906         HWRM_CHECK_RESULT();
4907
4908         flags = rte_le_to_cpu_32(resp->flags);
4909         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4910                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4911         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4912                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4913
4914         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4915             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4916                 rc = -EINVAL;
4917                 goto err;
4918         }
4919
4920         /* FW returned values are in units of 100msec */
4921         info->driver_polling_freq =
4922                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4923         info->master_func_wait_period =
4924                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4925         info->normal_func_wait_period =
4926                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4927         info->master_func_wait_period_after_reset =
4928                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4929         info->max_bailout_time_after_reset =
4930                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4931         info->status_regs[BNXT_FW_STATUS_REG] =
4932                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4933         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4934                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4935         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4936                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4937         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4938                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4939         info->reg_array_cnt =
4940                 rte_le_to_cpu_32(resp->reg_array_cnt);
4941
4942         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4943                 rc = -EINVAL;
4944                 goto err;
4945         }
4946
4947         for (i = 0; i < info->reg_array_cnt; i++) {
4948                 info->reset_reg[i] =
4949                         rte_le_to_cpu_32(resp->reset_reg[i]);
4950                 info->reset_reg_val[i] =
4951                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4952                 info->delay_after_reset[i] =
4953                         resp->delay_after_reset[i];
4954         }
4955 err:
4956         HWRM_UNLOCK();
4957
4958         /* Map the FW status registers */
4959         if (!rc)
4960                 rc = bnxt_map_fw_health_status_regs(bp);
4961
4962         if (rc) {
4963                 rte_free(bp->recovery_info);
4964                 bp->recovery_info = NULL;
4965         }
4966         return rc;
4967 }
4968
4969 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4970 {
4971         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4972         struct hwrm_fw_reset_input req = {0};
4973         int rc;
4974
4975         if (!BNXT_PF(bp))
4976                 return -EOPNOTSUPP;
4977
4978         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4979
4980         req.embedded_proc_type =
4981                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4982         req.selfrst_status =
4983                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4984         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4985
4986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4987                                     BNXT_USE_KONG(bp));
4988
4989         HWRM_CHECK_RESULT();
4990         HWRM_UNLOCK();
4991
4992         return rc;
4993 }
4994
4995 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4996 {
4997         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4998         struct hwrm_port_ts_query_input req = {0};
4999         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5000         uint32_t flags = 0;
5001         int rc;
5002
5003         if (!ptp)
5004                 return 0;
5005
5006         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5007
5008         switch (path) {
5009         case BNXT_PTP_FLAGS_PATH_TX:
5010                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5011                 break;
5012         case BNXT_PTP_FLAGS_PATH_RX:
5013                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5014                 break;
5015         case BNXT_PTP_FLAGS_CURRENT_TIME:
5016                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5017                 break;
5018         }
5019
5020         req.flags = rte_cpu_to_le_32(flags);
5021         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5022
5023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5024
5025         HWRM_CHECK_RESULT();
5026
5027         if (timestamp) {
5028                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5029                 *timestamp |=
5030                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5031         }
5032         HWRM_UNLOCK();
5033
5034         return rc;
5035 }
5036
5037 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5038 {
5039         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5040                                         bp->hwrm_cmd_resp_addr;
5041         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5042         uint32_t flags = 0;
5043         int rc = 0;
5044
5045         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5046                 return rc;
5047
5048         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5049                 PMD_DRV_LOG(DEBUG,
5050                             "Not a PF or trusted VF. Command not supported\n");
5051                 return 0;
5052         }
5053
5054         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5055         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5056
5057         HWRM_CHECK_RESULT();
5058         flags = rte_le_to_cpu_32(resp->flags);
5059         HWRM_UNLOCK();
5060
5061         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5062                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5063                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5064         }
5065
5066         return rc;
5067 }