drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 168                             req->req_type);
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns. If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type, kong) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         if (bp->hwrm_cmd_resp_addr == NULL) { \
 188                 rte_spinlock_unlock(&bp->hwrm_lock); \
 189                 return -EACCES; \
 190         } \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         (req)->req_type = rte_cpu_to_le_16(type); \
 193         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 194         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 196         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 197         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 261                                 bool use_kong_mb,
 262                                 uint16_t msg_type,
 263                                 void *msg,
 264                                 uint32_t msg_len,
 265                                 void *resp_msg,
 266                                 uint32_t resp_len)
 267 {
 268         int rc = 0;
 269         bool mailbox = BNXT_USE_CHIMP_MB;
 270         struct input *req = msg;
 271         struct output *resp = bp->hwrm_cmd_resp_addr;
 272
 273         if (use_kong_mb)
 274                 mailbox = BNXT_USE_KONG(bp);
 275
 276         HWRM_PREP(req, msg_type, mailbox);
 277
 278         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 279
 280         HWRM_CHECK_RESULT();
 281
 282         if (resp_msg)
 283                 memcpy(resp_msg, resp, resp_len);
 284
 285         HWRM_UNLOCK();
 286
 287         return rc;
 288 }
 289
 290 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 291                                   bool use_kong_mb,
 292                                   uint16_t tf_type,
 293                                   uint16_t tf_subtype,
 294                                   uint32_t *tf_response_code,
 295                                   void *msg,
 296                                   uint32_t msg_len,
 297                                   void *response,
 298                                   uint32_t response_len)
 299 {
 300         int rc = 0;
 301         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 302         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 303         bool mailbox = BNXT_USE_CHIMP_MB;
 304
 305         if (msg_len > sizeof(req.tf_req))
 306                 return -ENOMEM;
 307
 308         if (use_kong_mb)
 309                 mailbox = BNXT_USE_KONG(bp);
 310
 311         HWRM_PREP(&req, HWRM_TF, mailbox);
 312         /* Build request using the user supplied request payload.
 313          * TLV request size is checked at build time against HWRM
 314          * request max size, thus no checking required.
 315          */
 316         req.tf_type = tf_type;
 317         req.tf_subtype = tf_subtype;
 318         memcpy(req.tf_req, msg, msg_len);
 319
 320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 321         HWRM_CHECK_RESULT();
 322
 323         /* Copy the resp to user provided response buffer */
 324         if (response != NULL)
 325                 /* Post process response data. We need to copy only
 326                  * the 'payload' as the HWRM data structure really is
 327                  * HWRM header + msg header + payload and the TFLIB
 328                  * only provided a payload place holder.
 329                  */
 330                 if (response_len != 0) {
 331                         memcpy(response,
 332                                resp->tf_resp,
 333                                response_len);
 334                 }
 335
 336         /* Extract the internal tflib response code */
 337         *tf_response_code = resp->tf_resp_code;
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 344 {
 345         int rc = 0;
 346         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 347         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 348
 349         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 350         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 351         req.mask = 0;
 352
 353         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 354
 355         HWRM_CHECK_RESULT();
 356         HWRM_UNLOCK();
 357
 358         return rc;
 359 }
 360
 361 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 362                                  struct bnxt_vnic_info *vnic,
 363                                  uint16_t vlan_count,
 364                                  struct bnxt_vlan_table_entry *vlan_table)
 365 {
 366         int rc = 0;
 367         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 368         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 369         uint32_t mask = 0;
 370
 371         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 372                 return rc;
 373
 374         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 375         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 376
 377         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 378                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 379         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 380                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 384
 385         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 386                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 387         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 389                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 390                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 391         }
 392         if (vlan_table) {
 393                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 394                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 395                 req.vlan_tag_tbl_addr =
 396                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 397                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 398         }
 399         req.mask = rte_cpu_to_le_32(mask);
 400
 401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 402
 403         HWRM_CHECK_RESULT();
 404         HWRM_UNLOCK();
 405
 406         return rc;
 407 }
 408
 409 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 410                         uint16_t vlan_count,
 411                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 412 {
 413         int rc = 0;
 414         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 415         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 416                                                 bp->hwrm_cmd_resp_addr;
 417
 418         /*
 419          * Older HWRM versions did not support this command, and the set_rx_mask
 420          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 421          * removed from set_rx_mask call, and this command was added.
 422          *
 423          * This command is also present from 1.7.8.11 and higher,
 424          * as well as 1.7.8.0
 425          */
 426         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 427                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 428                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 429                                         (11)))
 430                                 return 0;
 431                 }
 432         }
 433         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 434         req.fid = rte_cpu_to_le_16(fid);
 435
 436         req.vlan_tag_mask_tbl_addr =
 437                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 438         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 439
 440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 441
 442         HWRM_CHECK_RESULT();
 443         HWRM_UNLOCK();
 444
 445         return rc;
 446 }
 447
 448 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 449                              struct bnxt_filter_info *filter)
 450 {
 451         int rc = 0;
 452         struct bnxt_filter_info *l2_filter = filter;
 453         struct bnxt_vnic_info *vnic = NULL;
 454         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 455         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 456
 457         if (filter->fw_l2_filter_id == UINT64_MAX)
 458                 return 0;
 459
 460         if (filter->matching_l2_fltr_ptr)
 461                 l2_filter = filter->matching_l2_fltr_ptr;
 462
 463         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 464                     filter, l2_filter, l2_filter->l2_ref_cnt);
 465
 466         if (l2_filter->l2_ref_cnt == 0)
 467                 return 0;
 468
 469         if (l2_filter->l2_ref_cnt > 0)
 470                 l2_filter->l2_ref_cnt--;
 471
 472         if (l2_filter->l2_ref_cnt > 0)
 473                 return 0;
 474
 475         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 476
 477         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 478
 479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 480
 481         HWRM_CHECK_RESULT();
 482         HWRM_UNLOCK();
 483
 484         filter->fw_l2_filter_id = UINT64_MAX;
 485         if (l2_filter->l2_ref_cnt == 0) {
 486                 vnic = l2_filter->vnic;
 487                 if (vnic) {
 488                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 489                                       bnxt_filter_info, next);
 490                         bnxt_free_filter(bp, l2_filter);
 491                 }
 492         }
 493
 494         return 0;
 495 }
 496
 497 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 498                          uint16_t dst_id,
 499                          struct bnxt_filter_info *filter)
 500 {
 501         int rc = 0;
 502         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 503         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 504         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 505         const struct rte_eth_vmdq_rx_conf *conf =
 506                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 507         uint32_t enables = 0;
 508         uint16_t j = dst_id - 1;
 509
 510         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 511         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 512             conf->pool_map[j].pools & (1UL << j)) {
 513                 PMD_DRV_LOG(DEBUG,
 514                         "Add vlan %u to vmdq pool %u\n",
 515                         conf->pool_map[j].vlan_id, j);
 516
 517                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 518                 filter->enables |=
 519                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 520                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 521         }
 522
 523         if (filter->fw_l2_filter_id != UINT64_MAX)
 524                 bnxt_hwrm_clear_l2_filter(bp, filter);
 525
 526         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 527
 528         req.flags = rte_cpu_to_le_32(filter->flags);
 529
 530         enables = filter->enables |
 531               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 532         req.dst_id = rte_cpu_to_le_16(dst_id);
 533
 534         if (enables &
 535             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 536                 memcpy(req.l2_addr, filter->l2_addr,
 537                        RTE_ETHER_ADDR_LEN);
 538         if (enables &
 539             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 540                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 541                        RTE_ETHER_ADDR_LEN);
 542         if (enables &
 543             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 544                 req.l2_ovlan = filter->l2_ovlan;
 545         if (enables &
 546             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 547                 req.l2_ivlan = filter->l2_ivlan;
 548         if (enables &
 549             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 550                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 551         if (enables &
 552             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 553                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 554         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 555                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 556         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 557                 req.src_type = filter->src_type;
 558         if (filter->pri_hint) {
 559                 req.pri_hint = filter->pri_hint;
 560                 req.l2_filter_id_hint =
 561                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 562         }
 563
 564         req.enables = rte_cpu_to_le_32(enables);
 565
 566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 567
 568         HWRM_CHECK_RESULT();
 569
 570         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 571         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 572         HWRM_UNLOCK();
 573
 574         filter->l2_ref_cnt++;
 575
 576         return rc;
 577 }
 578
 579 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 580 {
 581         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 582         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 583         uint32_t flags = 0;
 584         int rc;
 585
 586         if (!ptp)
 587                 return 0;
 588
 589         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 590
 591         if (ptp->rx_filter)
 592                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 593         else
 594                 flags |=
 595                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 596         if (ptp->tx_tstamp_en)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 601         req.flags = rte_cpu_to_le_32(flags);
 602         req.enables = rte_cpu_to_le_32
 603                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 604         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 605
 606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 607         HWRM_UNLOCK();
 608
 609         return rc;
 610 }
 611
 612 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 613 {
 614         int rc = 0;
 615         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 616         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 617         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 618
 619         if (ptp)
 620                 return 0;
 621
 622         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 623
 624         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 625
 626         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 627
 628         HWRM_CHECK_RESULT();
 629
 630         if (!BNXT_CHIP_THOR(bp) &&
 631             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 632                 return 0;
 633
 634         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 635                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 636
 637         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 638         if (!ptp)
 639                 return -ENOMEM;
 640
 641         if (!BNXT_CHIP_THOR(bp)) {
 642                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 643                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 644                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 645                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 646                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 647                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 648                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 649                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 650                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 651                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 652                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 653                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 654                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 655                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 656                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 657                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 658                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 659                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 660         }
 661
 662         ptp->bp = bp;
 663         bp->ptp_cfg = ptp;
 664
 665         return 0;
 666 }
 667
 668 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 669 {
 670         int rc = 0;
 671         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 672         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 673         uint16_t new_max_vfs;
 674         uint32_t flags;
 675         int i;
 676
 677         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 678
 679         req.fid = rte_cpu_to_le_16(0xffff);
 680
 681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 682
 683         HWRM_CHECK_RESULT();
 684
 685         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 686         flags = rte_le_to_cpu_32(resp->flags);
 687         if (BNXT_PF(bp)) {
 688                 bp->pf.port_id = resp->port_id;
 689                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 690                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 691                 new_max_vfs = bp->pdev->max_vfs;
 692                 if (new_max_vfs != bp->pf.max_vfs) {
 693                         if (bp->pf.vf_info)
 694                                 rte_free(bp->pf.vf_info);
 695                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 696                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 697                         bp->pf.max_vfs = new_max_vfs;
 698                         for (i = 0; i < new_max_vfs; i++) {
 699                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 700                                 bp->pf.vf_info[i].vlan_table =
 701                                         rte_zmalloc("VF VLAN table",
 702                                                     getpagesize(),
 703                                                     getpagesize());
 704                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 705                                         PMD_DRV_LOG(ERR,
 706                                         "Fail to alloc VLAN table for VF %d\n",
 707                                         i);
 708                                 else
 709                                         rte_mem_lock_page(
 710                                                 bp->pf.vf_info[i].vlan_table);
 711                                 bp->pf.vf_info[i].vlan_as_table =
 712                                         rte_zmalloc("VF VLAN AS table",
 713                                                     getpagesize(),
 714                                                     getpagesize());
 715                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 716                                         PMD_DRV_LOG(ERR,
 717                                         "Alloc VLAN AS table for VF %d fail\n",
 718                                         i);
 719                                 else
 720                                         rte_mem_lock_page(
 721                                                bp->pf.vf_info[i].vlan_as_table);
 722                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 723                         }
 724                 }
 725         }
 726
 727         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 728         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 729         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 730         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 731         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 732         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 733         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 734         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 735         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 736         if (!BNXT_CHIP_THOR(bp))
 737                 bp->max_l2_ctx += bp->max_rx_em_flows;
 738         /* TODO: For now, do not support VMDq/RFS on VFs. */
 739         if (BNXT_PF(bp)) {
 740                 if (bp->pf.max_vfs)
 741                         bp->max_vnics = 1;
 742                 else
 743                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 744         } else {
 745                 bp->max_vnics = 1;
 746         }
 747         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 748         if (BNXT_PF(bp)) {
 749                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 750                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 751                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 752                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 753                         HWRM_UNLOCK();
 754                         bnxt_hwrm_ptp_qcfg(bp);
 755                 }
 756         }
 757
 758         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 759                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 760
 761         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 762                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 763                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 764         }
 765
 766         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 767                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 768
 769         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 770                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 771
 772         HWRM_UNLOCK();
 773
 774         return rc;
 775 }
 776
 777 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 778 {
 779         int rc;
 780
 781         rc = __bnxt_hwrm_func_qcaps(bp);
 782         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 783                 rc = bnxt_alloc_ctx_mem(bp);
 784                 if (rc)
 785                         return rc;
 786
 787                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 788                 if (!rc)
 789                         bp->flags |= BNXT_FLAG_NEW_RM;
 790         }
 791
 792         /* On older FW,
 793          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 794          * But the error can be ignored. Return success.
 795          */
 796
 797         return 0;
 798 }
 799
 800 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 801 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 802 {
 803         int rc = 0;
 804         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 805         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 806
 807         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 808
 809         req.target_id = rte_cpu_to_le_16(0xffff);
 810
 811         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 812
 813         HWRM_CHECK_RESULT();
 814
 815         if (rte_le_to_cpu_32(resp->flags) &
 816             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 817                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 818                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 819         }
 820
 821         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 822
 823         HWRM_UNLOCK();
 824
 825         return rc;
 826 }
 827
 828 int bnxt_hwrm_func_reset(struct bnxt *bp)
 829 {
 830         int rc = 0;
 831         struct hwrm_func_reset_input req = {.req_type = 0 };
 832         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 833
 834         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 835
 836         req.enables = rte_cpu_to_le_32(0);
 837
 838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 839
 840         HWRM_CHECK_RESULT();
 841         HWRM_UNLOCK();
 842
 843         return rc;
 844 }
 845
 846 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 847 {
 848         int rc;
 849         uint32_t flags = 0;
 850         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 851         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 852
 853         if (bp->flags & BNXT_FLAG_REGISTERED)
 854                 return 0;
 855
 856         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 857                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 858         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 859                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 860
 861         /* PFs and trusted VFs should indicate the support of the
 862          * Master capability on non Stingray platform
 863          */
 864         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 865                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 866
 867         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 868         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 869                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 870         req.ver_maj = RTE_VER_YEAR;
 871         req.ver_min = RTE_VER_MONTH;
 872         req.ver_upd = RTE_VER_MINOR;
 873
 874         if (BNXT_PF(bp)) {
 875                 req.enables |= rte_cpu_to_le_32(
 876                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 877                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 878                        RTE_MIN(sizeof(req.vf_req_fwd),
 879                                sizeof(bp->pf.vf_req_fwd)));
 880
 881                 /*
 882                  * PF can sniff HWRM API issued by VF. This can be set up by
 883                  * linux driver and inherited by the DPDK PF driver. Clear
 884                  * this HWRM sniffer list in FW because DPDK PF driver does
 885                  * not support this.
 886                  */
 887                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 888         }
 889
 890         req.flags = rte_cpu_to_le_32(flags);
 891
 892         req.async_event_fwd[0] |=
 893                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 894                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 895                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 896                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 897                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 898         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 899                 req.async_event_fwd[0] |=
 900                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 901         req.async_event_fwd[1] |=
 902                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 903                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 904         if (BNXT_PF(bp))
 905                 req.async_event_fwd[1] |=
 906                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 907
 908         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 909
 910         HWRM_CHECK_RESULT();
 911
 912         flags = rte_le_to_cpu_32(resp->flags);
 913         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 914                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 915
 916         HWRM_UNLOCK();
 917
 918         bp->flags |= BNXT_FLAG_REGISTERED;
 919
 920         return rc;
 921 }
 922
 923 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 924 {
 925         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 926                 return 0;
 927
 928         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 929 }
 930
 931 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 932 {
 933         int rc;
 934         uint32_t flags = 0;
 935         uint32_t enables;
 936         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 937         struct hwrm_func_vf_cfg_input req = {0};
 938
 939         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 940
 941         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 942                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 943                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 944                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 945                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 946
 947         if (BNXT_HAS_RING_GRPS(bp)) {
 948                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 949                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 950         }
 951
 952         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 953         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 954                                             AGG_RING_MULTIPLIER);
 955         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 956         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 957                                               bp->tx_nr_rings +
 958                                               BNXT_NUM_ASYNC_CPR(bp));
 959         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 960         if (bp->vf_resv_strategy ==
 961             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 962                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 963                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 964                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 965                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 966                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 967                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 968         } else if (bp->vf_resv_strategy ==
 969                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 970                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 971                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 972         }
 973
 974         if (test)
 975                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 976                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 977                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 978                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 979                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 980                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 981
 982         if (test && BNXT_HAS_RING_GRPS(bp))
 983                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 984
 985         req.flags = rte_cpu_to_le_32(flags);
 986         req.enables |= rte_cpu_to_le_32(enables);
 987
 988         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 989
 990         if (test)
 991                 HWRM_CHECK_RESULT_SILENT();
 992         else
 993                 HWRM_CHECK_RESULT();
 994
 995         HWRM_UNLOCK();
 996         return rc;
 997 }
 998
 999 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1000 {
1001         int rc;
1002         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1003         struct hwrm_func_resource_qcaps_input req = {0};
1004
1005         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1006         req.fid = rte_cpu_to_le_16(0xffff);
1007
1008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1009
1010         HWRM_CHECK_RESULT_SILENT();
1011
1012         if (BNXT_VF(bp)) {
1013                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1014                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1015                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1016                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1017                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1018                 /* func_resource_qcaps does not return max_rx_em_flows.
1019                  * So use the value provided by func_qcaps.
1020                  */
1021                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1022                 if (!BNXT_CHIP_THOR(bp))
1023                         bp->max_l2_ctx += bp->max_rx_em_flows;
1024                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1025                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1026         }
1027         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1028         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1029         if (bp->vf_resv_strategy >
1030             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1031                 bp->vf_resv_strategy =
1032                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1033
1034         HWRM_UNLOCK();
1035         return rc;
1036 }
1037
1038 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1039 {
1040         int rc = 0;
1041         struct hwrm_ver_get_input req = {.req_type = 0 };
1042         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1043         uint32_t fw_version;
1044         uint16_t max_resp_len;
1045         char type[RTE_MEMZONE_NAMESIZE];
1046         uint32_t dev_caps_cfg;
1047
1048         bp->max_req_len = HWRM_MAX_REQ_LEN;
1049         bp->hwrm_cmd_timeout = timeout;
1050         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1051
1052         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1053         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1054         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1055
1056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1057
1058         if (bp->flags & BNXT_FLAG_FW_RESET)
1059                 HWRM_CHECK_RESULT_SILENT();
1060         else
1061                 HWRM_CHECK_RESULT();
1062
1063         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1064                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1065                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1066                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1067         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1068                      (resp->hwrm_fw_min_8b << 16) |
1069                      (resp->hwrm_fw_bld_8b << 8) |
1070                      resp->hwrm_fw_rsvd_8b;
1071         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1072                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1073
1074         fw_version = resp->hwrm_intf_maj_8b << 16;
1075         fw_version |= resp->hwrm_intf_min_8b << 8;
1076         fw_version |= resp->hwrm_intf_upd_8b;
1077         bp->hwrm_spec_code = fw_version;
1078
1079         /* def_req_timeout value is in milliseconds */
1080         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1081         /* convert timeout to usec */
1082         bp->hwrm_cmd_timeout *= 1000;
1083         if (!bp->hwrm_cmd_timeout)
1084                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1085
1086         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1087                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1088                 rc = -EINVAL;
1089                 goto error;
1090         }
1091
1092         if (bp->max_req_len > resp->max_req_win_len) {
1093                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1094                 rc = -EINVAL;
1095         }
1096         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1097         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1098         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1099                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1100
1101         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1102         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1103
1104         if (bp->max_resp_len != max_resp_len) {
1105                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
1106                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1107                         bp->pdev->addr.devid, bp->pdev->addr.function);
1108
1109                 rte_free(bp->hwrm_cmd_resp_addr);
1110
1111                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1112                 if (bp->hwrm_cmd_resp_addr == NULL) {
1113                         rc = -ENOMEM;
1114                         goto error;
1115                 }
1116                 bp->hwrm_cmd_resp_dma_addr =
1117                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1118                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1119                         PMD_DRV_LOG(ERR,
1120                         "Unable to map response buffer to physical memory.\n");
1121                         rc = -ENOMEM;
1122                         goto error;
1123                 }
1124                 bp->max_resp_len = max_resp_len;
1125         }
1126
1127         if ((dev_caps_cfg &
1128                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1129             (dev_caps_cfg &
1130              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1131                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1132                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1133         }
1134
1135         if (((dev_caps_cfg &
1136               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1137              (dev_caps_cfg &
1138               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1139             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1140                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1141                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1142                         bp->pdev->addr.devid, bp->pdev->addr.function);
1143
1144                 rte_free(bp->hwrm_short_cmd_req_addr);
1145
1146                 bp->hwrm_short_cmd_req_addr =
1147                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1148                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1149                         rc = -ENOMEM;
1150                         goto error;
1151                 }
1152                 bp->hwrm_short_cmd_req_dma_addr =
1153                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1154                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1155                         rte_free(bp->hwrm_short_cmd_req_addr);
1156                         PMD_DRV_LOG(ERR,
1157                                 "Unable to map buffer to physical memory.\n");
1158                         rc = -ENOMEM;
1159                         goto error;
1160                 }
1161         }
1162         if (dev_caps_cfg &
1163             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1164                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1165                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1166         }
1167         if (dev_caps_cfg &
1168             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1169                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1170         if (dev_caps_cfg &
1171             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1172                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1173                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1174         }
1175
1176 error:
1177         HWRM_UNLOCK();
1178         return rc;
1179 }
1180
1181 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1182 {
1183         int rc;
1184         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1185         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1186
1187         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1188                 return 0;
1189
1190         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1191         req.flags = flags;
1192
1193         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1194
1195         HWRM_CHECK_RESULT();
1196         HWRM_UNLOCK();
1197
1198         return rc;
1199 }
1200
1201 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1202 {
1203         int rc = 0;
1204         struct hwrm_port_phy_cfg_input req = {0};
1205         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1206         uint32_t enables = 0;
1207
1208         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1209
1210         if (conf->link_up) {
1211                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1212                 if (bp->link_info.auto_mode && conf->link_speed) {
1213                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1214                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1215                 }
1216
1217                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1218                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1219                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1220                 /*
1221                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1222                  * any auto mode, even "none".
1223                  */
1224                 if (!conf->link_speed) {
1225                         /* No speeds specified. Enable AutoNeg - all speeds */
1226                         req.auto_mode =
1227                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1228                 }
1229                 /* AutoNeg - Advertise speeds specified. */
1230                 if (conf->auto_link_speed_mask &&
1231                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1232                         req.auto_mode =
1233                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1234                         req.auto_link_speed_mask =
1235                                 conf->auto_link_speed_mask;
1236                         enables |=
1237                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1238                 }
1239
1240                 req.auto_duplex = conf->duplex;
1241                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1242                 req.auto_pause = conf->auto_pause;
1243                 req.force_pause = conf->force_pause;
1244                 /* Set force_pause if there is no auto or if there is a force */
1245                 if (req.auto_pause && !req.force_pause)
1246                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1247                 else
1248                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1249
1250                 req.enables = rte_cpu_to_le_32(enables);
1251         } else {
1252                 req.flags =
1253                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1254                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1255         }
1256
1257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1258
1259         HWRM_CHECK_RESULT();
1260         HWRM_UNLOCK();
1261
1262         return rc;
1263 }
1264
1265 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1266                                    struct bnxt_link_info *link_info)
1267 {
1268         int rc = 0;
1269         struct hwrm_port_phy_qcfg_input req = {0};
1270         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1271
1272         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1273
1274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1275
1276         HWRM_CHECK_RESULT();
1277
1278         link_info->phy_link_status = resp->link;
1279         link_info->link_up =
1280                 (link_info->phy_link_status ==
1281                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1282         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1283         link_info->duplex = resp->duplex_cfg;
1284         link_info->pause = resp->pause;
1285         link_info->auto_pause = resp->auto_pause;
1286         link_info->force_pause = resp->force_pause;
1287         link_info->auto_mode = resp->auto_mode;
1288         link_info->phy_type = resp->phy_type;
1289         link_info->media_type = resp->media_type;
1290
1291         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1292         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1293         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1294         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1295         link_info->phy_ver[0] = resp->phy_maj;
1296         link_info->phy_ver[1] = resp->phy_min;
1297         link_info->phy_ver[2] = resp->phy_bld;
1298
1299         HWRM_UNLOCK();
1300
1301         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1302         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1303         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1304         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1305         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1306                     link_info->auto_link_speed_mask);
1307         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1308                     link_info->force_link_speed);
1309
1310         return rc;
1311 }
1312
1313 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1314 {
1315         int i = 0;
1316
1317         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1318                 if (bp->tx_cos_queue[i].profile ==
1319                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1320                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1321                         return true;
1322                 }
1323         }
1324         return false;
1325 }
1326
1327 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1328 {
1329         int i = 0;
1330
1331         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1332                 if (bp->tx_cos_queue[i].profile !=
1333                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1334                     bp->tx_cos_queue[i].id !=
1335                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1336                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1337                         break;
1338                 }
1339         }
1340 }
1341
1342 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1343 {
1344         int rc = 0;
1345         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1346         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1347         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1348         int i;
1349
1350 get_rx_info:
1351         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1352
1353         req.flags = rte_cpu_to_le_32(dir);
1354         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1355         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1356             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1357                 req.drv_qmap_cap =
1358                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1360
1361         HWRM_CHECK_RESULT();
1362
1363         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1364                 GET_TX_QUEUE_INFO(0);
1365                 GET_TX_QUEUE_INFO(1);
1366                 GET_TX_QUEUE_INFO(2);
1367                 GET_TX_QUEUE_INFO(3);
1368                 GET_TX_QUEUE_INFO(4);
1369                 GET_TX_QUEUE_INFO(5);
1370                 GET_TX_QUEUE_INFO(6);
1371                 GET_TX_QUEUE_INFO(7);
1372         } else  {
1373                 GET_RX_QUEUE_INFO(0);
1374                 GET_RX_QUEUE_INFO(1);
1375                 GET_RX_QUEUE_INFO(2);
1376                 GET_RX_QUEUE_INFO(3);
1377                 GET_RX_QUEUE_INFO(4);
1378                 GET_RX_QUEUE_INFO(5);
1379                 GET_RX_QUEUE_INFO(6);
1380                 GET_RX_QUEUE_INFO(7);
1381         }
1382
1383         HWRM_UNLOCK();
1384
1385         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1386                 goto done;
1387
1388         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1389                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1390         } else {
1391                 int j;
1392
1393                 /* iterate and find the COSq profile to use for Tx */
1394                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1395                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1396                                 if (bp->tx_cos_queue[i].id != 0xff)
1397                                         bp->tx_cosq_id[j++] =
1398                                                 bp->tx_cos_queue[i].id;
1399                         }
1400                 } else {
1401                         /* When CoS classification is disabled, for normal NIC
1402                          * operations, ideally we should look to use LOSSY.
1403                          * If not found, fallback to the first valid profile
1404                          */
1405                         if (!bnxt_find_lossy_profile(bp))
1406                                 bnxt_find_first_valid_profile(bp);
1407
1408                 }
1409         }
1410
1411         bp->max_tc = resp->max_configurable_queues;
1412         bp->max_lltc = resp->max_configurable_lossless_queues;
1413         if (bp->max_tc > BNXT_MAX_QUEUE)
1414                 bp->max_tc = BNXT_MAX_QUEUE;
1415         bp->max_q = bp->max_tc;
1416
1417         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1418                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1419                 goto get_rx_info;
1420         }
1421
1422 done:
1423         return rc;
1424 }
1425
1426 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1427                          struct bnxt_ring *ring,
1428                          uint32_t ring_type, uint32_t map_index,
1429                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1430                          uint16_t tx_cosq_id)
1431 {
1432         int rc = 0;
1433         uint32_t enables = 0;
1434         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1435         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1436         struct rte_mempool *mb_pool;
1437         uint16_t rx_buf_size;
1438
1439         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1440
1441         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1442         req.fbo = rte_cpu_to_le_32(0);
1443         /* Association of ring index with doorbell index */
1444         req.logical_id = rte_cpu_to_le_16(map_index);
1445         req.length = rte_cpu_to_le_32(ring->ring_size);
1446
1447         switch (ring_type) {
1448         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1449                 req.ring_type = ring_type;
1450                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1451                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1452                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1453                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1454                         enables |=
1455                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1456                 break;
1457         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1458                 req.ring_type = ring_type;
1459                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1460                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1461                 if (BNXT_CHIP_THOR(bp)) {
1462                         mb_pool = bp->rx_queues[0]->mb_pool;
1463                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1464                                       RTE_PKTMBUF_HEADROOM;
1465                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1466                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1467                         enables |=
1468                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1469                 }
1470                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1471                         enables |=
1472                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1473                 break;
1474         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1475                 req.ring_type = ring_type;
1476                 if (BNXT_HAS_NQ(bp)) {
1477                         /* Association of cp ring with nq */
1478                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1479                         enables |=
1480                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1481                 }
1482                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1483                 break;
1484         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1485                 req.ring_type = ring_type;
1486                 req.page_size = BNXT_PAGE_SHFT;
1487                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1488                 break;
1489         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1490                 req.ring_type = ring_type;
1491                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1492
1493                 mb_pool = bp->rx_queues[0]->mb_pool;
1494                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1495                               RTE_PKTMBUF_HEADROOM;
1496                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1497                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1498
1499                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1500                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1501                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1502                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1503                 break;
1504         default:
1505                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1506                         ring_type);
1507                 HWRM_UNLOCK();
1508                 return -EINVAL;
1509         }
1510         req.enables = rte_cpu_to_le_32(enables);
1511
1512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1513
1514         if (rc || resp->error_code) {
1515                 if (rc == 0 && resp->error_code)
1516                         rc = rte_le_to_cpu_16(resp->error_code);
1517                 switch (ring_type) {
1518                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1519                         PMD_DRV_LOG(ERR,
1520                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1521                         HWRM_UNLOCK();
1522                         return rc;
1523                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1524                         PMD_DRV_LOG(ERR,
1525                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1526                         HWRM_UNLOCK();
1527                         return rc;
1528                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1529                         PMD_DRV_LOG(ERR,
1530                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1531                                     rc);
1532                         HWRM_UNLOCK();
1533                         return rc;
1534                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1535                         PMD_DRV_LOG(ERR,
1536                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1537                         HWRM_UNLOCK();
1538                         return rc;
1539                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1540                         PMD_DRV_LOG(ERR,
1541                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1542                         HWRM_UNLOCK();
1543                         return rc;
1544                 default:
1545                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1546                         HWRM_UNLOCK();
1547                         return rc;
1548                 }
1549         }
1550
1551         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1552         HWRM_UNLOCK();
1553         return rc;
1554 }
1555
1556 int bnxt_hwrm_ring_free(struct bnxt *bp,
1557                         struct bnxt_ring *ring, uint32_t ring_type)
1558 {
1559         int rc;
1560         struct hwrm_ring_free_input req = {.req_type = 0 };
1561         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1562
1563         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1564
1565         req.ring_type = ring_type;
1566         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1567
1568         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1569
1570         if (rc || resp->error_code) {
1571                 if (rc == 0 && resp->error_code)
1572                         rc = rte_le_to_cpu_16(resp->error_code);
1573                 HWRM_UNLOCK();
1574
1575                 switch (ring_type) {
1576                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1577                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1578                                 rc);
1579                         return rc;
1580                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1581                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1582                                 rc);
1583                         return rc;
1584                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1585                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1586                                 rc);
1587                         return rc;
1588                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1589                         PMD_DRV_LOG(ERR,
1590                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1591                         return rc;
1592                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1593                         PMD_DRV_LOG(ERR,
1594                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1595                         return rc;
1596                 default:
1597                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1598                         return rc;
1599                 }
1600         }
1601         HWRM_UNLOCK();
1602         return 0;
1603 }
1604
1605 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1606 {
1607         int rc = 0;
1608         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1609         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1610
1611         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1612
1613         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1614         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1615         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1616         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1617
1618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619
1620         HWRM_CHECK_RESULT();
1621
1622         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1623
1624         HWRM_UNLOCK();
1625
1626         return rc;
1627 }
1628
1629 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1630 {
1631         int rc;
1632         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1633         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1634
1635         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1636
1637         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1638
1639         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1640
1641         HWRM_CHECK_RESULT();
1642         HWRM_UNLOCK();
1643
1644         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1645         return rc;
1646 }
1647
1648 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1649 {
1650         int rc = 0;
1651         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1652         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1653
1654         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1655                 return rc;
1656
1657         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1658
1659         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1660
1661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1662
1663         HWRM_CHECK_RESULT();
1664         HWRM_UNLOCK();
1665
1666         return rc;
1667 }
1668
1669 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1670                                 unsigned int idx __rte_unused)
1671 {
1672         int rc;
1673         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1674         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1675
1676         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1677
1678         req.update_period_ms = rte_cpu_to_le_32(0);
1679
1680         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1681
1682         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683
1684         HWRM_CHECK_RESULT();
1685
1686         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1687
1688         HWRM_UNLOCK();
1689
1690         return rc;
1691 }
1692
1693 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1694                                 unsigned int idx __rte_unused)
1695 {
1696         int rc;
1697         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1698         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1699
1700         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1701
1702         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1703
1704         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1705
1706         HWRM_CHECK_RESULT();
1707         HWRM_UNLOCK();
1708
1709         return rc;
1710 }
1711
1712 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1713 {
1714         int rc = 0, i, j;
1715         struct hwrm_vnic_alloc_input req = { 0 };
1716         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1717
1718         if (!BNXT_HAS_RING_GRPS(bp))
1719                 goto skip_ring_grps;
1720
1721         /* map ring groups to this vnic */
1722         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1723                 vnic->start_grp_id, vnic->end_grp_id);
1724         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1725                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1726
1727         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1728         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1729         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1730         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1731
1732 skip_ring_grps:
1733         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1734         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1735
1736         if (vnic->func_default)
1737                 req.flags =
1738                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1739         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1740
1741         HWRM_CHECK_RESULT();
1742
1743         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1744         HWRM_UNLOCK();
1745         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1746         return rc;
1747 }
1748
1749 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1750                                         struct bnxt_vnic_info *vnic,
1751                                         struct bnxt_plcmodes_cfg *pmode)
1752 {
1753         int rc = 0;
1754         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1755         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1756
1757         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1758
1759         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1760
1761         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1762
1763         HWRM_CHECK_RESULT();
1764
1765         pmode->flags = rte_le_to_cpu_32(resp->flags);
1766         /* dflt_vnic bit doesn't exist in the _cfg command */
1767         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1768         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1769         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1770         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1771
1772         HWRM_UNLOCK();
1773
1774         return rc;
1775 }
1776
1777 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1778                                        struct bnxt_vnic_info *vnic,
1779                                        struct bnxt_plcmodes_cfg *pmode)
1780 {
1781         int rc = 0;
1782         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1783         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1784
1785         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1786                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1787                 return rc;
1788         }
1789
1790         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1791
1792         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1793         req.flags = rte_cpu_to_le_32(pmode->flags);
1794         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1795         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1796         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1797         req.enables = rte_cpu_to_le_32(
1798             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1799             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1800             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1801         );
1802
1803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1804
1805         HWRM_CHECK_RESULT();
1806         HWRM_UNLOCK();
1807
1808         return rc;
1809 }
1810
1811 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1812 {
1813         int rc = 0;
1814         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1815         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1816         struct bnxt_plcmodes_cfg pmodes = { 0 };
1817         uint32_t ctx_enable_flag = 0;
1818         uint32_t enables = 0;
1819
1820         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1821                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1822                 return rc;
1823         }
1824
1825         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1826         if (rc)
1827                 return rc;
1828
1829         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1830
1831         if (BNXT_CHIP_THOR(bp)) {
1832                 int dflt_rxq = vnic->start_grp_id;
1833                 struct bnxt_rx_ring_info *rxr;
1834                 struct bnxt_cp_ring_info *cpr;
1835                 struct bnxt_rx_queue *rxq;
1836                 int i;
1837
1838                 /*
1839                  * The first active receive ring is used as the VNIC
1840                  * default receive ring. If there are no active receive
1841                  * rings (all corresponding receive queues are stopped),
1842                  * the first receive ring is used.
1843                  */
1844                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1845                         rxq = bp->eth_dev->data->rx_queues[i];
1846                         if (rxq->rx_started) {
1847                                 dflt_rxq = i;
1848                                 break;
1849                         }
1850                 }
1851
1852                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1853                 rxr = rxq->rx_ring;
1854                 cpr = rxq->cp_ring;
1855
1856                 req.default_rx_ring_id =
1857                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1858                 req.default_cmpl_ring_id =
1859                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1860                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1861                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1862                 goto config_mru;
1863         }
1864
1865         /* Only RSS support for now TBD: COS & LB */
1866         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1867         if (vnic->lb_rule != 0xffff)
1868                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1869         if (vnic->cos_rule != 0xffff)
1870                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1871         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1872                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1873                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1874         }
1875         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1876                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1877                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1878         }
1879
1880         enables |= ctx_enable_flag;
1881         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1882         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1883         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1884         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1885
1886 config_mru:
1887         req.enables = rte_cpu_to_le_32(enables);
1888         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1889         req.mru = rte_cpu_to_le_16(vnic->mru);
1890         /* Configure default VNIC only once. */
1891         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1892                 req.flags |=
1893                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1894                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1895         }
1896         if (vnic->vlan_strip)
1897                 req.flags |=
1898                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1899         if (vnic->bd_stall)
1900                 req.flags |=
1901                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1902         if (vnic->roce_dual)
1903                 req.flags |= rte_cpu_to_le_32(
1904                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1905         if (vnic->roce_only)
1906                 req.flags |= rte_cpu_to_le_32(
1907                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1908         if (vnic->rss_dflt_cr)
1909                 req.flags |= rte_cpu_to_le_32(
1910                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1911
1912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1913
1914         HWRM_CHECK_RESULT();
1915         HWRM_UNLOCK();
1916
1917         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1918
1919         return rc;
1920 }
1921
1922 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1923                 int16_t fw_vf_id)
1924 {
1925         int rc = 0;
1926         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1927         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1928
1929         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1930                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1931                 return rc;
1932         }
1933         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1934
1935         req.enables =
1936                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1937         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1938         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1939
1940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1941
1942         HWRM_CHECK_RESULT();
1943
1944         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1945         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1946         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1947         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1948         vnic->mru = rte_le_to_cpu_16(resp->mru);
1949         vnic->func_default = rte_le_to_cpu_32(
1950                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1951         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1952                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1953         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1954                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1955         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1956                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1957         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1958                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1959         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1960                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1961
1962         HWRM_UNLOCK();
1963
1964         return rc;
1965 }
1966
1967 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1968                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1969 {
1970         int rc = 0;
1971         uint16_t ctx_id;
1972         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1973         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1974                                                 bp->hwrm_cmd_resp_addr;
1975
1976         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1977
1978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1979         HWRM_CHECK_RESULT();
1980
1981         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1982         if (!BNXT_HAS_RING_GRPS(bp))
1983                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1984         else if (ctx_idx == 0)
1985                 vnic->rss_rule = ctx_id;
1986
1987         HWRM_UNLOCK();
1988
1989         return rc;
1990 }
1991
1992 static
1993 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1994                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1995 {
1996         int rc = 0;
1997         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1998         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1999                                                 bp->hwrm_cmd_resp_addr;
2000
2001         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2002                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2003                 return rc;
2004         }
2005         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2006
2007         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2008
2009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2010
2011         HWRM_CHECK_RESULT();
2012         HWRM_UNLOCK();
2013
2014         return rc;
2015 }
2016
2017 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2018 {
2019         int rc = 0;
2020
2021         if (BNXT_CHIP_THOR(bp)) {
2022                 int j;
2023
2024                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2025                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2026                                                       vnic,
2027                                                       vnic->fw_grp_ids[j]);
2028                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2029                 }
2030                 vnic->num_lb_ctxts = 0;
2031         } else {
2032                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2033                 vnic->rss_rule = INVALID_HW_RING_ID;
2034         }
2035
2036         return rc;
2037 }
2038
2039 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2040 {
2041         int rc = 0;
2042         struct hwrm_vnic_free_input req = {.req_type = 0 };
2043         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2044
2045         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2046                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2047                 return rc;
2048         }
2049
2050         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2051
2052         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057         HWRM_UNLOCK();
2058
2059         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2060         /* Configure default VNIC again if necessary. */
2061         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2062                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2063
2064         return rc;
2065 }
2066
2067 static int
2068 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2069 {
2070         int i;
2071         int rc = 0;
2072         int nr_ctxs = vnic->num_lb_ctxts;
2073         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2074         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2075
2076         for (i = 0; i < nr_ctxs; i++) {
2077                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2078
2079                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2080                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2081                 req.hash_mode_flags = vnic->hash_mode;
2082
2083                 req.hash_key_tbl_addr =
2084                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2085
2086                 req.ring_grp_tbl_addr =
2087                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2088                                          i * HW_HASH_INDEX_SIZE);
2089                 req.ring_table_pair_index = i;
2090                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2091
2092                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2093                                             BNXT_USE_CHIMP_MB);
2094
2095                 HWRM_CHECK_RESULT();
2096                 HWRM_UNLOCK();
2097         }
2098
2099         return rc;
2100 }
2101
2102 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2103                            struct bnxt_vnic_info *vnic)
2104 {
2105         int rc = 0;
2106         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2107         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2108
2109         if (!vnic->rss_table)
2110                 return 0;
2111
2112         if (BNXT_CHIP_THOR(bp))
2113                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2114
2115         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2116
2117         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2118         req.hash_mode_flags = vnic->hash_mode;
2119
2120         req.ring_grp_tbl_addr =
2121             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2122         req.hash_key_tbl_addr =
2123             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2124         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2125         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2126
2127         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2128
2129         HWRM_CHECK_RESULT();
2130         HWRM_UNLOCK();
2131
2132         return rc;
2133 }
2134
2135 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2136                         struct bnxt_vnic_info *vnic)
2137 {
2138         int rc = 0;
2139         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2140         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2141         uint16_t size;
2142
2143         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2144                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2145                 return rc;
2146         }
2147
2148         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2149
2150         req.flags = rte_cpu_to_le_32(
2151                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2152
2153         req.enables = rte_cpu_to_le_32(
2154                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2155
2156         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2157         size -= RTE_PKTMBUF_HEADROOM;
2158         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2159
2160         req.jumbo_thresh = rte_cpu_to_le_16(size);
2161         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2162
2163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2164
2165         HWRM_CHECK_RESULT();
2166         HWRM_UNLOCK();
2167
2168         return rc;
2169 }
2170
2171 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2172                         struct bnxt_vnic_info *vnic, bool enable)
2173 {
2174         int rc = 0;
2175         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2176         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2177
2178         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2179                 if (enable)
2180                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2181                 return -ENOTSUP;
2182         }
2183
2184         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2185                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2186                 return 0;
2187         }
2188
2189         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2190
2191         if (enable) {
2192                 req.enables = rte_cpu_to_le_32(
2193                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2194                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2195                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2196                 req.flags = rte_cpu_to_le_32(
2197                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2198                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2199                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2200                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2201                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2202                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2203                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2204                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2205                 req.min_agg_len = rte_cpu_to_le_32(512);
2206         }
2207         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2208
2209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2210
2211         HWRM_CHECK_RESULT();
2212         HWRM_UNLOCK();
2213
2214         return rc;
2215 }
2216
2217 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2218 {
2219         struct hwrm_func_cfg_input req = {0};
2220         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2221         int rc;
2222
2223         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2224         req.enables = rte_cpu_to_le_32(
2225                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2226         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2227         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2228
2229         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2230
2231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2232         HWRM_CHECK_RESULT();
2233         HWRM_UNLOCK();
2234
2235         bp->pf.vf_info[vf].random_mac = false;
2236
2237         return rc;
2238 }
2239
2240 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2241                                   uint64_t *dropped)
2242 {
2243         int rc = 0;
2244         struct hwrm_func_qstats_input req = {.req_type = 0};
2245         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2246
2247         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2248
2249         req.fid = rte_cpu_to_le_16(fid);
2250
2251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252
2253         HWRM_CHECK_RESULT();
2254
2255         if (dropped)
2256                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2257
2258         HWRM_UNLOCK();
2259
2260         return rc;
2261 }
2262
2263 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2264                           struct rte_eth_stats *stats,
2265                           struct hwrm_func_qstats_output *func_qstats)
2266 {
2267         int rc = 0;
2268         struct hwrm_func_qstats_input req = {.req_type = 0};
2269         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2270
2271         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2272
2273         req.fid = rte_cpu_to_le_16(fid);
2274
2275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2276
2277         HWRM_CHECK_RESULT();
2278         if (func_qstats)
2279                 memcpy(func_qstats, resp,
2280                        sizeof(struct hwrm_func_qstats_output));
2281
2282         if (!stats)
2283                 goto exit;
2284
2285         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2286         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2287         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2288         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2289         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2290         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2291
2292         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2293         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2294         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2295         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2296         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2297         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2298
2299         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2300         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2301         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2302
2303 exit:
2304         HWRM_UNLOCK();
2305
2306         return rc;
2307 }
2308
2309 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2310 {
2311         int rc = 0;
2312         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2313         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2314
2315         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2316
2317         req.fid = rte_cpu_to_le_16(fid);
2318
2319         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2320
2321         HWRM_CHECK_RESULT();
2322         HWRM_UNLOCK();
2323
2324         return rc;
2325 }
2326
2327 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2328 {
2329         unsigned int i;
2330         int rc = 0;
2331
2332         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2333                 struct bnxt_tx_queue *txq;
2334                 struct bnxt_rx_queue *rxq;
2335                 struct bnxt_cp_ring_info *cpr;
2336
2337                 if (i >= bp->rx_cp_nr_rings) {
2338                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2339                         cpr = txq->cp_ring;
2340                 } else {
2341                         rxq = bp->rx_queues[i];
2342                         cpr = rxq->cp_ring;
2343                 }
2344
2345                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2346                 if (rc)
2347                         return rc;
2348         }
2349         return 0;
2350 }
2351
2352 static int
2353 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2354 {
2355         int rc;
2356         unsigned int i;
2357         struct bnxt_cp_ring_info *cpr;
2358
2359         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2360
2361                 if (i >= bp->rx_cp_nr_rings) {
2362                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2363                 } else {
2364                         cpr = bp->rx_queues[i]->cp_ring;
2365                         if (BNXT_HAS_RING_GRPS(bp))
2366                                 bp->grp_info[i].fw_stats_ctx = -1;
2367                 }
2368                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2369                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2370                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2371                         if (rc)
2372                                 return rc;
2373                 }
2374         }
2375         return 0;
2376 }
2377
2378 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2379 {
2380         unsigned int i;
2381         int rc = 0;
2382
2383         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2384                 struct bnxt_tx_queue *txq;
2385                 struct bnxt_rx_queue *rxq;
2386                 struct bnxt_cp_ring_info *cpr;
2387
2388                 if (i >= bp->rx_cp_nr_rings) {
2389                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2390                         cpr = txq->cp_ring;
2391                 } else {
2392                         rxq = bp->rx_queues[i];
2393                         cpr = rxq->cp_ring;
2394                 }
2395
2396                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2397
2398                 if (rc)
2399                         return rc;
2400         }
2401         return rc;
2402 }
2403
2404 static int
2405 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2406 {
2407         uint16_t idx;
2408         uint32_t rc = 0;
2409
2410         if (!BNXT_HAS_RING_GRPS(bp))
2411                 return 0;
2412
2413         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2414
2415                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2416                         continue;
2417
2418                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2419
2420                 if (rc)
2421                         return rc;
2422         }
2423         return rc;
2424 }
2425
2426 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2427 {
2428         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2429
2430         bnxt_hwrm_ring_free(bp, cp_ring,
2431                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2432         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2433         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2434                                      sizeof(*cpr->cp_desc_ring));
2435         cpr->cp_raw_cons = 0;
2436         cpr->valid = 0;
2437 }
2438
2439 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2440 {
2441         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2442
2443         bnxt_hwrm_ring_free(bp, cp_ring,
2444                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2445         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2446         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2447                         sizeof(*cpr->cp_desc_ring));
2448         cpr->cp_raw_cons = 0;
2449         cpr->valid = 0;
2450 }
2451
2452 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2453 {
2454         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2455         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2456         struct bnxt_ring *ring = rxr->rx_ring_struct;
2457         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2458
2459         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2460                 bnxt_hwrm_ring_free(bp, ring,
2461                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2462                 ring->fw_ring_id = INVALID_HW_RING_ID;
2463                 if (BNXT_HAS_RING_GRPS(bp))
2464                         bp->grp_info[queue_index].rx_fw_ring_id =
2465                                                         INVALID_HW_RING_ID;
2466                 memset(rxr->rx_desc_ring, 0,
2467                        rxr->rx_ring_struct->ring_size *
2468                        sizeof(*rxr->rx_desc_ring));
2469                 memset(rxr->rx_buf_ring, 0,
2470                        rxr->rx_ring_struct->ring_size *
2471                        sizeof(*rxr->rx_buf_ring));
2472                 rxr->rx_prod = 0;
2473         }
2474         ring = rxr->ag_ring_struct;
2475         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2476                 bnxt_hwrm_ring_free(bp, ring,
2477                                     BNXT_CHIP_THOR(bp) ?
2478                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2479                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2480                 ring->fw_ring_id = INVALID_HW_RING_ID;
2481                 memset(rxr->ag_buf_ring, 0,
2482                        rxr->ag_ring_struct->ring_size *
2483                        sizeof(*rxr->ag_buf_ring));
2484                 rxr->ag_prod = 0;
2485                 if (BNXT_HAS_RING_GRPS(bp))
2486                         bp->grp_info[queue_index].ag_fw_ring_id =
2487                                                         INVALID_HW_RING_ID;
2488         }
2489         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2490                 bnxt_free_cp_ring(bp, cpr);
2491
2492         if (BNXT_HAS_RING_GRPS(bp))
2493                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2494 }
2495
2496 static int
2497 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2498 {
2499         unsigned int i;
2500
2501         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2502                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2503                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2504                 struct bnxt_ring *ring = txr->tx_ring_struct;
2505                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2506
2507                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2508                         bnxt_hwrm_ring_free(bp, ring,
2509                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2510                         ring->fw_ring_id = INVALID_HW_RING_ID;
2511                         memset(txr->tx_desc_ring, 0,
2512                                         txr->tx_ring_struct->ring_size *
2513                                         sizeof(*txr->tx_desc_ring));
2514                         memset(txr->tx_buf_ring, 0,
2515                                         txr->tx_ring_struct->ring_size *
2516                                         sizeof(*txr->tx_buf_ring));
2517                         txr->tx_prod = 0;
2518                         txr->tx_cons = 0;
2519                 }
2520                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2521                         bnxt_free_cp_ring(bp, cpr);
2522                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2523                 }
2524         }
2525
2526         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2527                 bnxt_free_hwrm_rx_ring(bp, i);
2528
2529         return 0;
2530 }
2531
2532 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2533 {
2534         uint16_t i;
2535         uint32_t rc = 0;
2536
2537         if (!BNXT_HAS_RING_GRPS(bp))
2538                 return 0;
2539
2540         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2541                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2542                 if (rc)
2543                         return rc;
2544         }
2545         return rc;
2546 }
2547
2548 /*
2549  * HWRM utility functions
2550  */
2551
2552 void bnxt_free_hwrm_resources(struct bnxt *bp)
2553 {
2554         /* Release memzone */
2555         rte_free(bp->hwrm_cmd_resp_addr);
2556         rte_free(bp->hwrm_short_cmd_req_addr);
2557         bp->hwrm_cmd_resp_addr = NULL;
2558         bp->hwrm_short_cmd_req_addr = NULL;
2559         bp->hwrm_cmd_resp_dma_addr = 0;
2560         bp->hwrm_short_cmd_req_dma_addr = 0;
2561 }
2562
2563 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2564 {
2565         struct rte_pci_device *pdev = bp->pdev;
2566         char type[RTE_MEMZONE_NAMESIZE];
2567
2568         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2569                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2570         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2571         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2572         if (bp->hwrm_cmd_resp_addr == NULL)
2573                 return -ENOMEM;
2574         bp->hwrm_cmd_resp_dma_addr =
2575                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2576         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2577                 PMD_DRV_LOG(ERR,
2578                         "unable to map response address to physical memory\n");
2579                 return -ENOMEM;
2580         }
2581         rte_spinlock_init(&bp->hwrm_lock);
2582
2583         return 0;
2584 }
2585
2586 static int
2587 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2588 {
2589         struct bnxt_filter_info *filter;
2590         int rc = 0;
2591
2592         STAILQ_FOREACH(filter, &vnic->filter, next) {
2593                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2594                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2595                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2596                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2597                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2598                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2599                 bnxt_free_filter(bp, filter);
2600         }
2601         return rc;
2602 }
2603
2604 static int
2605 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2606 {
2607         struct bnxt_filter_info *filter;
2608         struct rte_flow *flow;
2609         int rc = 0;
2610
2611         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2612                 flow = STAILQ_FIRST(&vnic->flow_list);
2613                 filter = flow->filter;
2614                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2615                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2616                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2617                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2618                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2619                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2620
2621                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2622                 rte_free(flow);
2623         }
2624         return rc;
2625 }
2626
2627 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2628 {
2629         struct bnxt_filter_info *filter;
2630         int rc = 0;
2631
2632         STAILQ_FOREACH(filter, &vnic->filter, next) {
2633                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2634                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2635                                                      filter);
2636                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2637                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2638                                                          filter);
2639                 else
2640                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2641                                                      filter);
2642                 if (rc)
2643                         break;
2644         }
2645         return rc;
2646 }
2647
2648 static void
2649 bnxt_free_tunnel_ports(struct bnxt *bp)
2650 {
2651         if (bp->vxlan_port_cnt)
2652                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2653                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2654         bp->vxlan_port = 0;
2655         if (bp->geneve_port_cnt)
2656                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2657                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2658         bp->geneve_port = 0;
2659 }
2660
2661 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2662 {
2663         int i;
2664
2665         if (bp->vnic_info == NULL)
2666                 return;
2667
2668         /*
2669          * Cleanup VNICs in reverse order, to make sure the L2 filter
2670          * from vnic0 is last to be cleaned up.
2671          */
2672         for (i = bp->max_vnics - 1; i >= 0; i--) {
2673                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2674
2675                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2676                         continue;
2677
2678                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2679
2680                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2681
2682                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2683
2684                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2685
2686                 bnxt_hwrm_vnic_free(bp, vnic);
2687
2688                 rte_free(vnic->fw_grp_ids);
2689         }
2690         /* Ring resources */
2691         bnxt_free_all_hwrm_rings(bp);
2692         bnxt_free_all_hwrm_ring_grps(bp);
2693         bnxt_free_all_hwrm_stat_ctxs(bp);
2694         bnxt_free_tunnel_ports(bp);
2695 }
2696
2697 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2698 {
2699         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2700
2701         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2702                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2703
2704         switch (conf_link_speed) {
2705         case ETH_LINK_SPEED_10M_HD:
2706         case ETH_LINK_SPEED_100M_HD:
2707                 /* FALLTHROUGH */
2708                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2709         }
2710         return hw_link_duplex;
2711 }
2712
2713 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2714 {
2715         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2716 }
2717
2718 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2719 {
2720         uint16_t eth_link_speed = 0;
2721
2722         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2723                 return ETH_LINK_SPEED_AUTONEG;
2724
2725         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2726         case ETH_LINK_SPEED_100M:
2727         case ETH_LINK_SPEED_100M_HD:
2728                 /* FALLTHROUGH */
2729                 eth_link_speed =
2730                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2731                 break;
2732         case ETH_LINK_SPEED_1G:
2733                 eth_link_speed =
2734                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2735                 break;
2736         case ETH_LINK_SPEED_2_5G:
2737                 eth_link_speed =
2738                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2739                 break;
2740         case ETH_LINK_SPEED_10G:
2741                 eth_link_speed =
2742                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2743                 break;
2744         case ETH_LINK_SPEED_20G:
2745                 eth_link_speed =
2746                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2747                 break;
2748         case ETH_LINK_SPEED_25G:
2749                 eth_link_speed =
2750                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2751                 break;
2752         case ETH_LINK_SPEED_40G:
2753                 eth_link_speed =
2754                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2755                 break;
2756         case ETH_LINK_SPEED_50G:
2757                 eth_link_speed =
2758                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2759                 break;
2760         case ETH_LINK_SPEED_100G:
2761                 eth_link_speed =
2762                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2763                 break;
2764         default:
2765                 PMD_DRV_LOG(ERR,
2766                         "Unsupported link speed %d; default to AUTO\n",
2767                         conf_link_speed);
2768                 break;
2769         }
2770         return eth_link_speed;
2771 }
2772
2773 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2774                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2775                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2776                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2777
2778 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2779 {
2780         uint32_t one_speed;
2781
2782         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2783                 return 0;
2784
2785         if (link_speed & ETH_LINK_SPEED_FIXED) {
2786                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2787
2788                 if (one_speed & (one_speed - 1)) {
2789                         PMD_DRV_LOG(ERR,
2790                                 "Invalid advertised speeds (%u) for port %u\n",
2791                                 link_speed, port_id);
2792                         return -EINVAL;
2793                 }
2794                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2795                         PMD_DRV_LOG(ERR,
2796                                 "Unsupported advertised speed (%u) for port %u\n",
2797                                 link_speed, port_id);
2798                         return -EINVAL;
2799                 }
2800         } else {
2801                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2802                         PMD_DRV_LOG(ERR,
2803                                 "Unsupported advertised speeds (%u) for port %u\n",
2804                                 link_speed, port_id);
2805                         return -EINVAL;
2806                 }
2807         }
2808         return 0;
2809 }
2810
2811 static uint16_t
2812 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2813 {
2814         uint16_t ret = 0;
2815
2816         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2817                 if (bp->link_info.support_speeds)
2818                         return bp->link_info.support_speeds;
2819                 link_speed = BNXT_SUPPORTED_SPEEDS;
2820         }
2821
2822         if (link_speed & ETH_LINK_SPEED_100M)
2823                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2824         if (link_speed & ETH_LINK_SPEED_100M_HD)
2825                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2826         if (link_speed & ETH_LINK_SPEED_1G)
2827                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2828         if (link_speed & ETH_LINK_SPEED_2_5G)
2829                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2830         if (link_speed & ETH_LINK_SPEED_10G)
2831                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2832         if (link_speed & ETH_LINK_SPEED_20G)
2833                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2834         if (link_speed & ETH_LINK_SPEED_25G)
2835                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2836         if (link_speed & ETH_LINK_SPEED_40G)
2837                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2838         if (link_speed & ETH_LINK_SPEED_50G)
2839                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2840         if (link_speed & ETH_LINK_SPEED_100G)
2841                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2842         return ret;
2843 }
2844
2845 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2846 {
2847         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2848
2849         switch (hw_link_speed) {
2850         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2851                 eth_link_speed = ETH_SPEED_NUM_100M;
2852                 break;
2853         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2854                 eth_link_speed = ETH_SPEED_NUM_1G;
2855                 break;
2856         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2857                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2858                 break;
2859         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2860                 eth_link_speed = ETH_SPEED_NUM_10G;
2861                 break;
2862         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2863                 eth_link_speed = ETH_SPEED_NUM_20G;
2864                 break;
2865         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2866                 eth_link_speed = ETH_SPEED_NUM_25G;
2867                 break;
2868         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2869                 eth_link_speed = ETH_SPEED_NUM_40G;
2870                 break;
2871         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2872                 eth_link_speed = ETH_SPEED_NUM_50G;
2873                 break;
2874         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2875                 eth_link_speed = ETH_SPEED_NUM_100G;
2876                 break;
2877         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2878         default:
2879                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2880                         hw_link_speed);
2881                 break;
2882         }
2883         return eth_link_speed;
2884 }
2885
2886 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2887 {
2888         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2889
2890         switch (hw_link_duplex) {
2891         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2892         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2893                 /* FALLTHROUGH */
2894                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2895                 break;
2896         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2897                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2898                 break;
2899         default:
2900                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2901                         hw_link_duplex);
2902                 break;
2903         }
2904         return eth_link_duplex;
2905 }
2906
2907 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2908 {
2909         int rc = 0;
2910         struct bnxt_link_info *link_info = &bp->link_info;
2911
2912         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2913         if (rc) {
2914                 PMD_DRV_LOG(ERR,
2915                         "Get link config failed with rc %d\n", rc);
2916                 goto exit;
2917         }
2918         if (link_info->link_speed)
2919                 link->link_speed =
2920                         bnxt_parse_hw_link_speed(link_info->link_speed);
2921         else
2922                 link->link_speed = ETH_SPEED_NUM_NONE;
2923         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2924         link->link_status = link_info->link_up;
2925         link->link_autoneg = link_info->auto_mode ==
2926                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2927                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2928 exit:
2929         return rc;
2930 }
2931
2932 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2933 {
2934         int rc = 0;
2935         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2936         struct bnxt_link_info link_req;
2937         uint16_t speed, autoneg;
2938
2939         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2940                 return 0;
2941
2942         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2943                         bp->eth_dev->data->port_id);
2944         if (rc)
2945                 goto error;
2946
2947         memset(&link_req, 0, sizeof(link_req));
2948         link_req.link_up = link_up;
2949         if (!link_up)
2950                 goto port_phy_cfg;
2951
2952         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2953         if (BNXT_CHIP_THOR(bp) &&
2954             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2955                 /* 40G is not supported as part of media auto detect.
2956                  * The speed should be forced and autoneg disabled
2957                  * to configure 40G speed.
2958                  */
2959                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2960                 autoneg = 0;
2961         }
2962
2963         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2964         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2965         /* Autoneg can be done only when the FW allows.
2966          * When user configures fixed speed of 40G and later changes to
2967          * any other speed, auto_link_speed/force_link_speed is still set
2968          * to 40G until link comes up at new speed.
2969          */
2970         if (autoneg == 1 &&
2971             !(!BNXT_CHIP_THOR(bp) &&
2972               (bp->link_info.auto_link_speed ||
2973                bp->link_info.force_link_speed))) {
2974                 link_req.phy_flags |=
2975                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2976                 link_req.auto_link_speed_mask =
2977                         bnxt_parse_eth_link_speed_mask(bp,
2978                                                        dev_conf->link_speeds);
2979         } else {
2980                 if (bp->link_info.phy_type ==
2981                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2982                     bp->link_info.phy_type ==
2983                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2984                     bp->link_info.media_type ==
2985                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2986                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2987                         return -EINVAL;
2988                 }
2989
2990                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2991                 /* If user wants a particular speed try that first. */
2992                 if (speed)
2993                         link_req.link_speed = speed;
2994                 else if (bp->link_info.force_link_speed)
2995                         link_req.link_speed = bp->link_info.force_link_speed;
2996                 else
2997                         link_req.link_speed = bp->link_info.auto_link_speed;
2998         }
2999         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3000         link_req.auto_pause = bp->link_info.auto_pause;
3001         link_req.force_pause = bp->link_info.force_pause;
3002
3003 port_phy_cfg:
3004         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3005         if (rc) {
3006                 PMD_DRV_LOG(ERR,
3007                         "Set link config failed with rc %d\n", rc);
3008         }
3009
3010 error:
3011         return rc;
3012 }
3013
3014 /* JIRA 22088 */
3015 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3016 {
3017         struct hwrm_func_qcfg_input req = {0};
3018         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3019         uint16_t flags;
3020         int rc = 0;
3021         bp->func_svif = BNXT_SVIF_INVALID;
3022         uint16_t svif_info;
3023
3024         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3025         req.fid = rte_cpu_to_le_16(0xffff);
3026
3027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3028
3029         HWRM_CHECK_RESULT();
3030
3031         /* Hard Coded.. 0xfff VLAN ID mask */
3032         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3033
3034         svif_info = rte_le_to_cpu_16(resp->svif_info);
3035         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3036                 bp->func_svif = svif_info &
3037                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3038
3039         flags = rte_le_to_cpu_16(resp->flags);
3040         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3041                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3042
3043         if (BNXT_VF(bp) &&
3044             !BNXT_VF_IS_TRUSTED(bp) &&
3045             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3046                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3047                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3048         } else if (BNXT_VF(bp) &&
3049                    BNXT_VF_IS_TRUSTED(bp) &&
3050                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3051                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3052                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3053         }
3054
3055         if (mtu)
3056                 *mtu = rte_le_to_cpu_16(resp->mtu);
3057
3058         switch (resp->port_partition_type) {
3059         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3060         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3061         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3062                 /* FALLTHROUGH */
3063                 bp->flags |= BNXT_FLAG_NPAR_PF;
3064                 break;
3065         default:
3066                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3067                 break;
3068         }
3069
3070         HWRM_UNLOCK();
3071
3072         return rc;
3073 }
3074
3075 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3076 {
3077         struct hwrm_port_mac_qcfg_input req = {0};
3078         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3079         uint16_t port_svif_info;
3080         int rc;
3081
3082         bp->port_svif = BNXT_SVIF_INVALID;
3083
3084         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3085
3086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3087
3088         HWRM_CHECK_RESULT();
3089
3090         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3091         if (port_svif_info &
3092             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3093                 bp->port_svif = port_svif_info &
3094                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3095
3096         HWRM_UNLOCK();
3097
3098         return 0;
3099 }
3100
3101 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3102                                    struct hwrm_func_qcaps_output *qcaps)
3103 {
3104         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3105         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3106                sizeof(qcaps->mac_address));
3107         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3108         qcaps->max_rx_rings = fcfg->num_rx_rings;
3109         qcaps->max_tx_rings = fcfg->num_tx_rings;
3110         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3111         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3112         qcaps->max_vfs = 0;
3113         qcaps->first_vf_id = 0;
3114         qcaps->max_vnics = fcfg->num_vnics;
3115         qcaps->max_decap_records = 0;
3116         qcaps->max_encap_records = 0;
3117         qcaps->max_tx_wm_flows = 0;
3118         qcaps->max_tx_em_flows = 0;
3119         qcaps->max_rx_wm_flows = 0;
3120         qcaps->max_rx_em_flows = 0;
3121         qcaps->max_flow_id = 0;
3122         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3123         qcaps->max_sp_tx_rings = 0;
3124         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3125 }
3126
3127 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3128 {
3129         struct hwrm_func_cfg_input req = {0};
3130         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3131         uint32_t enables;
3132         int rc;
3133
3134         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3135                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3136                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3137                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3138                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3139                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3140                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3141                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3142                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3143
3144         if (BNXT_HAS_RING_GRPS(bp)) {
3145                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3146                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3147         } else if (BNXT_HAS_NQ(bp)) {
3148                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3149                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3150         }
3151
3152         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3153         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3154         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3155         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3156         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3157         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3158         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3159         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3160         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3161         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3162         req.fid = rte_cpu_to_le_16(0xffff);
3163         req.enables = rte_cpu_to_le_32(enables);
3164
3165         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3166
3167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3168
3169         HWRM_CHECK_RESULT();
3170         HWRM_UNLOCK();
3171
3172         return rc;
3173 }
3174
3175 static void populate_vf_func_cfg_req(struct bnxt *bp,
3176                                      struct hwrm_func_cfg_input *req,
3177                                      int num_vfs)
3178 {
3179         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3180                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3181                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3182                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3183                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3184                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3185                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3186                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3187                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3188                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3189
3190         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3191                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3192                                     BNXT_NUM_VLANS);
3193         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3194         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3195                                                 (num_vfs + 1));
3196         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3197         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3198                                                (num_vfs + 1));
3199         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3200         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3201         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3202         /* TODO: For now, do not support VMDq/RFS on VFs. */
3203         req->num_vnics = rte_cpu_to_le_16(1);
3204         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3205                                                  (num_vfs + 1));
3206 }
3207
3208 static void add_random_mac_if_needed(struct bnxt *bp,
3209                                      struct hwrm_func_cfg_input *cfg_req,
3210                                      int vf)
3211 {
3212         struct rte_ether_addr mac;
3213
3214         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3215                 return;
3216
3217         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3218                 cfg_req->enables |=
3219                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3220                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3221                 bp->pf.vf_info[vf].random_mac = true;
3222         } else {
3223                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3224                         RTE_ETHER_ADDR_LEN);
3225         }
3226 }
3227
3228 static int reserve_resources_from_vf(struct bnxt *bp,
3229                                      struct hwrm_func_cfg_input *cfg_req,
3230                                      int vf)
3231 {
3232         struct hwrm_func_qcaps_input req = {0};
3233         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3234         int rc;
3235
3236         /* Get the actual allocated values now */
3237         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3238         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3239         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3240
3241         if (rc) {
3242                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3243                 copy_func_cfg_to_qcaps(cfg_req, resp);
3244         } else if (resp->error_code) {
3245                 rc = rte_le_to_cpu_16(resp->error_code);
3246                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3247                 copy_func_cfg_to_qcaps(cfg_req, resp);
3248         }
3249
3250         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3251         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3252         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3253         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3254         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3255         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3256         /*
3257          * TODO: While not supporting VMDq with VFs, max_vnics is always
3258          * forced to 1 in this case
3259          */
3260         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3261         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3262
3263         HWRM_UNLOCK();
3264
3265         return 0;
3266 }
3267
3268 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3269 {
3270         struct hwrm_func_qcfg_input req = {0};
3271         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3272         int rc;
3273
3274         /* Check for zero MAC address */
3275         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3276         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3278         HWRM_CHECK_RESULT();
3279         rc = rte_le_to_cpu_16(resp->vlan);
3280
3281         HWRM_UNLOCK();
3282
3283         return rc;
3284 }
3285
3286 static int update_pf_resource_max(struct bnxt *bp)
3287 {
3288         struct hwrm_func_qcfg_input req = {0};
3289         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3290         int rc;
3291
3292         /* And copy the allocated numbers into the pf struct */
3293         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3294         req.fid = rte_cpu_to_le_16(0xffff);
3295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3296         HWRM_CHECK_RESULT();
3297
3298         /* Only TX ring value reflects actual allocation? TODO */
3299         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3300         bp->pf.evb_mode = resp->evb_mode;
3301
3302         HWRM_UNLOCK();
3303
3304         return rc;
3305 }
3306
3307 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3308 {
3309         int rc;
3310
3311         if (!BNXT_PF(bp)) {
3312                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3313                 return -EINVAL;
3314         }
3315
3316         rc = bnxt_hwrm_func_qcaps(bp);
3317         if (rc)
3318                 return rc;
3319
3320         bp->pf.func_cfg_flags &=
3321                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3322                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3323         bp->pf.func_cfg_flags |=
3324                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3325         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3326         rc = __bnxt_hwrm_func_qcaps(bp);
3327         return rc;
3328 }
3329
3330 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3331 {
3332         struct hwrm_func_cfg_input req = {0};
3333         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3334         int i;
3335         size_t sz;
3336         int rc = 0;
3337         size_t req_buf_sz;
3338
3339         if (!BNXT_PF(bp)) {
3340                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3341                 return -EINVAL;
3342         }
3343
3344         rc = bnxt_hwrm_func_qcaps(bp);
3345
3346         if (rc)
3347                 return rc;
3348
3349         bp->pf.active_vfs = num_vfs;
3350
3351         /*
3352          * First, configure the PF to only use one TX ring.  This ensures that
3353          * there are enough rings for all VFs.
3354          *
3355          * If we don't do this, when we call func_alloc() later, we will lock
3356          * extra rings to the PF that won't be available during func_cfg() of
3357          * the VFs.
3358          *
3359          * This has been fixed with firmware versions above 20.6.54
3360          */
3361         bp->pf.func_cfg_flags &=
3362                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3363                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3364         bp->pf.func_cfg_flags |=
3365                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3366         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3367         if (rc)
3368                 return rc;
3369
3370         /*
3371          * Now, create and register a buffer to hold forwarded VF requests
3372          */
3373         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3374         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3375                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3376         if (bp->pf.vf_req_buf == NULL) {
3377                 rc = -ENOMEM;
3378                 goto error_free;
3379         }
3380         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3381                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3382         for (i = 0; i < num_vfs; i++)
3383                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3384                                         (i * HWRM_MAX_REQ_LEN);
3385
3386         rc = bnxt_hwrm_func_buf_rgtr(bp);
3387         if (rc)
3388                 goto error_free;
3389
3390         populate_vf_func_cfg_req(bp, &req, num_vfs);
3391
3392         bp->pf.active_vfs = 0;
3393         for (i = 0; i < num_vfs; i++) {
3394                 add_random_mac_if_needed(bp, &req, i);
3395
3396                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3397                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3398                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3399                 rc = bnxt_hwrm_send_message(bp,
3400                                             &req,
3401                                             sizeof(req),
3402                                             BNXT_USE_CHIMP_MB);
3403
3404                 /* Clear enable flag for next pass */
3405                 req.enables &= ~rte_cpu_to_le_32(
3406                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3407
3408                 if (rc || resp->error_code) {
3409                         PMD_DRV_LOG(ERR,
3410                                 "Failed to initizlie VF %d\n", i);
3411                         PMD_DRV_LOG(ERR,
3412                                 "Not all VFs available. (%d, %d)\n",
3413                                 rc, resp->error_code);
3414                         HWRM_UNLOCK();
3415                         break;
3416                 }
3417
3418                 HWRM_UNLOCK();
3419
3420                 reserve_resources_from_vf(bp, &req, i);
3421                 bp->pf.active_vfs++;
3422                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3423         }
3424
3425         /*
3426          * Now configure the PF to use "the rest" of the resources
3427          * We're using STD_TX_RING_MODE here though which will limit the TX
3428          * rings.  This will allow QoS to function properly.  Not setting this
3429          * will cause PF rings to break bandwidth settings.
3430          */
3431         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3432         if (rc)
3433                 goto error_free;
3434
3435         rc = update_pf_resource_max(bp);
3436         if (rc)
3437                 goto error_free;
3438
3439         return rc;
3440
3441 error_free:
3442         bnxt_hwrm_func_buf_unrgtr(bp);
3443         return rc;
3444 }
3445
3446 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3447 {
3448         struct hwrm_func_cfg_input req = {0};
3449         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3450         int rc;
3451
3452         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3453
3454         req.fid = rte_cpu_to_le_16(0xffff);
3455         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3456         req.evb_mode = bp->pf.evb_mode;
3457
3458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3459         HWRM_CHECK_RESULT();
3460         HWRM_UNLOCK();
3461
3462         return rc;
3463 }
3464
3465 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3466                                 uint8_t tunnel_type)
3467 {
3468         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3469         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3470         int rc = 0;
3471
3472         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3473         req.tunnel_type = tunnel_type;
3474         req.tunnel_dst_port_val = port;
3475         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3476         HWRM_CHECK_RESULT();
3477
3478         switch (tunnel_type) {
3479         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3480                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3481                 bp->vxlan_port = port;
3482                 break;
3483         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3484                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3485                 bp->geneve_port = port;
3486                 break;
3487         default:
3488                 break;
3489         }
3490
3491         HWRM_UNLOCK();
3492
3493         return rc;
3494 }
3495
3496 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3497                                 uint8_t tunnel_type)
3498 {
3499         struct hwrm_tunnel_dst_port_free_input req = {0};
3500         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3501         int rc = 0;
3502
3503         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3504
3505         req.tunnel_type = tunnel_type;
3506         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3507         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3508
3509         HWRM_CHECK_RESULT();
3510         HWRM_UNLOCK();
3511
3512         return rc;
3513 }
3514
3515 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3516                                         uint32_t flags)
3517 {
3518         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3519         struct hwrm_func_cfg_input req = {0};
3520         int rc;
3521
3522         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3523
3524         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3525         req.flags = rte_cpu_to_le_32(flags);
3526         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3527
3528         HWRM_CHECK_RESULT();
3529         HWRM_UNLOCK();
3530
3531         return rc;
3532 }
3533
3534 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3535 {
3536         uint32_t *flag = flagp;
3537
3538         vnic->flags = *flag;
3539 }
3540
3541 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3542 {
3543         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3544 }
3545
3546 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3547 {
3548         int rc = 0;
3549         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3550         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3551
3552         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3553
3554         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3555         req.req_buf_page_size = rte_cpu_to_le_16(
3556                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3557         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3558         req.req_buf_page_addr0 =
3559                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf.vf_req_buf));
3560         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3561                 PMD_DRV_LOG(ERR,
3562                         "unable to map buffer address to physical memory\n");
3563                 return -ENOMEM;
3564         }
3565
3566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3567
3568         HWRM_CHECK_RESULT();
3569         HWRM_UNLOCK();
3570
3571         return rc;
3572 }
3573
3574 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3575 {
3576         int rc = 0;
3577         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3578         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3579
3580         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3581                 return 0;
3582
3583         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3584
3585         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3586
3587         HWRM_CHECK_RESULT();
3588         HWRM_UNLOCK();
3589
3590         return rc;
3591 }
3592
3593 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3594 {
3595         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3596         struct hwrm_func_cfg_input req = {0};
3597         int rc;
3598
3599         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3600
3601         req.fid = rte_cpu_to_le_16(0xffff);
3602         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3603         req.enables = rte_cpu_to_le_32(
3604                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3605         req.async_event_cr = rte_cpu_to_le_16(
3606                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3607         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3608
3609         HWRM_CHECK_RESULT();
3610         HWRM_UNLOCK();
3611
3612         return rc;
3613 }
3614
3615 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3616 {
3617         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3618         struct hwrm_func_vf_cfg_input req = {0};
3619         int rc;
3620
3621         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3622
3623         req.enables = rte_cpu_to_le_32(
3624                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3625         req.async_event_cr = rte_cpu_to_le_16(
3626                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3628
3629         HWRM_CHECK_RESULT();
3630         HWRM_UNLOCK();
3631
3632         return rc;
3633 }
3634
3635 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3636 {
3637         struct hwrm_func_cfg_input req = {0};
3638         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3639         uint16_t dflt_vlan, fid;
3640         uint32_t func_cfg_flags;
3641         int rc = 0;
3642
3643         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3644
3645         if (is_vf) {
3646                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3647                 fid = bp->pf.vf_info[vf].fid;
3648                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3649         } else {
3650                 fid = rte_cpu_to_le_16(0xffff);
3651                 func_cfg_flags = bp->pf.func_cfg_flags;
3652                 dflt_vlan = bp->vlan;
3653         }
3654
3655         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3656         req.fid = rte_cpu_to_le_16(fid);
3657         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3658         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3659
3660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661
3662         HWRM_CHECK_RESULT();
3663         HWRM_UNLOCK();
3664
3665         return rc;
3666 }
3667
3668 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3669                         uint16_t max_bw, uint16_t enables)
3670 {
3671         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3672         struct hwrm_func_cfg_input req = {0};
3673         int rc;
3674
3675         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3676
3677         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3678         req.enables |= rte_cpu_to_le_32(enables);
3679         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3680         req.max_bw = rte_cpu_to_le_32(max_bw);
3681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3682
3683         HWRM_CHECK_RESULT();
3684         HWRM_UNLOCK();
3685
3686         return rc;
3687 }
3688
3689 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3690 {
3691         struct hwrm_func_cfg_input req = {0};
3692         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3693         int rc = 0;
3694
3695         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3696
3697         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3698         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3699         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3700         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3701
3702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3703
3704         HWRM_CHECK_RESULT();
3705         HWRM_UNLOCK();
3706
3707         return rc;
3708 }
3709
3710 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3711 {
3712         int rc;
3713
3714         if (BNXT_PF(bp))
3715                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3716         else
3717                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3718
3719         return rc;
3720 }
3721
3722 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3723                               void *encaped, size_t ec_size)
3724 {
3725         int rc = 0;
3726         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3727         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3728
3729         if (ec_size > sizeof(req.encap_request))
3730                 return -1;
3731
3732         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3733
3734         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3735         memcpy(req.encap_request, encaped, ec_size);
3736
3737         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3738
3739         HWRM_CHECK_RESULT();
3740         HWRM_UNLOCK();
3741
3742         return rc;
3743 }
3744
3745 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3746                                        struct rte_ether_addr *mac)
3747 {
3748         struct hwrm_func_qcfg_input req = {0};
3749         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3750         int rc;
3751
3752         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3753
3754         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3755         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3756
3757         HWRM_CHECK_RESULT();
3758
3759         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3760
3761         HWRM_UNLOCK();
3762
3763         return rc;
3764 }
3765
3766 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3767                             void *encaped, size_t ec_size)
3768 {
3769         int rc = 0;
3770         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3771         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3772
3773         if (ec_size > sizeof(req.encap_request))
3774                 return -1;
3775
3776         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3777
3778         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3779         memcpy(req.encap_request, encaped, ec_size);
3780
3781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3782
3783         HWRM_CHECK_RESULT();
3784         HWRM_UNLOCK();
3785
3786         return rc;
3787 }
3788
3789 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3790                          struct rte_eth_stats *stats, uint8_t rx)
3791 {
3792         int rc = 0;
3793         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3794         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3795
3796         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3797
3798         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3799
3800         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3801
3802         HWRM_CHECK_RESULT();
3803
3804         if (rx) {
3805                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3806                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3807                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3808                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3809                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3810                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3811                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3812                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3813         } else {
3814                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3815                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3816                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3817                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3818                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3819                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3820         }
3821
3822         HWRM_UNLOCK();
3823
3824         return rc;
3825 }
3826
3827 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3828 {
3829         struct hwrm_port_qstats_input req = {0};
3830         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3831         struct bnxt_pf_info *pf = &bp->pf;
3832         int rc;
3833
3834         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3835
3836         req.port_id = rte_cpu_to_le_16(pf->port_id);
3837         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3838         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3839         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3840
3841         HWRM_CHECK_RESULT();
3842         HWRM_UNLOCK();
3843
3844         return rc;
3845 }
3846
3847 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3848 {
3849         struct hwrm_port_clr_stats_input req = {0};
3850         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3851         struct bnxt_pf_info *pf = &bp->pf;
3852         int rc;
3853
3854         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3855         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3856             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3857                 return 0;
3858
3859         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3860
3861         req.port_id = rte_cpu_to_le_16(pf->port_id);
3862         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3863
3864         HWRM_CHECK_RESULT();
3865         HWRM_UNLOCK();
3866
3867         return rc;
3868 }
3869
3870 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3871 {
3872         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3873         struct hwrm_port_led_qcaps_input req = {0};
3874         int rc;
3875
3876         if (BNXT_VF(bp))
3877                 return 0;
3878
3879         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3880         req.port_id = bp->pf.port_id;
3881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3882
3883         HWRM_CHECK_RESULT();
3884
3885         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3886                 unsigned int i;
3887
3888                 bp->num_leds = resp->num_leds;
3889                 memcpy(bp->leds, &resp->led0_id,
3890                         sizeof(bp->leds[0]) * bp->num_leds);
3891                 for (i = 0; i < bp->num_leds; i++) {
3892                         struct bnxt_led_info *led = &bp->leds[i];
3893
3894                         uint16_t caps = led->led_state_caps;
3895
3896                         if (!led->led_group_id ||
3897                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3898                                 bp->num_leds = 0;
3899                                 break;
3900                         }
3901                 }
3902         }
3903
3904         HWRM_UNLOCK();
3905
3906         return rc;
3907 }
3908
3909 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3910 {
3911         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3912         struct hwrm_port_led_cfg_input req = {0};
3913         struct bnxt_led_cfg *led_cfg;
3914         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3915         uint16_t duration = 0;
3916         int rc, i;
3917
3918         if (!bp->num_leds || BNXT_VF(bp))
3919                 return -EOPNOTSUPP;
3920
3921         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3922
3923         if (led_on) {
3924                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3925                 duration = rte_cpu_to_le_16(500);
3926         }
3927         req.port_id = bp->pf.port_id;
3928         req.num_leds = bp->num_leds;
3929         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3930         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3931                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3932                 led_cfg->led_id = bp->leds[i].led_id;
3933                 led_cfg->led_state = led_state;
3934                 led_cfg->led_blink_on = duration;
3935                 led_cfg->led_blink_off = duration;
3936                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3937         }
3938
3939         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3940
3941         HWRM_CHECK_RESULT();
3942         HWRM_UNLOCK();
3943
3944         return rc;
3945 }
3946
3947 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3948                                uint32_t *length)
3949 {
3950         int rc;
3951         struct hwrm_nvm_get_dir_info_input req = {0};
3952         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3953
3954         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3955
3956         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3957
3958         HWRM_CHECK_RESULT();
3959
3960         *entries = rte_le_to_cpu_32(resp->entries);
3961         *length = rte_le_to_cpu_32(resp->entry_length);
3962
3963         HWRM_UNLOCK();
3964         return rc;
3965 }
3966
3967 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3968 {
3969         int rc;
3970         uint32_t dir_entries;
3971         uint32_t entry_length;
3972         uint8_t *buf;
3973         size_t buflen;
3974         rte_iova_t dma_handle;
3975         struct hwrm_nvm_get_dir_entries_input req = {0};
3976         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3977
3978         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3979         if (rc != 0)
3980                 return rc;
3981
3982         *data++ = dir_entries;
3983         *data++ = entry_length;
3984         len -= 2;
3985         memset(data, 0xff, len);
3986
3987         buflen = dir_entries * entry_length;
3988         buf = rte_malloc("nvm_dir", buflen, 0);
3989         if (buf == NULL)
3990                 return -ENOMEM;
3991         dma_handle = rte_malloc_virt2iova(buf);
3992         if (dma_handle == RTE_BAD_IOVA) {
3993                 PMD_DRV_LOG(ERR,
3994                         "unable to map response address to physical memory\n");
3995                 return -ENOMEM;
3996         }
3997         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3998         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3999         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4000
4001         if (rc == 0)
4002                 memcpy(data, buf, len > buflen ? buflen : len);
4003
4004         rte_free(buf);
4005         HWRM_CHECK_RESULT();
4006         HWRM_UNLOCK();
4007
4008         return rc;
4009 }
4010
4011 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4012                              uint32_t offset, uint32_t length,
4013                              uint8_t *data)
4014 {
4015         int rc;
4016         uint8_t *buf;
4017         rte_iova_t dma_handle;
4018         struct hwrm_nvm_read_input req = {0};
4019         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4020
4021         buf = rte_malloc("nvm_item", length, 0);
4022         if (!buf)
4023                 return -ENOMEM;
4024
4025         dma_handle = rte_malloc_virt2iova(buf);
4026         if (dma_handle == RTE_BAD_IOVA) {
4027                 PMD_DRV_LOG(ERR,
4028                         "unable to map response address to physical memory\n");
4029                 return -ENOMEM;
4030         }
4031         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4032         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4033         req.dir_idx = rte_cpu_to_le_16(index);
4034         req.offset = rte_cpu_to_le_32(offset);
4035         req.len = rte_cpu_to_le_32(length);
4036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4037         if (rc == 0)
4038                 memcpy(data, buf, length);
4039
4040         rte_free(buf);
4041         HWRM_CHECK_RESULT();
4042         HWRM_UNLOCK();
4043
4044         return rc;
4045 }
4046
4047 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4048 {
4049         int rc;
4050         struct hwrm_nvm_erase_dir_entry_input req = {0};
4051         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4052
4053         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4054         req.dir_idx = rte_cpu_to_le_16(index);
4055         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4056         HWRM_CHECK_RESULT();
4057         HWRM_UNLOCK();
4058
4059         return rc;
4060 }
4061
4062
4063 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4064                           uint16_t dir_ordinal, uint16_t dir_ext,
4065                           uint16_t dir_attr, const uint8_t *data,
4066                           size_t data_len)
4067 {
4068         int rc;
4069         struct hwrm_nvm_write_input req = {0};
4070         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4071         rte_iova_t dma_handle;
4072         uint8_t *buf;
4073
4074         buf = rte_malloc("nvm_write", data_len, 0);
4075         if (!buf)
4076                 return -ENOMEM;
4077
4078         dma_handle = rte_malloc_virt2iova(buf);
4079         if (dma_handle == RTE_BAD_IOVA) {
4080                 PMD_DRV_LOG(ERR,
4081                         "unable to map response address to physical memory\n");
4082                 return -ENOMEM;
4083         }
4084         memcpy(buf, data, data_len);
4085
4086         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4087
4088         req.dir_type = rte_cpu_to_le_16(dir_type);
4089         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4090         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4091         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4092         req.dir_data_length = rte_cpu_to_le_32(data_len);
4093         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4094
4095         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096
4097         rte_free(buf);
4098         HWRM_CHECK_RESULT();
4099         HWRM_UNLOCK();
4100
4101         return rc;
4102 }
4103
4104 static void
4105 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4106 {
4107         uint32_t *count = cbdata;
4108
4109         *count = *count + 1;
4110 }
4111
4112 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4113                                      struct bnxt_vnic_info *vnic __rte_unused)
4114 {
4115         return 0;
4116 }
4117
4118 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4119 {
4120         uint32_t count = 0;
4121
4122         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4123             &count, bnxt_vnic_count_hwrm_stub);
4124
4125         return count;
4126 }
4127
4128 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4129                                         uint16_t *vnic_ids)
4130 {
4131         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4132         struct hwrm_func_vf_vnic_ids_query_output *resp =
4133                                                 bp->hwrm_cmd_resp_addr;
4134         int rc;
4135
4136         /* First query all VNIC ids */
4137         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4138
4139         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
4140         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
4141         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4142
4143         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4144                 HWRM_UNLOCK();
4145                 PMD_DRV_LOG(ERR,
4146                 "unable to map VNIC ID table address to physical memory\n");
4147                 return -ENOMEM;
4148         }
4149         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4150         HWRM_CHECK_RESULT();
4151         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4152
4153         HWRM_UNLOCK();
4154
4155         return rc;
4156 }
4157
4158 /*
4159  * This function queries the VNIC IDs  for a specified VF. It then calls
4160  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4161  * Then it calls the hwrm_cb function to program this new vnic configuration.
4162  */
4163 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4164         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4165         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4166 {
4167         struct bnxt_vnic_info vnic;
4168         int rc = 0;
4169         int i, num_vnic_ids;
4170         uint16_t *vnic_ids;
4171         size_t vnic_id_sz;
4172         size_t sz;
4173
4174         /* First query all VNIC ids */
4175         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4176         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4177                         RTE_CACHE_LINE_SIZE);
4178         if (vnic_ids == NULL)
4179                 return -ENOMEM;
4180
4181         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4182                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4183
4184         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4185
4186         if (num_vnic_ids < 0)
4187                 return num_vnic_ids;
4188
4189         /* Retrieve VNIC, update bd_stall then update */
4190
4191         for (i = 0; i < num_vnic_ids; i++) {
4192                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4193                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4194                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4195                 if (rc)
4196                         break;
4197                 if (vnic.mru <= 4)      /* Indicates unallocated */
4198                         continue;
4199
4200                 vnic_cb(&vnic, cbdata);
4201
4202                 rc = hwrm_cb(bp, &vnic);
4203                 if (rc)
4204                         break;
4205         }
4206
4207         rte_free(vnic_ids);
4208
4209         return rc;
4210 }
4211
4212 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4213                                               bool on)
4214 {
4215         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4216         struct hwrm_func_cfg_input req = {0};
4217         int rc;
4218
4219         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4220
4221         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4222         req.enables |= rte_cpu_to_le_32(
4223                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4224         req.vlan_antispoof_mode = on ?
4225                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4226                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4227         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4228
4229         HWRM_CHECK_RESULT();
4230         HWRM_UNLOCK();
4231
4232         return rc;
4233 }
4234
4235 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4236 {
4237         struct bnxt_vnic_info vnic;
4238         uint16_t *vnic_ids;
4239         size_t vnic_id_sz;
4240         int num_vnic_ids, i;
4241         size_t sz;
4242         int rc;
4243
4244         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4245         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4246                         RTE_CACHE_LINE_SIZE);
4247         if (vnic_ids == NULL)
4248                 return -ENOMEM;
4249
4250         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4251                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4252
4253         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4254         if (rc <= 0)
4255                 goto exit;
4256         num_vnic_ids = rc;
4257
4258         /*
4259          * Loop through to find the default VNIC ID.
4260          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4261          * by sending the hwrm_func_qcfg command to the firmware.
4262          */
4263         for (i = 0; i < num_vnic_ids; i++) {
4264                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4265                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4266                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4267                                         bp->pf.first_vf_id + vf);
4268                 if (rc)
4269                         goto exit;
4270                 if (vnic.func_default) {
4271                         rte_free(vnic_ids);
4272                         return vnic.fw_vnic_id;
4273                 }
4274         }
4275         /* Could not find a default VNIC. */
4276         PMD_DRV_LOG(ERR, "No default VNIC\n");
4277 exit:
4278         rte_free(vnic_ids);
4279         return rc;
4280 }
4281
4282 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4283                          uint16_t dst_id,
4284                          struct bnxt_filter_info *filter)
4285 {
4286         int rc = 0;
4287         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4288         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4289         uint32_t enables = 0;
4290
4291         if (filter->fw_em_filter_id != UINT64_MAX)
4292                 bnxt_hwrm_clear_em_filter(bp, filter);
4293
4294         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4295
4296         req.flags = rte_cpu_to_le_32(filter->flags);
4297
4298         enables = filter->enables |
4299               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4300         req.dst_id = rte_cpu_to_le_16(dst_id);
4301
4302         if (filter->ip_addr_type) {
4303                 req.ip_addr_type = filter->ip_addr_type;
4304                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4305         }
4306         if (enables &
4307             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4308                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4309         if (enables &
4310             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4311                 memcpy(req.src_macaddr, filter->src_macaddr,
4312                        RTE_ETHER_ADDR_LEN);
4313         if (enables &
4314             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4315                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4316                        RTE_ETHER_ADDR_LEN);
4317         if (enables &
4318             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4319                 req.ovlan_vid = filter->l2_ovlan;
4320         if (enables &
4321             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4322                 req.ivlan_vid = filter->l2_ivlan;
4323         if (enables &
4324             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4325                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4326         if (enables &
4327             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4328                 req.ip_protocol = filter->ip_protocol;
4329         if (enables &
4330             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4331                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4332         if (enables &
4333             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4334                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4335         if (enables &
4336             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4337                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4338         if (enables &
4339             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4340                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4341         if (enables &
4342             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4343                 req.mirror_vnic_id = filter->mirror_vnic_id;
4344
4345         req.enables = rte_cpu_to_le_32(enables);
4346
4347         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4348
4349         HWRM_CHECK_RESULT();
4350
4351         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4352         HWRM_UNLOCK();
4353
4354         return rc;
4355 }
4356
4357 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4358 {
4359         int rc = 0;
4360         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4361         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4362
4363         if (filter->fw_em_filter_id == UINT64_MAX)
4364                 return 0;
4365
4366         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4367
4368         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4369
4370         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4371
4372         HWRM_CHECK_RESULT();
4373         HWRM_UNLOCK();
4374
4375         filter->fw_em_filter_id = UINT64_MAX;
4376         filter->fw_l2_filter_id = UINT64_MAX;
4377
4378         return 0;
4379 }
4380
4381 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4382                          uint16_t dst_id,
4383                          struct bnxt_filter_info *filter)
4384 {
4385         int rc = 0;
4386         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4387         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4388                                                 bp->hwrm_cmd_resp_addr;
4389         uint32_t enables = 0;
4390
4391         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4392                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4393
4394         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4395
4396         req.flags = rte_cpu_to_le_32(filter->flags);
4397
4398         enables = filter->enables |
4399               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4400         req.dst_id = rte_cpu_to_le_16(dst_id);
4401
4402         if (filter->ip_addr_type) {
4403                 req.ip_addr_type = filter->ip_addr_type;
4404                 enables |=
4405                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4406         }
4407         if (enables &
4408             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4409                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4410         if (enables &
4411             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4412                 memcpy(req.src_macaddr, filter->src_macaddr,
4413                        RTE_ETHER_ADDR_LEN);
4414         if (enables &
4415             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4416                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4417         if (enables &
4418             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4419                 req.ip_protocol = filter->ip_protocol;
4420         if (enables &
4421             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4422                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4423         if (enables &
4424             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4425                 req.src_ipaddr_mask[0] =
4426                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4427         if (enables &
4428             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4429                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4430         if (enables &
4431             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4432                 req.dst_ipaddr_mask[0] =
4433                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4434         if (enables &
4435             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4436                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4437         if (enables &
4438             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4439                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4440         if (enables &
4441             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4442                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4443         if (enables &
4444             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4445                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4446         if (enables &
4447             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4448                 req.mirror_vnic_id = filter->mirror_vnic_id;
4449
4450         req.enables = rte_cpu_to_le_32(enables);
4451
4452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4453
4454         HWRM_CHECK_RESULT();
4455
4456         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4457         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4458         HWRM_UNLOCK();
4459
4460         return rc;
4461 }
4462
4463 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4464                                 struct bnxt_filter_info *filter)
4465 {
4466         int rc = 0;
4467         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4468         struct hwrm_cfa_ntuple_filter_free_output *resp =
4469                                                 bp->hwrm_cmd_resp_addr;
4470
4471         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4472                 return 0;
4473
4474         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4475
4476         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4477
4478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4479
4480         HWRM_CHECK_RESULT();
4481         HWRM_UNLOCK();
4482
4483         filter->fw_ntuple_filter_id = UINT64_MAX;
4484
4485         return 0;
4486 }
4487
4488 static int
4489 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4490 {
4491         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4492         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4493         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4494         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4495         uint16_t *ring_tbl = vnic->rss_table;
4496         int nr_ctxs = vnic->num_lb_ctxts;
4497         int max_rings = bp->rx_nr_rings;
4498         int i, j, k, cnt;
4499         int rc = 0;
4500
4501         for (i = 0, k = 0; i < nr_ctxs; i++) {
4502                 struct bnxt_rx_ring_info *rxr;
4503                 struct bnxt_cp_ring_info *cpr;
4504
4505                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4506
4507                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4508                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4509                 req.hash_mode_flags = vnic->hash_mode;
4510
4511                 req.ring_grp_tbl_addr =
4512                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4513                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4514                                      2 * sizeof(*ring_tbl));
4515                 req.hash_key_tbl_addr =
4516                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4517
4518                 req.ring_table_pair_index = i;
4519                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4520
4521                 for (j = 0; j < 64; j++) {
4522                         uint16_t ring_id;
4523
4524                         /* Find next active ring. */
4525                         for (cnt = 0; cnt < max_rings; cnt++) {
4526                                 if (rx_queue_state[k] !=
4527                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4528                                         break;
4529                                 if (++k == max_rings)
4530                                         k = 0;
4531                         }
4532
4533                         /* Return if no rings are active. */
4534                         if (cnt == max_rings) {
4535                                 HWRM_UNLOCK();
4536                                 return 0;
4537                         }
4538
4539                         /* Add rx/cp ring pair to RSS table. */
4540                         rxr = rxqs[k]->rx_ring;
4541                         cpr = rxqs[k]->cp_ring;
4542
4543                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4544                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4545                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4546                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4547
4548                         if (++k == max_rings)
4549                                 k = 0;
4550                 }
4551                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4552                                             BNXT_USE_CHIMP_MB);
4553
4554                 HWRM_CHECK_RESULT();
4555                 HWRM_UNLOCK();
4556         }
4557
4558         return rc;
4559 }
4560
4561 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4562 {
4563         unsigned int rss_idx, fw_idx, i;
4564
4565         if (!(vnic->rss_table && vnic->hash_type))
4566                 return 0;
4567
4568         if (BNXT_CHIP_THOR(bp))
4569                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4570
4571         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4572                 return 0;
4573
4574         if (vnic->rss_table && vnic->hash_type) {
4575                 /*
4576                  * Fill the RSS hash & redirection table with
4577                  * ring group ids for all VNICs
4578                  */
4579                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4580                         rss_idx++, fw_idx++) {
4581                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4582                                 fw_idx %= bp->rx_cp_nr_rings;
4583                                 if (vnic->fw_grp_ids[fw_idx] !=
4584                                     INVALID_HW_RING_ID)
4585                                         break;
4586                                 fw_idx++;
4587                         }
4588                         if (i == bp->rx_cp_nr_rings)
4589                                 return 0;
4590                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4591                 }
4592                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4593         }
4594
4595         return 0;
4596 }
4597
4598 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4599         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4600 {
4601         uint16_t flags;
4602
4603         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4604
4605         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4606         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4607
4608         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4609         req->num_cmpl_dma_aggr_during_int =
4610                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4611
4612         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4613
4614         /* min timer set to 1/2 of interrupt timer */
4615         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4616
4617         /* buf timer set to 1/4 of interrupt timer */
4618         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4619
4620         req->cmpl_aggr_dma_tmr_during_int =
4621                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4622
4623         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4624                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4625         req->flags = rte_cpu_to_le_16(flags);
4626 }
4627
4628 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4629                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4630 {
4631         struct hwrm_ring_aggint_qcaps_input req = {0};
4632         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4633         uint32_t enables;
4634         uint16_t flags;
4635         int rc;
4636
4637         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4639         HWRM_CHECK_RESULT();
4640
4641         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4642         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4643
4644         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4645                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4646         agg_req->flags = rte_cpu_to_le_16(flags);
4647         enables =
4648          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4649          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4650         agg_req->enables = rte_cpu_to_le_32(enables);
4651
4652         HWRM_UNLOCK();
4653         return rc;
4654 }
4655
4656 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4657                         struct bnxt_coal *coal, uint16_t ring_id)
4658 {
4659         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4660         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4661                                                 bp->hwrm_cmd_resp_addr;
4662         int rc;
4663
4664         /* Set ring coalesce parameters only for 100G NICs */
4665         if (BNXT_CHIP_THOR(bp)) {
4666                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4667                         return -1;
4668         } else if (bnxt_stratus_device(bp)) {
4669                 bnxt_hwrm_set_coal_params(coal, &req);
4670         } else {
4671                 return 0;
4672         }
4673
4674         HWRM_PREP(&req,
4675                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4676                   BNXT_USE_CHIMP_MB);
4677         req.ring_id = rte_cpu_to_le_16(ring_id);
4678         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4679         HWRM_CHECK_RESULT();
4680         HWRM_UNLOCK();
4681         return 0;
4682 }
4683
4684 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4685 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4686 {
4687         struct hwrm_func_backing_store_qcaps_input req = {0};
4688         struct hwrm_func_backing_store_qcaps_output *resp =
4689                 bp->hwrm_cmd_resp_addr;
4690         struct bnxt_ctx_pg_info *ctx_pg;
4691         struct bnxt_ctx_mem_info *ctx;
4692         int total_alloc_len;
4693         int rc, i;
4694
4695         if (!BNXT_CHIP_THOR(bp) ||
4696             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4697             BNXT_VF(bp) ||
4698             bp->ctx)
4699                 return 0;
4700
4701         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4703         HWRM_CHECK_RESULT_SILENT();
4704
4705         total_alloc_len = sizeof(*ctx);
4706         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4707                           RTE_CACHE_LINE_SIZE);
4708         if (!ctx) {
4709                 rc = -ENOMEM;
4710                 goto ctx_err;
4711         }
4712
4713         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4714                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4715                             RTE_CACHE_LINE_SIZE);
4716         if (!ctx_pg) {
4717                 rc = -ENOMEM;
4718                 goto ctx_err;
4719         }
4720         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4721                 ctx->tqm_mem[i] = ctx_pg;
4722
4723         bp->ctx = ctx;
4724         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4725         ctx->qp_min_qp1_entries =
4726                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4727         ctx->qp_max_l2_entries =
4728                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4729         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4730         ctx->srq_max_l2_entries =
4731                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4732         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4733         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4734         ctx->cq_max_l2_entries =
4735                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4736         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4737         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4738         ctx->vnic_max_vnic_entries =
4739                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4740         ctx->vnic_max_ring_table_entries =
4741                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4742         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4743         ctx->stat_max_entries =
4744                 rte_le_to_cpu_32(resp->stat_max_entries);
4745         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4746         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4747         ctx->tqm_min_entries_per_ring =
4748                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4749         ctx->tqm_max_entries_per_ring =
4750                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4751         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4752         if (!ctx->tqm_entries_multiple)
4753                 ctx->tqm_entries_multiple = 1;
4754         ctx->mrav_max_entries =
4755                 rte_le_to_cpu_32(resp->mrav_max_entries);
4756         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4757         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4758         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4759 ctx_err:
4760         HWRM_UNLOCK();
4761         return rc;
4762 }
4763
4764 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4765 {
4766         struct hwrm_func_backing_store_cfg_input req = {0};
4767         struct hwrm_func_backing_store_cfg_output *resp =
4768                 bp->hwrm_cmd_resp_addr;
4769         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4770         struct bnxt_ctx_pg_info *ctx_pg;
4771         uint32_t *num_entries;
4772         uint64_t *pg_dir;
4773         uint8_t *pg_attr;
4774         uint32_t ena;
4775         int i, rc;
4776
4777         if (!ctx)
4778                 return 0;
4779
4780         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4781         req.enables = rte_cpu_to_le_32(enables);
4782
4783         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4784                 ctx_pg = &ctx->qp_mem;
4785                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4786                 req.qp_num_qp1_entries =
4787                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4788                 req.qp_num_l2_entries =
4789                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4790                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4791                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4792                                       &req.qpc_pg_size_qpc_lvl,
4793                                       &req.qpc_page_dir);
4794         }
4795
4796         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4797                 ctx_pg = &ctx->srq_mem;
4798                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4799                 req.srq_num_l2_entries =
4800                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4801                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4802                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4803                                       &req.srq_pg_size_srq_lvl,
4804                                       &req.srq_page_dir);
4805         }
4806
4807         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4808                 ctx_pg = &ctx->cq_mem;
4809                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4810                 req.cq_num_l2_entries =
4811                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4812                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4813                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4814                                       &req.cq_pg_size_cq_lvl,
4815                                       &req.cq_page_dir);
4816         }
4817
4818         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4819                 ctx_pg = &ctx->vnic_mem;
4820                 req.vnic_num_vnic_entries =
4821                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4822                 req.vnic_num_ring_table_entries =
4823                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4824                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4825                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4826                                       &req.vnic_pg_size_vnic_lvl,
4827                                       &req.vnic_page_dir);
4828         }
4829
4830         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4831                 ctx_pg = &ctx->stat_mem;
4832                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4833                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4834                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4835                                       &req.stat_pg_size_stat_lvl,
4836                                       &req.stat_page_dir);
4837         }
4838
4839         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4840         num_entries = &req.tqm_sp_num_entries;
4841         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4842         pg_dir = &req.tqm_sp_page_dir;
4843         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4844         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4845                 if (!(enables & ena))
4846                         continue;
4847
4848                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4849
4850                 ctx_pg = ctx->tqm_mem[i];
4851                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4852                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4853         }
4854
4855         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4856         HWRM_CHECK_RESULT();
4857         HWRM_UNLOCK();
4858
4859         return rc;
4860 }
4861
4862 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4863 {
4864         struct hwrm_port_qstats_ext_input req = {0};
4865         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4866         struct bnxt_pf_info *pf = &bp->pf;
4867         int rc;
4868
4869         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4870               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4871                 return 0;
4872
4873         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4874
4875         req.port_id = rte_cpu_to_le_16(pf->port_id);
4876         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4877                 req.tx_stat_host_addr =
4878                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4879                 req.tx_stat_size =
4880                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4881         }
4882         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4883                 req.rx_stat_host_addr =
4884                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4885                 req.rx_stat_size =
4886                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4887         }
4888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4889
4890         if (rc) {
4891                 bp->fw_rx_port_stats_ext_size = 0;
4892                 bp->fw_tx_port_stats_ext_size = 0;
4893         } else {
4894                 bp->fw_rx_port_stats_ext_size =
4895                         rte_le_to_cpu_16(resp->rx_stat_size);
4896                 bp->fw_tx_port_stats_ext_size =
4897                         rte_le_to_cpu_16(resp->tx_stat_size);
4898         }
4899
4900         HWRM_CHECK_RESULT();
4901         HWRM_UNLOCK();
4902
4903         return rc;
4904 }
4905
4906 int
4907 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4908 {
4909         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4910         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4911                 bp->hwrm_cmd_resp_addr;
4912         int rc = 0;
4913
4914         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4915         req.tunnel_type = type;
4916         req.dest_fid = bp->fw_fid;
4917         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4918         HWRM_CHECK_RESULT();
4919
4920         HWRM_UNLOCK();
4921
4922         return rc;
4923 }
4924
4925 int
4926 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4927 {
4928         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4929         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4930                 bp->hwrm_cmd_resp_addr;
4931         int rc = 0;
4932
4933         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4934         req.tunnel_type = type;
4935         req.dest_fid = bp->fw_fid;
4936         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4937         HWRM_CHECK_RESULT();
4938
4939         HWRM_UNLOCK();
4940
4941         return rc;
4942 }
4943
4944 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4945 {
4946         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4947         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4948                 bp->hwrm_cmd_resp_addr;
4949         int rc = 0;
4950
4951         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4952         req.src_fid = bp->fw_fid;
4953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4954         HWRM_CHECK_RESULT();
4955
4956         if (type)
4957                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4958
4959         HWRM_UNLOCK();
4960
4961         return rc;
4962 }
4963
4964 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4965                                    uint16_t *dst_fid)
4966 {
4967         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4968         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4969                 bp->hwrm_cmd_resp_addr;
4970         int rc = 0;
4971
4972         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4973         req.src_fid = bp->fw_fid;
4974         req.tunnel_type = tun_type;
4975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4976         HWRM_CHECK_RESULT();
4977
4978         if (dst_fid)
4979                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4980
4981         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4982
4983         HWRM_UNLOCK();
4984
4985         return rc;
4986 }
4987
4988 int bnxt_hwrm_set_mac(struct bnxt *bp)
4989 {
4990         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4991         struct hwrm_func_vf_cfg_input req = {0};
4992         int rc = 0;
4993
4994         if (!BNXT_VF(bp))
4995                 return 0;
4996
4997         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4998
4999         req.enables =
5000                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5001         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5002
5003         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5004
5005         HWRM_CHECK_RESULT();
5006
5007         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5008         HWRM_UNLOCK();
5009
5010         return rc;
5011 }
5012
5013 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5014 {
5015         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5016         struct hwrm_func_drv_if_change_input req = {0};
5017         uint32_t flags;
5018         int rc;
5019
5020         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5021                 return 0;
5022
5023         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5024          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5025          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5026          */
5027         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5028                 return 0;
5029
5030         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5031
5032         if (up)
5033                 req.flags =
5034                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5035
5036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5037
5038         HWRM_CHECK_RESULT();
5039         flags = rte_le_to_cpu_32(resp->flags);
5040         HWRM_UNLOCK();
5041
5042         if (!up)
5043                 return 0;
5044
5045         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5046                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5047                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5048         }
5049
5050         return 0;
5051 }
5052
5053 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5054 {
5055         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5056         struct bnxt_error_recovery_info *info = bp->recovery_info;
5057         struct hwrm_error_recovery_qcfg_input req = {0};
5058         uint32_t flags = 0;
5059         unsigned int i;
5060         int rc;
5061
5062         /* Older FW does not have error recovery support */
5063         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5064                 return 0;
5065
5066         if (!info) {
5067                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5068                                    sizeof(*info), 0);
5069                 bp->recovery_info = info;
5070                 if (info == NULL)
5071                         return -ENOMEM;
5072         } else {
5073                 memset(info, 0, sizeof(*info));
5074         }
5075
5076         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5077
5078         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5079
5080         HWRM_CHECK_RESULT();
5081
5082         flags = rte_le_to_cpu_32(resp->flags);
5083         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5084                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5085         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5086                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5087
5088         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5089             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5090                 rc = -EINVAL;
5091                 goto err;
5092         }
5093
5094         /* FW returned values are in units of 100msec */
5095         info->driver_polling_freq =
5096                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5097         info->master_func_wait_period =
5098                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5099         info->normal_func_wait_period =
5100                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5101         info->master_func_wait_period_after_reset =
5102                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5103         info->max_bailout_time_after_reset =
5104                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5105         info->status_regs[BNXT_FW_STATUS_REG] =
5106                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5107         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5108                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5109         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5110                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5111         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5112                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5113         info->reg_array_cnt =
5114                 rte_le_to_cpu_32(resp->reg_array_cnt);
5115
5116         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5117                 rc = -EINVAL;
5118                 goto err;
5119         }
5120
5121         for (i = 0; i < info->reg_array_cnt; i++) {
5122                 info->reset_reg[i] =
5123                         rte_le_to_cpu_32(resp->reset_reg[i]);
5124                 info->reset_reg_val[i] =
5125                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5126                 info->delay_after_reset[i] =
5127                         resp->delay_after_reset[i];
5128         }
5129 err:
5130         HWRM_UNLOCK();
5131
5132         /* Map the FW status registers */
5133         if (!rc)
5134                 rc = bnxt_map_fw_health_status_regs(bp);
5135
5136         if (rc) {
5137                 rte_free(bp->recovery_info);
5138                 bp->recovery_info = NULL;
5139         }
5140         return rc;
5141 }
5142
5143 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5144 {
5145         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5146         struct hwrm_fw_reset_input req = {0};
5147         int rc;
5148
5149         if (!BNXT_PF(bp))
5150                 return -EOPNOTSUPP;
5151
5152         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5153
5154         req.embedded_proc_type =
5155                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5156         req.selfrst_status =
5157                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5158         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5159
5160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5161                                     BNXT_USE_KONG(bp));
5162
5163         HWRM_CHECK_RESULT();
5164         HWRM_UNLOCK();
5165
5166         return rc;
5167 }
5168
5169 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5170 {
5171         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5172         struct hwrm_port_ts_query_input req = {0};
5173         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5174         uint32_t flags = 0;
5175         int rc;
5176
5177         if (!ptp)
5178                 return 0;
5179
5180         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5181
5182         switch (path) {
5183         case BNXT_PTP_FLAGS_PATH_TX:
5184                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5185                 break;
5186         case BNXT_PTP_FLAGS_PATH_RX:
5187                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5188                 break;
5189         case BNXT_PTP_FLAGS_CURRENT_TIME:
5190                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5191                 break;
5192         }
5193
5194         req.flags = rte_cpu_to_le_32(flags);
5195         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5196
5197         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5198
5199         HWRM_CHECK_RESULT();
5200
5201         if (timestamp) {
5202                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5203                 *timestamp |=
5204                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5205         }
5206         HWRM_UNLOCK();
5207
5208         return rc;
5209 }
5210
5211 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5212 {
5213         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5214                                         bp->hwrm_cmd_resp_addr;
5215         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5216         uint32_t flags = 0;
5217         int rc = 0;
5218
5219         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5220                 return rc;
5221
5222         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5223                 PMD_DRV_LOG(DEBUG,
5224                             "Not a PF or trusted VF. Command not supported\n");
5225                 return 0;
5226         }
5227
5228         HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5230
5231         HWRM_CHECK_RESULT();
5232         flags = rte_le_to_cpu_32(resp->flags);
5233         HWRM_UNLOCK();
5234
5235         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5236                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5237                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5238         }
5239
5240         return rc;
5241 }