drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc > 0) \
 223                         rc = -EINVAL; \
 224                 return rc; \
 225         } \
 226         if (resp->error_code) { \
 227                 rc = rte_le_to_cpu_16(resp->error_code); \
 228                 if (resp->resp_len >= 16) { \
 229                         struct hwrm_err_output *tmp_hwrm_err_op = \
 230                                                 (void *)resp; \
 231                         PMD_DRV_LOG(ERR, \
 232                                 "error %d:%d:%08x:%04x\n", \
 233                                 rc, tmp_hwrm_err_op->cmd_err, \
 234                                 rte_le_to_cpu_32(\
 235                                         tmp_hwrm_err_op->opaque_0), \
 236                                 rte_le_to_cpu_16(\
 237                                         tmp_hwrm_err_op->opaque_1)); \
 238                 } else { \
 239                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 240                 } \
 241                 rte_spinlock_unlock(&bp->hwrm_lock); \
 242                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 243                         rc = -EACCES; \
 244                 else if (rc > 0) \
 245                         rc = -EINVAL; \
 246                 return rc; \
 247         } \
 248 } while (0)
 249
 250 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 251
 252 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 253 {
 254         int rc = 0;
 255         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 256         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 257
 258         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 259         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 260         req.mask = 0;
 261
 262         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 263
 264         HWRM_CHECK_RESULT();
 265         HWRM_UNLOCK();
 266
 267         return rc;
 268 }
 269
 270 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 271                                  struct bnxt_vnic_info *vnic,
 272                                  uint16_t vlan_count,
 273                                  struct bnxt_vlan_table_entry *vlan_table)
 274 {
 275         int rc = 0;
 276         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 277         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 278         uint32_t mask = 0;
 279
 280         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 281                 return rc;
 282
 283         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 284         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 285
 286         /* FIXME add multicast flag, when multicast adding options is supported
 287          * by ethtool.
 288          */
 289         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 290                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 291         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 292                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 293         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 294                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 295         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 296                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 297         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 298                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 299         if (vnic->mc_addr_cnt) {
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 301                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 302                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 303         }
 304         if (vlan_table) {
 305                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 306                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 307                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 308                          rte_mem_virt2iova(vlan_table));
 309                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 310         }
 311         req.mask = rte_cpu_to_le_32(mask);
 312
 313         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 314
 315         HWRM_CHECK_RESULT();
 316         HWRM_UNLOCK();
 317
 318         return rc;
 319 }
 320
 321 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 322                         uint16_t vlan_count,
 323                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 324 {
 325         int rc = 0;
 326         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 327         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 328                                                 bp->hwrm_cmd_resp_addr;
 329
 330         /*
 331          * Older HWRM versions did not support this command, and the set_rx_mask
 332          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 333          * removed from set_rx_mask call, and this command was added.
 334          *
 335          * This command is also present from 1.7.8.11 and higher,
 336          * as well as 1.7.8.0
 337          */
 338         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 339                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 340                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 341                                         (11)))
 342                                 return 0;
 343                 }
 344         }
 345         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 346         req.fid = rte_cpu_to_le_16(fid);
 347
 348         req.vlan_tag_mask_tbl_addr =
 349                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 350         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 351
 352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 353
 354         HWRM_CHECK_RESULT();
 355         HWRM_UNLOCK();
 356
 357         return rc;
 358 }
 359
 360 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 361                            struct bnxt_filter_info *filter)
 362 {
 363         int rc = 0;
 364         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 365         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 366
 367         if (filter->fw_l2_filter_id == UINT64_MAX)
 368                 return 0;
 369
 370         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 371
 372         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 373
 374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 375
 376         HWRM_CHECK_RESULT();
 377         HWRM_UNLOCK();
 378
 379         filter->fw_l2_filter_id = UINT64_MAX;
 380
 381         return 0;
 382 }
 383
 384 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 385                          uint16_t dst_id,
 386                          struct bnxt_filter_info *filter)
 387 {
 388         int rc = 0;
 389         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 390         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 391         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 392         const struct rte_eth_vmdq_rx_conf *conf =
 393                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 394         uint32_t enables = 0;
 395         uint16_t j = dst_id - 1;
 396
 397         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 398         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 399             conf->pool_map[j].pools & (1UL << j)) {
 400                 PMD_DRV_LOG(DEBUG,
 401                         "Add vlan %u to vmdq pool %u\n",
 402                         conf->pool_map[j].vlan_id, j);
 403
 404                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 405                 filter->enables |=
 406                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 407                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 408         }
 409
 410         if (filter->fw_l2_filter_id != UINT64_MAX)
 411                 bnxt_hwrm_clear_l2_filter(bp, filter);
 412
 413         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 414
 415         req.flags = rte_cpu_to_le_32(filter->flags);
 416         req.flags |=
 417         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 418
 419         enables = filter->enables |
 420               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 421         req.dst_id = rte_cpu_to_le_16(dst_id);
 422
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 425                 memcpy(req.l2_addr, filter->l2_addr,
 426                        RTE_ETHER_ADDR_LEN);
 427         if (enables &
 428             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 429                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 430                        RTE_ETHER_ADDR_LEN);
 431         if (enables &
 432             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 433                 req.l2_ovlan = filter->l2_ovlan;
 434         if (enables &
 435             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 436                 req.l2_ivlan = filter->l2_ivlan;
 437         if (enables &
 438             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 439                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 440         if (enables &
 441             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 442                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 443         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 444                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 445         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 446                 req.src_type = filter->src_type;
 447
 448         req.enables = rte_cpu_to_le_32(enables);
 449
 450         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 451
 452         HWRM_CHECK_RESULT();
 453
 454         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 455         HWRM_UNLOCK();
 456
 457         return rc;
 458 }
 459
 460 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 461 {
 462         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 463         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 464         uint32_t flags = 0;
 465         int rc;
 466
 467         if (!ptp)
 468                 return 0;
 469
 470         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 471
 472         if (ptp->rx_filter)
 473                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 474         else
 475                 flags |=
 476                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 477         if (ptp->tx_tstamp_en)
 478                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 479         else
 480                 flags |=
 481                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 482         req.flags = rte_cpu_to_le_32(flags);
 483         req.enables = rte_cpu_to_le_32
 484                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 485         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 486
 487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 488         HWRM_UNLOCK();
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 494 {
 495         int rc = 0;
 496         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 497         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 498         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 499
 500 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 501         if (ptp)
 502                 return 0;
 503
 504         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 505
 506         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509
 510         HWRM_CHECK_RESULT();
 511
 512         if (!BNXT_CHIP_THOR(bp) &&
 513             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 514                 return 0;
 515
 516         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 517                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 518
 519         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 520         if (!ptp)
 521                 return -ENOMEM;
 522
 523         if (!BNXT_CHIP_THOR(bp)) {
 524                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 525                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 526                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 527                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 528                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 529                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 530                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 531                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 532                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 533                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 534                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 535                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 536                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 537                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 538                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 539                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 540                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 541                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 542         }
 543
 544         ptp->bp = bp;
 545         bp->ptp_cfg = ptp;
 546
 547         return 0;
 548 }
 549
 550 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 551 {
 552         int rc = 0;
 553         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 554         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 555         uint16_t new_max_vfs;
 556         uint32_t flags;
 557         int i;
 558
 559         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 560
 561         req.fid = rte_cpu_to_le_16(0xffff);
 562
 563         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 564
 565         HWRM_CHECK_RESULT();
 566
 567         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 568         flags = rte_le_to_cpu_32(resp->flags);
 569         if (BNXT_PF(bp)) {
 570                 bp->pf.port_id = resp->port_id;
 571                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 572                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 573                 new_max_vfs = bp->pdev->max_vfs;
 574                 if (new_max_vfs != bp->pf.max_vfs) {
 575                         if (bp->pf.vf_info)
 576                                 rte_free(bp->pf.vf_info);
 577                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 578                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 579                         bp->pf.max_vfs = new_max_vfs;
 580                         for (i = 0; i < new_max_vfs; i++) {
 581                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 582                                 bp->pf.vf_info[i].vlan_table =
 583                                         rte_zmalloc("VF VLAN table",
 584                                                     getpagesize(),
 585                                                     getpagesize());
 586                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 587                                         PMD_DRV_LOG(ERR,
 588                                         "Fail to alloc VLAN table for VF %d\n",
 589                                         i);
 590                                 else
 591                                         rte_mem_lock_page(
 592                                                 bp->pf.vf_info[i].vlan_table);
 593                                 bp->pf.vf_info[i].vlan_as_table =
 594                                         rte_zmalloc("VF VLAN AS table",
 595                                                     getpagesize(),
 596                                                     getpagesize());
 597                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 598                                         PMD_DRV_LOG(ERR,
 599                                         "Alloc VLAN AS table for VF %d fail\n",
 600                                         i);
 601                                 else
 602                                         rte_mem_lock_page(
 603                                                bp->pf.vf_info[i].vlan_as_table);
 604                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 605                         }
 606                 }
 607         }
 608
 609         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 610         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 611         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 612         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 613         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 614         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 615         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 616         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 617         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 618         if (!BNXT_CHIP_THOR(bp))
 619                 bp->max_l2_ctx += bp->max_rx_em_flows;
 620         /* TODO: For now, do not support VMDq/RFS on VFs. */
 621         if (BNXT_PF(bp)) {
 622                 if (bp->pf.max_vfs)
 623                         bp->max_vnics = 1;
 624                 else
 625                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 626         } else {
 627                 bp->max_vnics = 1;
 628         }
 629         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 630         if (BNXT_PF(bp)) {
 631                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 632                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 633                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 634                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 635                         HWRM_UNLOCK();
 636                         bnxt_hwrm_ptp_qcfg(bp);
 637                 }
 638         }
 639
 640         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 641                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 642
 643         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 644                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 645                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 646         } else {
 647                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 648         }
 649
 650         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 651                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 652         else
 653                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 654
 655         HWRM_UNLOCK();
 656
 657         return rc;
 658 }
 659
 660 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 661 {
 662         int rc;
 663
 664         rc = __bnxt_hwrm_func_qcaps(bp);
 665         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 666                 rc = bnxt_alloc_ctx_mem(bp);
 667                 if (rc)
 668                         return rc;
 669
 670                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 671                 if (!rc)
 672                         bp->flags |= BNXT_FLAG_NEW_RM;
 673         }
 674
 675         return rc;
 676 }
 677
 678 int bnxt_hwrm_func_reset(struct bnxt *bp)
 679 {
 680         int rc = 0;
 681         struct hwrm_func_reset_input req = {.req_type = 0 };
 682         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 683
 684         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 685
 686         req.enables = rte_cpu_to_le_32(0);
 687
 688         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 689
 690         HWRM_CHECK_RESULT();
 691         HWRM_UNLOCK();
 692
 693         return rc;
 694 }
 695
 696 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 697 {
 698         int rc;
 699         uint32_t flags = 0;
 700         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 701         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 702
 703         if (bp->flags & BNXT_FLAG_REGISTERED)
 704                 return 0;
 705
 706         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 707         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 708                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 709
 710         /* PFs and trusted VFs should indicate the support of the
 711          * Master capability on non Stingray platform
 712          */
 713         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 714                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 715
 716         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 717         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 718                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 719         req.ver_maj = RTE_VER_YEAR;
 720         req.ver_min = RTE_VER_MONTH;
 721         req.ver_upd = RTE_VER_MINOR;
 722
 723         if (BNXT_PF(bp)) {
 724                 req.enables |= rte_cpu_to_le_32(
 725                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 726                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 727                        RTE_MIN(sizeof(req.vf_req_fwd),
 728                                sizeof(bp->pf.vf_req_fwd)));
 729
 730                 /*
 731                  * PF can sniff HWRM API issued by VF. This can be set up by
 732                  * linux driver and inherited by the DPDK PF driver. Clear
 733                  * this HWRM sniffer list in FW because DPDK PF driver does
 734                  * not support this.
 735                  */
 736                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 737         }
 738
 739         req.flags = rte_cpu_to_le_32(flags);
 740
 741         req.async_event_fwd[0] |=
 742                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 743                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 744                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 745                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 746                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 747         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 748                 req.async_event_fwd[0] |=
 749                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 750         req.async_event_fwd[1] |=
 751                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 752                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 753
 754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 755
 756         HWRM_CHECK_RESULT();
 757
 758         flags = rte_le_to_cpu_32(resp->flags);
 759         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 760                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 761
 762         HWRM_UNLOCK();
 763
 764         bp->flags |= BNXT_FLAG_REGISTERED;
 765
 766         return rc;
 767 }
 768
 769 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 770 {
 771         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 772                 return 0;
 773
 774         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 775 }
 776
 777 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 778 {
 779         int rc;
 780         uint32_t flags = 0;
 781         uint32_t enables;
 782         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 783         struct hwrm_func_vf_cfg_input req = {0};
 784
 785         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 786
 787         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 788                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 789                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 790                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 791                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 792
 793         if (BNXT_HAS_RING_GRPS(bp)) {
 794                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 795                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 796         }
 797
 798         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 799         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 800                                             AGG_RING_MULTIPLIER);
 801         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 802                                              bp->tx_nr_rings +
 803                                              BNXT_NUM_ASYNC_CPR(bp));
 804         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 805                                               bp->tx_nr_rings +
 806                                               BNXT_NUM_ASYNC_CPR(bp));
 807         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 808         if (bp->vf_resv_strategy ==
 809             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 810                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 811                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 812                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 813                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 814                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 815                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 816         }
 817
 818         if (test)
 819                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 820                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 821                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 822                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 823                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 824                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 825
 826         if (test && BNXT_HAS_RING_GRPS(bp))
 827                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 828
 829         req.flags = rte_cpu_to_le_32(flags);
 830         req.enables |= rte_cpu_to_le_32(enables);
 831
 832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 833
 834         if (test)
 835                 HWRM_CHECK_RESULT_SILENT();
 836         else
 837                 HWRM_CHECK_RESULT();
 838
 839         HWRM_UNLOCK();
 840         return rc;
 841 }
 842
 843 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 844 {
 845         int rc;
 846         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 847         struct hwrm_func_resource_qcaps_input req = {0};
 848
 849         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 850         req.fid = rte_cpu_to_le_16(0xffff);
 851
 852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 853
 854         HWRM_CHECK_RESULT();
 855
 856         if (BNXT_VF(bp)) {
 857                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 858                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 859                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 860                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 861                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 862                 /* func_resource_qcaps does not return max_rx_em_flows.
 863                  * So use the value provided by func_qcaps.
 864                  */
 865                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 866                 if (!BNXT_CHIP_THOR(bp))
 867                         bp->max_l2_ctx += bp->max_rx_em_flows;
 868                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 869                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 870         }
 871         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 872         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 873         if (bp->vf_resv_strategy >
 874             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 875                 bp->vf_resv_strategy =
 876                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 877
 878         HWRM_UNLOCK();
 879         return rc;
 880 }
 881
 882 int bnxt_hwrm_ver_get(struct bnxt *bp)
 883 {
 884         int rc = 0;
 885         struct hwrm_ver_get_input req = {.req_type = 0 };
 886         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 887         uint32_t fw_version;
 888         uint16_t max_resp_len;
 889         char type[RTE_MEMZONE_NAMESIZE];
 890         uint32_t dev_caps_cfg;
 891
 892         bp->max_req_len = HWRM_MAX_REQ_LEN;
 893         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 894
 895         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 896         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 897         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 898
 899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 900
 901         if (bp->flags & BNXT_FLAG_FW_RESET)
 902                 HWRM_CHECK_RESULT_SILENT();
 903         else
 904                 HWRM_CHECK_RESULT();
 905
 906         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 907                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 908                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 909                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 910         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 911                      (resp->hwrm_fw_min_8b << 16) |
 912                      (resp->hwrm_fw_bld_8b << 8) |
 913                      resp->hwrm_fw_rsvd_8b;
 914         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 915                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 916
 917         fw_version = resp->hwrm_intf_maj_8b << 16;
 918         fw_version |= resp->hwrm_intf_min_8b << 8;
 919         fw_version |= resp->hwrm_intf_upd_8b;
 920         bp->hwrm_spec_code = fw_version;
 921
 922         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 923                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 924                 rc = -EINVAL;
 925                 goto error;
 926         }
 927
 928         if (bp->max_req_len > resp->max_req_win_len) {
 929                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 930                 rc = -EINVAL;
 931         }
 932         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 933         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 934         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 935                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 936
 937         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 938         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 939
 940         if (bp->max_resp_len != max_resp_len) {
 941                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 942                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 943                         bp->pdev->addr.devid, bp->pdev->addr.function);
 944
 945                 rte_free(bp->hwrm_cmd_resp_addr);
 946
 947                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 948                 if (bp->hwrm_cmd_resp_addr == NULL) {
 949                         rc = -ENOMEM;
 950                         goto error;
 951                 }
 952                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 953                 bp->hwrm_cmd_resp_dma_addr =
 954                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 955                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 956                         PMD_DRV_LOG(ERR,
 957                         "Unable to map response buffer to physical memory.\n");
 958                         rc = -ENOMEM;
 959                         goto error;
 960                 }
 961                 bp->max_resp_len = max_resp_len;
 962         }
 963
 964         if ((dev_caps_cfg &
 965                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 966             (dev_caps_cfg &
 967              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 968                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 969                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 970         }
 971
 972         if (((dev_caps_cfg &
 973               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 974              (dev_caps_cfg &
 975               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 976             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 977                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 978                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 979                         bp->pdev->addr.devid, bp->pdev->addr.function);
 980
 981                 rte_free(bp->hwrm_short_cmd_req_addr);
 982
 983                 bp->hwrm_short_cmd_req_addr =
 984                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 985                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 986                         rc = -ENOMEM;
 987                         goto error;
 988                 }
 989                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 990                 bp->hwrm_short_cmd_req_dma_addr =
 991                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 992                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 993                         rte_free(bp->hwrm_short_cmd_req_addr);
 994                         PMD_DRV_LOG(ERR,
 995                                 "Unable to map buffer to physical memory.\n");
 996                         rc = -ENOMEM;
 997                         goto error;
 998                 }
 999         }
1000         if (dev_caps_cfg &
1001             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1002                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1003                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1004         }
1005         if (dev_caps_cfg &
1006             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1007                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1008
1009 error:
1010         HWRM_UNLOCK();
1011         return rc;
1012 }
1013
1014 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1015 {
1016         int rc;
1017         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1018         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1019
1020         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1021                 return 0;
1022
1023         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1024         req.flags = flags;
1025
1026         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1027
1028         HWRM_CHECK_RESULT();
1029         HWRM_UNLOCK();
1030
1031         return rc;
1032 }
1033
1034 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1035 {
1036         int rc = 0;
1037         struct hwrm_port_phy_cfg_input req = {0};
1038         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1039         uint32_t enables = 0;
1040
1041         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1042
1043         if (conf->link_up) {
1044                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1045                 if (bp->link_info.auto_mode && conf->link_speed) {
1046                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1047                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1048                 }
1049
1050                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1051                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1052                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1053                 /*
1054                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1055                  * any auto mode, even "none".
1056                  */
1057                 if (!conf->link_speed) {
1058                         /* No speeds specified. Enable AutoNeg - all speeds */
1059                         req.auto_mode =
1060                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1061                 }
1062                 /* AutoNeg - Advertise speeds specified. */
1063                 if (conf->auto_link_speed_mask &&
1064                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1065                         req.auto_mode =
1066                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1067                         req.auto_link_speed_mask =
1068                                 conf->auto_link_speed_mask;
1069                         enables |=
1070                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1071                 }
1072
1073                 req.auto_duplex = conf->duplex;
1074                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1075                 req.auto_pause = conf->auto_pause;
1076                 req.force_pause = conf->force_pause;
1077                 /* Set force_pause if there is no auto or if there is a force */
1078                 if (req.auto_pause && !req.force_pause)
1079                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1080                 else
1081                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1082
1083                 req.enables = rte_cpu_to_le_32(enables);
1084         } else {
1085                 req.flags =
1086                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1087                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1088         }
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1091
1092         HWRM_CHECK_RESULT();
1093         HWRM_UNLOCK();
1094
1095         return rc;
1096 }
1097
1098 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1099                                    struct bnxt_link_info *link_info)
1100 {
1101         int rc = 0;
1102         struct hwrm_port_phy_qcfg_input req = {0};
1103         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1104
1105         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1106
1107         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1108
1109         HWRM_CHECK_RESULT();
1110
1111         link_info->phy_link_status = resp->link;
1112         link_info->link_up =
1113                 (link_info->phy_link_status ==
1114                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1115         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1116         link_info->duplex = resp->duplex_cfg;
1117         link_info->pause = resp->pause;
1118         link_info->auto_pause = resp->auto_pause;
1119         link_info->force_pause = resp->force_pause;
1120         link_info->auto_mode = resp->auto_mode;
1121         link_info->phy_type = resp->phy_type;
1122         link_info->media_type = resp->media_type;
1123
1124         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1125         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1126         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1127         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1128         link_info->phy_ver[0] = resp->phy_maj;
1129         link_info->phy_ver[1] = resp->phy_min;
1130         link_info->phy_ver[2] = resp->phy_bld;
1131
1132         HWRM_UNLOCK();
1133
1134         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1135         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1136         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1137         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1138         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1139                     link_info->auto_link_speed_mask);
1140         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1141                     link_info->force_link_speed);
1142
1143         return rc;
1144 }
1145
1146 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1147 {
1148         int rc = 0;
1149         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1150         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1151         int i;
1152
1153         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1154
1155         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1156         /* HWRM Version >= 1.9.1 */
1157         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1158                 req.drv_qmap_cap =
1159                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1161
1162         HWRM_CHECK_RESULT();
1163
1164 #define GET_QUEUE_INFO(x) \
1165         bp->cos_queue[x].id = resp->queue_id##x; \
1166         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1167
1168         GET_QUEUE_INFO(0);
1169         GET_QUEUE_INFO(1);
1170         GET_QUEUE_INFO(2);
1171         GET_QUEUE_INFO(3);
1172         GET_QUEUE_INFO(4);
1173         GET_QUEUE_INFO(5);
1174         GET_QUEUE_INFO(6);
1175         GET_QUEUE_INFO(7);
1176
1177         HWRM_UNLOCK();
1178
1179         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1180                 bp->tx_cosq_id = bp->cos_queue[0].id;
1181         } else {
1182                 /* iterate and find the COSq profile to use for Tx */
1183                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1184                         if (bp->cos_queue[i].profile ==
1185                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1186                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1187                                 break;
1188                         }
1189                 }
1190         }
1191
1192         bp->max_tc = resp->max_configurable_queues;
1193         bp->max_lltc = resp->max_configurable_lossless_queues;
1194         if (bp->max_tc > BNXT_MAX_QUEUE)
1195                 bp->max_tc = BNXT_MAX_QUEUE;
1196         bp->max_q = bp->max_tc;
1197
1198         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1199
1200         return rc;
1201 }
1202
1203 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1204                          struct bnxt_ring *ring,
1205                          uint32_t ring_type, uint32_t map_index,
1206                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1207 {
1208         int rc = 0;
1209         uint32_t enables = 0;
1210         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1211         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1212         struct rte_mempool *mb_pool;
1213         uint16_t rx_buf_size;
1214
1215         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1216
1217         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1218         req.fbo = rte_cpu_to_le_32(0);
1219         /* Association of ring index with doorbell index */
1220         req.logical_id = rte_cpu_to_le_16(map_index);
1221         req.length = rte_cpu_to_le_32(ring->ring_size);
1222
1223         switch (ring_type) {
1224         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1225                 req.ring_type = ring_type;
1226                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1227                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1228                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1229                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1230                         enables |=
1231                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1232                 break;
1233         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1234                 req.ring_type = ring_type;
1235                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1236                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1237                 if (BNXT_CHIP_THOR(bp)) {
1238                         mb_pool = bp->rx_queues[0]->mb_pool;
1239                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1240                                       RTE_PKTMBUF_HEADROOM;
1241                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1242                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1243                         enables |=
1244                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1245                 }
1246                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1247                         enables |=
1248                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1249                 break;
1250         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1251                 req.ring_type = ring_type;
1252                 if (BNXT_HAS_NQ(bp)) {
1253                         /* Association of cp ring with nq */
1254                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1255                         enables |=
1256                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1257                 }
1258                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1259                 break;
1260         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1261                 req.ring_type = ring_type;
1262                 req.page_size = BNXT_PAGE_SHFT;
1263                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1264                 break;
1265         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1266                 req.ring_type = ring_type;
1267                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1268
1269                 mb_pool = bp->rx_queues[0]->mb_pool;
1270                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1271                               RTE_PKTMBUF_HEADROOM;
1272                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1273                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1274
1275                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1276                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1277                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1278                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1279                 break;
1280         default:
1281                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1282                         ring_type);
1283                 HWRM_UNLOCK();
1284                 return -EINVAL;
1285         }
1286         req.enables = rte_cpu_to_le_32(enables);
1287
1288         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1289
1290         if (rc || resp->error_code) {
1291                 if (rc == 0 && resp->error_code)
1292                         rc = rte_le_to_cpu_16(resp->error_code);
1293                 switch (ring_type) {
1294                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1295                         PMD_DRV_LOG(ERR,
1296                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1297                         HWRM_UNLOCK();
1298                         return rc;
1299                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1300                         PMD_DRV_LOG(ERR,
1301                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1302                         HWRM_UNLOCK();
1303                         return rc;
1304                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1305                         PMD_DRV_LOG(ERR,
1306                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1307                                     rc);
1308                         HWRM_UNLOCK();
1309                         return rc;
1310                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1311                         PMD_DRV_LOG(ERR,
1312                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1313                         HWRM_UNLOCK();
1314                         return rc;
1315                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1316                         PMD_DRV_LOG(ERR,
1317                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1318                         HWRM_UNLOCK();
1319                         return rc;
1320                 default:
1321                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1322                         HWRM_UNLOCK();
1323                         return rc;
1324                 }
1325         }
1326
1327         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1328         HWRM_UNLOCK();
1329         return rc;
1330 }
1331
1332 int bnxt_hwrm_ring_free(struct bnxt *bp,
1333                         struct bnxt_ring *ring, uint32_t ring_type)
1334 {
1335         int rc;
1336         struct hwrm_ring_free_input req = {.req_type = 0 };
1337         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1338
1339         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1340
1341         req.ring_type = ring_type;
1342         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1343
1344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1345
1346         if (rc || resp->error_code) {
1347                 if (rc == 0 && resp->error_code)
1348                         rc = rte_le_to_cpu_16(resp->error_code);
1349                 HWRM_UNLOCK();
1350
1351                 switch (ring_type) {
1352                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1353                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1354                                 rc);
1355                         return rc;
1356                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1357                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1358                                 rc);
1359                         return rc;
1360                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1361                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1362                                 rc);
1363                         return rc;
1364                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1365                         PMD_DRV_LOG(ERR,
1366                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1367                         return rc;
1368                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1369                         PMD_DRV_LOG(ERR,
1370                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1371                         return rc;
1372                 default:
1373                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1374                         return rc;
1375                 }
1376         }
1377         HWRM_UNLOCK();
1378         return 0;
1379 }
1380
1381 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1382 {
1383         int rc = 0;
1384         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1385         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1386
1387         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1388
1389         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1390         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1391         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1392         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1393
1394         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1395
1396         HWRM_CHECK_RESULT();
1397
1398         bp->grp_info[idx].fw_grp_id =
1399             rte_le_to_cpu_16(resp->ring_group_id);
1400
1401         HWRM_UNLOCK();
1402
1403         return rc;
1404 }
1405
1406 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1407 {
1408         int rc;
1409         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1410         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1411
1412         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1413
1414         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1415
1416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1417
1418         HWRM_CHECK_RESULT();
1419         HWRM_UNLOCK();
1420
1421         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1422         return rc;
1423 }
1424
1425 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1426 {
1427         int rc = 0;
1428         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1429         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1430
1431         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1432                 return rc;
1433
1434         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1435
1436         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1437
1438         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1439
1440         HWRM_CHECK_RESULT();
1441         HWRM_UNLOCK();
1442
1443         return rc;
1444 }
1445
1446 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1447                                 unsigned int idx __rte_unused)
1448 {
1449         int rc;
1450         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1451         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1452
1453         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1454
1455         req.update_period_ms = rte_cpu_to_le_32(0);
1456
1457         req.stats_dma_addr =
1458             rte_cpu_to_le_64(cpr->hw_stats_map);
1459
1460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1461
1462         HWRM_CHECK_RESULT();
1463
1464         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1465
1466         HWRM_UNLOCK();
1467
1468         return rc;
1469 }
1470
1471 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1472                                 unsigned int idx __rte_unused)
1473 {
1474         int rc;
1475         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1476         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1477
1478         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1479
1480         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1481
1482         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1483
1484         HWRM_CHECK_RESULT();
1485         HWRM_UNLOCK();
1486
1487         return rc;
1488 }
1489
1490 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1491 {
1492         int rc = 0, i, j;
1493         struct hwrm_vnic_alloc_input req = { 0 };
1494         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1495
1496         if (!BNXT_HAS_RING_GRPS(bp))
1497                 goto skip_ring_grps;
1498
1499         /* map ring groups to this vnic */
1500         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1501                 vnic->start_grp_id, vnic->end_grp_id);
1502         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1503                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1504
1505         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1506         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1507         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1508         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1509
1510 skip_ring_grps:
1511         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1512                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1513         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1514
1515         if (vnic->func_default)
1516                 req.flags =
1517                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1519
1520         HWRM_CHECK_RESULT();
1521
1522         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1523         HWRM_UNLOCK();
1524         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1525         return rc;
1526 }
1527
1528 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1529                                         struct bnxt_vnic_info *vnic,
1530                                         struct bnxt_plcmodes_cfg *pmode)
1531 {
1532         int rc = 0;
1533         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1534         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1535
1536         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1537
1538         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1539
1540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1541
1542         HWRM_CHECK_RESULT();
1543
1544         pmode->flags = rte_le_to_cpu_32(resp->flags);
1545         /* dflt_vnic bit doesn't exist in the _cfg command */
1546         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1547         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1548         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1549         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1550
1551         HWRM_UNLOCK();
1552
1553         return rc;
1554 }
1555
1556 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1557                                        struct bnxt_vnic_info *vnic,
1558                                        struct bnxt_plcmodes_cfg *pmode)
1559 {
1560         int rc = 0;
1561         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1562         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1563
1564         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1565                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1566                 return rc;
1567         }
1568
1569         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1570
1571         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1572         req.flags = rte_cpu_to_le_32(pmode->flags);
1573         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1574         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1575         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1576         req.enables = rte_cpu_to_le_32(
1577             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1578             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1579             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1580         );
1581
1582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1583
1584         HWRM_CHECK_RESULT();
1585         HWRM_UNLOCK();
1586
1587         return rc;
1588 }
1589
1590 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1591 {
1592         int rc = 0;
1593         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1594         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1595         struct bnxt_plcmodes_cfg pmodes = { 0 };
1596         uint32_t ctx_enable_flag = 0;
1597         uint32_t enables = 0;
1598
1599         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1600                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1601                 return rc;
1602         }
1603
1604         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1605         if (rc)
1606                 return rc;
1607
1608         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1609
1610         if (BNXT_CHIP_THOR(bp)) {
1611                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1612                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1613                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1614
1615                 req.default_rx_ring_id =
1616                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1617                 req.default_cmpl_ring_id =
1618                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1619                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1620                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1621                 goto config_mru;
1622         }
1623
1624         /* Only RSS support for now TBD: COS & LB */
1625         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1626         if (vnic->lb_rule != 0xffff)
1627                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1628         if (vnic->cos_rule != 0xffff)
1629                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1630         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1631                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1632                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1633         }
1634         enables |= ctx_enable_flag;
1635         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1636         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1637         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1638         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1639
1640 config_mru:
1641         req.enables = rte_cpu_to_le_32(enables);
1642         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1643         req.mru = rte_cpu_to_le_16(vnic->mru);
1644         /* Configure default VNIC only once. */
1645         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1646                 req.flags |=
1647                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1648                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1649         }
1650         if (vnic->vlan_strip)
1651                 req.flags |=
1652                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1653         if (vnic->bd_stall)
1654                 req.flags |=
1655                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1656         if (vnic->roce_dual)
1657                 req.flags |= rte_cpu_to_le_32(
1658                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1659         if (vnic->roce_only)
1660                 req.flags |= rte_cpu_to_le_32(
1661                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1662         if (vnic->rss_dflt_cr)
1663                 req.flags |= rte_cpu_to_le_32(
1664                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1665
1666         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1667
1668         HWRM_CHECK_RESULT();
1669         HWRM_UNLOCK();
1670
1671         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1672
1673         return rc;
1674 }
1675
1676 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1677                 int16_t fw_vf_id)
1678 {
1679         int rc = 0;
1680         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1681         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1682
1683         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1684                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1685                 return rc;
1686         }
1687         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1688
1689         req.enables =
1690                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1691         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1692         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1693
1694         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1695
1696         HWRM_CHECK_RESULT();
1697
1698         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1699         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1700         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1701         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1702         vnic->mru = rte_le_to_cpu_16(resp->mru);
1703         vnic->func_default = rte_le_to_cpu_32(
1704                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1705         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1706                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1707         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1708                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1709         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1710                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1711         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1712                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1713         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1714                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1715
1716         HWRM_UNLOCK();
1717
1718         return rc;
1719 }
1720
1721 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1722                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1723 {
1724         int rc = 0;
1725         uint16_t ctx_id;
1726         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1727         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1728                                                 bp->hwrm_cmd_resp_addr;
1729
1730         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1731
1732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1733         HWRM_CHECK_RESULT();
1734
1735         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1736         if (!BNXT_HAS_RING_GRPS(bp))
1737                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1738         else if (ctx_idx == 0)
1739                 vnic->rss_rule = ctx_id;
1740
1741         HWRM_UNLOCK();
1742
1743         return rc;
1744 }
1745
1746 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1747                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1748 {
1749         int rc = 0;
1750         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1751         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1752                                                 bp->hwrm_cmd_resp_addr;
1753
1754         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1755                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1756                 return rc;
1757         }
1758         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1759
1760         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1761
1762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763
1764         HWRM_CHECK_RESULT();
1765         HWRM_UNLOCK();
1766
1767         return rc;
1768 }
1769
1770 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1771 {
1772         int rc = 0;
1773         struct hwrm_vnic_free_input req = {.req_type = 0 };
1774         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1775
1776         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1777                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1778                 return rc;
1779         }
1780
1781         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1782
1783         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1784
1785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786
1787         HWRM_CHECK_RESULT();
1788         HWRM_UNLOCK();
1789
1790         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1791         /* Configure default VNIC again if necessary. */
1792         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1793                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1794
1795         return rc;
1796 }
1797
1798 static int
1799 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1800 {
1801         int i;
1802         int rc = 0;
1803         int nr_ctxs = vnic->num_lb_ctxts;
1804         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1805         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1806
1807         for (i = 0; i < nr_ctxs; i++) {
1808                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1809
1810                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1811                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1812                 req.hash_mode_flags = vnic->hash_mode;
1813
1814                 req.hash_key_tbl_addr =
1815                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1816
1817                 req.ring_grp_tbl_addr =
1818                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1819                                          i * HW_HASH_INDEX_SIZE);
1820                 req.ring_table_pair_index = i;
1821                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1822
1823                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1824                                             BNXT_USE_CHIMP_MB);
1825
1826                 HWRM_CHECK_RESULT();
1827                 HWRM_UNLOCK();
1828         }
1829
1830         return rc;
1831 }
1832
1833 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1834                            struct bnxt_vnic_info *vnic)
1835 {
1836         int rc = 0;
1837         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1838         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1839
1840         if (!vnic->rss_table)
1841                 return 0;
1842
1843         if (BNXT_CHIP_THOR(bp))
1844                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1845
1846         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1847
1848         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1849         req.hash_mode_flags = vnic->hash_mode;
1850
1851         req.ring_grp_tbl_addr =
1852             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1853         req.hash_key_tbl_addr =
1854             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1855         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1856         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1857
1858         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1859
1860         HWRM_CHECK_RESULT();
1861         HWRM_UNLOCK();
1862
1863         return rc;
1864 }
1865
1866 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1867                         struct bnxt_vnic_info *vnic)
1868 {
1869         int rc = 0;
1870         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1871         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1872         uint16_t size;
1873
1874         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1875                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1876                 return rc;
1877         }
1878
1879         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1880
1881         req.flags = rte_cpu_to_le_32(
1882                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1883
1884         req.enables = rte_cpu_to_le_32(
1885                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1886
1887         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1888         size -= RTE_PKTMBUF_HEADROOM;
1889         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1890
1891         req.jumbo_thresh = rte_cpu_to_le_16(size);
1892         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1893
1894         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1895
1896         HWRM_CHECK_RESULT();
1897         HWRM_UNLOCK();
1898
1899         return rc;
1900 }
1901
1902 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1903                         struct bnxt_vnic_info *vnic, bool enable)
1904 {
1905         int rc = 0;
1906         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1907         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1908
1909         if (BNXT_CHIP_THOR(bp))
1910                 return 0;
1911
1912         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1913
1914         if (enable) {
1915                 req.enables = rte_cpu_to_le_32(
1916                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1917                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1918                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1919                 req.flags = rte_cpu_to_le_32(
1920                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1921                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1922                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1923                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1924                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1925                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1926                 req.max_agg_segs = rte_cpu_to_le_16(5);
1927                 req.max_aggs =
1928                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1929                 req.min_agg_len = rte_cpu_to_le_32(512);
1930         }
1931         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1932
1933         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1934
1935         HWRM_CHECK_RESULT();
1936         HWRM_UNLOCK();
1937
1938         return rc;
1939 }
1940
1941 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1942 {
1943         struct hwrm_func_cfg_input req = {0};
1944         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1945         int rc;
1946
1947         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1948         req.enables = rte_cpu_to_le_32(
1949                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1950         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1951         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1952
1953         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1954
1955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1956         HWRM_CHECK_RESULT();
1957         HWRM_UNLOCK();
1958
1959         bp->pf.vf_info[vf].random_mac = false;
1960
1961         return rc;
1962 }
1963
1964 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1965                                   uint64_t *dropped)
1966 {
1967         int rc = 0;
1968         struct hwrm_func_qstats_input req = {.req_type = 0};
1969         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1970
1971         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1972
1973         req.fid = rte_cpu_to_le_16(fid);
1974
1975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1976
1977         HWRM_CHECK_RESULT();
1978
1979         if (dropped)
1980                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1981
1982         HWRM_UNLOCK();
1983
1984         return rc;
1985 }
1986
1987 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1988                           struct rte_eth_stats *stats)
1989 {
1990         int rc = 0;
1991         struct hwrm_func_qstats_input req = {.req_type = 0};
1992         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1993
1994         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1995
1996         req.fid = rte_cpu_to_le_16(fid);
1997
1998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999
2000         HWRM_CHECK_RESULT();
2001
2002         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2003         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2004         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2005         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2006         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2007         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2008
2009         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2010         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2011         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2012         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2013         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2014         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2015
2016         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2017         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2018         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2019
2020         HWRM_UNLOCK();
2021
2022         return rc;
2023 }
2024
2025 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2026 {
2027         int rc = 0;
2028         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2029         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2030
2031         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2032
2033         req.fid = rte_cpu_to_le_16(fid);
2034
2035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2036
2037         HWRM_CHECK_RESULT();
2038         HWRM_UNLOCK();
2039
2040         return rc;
2041 }
2042
2043 /*
2044  * HWRM utility functions
2045  */
2046
2047 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2048 {
2049         unsigned int i;
2050         int rc = 0;
2051
2052         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2053                 struct bnxt_tx_queue *txq;
2054                 struct bnxt_rx_queue *rxq;
2055                 struct bnxt_cp_ring_info *cpr;
2056
2057                 if (i >= bp->rx_cp_nr_rings) {
2058                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2059                         cpr = txq->cp_ring;
2060                 } else {
2061                         rxq = bp->rx_queues[i];
2062                         cpr = rxq->cp_ring;
2063                 }
2064
2065                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2066                 if (rc)
2067                         return rc;
2068         }
2069         return 0;
2070 }
2071
2072 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2073 {
2074         int rc;
2075         unsigned int i;
2076         struct bnxt_cp_ring_info *cpr;
2077
2078         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2079
2080                 if (i >= bp->rx_cp_nr_rings) {
2081                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2082                 } else {
2083                         cpr = bp->rx_queues[i]->cp_ring;
2084                         if (BNXT_HAS_RING_GRPS(bp))
2085                                 bp->grp_info[i].fw_stats_ctx = -1;
2086                 }
2087                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2088                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2089                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2090                         if (rc)
2091                                 return rc;
2092                 }
2093         }
2094         return 0;
2095 }
2096
2097 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2098 {
2099         unsigned int i;
2100         int rc = 0;
2101
2102         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2103                 struct bnxt_tx_queue *txq;
2104                 struct bnxt_rx_queue *rxq;
2105                 struct bnxt_cp_ring_info *cpr;
2106
2107                 if (i >= bp->rx_cp_nr_rings) {
2108                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2109                         cpr = txq->cp_ring;
2110                 } else {
2111                         rxq = bp->rx_queues[i];
2112                         cpr = rxq->cp_ring;
2113                 }
2114
2115                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2116
2117                 if (rc)
2118                         return rc;
2119         }
2120         return rc;
2121 }
2122
2123 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2124 {
2125         uint16_t idx;
2126         uint32_t rc = 0;
2127
2128         if (!BNXT_HAS_RING_GRPS(bp))
2129                 return 0;
2130
2131         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2132
2133                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2134                         continue;
2135
2136                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2137
2138                 if (rc)
2139                         return rc;
2140         }
2141         return rc;
2142 }
2143
2144 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2145 {
2146         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2147
2148         bnxt_hwrm_ring_free(bp, cp_ring,
2149                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2150         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2151         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2152                                      sizeof(*cpr->cp_desc_ring));
2153         cpr->cp_raw_cons = 0;
2154         cpr->valid = 0;
2155 }
2156
2157 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2158 {
2159         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2160
2161         bnxt_hwrm_ring_free(bp, cp_ring,
2162                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2163         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2164         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2165                         sizeof(*cpr->cp_desc_ring));
2166         cpr->cp_raw_cons = 0;
2167         cpr->valid = 0;
2168 }
2169
2170 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2171 {
2172         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2173         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2174         struct bnxt_ring *ring = rxr->rx_ring_struct;
2175         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2176
2177         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2178                 bnxt_hwrm_ring_free(bp, ring,
2179                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2180                 ring->fw_ring_id = INVALID_HW_RING_ID;
2181                 if (BNXT_HAS_RING_GRPS(bp))
2182                         bp->grp_info[queue_index].rx_fw_ring_id =
2183                                                         INVALID_HW_RING_ID;
2184                 memset(rxr->rx_desc_ring, 0,
2185                        rxr->rx_ring_struct->ring_size *
2186                        sizeof(*rxr->rx_desc_ring));
2187                 memset(rxr->rx_buf_ring, 0,
2188                        rxr->rx_ring_struct->ring_size *
2189                        sizeof(*rxr->rx_buf_ring));
2190                 rxr->rx_prod = 0;
2191         }
2192         ring = rxr->ag_ring_struct;
2193         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2194                 bnxt_hwrm_ring_free(bp, ring,
2195                                     BNXT_CHIP_THOR(bp) ?
2196                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2197                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2198                 ring->fw_ring_id = INVALID_HW_RING_ID;
2199                 memset(rxr->ag_buf_ring, 0,
2200                        rxr->ag_ring_struct->ring_size *
2201                        sizeof(*rxr->ag_buf_ring));
2202                 rxr->ag_prod = 0;
2203                 if (BNXT_HAS_RING_GRPS(bp))
2204                         bp->grp_info[queue_index].ag_fw_ring_id =
2205                                                         INVALID_HW_RING_ID;
2206         }
2207         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2208                 bnxt_free_cp_ring(bp, cpr);
2209                 if (rxq->nq_ring)
2210                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2211         }
2212
2213         if (BNXT_HAS_RING_GRPS(bp))
2214                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2215 }
2216
2217 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2218 {
2219         unsigned int i;
2220
2221         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2222                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2223                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2224                 struct bnxt_ring *ring = txr->tx_ring_struct;
2225                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2226
2227                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2228                         bnxt_hwrm_ring_free(bp, ring,
2229                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2230                         ring->fw_ring_id = INVALID_HW_RING_ID;
2231                         memset(txr->tx_desc_ring, 0,
2232                                         txr->tx_ring_struct->ring_size *
2233                                         sizeof(*txr->tx_desc_ring));
2234                         memset(txr->tx_buf_ring, 0,
2235                                         txr->tx_ring_struct->ring_size *
2236                                         sizeof(*txr->tx_buf_ring));
2237                         txr->tx_prod = 0;
2238                         txr->tx_cons = 0;
2239                 }
2240                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2241                         bnxt_free_cp_ring(bp, cpr);
2242                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2243                         if (txq->nq_ring)
2244                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2245                 }
2246         }
2247
2248         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2249                 bnxt_free_hwrm_rx_ring(bp, i);
2250
2251         return 0;
2252 }
2253
2254 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2255 {
2256         uint16_t i;
2257         uint32_t rc = 0;
2258
2259         if (!BNXT_HAS_RING_GRPS(bp))
2260                 return 0;
2261
2262         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2263                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2264                 if (rc)
2265                         return rc;
2266         }
2267         return rc;
2268 }
2269
2270 void bnxt_free_hwrm_resources(struct bnxt *bp)
2271 {
2272         /* Release memzone */
2273         rte_free(bp->hwrm_cmd_resp_addr);
2274         rte_free(bp->hwrm_short_cmd_req_addr);
2275         bp->hwrm_cmd_resp_addr = NULL;
2276         bp->hwrm_short_cmd_req_addr = NULL;
2277         bp->hwrm_cmd_resp_dma_addr = 0;
2278         bp->hwrm_short_cmd_req_dma_addr = 0;
2279 }
2280
2281 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2282 {
2283         struct rte_pci_device *pdev = bp->pdev;
2284         char type[RTE_MEMZONE_NAMESIZE];
2285
2286         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2287                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2288         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2289         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2290         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2291         if (bp->hwrm_cmd_resp_addr == NULL)
2292                 return -ENOMEM;
2293         bp->hwrm_cmd_resp_dma_addr =
2294                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2295         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2296                 PMD_DRV_LOG(ERR,
2297                         "unable to map response address to physical memory\n");
2298                 return -ENOMEM;
2299         }
2300         rte_spinlock_init(&bp->hwrm_lock);
2301
2302         return 0;
2303 }
2304
2305 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2306 {
2307         struct bnxt_filter_info *filter;
2308         int rc = 0;
2309
2310         STAILQ_FOREACH(filter, &vnic->filter, next) {
2311                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2312                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2313                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2314                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2315                 else
2316                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2317                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2318                 //if (rc)
2319                         //break;
2320         }
2321         return rc;
2322 }
2323
2324 static int
2325 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2326 {
2327         struct bnxt_filter_info *filter;
2328         struct rte_flow *flow;
2329         int rc = 0;
2330
2331         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2332                 filter = flow->filter;
2333                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2334                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2335                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2336                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2337                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2338                 else
2339                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2340
2341                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2342                 rte_free(flow);
2343                 //if (rc)
2344                         //break;
2345         }
2346         return rc;
2347 }
2348
2349 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2350 {
2351         struct bnxt_filter_info *filter;
2352         int rc = 0;
2353
2354         STAILQ_FOREACH(filter, &vnic->filter, next) {
2355                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2356                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2357                                                      filter);
2358                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2359                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2360                                                          filter);
2361                 else
2362                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2363                                                      filter);
2364                 if (rc)
2365                         break;
2366         }
2367         return rc;
2368 }
2369
2370 void bnxt_free_tunnel_ports(struct bnxt *bp)
2371 {
2372         if (bp->vxlan_port_cnt)
2373                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2374                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2375         bp->vxlan_port = 0;
2376         if (bp->geneve_port_cnt)
2377                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2378                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2379         bp->geneve_port = 0;
2380 }
2381
2382 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2383 {
2384         int i, j;
2385
2386         if (bp->vnic_info == NULL)
2387                 return;
2388
2389         /*
2390          * Cleanup VNICs in reverse order, to make sure the L2 filter
2391          * from vnic0 is last to be cleaned up.
2392          */
2393         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2394                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2395
2396                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2397                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2398                         return;
2399                 }
2400
2401                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2402
2403                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2404
2405                 if (BNXT_CHIP_THOR(bp)) {
2406                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2407                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2408                                                         vnic->fw_grp_ids[j]);
2409                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2410                         }
2411                         vnic->num_lb_ctxts = 0;
2412                 } else {
2413                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2414                         vnic->rss_rule = INVALID_HW_RING_ID;
2415                 }
2416
2417                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2418
2419                 bnxt_hwrm_vnic_free(bp, vnic);
2420
2421                 rte_free(vnic->fw_grp_ids);
2422         }
2423         /* Ring resources */
2424         bnxt_free_all_hwrm_rings(bp);
2425         bnxt_free_all_hwrm_ring_grps(bp);
2426         bnxt_free_all_hwrm_stat_ctxs(bp);
2427         bnxt_free_tunnel_ports(bp);
2428 }
2429
2430 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2431 {
2432         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2433
2434         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2435                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2436
2437         switch (conf_link_speed) {
2438         case ETH_LINK_SPEED_10M_HD:
2439         case ETH_LINK_SPEED_100M_HD:
2440                 /* FALLTHROUGH */
2441                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2442         }
2443         return hw_link_duplex;
2444 }
2445
2446 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2447 {
2448         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2449 }
2450
2451 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2452 {
2453         uint16_t eth_link_speed = 0;
2454
2455         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2456                 return ETH_LINK_SPEED_AUTONEG;
2457
2458         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2459         case ETH_LINK_SPEED_100M:
2460         case ETH_LINK_SPEED_100M_HD:
2461                 /* FALLTHROUGH */
2462                 eth_link_speed =
2463                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2464                 break;
2465         case ETH_LINK_SPEED_1G:
2466                 eth_link_speed =
2467                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2468                 break;
2469         case ETH_LINK_SPEED_2_5G:
2470                 eth_link_speed =
2471                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2472                 break;
2473         case ETH_LINK_SPEED_10G:
2474                 eth_link_speed =
2475                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2476                 break;
2477         case ETH_LINK_SPEED_20G:
2478                 eth_link_speed =
2479                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2480                 break;
2481         case ETH_LINK_SPEED_25G:
2482                 eth_link_speed =
2483                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2484                 break;
2485         case ETH_LINK_SPEED_40G:
2486                 eth_link_speed =
2487                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2488                 break;
2489         case ETH_LINK_SPEED_50G:
2490                 eth_link_speed =
2491                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2492                 break;
2493         case ETH_LINK_SPEED_100G:
2494                 eth_link_speed =
2495                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2496                 break;
2497         default:
2498                 PMD_DRV_LOG(ERR,
2499                         "Unsupported link speed %d; default to AUTO\n",
2500                         conf_link_speed);
2501                 break;
2502         }
2503         return eth_link_speed;
2504 }
2505
2506 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2507                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2508                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2509                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2510
2511 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2512 {
2513         uint32_t one_speed;
2514
2515         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2516                 return 0;
2517
2518         if (link_speed & ETH_LINK_SPEED_FIXED) {
2519                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2520
2521                 if (one_speed & (one_speed - 1)) {
2522                         PMD_DRV_LOG(ERR,
2523                                 "Invalid advertised speeds (%u) for port %u\n",
2524                                 link_speed, port_id);
2525                         return -EINVAL;
2526                 }
2527                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2528                         PMD_DRV_LOG(ERR,
2529                                 "Unsupported advertised speed (%u) for port %u\n",
2530                                 link_speed, port_id);
2531                         return -EINVAL;
2532                 }
2533         } else {
2534                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2535                         PMD_DRV_LOG(ERR,
2536                                 "Unsupported advertised speeds (%u) for port %u\n",
2537                                 link_speed, port_id);
2538                         return -EINVAL;
2539                 }
2540         }
2541         return 0;
2542 }
2543
2544 static uint16_t
2545 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2546 {
2547         uint16_t ret = 0;
2548
2549         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2550                 if (bp->link_info.support_speeds)
2551                         return bp->link_info.support_speeds;
2552                 link_speed = BNXT_SUPPORTED_SPEEDS;
2553         }
2554
2555         if (link_speed & ETH_LINK_SPEED_100M)
2556                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2557         if (link_speed & ETH_LINK_SPEED_100M_HD)
2558                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2559         if (link_speed & ETH_LINK_SPEED_1G)
2560                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2561         if (link_speed & ETH_LINK_SPEED_2_5G)
2562                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2563         if (link_speed & ETH_LINK_SPEED_10G)
2564                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2565         if (link_speed & ETH_LINK_SPEED_20G)
2566                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2567         if (link_speed & ETH_LINK_SPEED_25G)
2568                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2569         if (link_speed & ETH_LINK_SPEED_40G)
2570                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2571         if (link_speed & ETH_LINK_SPEED_50G)
2572                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2573         if (link_speed & ETH_LINK_SPEED_100G)
2574                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2575         return ret;
2576 }
2577
2578 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2579 {
2580         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2581
2582         switch (hw_link_speed) {
2583         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2584                 eth_link_speed = ETH_SPEED_NUM_100M;
2585                 break;
2586         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2587                 eth_link_speed = ETH_SPEED_NUM_1G;
2588                 break;
2589         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2590                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2591                 break;
2592         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2593                 eth_link_speed = ETH_SPEED_NUM_10G;
2594                 break;
2595         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2596                 eth_link_speed = ETH_SPEED_NUM_20G;
2597                 break;
2598         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2599                 eth_link_speed = ETH_SPEED_NUM_25G;
2600                 break;
2601         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2602                 eth_link_speed = ETH_SPEED_NUM_40G;
2603                 break;
2604         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2605                 eth_link_speed = ETH_SPEED_NUM_50G;
2606                 break;
2607         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2608                 eth_link_speed = ETH_SPEED_NUM_100G;
2609                 break;
2610         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2611         default:
2612                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2613                         hw_link_speed);
2614                 break;
2615         }
2616         return eth_link_speed;
2617 }
2618
2619 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2620 {
2621         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2622
2623         switch (hw_link_duplex) {
2624         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2625         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2626                 /* FALLTHROUGH */
2627                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2628                 break;
2629         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2630                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2631                 break;
2632         default:
2633                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2634                         hw_link_duplex);
2635                 break;
2636         }
2637         return eth_link_duplex;
2638 }
2639
2640 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2641 {
2642         int rc = 0;
2643         struct bnxt_link_info *link_info = &bp->link_info;
2644
2645         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2646         if (rc) {
2647                 PMD_DRV_LOG(ERR,
2648                         "Get link config failed with rc %d\n", rc);
2649                 goto exit;
2650         }
2651         if (link_info->link_speed)
2652                 link->link_speed =
2653                         bnxt_parse_hw_link_speed(link_info->link_speed);
2654         else
2655                 link->link_speed = ETH_SPEED_NUM_NONE;
2656         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2657         link->link_status = link_info->link_up;
2658         link->link_autoneg = link_info->auto_mode ==
2659                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2660                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2661 exit:
2662         return rc;
2663 }
2664
2665 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2666 {
2667         int rc = 0;
2668         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2669         struct bnxt_link_info link_req;
2670         uint16_t speed, autoneg;
2671
2672         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2673                 return 0;
2674
2675         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2676                         bp->eth_dev->data->port_id);
2677         if (rc)
2678                 goto error;
2679
2680         memset(&link_req, 0, sizeof(link_req));
2681         link_req.link_up = link_up;
2682         if (!link_up)
2683                 goto port_phy_cfg;
2684
2685         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2686         if (BNXT_CHIP_THOR(bp) &&
2687             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2688                 /* 40G is not supported as part of media auto detect.
2689                  * The speed should be forced and autoneg disabled
2690                  * to configure 40G speed.
2691                  */
2692                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2693                 autoneg = 0;
2694         }
2695
2696         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2697         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2698         /* Autoneg can be done only when the FW allows.
2699          * When user configures fixed speed of 40G and later changes to
2700          * any other speed, auto_link_speed/force_link_speed is still set
2701          * to 40G until link comes up at new speed.
2702          */
2703         if (autoneg == 1 &&
2704             !(!BNXT_CHIP_THOR(bp) &&
2705               (bp->link_info.auto_link_speed ||
2706                bp->link_info.force_link_speed))) {
2707                 link_req.phy_flags |=
2708                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2709                 link_req.auto_link_speed_mask =
2710                         bnxt_parse_eth_link_speed_mask(bp,
2711                                                        dev_conf->link_speeds);
2712         } else {
2713                 if (bp->link_info.phy_type ==
2714                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2715                     bp->link_info.phy_type ==
2716                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2717                     bp->link_info.media_type ==
2718                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2719                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2720                         return -EINVAL;
2721                 }
2722
2723                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2724                 /* If user wants a particular speed try that first. */
2725                 if (speed)
2726                         link_req.link_speed = speed;
2727                 else if (bp->link_info.force_link_speed)
2728                         link_req.link_speed = bp->link_info.force_link_speed;
2729                 else
2730                         link_req.link_speed = bp->link_info.auto_link_speed;
2731         }
2732         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2733         link_req.auto_pause = bp->link_info.auto_pause;
2734         link_req.force_pause = bp->link_info.force_pause;
2735
2736 port_phy_cfg:
2737         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2738         if (rc) {
2739                 PMD_DRV_LOG(ERR,
2740                         "Set link config failed with rc %d\n", rc);
2741         }
2742
2743 error:
2744         return rc;
2745 }
2746
2747 /* JIRA 22088 */
2748 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2749 {
2750         struct hwrm_func_qcfg_input req = {0};
2751         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2752         uint16_t flags;
2753         int rc = 0;
2754
2755         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2756         req.fid = rte_cpu_to_le_16(0xffff);
2757
2758         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2759
2760         HWRM_CHECK_RESULT();
2761
2762         /* Hard Coded.. 0xfff VLAN ID mask */
2763         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2764         flags = rte_le_to_cpu_16(resp->flags);
2765         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2766                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2767
2768         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2769                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2770                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2771         } else if (BNXT_VF(bp) &&
2772                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2773                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2774                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2775         }
2776
2777         if (mtu)
2778                 *mtu = resp->mtu;
2779
2780         switch (resp->port_partition_type) {
2781         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2782         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2783         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2784                 /* FALLTHROUGH */
2785                 bp->port_partition_type = resp->port_partition_type;
2786                 break;
2787         default:
2788                 bp->port_partition_type = 0;
2789                 break;
2790         }
2791
2792         HWRM_UNLOCK();
2793
2794         return rc;
2795 }
2796
2797 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2798                                    struct hwrm_func_qcaps_output *qcaps)
2799 {
2800         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2801         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2802                sizeof(qcaps->mac_address));
2803         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2804         qcaps->max_rx_rings = fcfg->num_rx_rings;
2805         qcaps->max_tx_rings = fcfg->num_tx_rings;
2806         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2807         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2808         qcaps->max_vfs = 0;
2809         qcaps->first_vf_id = 0;
2810         qcaps->max_vnics = fcfg->num_vnics;
2811         qcaps->max_decap_records = 0;
2812         qcaps->max_encap_records = 0;
2813         qcaps->max_tx_wm_flows = 0;
2814         qcaps->max_tx_em_flows = 0;
2815         qcaps->max_rx_wm_flows = 0;
2816         qcaps->max_rx_em_flows = 0;
2817         qcaps->max_flow_id = 0;
2818         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2819         qcaps->max_sp_tx_rings = 0;
2820         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2821 }
2822
2823 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2824 {
2825         struct hwrm_func_cfg_input req = {0};
2826         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2827         uint32_t enables;
2828         int rc;
2829
2830         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2831                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2832                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2833                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2834                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2835                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2836                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2837                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2838                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2839
2840         if (BNXT_HAS_RING_GRPS(bp)) {
2841                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2842                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2843         } else if (BNXT_HAS_NQ(bp)) {
2844                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2845                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2846         }
2847
2848         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2849         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2850         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2851                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2852                                    BNXT_NUM_VLANS);
2853         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2854         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2855         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2856         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2857         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2858         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2859         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2860         req.fid = rte_cpu_to_le_16(0xffff);
2861         req.enables = rte_cpu_to_le_32(enables);
2862
2863         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2864
2865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2866
2867         HWRM_CHECK_RESULT();
2868         HWRM_UNLOCK();
2869
2870         return rc;
2871 }
2872
2873 static void populate_vf_func_cfg_req(struct bnxt *bp,
2874                                      struct hwrm_func_cfg_input *req,
2875                                      int num_vfs)
2876 {
2877         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2878                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2879                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2880                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2881                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2882                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2883                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2884                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2885                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2886                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2887
2888         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2889                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2890                                     BNXT_NUM_VLANS);
2891         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2892                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2893                                     BNXT_NUM_VLANS);
2894         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2895                                                 (num_vfs + 1));
2896         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2897         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2898                                                (num_vfs + 1));
2899         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2900         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2901         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2902         /* TODO: For now, do not support VMDq/RFS on VFs. */
2903         req->num_vnics = rte_cpu_to_le_16(1);
2904         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2905                                                  (num_vfs + 1));
2906 }
2907
2908 static void add_random_mac_if_needed(struct bnxt *bp,
2909                                      struct hwrm_func_cfg_input *cfg_req,
2910                                      int vf)
2911 {
2912         struct rte_ether_addr mac;
2913
2914         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2915                 return;
2916
2917         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2918                 cfg_req->enables |=
2919                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2920                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2921                 bp->pf.vf_info[vf].random_mac = true;
2922         } else {
2923                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2924                         RTE_ETHER_ADDR_LEN);
2925         }
2926 }
2927
2928 static void reserve_resources_from_vf(struct bnxt *bp,
2929                                       struct hwrm_func_cfg_input *cfg_req,
2930                                       int vf)
2931 {
2932         struct hwrm_func_qcaps_input req = {0};
2933         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2934         int rc;
2935
2936         /* Get the actual allocated values now */
2937         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2938         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2939         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2940
2941         if (rc) {
2942                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2943                 copy_func_cfg_to_qcaps(cfg_req, resp);
2944         } else if (resp->error_code) {
2945                 rc = rte_le_to_cpu_16(resp->error_code);
2946                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2947                 copy_func_cfg_to_qcaps(cfg_req, resp);
2948         }
2949
2950         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2951         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2952         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2953         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2954         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2955         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2956         /*
2957          * TODO: While not supporting VMDq with VFs, max_vnics is always
2958          * forced to 1 in this case
2959          */
2960         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2961         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2962
2963         HWRM_UNLOCK();
2964 }
2965
2966 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2967 {
2968         struct hwrm_func_qcfg_input req = {0};
2969         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2970         int rc;
2971
2972         /* Check for zero MAC address */
2973         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2974         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2975         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2976         HWRM_CHECK_RESULT();
2977         rc = rte_le_to_cpu_16(resp->vlan);
2978
2979         HWRM_UNLOCK();
2980
2981         return rc;
2982 }
2983
2984 static int update_pf_resource_max(struct bnxt *bp)
2985 {
2986         struct hwrm_func_qcfg_input req = {0};
2987         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2988         int rc;
2989
2990         /* And copy the allocated numbers into the pf struct */
2991         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2992         req.fid = rte_cpu_to_le_16(0xffff);
2993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2994         HWRM_CHECK_RESULT();
2995
2996         /* Only TX ring value reflects actual allocation? TODO */
2997         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2998         bp->pf.evb_mode = resp->evb_mode;
2999
3000         HWRM_UNLOCK();
3001
3002         return rc;
3003 }
3004
3005 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3006 {
3007         int rc;
3008
3009         if (!BNXT_PF(bp)) {
3010                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3011                 return -EINVAL;
3012         }
3013
3014         rc = bnxt_hwrm_func_qcaps(bp);
3015         if (rc)
3016                 return rc;
3017
3018         bp->pf.func_cfg_flags &=
3019                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3020                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3021         bp->pf.func_cfg_flags |=
3022                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3023         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3024         rc = __bnxt_hwrm_func_qcaps(bp);
3025         return rc;
3026 }
3027
3028 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3029 {
3030         struct hwrm_func_cfg_input req = {0};
3031         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3032         int i;
3033         size_t sz;
3034         int rc = 0;
3035         size_t req_buf_sz;
3036
3037         if (!BNXT_PF(bp)) {
3038                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3039                 return -EINVAL;
3040         }
3041
3042         rc = bnxt_hwrm_func_qcaps(bp);
3043
3044         if (rc)
3045                 return rc;
3046
3047         bp->pf.active_vfs = num_vfs;
3048
3049         /*
3050          * First, configure the PF to only use one TX ring.  This ensures that
3051          * there are enough rings for all VFs.
3052          *
3053          * If we don't do this, when we call func_alloc() later, we will lock
3054          * extra rings to the PF that won't be available during func_cfg() of
3055          * the VFs.
3056          *
3057          * This has been fixed with firmware versions above 20.6.54
3058          */
3059         bp->pf.func_cfg_flags &=
3060                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3061                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3062         bp->pf.func_cfg_flags |=
3063                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3064         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3065         if (rc)
3066                 return rc;
3067
3068         /*
3069          * Now, create and register a buffer to hold forwarded VF requests
3070          */
3071         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3072         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3073                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3074         if (bp->pf.vf_req_buf == NULL) {
3075                 rc = -ENOMEM;
3076                 goto error_free;
3077         }
3078         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3079                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3080         for (i = 0; i < num_vfs; i++)
3081                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3082                                         (i * HWRM_MAX_REQ_LEN);
3083
3084         rc = bnxt_hwrm_func_buf_rgtr(bp);
3085         if (rc)
3086                 goto error_free;
3087
3088         populate_vf_func_cfg_req(bp, &req, num_vfs);
3089
3090         bp->pf.active_vfs = 0;
3091         for (i = 0; i < num_vfs; i++) {
3092                 add_random_mac_if_needed(bp, &req, i);
3093
3094                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3095                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3096                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3097                 rc = bnxt_hwrm_send_message(bp,
3098                                             &req,
3099                                             sizeof(req),
3100                                             BNXT_USE_CHIMP_MB);
3101
3102                 /* Clear enable flag for next pass */
3103                 req.enables &= ~rte_cpu_to_le_32(
3104                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3105
3106                 if (rc || resp->error_code) {
3107                         PMD_DRV_LOG(ERR,
3108                                 "Failed to initizlie VF %d\n", i);
3109                         PMD_DRV_LOG(ERR,
3110                                 "Not all VFs available. (%d, %d)\n",
3111                                 rc, resp->error_code);
3112                         HWRM_UNLOCK();
3113                         break;
3114                 }
3115
3116                 HWRM_UNLOCK();
3117
3118                 reserve_resources_from_vf(bp, &req, i);
3119                 bp->pf.active_vfs++;
3120                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3121         }
3122
3123         /*
3124          * Now configure the PF to use "the rest" of the resources
3125          * We're using STD_TX_RING_MODE here though which will limit the TX
3126          * rings.  This will allow QoS to function properly.  Not setting this
3127          * will cause PF rings to break bandwidth settings.
3128          */
3129         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3130         if (rc)
3131                 goto error_free;
3132
3133         rc = update_pf_resource_max(bp);
3134         if (rc)
3135                 goto error_free;
3136
3137         return rc;
3138
3139 error_free:
3140         bnxt_hwrm_func_buf_unrgtr(bp);
3141         return rc;
3142 }
3143
3144 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3145 {
3146         struct hwrm_func_cfg_input req = {0};
3147         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3148         int rc;
3149
3150         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3151
3152         req.fid = rte_cpu_to_le_16(0xffff);
3153         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3154         req.evb_mode = bp->pf.evb_mode;
3155
3156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3157         HWRM_CHECK_RESULT();
3158         HWRM_UNLOCK();
3159
3160         return rc;
3161 }
3162
3163 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3164                                 uint8_t tunnel_type)
3165 {
3166         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3167         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3168         int rc = 0;
3169
3170         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3171         req.tunnel_type = tunnel_type;
3172         req.tunnel_dst_port_val = port;
3173         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3174         HWRM_CHECK_RESULT();
3175
3176         switch (tunnel_type) {
3177         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3178                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3179                 bp->vxlan_port = port;
3180                 break;
3181         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3182                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3183                 bp->geneve_port = port;
3184                 break;
3185         default:
3186                 break;
3187         }
3188
3189         HWRM_UNLOCK();
3190
3191         return rc;
3192 }
3193
3194 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3195                                 uint8_t tunnel_type)
3196 {
3197         struct hwrm_tunnel_dst_port_free_input req = {0};
3198         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3199         int rc = 0;
3200
3201         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3202
3203         req.tunnel_type = tunnel_type;
3204         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3206
3207         HWRM_CHECK_RESULT();
3208         HWRM_UNLOCK();
3209
3210         return rc;
3211 }
3212
3213 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3214                                         uint32_t flags)
3215 {
3216         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3217         struct hwrm_func_cfg_input req = {0};
3218         int rc;
3219
3220         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3221
3222         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3223         req.flags = rte_cpu_to_le_32(flags);
3224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3225
3226         HWRM_CHECK_RESULT();
3227         HWRM_UNLOCK();
3228
3229         return rc;
3230 }
3231
3232 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3233 {
3234         uint32_t *flag = flagp;
3235
3236         vnic->flags = *flag;
3237 }
3238
3239 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3240 {
3241         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3242 }
3243
3244 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3245 {
3246         int rc = 0;
3247         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3248         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3249
3250         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3251
3252         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3253         req.req_buf_page_size = rte_cpu_to_le_16(
3254                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3255         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3256         req.req_buf_page_addr0 =
3257                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3258         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3259                 PMD_DRV_LOG(ERR,
3260                         "unable to map buffer address to physical memory\n");
3261                 return -ENOMEM;
3262         }
3263
3264         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3265
3266         HWRM_CHECK_RESULT();
3267         HWRM_UNLOCK();
3268
3269         return rc;
3270 }
3271
3272 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3273 {
3274         int rc = 0;
3275         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3276         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3277
3278         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3279                 return 0;
3280
3281         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3282
3283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284
3285         HWRM_CHECK_RESULT();
3286         HWRM_UNLOCK();
3287
3288         return rc;
3289 }
3290
3291 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3292 {
3293         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3294         struct hwrm_func_cfg_input req = {0};
3295         int rc;
3296
3297         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3298
3299         req.fid = rte_cpu_to_le_16(0xffff);
3300         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3301         req.enables = rte_cpu_to_le_32(
3302                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3303         req.async_event_cr = rte_cpu_to_le_16(
3304                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3305         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3306
3307         HWRM_CHECK_RESULT();
3308         HWRM_UNLOCK();
3309
3310         return rc;
3311 }
3312
3313 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3314 {
3315         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3316         struct hwrm_func_vf_cfg_input req = {0};
3317         int rc;
3318
3319         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3320
3321         req.enables = rte_cpu_to_le_32(
3322                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3323         req.async_event_cr = rte_cpu_to_le_16(
3324                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3326
3327         HWRM_CHECK_RESULT();
3328         HWRM_UNLOCK();
3329
3330         return rc;
3331 }
3332
3333 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3334 {
3335         struct hwrm_func_cfg_input req = {0};
3336         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3337         uint16_t dflt_vlan, fid;
3338         uint32_t func_cfg_flags;
3339         int rc = 0;
3340
3341         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3342
3343         if (is_vf) {
3344                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3345                 fid = bp->pf.vf_info[vf].fid;
3346                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3347         } else {
3348                 fid = rte_cpu_to_le_16(0xffff);
3349                 func_cfg_flags = bp->pf.func_cfg_flags;
3350                 dflt_vlan = bp->vlan;
3351         }
3352
3353         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3354         req.fid = rte_cpu_to_le_16(fid);
3355         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3356         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3357
3358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3359
3360         HWRM_CHECK_RESULT();
3361         HWRM_UNLOCK();
3362
3363         return rc;
3364 }
3365
3366 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3367                         uint16_t max_bw, uint16_t enables)
3368 {
3369         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3370         struct hwrm_func_cfg_input req = {0};
3371         int rc;
3372
3373         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3374
3375         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3376         req.enables |= rte_cpu_to_le_32(enables);
3377         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3378         req.max_bw = rte_cpu_to_le_32(max_bw);
3379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3380
3381         HWRM_CHECK_RESULT();
3382         HWRM_UNLOCK();
3383
3384         return rc;
3385 }
3386
3387 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3388 {
3389         struct hwrm_func_cfg_input req = {0};
3390         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3391         int rc = 0;
3392
3393         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3394
3395         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3396         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3397         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3398         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3399
3400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3401
3402         HWRM_CHECK_RESULT();
3403         HWRM_UNLOCK();
3404
3405         return rc;
3406 }
3407
3408 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3409 {
3410         int rc;
3411
3412         if (BNXT_PF(bp))
3413                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3414         else
3415                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3416
3417         return rc;
3418 }
3419
3420 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3421                               void *encaped, size_t ec_size)
3422 {
3423         int rc = 0;
3424         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3425         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3426
3427         if (ec_size > sizeof(req.encap_request))
3428                 return -1;
3429
3430         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3431
3432         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3433         memcpy(req.encap_request, encaped, ec_size);
3434
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3436
3437         HWRM_CHECK_RESULT();
3438         HWRM_UNLOCK();
3439
3440         return rc;
3441 }
3442
3443 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3444                                        struct rte_ether_addr *mac)
3445 {
3446         struct hwrm_func_qcfg_input req = {0};
3447         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3448         int rc;
3449
3450         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3451
3452         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3454
3455         HWRM_CHECK_RESULT();
3456
3457         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3458
3459         HWRM_UNLOCK();
3460
3461         return rc;
3462 }
3463
3464 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3465                             void *encaped, size_t ec_size)
3466 {
3467         int rc = 0;
3468         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3469         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3470
3471         if (ec_size > sizeof(req.encap_request))
3472                 return -1;
3473
3474         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3475
3476         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3477         memcpy(req.encap_request, encaped, ec_size);
3478
3479         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3480
3481         HWRM_CHECK_RESULT();
3482         HWRM_UNLOCK();
3483
3484         return rc;
3485 }
3486
3487 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3488                          struct rte_eth_stats *stats, uint8_t rx)
3489 {
3490         int rc = 0;
3491         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3492         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3493
3494         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3495
3496         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3497
3498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3499
3500         HWRM_CHECK_RESULT();
3501
3502         if (rx) {
3503                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3504                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3505                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3506                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3507                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3508                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3509                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3510                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3511         } else {
3512                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3513                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3514                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3515                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3516                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3517                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3518         }
3519
3520
3521         HWRM_UNLOCK();
3522
3523         return rc;
3524 }
3525
3526 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3527 {
3528         struct hwrm_port_qstats_input req = {0};
3529         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3530         struct bnxt_pf_info *pf = &bp->pf;
3531         int rc;
3532
3533         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3534
3535         req.port_id = rte_cpu_to_le_16(pf->port_id);
3536         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3537         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3538         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3539
3540         HWRM_CHECK_RESULT();
3541         HWRM_UNLOCK();
3542
3543         return rc;
3544 }
3545
3546 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3547 {
3548         struct hwrm_port_clr_stats_input req = {0};
3549         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3550         struct bnxt_pf_info *pf = &bp->pf;
3551         int rc;
3552
3553         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3554         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3555             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3556                 return 0;
3557
3558         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3559
3560         req.port_id = rte_cpu_to_le_16(pf->port_id);
3561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3562
3563         HWRM_CHECK_RESULT();
3564         HWRM_UNLOCK();
3565
3566         return rc;
3567 }
3568
3569 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3570 {
3571         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3572         struct hwrm_port_led_qcaps_input req = {0};
3573         int rc;
3574
3575         if (BNXT_VF(bp))
3576                 return 0;
3577
3578         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3579         req.port_id = bp->pf.port_id;
3580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3581
3582         HWRM_CHECK_RESULT();
3583
3584         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3585                 unsigned int i;
3586
3587                 bp->num_leds = resp->num_leds;
3588                 memcpy(bp->leds, &resp->led0_id,
3589                         sizeof(bp->leds[0]) * bp->num_leds);
3590                 for (i = 0; i < bp->num_leds; i++) {
3591                         struct bnxt_led_info *led = &bp->leds[i];
3592
3593                         uint16_t caps = led->led_state_caps;
3594
3595                         if (!led->led_group_id ||
3596                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3597                                 bp->num_leds = 0;
3598                                 break;
3599                         }
3600                 }
3601         }
3602
3603         HWRM_UNLOCK();
3604
3605         return rc;
3606 }
3607
3608 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3609 {
3610         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3611         struct hwrm_port_led_cfg_input req = {0};
3612         struct bnxt_led_cfg *led_cfg;
3613         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3614         uint16_t duration = 0;
3615         int rc, i;
3616
3617         if (!bp->num_leds || BNXT_VF(bp))
3618                 return -EOPNOTSUPP;
3619
3620         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3621
3622         if (led_on) {
3623                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3624                 duration = rte_cpu_to_le_16(500);
3625         }
3626         req.port_id = bp->pf.port_id;
3627         req.num_leds = bp->num_leds;
3628         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3629         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3630                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3631                 led_cfg->led_id = bp->leds[i].led_id;
3632                 led_cfg->led_state = led_state;
3633                 led_cfg->led_blink_on = duration;
3634                 led_cfg->led_blink_off = duration;
3635                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3636         }
3637
3638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3639
3640         HWRM_CHECK_RESULT();
3641         HWRM_UNLOCK();
3642
3643         return rc;
3644 }
3645
3646 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3647                                uint32_t *length)
3648 {
3649         int rc;
3650         struct hwrm_nvm_get_dir_info_input req = {0};
3651         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3652
3653         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3654
3655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3656
3657         HWRM_CHECK_RESULT();
3658
3659         *entries = rte_le_to_cpu_32(resp->entries);
3660         *length = rte_le_to_cpu_32(resp->entry_length);
3661
3662         HWRM_UNLOCK();
3663         return rc;
3664 }
3665
3666 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3667 {
3668         int rc;
3669         uint32_t dir_entries;
3670         uint32_t entry_length;
3671         uint8_t *buf;
3672         size_t buflen;
3673         rte_iova_t dma_handle;
3674         struct hwrm_nvm_get_dir_entries_input req = {0};
3675         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3676
3677         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3678         if (rc != 0)
3679                 return rc;
3680
3681         *data++ = dir_entries;
3682         *data++ = entry_length;
3683         len -= 2;
3684         memset(data, 0xff, len);
3685
3686         buflen = dir_entries * entry_length;
3687         buf = rte_malloc("nvm_dir", buflen, 0);
3688         rte_mem_lock_page(buf);
3689         if (buf == NULL)
3690                 return -ENOMEM;
3691         dma_handle = rte_mem_virt2iova(buf);
3692         if (dma_handle == RTE_BAD_IOVA) {
3693                 PMD_DRV_LOG(ERR,
3694                         "unable to map response address to physical memory\n");
3695                 return -ENOMEM;
3696         }
3697         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3698         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3700
3701         if (rc == 0)
3702                 memcpy(data, buf, len > buflen ? buflen : len);
3703
3704         rte_free(buf);
3705         HWRM_CHECK_RESULT();
3706         HWRM_UNLOCK();
3707
3708         return rc;
3709 }
3710
3711 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3712                              uint32_t offset, uint32_t length,
3713                              uint8_t *data)
3714 {
3715         int rc;
3716         uint8_t *buf;
3717         rte_iova_t dma_handle;
3718         struct hwrm_nvm_read_input req = {0};
3719         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3720
3721         buf = rte_malloc("nvm_item", length, 0);
3722         rte_mem_lock_page(buf);
3723         if (!buf)
3724                 return -ENOMEM;
3725
3726         dma_handle = rte_mem_virt2iova(buf);
3727         if (dma_handle == RTE_BAD_IOVA) {
3728                 PMD_DRV_LOG(ERR,
3729                         "unable to map response address to physical memory\n");
3730                 return -ENOMEM;
3731         }
3732         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3733         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3734         req.dir_idx = rte_cpu_to_le_16(index);
3735         req.offset = rte_cpu_to_le_32(offset);
3736         req.len = rte_cpu_to_le_32(length);
3737         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3738         if (rc == 0)
3739                 memcpy(data, buf, length);
3740
3741         rte_free(buf);
3742         HWRM_CHECK_RESULT();
3743         HWRM_UNLOCK();
3744
3745         return rc;
3746 }
3747
3748 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3749 {
3750         int rc;
3751         struct hwrm_nvm_erase_dir_entry_input req = {0};
3752         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3753
3754         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3755         req.dir_idx = rte_cpu_to_le_16(index);
3756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3757         HWRM_CHECK_RESULT();
3758         HWRM_UNLOCK();
3759
3760         return rc;
3761 }
3762
3763
3764 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3765                           uint16_t dir_ordinal, uint16_t dir_ext,
3766                           uint16_t dir_attr, const uint8_t *data,
3767                           size_t data_len)
3768 {
3769         int rc;
3770         struct hwrm_nvm_write_input req = {0};
3771         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3772         rte_iova_t dma_handle;
3773         uint8_t *buf;
3774
3775         buf = rte_malloc("nvm_write", data_len, 0);
3776         rte_mem_lock_page(buf);
3777         if (!buf)
3778                 return -ENOMEM;
3779
3780         dma_handle = rte_mem_virt2iova(buf);
3781         if (dma_handle == RTE_BAD_IOVA) {
3782                 PMD_DRV_LOG(ERR,
3783                         "unable to map response address to physical memory\n");
3784                 return -ENOMEM;
3785         }
3786         memcpy(buf, data, data_len);
3787
3788         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3789
3790         req.dir_type = rte_cpu_to_le_16(dir_type);
3791         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3792         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3793         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3794         req.dir_data_length = rte_cpu_to_le_32(data_len);
3795         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3796
3797         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3798
3799         rte_free(buf);
3800         HWRM_CHECK_RESULT();
3801         HWRM_UNLOCK();
3802
3803         return rc;
3804 }
3805
3806 static void
3807 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3808 {
3809         uint32_t *count = cbdata;
3810
3811         *count = *count + 1;
3812 }
3813
3814 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3815                                      struct bnxt_vnic_info *vnic __rte_unused)
3816 {
3817         return 0;
3818 }
3819
3820 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3821 {
3822         uint32_t count = 0;
3823
3824         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3825             &count, bnxt_vnic_count_hwrm_stub);
3826
3827         return count;
3828 }
3829
3830 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3831                                         uint16_t *vnic_ids)
3832 {
3833         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3834         struct hwrm_func_vf_vnic_ids_query_output *resp =
3835                                                 bp->hwrm_cmd_resp_addr;
3836         int rc;
3837
3838         /* First query all VNIC ids */
3839         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3840
3841         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3842         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3843         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3844
3845         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3846                 HWRM_UNLOCK();
3847                 PMD_DRV_LOG(ERR,
3848                 "unable to map VNIC ID table address to physical memory\n");
3849                 return -ENOMEM;
3850         }
3851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3852         HWRM_CHECK_RESULT();
3853         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3854
3855         HWRM_UNLOCK();
3856
3857         return rc;
3858 }
3859
3860 /*
3861  * This function queries the VNIC IDs  for a specified VF. It then calls
3862  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3863  * Then it calls the hwrm_cb function to program this new vnic configuration.
3864  */
3865 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3866         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3867         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3868 {
3869         struct bnxt_vnic_info vnic;
3870         int rc = 0;
3871         int i, num_vnic_ids;
3872         uint16_t *vnic_ids;
3873         size_t vnic_id_sz;
3874         size_t sz;
3875
3876         /* First query all VNIC ids */
3877         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3878         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3879                         RTE_CACHE_LINE_SIZE);
3880         if (vnic_ids == NULL)
3881                 return -ENOMEM;
3882
3883         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3884                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3885
3886         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3887
3888         if (num_vnic_ids < 0)
3889                 return num_vnic_ids;
3890
3891         /* Retrieve VNIC, update bd_stall then update */
3892
3893         for (i = 0; i < num_vnic_ids; i++) {
3894                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3895                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3896                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3897                 if (rc)
3898                         break;
3899                 if (vnic.mru <= 4)      /* Indicates unallocated */
3900                         continue;
3901
3902                 vnic_cb(&vnic, cbdata);
3903
3904                 rc = hwrm_cb(bp, &vnic);
3905                 if (rc)
3906                         break;
3907         }
3908
3909         rte_free(vnic_ids);
3910
3911         return rc;
3912 }
3913
3914 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3915                                               bool on)
3916 {
3917         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3918         struct hwrm_func_cfg_input req = {0};
3919         int rc;
3920
3921         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3922
3923         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3924         req.enables |= rte_cpu_to_le_32(
3925                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3926         req.vlan_antispoof_mode = on ?
3927                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3928                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3929         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3930
3931         HWRM_CHECK_RESULT();
3932         HWRM_UNLOCK();
3933
3934         return rc;
3935 }
3936
3937 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3938 {
3939         struct bnxt_vnic_info vnic;
3940         uint16_t *vnic_ids;
3941         size_t vnic_id_sz;
3942         int num_vnic_ids, i;
3943         size_t sz;
3944         int rc;
3945
3946         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3947         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3948                         RTE_CACHE_LINE_SIZE);
3949         if (vnic_ids == NULL)
3950                 return -ENOMEM;
3951
3952         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3953                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3954
3955         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3956         if (rc <= 0)
3957                 goto exit;
3958         num_vnic_ids = rc;
3959
3960         /*
3961          * Loop through to find the default VNIC ID.
3962          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3963          * by sending the hwrm_func_qcfg command to the firmware.
3964          */
3965         for (i = 0; i < num_vnic_ids; i++) {
3966                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3967                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3968                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3969                                         bp->pf.first_vf_id + vf);
3970                 if (rc)
3971                         goto exit;
3972                 if (vnic.func_default) {
3973                         rte_free(vnic_ids);
3974                         return vnic.fw_vnic_id;
3975                 }
3976         }
3977         /* Could not find a default VNIC. */
3978         PMD_DRV_LOG(ERR, "No default VNIC\n");
3979 exit:
3980         rte_free(vnic_ids);
3981         return rc;
3982 }
3983
3984 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3985                          uint16_t dst_id,
3986                          struct bnxt_filter_info *filter)
3987 {
3988         int rc = 0;
3989         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3990         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3991         uint32_t enables = 0;
3992
3993         if (filter->fw_em_filter_id != UINT64_MAX)
3994                 bnxt_hwrm_clear_em_filter(bp, filter);
3995
3996         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3997
3998         req.flags = rte_cpu_to_le_32(filter->flags);
3999
4000         enables = filter->enables |
4001               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4002         req.dst_id = rte_cpu_to_le_16(dst_id);
4003
4004         if (filter->ip_addr_type) {
4005                 req.ip_addr_type = filter->ip_addr_type;
4006                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4007         }
4008         if (enables &
4009             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4010                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4011         if (enables &
4012             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4013                 memcpy(req.src_macaddr, filter->src_macaddr,
4014                        RTE_ETHER_ADDR_LEN);
4015         if (enables &
4016             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4017                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4018                        RTE_ETHER_ADDR_LEN);
4019         if (enables &
4020             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4021                 req.ovlan_vid = filter->l2_ovlan;
4022         if (enables &
4023             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4024                 req.ivlan_vid = filter->l2_ivlan;
4025         if (enables &
4026             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4027                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4028         if (enables &
4029             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4030                 req.ip_protocol = filter->ip_protocol;
4031         if (enables &
4032             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4033                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4034         if (enables &
4035             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4036                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4037         if (enables &
4038             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4039                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4040         if (enables &
4041             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4042                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4043         if (enables &
4044             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4045                 req.mirror_vnic_id = filter->mirror_vnic_id;
4046
4047         req.enables = rte_cpu_to_le_32(enables);
4048
4049         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4050
4051         HWRM_CHECK_RESULT();
4052
4053         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4054         HWRM_UNLOCK();
4055
4056         return rc;
4057 }
4058
4059 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4060 {
4061         int rc = 0;
4062         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4063         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4064
4065         if (filter->fw_em_filter_id == UINT64_MAX)
4066                 return 0;
4067
4068         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4069         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4070
4071         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4072
4073         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4074
4075         HWRM_CHECK_RESULT();
4076         HWRM_UNLOCK();
4077
4078         filter->fw_em_filter_id = UINT64_MAX;
4079         filter->fw_l2_filter_id = UINT64_MAX;
4080
4081         return 0;
4082 }
4083
4084 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4085                          uint16_t dst_id,
4086                          struct bnxt_filter_info *filter)
4087 {
4088         int rc = 0;
4089         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4090         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4091                                                 bp->hwrm_cmd_resp_addr;
4092         uint32_t enables = 0;
4093
4094         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4095                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4096
4097         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4098
4099         req.flags = rte_cpu_to_le_32(filter->flags);
4100
4101         enables = filter->enables |
4102               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4103         req.dst_id = rte_cpu_to_le_16(dst_id);
4104
4105
4106         if (filter->ip_addr_type) {
4107                 req.ip_addr_type = filter->ip_addr_type;
4108                 enables |=
4109                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4110         }
4111         if (enables &
4112             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4113                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4114         if (enables &
4115             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4116                 memcpy(req.src_macaddr, filter->src_macaddr,
4117                        RTE_ETHER_ADDR_LEN);
4118         //if (enables &
4119             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4120                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4121                        //RTE_ETHER_ADDR_LEN);
4122         if (enables &
4123             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4124                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4125         if (enables &
4126             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4127                 req.ip_protocol = filter->ip_protocol;
4128         if (enables &
4129             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4130                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4131         if (enables &
4132             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4133                 req.src_ipaddr_mask[0] =
4134                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4135         if (enables &
4136             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4137                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4138         if (enables &
4139             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4140                 req.dst_ipaddr_mask[0] =
4141                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4142         if (enables &
4143             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4144                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4145         if (enables &
4146             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4147                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4148         if (enables &
4149             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4150                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4151         if (enables &
4152             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4153                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4154         if (enables &
4155             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4156                 req.mirror_vnic_id = filter->mirror_vnic_id;
4157
4158         req.enables = rte_cpu_to_le_32(enables);
4159
4160         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4161
4162         HWRM_CHECK_RESULT();
4163
4164         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4165         HWRM_UNLOCK();
4166
4167         return rc;
4168 }
4169
4170 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4171                                 struct bnxt_filter_info *filter)
4172 {
4173         int rc = 0;
4174         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4175         struct hwrm_cfa_ntuple_filter_free_output *resp =
4176                                                 bp->hwrm_cmd_resp_addr;
4177
4178         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4179                 return 0;
4180
4181         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4182
4183         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4184
4185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4186
4187         HWRM_CHECK_RESULT();
4188         HWRM_UNLOCK();
4189
4190         filter->fw_ntuple_filter_id = UINT64_MAX;
4191
4192         return 0;
4193 }
4194
4195 static int
4196 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4197 {
4198         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4199         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4200         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4201         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4202         uint16_t *ring_tbl = vnic->rss_table;
4203         int nr_ctxs = vnic->num_lb_ctxts;
4204         int max_rings = bp->rx_nr_rings;
4205         int i, j, k, cnt;
4206         int rc = 0;
4207
4208         for (i = 0, k = 0; i < nr_ctxs; i++) {
4209                 struct bnxt_rx_ring_info *rxr;
4210                 struct bnxt_cp_ring_info *cpr;
4211
4212                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4213
4214                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4215                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4216                 req.hash_mode_flags = vnic->hash_mode;
4217
4218                 req.ring_grp_tbl_addr =
4219                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4220                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4221                                      2 * sizeof(*ring_tbl));
4222                 req.hash_key_tbl_addr =
4223                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4224
4225                 req.ring_table_pair_index = i;
4226                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4227
4228                 for (j = 0; j < 64; j++) {
4229                         uint16_t ring_id;
4230
4231                         /* Find next active ring. */
4232                         for (cnt = 0; cnt < max_rings; cnt++) {
4233                                 if (rx_queue_state[k] !=
4234                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4235                                         break;
4236                                 if (++k == max_rings)
4237                                         k = 0;
4238                         }
4239
4240                         /* Return if no rings are active. */
4241                         if (cnt == max_rings)
4242                                 return 0;
4243
4244                         /* Add rx/cp ring pair to RSS table. */
4245                         rxr = rxqs[k]->rx_ring;
4246                         cpr = rxqs[k]->cp_ring;
4247
4248                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4249                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4250                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4251                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4252
4253                         if (++k == max_rings)
4254                                 k = 0;
4255                 }
4256                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4257                                             BNXT_USE_CHIMP_MB);
4258
4259                 HWRM_CHECK_RESULT();
4260                 HWRM_UNLOCK();
4261         }
4262
4263         return rc;
4264 }
4265
4266 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4267 {
4268         unsigned int rss_idx, fw_idx, i;
4269
4270         if (!(vnic->rss_table && vnic->hash_type))
4271                 return 0;
4272
4273         if (BNXT_CHIP_THOR(bp))
4274                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4275
4276         /*
4277          * Fill the RSS hash & redirection table with
4278          * ring group ids for all VNICs
4279          */
4280         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4281                 rss_idx++, fw_idx++) {
4282                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4283                         fw_idx %= bp->rx_cp_nr_rings;
4284                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4285                                 break;
4286                         fw_idx++;
4287                 }
4288                 if (i == bp->rx_cp_nr_rings)
4289                         return 0;
4290                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4291         }
4292         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4293 }
4294
4295 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4296         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4297 {
4298         uint16_t flags;
4299
4300         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4301
4302         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4303         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4304
4305         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4306         req->num_cmpl_dma_aggr_during_int =
4307                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4308
4309         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4310
4311         /* min timer set to 1/2 of interrupt timer */
4312         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4313
4314         /* buf timer set to 1/4 of interrupt timer */
4315         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4316
4317         req->cmpl_aggr_dma_tmr_during_int =
4318                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4319
4320         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4321                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4322         req->flags = rte_cpu_to_le_16(flags);
4323 }
4324
4325 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4326                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4327 {
4328         struct hwrm_ring_aggint_qcaps_input req = {0};
4329         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4330         uint32_t enables;
4331         uint16_t flags;
4332         int rc;
4333
4334         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4336         HWRM_CHECK_RESULT();
4337
4338         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4339         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4340
4341         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4342                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4343         agg_req->flags = rte_cpu_to_le_16(flags);
4344         enables =
4345          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4346          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4347         agg_req->enables = rte_cpu_to_le_32(enables);
4348
4349         HWRM_UNLOCK();
4350         return rc;
4351 }
4352
4353 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4354                         struct bnxt_coal *coal, uint16_t ring_id)
4355 {
4356         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4357         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4358                                                 bp->hwrm_cmd_resp_addr;
4359         int rc;
4360
4361         /* Set ring coalesce parameters only for 100G NICs */
4362         if (BNXT_CHIP_THOR(bp)) {
4363                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4364                         return -1;
4365         } else if (bnxt_stratus_device(bp)) {
4366                 bnxt_hwrm_set_coal_params(coal, &req);
4367         } else {
4368                 return 0;
4369         }
4370
4371         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4372         req.ring_id = rte_cpu_to_le_16(ring_id);
4373         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4374         HWRM_CHECK_RESULT();
4375         HWRM_UNLOCK();
4376         return 0;
4377 }
4378
4379 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4380 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4381 {
4382         struct hwrm_func_backing_store_qcaps_input req = {0};
4383         struct hwrm_func_backing_store_qcaps_output *resp =
4384                 bp->hwrm_cmd_resp_addr;
4385         int rc;
4386
4387         if (!BNXT_CHIP_THOR(bp) ||
4388             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4389             BNXT_VF(bp) ||
4390             bp->ctx)
4391                 return 0;
4392
4393         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4394         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4395         HWRM_CHECK_RESULT_SILENT();
4396
4397         if (!rc) {
4398                 struct bnxt_ctx_pg_info *ctx_pg;
4399                 struct bnxt_ctx_mem_info *ctx;
4400                 int total_alloc_len;
4401                 int i;
4402
4403                 total_alloc_len = sizeof(*ctx);
4404                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4405                                  RTE_CACHE_LINE_SIZE);
4406                 if (!ctx) {
4407                         rc = -ENOMEM;
4408                         goto ctx_err;
4409                 }
4410                 memset(ctx, 0, total_alloc_len);
4411
4412                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4413                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4414                                     RTE_CACHE_LINE_SIZE);
4415                 if (!ctx_pg) {
4416                         rc = -ENOMEM;
4417                         goto ctx_err;
4418                 }
4419                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4420                         ctx->tqm_mem[i] = ctx_pg;
4421
4422                 bp->ctx = ctx;
4423                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4424                 ctx->qp_min_qp1_entries =
4425                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4426                 ctx->qp_max_l2_entries =
4427                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4428                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4429                 ctx->srq_max_l2_entries =
4430                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4431                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4432                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4433                 ctx->cq_max_l2_entries =
4434                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4435                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4436                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4437                 ctx->vnic_max_vnic_entries =
4438                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4439                 ctx->vnic_max_ring_table_entries =
4440                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4441                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4442                 ctx->stat_max_entries =
4443                         rte_le_to_cpu_32(resp->stat_max_entries);
4444                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4445                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4446                 ctx->tqm_min_entries_per_ring =
4447                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4448                 ctx->tqm_max_entries_per_ring =
4449                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4450                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4451                 if (!ctx->tqm_entries_multiple)
4452                         ctx->tqm_entries_multiple = 1;
4453                 ctx->mrav_max_entries =
4454                         rte_le_to_cpu_32(resp->mrav_max_entries);
4455                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4456                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4457                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4458         } else {
4459                 rc = 0;
4460         }
4461 ctx_err:
4462         HWRM_UNLOCK();
4463         return rc;
4464 }
4465
4466 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4467 {
4468         struct hwrm_func_backing_store_cfg_input req = {0};
4469         struct hwrm_func_backing_store_cfg_output *resp =
4470                 bp->hwrm_cmd_resp_addr;
4471         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4472         struct bnxt_ctx_pg_info *ctx_pg;
4473         uint32_t *num_entries;
4474         uint64_t *pg_dir;
4475         uint8_t *pg_attr;
4476         uint32_t ena;
4477         int i, rc;
4478
4479         if (!ctx)
4480                 return 0;
4481
4482         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4483         req.enables = rte_cpu_to_le_32(enables);
4484
4485         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4486                 ctx_pg = &ctx->qp_mem;
4487                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4488                 req.qp_num_qp1_entries =
4489                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4490                 req.qp_num_l2_entries =
4491                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4492                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4493                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4494                                       &req.qpc_pg_size_qpc_lvl,
4495                                       &req.qpc_page_dir);
4496         }
4497
4498         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4499                 ctx_pg = &ctx->srq_mem;
4500                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4501                 req.srq_num_l2_entries =
4502                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4503                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4504                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4505                                       &req.srq_pg_size_srq_lvl,
4506                                       &req.srq_page_dir);
4507         }
4508
4509         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4510                 ctx_pg = &ctx->cq_mem;
4511                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4512                 req.cq_num_l2_entries =
4513                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4514                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4515                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4516                                       &req.cq_pg_size_cq_lvl,
4517                                       &req.cq_page_dir);
4518         }
4519
4520         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4521                 ctx_pg = &ctx->vnic_mem;
4522                 req.vnic_num_vnic_entries =
4523                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4524                 req.vnic_num_ring_table_entries =
4525                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4526                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4527                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4528                                       &req.vnic_pg_size_vnic_lvl,
4529                                       &req.vnic_page_dir);
4530         }
4531
4532         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4533                 ctx_pg = &ctx->stat_mem;
4534                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4535                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4536                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4537                                       &req.stat_pg_size_stat_lvl,
4538                                       &req.stat_page_dir);
4539         }
4540
4541         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4542         num_entries = &req.tqm_sp_num_entries;
4543         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4544         pg_dir = &req.tqm_sp_page_dir;
4545         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4546         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4547                 if (!(enables & ena))
4548                         continue;
4549
4550                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4551
4552                 ctx_pg = ctx->tqm_mem[i];
4553                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4554                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4555         }
4556
4557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4558         HWRM_CHECK_RESULT();
4559         HWRM_UNLOCK();
4560
4561         return rc;
4562 }
4563
4564 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4565 {
4566         struct hwrm_port_qstats_ext_input req = {0};
4567         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4568         struct bnxt_pf_info *pf = &bp->pf;
4569         int rc;
4570
4571         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4572               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4573                 return 0;
4574
4575         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4576
4577         req.port_id = rte_cpu_to_le_16(pf->port_id);
4578         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4579                 req.tx_stat_host_addr =
4580                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4581                 req.tx_stat_size =
4582                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4583         }
4584         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4585                 req.rx_stat_host_addr =
4586                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4587                 req.rx_stat_size =
4588                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4589         }
4590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4591
4592         if (rc) {
4593                 bp->fw_rx_port_stats_ext_size = 0;
4594                 bp->fw_tx_port_stats_ext_size = 0;
4595         } else {
4596                 bp->fw_rx_port_stats_ext_size =
4597                         rte_le_to_cpu_16(resp->rx_stat_size);
4598                 bp->fw_tx_port_stats_ext_size =
4599                         rte_le_to_cpu_16(resp->tx_stat_size);
4600         }
4601
4602         HWRM_CHECK_RESULT();
4603         HWRM_UNLOCK();
4604
4605         return rc;
4606 }
4607
4608 int
4609 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4610 {
4611         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4612         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4613                 bp->hwrm_cmd_resp_addr;
4614         int rc = 0;
4615
4616         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4617         req.tunnel_type = type;
4618         req.dest_fid = bp->fw_fid;
4619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4620         HWRM_CHECK_RESULT();
4621
4622         HWRM_UNLOCK();
4623
4624         return rc;
4625 }
4626
4627 int
4628 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4629 {
4630         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4631         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4632                 bp->hwrm_cmd_resp_addr;
4633         int rc = 0;
4634
4635         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4636         req.tunnel_type = type;
4637         req.dest_fid = bp->fw_fid;
4638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4639         HWRM_CHECK_RESULT();
4640
4641         HWRM_UNLOCK();
4642
4643         return rc;
4644 }
4645
4646 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4647 {
4648         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4649         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4650                 bp->hwrm_cmd_resp_addr;
4651         int rc = 0;
4652
4653         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4654         req.src_fid = bp->fw_fid;
4655         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4656         HWRM_CHECK_RESULT();
4657
4658         if (type)
4659                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4660
4661         HWRM_UNLOCK();
4662
4663         return rc;
4664 }
4665
4666 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4667                                    uint16_t *dst_fid)
4668 {
4669         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4670         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4671                 bp->hwrm_cmd_resp_addr;
4672         int rc = 0;
4673
4674         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4675         req.src_fid = bp->fw_fid;
4676         req.tunnel_type = tun_type;
4677         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4678         HWRM_CHECK_RESULT();
4679
4680         if (dst_fid)
4681                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4682
4683         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4684
4685         HWRM_UNLOCK();
4686
4687         return rc;
4688 }
4689
4690 int bnxt_hwrm_set_mac(struct bnxt *bp)
4691 {
4692         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4693         struct hwrm_func_vf_cfg_input req = {0};
4694         int rc = 0;
4695
4696         if (!BNXT_VF(bp))
4697                 return 0;
4698
4699         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4700
4701         req.enables =
4702                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4703         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4704
4705         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4706
4707         HWRM_CHECK_RESULT();
4708
4709         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4710         HWRM_UNLOCK();
4711
4712         return rc;
4713 }
4714
4715 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4716 {
4717         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4718         struct hwrm_func_drv_if_change_input req = {0};
4719         uint32_t flags;
4720         int rc;
4721
4722         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4723                 return 0;
4724
4725         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4726          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4727          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4728          */
4729         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4730                 return 0;
4731
4732         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4733
4734         if (up)
4735                 req.flags =
4736                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4737
4738         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4739
4740         HWRM_CHECK_RESULT();
4741         flags = rte_le_to_cpu_32(resp->flags);
4742         HWRM_UNLOCK();
4743
4744         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4745                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4746                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4747         }
4748
4749         return 0;
4750 }
4751
4752 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4753 {
4754         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4755         struct bnxt_error_recovery_info *info = bp->recovery_info;
4756         struct hwrm_error_recovery_qcfg_input req = {0};
4757         uint32_t flags = 0;
4758         unsigned int i;
4759         int rc;
4760
4761         /* Older FW does not have error recovery support */
4762         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4763                 return 0;
4764
4765         if (!info) {
4766                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4767                                    sizeof(*info), 0);
4768                 bp->recovery_info = info;
4769                 if (info == NULL)
4770                         return -ENOMEM;
4771         } else {
4772                 memset(info, 0, sizeof(*info));
4773         }
4774
4775         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4776
4777         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4778
4779         HWRM_CHECK_RESULT();
4780
4781         flags = rte_le_to_cpu_32(resp->flags);
4782         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4783                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4784         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4785                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4786
4787         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4788             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4789                 rc = -EINVAL;
4790                 goto err;
4791         }
4792
4793         /* FW returned values are in units of 100msec */
4794         info->driver_polling_freq =
4795                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4796         info->master_func_wait_period =
4797                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4798         info->normal_func_wait_period =
4799                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4800         info->master_func_wait_period_after_reset =
4801                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4802         info->max_bailout_time_after_reset =
4803                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4804         info->status_regs[BNXT_FW_STATUS_REG] =
4805                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4806         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4807                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4808         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4809                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4810         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4811                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4812         info->reg_array_cnt =
4813                 rte_le_to_cpu_32(resp->reg_array_cnt);
4814
4815         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4816                 rc = -EINVAL;
4817                 goto err;
4818         }
4819
4820         for (i = 0; i < info->reg_array_cnt; i++) {
4821                 info->reset_reg[i] =
4822                         rte_le_to_cpu_32(resp->reset_reg[i]);
4823                 info->reset_reg_val[i] =
4824                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4825                 info->delay_after_reset[i] =
4826                         resp->delay_after_reset[i];
4827         }
4828 err:
4829         HWRM_UNLOCK();
4830
4831         /* Map the FW status registers */
4832         if (!rc)
4833                 rc = bnxt_map_fw_health_status_regs(bp);
4834
4835         if (rc) {
4836                 rte_free(bp->recovery_info);
4837                 bp->recovery_info = NULL;
4838         }
4839         return rc;
4840 }
4841
4842 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4843 {
4844         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4845         struct hwrm_fw_reset_input req = {0};
4846         int rc;
4847
4848         if (!BNXT_PF(bp))
4849                 return -EOPNOTSUPP;
4850
4851         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4852
4853         req.embedded_proc_type =
4854                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4855         req.selfrst_status =
4856                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4857         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4858
4859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4860                                     BNXT_USE_KONG(bp));
4861
4862         HWRM_CHECK_RESULT();
4863         HWRM_UNLOCK();
4864
4865         return rc;
4866 }
4867
4868 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4869 {
4870         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4871         struct hwrm_port_ts_query_input req = {0};
4872         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4873         uint32_t flags = 0;
4874         int rc;
4875
4876         if (!ptp)
4877                 return 0;
4878
4879         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4880
4881         switch (path) {
4882         case BNXT_PTP_FLAGS_PATH_TX:
4883                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4884                 break;
4885         case BNXT_PTP_FLAGS_PATH_RX:
4886                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4887                 break;
4888         case BNXT_PTP_FLAGS_CURRENT_TIME:
4889                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4890                 break;
4891         }
4892
4893         req.flags = rte_cpu_to_le_32(flags);
4894         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4895
4896         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4897
4898         HWRM_CHECK_RESULT();
4899
4900         if (timestamp) {
4901                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4902                 *timestamp |=
4903                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4904         }
4905         HWRM_UNLOCK();
4906
4907         return rc;
4908 }