drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 131         }
 132
 133         /* Write request msg to hwrm channel */
 134         for (i = 0; i < msg_len; i += 4) {
 135                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 136                 rte_write32(*data, bar);
 137                 data++;
 138         }
 139
 140         /* Zero the rest of the request space */
 141         for (; i < max_req_len; i += 4) {
 142                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 143                 rte_write32(0, bar);
 144         }
 145
 146         /* Ring channel doorbell */
 147         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 148         rte_write32(1, bar);
 149         /*
 150          * Make sure the channel doorbell ring command complete before
 151          * reading the response to avoid getting stale or invalid
 152          * responses.
 153          */
 154         rte_io_mb();
 155
 156         /* Poll for the valid bit */
 157         for (i = 0; i < timeout; i++) {
 158                 /* Sanity check on the resp->resp_len */
 159                 rte_cio_rmb();
 160                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 161                         /* Last byte of resp contains the valid key */
 162                         valid = (uint8_t *)resp + resp->resp_len - 1;
 163                         if (*valid == HWRM_RESP_VALID_KEY)
 164                                 break;
 165                 }
 166                 rte_delay_us(1);
 167         }
 168
 169         if (i >= timeout) {
 170                 /* Suppress VER_GET timeout messages during reset recovery */
 171                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 172                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 173                         return -ETIMEDOUT;
 174
 175                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 176                             req->req_type);
 177                 return -ETIMEDOUT;
 178         }
 179         return 0;
 180 }
 181
 182 /*
 183  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 184  * spinlock, and does initial processing.
 185  *
 186  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 187  * releases the spinlock only if it returns.  If the regular int return codes
 188  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 189  * directly, rather it should be copied and modified to suit the function.
 190  *
 191  * HWRM_UNLOCK() must be called after all response processing is completed.
 192  */
 193 #define HWRM_PREP(req, type, kong) do { \
 194         rte_spinlock_lock(&bp->hwrm_lock); \
 195         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 196         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 197         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 198         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 199                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 200         req.target_id = rte_cpu_to_le_16(0xffff); \
 201         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 202 } while (0)
 203
 204 #define HWRM_CHECK_RESULT_SILENT() do {\
 205         if (rc) { \
 206                 rte_spinlock_unlock(&bp->hwrm_lock); \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 rte_spinlock_unlock(&bp->hwrm_lock); \
 212                 return rc; \
 213         } \
 214 } while (0)
 215
 216 #define HWRM_CHECK_RESULT() do {\
 217         if (rc) { \
 218                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 219                 rte_spinlock_unlock(&bp->hwrm_lock); \
 220                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 221                         rc = -EACCES; \
 222                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 223                         rc = -ENOSPC; \
 224                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 225                         rc = -EINVAL; \
 226                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 227                         rc = -ENOTSUP; \
 228                 else if (rc > 0) \
 229                         rc = -EIO; \
 230                 return rc; \
 231         } \
 232         if (resp->error_code) { \
 233                 rc = rte_le_to_cpu_16(resp->error_code); \
 234                 if (resp->resp_len >= 16) { \
 235                         struct hwrm_err_output *tmp_hwrm_err_op = \
 236                                                 (void *)resp; \
 237                         PMD_DRV_LOG(ERR, \
 238                                 "error %d:%d:%08x:%04x\n", \
 239                                 rc, tmp_hwrm_err_op->cmd_err, \
 240                                 rte_le_to_cpu_32(\
 241                                         tmp_hwrm_err_op->opaque_0), \
 242                                 rte_le_to_cpu_16(\
 243                                         tmp_hwrm_err_op->opaque_1)); \
 244                 } else { \
 245                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 246                 } \
 247                 rte_spinlock_unlock(&bp->hwrm_lock); \
 248                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 249                         rc = -EACCES; \
 250                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 251                         rc = -ENOSPC; \
 252                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 253                         rc = -EINVAL; \
 254                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 255                         rc = -ENOTSUP; \
 256                 else if (rc > 0) \
 257                         rc = -EIO; \
 258                 return rc; \
 259         } \
 260 } while (0)
 261
 262 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 263
 264 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 268         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 269
 270         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 271         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 272         req.mask = 0;
 273
 274         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 275
 276         HWRM_CHECK_RESULT();
 277         HWRM_UNLOCK();
 278
 279         return rc;
 280 }
 281
 282 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 283                                  struct bnxt_vnic_info *vnic,
 284                                  uint16_t vlan_count,
 285                                  struct bnxt_vlan_table_entry *vlan_table)
 286 {
 287         int rc = 0;
 288         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 289         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 290         uint32_t mask = 0;
 291
 292         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 293                 return rc;
 294
 295         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 296         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 297
 298         /* FIXME add multicast flag, when multicast adding options is supported
 299          * by ethtool.
 300          */
 301         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 302                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 303         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 304                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 305         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 306                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 307         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 308                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 309         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 310                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 311         if (vnic->mc_addr_cnt) {
 312                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 313                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 314                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 315         }
 316         if (vlan_table) {
 317                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 318                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 319                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 320                          rte_mem_virt2iova(vlan_table));
 321                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 322         }
 323         req.mask = rte_cpu_to_le_32(mask);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 326
 327         HWRM_CHECK_RESULT();
 328         HWRM_UNLOCK();
 329
 330         return rc;
 331 }
 332
 333 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 334                         uint16_t vlan_count,
 335                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 336 {
 337         int rc = 0;
 338         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 339         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 340                                                 bp->hwrm_cmd_resp_addr;
 341
 342         /*
 343          * Older HWRM versions did not support this command, and the set_rx_mask
 344          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 345          * removed from set_rx_mask call, and this command was added.
 346          *
 347          * This command is also present from 1.7.8.11 and higher,
 348          * as well as 1.7.8.0
 349          */
 350         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 351                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 352                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 353                                         (11)))
 354                                 return 0;
 355                 }
 356         }
 357         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 358         req.fid = rte_cpu_to_le_16(fid);
 359
 360         req.vlan_tag_mask_tbl_addr =
 361                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 362         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 363
 364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 365
 366         HWRM_CHECK_RESULT();
 367         HWRM_UNLOCK();
 368
 369         return rc;
 370 }
 371
 372 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 373                            struct bnxt_filter_info *filter)
 374 {
 375         int rc = 0;
 376         struct bnxt_filter_info *l2_filter = filter;
 377         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 378         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 379
 380         if (filter->fw_l2_filter_id == UINT64_MAX)
 381                 return 0;
 382
 383         if (filter->matching_l2_fltr_ptr)
 384                 l2_filter = filter->matching_l2_fltr_ptr;
 385
 386         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 387                     filter, l2_filter, l2_filter->l2_ref_cnt);
 388
 389         if (l2_filter->l2_ref_cnt > 0)
 390                 l2_filter->l2_ref_cnt--;
 391
 392         if (l2_filter->l2_ref_cnt > 0)
 393                 return 0;
 394
 395         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 396
 397         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 398
 399         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 400
 401         HWRM_CHECK_RESULT();
 402         HWRM_UNLOCK();
 403
 404         filter->fw_l2_filter_id = UINT64_MAX;
 405
 406         return 0;
 407 }
 408
 409 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 410                          uint16_t dst_id,
 411                          struct bnxt_filter_info *filter)
 412 {
 413         int rc = 0;
 414         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 415         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 416         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 417         const struct rte_eth_vmdq_rx_conf *conf =
 418                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 419         uint32_t enables = 0;
 420         uint16_t j = dst_id - 1;
 421
 422         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 423         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 424             conf->pool_map[j].pools & (1UL << j)) {
 425                 PMD_DRV_LOG(DEBUG,
 426                         "Add vlan %u to vmdq pool %u\n",
 427                         conf->pool_map[j].vlan_id, j);
 428
 429                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 430                 filter->enables |=
 431                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 432                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 433         }
 434
 435         if (filter->fw_l2_filter_id != UINT64_MAX)
 436                 bnxt_hwrm_clear_l2_filter(bp, filter);
 437
 438         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 439
 440         req.flags = rte_cpu_to_le_32(filter->flags);
 441
 442         enables = filter->enables |
 443               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 444         req.dst_id = rte_cpu_to_le_16(dst_id);
 445
 446         if (enables &
 447             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 448                 memcpy(req.l2_addr, filter->l2_addr,
 449                        RTE_ETHER_ADDR_LEN);
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 452                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 453                        RTE_ETHER_ADDR_LEN);
 454         if (enables &
 455             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 456                 req.l2_ovlan = filter->l2_ovlan;
 457         if (enables &
 458             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 459                 req.l2_ivlan = filter->l2_ivlan;
 460         if (enables &
 461             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 462                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 463         if (enables &
 464             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 465                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 466         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 467                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 468         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 469                 req.src_type = filter->src_type;
 470         if (filter->pri_hint) {
 471                 req.pri_hint = filter->pri_hint;
 472                 req.l2_filter_id_hint =
 473                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 474         }
 475
 476         req.enables = rte_cpu_to_le_32(enables);
 477
 478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 479
 480         HWRM_CHECK_RESULT();
 481
 482         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 483         HWRM_UNLOCK();
 484
 485         return rc;
 486 }
 487
 488 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 489 {
 490         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 491         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 492         uint32_t flags = 0;
 493         int rc;
 494
 495         if (!ptp)
 496                 return 0;
 497
 498         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 499
 500         if (ptp->rx_filter)
 501                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 502         else
 503                 flags |=
 504                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 505         if (ptp->tx_tstamp_en)
 506                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 507         else
 508                 flags |=
 509                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 510         req.flags = rte_cpu_to_le_32(flags);
 511         req.enables = rte_cpu_to_le_32
 512                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 513         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 514
 515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 516         HWRM_UNLOCK();
 517
 518         return rc;
 519 }
 520
 521 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 522 {
 523         int rc = 0;
 524         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 525         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 526         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 527
 528 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 529         if (ptp)
 530                 return 0;
 531
 532         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 533
 534         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 535
 536         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 537
 538         HWRM_CHECK_RESULT();
 539
 540         if (!BNXT_CHIP_THOR(bp) &&
 541             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 542                 return 0;
 543
 544         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 545                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 546
 547         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 548         if (!ptp)
 549                 return -ENOMEM;
 550
 551         if (!BNXT_CHIP_THOR(bp)) {
 552                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 553                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 554                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 555                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 556                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 557                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 558                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 559                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 560                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 561                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 562                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 563                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 564                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 565                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 566                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 567                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 568                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 569                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 570         }
 571
 572         ptp->bp = bp;
 573         bp->ptp_cfg = ptp;
 574
 575         return 0;
 576 }
 577
 578 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 579 {
 580         int rc = 0;
 581         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 582         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 583         uint16_t new_max_vfs;
 584         uint32_t flags;
 585         int i;
 586
 587         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 588
 589         req.fid = rte_cpu_to_le_16(0xffff);
 590
 591         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 592
 593         HWRM_CHECK_RESULT();
 594
 595         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 596         flags = rte_le_to_cpu_32(resp->flags);
 597         if (BNXT_PF(bp)) {
 598                 bp->pf.port_id = resp->port_id;
 599                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 600                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 601                 new_max_vfs = bp->pdev->max_vfs;
 602                 if (new_max_vfs != bp->pf.max_vfs) {
 603                         if (bp->pf.vf_info)
 604                                 rte_free(bp->pf.vf_info);
 605                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 606                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 607                         bp->pf.max_vfs = new_max_vfs;
 608                         for (i = 0; i < new_max_vfs; i++) {
 609                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 610                                 bp->pf.vf_info[i].vlan_table =
 611                                         rte_zmalloc("VF VLAN table",
 612                                                     getpagesize(),
 613                                                     getpagesize());
 614                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 615                                         PMD_DRV_LOG(ERR,
 616                                         "Fail to alloc VLAN table for VF %d\n",
 617                                         i);
 618                                 else
 619                                         rte_mem_lock_page(
 620                                                 bp->pf.vf_info[i].vlan_table);
 621                                 bp->pf.vf_info[i].vlan_as_table =
 622                                         rte_zmalloc("VF VLAN AS table",
 623                                                     getpagesize(),
 624                                                     getpagesize());
 625                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 626                                         PMD_DRV_LOG(ERR,
 627                                         "Alloc VLAN AS table for VF %d fail\n",
 628                                         i);
 629                                 else
 630                                         rte_mem_lock_page(
 631                                                bp->pf.vf_info[i].vlan_as_table);
 632                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 633                         }
 634                 }
 635         }
 636
 637         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 638         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 639         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 640         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 641         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 642         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 643         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 644         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 645         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 646         if (!BNXT_CHIP_THOR(bp))
 647                 bp->max_l2_ctx += bp->max_rx_em_flows;
 648         /* TODO: For now, do not support VMDq/RFS on VFs. */
 649         if (BNXT_PF(bp)) {
 650                 if (bp->pf.max_vfs)
 651                         bp->max_vnics = 1;
 652                 else
 653                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 654         } else {
 655                 bp->max_vnics = 1;
 656         }
 657         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 658         if (BNXT_PF(bp)) {
 659                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 660                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 661                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 662                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 663                         HWRM_UNLOCK();
 664                         bnxt_hwrm_ptp_qcfg(bp);
 665                 }
 666         }
 667
 668         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 669                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 672                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 673                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 674         } else {
 675                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 676         }
 677
 678         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 679                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 680         else
 681                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 682
 683         HWRM_UNLOCK();
 684
 685         return rc;
 686 }
 687
 688 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 689 {
 690         int rc;
 691
 692         rc = __bnxt_hwrm_func_qcaps(bp);
 693         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 694                 rc = bnxt_alloc_ctx_mem(bp);
 695                 if (rc)
 696                         return rc;
 697
 698                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 699                 if (!rc)
 700                         bp->flags |= BNXT_FLAG_NEW_RM;
 701         }
 702
 703         return rc;
 704 }
 705
 706 int bnxt_hwrm_func_reset(struct bnxt *bp)
 707 {
 708         int rc = 0;
 709         struct hwrm_func_reset_input req = {.req_type = 0 };
 710         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 711
 712         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 713
 714         req.enables = rte_cpu_to_le_32(0);
 715
 716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 717
 718         HWRM_CHECK_RESULT();
 719         HWRM_UNLOCK();
 720
 721         return rc;
 722 }
 723
 724 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 725 {
 726         int rc;
 727         uint32_t flags = 0;
 728         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 729         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 730
 731         if (bp->flags & BNXT_FLAG_REGISTERED)
 732                 return 0;
 733
 734         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 735         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 736                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 737
 738         /* PFs and trusted VFs should indicate the support of the
 739          * Master capability on non Stingray platform
 740          */
 741         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 742                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 743
 744         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 745         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 746                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 747         req.ver_maj = RTE_VER_YEAR;
 748         req.ver_min = RTE_VER_MONTH;
 749         req.ver_upd = RTE_VER_MINOR;
 750
 751         if (BNXT_PF(bp)) {
 752                 req.enables |= rte_cpu_to_le_32(
 753                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 754                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 755                        RTE_MIN(sizeof(req.vf_req_fwd),
 756                                sizeof(bp->pf.vf_req_fwd)));
 757
 758                 /*
 759                  * PF can sniff HWRM API issued by VF. This can be set up by
 760                  * linux driver and inherited by the DPDK PF driver. Clear
 761                  * this HWRM sniffer list in FW because DPDK PF driver does
 762                  * not support this.
 763                  */
 764                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 765         }
 766
 767         req.flags = rte_cpu_to_le_32(flags);
 768
 769         req.async_event_fwd[0] |=
 770                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 771                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 772                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 773                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 774                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 775         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 776                 req.async_event_fwd[0] |=
 777                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 778         req.async_event_fwd[1] |=
 779                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 780                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 781
 782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 783
 784         HWRM_CHECK_RESULT();
 785
 786         flags = rte_le_to_cpu_32(resp->flags);
 787         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 788                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 789
 790         HWRM_UNLOCK();
 791
 792         bp->flags |= BNXT_FLAG_REGISTERED;
 793
 794         return rc;
 795 }
 796
 797 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 798 {
 799         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 800                 return 0;
 801
 802         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 803 }
 804
 805 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 806 {
 807         int rc;
 808         uint32_t flags = 0;
 809         uint32_t enables;
 810         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 811         struct hwrm_func_vf_cfg_input req = {0};
 812
 813         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 814
 815         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 816                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 817                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 818                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 819                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 820
 821         if (BNXT_HAS_RING_GRPS(bp)) {
 822                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 823                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 824         }
 825
 826         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 827         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 828                                             AGG_RING_MULTIPLIER);
 829         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 830                                              bp->tx_nr_rings +
 831                                              BNXT_NUM_ASYNC_CPR(bp));
 832         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 833                                               bp->tx_nr_rings +
 834                                               BNXT_NUM_ASYNC_CPR(bp));
 835         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 836         if (bp->vf_resv_strategy ==
 837             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 838                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 839                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 840                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 841                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 842                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 843                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 844         }
 845
 846         if (test)
 847                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 848                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 849                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 850                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 851                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 852                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 853
 854         if (test && BNXT_HAS_RING_GRPS(bp))
 855                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 856
 857         req.flags = rte_cpu_to_le_32(flags);
 858         req.enables |= rte_cpu_to_le_32(enables);
 859
 860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 861
 862         if (test)
 863                 HWRM_CHECK_RESULT_SILENT();
 864         else
 865                 HWRM_CHECK_RESULT();
 866
 867         HWRM_UNLOCK();
 868         return rc;
 869 }
 870
 871 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 872 {
 873         int rc;
 874         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 875         struct hwrm_func_resource_qcaps_input req = {0};
 876
 877         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 878         req.fid = rte_cpu_to_le_16(0xffff);
 879
 880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 881
 882         HWRM_CHECK_RESULT();
 883
 884         if (BNXT_VF(bp)) {
 885                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 886                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 887                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 888                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 889                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 890                 /* func_resource_qcaps does not return max_rx_em_flows.
 891                  * So use the value provided by func_qcaps.
 892                  */
 893                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 894                 if (!BNXT_CHIP_THOR(bp))
 895                         bp->max_l2_ctx += bp->max_rx_em_flows;
 896                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 897                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 898         }
 899         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 900         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 901         if (bp->vf_resv_strategy >
 902             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 903                 bp->vf_resv_strategy =
 904                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 905
 906         HWRM_UNLOCK();
 907         return rc;
 908 }
 909
 910 int bnxt_hwrm_ver_get(struct bnxt *bp)
 911 {
 912         int rc = 0;
 913         struct hwrm_ver_get_input req = {.req_type = 0 };
 914         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 915         uint32_t fw_version;
 916         uint16_t max_resp_len;
 917         char type[RTE_MEMZONE_NAMESIZE];
 918         uint32_t dev_caps_cfg;
 919
 920         bp->max_req_len = HWRM_MAX_REQ_LEN;
 921         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 922
 923         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 924         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 925         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 926
 927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 928
 929         if (bp->flags & BNXT_FLAG_FW_RESET)
 930                 HWRM_CHECK_RESULT_SILENT();
 931         else
 932                 HWRM_CHECK_RESULT();
 933
 934         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 935                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 936                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 937                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 938         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 939                      (resp->hwrm_fw_min_8b << 16) |
 940                      (resp->hwrm_fw_bld_8b << 8) |
 941                      resp->hwrm_fw_rsvd_8b;
 942         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 943                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 944
 945         fw_version = resp->hwrm_intf_maj_8b << 16;
 946         fw_version |= resp->hwrm_intf_min_8b << 8;
 947         fw_version |= resp->hwrm_intf_upd_8b;
 948         bp->hwrm_spec_code = fw_version;
 949
 950         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 951                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 952                 rc = -EINVAL;
 953                 goto error;
 954         }
 955
 956         if (bp->max_req_len > resp->max_req_win_len) {
 957                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 958                 rc = -EINVAL;
 959         }
 960         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 961         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 962         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 963                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 964
 965         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 966         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 967
 968         if (bp->max_resp_len != max_resp_len) {
 969                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 970                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 971                         bp->pdev->addr.devid, bp->pdev->addr.function);
 972
 973                 rte_free(bp->hwrm_cmd_resp_addr);
 974
 975                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 976                 if (bp->hwrm_cmd_resp_addr == NULL) {
 977                         rc = -ENOMEM;
 978                         goto error;
 979                 }
 980                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 981                 bp->hwrm_cmd_resp_dma_addr =
 982                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 983                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 984                         PMD_DRV_LOG(ERR,
 985                         "Unable to map response buffer to physical memory.\n");
 986                         rc = -ENOMEM;
 987                         goto error;
 988                 }
 989                 bp->max_resp_len = max_resp_len;
 990         }
 991
 992         if ((dev_caps_cfg &
 993                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 994             (dev_caps_cfg &
 995              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 996                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 997                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 998         }
 999
1000         if (((dev_caps_cfg &
1001               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1002              (dev_caps_cfg &
1003               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1004             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1005                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1006                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1007                         bp->pdev->addr.devid, bp->pdev->addr.function);
1008
1009                 rte_free(bp->hwrm_short_cmd_req_addr);
1010
1011                 bp->hwrm_short_cmd_req_addr =
1012                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1013                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1014                         rc = -ENOMEM;
1015                         goto error;
1016                 }
1017                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1018                 bp->hwrm_short_cmd_req_dma_addr =
1019                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1020                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1021                         rte_free(bp->hwrm_short_cmd_req_addr);
1022                         PMD_DRV_LOG(ERR,
1023                                 "Unable to map buffer to physical memory.\n");
1024                         rc = -ENOMEM;
1025                         goto error;
1026                 }
1027         }
1028         if (dev_caps_cfg &
1029             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1030                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1031                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1032         }
1033         if (dev_caps_cfg &
1034             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1035                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1036         if (dev_caps_cfg &
1037             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1038                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1039                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1040         }
1041
1042 error:
1043         HWRM_UNLOCK();
1044         return rc;
1045 }
1046
1047 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1048 {
1049         int rc;
1050         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1051         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1052
1053         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1054                 return 0;
1055
1056         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1057         req.flags = flags;
1058
1059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1060
1061         HWRM_CHECK_RESULT();
1062         HWRM_UNLOCK();
1063
1064         return rc;
1065 }
1066
1067 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1068 {
1069         int rc = 0;
1070         struct hwrm_port_phy_cfg_input req = {0};
1071         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1072         uint32_t enables = 0;
1073
1074         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1075
1076         if (conf->link_up) {
1077                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1078                 if (bp->link_info.auto_mode && conf->link_speed) {
1079                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1080                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1081                 }
1082
1083                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1084                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1085                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1086                 /*
1087                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1088                  * any auto mode, even "none".
1089                  */
1090                 if (!conf->link_speed) {
1091                         /* No speeds specified. Enable AutoNeg - all speeds */
1092                         req.auto_mode =
1093                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1094                 }
1095                 /* AutoNeg - Advertise speeds specified. */
1096                 if (conf->auto_link_speed_mask &&
1097                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1098                         req.auto_mode =
1099                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1100                         req.auto_link_speed_mask =
1101                                 conf->auto_link_speed_mask;
1102                         enables |=
1103                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1104                 }
1105
1106                 req.auto_duplex = conf->duplex;
1107                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1108                 req.auto_pause = conf->auto_pause;
1109                 req.force_pause = conf->force_pause;
1110                 /* Set force_pause if there is no auto or if there is a force */
1111                 if (req.auto_pause && !req.force_pause)
1112                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1113                 else
1114                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1115
1116                 req.enables = rte_cpu_to_le_32(enables);
1117         } else {
1118                 req.flags =
1119                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1120                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1121         }
1122
1123         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1124
1125         HWRM_CHECK_RESULT();
1126         HWRM_UNLOCK();
1127
1128         return rc;
1129 }
1130
1131 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1132                                    struct bnxt_link_info *link_info)
1133 {
1134         int rc = 0;
1135         struct hwrm_port_phy_qcfg_input req = {0};
1136         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1137
1138         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1139
1140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1141
1142         HWRM_CHECK_RESULT();
1143
1144         link_info->phy_link_status = resp->link;
1145         link_info->link_up =
1146                 (link_info->phy_link_status ==
1147                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1148         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1149         link_info->duplex = resp->duplex_cfg;
1150         link_info->pause = resp->pause;
1151         link_info->auto_pause = resp->auto_pause;
1152         link_info->force_pause = resp->force_pause;
1153         link_info->auto_mode = resp->auto_mode;
1154         link_info->phy_type = resp->phy_type;
1155         link_info->media_type = resp->media_type;
1156
1157         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1158         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1159         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1160         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1161         link_info->phy_ver[0] = resp->phy_maj;
1162         link_info->phy_ver[1] = resp->phy_min;
1163         link_info->phy_ver[2] = resp->phy_bld;
1164
1165         HWRM_UNLOCK();
1166
1167         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1168         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1169         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1170         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1171         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1172                     link_info->auto_link_speed_mask);
1173         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1174                     link_info->force_link_speed);
1175
1176         return rc;
1177 }
1178
1179 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1180 {
1181         int rc = 0;
1182         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1183         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1184         int i;
1185
1186         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1187
1188         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1189         /* HWRM Version >= 1.9.1 */
1190         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1191                 req.drv_qmap_cap =
1192                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1193         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1194
1195         HWRM_CHECK_RESULT();
1196
1197 #define GET_QUEUE_INFO(x) \
1198         bp->cos_queue[x].id = resp->queue_id##x; \
1199         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1200
1201         GET_QUEUE_INFO(0);
1202         GET_QUEUE_INFO(1);
1203         GET_QUEUE_INFO(2);
1204         GET_QUEUE_INFO(3);
1205         GET_QUEUE_INFO(4);
1206         GET_QUEUE_INFO(5);
1207         GET_QUEUE_INFO(6);
1208         GET_QUEUE_INFO(7);
1209
1210         HWRM_UNLOCK();
1211
1212         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1213                 bp->tx_cosq_id = bp->cos_queue[0].id;
1214         } else {
1215                 /* iterate and find the COSq profile to use for Tx */
1216                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1217                         if (bp->cos_queue[i].profile ==
1218                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1219                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1220                                 break;
1221                         }
1222                 }
1223         }
1224
1225         bp->max_tc = resp->max_configurable_queues;
1226         bp->max_lltc = resp->max_configurable_lossless_queues;
1227         if (bp->max_tc > BNXT_MAX_QUEUE)
1228                 bp->max_tc = BNXT_MAX_QUEUE;
1229         bp->max_q = bp->max_tc;
1230
1231         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1232
1233         return rc;
1234 }
1235
1236 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1237                          struct bnxt_ring *ring,
1238                          uint32_t ring_type, uint32_t map_index,
1239                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1240 {
1241         int rc = 0;
1242         uint32_t enables = 0;
1243         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1244         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1245         struct rte_mempool *mb_pool;
1246         uint16_t rx_buf_size;
1247
1248         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1249
1250         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1251         req.fbo = rte_cpu_to_le_32(0);
1252         /* Association of ring index with doorbell index */
1253         req.logical_id = rte_cpu_to_le_16(map_index);
1254         req.length = rte_cpu_to_le_32(ring->ring_size);
1255
1256         switch (ring_type) {
1257         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1258                 req.ring_type = ring_type;
1259                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1260                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1261                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1262                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1263                         enables |=
1264                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1265                 break;
1266         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1267                 req.ring_type = ring_type;
1268                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1269                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1270                 if (BNXT_CHIP_THOR(bp)) {
1271                         mb_pool = bp->rx_queues[0]->mb_pool;
1272                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1273                                       RTE_PKTMBUF_HEADROOM;
1274                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1275                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1276                         enables |=
1277                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1278                 }
1279                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1280                         enables |=
1281                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1282                 break;
1283         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1284                 req.ring_type = ring_type;
1285                 if (BNXT_HAS_NQ(bp)) {
1286                         /* Association of cp ring with nq */
1287                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1288                         enables |=
1289                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1290                 }
1291                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1292                 break;
1293         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1294                 req.ring_type = ring_type;
1295                 req.page_size = BNXT_PAGE_SHFT;
1296                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1297                 break;
1298         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1299                 req.ring_type = ring_type;
1300                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1301
1302                 mb_pool = bp->rx_queues[0]->mb_pool;
1303                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1304                               RTE_PKTMBUF_HEADROOM;
1305                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1306                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1307
1308                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1309                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1310                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1311                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1312                 break;
1313         default:
1314                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1315                         ring_type);
1316                 HWRM_UNLOCK();
1317                 return -EINVAL;
1318         }
1319         req.enables = rte_cpu_to_le_32(enables);
1320
1321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322
1323         if (rc || resp->error_code) {
1324                 if (rc == 0 && resp->error_code)
1325                         rc = rte_le_to_cpu_16(resp->error_code);
1326                 switch (ring_type) {
1327                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1328                         PMD_DRV_LOG(ERR,
1329                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1330                         HWRM_UNLOCK();
1331                         return rc;
1332                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1333                         PMD_DRV_LOG(ERR,
1334                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1335                         HWRM_UNLOCK();
1336                         return rc;
1337                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1338                         PMD_DRV_LOG(ERR,
1339                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1340                                     rc);
1341                         HWRM_UNLOCK();
1342                         return rc;
1343                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1344                         PMD_DRV_LOG(ERR,
1345                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1346                         HWRM_UNLOCK();
1347                         return rc;
1348                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1349                         PMD_DRV_LOG(ERR,
1350                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1351                         HWRM_UNLOCK();
1352                         return rc;
1353                 default:
1354                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1355                         HWRM_UNLOCK();
1356                         return rc;
1357                 }
1358         }
1359
1360         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1361         HWRM_UNLOCK();
1362         return rc;
1363 }
1364
1365 int bnxt_hwrm_ring_free(struct bnxt *bp,
1366                         struct bnxt_ring *ring, uint32_t ring_type)
1367 {
1368         int rc;
1369         struct hwrm_ring_free_input req = {.req_type = 0 };
1370         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1371
1372         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1373
1374         req.ring_type = ring_type;
1375         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1376
1377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1378
1379         if (rc || resp->error_code) {
1380                 if (rc == 0 && resp->error_code)
1381                         rc = rte_le_to_cpu_16(resp->error_code);
1382                 HWRM_UNLOCK();
1383
1384                 switch (ring_type) {
1385                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1386                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1387                                 rc);
1388                         return rc;
1389                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1390                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1391                                 rc);
1392                         return rc;
1393                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1394                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1395                                 rc);
1396                         return rc;
1397                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1398                         PMD_DRV_LOG(ERR,
1399                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1400                         return rc;
1401                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1402                         PMD_DRV_LOG(ERR,
1403                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1404                         return rc;
1405                 default:
1406                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1407                         return rc;
1408                 }
1409         }
1410         HWRM_UNLOCK();
1411         return 0;
1412 }
1413
1414 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1415 {
1416         int rc = 0;
1417         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1418         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1419
1420         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1421
1422         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1423         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1424         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1425         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1426
1427         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1428
1429         HWRM_CHECK_RESULT();
1430
1431         bp->grp_info[idx].fw_grp_id =
1432             rte_le_to_cpu_16(resp->ring_group_id);
1433
1434         HWRM_UNLOCK();
1435
1436         return rc;
1437 }
1438
1439 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1440 {
1441         int rc;
1442         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1443         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1444
1445         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1446
1447         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1448
1449         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1450
1451         HWRM_CHECK_RESULT();
1452         HWRM_UNLOCK();
1453
1454         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1455         return rc;
1456 }
1457
1458 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1459 {
1460         int rc = 0;
1461         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1462         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1463
1464         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1465                 return rc;
1466
1467         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1468
1469         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1470
1471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1472
1473         HWRM_CHECK_RESULT();
1474         HWRM_UNLOCK();
1475
1476         return rc;
1477 }
1478
1479 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1480                                 unsigned int idx __rte_unused)
1481 {
1482         int rc;
1483         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1484         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1485
1486         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1487
1488         req.update_period_ms = rte_cpu_to_le_32(0);
1489
1490         req.stats_dma_addr =
1491             rte_cpu_to_le_64(cpr->hw_stats_map);
1492
1493         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1494
1495         HWRM_CHECK_RESULT();
1496
1497         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1498
1499         HWRM_UNLOCK();
1500
1501         return rc;
1502 }
1503
1504 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1505                                 unsigned int idx __rte_unused)
1506 {
1507         int rc;
1508         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1509         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1510
1511         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1512
1513         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1514
1515         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1516
1517         HWRM_CHECK_RESULT();
1518         HWRM_UNLOCK();
1519
1520         return rc;
1521 }
1522
1523 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1524 {
1525         int rc = 0, i, j;
1526         struct hwrm_vnic_alloc_input req = { 0 };
1527         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1528
1529         if (!BNXT_HAS_RING_GRPS(bp))
1530                 goto skip_ring_grps;
1531
1532         /* map ring groups to this vnic */
1533         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1534                 vnic->start_grp_id, vnic->end_grp_id);
1535         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1536                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1537
1538         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1539         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1540         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1541         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1542
1543 skip_ring_grps:
1544         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1545                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1546         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1547
1548         if (vnic->func_default)
1549                 req.flags =
1550                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1551         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1552
1553         HWRM_CHECK_RESULT();
1554
1555         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1556         HWRM_UNLOCK();
1557         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1558         return rc;
1559 }
1560
1561 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1562                                         struct bnxt_vnic_info *vnic,
1563                                         struct bnxt_plcmodes_cfg *pmode)
1564 {
1565         int rc = 0;
1566         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1567         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1568
1569         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1570
1571         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1572
1573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1574
1575         HWRM_CHECK_RESULT();
1576
1577         pmode->flags = rte_le_to_cpu_32(resp->flags);
1578         /* dflt_vnic bit doesn't exist in the _cfg command */
1579         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1580         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1581         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1582         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1583
1584         HWRM_UNLOCK();
1585
1586         return rc;
1587 }
1588
1589 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1590                                        struct bnxt_vnic_info *vnic,
1591                                        struct bnxt_plcmodes_cfg *pmode)
1592 {
1593         int rc = 0;
1594         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1595         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1596
1597         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1598                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1599                 return rc;
1600         }
1601
1602         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1603
1604         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1605         req.flags = rte_cpu_to_le_32(pmode->flags);
1606         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1607         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1608         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1609         req.enables = rte_cpu_to_le_32(
1610             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1611             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1612             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1613         );
1614
1615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1616
1617         HWRM_CHECK_RESULT();
1618         HWRM_UNLOCK();
1619
1620         return rc;
1621 }
1622
1623 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1624 {
1625         int rc = 0;
1626         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1627         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1628         struct bnxt_plcmodes_cfg pmodes = { 0 };
1629         uint32_t ctx_enable_flag = 0;
1630         uint32_t enables = 0;
1631
1632         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1633                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1634                 return rc;
1635         }
1636
1637         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1638         if (rc)
1639                 return rc;
1640
1641         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1642
1643         if (BNXT_CHIP_THOR(bp)) {
1644                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1645                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1646                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1647
1648                 req.default_rx_ring_id =
1649                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1650                 req.default_cmpl_ring_id =
1651                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1652                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1653                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1654                 goto config_mru;
1655         }
1656
1657         /* Only RSS support for now TBD: COS & LB */
1658         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1659         if (vnic->lb_rule != 0xffff)
1660                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1661         if (vnic->cos_rule != 0xffff)
1662                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1663         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1664                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1665                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1666         }
1667         enables |= ctx_enable_flag;
1668         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1669         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1670         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1671         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1672
1673 config_mru:
1674         req.enables = rte_cpu_to_le_32(enables);
1675         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1676         req.mru = rte_cpu_to_le_16(vnic->mru);
1677         /* Configure default VNIC only once. */
1678         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1679                 req.flags |=
1680                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1681                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1682         }
1683         if (vnic->vlan_strip)
1684                 req.flags |=
1685                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1686         if (vnic->bd_stall)
1687                 req.flags |=
1688                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1689         if (vnic->roce_dual)
1690                 req.flags |= rte_cpu_to_le_32(
1691                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1692         if (vnic->roce_only)
1693                 req.flags |= rte_cpu_to_le_32(
1694                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1695         if (vnic->rss_dflt_cr)
1696                 req.flags |= rte_cpu_to_le_32(
1697                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1698
1699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1700
1701         HWRM_CHECK_RESULT();
1702         HWRM_UNLOCK();
1703
1704         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1705
1706         return rc;
1707 }
1708
1709 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1710                 int16_t fw_vf_id)
1711 {
1712         int rc = 0;
1713         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1714         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1715
1716         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1717                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1718                 return rc;
1719         }
1720         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1721
1722         req.enables =
1723                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1724         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1725         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1726
1727         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1728
1729         HWRM_CHECK_RESULT();
1730
1731         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1732         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1733         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1734         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1735         vnic->mru = rte_le_to_cpu_16(resp->mru);
1736         vnic->func_default = rte_le_to_cpu_32(
1737                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1738         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1739                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1740         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1741                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1742         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1743                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1744         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1745                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1746         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1747                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1748
1749         HWRM_UNLOCK();
1750
1751         return rc;
1752 }
1753
1754 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1755                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1756 {
1757         int rc = 0;
1758         uint16_t ctx_id;
1759         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1760         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1761                                                 bp->hwrm_cmd_resp_addr;
1762
1763         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1764
1765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1766         HWRM_CHECK_RESULT();
1767
1768         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1769         if (!BNXT_HAS_RING_GRPS(bp))
1770                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1771         else if (ctx_idx == 0)
1772                 vnic->rss_rule = ctx_id;
1773
1774         HWRM_UNLOCK();
1775
1776         return rc;
1777 }
1778
1779 static
1780 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1781                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1782 {
1783         int rc = 0;
1784         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1785         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1786                                                 bp->hwrm_cmd_resp_addr;
1787
1788         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1789                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1790                 return rc;
1791         }
1792         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1793
1794         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1795
1796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1797
1798         HWRM_CHECK_RESULT();
1799         HWRM_UNLOCK();
1800
1801         return rc;
1802 }
1803
1804 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1805 {
1806         int rc = 0;
1807
1808         if (BNXT_CHIP_THOR(bp)) {
1809                 int j;
1810
1811                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1812                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1813                                                       vnic,
1814                                                       vnic->fw_grp_ids[j]);
1815                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1816                 }
1817                 vnic->num_lb_ctxts = 0;
1818         } else {
1819                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1820                 vnic->rss_rule = INVALID_HW_RING_ID;
1821         }
1822
1823         return rc;
1824 }
1825
1826 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1827 {
1828         int rc = 0;
1829         struct hwrm_vnic_free_input req = {.req_type = 0 };
1830         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1831
1832         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1833                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1834                 return rc;
1835         }
1836
1837         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1838
1839         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1840
1841         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1842
1843         HWRM_CHECK_RESULT();
1844         HWRM_UNLOCK();
1845
1846         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1847         /* Configure default VNIC again if necessary. */
1848         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1849                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1850
1851         return rc;
1852 }
1853
1854 static int
1855 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1856 {
1857         int i;
1858         int rc = 0;
1859         int nr_ctxs = vnic->num_lb_ctxts;
1860         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1861         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1862
1863         for (i = 0; i < nr_ctxs; i++) {
1864                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1865
1866                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1867                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1868                 req.hash_mode_flags = vnic->hash_mode;
1869
1870                 req.hash_key_tbl_addr =
1871                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1872
1873                 req.ring_grp_tbl_addr =
1874                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1875                                          i * HW_HASH_INDEX_SIZE);
1876                 req.ring_table_pair_index = i;
1877                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1878
1879                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1880                                             BNXT_USE_CHIMP_MB);
1881
1882                 HWRM_CHECK_RESULT();
1883                 HWRM_UNLOCK();
1884         }
1885
1886         return rc;
1887 }
1888
1889 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1890                            struct bnxt_vnic_info *vnic)
1891 {
1892         int rc = 0;
1893         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1894         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1895
1896         if (!vnic->rss_table)
1897                 return 0;
1898
1899         if (BNXT_CHIP_THOR(bp))
1900                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1901
1902         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1903
1904         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1905         req.hash_mode_flags = vnic->hash_mode;
1906
1907         req.ring_grp_tbl_addr =
1908             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1909         req.hash_key_tbl_addr =
1910             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1911         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1912         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1913
1914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1915
1916         HWRM_CHECK_RESULT();
1917         HWRM_UNLOCK();
1918
1919         return rc;
1920 }
1921
1922 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1923                         struct bnxt_vnic_info *vnic)
1924 {
1925         int rc = 0;
1926         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1927         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1928         uint16_t size;
1929
1930         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1931                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1932                 return rc;
1933         }
1934
1935         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1936
1937         req.flags = rte_cpu_to_le_32(
1938                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1939
1940         req.enables = rte_cpu_to_le_32(
1941                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1942
1943         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1944         size -= RTE_PKTMBUF_HEADROOM;
1945         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
1946
1947         req.jumbo_thresh = rte_cpu_to_le_16(size);
1948         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1949
1950         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1951
1952         HWRM_CHECK_RESULT();
1953         HWRM_UNLOCK();
1954
1955         return rc;
1956 }
1957
1958 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1959                         struct bnxt_vnic_info *vnic, bool enable)
1960 {
1961         int rc = 0;
1962         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1963         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1964
1965         if (BNXT_CHIP_THOR(bp))
1966                 return 0;
1967
1968         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1969                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
1970                 return 0;
1971         }
1972
1973         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1974
1975         if (enable) {
1976                 req.enables = rte_cpu_to_le_32(
1977                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1978                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1979                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1980                 req.flags = rte_cpu_to_le_32(
1981                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1982                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1983                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1984                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1985                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1986                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1987                 req.max_agg_segs = rte_cpu_to_le_16(5);
1988                 req.max_aggs =
1989                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1990                 req.min_agg_len = rte_cpu_to_le_32(512);
1991         }
1992         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1993
1994         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1995
1996         HWRM_CHECK_RESULT();
1997         HWRM_UNLOCK();
1998
1999         return rc;
2000 }
2001
2002 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2003 {
2004         struct hwrm_func_cfg_input req = {0};
2005         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2006         int rc;
2007
2008         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2009         req.enables = rte_cpu_to_le_32(
2010                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2011         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2012         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2013
2014         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2015
2016         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2017         HWRM_CHECK_RESULT();
2018         HWRM_UNLOCK();
2019
2020         bp->pf.vf_info[vf].random_mac = false;
2021
2022         return rc;
2023 }
2024
2025 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2026                                   uint64_t *dropped)
2027 {
2028         int rc = 0;
2029         struct hwrm_func_qstats_input req = {.req_type = 0};
2030         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2031
2032         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2033
2034         req.fid = rte_cpu_to_le_16(fid);
2035
2036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2037
2038         HWRM_CHECK_RESULT();
2039
2040         if (dropped)
2041                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2042
2043         HWRM_UNLOCK();
2044
2045         return rc;
2046 }
2047
2048 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2049                           struct rte_eth_stats *stats)
2050 {
2051         int rc = 0;
2052         struct hwrm_func_qstats_input req = {.req_type = 0};
2053         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2054
2055         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2056
2057         req.fid = rte_cpu_to_le_16(fid);
2058
2059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2060
2061         HWRM_CHECK_RESULT();
2062
2063         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2064         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2065         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2066         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2067         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2068         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2069
2070         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2071         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2072         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2073         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2074         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2075         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2076
2077         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2078         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2079         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2080
2081         HWRM_UNLOCK();
2082
2083         return rc;
2084 }
2085
2086 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2087 {
2088         int rc = 0;
2089         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2090         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2091
2092         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2093
2094         req.fid = rte_cpu_to_le_16(fid);
2095
2096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2097
2098         HWRM_CHECK_RESULT();
2099         HWRM_UNLOCK();
2100
2101         return rc;
2102 }
2103
2104 /*
2105  * HWRM utility functions
2106  */
2107
2108 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2109 {
2110         unsigned int i;
2111         int rc = 0;
2112
2113         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2114                 struct bnxt_tx_queue *txq;
2115                 struct bnxt_rx_queue *rxq;
2116                 struct bnxt_cp_ring_info *cpr;
2117
2118                 if (i >= bp->rx_cp_nr_rings) {
2119                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2120                         cpr = txq->cp_ring;
2121                 } else {
2122                         rxq = bp->rx_queues[i];
2123                         cpr = rxq->cp_ring;
2124                 }
2125
2126                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2127                 if (rc)
2128                         return rc;
2129         }
2130         return 0;
2131 }
2132
2133 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2134 {
2135         int rc;
2136         unsigned int i;
2137         struct bnxt_cp_ring_info *cpr;
2138
2139         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2140
2141                 if (i >= bp->rx_cp_nr_rings) {
2142                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2143                 } else {
2144                         cpr = bp->rx_queues[i]->cp_ring;
2145                         if (BNXT_HAS_RING_GRPS(bp))
2146                                 bp->grp_info[i].fw_stats_ctx = -1;
2147                 }
2148                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2149                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2150                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2151                         if (rc)
2152                                 return rc;
2153                 }
2154         }
2155         return 0;
2156 }
2157
2158 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2159 {
2160         unsigned int i;
2161         int rc = 0;
2162
2163         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2164                 struct bnxt_tx_queue *txq;
2165                 struct bnxt_rx_queue *rxq;
2166                 struct bnxt_cp_ring_info *cpr;
2167
2168                 if (i >= bp->rx_cp_nr_rings) {
2169                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2170                         cpr = txq->cp_ring;
2171                 } else {
2172                         rxq = bp->rx_queues[i];
2173                         cpr = rxq->cp_ring;
2174                 }
2175
2176                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2177
2178                 if (rc)
2179                         return rc;
2180         }
2181         return rc;
2182 }
2183
2184 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2185 {
2186         uint16_t idx;
2187         uint32_t rc = 0;
2188
2189         if (!BNXT_HAS_RING_GRPS(bp))
2190                 return 0;
2191
2192         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2193
2194                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2195                         continue;
2196
2197                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2198
2199                 if (rc)
2200                         return rc;
2201         }
2202         return rc;
2203 }
2204
2205 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2206 {
2207         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2208
2209         bnxt_hwrm_ring_free(bp, cp_ring,
2210                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2211         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2212         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2213                                      sizeof(*cpr->cp_desc_ring));
2214         cpr->cp_raw_cons = 0;
2215         cpr->valid = 0;
2216 }
2217
2218 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2219 {
2220         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2221
2222         bnxt_hwrm_ring_free(bp, cp_ring,
2223                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2224         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2225         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2226                         sizeof(*cpr->cp_desc_ring));
2227         cpr->cp_raw_cons = 0;
2228         cpr->valid = 0;
2229 }
2230
2231 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2232 {
2233         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2234         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2235         struct bnxt_ring *ring = rxr->rx_ring_struct;
2236         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2237
2238         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2239                 bnxt_hwrm_ring_free(bp, ring,
2240                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2241                 ring->fw_ring_id = INVALID_HW_RING_ID;
2242                 if (BNXT_HAS_RING_GRPS(bp))
2243                         bp->grp_info[queue_index].rx_fw_ring_id =
2244                                                         INVALID_HW_RING_ID;
2245                 memset(rxr->rx_desc_ring, 0,
2246                        rxr->rx_ring_struct->ring_size *
2247                        sizeof(*rxr->rx_desc_ring));
2248                 memset(rxr->rx_buf_ring, 0,
2249                        rxr->rx_ring_struct->ring_size *
2250                        sizeof(*rxr->rx_buf_ring));
2251                 rxr->rx_prod = 0;
2252         }
2253         ring = rxr->ag_ring_struct;
2254         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2255                 bnxt_hwrm_ring_free(bp, ring,
2256                                     BNXT_CHIP_THOR(bp) ?
2257                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2258                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2259                 ring->fw_ring_id = INVALID_HW_RING_ID;
2260                 memset(rxr->ag_buf_ring, 0,
2261                        rxr->ag_ring_struct->ring_size *
2262                        sizeof(*rxr->ag_buf_ring));
2263                 rxr->ag_prod = 0;
2264                 if (BNXT_HAS_RING_GRPS(bp))
2265                         bp->grp_info[queue_index].ag_fw_ring_id =
2266                                                         INVALID_HW_RING_ID;
2267         }
2268         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2269                 bnxt_free_cp_ring(bp, cpr);
2270                 if (rxq->nq_ring)
2271                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2272         }
2273
2274         if (BNXT_HAS_RING_GRPS(bp))
2275                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2276 }
2277
2278 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2279 {
2280         unsigned int i;
2281
2282         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2283                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2284                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2285                 struct bnxt_ring *ring = txr->tx_ring_struct;
2286                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2287
2288                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2289                         bnxt_hwrm_ring_free(bp, ring,
2290                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2291                         ring->fw_ring_id = INVALID_HW_RING_ID;
2292                         memset(txr->tx_desc_ring, 0,
2293                                         txr->tx_ring_struct->ring_size *
2294                                         sizeof(*txr->tx_desc_ring));
2295                         memset(txr->tx_buf_ring, 0,
2296                                         txr->tx_ring_struct->ring_size *
2297                                         sizeof(*txr->tx_buf_ring));
2298                         txr->tx_prod = 0;
2299                         txr->tx_cons = 0;
2300                 }
2301                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2302                         bnxt_free_cp_ring(bp, cpr);
2303                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2304                         if (txq->nq_ring)
2305                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2306                 }
2307         }
2308
2309         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2310                 bnxt_free_hwrm_rx_ring(bp, i);
2311
2312         return 0;
2313 }
2314
2315 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2316 {
2317         uint16_t i;
2318         uint32_t rc = 0;
2319
2320         if (!BNXT_HAS_RING_GRPS(bp))
2321                 return 0;
2322
2323         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2324                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2325                 if (rc)
2326                         return rc;
2327         }
2328         return rc;
2329 }
2330
2331 void bnxt_free_hwrm_resources(struct bnxt *bp)
2332 {
2333         /* Release memzone */
2334         rte_free(bp->hwrm_cmd_resp_addr);
2335         rte_free(bp->hwrm_short_cmd_req_addr);
2336         bp->hwrm_cmd_resp_addr = NULL;
2337         bp->hwrm_short_cmd_req_addr = NULL;
2338         bp->hwrm_cmd_resp_dma_addr = 0;
2339         bp->hwrm_short_cmd_req_dma_addr = 0;
2340 }
2341
2342 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2343 {
2344         struct rte_pci_device *pdev = bp->pdev;
2345         char type[RTE_MEMZONE_NAMESIZE];
2346
2347         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2348                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2349         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2350         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2351         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2352         if (bp->hwrm_cmd_resp_addr == NULL)
2353                 return -ENOMEM;
2354         bp->hwrm_cmd_resp_dma_addr =
2355                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2356         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2357                 PMD_DRV_LOG(ERR,
2358                         "unable to map response address to physical memory\n");
2359                 return -ENOMEM;
2360         }
2361         rte_spinlock_init(&bp->hwrm_lock);
2362
2363         return 0;
2364 }
2365
2366 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2367 {
2368         struct bnxt_filter_info *filter;
2369         int rc = 0;
2370
2371         STAILQ_FOREACH(filter, &vnic->filter, next) {
2372                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2373                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2374                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2375                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2376                 else
2377                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2378                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2379                 bnxt_free_filter(bp, filter);
2380                 //if (rc)
2381                         //break;
2382         }
2383         return rc;
2384 }
2385
2386 static int
2387 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2388 {
2389         struct bnxt_filter_info *filter;
2390         struct rte_flow *flow;
2391         int rc = 0;
2392
2393         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2394                 flow = STAILQ_FIRST(&vnic->flow_list);
2395                 filter = flow->filter;
2396                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2397                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2398                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2399                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2400                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2401                 else
2402                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2403
2404                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2405                 rte_free(flow);
2406                 //if (rc)
2407                         //break;
2408         }
2409         return rc;
2410 }
2411
2412 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2413 {
2414         struct bnxt_filter_info *filter;
2415         int rc = 0;
2416
2417         STAILQ_FOREACH(filter, &vnic->filter, next) {
2418                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2419                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2420                                                      filter);
2421                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2422                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2423                                                          filter);
2424                 else
2425                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2426                                                      filter);
2427                 if (rc)
2428                         break;
2429         }
2430         return rc;
2431 }
2432
2433 void bnxt_free_tunnel_ports(struct bnxt *bp)
2434 {
2435         if (bp->vxlan_port_cnt)
2436                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2437                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2438         bp->vxlan_port = 0;
2439         if (bp->geneve_port_cnt)
2440                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2441                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2442         bp->geneve_port = 0;
2443 }
2444
2445 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2446 {
2447         int i;
2448
2449         if (bp->vnic_info == NULL)
2450                 return;
2451
2452         /*
2453          * Cleanup VNICs in reverse order, to make sure the L2 filter
2454          * from vnic0 is last to be cleaned up.
2455          */
2456         for (i = bp->max_vnics - 1; i >= 0; i--) {
2457                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2458
2459                 // If the VNIC ID is invalid we are not currently using the VNIC
2460                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2461                         continue;
2462
2463                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2464
2465                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2466
2467                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2468
2469                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2470
2471                 bnxt_hwrm_vnic_free(bp, vnic);
2472
2473                 rte_free(vnic->fw_grp_ids);
2474         }
2475         /* Ring resources */
2476         bnxt_free_all_hwrm_rings(bp);
2477         bnxt_free_all_hwrm_ring_grps(bp);
2478         bnxt_free_all_hwrm_stat_ctxs(bp);
2479         bnxt_free_tunnel_ports(bp);
2480 }
2481
2482 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2483 {
2484         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2485
2486         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2487                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2488
2489         switch (conf_link_speed) {
2490         case ETH_LINK_SPEED_10M_HD:
2491         case ETH_LINK_SPEED_100M_HD:
2492                 /* FALLTHROUGH */
2493                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2494         }
2495         return hw_link_duplex;
2496 }
2497
2498 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2499 {
2500         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2501 }
2502
2503 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2504 {
2505         uint16_t eth_link_speed = 0;
2506
2507         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2508                 return ETH_LINK_SPEED_AUTONEG;
2509
2510         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2511         case ETH_LINK_SPEED_100M:
2512         case ETH_LINK_SPEED_100M_HD:
2513                 /* FALLTHROUGH */
2514                 eth_link_speed =
2515                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2516                 break;
2517         case ETH_LINK_SPEED_1G:
2518                 eth_link_speed =
2519                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2520                 break;
2521         case ETH_LINK_SPEED_2_5G:
2522                 eth_link_speed =
2523                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2524                 break;
2525         case ETH_LINK_SPEED_10G:
2526                 eth_link_speed =
2527                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2528                 break;
2529         case ETH_LINK_SPEED_20G:
2530                 eth_link_speed =
2531                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2532                 break;
2533         case ETH_LINK_SPEED_25G:
2534                 eth_link_speed =
2535                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2536                 break;
2537         case ETH_LINK_SPEED_40G:
2538                 eth_link_speed =
2539                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2540                 break;
2541         case ETH_LINK_SPEED_50G:
2542                 eth_link_speed =
2543                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2544                 break;
2545         case ETH_LINK_SPEED_100G:
2546                 eth_link_speed =
2547                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2548                 break;
2549         default:
2550                 PMD_DRV_LOG(ERR,
2551                         "Unsupported link speed %d; default to AUTO\n",
2552                         conf_link_speed);
2553                 break;
2554         }
2555         return eth_link_speed;
2556 }
2557
2558 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2559                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2560                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2561                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2562
2563 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2564 {
2565         uint32_t one_speed;
2566
2567         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2568                 return 0;
2569
2570         if (link_speed & ETH_LINK_SPEED_FIXED) {
2571                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2572
2573                 if (one_speed & (one_speed - 1)) {
2574                         PMD_DRV_LOG(ERR,
2575                                 "Invalid advertised speeds (%u) for port %u\n",
2576                                 link_speed, port_id);
2577                         return -EINVAL;
2578                 }
2579                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2580                         PMD_DRV_LOG(ERR,
2581                                 "Unsupported advertised speed (%u) for port %u\n",
2582                                 link_speed, port_id);
2583                         return -EINVAL;
2584                 }
2585         } else {
2586                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2587                         PMD_DRV_LOG(ERR,
2588                                 "Unsupported advertised speeds (%u) for port %u\n",
2589                                 link_speed, port_id);
2590                         return -EINVAL;
2591                 }
2592         }
2593         return 0;
2594 }
2595
2596 static uint16_t
2597 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2598 {
2599         uint16_t ret = 0;
2600
2601         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2602                 if (bp->link_info.support_speeds)
2603                         return bp->link_info.support_speeds;
2604                 link_speed = BNXT_SUPPORTED_SPEEDS;
2605         }
2606
2607         if (link_speed & ETH_LINK_SPEED_100M)
2608                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2609         if (link_speed & ETH_LINK_SPEED_100M_HD)
2610                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2611         if (link_speed & ETH_LINK_SPEED_1G)
2612                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2613         if (link_speed & ETH_LINK_SPEED_2_5G)
2614                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2615         if (link_speed & ETH_LINK_SPEED_10G)
2616                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2617         if (link_speed & ETH_LINK_SPEED_20G)
2618                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2619         if (link_speed & ETH_LINK_SPEED_25G)
2620                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2621         if (link_speed & ETH_LINK_SPEED_40G)
2622                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2623         if (link_speed & ETH_LINK_SPEED_50G)
2624                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2625         if (link_speed & ETH_LINK_SPEED_100G)
2626                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2627         return ret;
2628 }
2629
2630 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2631 {
2632         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2633
2634         switch (hw_link_speed) {
2635         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2636                 eth_link_speed = ETH_SPEED_NUM_100M;
2637                 break;
2638         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2639                 eth_link_speed = ETH_SPEED_NUM_1G;
2640                 break;
2641         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2642                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2643                 break;
2644         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2645                 eth_link_speed = ETH_SPEED_NUM_10G;
2646                 break;
2647         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2648                 eth_link_speed = ETH_SPEED_NUM_20G;
2649                 break;
2650         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2651                 eth_link_speed = ETH_SPEED_NUM_25G;
2652                 break;
2653         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2654                 eth_link_speed = ETH_SPEED_NUM_40G;
2655                 break;
2656         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2657                 eth_link_speed = ETH_SPEED_NUM_50G;
2658                 break;
2659         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2660                 eth_link_speed = ETH_SPEED_NUM_100G;
2661                 break;
2662         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2663         default:
2664                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2665                         hw_link_speed);
2666                 break;
2667         }
2668         return eth_link_speed;
2669 }
2670
2671 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2672 {
2673         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2674
2675         switch (hw_link_duplex) {
2676         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2677         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2678                 /* FALLTHROUGH */
2679                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2680                 break;
2681         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2682                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2683                 break;
2684         default:
2685                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2686                         hw_link_duplex);
2687                 break;
2688         }
2689         return eth_link_duplex;
2690 }
2691
2692 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2693 {
2694         int rc = 0;
2695         struct bnxt_link_info *link_info = &bp->link_info;
2696
2697         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2698         if (rc) {
2699                 PMD_DRV_LOG(ERR,
2700                         "Get link config failed with rc %d\n", rc);
2701                 goto exit;
2702         }
2703         if (link_info->link_speed)
2704                 link->link_speed =
2705                         bnxt_parse_hw_link_speed(link_info->link_speed);
2706         else
2707                 link->link_speed = ETH_SPEED_NUM_NONE;
2708         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2709         link->link_status = link_info->link_up;
2710         link->link_autoneg = link_info->auto_mode ==
2711                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2712                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2713 exit:
2714         return rc;
2715 }
2716
2717 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2718 {
2719         int rc = 0;
2720         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2721         struct bnxt_link_info link_req;
2722         uint16_t speed, autoneg;
2723
2724         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2725                 return 0;
2726
2727         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2728                         bp->eth_dev->data->port_id);
2729         if (rc)
2730                 goto error;
2731
2732         memset(&link_req, 0, sizeof(link_req));
2733         link_req.link_up = link_up;
2734         if (!link_up)
2735                 goto port_phy_cfg;
2736
2737         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2738         if (BNXT_CHIP_THOR(bp) &&
2739             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2740                 /* 40G is not supported as part of media auto detect.
2741                  * The speed should be forced and autoneg disabled
2742                  * to configure 40G speed.
2743                  */
2744                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2745                 autoneg = 0;
2746         }
2747
2748         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2749         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2750         /* Autoneg can be done only when the FW allows.
2751          * When user configures fixed speed of 40G and later changes to
2752          * any other speed, auto_link_speed/force_link_speed is still set
2753          * to 40G until link comes up at new speed.
2754          */
2755         if (autoneg == 1 &&
2756             !(!BNXT_CHIP_THOR(bp) &&
2757               (bp->link_info.auto_link_speed ||
2758                bp->link_info.force_link_speed))) {
2759                 link_req.phy_flags |=
2760                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2761                 link_req.auto_link_speed_mask =
2762                         bnxt_parse_eth_link_speed_mask(bp,
2763                                                        dev_conf->link_speeds);
2764         } else {
2765                 if (bp->link_info.phy_type ==
2766                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2767                     bp->link_info.phy_type ==
2768                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2769                     bp->link_info.media_type ==
2770                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2771                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2772                         return -EINVAL;
2773                 }
2774
2775                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2776                 /* If user wants a particular speed try that first. */
2777                 if (speed)
2778                         link_req.link_speed = speed;
2779                 else if (bp->link_info.force_link_speed)
2780                         link_req.link_speed = bp->link_info.force_link_speed;
2781                 else
2782                         link_req.link_speed = bp->link_info.auto_link_speed;
2783         }
2784         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2785         link_req.auto_pause = bp->link_info.auto_pause;
2786         link_req.force_pause = bp->link_info.force_pause;
2787
2788 port_phy_cfg:
2789         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2790         if (rc) {
2791                 PMD_DRV_LOG(ERR,
2792                         "Set link config failed with rc %d\n", rc);
2793         }
2794
2795 error:
2796         return rc;
2797 }
2798
2799 /* JIRA 22088 */
2800 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2801 {
2802         struct hwrm_func_qcfg_input req = {0};
2803         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2804         uint16_t flags;
2805         int rc = 0;
2806
2807         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2808         req.fid = rte_cpu_to_le_16(0xffff);
2809
2810         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2811
2812         HWRM_CHECK_RESULT();
2813
2814         /* Hard Coded.. 0xfff VLAN ID mask */
2815         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2816         flags = rte_le_to_cpu_16(resp->flags);
2817         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2818                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2819
2820         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2821                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2822                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2823         } else if (BNXT_VF(bp) &&
2824                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2825                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2826                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2827         }
2828
2829         if (mtu)
2830                 *mtu = resp->mtu;
2831
2832         switch (resp->port_partition_type) {
2833         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2834         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2835         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2836                 /* FALLTHROUGH */
2837                 bp->port_partition_type = resp->port_partition_type;
2838                 break;
2839         default:
2840                 bp->port_partition_type = 0;
2841                 break;
2842         }
2843
2844         HWRM_UNLOCK();
2845
2846         return rc;
2847 }
2848
2849 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2850                                    struct hwrm_func_qcaps_output *qcaps)
2851 {
2852         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2853         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2854                sizeof(qcaps->mac_address));
2855         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2856         qcaps->max_rx_rings = fcfg->num_rx_rings;
2857         qcaps->max_tx_rings = fcfg->num_tx_rings;
2858         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2859         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2860         qcaps->max_vfs = 0;
2861         qcaps->first_vf_id = 0;
2862         qcaps->max_vnics = fcfg->num_vnics;
2863         qcaps->max_decap_records = 0;
2864         qcaps->max_encap_records = 0;
2865         qcaps->max_tx_wm_flows = 0;
2866         qcaps->max_tx_em_flows = 0;
2867         qcaps->max_rx_wm_flows = 0;
2868         qcaps->max_rx_em_flows = 0;
2869         qcaps->max_flow_id = 0;
2870         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2871         qcaps->max_sp_tx_rings = 0;
2872         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2873 }
2874
2875 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2876 {
2877         struct hwrm_func_cfg_input req = {0};
2878         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2879         uint32_t enables;
2880         int rc;
2881
2882         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2883                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2884                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2885                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2886                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2887                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2888                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2889                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2890                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2891
2892         if (BNXT_HAS_RING_GRPS(bp)) {
2893                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2894                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2895         } else if (BNXT_HAS_NQ(bp)) {
2896                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2897                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2898         }
2899
2900         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2901         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2902         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2903                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2904                                    BNXT_NUM_VLANS);
2905         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2906         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2907         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2908         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2909         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2910         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2911         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2912         req.fid = rte_cpu_to_le_16(0xffff);
2913         req.enables = rte_cpu_to_le_32(enables);
2914
2915         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2916
2917         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2918
2919         HWRM_CHECK_RESULT();
2920         HWRM_UNLOCK();
2921
2922         return rc;
2923 }
2924
2925 static void populate_vf_func_cfg_req(struct bnxt *bp,
2926                                      struct hwrm_func_cfg_input *req,
2927                                      int num_vfs)
2928 {
2929         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2930                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2931                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2932                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2933                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2934                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2935                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2936                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2937                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2938                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2939
2940         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2941                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2942                                     BNXT_NUM_VLANS);
2943         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2944                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2945                                     BNXT_NUM_VLANS);
2946         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2947                                                 (num_vfs + 1));
2948         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2949         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2950                                                (num_vfs + 1));
2951         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2952         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2953         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2954         /* TODO: For now, do not support VMDq/RFS on VFs. */
2955         req->num_vnics = rte_cpu_to_le_16(1);
2956         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2957                                                  (num_vfs + 1));
2958 }
2959
2960 static void add_random_mac_if_needed(struct bnxt *bp,
2961                                      struct hwrm_func_cfg_input *cfg_req,
2962                                      int vf)
2963 {
2964         struct rte_ether_addr mac;
2965
2966         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2967                 return;
2968
2969         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2970                 cfg_req->enables |=
2971                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2972                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2973                 bp->pf.vf_info[vf].random_mac = true;
2974         } else {
2975                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2976                         RTE_ETHER_ADDR_LEN);
2977         }
2978 }
2979
2980 static void reserve_resources_from_vf(struct bnxt *bp,
2981                                       struct hwrm_func_cfg_input *cfg_req,
2982                                       int vf)
2983 {
2984         struct hwrm_func_qcaps_input req = {0};
2985         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2986         int rc;
2987
2988         /* Get the actual allocated values now */
2989         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2990         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2992
2993         if (rc) {
2994                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2995                 copy_func_cfg_to_qcaps(cfg_req, resp);
2996         } else if (resp->error_code) {
2997                 rc = rte_le_to_cpu_16(resp->error_code);
2998                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2999                 copy_func_cfg_to_qcaps(cfg_req, resp);
3000         }
3001
3002         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3003         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3004         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3005         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3006         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3007         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3008         /*
3009          * TODO: While not supporting VMDq with VFs, max_vnics is always
3010          * forced to 1 in this case
3011          */
3012         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3013         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3014
3015         HWRM_UNLOCK();
3016 }
3017
3018 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3019 {
3020         struct hwrm_func_qcfg_input req = {0};
3021         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3022         int rc;
3023
3024         /* Check for zero MAC address */
3025         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3026         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3027         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3028         HWRM_CHECK_RESULT();
3029         rc = rte_le_to_cpu_16(resp->vlan);
3030
3031         HWRM_UNLOCK();
3032
3033         return rc;
3034 }
3035
3036 static int update_pf_resource_max(struct bnxt *bp)
3037 {
3038         struct hwrm_func_qcfg_input req = {0};
3039         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3040         int rc;
3041
3042         /* And copy the allocated numbers into the pf struct */
3043         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3044         req.fid = rte_cpu_to_le_16(0xffff);
3045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3046         HWRM_CHECK_RESULT();
3047
3048         /* Only TX ring value reflects actual allocation? TODO */
3049         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3050         bp->pf.evb_mode = resp->evb_mode;
3051
3052         HWRM_UNLOCK();
3053
3054         return rc;
3055 }
3056
3057 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3058 {
3059         int rc;
3060
3061         if (!BNXT_PF(bp)) {
3062                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3063                 return -EINVAL;
3064         }
3065
3066         rc = bnxt_hwrm_func_qcaps(bp);
3067         if (rc)
3068                 return rc;
3069
3070         bp->pf.func_cfg_flags &=
3071                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3072                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3073         bp->pf.func_cfg_flags |=
3074                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3075         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3076         rc = __bnxt_hwrm_func_qcaps(bp);
3077         return rc;
3078 }
3079
3080 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3081 {
3082         struct hwrm_func_cfg_input req = {0};
3083         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3084         int i;
3085         size_t sz;
3086         int rc = 0;
3087         size_t req_buf_sz;
3088
3089         if (!BNXT_PF(bp)) {
3090                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3091                 return -EINVAL;
3092         }
3093
3094         rc = bnxt_hwrm_func_qcaps(bp);
3095
3096         if (rc)
3097                 return rc;
3098
3099         bp->pf.active_vfs = num_vfs;
3100
3101         /*
3102          * First, configure the PF to only use one TX ring.  This ensures that
3103          * there are enough rings for all VFs.
3104          *
3105          * If we don't do this, when we call func_alloc() later, we will lock
3106          * extra rings to the PF that won't be available during func_cfg() of
3107          * the VFs.
3108          *
3109          * This has been fixed with firmware versions above 20.6.54
3110          */
3111         bp->pf.func_cfg_flags &=
3112                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3113                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3114         bp->pf.func_cfg_flags |=
3115                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3116         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3117         if (rc)
3118                 return rc;
3119
3120         /*
3121          * Now, create and register a buffer to hold forwarded VF requests
3122          */
3123         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3124         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3125                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3126         if (bp->pf.vf_req_buf == NULL) {
3127                 rc = -ENOMEM;
3128                 goto error_free;
3129         }
3130         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3131                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3132         for (i = 0; i < num_vfs; i++)
3133                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3134                                         (i * HWRM_MAX_REQ_LEN);
3135
3136         rc = bnxt_hwrm_func_buf_rgtr(bp);
3137         if (rc)
3138                 goto error_free;
3139
3140         populate_vf_func_cfg_req(bp, &req, num_vfs);
3141
3142         bp->pf.active_vfs = 0;
3143         for (i = 0; i < num_vfs; i++) {
3144                 add_random_mac_if_needed(bp, &req, i);
3145
3146                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3147                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3148                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3149                 rc = bnxt_hwrm_send_message(bp,
3150                                             &req,
3151                                             sizeof(req),
3152                                             BNXT_USE_CHIMP_MB);
3153
3154                 /* Clear enable flag for next pass */
3155                 req.enables &= ~rte_cpu_to_le_32(
3156                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3157
3158                 if (rc || resp->error_code) {
3159                         PMD_DRV_LOG(ERR,
3160                                 "Failed to initizlie VF %d\n", i);
3161                         PMD_DRV_LOG(ERR,
3162                                 "Not all VFs available. (%d, %d)\n",
3163                                 rc, resp->error_code);
3164                         HWRM_UNLOCK();
3165                         break;
3166                 }
3167
3168                 HWRM_UNLOCK();
3169
3170                 reserve_resources_from_vf(bp, &req, i);
3171                 bp->pf.active_vfs++;
3172                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3173         }
3174
3175         /*
3176          * Now configure the PF to use "the rest" of the resources
3177          * We're using STD_TX_RING_MODE here though which will limit the TX
3178          * rings.  This will allow QoS to function properly.  Not setting this
3179          * will cause PF rings to break bandwidth settings.
3180          */
3181         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3182         if (rc)
3183                 goto error_free;
3184
3185         rc = update_pf_resource_max(bp);
3186         if (rc)
3187                 goto error_free;
3188
3189         return rc;
3190
3191 error_free:
3192         bnxt_hwrm_func_buf_unrgtr(bp);
3193         return rc;
3194 }
3195
3196 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3197 {
3198         struct hwrm_func_cfg_input req = {0};
3199         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3200         int rc;
3201
3202         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3203
3204         req.fid = rte_cpu_to_le_16(0xffff);
3205         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3206         req.evb_mode = bp->pf.evb_mode;
3207
3208         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3209         HWRM_CHECK_RESULT();
3210         HWRM_UNLOCK();
3211
3212         return rc;
3213 }
3214
3215 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3216                                 uint8_t tunnel_type)
3217 {
3218         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3219         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3220         int rc = 0;
3221
3222         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3223         req.tunnel_type = tunnel_type;
3224         req.tunnel_dst_port_val = port;
3225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3226         HWRM_CHECK_RESULT();
3227
3228         switch (tunnel_type) {
3229         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3230                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3231                 bp->vxlan_port = port;
3232                 break;
3233         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3234                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3235                 bp->geneve_port = port;
3236                 break;
3237         default:
3238                 break;
3239         }
3240
3241         HWRM_UNLOCK();
3242
3243         return rc;
3244 }
3245
3246 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3247                                 uint8_t tunnel_type)
3248 {
3249         struct hwrm_tunnel_dst_port_free_input req = {0};
3250         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3251         int rc = 0;
3252
3253         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3254
3255         req.tunnel_type = tunnel_type;
3256         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3257         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3258
3259         HWRM_CHECK_RESULT();
3260         HWRM_UNLOCK();
3261
3262         return rc;
3263 }
3264
3265 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3266                                         uint32_t flags)
3267 {
3268         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3269         struct hwrm_func_cfg_input req = {0};
3270         int rc;
3271
3272         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3273
3274         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3275         req.flags = rte_cpu_to_le_32(flags);
3276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3277
3278         HWRM_CHECK_RESULT();
3279         HWRM_UNLOCK();
3280
3281         return rc;
3282 }
3283
3284 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3285 {
3286         uint32_t *flag = flagp;
3287
3288         vnic->flags = *flag;
3289 }
3290
3291 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3292 {
3293         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3294 }
3295
3296 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3297 {
3298         int rc = 0;
3299         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3300         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3301
3302         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3303
3304         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3305         req.req_buf_page_size = rte_cpu_to_le_16(
3306                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3307         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3308         req.req_buf_page_addr0 =
3309                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3310         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3311                 PMD_DRV_LOG(ERR,
3312                         "unable to map buffer address to physical memory\n");
3313                 return -ENOMEM;
3314         }
3315
3316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317
3318         HWRM_CHECK_RESULT();
3319         HWRM_UNLOCK();
3320
3321         return rc;
3322 }
3323
3324 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3325 {
3326         int rc = 0;
3327         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3328         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3329
3330         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3331                 return 0;
3332
3333         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3334
3335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336
3337         HWRM_CHECK_RESULT();
3338         HWRM_UNLOCK();
3339
3340         return rc;
3341 }
3342
3343 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3344 {
3345         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3346         struct hwrm_func_cfg_input req = {0};
3347         int rc;
3348
3349         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3350
3351         req.fid = rte_cpu_to_le_16(0xffff);
3352         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3353         req.enables = rte_cpu_to_le_32(
3354                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3355         req.async_event_cr = rte_cpu_to_le_16(
3356                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3358
3359         HWRM_CHECK_RESULT();
3360         HWRM_UNLOCK();
3361
3362         return rc;
3363 }
3364
3365 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3366 {
3367         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3368         struct hwrm_func_vf_cfg_input req = {0};
3369         int rc;
3370
3371         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3372
3373         req.enables = rte_cpu_to_le_32(
3374                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3375         req.async_event_cr = rte_cpu_to_le_16(
3376                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3378
3379         HWRM_CHECK_RESULT();
3380         HWRM_UNLOCK();
3381
3382         return rc;
3383 }
3384
3385 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3386 {
3387         struct hwrm_func_cfg_input req = {0};
3388         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3389         uint16_t dflt_vlan, fid;
3390         uint32_t func_cfg_flags;
3391         int rc = 0;
3392
3393         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3394
3395         if (is_vf) {
3396                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3397                 fid = bp->pf.vf_info[vf].fid;
3398                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3399         } else {
3400                 fid = rte_cpu_to_le_16(0xffff);
3401                 func_cfg_flags = bp->pf.func_cfg_flags;
3402                 dflt_vlan = bp->vlan;
3403         }
3404
3405         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3406         req.fid = rte_cpu_to_le_16(fid);
3407         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3408         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3409
3410         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3411
3412         HWRM_CHECK_RESULT();
3413         HWRM_UNLOCK();
3414
3415         return rc;
3416 }
3417
3418 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3419                         uint16_t max_bw, uint16_t enables)
3420 {
3421         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3422         struct hwrm_func_cfg_input req = {0};
3423         int rc;
3424
3425         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3426
3427         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3428         req.enables |= rte_cpu_to_le_32(enables);
3429         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3430         req.max_bw = rte_cpu_to_le_32(max_bw);
3431         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3432
3433         HWRM_CHECK_RESULT();
3434         HWRM_UNLOCK();
3435
3436         return rc;
3437 }
3438
3439 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3440 {
3441         struct hwrm_func_cfg_input req = {0};
3442         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3443         int rc = 0;
3444
3445         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3446
3447         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3448         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3449         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3450         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3451
3452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3453
3454         HWRM_CHECK_RESULT();
3455         HWRM_UNLOCK();
3456
3457         return rc;
3458 }
3459
3460 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3461 {
3462         int rc;
3463
3464         if (BNXT_PF(bp))
3465                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3466         else
3467                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3468
3469         return rc;
3470 }
3471
3472 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3473                               void *encaped, size_t ec_size)
3474 {
3475         int rc = 0;
3476         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3477         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3478
3479         if (ec_size > sizeof(req.encap_request))
3480                 return -1;
3481
3482         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3483
3484         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3485         memcpy(req.encap_request, encaped, ec_size);
3486
3487         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3488
3489         HWRM_CHECK_RESULT();
3490         HWRM_UNLOCK();
3491
3492         return rc;
3493 }
3494
3495 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3496                                        struct rte_ether_addr *mac)
3497 {
3498         struct hwrm_func_qcfg_input req = {0};
3499         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3500         int rc;
3501
3502         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3503
3504         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3506
3507         HWRM_CHECK_RESULT();
3508
3509         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3510
3511         HWRM_UNLOCK();
3512
3513         return rc;
3514 }
3515
3516 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3517                             void *encaped, size_t ec_size)
3518 {
3519         int rc = 0;
3520         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3521         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3522
3523         if (ec_size > sizeof(req.encap_request))
3524                 return -1;
3525
3526         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3527
3528         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3529         memcpy(req.encap_request, encaped, ec_size);
3530
3531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3532
3533         HWRM_CHECK_RESULT();
3534         HWRM_UNLOCK();
3535
3536         return rc;
3537 }
3538
3539 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3540                          struct rte_eth_stats *stats, uint8_t rx)
3541 {
3542         int rc = 0;
3543         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3544         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3545
3546         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3547
3548         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3549
3550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3551
3552         HWRM_CHECK_RESULT();
3553
3554         if (rx) {
3555                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3556                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3557                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3558                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3559                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3560                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3561                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3562                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3563         } else {
3564                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3565                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3566                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3567                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3568                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3569                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3570         }
3571
3572
3573         HWRM_UNLOCK();
3574
3575         return rc;
3576 }
3577
3578 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3579 {
3580         struct hwrm_port_qstats_input req = {0};
3581         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3582         struct bnxt_pf_info *pf = &bp->pf;
3583         int rc;
3584
3585         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3586
3587         req.port_id = rte_cpu_to_le_16(pf->port_id);
3588         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3589         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3591
3592         HWRM_CHECK_RESULT();
3593         HWRM_UNLOCK();
3594
3595         return rc;
3596 }
3597
3598 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3599 {
3600         struct hwrm_port_clr_stats_input req = {0};
3601         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3602         struct bnxt_pf_info *pf = &bp->pf;
3603         int rc;
3604
3605         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3606         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3607             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3608                 return 0;
3609
3610         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3611
3612         req.port_id = rte_cpu_to_le_16(pf->port_id);
3613         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3614
3615         HWRM_CHECK_RESULT();
3616         HWRM_UNLOCK();
3617
3618         return rc;
3619 }
3620
3621 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3622 {
3623         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3624         struct hwrm_port_led_qcaps_input req = {0};
3625         int rc;
3626
3627         if (BNXT_VF(bp))
3628                 return 0;
3629
3630         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3631         req.port_id = bp->pf.port_id;
3632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3633
3634         HWRM_CHECK_RESULT();
3635
3636         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3637                 unsigned int i;
3638
3639                 bp->num_leds = resp->num_leds;
3640                 memcpy(bp->leds, &resp->led0_id,
3641                         sizeof(bp->leds[0]) * bp->num_leds);
3642                 for (i = 0; i < bp->num_leds; i++) {
3643                         struct bnxt_led_info *led = &bp->leds[i];
3644
3645                         uint16_t caps = led->led_state_caps;
3646
3647                         if (!led->led_group_id ||
3648                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3649                                 bp->num_leds = 0;
3650                                 break;
3651                         }
3652                 }
3653         }
3654
3655         HWRM_UNLOCK();
3656
3657         return rc;
3658 }
3659
3660 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3661 {
3662         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3663         struct hwrm_port_led_cfg_input req = {0};
3664         struct bnxt_led_cfg *led_cfg;
3665         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3666         uint16_t duration = 0;
3667         int rc, i;
3668
3669         if (!bp->num_leds || BNXT_VF(bp))
3670                 return -EOPNOTSUPP;
3671
3672         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3673
3674         if (led_on) {
3675                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3676                 duration = rte_cpu_to_le_16(500);
3677         }
3678         req.port_id = bp->pf.port_id;
3679         req.num_leds = bp->num_leds;
3680         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3681         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3682                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3683                 led_cfg->led_id = bp->leds[i].led_id;
3684                 led_cfg->led_state = led_state;
3685                 led_cfg->led_blink_on = duration;
3686                 led_cfg->led_blink_off = duration;
3687                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3688         }
3689
3690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3691
3692         HWRM_CHECK_RESULT();
3693         HWRM_UNLOCK();
3694
3695         return rc;
3696 }
3697
3698 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3699                                uint32_t *length)
3700 {
3701         int rc;
3702         struct hwrm_nvm_get_dir_info_input req = {0};
3703         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3704
3705         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3706
3707         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3708
3709         HWRM_CHECK_RESULT();
3710
3711         *entries = rte_le_to_cpu_32(resp->entries);
3712         *length = rte_le_to_cpu_32(resp->entry_length);
3713
3714         HWRM_UNLOCK();
3715         return rc;
3716 }
3717
3718 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3719 {
3720         int rc;
3721         uint32_t dir_entries;
3722         uint32_t entry_length;
3723         uint8_t *buf;
3724         size_t buflen;
3725         rte_iova_t dma_handle;
3726         struct hwrm_nvm_get_dir_entries_input req = {0};
3727         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3728
3729         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3730         if (rc != 0)
3731                 return rc;
3732
3733         *data++ = dir_entries;
3734         *data++ = entry_length;
3735         len -= 2;
3736         memset(data, 0xff, len);
3737
3738         buflen = dir_entries * entry_length;
3739         buf = rte_malloc("nvm_dir", buflen, 0);
3740         rte_mem_lock_page(buf);
3741         if (buf == NULL)
3742                 return -ENOMEM;
3743         dma_handle = rte_mem_virt2iova(buf);
3744         if (dma_handle == RTE_BAD_IOVA) {
3745                 PMD_DRV_LOG(ERR,
3746                         "unable to map response address to physical memory\n");
3747                 return -ENOMEM;
3748         }
3749         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3750         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3751         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3752
3753         if (rc == 0)
3754                 memcpy(data, buf, len > buflen ? buflen : len);
3755
3756         rte_free(buf);
3757         HWRM_CHECK_RESULT();
3758         HWRM_UNLOCK();
3759
3760         return rc;
3761 }
3762
3763 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3764                              uint32_t offset, uint32_t length,
3765                              uint8_t *data)
3766 {
3767         int rc;
3768         uint8_t *buf;
3769         rte_iova_t dma_handle;
3770         struct hwrm_nvm_read_input req = {0};
3771         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3772
3773         buf = rte_malloc("nvm_item", length, 0);
3774         rte_mem_lock_page(buf);
3775         if (!buf)
3776                 return -ENOMEM;
3777
3778         dma_handle = rte_mem_virt2iova(buf);
3779         if (dma_handle == RTE_BAD_IOVA) {
3780                 PMD_DRV_LOG(ERR,
3781                         "unable to map response address to physical memory\n");
3782                 return -ENOMEM;
3783         }
3784         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3785         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3786         req.dir_idx = rte_cpu_to_le_16(index);
3787         req.offset = rte_cpu_to_le_32(offset);
3788         req.len = rte_cpu_to_le_32(length);
3789         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3790         if (rc == 0)
3791                 memcpy(data, buf, length);
3792
3793         rte_free(buf);
3794         HWRM_CHECK_RESULT();
3795         HWRM_UNLOCK();
3796
3797         return rc;
3798 }
3799
3800 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3801 {
3802         int rc;
3803         struct hwrm_nvm_erase_dir_entry_input req = {0};
3804         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3805
3806         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3807         req.dir_idx = rte_cpu_to_le_16(index);
3808         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3809         HWRM_CHECK_RESULT();
3810         HWRM_UNLOCK();
3811
3812         return rc;
3813 }
3814
3815
3816 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3817                           uint16_t dir_ordinal, uint16_t dir_ext,
3818                           uint16_t dir_attr, const uint8_t *data,
3819                           size_t data_len)
3820 {
3821         int rc;
3822         struct hwrm_nvm_write_input req = {0};
3823         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3824         rte_iova_t dma_handle;
3825         uint8_t *buf;
3826
3827         buf = rte_malloc("nvm_write", data_len, 0);
3828         rte_mem_lock_page(buf);
3829         if (!buf)
3830                 return -ENOMEM;
3831
3832         dma_handle = rte_mem_virt2iova(buf);
3833         if (dma_handle == RTE_BAD_IOVA) {
3834                 PMD_DRV_LOG(ERR,
3835                         "unable to map response address to physical memory\n");
3836                 return -ENOMEM;
3837         }
3838         memcpy(buf, data, data_len);
3839
3840         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3841
3842         req.dir_type = rte_cpu_to_le_16(dir_type);
3843         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3844         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3845         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3846         req.dir_data_length = rte_cpu_to_le_32(data_len);
3847         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3848
3849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3850
3851         rte_free(buf);
3852         HWRM_CHECK_RESULT();
3853         HWRM_UNLOCK();
3854
3855         return rc;
3856 }
3857
3858 static void
3859 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3860 {
3861         uint32_t *count = cbdata;
3862
3863         *count = *count + 1;
3864 }
3865
3866 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3867                                      struct bnxt_vnic_info *vnic __rte_unused)
3868 {
3869         return 0;
3870 }
3871
3872 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3873 {
3874         uint32_t count = 0;
3875
3876         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3877             &count, bnxt_vnic_count_hwrm_stub);
3878
3879         return count;
3880 }
3881
3882 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3883                                         uint16_t *vnic_ids)
3884 {
3885         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3886         struct hwrm_func_vf_vnic_ids_query_output *resp =
3887                                                 bp->hwrm_cmd_resp_addr;
3888         int rc;
3889
3890         /* First query all VNIC ids */
3891         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3892
3893         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3894         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3895         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3896
3897         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3898                 HWRM_UNLOCK();
3899                 PMD_DRV_LOG(ERR,
3900                 "unable to map VNIC ID table address to physical memory\n");
3901                 return -ENOMEM;
3902         }
3903         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3904         HWRM_CHECK_RESULT();
3905         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3906
3907         HWRM_UNLOCK();
3908
3909         return rc;
3910 }
3911
3912 /*
3913  * This function queries the VNIC IDs  for a specified VF. It then calls
3914  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3915  * Then it calls the hwrm_cb function to program this new vnic configuration.
3916  */
3917 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3918         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3919         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3920 {
3921         struct bnxt_vnic_info vnic;
3922         int rc = 0;
3923         int i, num_vnic_ids;
3924         uint16_t *vnic_ids;
3925         size_t vnic_id_sz;
3926         size_t sz;
3927
3928         /* First query all VNIC ids */
3929         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3930         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3931                         RTE_CACHE_LINE_SIZE);
3932         if (vnic_ids == NULL)
3933                 return -ENOMEM;
3934
3935         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3936                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3937
3938         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3939
3940         if (num_vnic_ids < 0)
3941                 return num_vnic_ids;
3942
3943         /* Retrieve VNIC, update bd_stall then update */
3944
3945         for (i = 0; i < num_vnic_ids; i++) {
3946                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3947                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3948                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3949                 if (rc)
3950                         break;
3951                 if (vnic.mru <= 4)      /* Indicates unallocated */
3952                         continue;
3953
3954                 vnic_cb(&vnic, cbdata);
3955
3956                 rc = hwrm_cb(bp, &vnic);
3957                 if (rc)
3958                         break;
3959         }
3960
3961         rte_free(vnic_ids);
3962
3963         return rc;
3964 }
3965
3966 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3967                                               bool on)
3968 {
3969         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3970         struct hwrm_func_cfg_input req = {0};
3971         int rc;
3972
3973         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3974
3975         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3976         req.enables |= rte_cpu_to_le_32(
3977                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3978         req.vlan_antispoof_mode = on ?
3979                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3980                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3982
3983         HWRM_CHECK_RESULT();
3984         HWRM_UNLOCK();
3985
3986         return rc;
3987 }
3988
3989 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3990 {
3991         struct bnxt_vnic_info vnic;
3992         uint16_t *vnic_ids;
3993         size_t vnic_id_sz;
3994         int num_vnic_ids, i;
3995         size_t sz;
3996         int rc;
3997
3998         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3999         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4000                         RTE_CACHE_LINE_SIZE);
4001         if (vnic_ids == NULL)
4002                 return -ENOMEM;
4003
4004         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4005                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4006
4007         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4008         if (rc <= 0)
4009                 goto exit;
4010         num_vnic_ids = rc;
4011
4012         /*
4013          * Loop through to find the default VNIC ID.
4014          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4015          * by sending the hwrm_func_qcfg command to the firmware.
4016          */
4017         for (i = 0; i < num_vnic_ids; i++) {
4018                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4019                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4020                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4021                                         bp->pf.first_vf_id + vf);
4022                 if (rc)
4023                         goto exit;
4024                 if (vnic.func_default) {
4025                         rte_free(vnic_ids);
4026                         return vnic.fw_vnic_id;
4027                 }
4028         }
4029         /* Could not find a default VNIC. */
4030         PMD_DRV_LOG(ERR, "No default VNIC\n");
4031 exit:
4032         rte_free(vnic_ids);
4033         return rc;
4034 }
4035
4036 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4037                          uint16_t dst_id,
4038                          struct bnxt_filter_info *filter)
4039 {
4040         int rc = 0;
4041         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4042         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4043         uint32_t enables = 0;
4044
4045         if (filter->fw_em_filter_id != UINT64_MAX)
4046                 bnxt_hwrm_clear_em_filter(bp, filter);
4047
4048         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4049
4050         req.flags = rte_cpu_to_le_32(filter->flags);
4051
4052         enables = filter->enables |
4053               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4054         req.dst_id = rte_cpu_to_le_16(dst_id);
4055
4056         if (filter->ip_addr_type) {
4057                 req.ip_addr_type = filter->ip_addr_type;
4058                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4059         }
4060         if (enables &
4061             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4062                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4063         if (enables &
4064             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4065                 memcpy(req.src_macaddr, filter->src_macaddr,
4066                        RTE_ETHER_ADDR_LEN);
4067         if (enables &
4068             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4069                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4070                        RTE_ETHER_ADDR_LEN);
4071         if (enables &
4072             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4073                 req.ovlan_vid = filter->l2_ovlan;
4074         if (enables &
4075             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4076                 req.ivlan_vid = filter->l2_ivlan;
4077         if (enables &
4078             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4079                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4080         if (enables &
4081             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4082                 req.ip_protocol = filter->ip_protocol;
4083         if (enables &
4084             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4085                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4086         if (enables &
4087             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4088                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4089         if (enables &
4090             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4091                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4092         if (enables &
4093             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4094                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4095         if (enables &
4096             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4097                 req.mirror_vnic_id = filter->mirror_vnic_id;
4098
4099         req.enables = rte_cpu_to_le_32(enables);
4100
4101         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4102
4103         HWRM_CHECK_RESULT();
4104
4105         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4106         HWRM_UNLOCK();
4107
4108         return rc;
4109 }
4110
4111 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4112 {
4113         int rc = 0;
4114         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4115         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4116
4117         if (filter->fw_em_filter_id == UINT64_MAX)
4118                 return 0;
4119
4120         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4121         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4122
4123         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4124
4125         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4126
4127         HWRM_CHECK_RESULT();
4128         HWRM_UNLOCK();
4129
4130         filter->fw_em_filter_id = UINT64_MAX;
4131         filter->fw_l2_filter_id = UINT64_MAX;
4132
4133         return 0;
4134 }
4135
4136 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4137                          uint16_t dst_id,
4138                          struct bnxt_filter_info *filter)
4139 {
4140         int rc = 0;
4141         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4142         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4143                                                 bp->hwrm_cmd_resp_addr;
4144         uint32_t enables = 0;
4145
4146         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4147                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4148
4149         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4150
4151         req.flags = rte_cpu_to_le_32(filter->flags);
4152
4153         enables = filter->enables |
4154               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4155         req.dst_id = rte_cpu_to_le_16(dst_id);
4156
4157
4158         if (filter->ip_addr_type) {
4159                 req.ip_addr_type = filter->ip_addr_type;
4160                 enables |=
4161                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4162         }
4163         if (enables &
4164             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4165                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4166         if (enables &
4167             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4168                 memcpy(req.src_macaddr, filter->src_macaddr,
4169                        RTE_ETHER_ADDR_LEN);
4170         //if (enables &
4171             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4172                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4173                        //RTE_ETHER_ADDR_LEN);
4174         if (enables &
4175             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4176                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4177         if (enables &
4178             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4179                 req.ip_protocol = filter->ip_protocol;
4180         if (enables &
4181             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4182                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4183         if (enables &
4184             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4185                 req.src_ipaddr_mask[0] =
4186                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4187         if (enables &
4188             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4189                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4190         if (enables &
4191             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4192                 req.dst_ipaddr_mask[0] =
4193                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4194         if (enables &
4195             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4196                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4197         if (enables &
4198             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4199                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4200         if (enables &
4201             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4202                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4203         if (enables &
4204             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4205                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4206         if (enables &
4207             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4208                 req.mirror_vnic_id = filter->mirror_vnic_id;
4209
4210         req.enables = rte_cpu_to_le_32(enables);
4211
4212         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4213
4214         HWRM_CHECK_RESULT();
4215
4216         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4217         HWRM_UNLOCK();
4218
4219         return rc;
4220 }
4221
4222 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4223                                 struct bnxt_filter_info *filter)
4224 {
4225         int rc = 0;
4226         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4227         struct hwrm_cfa_ntuple_filter_free_output *resp =
4228                                                 bp->hwrm_cmd_resp_addr;
4229
4230         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4231                 return 0;
4232
4233         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4234
4235         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4236
4237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4238
4239         HWRM_CHECK_RESULT();
4240         HWRM_UNLOCK();
4241
4242         filter->fw_ntuple_filter_id = UINT64_MAX;
4243
4244         return 0;
4245 }
4246
4247 static int
4248 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4249 {
4250         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4251         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4252         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4253         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4254         uint16_t *ring_tbl = vnic->rss_table;
4255         int nr_ctxs = vnic->num_lb_ctxts;
4256         int max_rings = bp->rx_nr_rings;
4257         int i, j, k, cnt;
4258         int rc = 0;
4259
4260         for (i = 0, k = 0; i < nr_ctxs; i++) {
4261                 struct bnxt_rx_ring_info *rxr;
4262                 struct bnxt_cp_ring_info *cpr;
4263
4264                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4265
4266                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4267                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4268                 req.hash_mode_flags = vnic->hash_mode;
4269
4270                 req.ring_grp_tbl_addr =
4271                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4272                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4273                                      2 * sizeof(*ring_tbl));
4274                 req.hash_key_tbl_addr =
4275                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4276
4277                 req.ring_table_pair_index = i;
4278                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4279
4280                 for (j = 0; j < 64; j++) {
4281                         uint16_t ring_id;
4282
4283                         /* Find next active ring. */
4284                         for (cnt = 0; cnt < max_rings; cnt++) {
4285                                 if (rx_queue_state[k] !=
4286                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4287                                         break;
4288                                 if (++k == max_rings)
4289                                         k = 0;
4290                         }
4291
4292                         /* Return if no rings are active. */
4293                         if (cnt == max_rings)
4294                                 return 0;
4295
4296                         /* Add rx/cp ring pair to RSS table. */
4297                         rxr = rxqs[k]->rx_ring;
4298                         cpr = rxqs[k]->cp_ring;
4299
4300                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4301                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4302                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4303                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4304
4305                         if (++k == max_rings)
4306                                 k = 0;
4307                 }
4308                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4309                                             BNXT_USE_CHIMP_MB);
4310
4311                 HWRM_CHECK_RESULT();
4312                 HWRM_UNLOCK();
4313         }
4314
4315         return rc;
4316 }
4317
4318 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4319 {
4320         unsigned int rss_idx, fw_idx, i;
4321
4322         if (!(vnic->rss_table && vnic->hash_type))
4323                 return 0;
4324
4325         if (BNXT_CHIP_THOR(bp))
4326                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4327
4328         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4329                 return 0;
4330
4331         if (vnic->rss_table && vnic->hash_type) {
4332                 /*
4333                  * Fill the RSS hash & redirection table with
4334                  * ring group ids for all VNICs
4335                  */
4336                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4337                         rss_idx++, fw_idx++) {
4338                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4339                                 fw_idx %= bp->rx_cp_nr_rings;
4340                                 if (vnic->fw_grp_ids[fw_idx] !=
4341                                     INVALID_HW_RING_ID)
4342                                         break;
4343                                 fw_idx++;
4344                         }
4345                         if (i == bp->rx_cp_nr_rings)
4346                                 return 0;
4347                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4348                 }
4349                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4350         }
4351
4352         return 0;
4353 }
4354
4355 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4356         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4357 {
4358         uint16_t flags;
4359
4360         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4361
4362         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4363         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4364
4365         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4366         req->num_cmpl_dma_aggr_during_int =
4367                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4368
4369         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4370
4371         /* min timer set to 1/2 of interrupt timer */
4372         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4373
4374         /* buf timer set to 1/4 of interrupt timer */
4375         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4376
4377         req->cmpl_aggr_dma_tmr_during_int =
4378                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4379
4380         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4381                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4382         req->flags = rte_cpu_to_le_16(flags);
4383 }
4384
4385 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4386                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4387 {
4388         struct hwrm_ring_aggint_qcaps_input req = {0};
4389         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4390         uint32_t enables;
4391         uint16_t flags;
4392         int rc;
4393
4394         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4396         HWRM_CHECK_RESULT();
4397
4398         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4399         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4400
4401         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4402                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4403         agg_req->flags = rte_cpu_to_le_16(flags);
4404         enables =
4405          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4406          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4407         agg_req->enables = rte_cpu_to_le_32(enables);
4408
4409         HWRM_UNLOCK();
4410         return rc;
4411 }
4412
4413 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4414                         struct bnxt_coal *coal, uint16_t ring_id)
4415 {
4416         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4417         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4418                                                 bp->hwrm_cmd_resp_addr;
4419         int rc;
4420
4421         /* Set ring coalesce parameters only for 100G NICs */
4422         if (BNXT_CHIP_THOR(bp)) {
4423                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4424                         return -1;
4425         } else if (bnxt_stratus_device(bp)) {
4426                 bnxt_hwrm_set_coal_params(coal, &req);
4427         } else {
4428                 return 0;
4429         }
4430
4431         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4432         req.ring_id = rte_cpu_to_le_16(ring_id);
4433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4434         HWRM_CHECK_RESULT();
4435         HWRM_UNLOCK();
4436         return 0;
4437 }
4438
4439 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4440 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4441 {
4442         struct hwrm_func_backing_store_qcaps_input req = {0};
4443         struct hwrm_func_backing_store_qcaps_output *resp =
4444                 bp->hwrm_cmd_resp_addr;
4445         struct bnxt_ctx_pg_info *ctx_pg;
4446         struct bnxt_ctx_mem_info *ctx;
4447         int total_alloc_len;
4448         int rc, i;
4449
4450         if (!BNXT_CHIP_THOR(bp) ||
4451             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4452             BNXT_VF(bp) ||
4453             bp->ctx)
4454                 return 0;
4455
4456         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4457         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4458         HWRM_CHECK_RESULT_SILENT();
4459
4460         total_alloc_len = sizeof(*ctx);
4461         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4462                           RTE_CACHE_LINE_SIZE);
4463         if (!ctx) {
4464                 rc = -ENOMEM;
4465                 goto ctx_err;
4466         }
4467
4468         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4469                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4470                             RTE_CACHE_LINE_SIZE);
4471         if (!ctx_pg) {
4472                 rc = -ENOMEM;
4473                 goto ctx_err;
4474         }
4475         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4476                 ctx->tqm_mem[i] = ctx_pg;
4477
4478         bp->ctx = ctx;
4479         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4480         ctx->qp_min_qp1_entries =
4481                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4482         ctx->qp_max_l2_entries =
4483                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4484         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4485         ctx->srq_max_l2_entries =
4486                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4487         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4488         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4489         ctx->cq_max_l2_entries =
4490                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4491         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4492         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4493         ctx->vnic_max_vnic_entries =
4494                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4495         ctx->vnic_max_ring_table_entries =
4496                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4497         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4498         ctx->stat_max_entries =
4499                 rte_le_to_cpu_32(resp->stat_max_entries);
4500         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4501         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4502         ctx->tqm_min_entries_per_ring =
4503                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4504         ctx->tqm_max_entries_per_ring =
4505                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4506         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4507         if (!ctx->tqm_entries_multiple)
4508                 ctx->tqm_entries_multiple = 1;
4509         ctx->mrav_max_entries =
4510                 rte_le_to_cpu_32(resp->mrav_max_entries);
4511         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4512         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4513         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4514 ctx_err:
4515         HWRM_UNLOCK();
4516         return rc;
4517 }
4518
4519 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4520 {
4521         struct hwrm_func_backing_store_cfg_input req = {0};
4522         struct hwrm_func_backing_store_cfg_output *resp =
4523                 bp->hwrm_cmd_resp_addr;
4524         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4525         struct bnxt_ctx_pg_info *ctx_pg;
4526         uint32_t *num_entries;
4527         uint64_t *pg_dir;
4528         uint8_t *pg_attr;
4529         uint32_t ena;
4530         int i, rc;
4531
4532         if (!ctx)
4533                 return 0;
4534
4535         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4536         req.enables = rte_cpu_to_le_32(enables);
4537
4538         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4539                 ctx_pg = &ctx->qp_mem;
4540                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4541                 req.qp_num_qp1_entries =
4542                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4543                 req.qp_num_l2_entries =
4544                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4545                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4546                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4547                                       &req.qpc_pg_size_qpc_lvl,
4548                                       &req.qpc_page_dir);
4549         }
4550
4551         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4552                 ctx_pg = &ctx->srq_mem;
4553                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4554                 req.srq_num_l2_entries =
4555                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4556                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4557                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4558                                       &req.srq_pg_size_srq_lvl,
4559                                       &req.srq_page_dir);
4560         }
4561
4562         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4563                 ctx_pg = &ctx->cq_mem;
4564                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4565                 req.cq_num_l2_entries =
4566                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4567                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4568                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4569                                       &req.cq_pg_size_cq_lvl,
4570                                       &req.cq_page_dir);
4571         }
4572
4573         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4574                 ctx_pg = &ctx->vnic_mem;
4575                 req.vnic_num_vnic_entries =
4576                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4577                 req.vnic_num_ring_table_entries =
4578                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4579                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4580                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4581                                       &req.vnic_pg_size_vnic_lvl,
4582                                       &req.vnic_page_dir);
4583         }
4584
4585         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4586                 ctx_pg = &ctx->stat_mem;
4587                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4588                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4589                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4590                                       &req.stat_pg_size_stat_lvl,
4591                                       &req.stat_page_dir);
4592         }
4593
4594         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4595         num_entries = &req.tqm_sp_num_entries;
4596         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4597         pg_dir = &req.tqm_sp_page_dir;
4598         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4599         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4600                 if (!(enables & ena))
4601                         continue;
4602
4603                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4604
4605                 ctx_pg = ctx->tqm_mem[i];
4606                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4607                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4608         }
4609
4610         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4611         HWRM_CHECK_RESULT();
4612         HWRM_UNLOCK();
4613
4614         return rc;
4615 }
4616
4617 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4618 {
4619         struct hwrm_port_qstats_ext_input req = {0};
4620         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4621         struct bnxt_pf_info *pf = &bp->pf;
4622         int rc;
4623
4624         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4625               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4626                 return 0;
4627
4628         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4629
4630         req.port_id = rte_cpu_to_le_16(pf->port_id);
4631         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4632                 req.tx_stat_host_addr =
4633                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4634                 req.tx_stat_size =
4635                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4636         }
4637         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4638                 req.rx_stat_host_addr =
4639                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4640                 req.rx_stat_size =
4641                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4642         }
4643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4644
4645         if (rc) {
4646                 bp->fw_rx_port_stats_ext_size = 0;
4647                 bp->fw_tx_port_stats_ext_size = 0;
4648         } else {
4649                 bp->fw_rx_port_stats_ext_size =
4650                         rte_le_to_cpu_16(resp->rx_stat_size);
4651                 bp->fw_tx_port_stats_ext_size =
4652                         rte_le_to_cpu_16(resp->tx_stat_size);
4653         }
4654
4655         HWRM_CHECK_RESULT();
4656         HWRM_UNLOCK();
4657
4658         return rc;
4659 }
4660
4661 int
4662 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4663 {
4664         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4665         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4666                 bp->hwrm_cmd_resp_addr;
4667         int rc = 0;
4668
4669         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4670         req.tunnel_type = type;
4671         req.dest_fid = bp->fw_fid;
4672         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4673         HWRM_CHECK_RESULT();
4674
4675         HWRM_UNLOCK();
4676
4677         return rc;
4678 }
4679
4680 int
4681 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4682 {
4683         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4684         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4685                 bp->hwrm_cmd_resp_addr;
4686         int rc = 0;
4687
4688         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4689         req.tunnel_type = type;
4690         req.dest_fid = bp->fw_fid;
4691         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4692         HWRM_CHECK_RESULT();
4693
4694         HWRM_UNLOCK();
4695
4696         return rc;
4697 }
4698
4699 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4700 {
4701         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4702         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4703                 bp->hwrm_cmd_resp_addr;
4704         int rc = 0;
4705
4706         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4707         req.src_fid = bp->fw_fid;
4708         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4709         HWRM_CHECK_RESULT();
4710
4711         if (type)
4712                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4713
4714         HWRM_UNLOCK();
4715
4716         return rc;
4717 }
4718
4719 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4720                                    uint16_t *dst_fid)
4721 {
4722         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4723         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4724                 bp->hwrm_cmd_resp_addr;
4725         int rc = 0;
4726
4727         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4728         req.src_fid = bp->fw_fid;
4729         req.tunnel_type = tun_type;
4730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4731         HWRM_CHECK_RESULT();
4732
4733         if (dst_fid)
4734                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4735
4736         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4737
4738         HWRM_UNLOCK();
4739
4740         return rc;
4741 }
4742
4743 int bnxt_hwrm_set_mac(struct bnxt *bp)
4744 {
4745         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4746         struct hwrm_func_vf_cfg_input req = {0};
4747         int rc = 0;
4748
4749         if (!BNXT_VF(bp))
4750                 return 0;
4751
4752         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4753
4754         req.enables =
4755                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4756         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4757
4758         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4759
4760         HWRM_CHECK_RESULT();
4761
4762         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4763         HWRM_UNLOCK();
4764
4765         return rc;
4766 }
4767
4768 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4769 {
4770         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4771         struct hwrm_func_drv_if_change_input req = {0};
4772         uint32_t flags;
4773         int rc;
4774
4775         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4776                 return 0;
4777
4778         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4779          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4780          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4781          */
4782         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4783                 return 0;
4784
4785         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4786
4787         if (up)
4788                 req.flags =
4789                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4790
4791         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4792
4793         HWRM_CHECK_RESULT();
4794         flags = rte_le_to_cpu_32(resp->flags);
4795         HWRM_UNLOCK();
4796
4797         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4798                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4799                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4800         }
4801
4802         return 0;
4803 }
4804
4805 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4806 {
4807         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4808         struct bnxt_error_recovery_info *info = bp->recovery_info;
4809         struct hwrm_error_recovery_qcfg_input req = {0};
4810         uint32_t flags = 0;
4811         unsigned int i;
4812         int rc;
4813
4814         /* Older FW does not have error recovery support */
4815         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4816                 return 0;
4817
4818         if (!info) {
4819                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4820                                    sizeof(*info), 0);
4821                 bp->recovery_info = info;
4822                 if (info == NULL)
4823                         return -ENOMEM;
4824         } else {
4825                 memset(info, 0, sizeof(*info));
4826         }
4827
4828         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4829
4830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4831
4832         HWRM_CHECK_RESULT();
4833
4834         flags = rte_le_to_cpu_32(resp->flags);
4835         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4836                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4837         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4838                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4839
4840         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4841             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4842                 rc = -EINVAL;
4843                 goto err;
4844         }
4845
4846         /* FW returned values are in units of 100msec */
4847         info->driver_polling_freq =
4848                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4849         info->master_func_wait_period =
4850                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4851         info->normal_func_wait_period =
4852                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4853         info->master_func_wait_period_after_reset =
4854                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4855         info->max_bailout_time_after_reset =
4856                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4857         info->status_regs[BNXT_FW_STATUS_REG] =
4858                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4859         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4860                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4861         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4862                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4863         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4864                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4865         info->reg_array_cnt =
4866                 rte_le_to_cpu_32(resp->reg_array_cnt);
4867
4868         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4869                 rc = -EINVAL;
4870                 goto err;
4871         }
4872
4873         for (i = 0; i < info->reg_array_cnt; i++) {
4874                 info->reset_reg[i] =
4875                         rte_le_to_cpu_32(resp->reset_reg[i]);
4876                 info->reset_reg_val[i] =
4877                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4878                 info->delay_after_reset[i] =
4879                         resp->delay_after_reset[i];
4880         }
4881 err:
4882         HWRM_UNLOCK();
4883
4884         /* Map the FW status registers */
4885         if (!rc)
4886                 rc = bnxt_map_fw_health_status_regs(bp);
4887
4888         if (rc) {
4889                 rte_free(bp->recovery_info);
4890                 bp->recovery_info = NULL;
4891         }
4892         return rc;
4893 }
4894
4895 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4896 {
4897         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4898         struct hwrm_fw_reset_input req = {0};
4899         int rc;
4900
4901         if (!BNXT_PF(bp))
4902                 return -EOPNOTSUPP;
4903
4904         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4905
4906         req.embedded_proc_type =
4907                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4908         req.selfrst_status =
4909                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4910         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4911
4912         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4913                                     BNXT_USE_KONG(bp));
4914
4915         HWRM_CHECK_RESULT();
4916         HWRM_UNLOCK();
4917
4918         return rc;
4919 }
4920
4921 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4922 {
4923         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4924         struct hwrm_port_ts_query_input req = {0};
4925         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4926         uint32_t flags = 0;
4927         int rc;
4928
4929         if (!ptp)
4930                 return 0;
4931
4932         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4933
4934         switch (path) {
4935         case BNXT_PTP_FLAGS_PATH_TX:
4936                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4937                 break;
4938         case BNXT_PTP_FLAGS_PATH_RX:
4939                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
4940                 break;
4941         case BNXT_PTP_FLAGS_CURRENT_TIME:
4942                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
4943                 break;
4944         }
4945
4946         req.flags = rte_cpu_to_le_32(flags);
4947         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
4948
4949         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4950
4951         HWRM_CHECK_RESULT();
4952
4953         if (timestamp) {
4954                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
4955                 *timestamp |=
4956                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
4957         }
4958         HWRM_UNLOCK();
4959
4960         return rc;
4961 }
4962
4963 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
4964 {
4965         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
4966                                         bp->hwrm_cmd_resp_addr;
4967         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
4968         uint32_t flags = 0;
4969         int rc = 0;
4970
4971         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
4972                 return rc;
4973
4974         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
4975                 PMD_DRV_LOG(DEBUG,
4976                             "Not a PF or trusted VF. Command not supported\n");
4977                 return 0;
4978         }
4979
4980         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
4981         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4982
4983         HWRM_CHECK_RESULT();
4984         flags = rte_le_to_cpu_32(resp->flags);
4985         HWRM_UNLOCK();
4986
4987         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
4988                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
4989                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
4990         }
4991
4992         return rc;
4993 }