1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 req.flags = rte_cpu_to_le_32(filter->flags);
535 enables = filter->enables |
536 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
537 req.dst_id = rte_cpu_to_le_16(dst_id);
540 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
541 memcpy(req.l2_addr, filter->l2_addr,
544 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
545 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
548 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
549 req.l2_ovlan = filter->l2_ovlan;
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
552 req.l2_ivlan = filter->l2_ivlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
555 req.l2_ovlan_mask = filter->l2_ovlan_mask;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
558 req.l2_ivlan_mask = filter->l2_ivlan_mask;
559 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
560 req.src_id = rte_cpu_to_le_32(filter->src_id);
561 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
562 req.src_type = filter->src_type;
563 if (filter->pri_hint) {
564 req.pri_hint = filter->pri_hint;
565 req.l2_filter_id_hint =
566 rte_cpu_to_le_64(filter->l2_filter_id_hint);
569 req.enables = rte_cpu_to_le_32(enables);
571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
575 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
576 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
579 filter->l2_ref_cnt++;
584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
586 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
587 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
594 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
597 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
600 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
601 if (ptp->tx_tstamp_en)
602 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
605 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
606 req.flags = rte_cpu_to_le_32(flags);
607 req.enables = rte_cpu_to_le_32
608 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
609 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
620 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
621 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
622 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
627 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
629 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
635 if (!BNXT_CHIP_THOR(bp) &&
636 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
639 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
640 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
642 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
646 if (!BNXT_CHIP_THOR(bp)) {
647 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
648 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
649 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
650 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
651 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
652 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
653 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
654 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
655 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
656 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
657 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
658 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
659 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
660 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
661 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
662 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
663 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
664 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
676 struct hwrm_func_qcaps_input req = {.req_type = 0 };
677 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
678 uint16_t new_max_vfs;
682 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
684 req.fid = rte_cpu_to_le_16(0xffff);
686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
690 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
691 flags = rte_le_to_cpu_32(resp->flags);
693 bp->pf->port_id = resp->port_id;
694 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
695 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
696 new_max_vfs = bp->pdev->max_vfs;
697 if (new_max_vfs != bp->pf->max_vfs) {
699 rte_free(bp->pf->vf_info);
700 bp->pf->vf_info = rte_malloc("bnxt_vf_info",
701 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
702 bp->pf->max_vfs = new_max_vfs;
703 for (i = 0; i < new_max_vfs; i++) {
704 bp->pf->vf_info[i].fid =
705 bp->pf->first_vf_id + i;
706 bp->pf->vf_info[i].vlan_table =
707 rte_zmalloc("VF VLAN table",
710 if (bp->pf->vf_info[i].vlan_table == NULL)
712 "Fail to alloc VLAN table for VF %d\n",
716 bp->pf->vf_info[i].vlan_table);
717 bp->pf->vf_info[i].vlan_as_table =
718 rte_zmalloc("VF VLAN AS table",
721 if (bp->pf->vf_info[i].vlan_as_table == NULL)
723 "Alloc VLAN AS table for VF %d fail\n",
727 bp->pf->vf_info[i].vlan_as_table);
728 STAILQ_INIT(&bp->pf->vf_info[i].filter);
733 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
734 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
735 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
736 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
738 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
740 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
741 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
742 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
743 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
744 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
745 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
746 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
747 if (!BNXT_CHIP_THOR(bp))
748 bp->max_l2_ctx += bp->max_rx_em_flows;
749 /* TODO: For now, do not support VMDq/RFS on VFs. */
754 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
758 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
759 bp->max_l2_ctx, bp->max_vnics);
760 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
762 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
763 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
764 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
765 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
767 bnxt_hwrm_ptp_qcfg(bp);
771 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
772 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
774 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
775 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
776 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
779 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
780 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
782 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
783 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
794 rc = __bnxt_hwrm_func_qcaps(bp);
795 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
796 rc = bnxt_alloc_ctx_mem(bp);
800 rc = bnxt_hwrm_func_resc_qcaps(bp);
802 bp->flags |= BNXT_FLAG_NEW_RM;
806 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
807 * But the error can be ignored. Return success.
813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
817 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
818 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
820 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
822 req.target_id = rte_cpu_to_le_16(0xffff);
824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
828 if (rte_le_to_cpu_32(resp->flags) &
829 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
830 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
831 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
834 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
841 int bnxt_hwrm_func_reset(struct bnxt *bp)
844 struct hwrm_func_reset_input req = {.req_type = 0 };
845 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
847 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
849 req.enables = rte_cpu_to_le_32(0);
851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
863 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
864 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
866 if (bp->flags & BNXT_FLAG_REGISTERED)
869 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
870 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
871 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
872 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
874 /* PFs and trusted VFs should indicate the support of the
875 * Master capability on non Stingray platform
877 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
878 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
880 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
881 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
882 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
883 req.ver_maj = RTE_VER_YEAR;
884 req.ver_min = RTE_VER_MONTH;
885 req.ver_upd = RTE_VER_MINOR;
888 req.enables |= rte_cpu_to_le_32(
889 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
890 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
891 RTE_MIN(sizeof(req.vf_req_fwd),
892 sizeof(bp->pf->vf_req_fwd)));
895 * PF can sniff HWRM API issued by VF. This can be set up by
896 * linux driver and inherited by the DPDK PF driver. Clear
897 * this HWRM sniffer list in FW because DPDK PF driver does
900 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
903 req.flags = rte_cpu_to_le_32(flags);
905 req.async_event_fwd[0] |=
906 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
907 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
908 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
909 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
910 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
911 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
912 req.async_event_fwd[0] |=
913 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
914 req.async_event_fwd[1] |=
915 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
916 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
918 req.async_event_fwd[1] |=
919 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
925 flags = rte_le_to_cpu_32(resp->flags);
926 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
927 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
931 bp->flags |= BNXT_FLAG_REGISTERED;
936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
938 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
941 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
949 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
950 struct hwrm_func_vf_cfg_input req = {0};
952 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
954 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
955 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
956 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
957 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
958 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
960 if (BNXT_HAS_RING_GRPS(bp)) {
961 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
962 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
965 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
966 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
967 AGG_RING_MULTIPLIER);
968 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
969 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
971 BNXT_NUM_ASYNC_CPR(bp));
972 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
973 if (bp->vf_resv_strategy ==
974 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
975 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
976 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
977 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
978 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
979 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
980 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
981 } else if (bp->vf_resv_strategy ==
982 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
983 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
984 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
988 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
989 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
990 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
991 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
992 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
993 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
995 if (test && BNXT_HAS_RING_GRPS(bp))
996 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
998 req.flags = rte_cpu_to_le_32(flags);
999 req.enables |= rte_cpu_to_le_32(enables);
1001 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1004 HWRM_CHECK_RESULT_SILENT();
1006 HWRM_CHECK_RESULT();
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1015 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016 struct hwrm_func_resource_qcaps_input req = {0};
1018 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019 req.fid = rte_cpu_to_le_16(0xffff);
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT_SILENT();
1026 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031 /* func_resource_qcaps does not return max_rx_em_flows.
1032 * So use the value provided by func_qcaps.
1034 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035 if (!BNXT_CHIP_THOR(bp))
1036 bp->max_l2_ctx += bp->max_rx_em_flows;
1037 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1040 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042 if (bp->vf_resv_strategy >
1043 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044 bp->vf_resv_strategy =
1045 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1054 struct hwrm_ver_get_input req = {.req_type = 0 };
1055 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056 uint32_t fw_version;
1057 uint16_t max_resp_len;
1058 char type[RTE_MEMZONE_NAMESIZE];
1059 uint32_t dev_caps_cfg;
1061 bp->max_req_len = HWRM_MAX_REQ_LEN;
1062 bp->hwrm_cmd_timeout = timeout;
1063 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1065 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1071 if (bp->flags & BNXT_FLAG_FW_RESET)
1072 HWRM_CHECK_RESULT_SILENT();
1074 HWRM_CHECK_RESULT();
1076 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081 (resp->hwrm_fw_min_8b << 16) |
1082 (resp->hwrm_fw_bld_8b << 8) |
1083 resp->hwrm_fw_rsvd_8b;
1084 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1087 fw_version = resp->hwrm_intf_maj_8b << 16;
1088 fw_version |= resp->hwrm_intf_min_8b << 8;
1089 fw_version |= resp->hwrm_intf_upd_8b;
1090 bp->hwrm_spec_code = fw_version;
1092 /* def_req_timeout value is in milliseconds */
1093 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094 /* convert timeout to usec */
1095 bp->hwrm_cmd_timeout *= 1000;
1096 if (!bp->hwrm_cmd_timeout)
1097 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1099 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1105 if (bp->max_req_len > resp->max_req_win_len) {
1106 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1109 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1114 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1117 if (bp->max_resp_len != max_resp_len) {
1118 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119 bp->pdev->addr.domain, bp->pdev->addr.bus,
1120 bp->pdev->addr.devid, bp->pdev->addr.function);
1122 rte_free(bp->hwrm_cmd_resp_addr);
1124 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125 if (bp->hwrm_cmd_resp_addr == NULL) {
1129 bp->hwrm_cmd_resp_dma_addr =
1130 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1133 "Unable to map response buffer to physical memory.\n");
1137 bp->max_resp_len = max_resp_len;
1141 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1143 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145 bp->flags |= BNXT_FLAG_SHORT_CMD;
1148 if (((dev_caps_cfg &
1149 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1151 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154 bp->pdev->addr.domain, bp->pdev->addr.bus,
1155 bp->pdev->addr.devid, bp->pdev->addr.function);
1157 rte_free(bp->hwrm_short_cmd_req_addr);
1159 bp->hwrm_short_cmd_req_addr =
1160 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161 if (bp->hwrm_short_cmd_req_addr == NULL) {
1165 bp->hwrm_short_cmd_req_dma_addr =
1166 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168 rte_free(bp->hwrm_short_cmd_req_addr);
1170 "Unable to map buffer to physical memory.\n");
1176 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1184 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1190 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1204 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1207 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1210 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215 HWRM_CHECK_RESULT();
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1224 struct hwrm_port_phy_cfg_input req = {0};
1225 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226 uint32_t enables = 0;
1228 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1230 if (conf->link_up) {
1231 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232 if (bp->link_info->auto_mode && conf->link_speed) {
1233 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1237 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1241 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242 * any auto mode, even "none".
1244 if (!conf->link_speed) {
1245 /* No speeds specified. Enable AutoNeg - all speeds */
1247 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1249 /* AutoNeg - Advertise speeds specified. */
1250 if (conf->auto_link_speed_mask &&
1251 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1253 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254 req.auto_link_speed_mask =
1255 conf->auto_link_speed_mask;
1257 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1260 req.auto_duplex = conf->duplex;
1261 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262 req.auto_pause = conf->auto_pause;
1263 req.force_pause = conf->force_pause;
1264 /* Set force_pause if there is no auto or if there is a force */
1265 if (req.auto_pause && !req.force_pause)
1266 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1268 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1270 req.enables = rte_cpu_to_le_32(enables);
1273 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274 PMD_DRV_LOG(INFO, "Force Link Down\n");
1277 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1279 HWRM_CHECK_RESULT();
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286 struct bnxt_link_info *link_info)
1289 struct hwrm_port_phy_qcfg_input req = {0};
1290 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1292 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1296 HWRM_CHECK_RESULT();
1298 link_info->phy_link_status = resp->link;
1299 link_info->link_up =
1300 (link_info->phy_link_status ==
1301 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303 link_info->duplex = resp->duplex_cfg;
1304 link_info->pause = resp->pause;
1305 link_info->auto_pause = resp->auto_pause;
1306 link_info->force_pause = resp->force_pause;
1307 link_info->auto_mode = resp->auto_mode;
1308 link_info->phy_type = resp->phy_type;
1309 link_info->media_type = resp->media_type;
1311 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315 link_info->phy_ver[0] = resp->phy_maj;
1316 link_info->phy_ver[1] = resp->phy_min;
1317 link_info->phy_ver[2] = resp->phy_bld;
1321 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326 link_info->auto_link_speed_mask);
1327 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328 link_info->force_link_speed);
1333 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1337 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1338 if (bp->tx_cos_queue[i].profile ==
1339 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1340 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1347 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1351 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1352 if (bp->tx_cos_queue[i].profile !=
1353 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1354 bp->tx_cos_queue[i].id !=
1355 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1356 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1362 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1365 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1366 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1367 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1371 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1373 req.flags = rte_cpu_to_le_32(dir);
1374 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1375 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1376 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1378 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1381 HWRM_CHECK_RESULT();
1383 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1384 GET_TX_QUEUE_INFO(0);
1385 GET_TX_QUEUE_INFO(1);
1386 GET_TX_QUEUE_INFO(2);
1387 GET_TX_QUEUE_INFO(3);
1388 GET_TX_QUEUE_INFO(4);
1389 GET_TX_QUEUE_INFO(5);
1390 GET_TX_QUEUE_INFO(6);
1391 GET_TX_QUEUE_INFO(7);
1393 GET_RX_QUEUE_INFO(0);
1394 GET_RX_QUEUE_INFO(1);
1395 GET_RX_QUEUE_INFO(2);
1396 GET_RX_QUEUE_INFO(3);
1397 GET_RX_QUEUE_INFO(4);
1398 GET_RX_QUEUE_INFO(5);
1399 GET_RX_QUEUE_INFO(6);
1400 GET_RX_QUEUE_INFO(7);
1405 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1408 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1409 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1413 /* iterate and find the COSq profile to use for Tx */
1414 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1415 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1416 if (bp->tx_cos_queue[i].id != 0xff)
1417 bp->tx_cosq_id[j++] =
1418 bp->tx_cos_queue[i].id;
1421 /* When CoS classification is disabled, for normal NIC
1422 * operations, ideally we should look to use LOSSY.
1423 * If not found, fallback to the first valid profile
1425 if (!bnxt_find_lossy_profile(bp))
1426 bnxt_find_first_valid_profile(bp);
1431 bp->max_tc = resp->max_configurable_queues;
1432 bp->max_lltc = resp->max_configurable_lossless_queues;
1433 if (bp->max_tc > BNXT_MAX_QUEUE)
1434 bp->max_tc = BNXT_MAX_QUEUE;
1435 bp->max_q = bp->max_tc;
1437 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1438 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1446 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1447 struct bnxt_ring *ring,
1448 uint32_t ring_type, uint32_t map_index,
1449 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1450 uint16_t tx_cosq_id)
1453 uint32_t enables = 0;
1454 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1455 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1456 struct rte_mempool *mb_pool;
1457 uint16_t rx_buf_size;
1459 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1461 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1462 req.fbo = rte_cpu_to_le_32(0);
1463 /* Association of ring index with doorbell index */
1464 req.logical_id = rte_cpu_to_le_16(map_index);
1465 req.length = rte_cpu_to_le_32(ring->ring_size);
1467 switch (ring_type) {
1468 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1469 req.ring_type = ring_type;
1470 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1471 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1472 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1473 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1475 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1477 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1478 req.ring_type = ring_type;
1479 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1480 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1481 if (BNXT_CHIP_THOR(bp)) {
1482 mb_pool = bp->rx_queues[0]->mb_pool;
1483 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1484 RTE_PKTMBUF_HEADROOM;
1485 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1486 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1488 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1490 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1492 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1494 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1495 req.ring_type = ring_type;
1496 if (BNXT_HAS_NQ(bp)) {
1497 /* Association of cp ring with nq */
1498 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1500 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1502 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1504 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1505 req.ring_type = ring_type;
1506 req.page_size = BNXT_PAGE_SHFT;
1507 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1509 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1510 req.ring_type = ring_type;
1511 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1513 mb_pool = bp->rx_queues[0]->mb_pool;
1514 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1515 RTE_PKTMBUF_HEADROOM;
1516 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1517 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1519 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1520 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1521 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1522 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1525 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1530 req.enables = rte_cpu_to_le_32(enables);
1532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1534 if (rc || resp->error_code) {
1535 if (rc == 0 && resp->error_code)
1536 rc = rte_le_to_cpu_16(resp->error_code);
1537 switch (ring_type) {
1538 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1540 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1543 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1545 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1548 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1550 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1554 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1556 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1559 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1561 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1565 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1571 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1576 int bnxt_hwrm_ring_free(struct bnxt *bp,
1577 struct bnxt_ring *ring, uint32_t ring_type)
1580 struct hwrm_ring_free_input req = {.req_type = 0 };
1581 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1583 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1585 req.ring_type = ring_type;
1586 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1590 if (rc || resp->error_code) {
1591 if (rc == 0 && resp->error_code)
1592 rc = rte_le_to_cpu_16(resp->error_code);
1595 switch (ring_type) {
1596 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1597 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1600 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1601 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1604 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1605 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1608 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1610 "hwrm_ring_free nq failed. rc:%d\n", rc);
1612 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1614 "hwrm_ring_free agg failed. rc:%d\n", rc);
1617 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1625 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1628 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1629 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1631 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1633 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1634 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1635 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1636 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1638 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1640 HWRM_CHECK_RESULT();
1642 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1649 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1652 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1653 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1655 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1657 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1661 HWRM_CHECK_RESULT();
1664 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1668 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1671 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1672 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1674 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1677 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1679 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683 HWRM_CHECK_RESULT();
1689 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1690 unsigned int idx __rte_unused)
1693 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1694 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1696 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1698 req.update_period_ms = rte_cpu_to_le_32(0);
1700 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1704 HWRM_CHECK_RESULT();
1706 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1713 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1714 unsigned int idx __rte_unused)
1717 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1718 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1720 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1722 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1726 HWRM_CHECK_RESULT();
1732 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1735 struct hwrm_vnic_alloc_input req = { 0 };
1736 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1738 if (!BNXT_HAS_RING_GRPS(bp))
1739 goto skip_ring_grps;
1741 /* map ring groups to this vnic */
1742 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1743 vnic->start_grp_id, vnic->end_grp_id);
1744 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1745 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1747 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1748 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1749 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1750 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1753 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1754 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1756 if (vnic->func_default)
1758 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761 HWRM_CHECK_RESULT();
1763 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1765 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1769 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1770 struct bnxt_vnic_info *vnic,
1771 struct bnxt_plcmodes_cfg *pmode)
1774 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1777 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1779 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783 HWRM_CHECK_RESULT();
1785 pmode->flags = rte_le_to_cpu_32(resp->flags);
1786 /* dflt_vnic bit doesn't exist in the _cfg command */
1787 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1788 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1789 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1790 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1797 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1798 struct bnxt_vnic_info *vnic,
1799 struct bnxt_plcmodes_cfg *pmode)
1802 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1803 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1805 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1806 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1810 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1812 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1813 req.flags = rte_cpu_to_le_32(pmode->flags);
1814 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1815 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1816 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1817 req.enables = rte_cpu_to_le_32(
1818 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1819 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1820 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1823 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1825 HWRM_CHECK_RESULT();
1831 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1834 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1835 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1836 struct bnxt_plcmodes_cfg pmodes = { 0 };
1837 uint32_t ctx_enable_flag = 0;
1838 uint32_t enables = 0;
1840 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1841 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1845 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1849 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1851 if (BNXT_CHIP_THOR(bp)) {
1852 int dflt_rxq = vnic->start_grp_id;
1853 struct bnxt_rx_ring_info *rxr;
1854 struct bnxt_cp_ring_info *cpr;
1855 struct bnxt_rx_queue *rxq;
1859 * The first active receive ring is used as the VNIC
1860 * default receive ring. If there are no active receive
1861 * rings (all corresponding receive queues are stopped),
1862 * the first receive ring is used.
1864 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1865 rxq = bp->eth_dev->data->rx_queues[i];
1866 if (rxq->rx_started) {
1872 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1876 req.default_rx_ring_id =
1877 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1878 req.default_cmpl_ring_id =
1879 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1880 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1881 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1885 /* Only RSS support for now TBD: COS & LB */
1886 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1887 if (vnic->lb_rule != 0xffff)
1888 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1889 if (vnic->cos_rule != 0xffff)
1890 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1891 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1892 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1893 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1895 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1896 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1897 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1900 enables |= ctx_enable_flag;
1901 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1902 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1903 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1904 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1907 req.enables = rte_cpu_to_le_32(enables);
1908 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1909 req.mru = rte_cpu_to_le_16(vnic->mru);
1910 /* Configure default VNIC only once. */
1911 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1913 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1914 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1916 if (vnic->vlan_strip)
1918 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1921 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1922 if (vnic->roce_dual)
1923 req.flags |= rte_cpu_to_le_32(
1924 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1925 if (vnic->roce_only)
1926 req.flags |= rte_cpu_to_le_32(
1927 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1928 if (vnic->rss_dflt_cr)
1929 req.flags |= rte_cpu_to_le_32(
1930 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1934 HWRM_CHECK_RESULT();
1937 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1942 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1946 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1947 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1949 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1950 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1953 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1956 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1957 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1958 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1962 HWRM_CHECK_RESULT();
1964 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1965 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1966 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1967 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1968 vnic->mru = rte_le_to_cpu_16(resp->mru);
1969 vnic->func_default = rte_le_to_cpu_32(
1970 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1971 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1972 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1973 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1974 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1975 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1976 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1977 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1978 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1979 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1980 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1987 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1988 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1992 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1993 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1994 bp->hwrm_cmd_resp_addr;
1996 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999 HWRM_CHECK_RESULT();
2001 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2002 if (!BNXT_HAS_RING_GRPS(bp))
2003 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2004 else if (ctx_idx == 0)
2005 vnic->rss_rule = ctx_id;
2013 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2014 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2017 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2018 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2019 bp->hwrm_cmd_resp_addr;
2021 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2022 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2025 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2027 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2031 HWRM_CHECK_RESULT();
2037 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2041 if (BNXT_CHIP_THOR(bp)) {
2044 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2045 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2047 vnic->fw_grp_ids[j]);
2048 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2050 vnic->num_lb_ctxts = 0;
2052 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2053 vnic->rss_rule = INVALID_HW_RING_ID;
2059 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2062 struct hwrm_vnic_free_input req = {.req_type = 0 };
2063 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2065 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2066 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2070 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2072 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2076 HWRM_CHECK_RESULT();
2079 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2080 /* Configure default VNIC again if necessary. */
2081 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2082 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2088 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2092 int nr_ctxs = vnic->num_lb_ctxts;
2093 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2094 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2096 for (i = 0; i < nr_ctxs; i++) {
2097 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2099 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2100 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2101 req.hash_mode_flags = vnic->hash_mode;
2103 req.hash_key_tbl_addr =
2104 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2106 req.ring_grp_tbl_addr =
2107 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2108 i * HW_HASH_INDEX_SIZE);
2109 req.ring_table_pair_index = i;
2110 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2115 HWRM_CHECK_RESULT();
2122 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2123 struct bnxt_vnic_info *vnic)
2126 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2127 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2129 if (!vnic->rss_table)
2132 if (BNXT_CHIP_THOR(bp))
2133 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2135 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2137 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2138 req.hash_mode_flags = vnic->hash_mode;
2140 req.ring_grp_tbl_addr =
2141 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2142 req.hash_key_tbl_addr =
2143 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2144 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2145 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2147 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2149 HWRM_CHECK_RESULT();
2155 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2156 struct bnxt_vnic_info *vnic)
2159 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2160 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2163 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2164 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2168 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2170 req.flags = rte_cpu_to_le_32(
2171 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2173 req.enables = rte_cpu_to_le_32(
2174 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2176 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2177 size -= RTE_PKTMBUF_HEADROOM;
2178 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2180 req.jumbo_thresh = rte_cpu_to_le_16(size);
2181 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2185 HWRM_CHECK_RESULT();
2191 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2192 struct bnxt_vnic_info *vnic, bool enable)
2195 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2196 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2198 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2200 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2204 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2205 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2209 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2212 req.enables = rte_cpu_to_le_32(
2213 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2214 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2215 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2216 req.flags = rte_cpu_to_le_32(
2217 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2218 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2219 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2220 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2221 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2222 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2223 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2224 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2225 req.min_agg_len = rte_cpu_to_le_32(512);
2227 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2231 HWRM_CHECK_RESULT();
2237 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2239 struct hwrm_func_cfg_input req = {0};
2240 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2243 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2244 req.enables = rte_cpu_to_le_32(
2245 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2246 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2247 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2249 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2251 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252 HWRM_CHECK_RESULT();
2255 bp->pf->vf_info[vf].random_mac = false;
2260 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2264 struct hwrm_func_qstats_input req = {.req_type = 0};
2265 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2267 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2269 req.fid = rte_cpu_to_le_16(fid);
2271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2273 HWRM_CHECK_RESULT();
2276 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2283 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2284 struct rte_eth_stats *stats,
2285 struct hwrm_func_qstats_output *func_qstats)
2288 struct hwrm_func_qstats_input req = {.req_type = 0};
2289 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2291 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2293 req.fid = rte_cpu_to_le_16(fid);
2295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2297 HWRM_CHECK_RESULT();
2299 memcpy(func_qstats, resp,
2300 sizeof(struct hwrm_func_qstats_output));
2305 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2306 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2307 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2308 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2309 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2310 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2312 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2313 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2314 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2315 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2316 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2317 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2319 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2320 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2321 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2329 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2332 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2333 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2335 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2337 req.fid = rte_cpu_to_le_16(fid);
2339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2341 HWRM_CHECK_RESULT();
2347 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2352 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2353 struct bnxt_tx_queue *txq;
2354 struct bnxt_rx_queue *rxq;
2355 struct bnxt_cp_ring_info *cpr;
2357 if (i >= bp->rx_cp_nr_rings) {
2358 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2361 rxq = bp->rx_queues[i];
2365 rc = bnxt_hwrm_stat_clear(bp, cpr);
2373 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2377 struct bnxt_cp_ring_info *cpr;
2379 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2381 if (i >= bp->rx_cp_nr_rings) {
2382 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2384 cpr = bp->rx_queues[i]->cp_ring;
2385 if (BNXT_HAS_RING_GRPS(bp))
2386 bp->grp_info[i].fw_stats_ctx = -1;
2388 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2389 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2390 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2398 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2403 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2404 struct bnxt_tx_queue *txq;
2405 struct bnxt_rx_queue *rxq;
2406 struct bnxt_cp_ring_info *cpr;
2408 if (i >= bp->rx_cp_nr_rings) {
2409 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2412 rxq = bp->rx_queues[i];
2416 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2425 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2430 if (!BNXT_HAS_RING_GRPS(bp))
2433 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2435 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2438 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2446 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2448 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2450 bnxt_hwrm_ring_free(bp, cp_ring,
2451 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2452 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2453 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2454 sizeof(*cpr->cp_desc_ring));
2455 cpr->cp_raw_cons = 0;
2459 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2461 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2463 bnxt_hwrm_ring_free(bp, cp_ring,
2464 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2465 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2466 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2467 sizeof(*cpr->cp_desc_ring));
2468 cpr->cp_raw_cons = 0;
2472 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2474 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2475 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2476 struct bnxt_ring *ring = rxr->rx_ring_struct;
2477 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2479 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2480 bnxt_hwrm_ring_free(bp, ring,
2481 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2482 ring->fw_ring_id = INVALID_HW_RING_ID;
2483 if (BNXT_HAS_RING_GRPS(bp))
2484 bp->grp_info[queue_index].rx_fw_ring_id =
2487 ring = rxr->ag_ring_struct;
2488 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2489 bnxt_hwrm_ring_free(bp, ring,
2490 BNXT_CHIP_THOR(bp) ?
2491 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2492 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2493 if (BNXT_HAS_RING_GRPS(bp))
2494 bp->grp_info[queue_index].ag_fw_ring_id =
2497 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2498 bnxt_free_cp_ring(bp, cpr);
2500 if (BNXT_HAS_RING_GRPS(bp))
2501 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2505 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2509 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2510 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2511 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2512 struct bnxt_ring *ring = txr->tx_ring_struct;
2513 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2515 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2516 bnxt_hwrm_ring_free(bp, ring,
2517 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2518 ring->fw_ring_id = INVALID_HW_RING_ID;
2519 memset(txr->tx_desc_ring, 0,
2520 txr->tx_ring_struct->ring_size *
2521 sizeof(*txr->tx_desc_ring));
2522 memset(txr->tx_buf_ring, 0,
2523 txr->tx_ring_struct->ring_size *
2524 sizeof(*txr->tx_buf_ring));
2528 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2529 bnxt_free_cp_ring(bp, cpr);
2530 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2534 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2535 bnxt_free_hwrm_rx_ring(bp, i);
2540 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2545 if (!BNXT_HAS_RING_GRPS(bp))
2548 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2549 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2557 * HWRM utility functions
2560 void bnxt_free_hwrm_resources(struct bnxt *bp)
2562 /* Release memzone */
2563 rte_free(bp->hwrm_cmd_resp_addr);
2564 rte_free(bp->hwrm_short_cmd_req_addr);
2565 bp->hwrm_cmd_resp_addr = NULL;
2566 bp->hwrm_short_cmd_req_addr = NULL;
2567 bp->hwrm_cmd_resp_dma_addr = 0;
2568 bp->hwrm_short_cmd_req_dma_addr = 0;
2571 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2573 struct rte_pci_device *pdev = bp->pdev;
2574 char type[RTE_MEMZONE_NAMESIZE];
2576 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2578 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2579 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2580 if (bp->hwrm_cmd_resp_addr == NULL)
2582 bp->hwrm_cmd_resp_dma_addr =
2583 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2584 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2586 "unable to map response address to physical memory\n");
2589 rte_spinlock_init(&bp->hwrm_lock);
2595 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2597 struct bnxt_filter_info *filter;
2600 STAILQ_FOREACH(filter, &vnic->filter, next) {
2601 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2602 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2603 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2604 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2605 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2606 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2607 bnxt_free_filter(bp, filter);
2613 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2615 struct bnxt_filter_info *filter;
2616 struct rte_flow *flow;
2619 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2620 flow = STAILQ_FIRST(&vnic->flow_list);
2621 filter = flow->filter;
2622 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2623 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2624 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2625 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2626 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2629 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2635 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2637 struct bnxt_filter_info *filter;
2640 STAILQ_FOREACH(filter, &vnic->filter, next) {
2641 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2642 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2644 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2645 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2648 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2657 bnxt_free_tunnel_ports(struct bnxt *bp)
2659 if (bp->vxlan_port_cnt)
2660 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2661 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2663 if (bp->geneve_port_cnt)
2664 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2665 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2666 bp->geneve_port = 0;
2669 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2673 if (bp->vnic_info == NULL)
2677 * Cleanup VNICs in reverse order, to make sure the L2 filter
2678 * from vnic0 is last to be cleaned up.
2680 for (i = bp->max_vnics - 1; i >= 0; i--) {
2681 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2683 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2686 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2688 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2690 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2692 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2694 bnxt_hwrm_vnic_free(bp, vnic);
2696 rte_free(vnic->fw_grp_ids);
2698 /* Ring resources */
2699 bnxt_free_all_hwrm_rings(bp);
2700 bnxt_free_all_hwrm_ring_grps(bp);
2701 bnxt_free_all_hwrm_stat_ctxs(bp);
2702 bnxt_free_tunnel_ports(bp);
2705 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2707 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2709 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2710 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2712 switch (conf_link_speed) {
2713 case ETH_LINK_SPEED_10M_HD:
2714 case ETH_LINK_SPEED_100M_HD:
2716 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2718 return hw_link_duplex;
2721 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2723 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2726 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2728 uint16_t eth_link_speed = 0;
2730 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2731 return ETH_LINK_SPEED_AUTONEG;
2733 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2734 case ETH_LINK_SPEED_100M:
2735 case ETH_LINK_SPEED_100M_HD:
2738 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2740 case ETH_LINK_SPEED_1G:
2742 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2744 case ETH_LINK_SPEED_2_5G:
2746 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2748 case ETH_LINK_SPEED_10G:
2750 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2752 case ETH_LINK_SPEED_20G:
2754 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2756 case ETH_LINK_SPEED_25G:
2758 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2760 case ETH_LINK_SPEED_40G:
2762 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2764 case ETH_LINK_SPEED_50G:
2766 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2768 case ETH_LINK_SPEED_100G:
2770 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2772 case ETH_LINK_SPEED_200G:
2774 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2778 "Unsupported link speed %d; default to AUTO\n",
2782 return eth_link_speed;
2785 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2786 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2787 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2788 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2789 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2791 static int bnxt_validate_link_speed(struct bnxt *bp)
2793 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2794 uint16_t port_id = bp->eth_dev->data->port_id;
2795 uint32_t link_speed_capa;
2798 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2801 link_speed_capa = bnxt_get_speed_capabilities(bp);
2803 if (link_speed & ETH_LINK_SPEED_FIXED) {
2804 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2806 if (one_speed & (one_speed - 1)) {
2808 "Invalid advertised speeds (%u) for port %u\n",
2809 link_speed, port_id);
2812 if ((one_speed & link_speed_capa) != one_speed) {
2814 "Unsupported advertised speed (%u) for port %u\n",
2815 link_speed, port_id);
2819 if (!(link_speed & link_speed_capa)) {
2821 "Unsupported advertised speeds (%u) for port %u\n",
2822 link_speed, port_id);
2830 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2834 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2835 if (bp->link_info->support_speeds)
2836 return bp->link_info->support_speeds;
2837 link_speed = BNXT_SUPPORTED_SPEEDS;
2840 if (link_speed & ETH_LINK_SPEED_100M)
2841 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2842 if (link_speed & ETH_LINK_SPEED_100M_HD)
2843 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2844 if (link_speed & ETH_LINK_SPEED_1G)
2845 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2846 if (link_speed & ETH_LINK_SPEED_2_5G)
2847 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2848 if (link_speed & ETH_LINK_SPEED_10G)
2849 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2850 if (link_speed & ETH_LINK_SPEED_20G)
2851 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2852 if (link_speed & ETH_LINK_SPEED_25G)
2853 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2854 if (link_speed & ETH_LINK_SPEED_40G)
2855 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2856 if (link_speed & ETH_LINK_SPEED_50G)
2857 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2858 if (link_speed & ETH_LINK_SPEED_100G)
2859 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2860 if (link_speed & ETH_LINK_SPEED_200G)
2861 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2865 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2867 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2869 switch (hw_link_speed) {
2870 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2871 eth_link_speed = ETH_SPEED_NUM_100M;
2873 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2874 eth_link_speed = ETH_SPEED_NUM_1G;
2876 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2877 eth_link_speed = ETH_SPEED_NUM_2_5G;
2879 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2880 eth_link_speed = ETH_SPEED_NUM_10G;
2882 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2883 eth_link_speed = ETH_SPEED_NUM_20G;
2885 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2886 eth_link_speed = ETH_SPEED_NUM_25G;
2888 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2889 eth_link_speed = ETH_SPEED_NUM_40G;
2891 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2892 eth_link_speed = ETH_SPEED_NUM_50G;
2894 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2895 eth_link_speed = ETH_SPEED_NUM_100G;
2897 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2898 eth_link_speed = ETH_SPEED_NUM_200G;
2900 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2902 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2906 return eth_link_speed;
2909 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2911 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2913 switch (hw_link_duplex) {
2914 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2915 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2917 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2919 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2920 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2923 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2927 return eth_link_duplex;
2930 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2933 struct bnxt_link_info *link_info = bp->link_info;
2935 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2938 "Get link config failed with rc %d\n", rc);
2941 if (link_info->link_speed)
2943 bnxt_parse_hw_link_speed(link_info->link_speed);
2945 link->link_speed = ETH_SPEED_NUM_NONE;
2946 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2947 link->link_status = link_info->link_up;
2948 link->link_autoneg = link_info->auto_mode ==
2949 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2950 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2955 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2958 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2959 struct bnxt_link_info link_req;
2960 uint16_t speed, autoneg;
2962 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2965 rc = bnxt_validate_link_speed(bp);
2969 memset(&link_req, 0, sizeof(link_req));
2970 link_req.link_up = link_up;
2974 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2975 if (BNXT_CHIP_THOR(bp) &&
2976 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2977 /* 40G is not supported as part of media auto detect.
2978 * The speed should be forced and autoneg disabled
2979 * to configure 40G speed.
2981 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2985 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2986 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2987 /* Autoneg can be done only when the FW allows.
2988 * When user configures fixed speed of 40G and later changes to
2989 * any other speed, auto_link_speed/force_link_speed is still set
2990 * to 40G until link comes up at new speed.
2993 !(!BNXT_CHIP_THOR(bp) &&
2994 (bp->link_info->auto_link_speed ||
2995 bp->link_info->force_link_speed))) {
2996 link_req.phy_flags |=
2997 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2998 link_req.auto_link_speed_mask =
2999 bnxt_parse_eth_link_speed_mask(bp,
3000 dev_conf->link_speeds);
3002 if (bp->link_info->phy_type ==
3003 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3004 bp->link_info->phy_type ==
3005 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3006 bp->link_info->media_type ==
3007 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3008 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3012 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3013 /* If user wants a particular speed try that first. */
3015 link_req.link_speed = speed;
3016 else if (bp->link_info->force_link_speed)
3017 link_req.link_speed = bp->link_info->force_link_speed;
3019 link_req.link_speed = bp->link_info->auto_link_speed;
3021 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3022 link_req.auto_pause = bp->link_info->auto_pause;
3023 link_req.force_pause = bp->link_info->force_pause;
3026 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3029 "Set link config failed with rc %d\n", rc);
3037 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3039 struct hwrm_func_qcfg_input req = {0};
3040 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3043 bp->func_svif = BNXT_SVIF_INVALID;
3046 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3047 req.fid = rte_cpu_to_le_16(0xffff);
3049 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3051 HWRM_CHECK_RESULT();
3053 /* Hard Coded.. 0xfff VLAN ID mask */
3054 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3056 svif_info = rte_le_to_cpu_16(resp->svif_info);
3057 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3058 bp->func_svif = svif_info &
3059 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3061 flags = rte_le_to_cpu_16(resp->flags);
3062 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3063 bp->flags |= BNXT_FLAG_MULTI_HOST;
3066 !BNXT_VF_IS_TRUSTED(bp) &&
3067 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3068 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3069 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3070 } else if (BNXT_VF(bp) &&
3071 BNXT_VF_IS_TRUSTED(bp) &&
3072 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3073 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3074 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3078 *mtu = rte_le_to_cpu_16(resp->mtu);
3080 switch (resp->port_partition_type) {
3081 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3082 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3083 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3085 bp->flags |= BNXT_FLAG_NPAR_PF;
3088 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3097 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3098 uint16_t *vnic_id, uint16_t *svif)
3100 struct hwrm_func_qcfg_input req = {0};
3101 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3105 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3106 req.fid = rte_cpu_to_le_16(fid);
3108 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3110 HWRM_CHECK_RESULT();
3113 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3115 svif_info = rte_le_to_cpu_16(resp->svif_info);
3116 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3117 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3124 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3126 struct hwrm_port_mac_qcfg_input req = {0};
3127 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3128 uint16_t port_svif_info;
3131 bp->port_svif = BNXT_SVIF_INVALID;
3136 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3138 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3140 HWRM_CHECK_RESULT();
3142 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3143 if (port_svif_info &
3144 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3145 bp->port_svif = port_svif_info &
3146 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3153 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3154 struct hwrm_func_qcaps_output *qcaps)
3156 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3157 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3158 sizeof(qcaps->mac_address));
3159 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3160 qcaps->max_rx_rings = fcfg->num_rx_rings;
3161 qcaps->max_tx_rings = fcfg->num_tx_rings;
3162 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3163 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3165 qcaps->first_vf_id = 0;
3166 qcaps->max_vnics = fcfg->num_vnics;
3167 qcaps->max_decap_records = 0;
3168 qcaps->max_encap_records = 0;
3169 qcaps->max_tx_wm_flows = 0;
3170 qcaps->max_tx_em_flows = 0;
3171 qcaps->max_rx_wm_flows = 0;
3172 qcaps->max_rx_em_flows = 0;
3173 qcaps->max_flow_id = 0;
3174 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3175 qcaps->max_sp_tx_rings = 0;
3176 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3179 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3181 struct hwrm_func_cfg_input req = {0};
3182 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3186 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3187 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3188 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3189 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3190 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3191 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3192 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3193 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3194 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3196 if (BNXT_HAS_RING_GRPS(bp)) {
3197 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3198 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3199 } else if (BNXT_HAS_NQ(bp)) {
3200 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3201 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3204 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3205 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3206 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3207 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3208 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3209 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3210 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3211 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3212 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3213 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3214 req.fid = rte_cpu_to_le_16(0xffff);
3215 req.enables = rte_cpu_to_le_32(enables);
3217 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3219 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3221 HWRM_CHECK_RESULT();
3227 static void populate_vf_func_cfg_req(struct bnxt *bp,
3228 struct hwrm_func_cfg_input *req,
3231 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3232 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3233 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3234 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3235 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3236 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3237 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3238 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3239 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3240 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3242 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3243 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3245 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3246 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3248 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3249 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3251 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3252 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3253 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3254 /* TODO: For now, do not support VMDq/RFS on VFs. */
3255 req->num_vnics = rte_cpu_to_le_16(1);
3256 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3260 static void add_random_mac_if_needed(struct bnxt *bp,
3261 struct hwrm_func_cfg_input *cfg_req,
3264 struct rte_ether_addr mac;
3266 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3269 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3271 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3272 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3273 bp->pf->vf_info[vf].random_mac = true;
3275 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3276 RTE_ETHER_ADDR_LEN);
3280 static int reserve_resources_from_vf(struct bnxt *bp,
3281 struct hwrm_func_cfg_input *cfg_req,
3284 struct hwrm_func_qcaps_input req = {0};
3285 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3288 /* Get the actual allocated values now */
3289 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3290 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3291 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3294 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3295 copy_func_cfg_to_qcaps(cfg_req, resp);
3296 } else if (resp->error_code) {
3297 rc = rte_le_to_cpu_16(resp->error_code);
3298 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3299 copy_func_cfg_to_qcaps(cfg_req, resp);
3302 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3303 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3304 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3305 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3306 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3307 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3309 * TODO: While not supporting VMDq with VFs, max_vnics is always
3310 * forced to 1 in this case
3312 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3313 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3320 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3322 struct hwrm_func_qcfg_input req = {0};
3323 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3326 /* Check for zero MAC address */
3327 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3328 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3329 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3330 HWRM_CHECK_RESULT();
3331 rc = rte_le_to_cpu_16(resp->vlan);
3338 static int update_pf_resource_max(struct bnxt *bp)
3340 struct hwrm_func_qcfg_input req = {0};
3341 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3344 /* And copy the allocated numbers into the pf struct */
3345 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3346 req.fid = rte_cpu_to_le_16(0xffff);
3347 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3348 HWRM_CHECK_RESULT();
3350 /* Only TX ring value reflects actual allocation? TODO */
3351 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3352 bp->pf->evb_mode = resp->evb_mode;
3359 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3364 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3368 rc = bnxt_hwrm_func_qcaps(bp);
3372 bp->pf->func_cfg_flags &=
3373 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3374 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3375 bp->pf->func_cfg_flags |=
3376 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3377 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3378 rc = __bnxt_hwrm_func_qcaps(bp);
3382 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3384 struct hwrm_func_cfg_input req = {0};
3385 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3392 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3396 rc = bnxt_hwrm_func_qcaps(bp);
3401 bp->pf->active_vfs = num_vfs;
3404 * First, configure the PF to only use one TX ring. This ensures that
3405 * there are enough rings for all VFs.
3407 * If we don't do this, when we call func_alloc() later, we will lock
3408 * extra rings to the PF that won't be available during func_cfg() of
3411 * This has been fixed with firmware versions above 20.6.54
3413 bp->pf->func_cfg_flags &=
3414 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3415 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3416 bp->pf->func_cfg_flags |=
3417 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3418 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3423 * Now, create and register a buffer to hold forwarded VF requests
3425 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3426 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3427 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3428 if (bp->pf->vf_req_buf == NULL) {
3432 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3433 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3434 for (i = 0; i < num_vfs; i++)
3435 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3436 (i * HWRM_MAX_REQ_LEN);
3438 rc = bnxt_hwrm_func_buf_rgtr(bp);
3442 populate_vf_func_cfg_req(bp, &req, num_vfs);
3444 bp->pf->active_vfs = 0;
3445 for (i = 0; i < num_vfs; i++) {
3446 add_random_mac_if_needed(bp, &req, i);
3448 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3449 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3450 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3451 rc = bnxt_hwrm_send_message(bp,
3456 /* Clear enable flag for next pass */
3457 req.enables &= ~rte_cpu_to_le_32(
3458 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3460 if (rc || resp->error_code) {
3462 "Failed to initizlie VF %d\n", i);
3464 "Not all VFs available. (%d, %d)\n",
3465 rc, resp->error_code);
3472 reserve_resources_from_vf(bp, &req, i);
3473 bp->pf->active_vfs++;
3474 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3478 * Now configure the PF to use "the rest" of the resources
3479 * We're using STD_TX_RING_MODE here though which will limit the TX
3480 * rings. This will allow QoS to function properly. Not setting this
3481 * will cause PF rings to break bandwidth settings.
3483 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3487 rc = update_pf_resource_max(bp);
3494 bnxt_hwrm_func_buf_unrgtr(bp);
3498 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3500 struct hwrm_func_cfg_input req = {0};
3501 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3504 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3506 req.fid = rte_cpu_to_le_16(0xffff);
3507 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3508 req.evb_mode = bp->pf->evb_mode;
3510 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3511 HWRM_CHECK_RESULT();
3517 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3518 uint8_t tunnel_type)
3520 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3521 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3524 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3525 req.tunnel_type = tunnel_type;
3526 req.tunnel_dst_port_val = port;
3527 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3528 HWRM_CHECK_RESULT();
3530 switch (tunnel_type) {
3531 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3532 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3533 bp->vxlan_port = port;
3535 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3536 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3537 bp->geneve_port = port;
3548 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3549 uint8_t tunnel_type)
3551 struct hwrm_tunnel_dst_port_free_input req = {0};
3552 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3555 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3557 req.tunnel_type = tunnel_type;
3558 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3559 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3561 HWRM_CHECK_RESULT();
3567 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3570 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3571 struct hwrm_func_cfg_input req = {0};
3574 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3576 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3577 req.flags = rte_cpu_to_le_32(flags);
3578 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3580 HWRM_CHECK_RESULT();
3586 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3588 uint32_t *flag = flagp;
3590 vnic->flags = *flag;
3593 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3595 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3598 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3601 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3602 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3604 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3606 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3607 req.req_buf_page_size = rte_cpu_to_le_16(
3608 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3609 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3610 req.req_buf_page_addr0 =
3611 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3612 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3614 "unable to map buffer address to physical memory\n");
3618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3620 HWRM_CHECK_RESULT();
3626 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3629 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3630 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3632 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3635 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3639 HWRM_CHECK_RESULT();
3645 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3647 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3648 struct hwrm_func_cfg_input req = {0};
3651 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3653 req.fid = rte_cpu_to_le_16(0xffff);
3654 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3655 req.enables = rte_cpu_to_le_32(
3656 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3657 req.async_event_cr = rte_cpu_to_le_16(
3658 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3661 HWRM_CHECK_RESULT();
3667 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3669 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3670 struct hwrm_func_vf_cfg_input req = {0};
3673 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3675 req.enables = rte_cpu_to_le_32(
3676 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3677 req.async_event_cr = rte_cpu_to_le_16(
3678 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3679 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3681 HWRM_CHECK_RESULT();
3687 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3689 struct hwrm_func_cfg_input req = {0};
3690 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3691 uint16_t dflt_vlan, fid;
3692 uint32_t func_cfg_flags;
3695 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3698 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3699 fid = bp->pf->vf_info[vf].fid;
3700 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3702 fid = rte_cpu_to_le_16(0xffff);
3703 func_cfg_flags = bp->pf->func_cfg_flags;
3704 dflt_vlan = bp->vlan;
3707 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3708 req.fid = rte_cpu_to_le_16(fid);
3709 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3710 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3712 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3714 HWRM_CHECK_RESULT();
3720 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3721 uint16_t max_bw, uint16_t enables)
3723 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3724 struct hwrm_func_cfg_input req = {0};
3727 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3729 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3730 req.enables |= rte_cpu_to_le_32(enables);
3731 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3732 req.max_bw = rte_cpu_to_le_32(max_bw);
3733 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3735 HWRM_CHECK_RESULT();
3741 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3743 struct hwrm_func_cfg_input req = {0};
3744 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3747 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3749 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3750 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3751 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3752 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3754 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3756 HWRM_CHECK_RESULT();
3762 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3767 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3769 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3774 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3775 void *encaped, size_t ec_size)
3778 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3779 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3781 if (ec_size > sizeof(req.encap_request))
3784 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3786 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3787 memcpy(req.encap_request, encaped, ec_size);
3789 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3791 HWRM_CHECK_RESULT();
3797 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3798 struct rte_ether_addr *mac)
3800 struct hwrm_func_qcfg_input req = {0};
3801 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3804 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3806 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3807 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3809 HWRM_CHECK_RESULT();
3811 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3818 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3819 void *encaped, size_t ec_size)
3822 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3823 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3825 if (ec_size > sizeof(req.encap_request))
3828 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3830 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3831 memcpy(req.encap_request, encaped, ec_size);
3833 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3835 HWRM_CHECK_RESULT();
3841 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3842 struct rte_eth_stats *stats, uint8_t rx)
3845 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3846 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3848 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3850 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3852 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3854 HWRM_CHECK_RESULT();
3857 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3858 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3859 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3860 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3861 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3862 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3863 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3864 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3866 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3867 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3868 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3869 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3870 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3871 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3879 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3881 struct hwrm_port_qstats_input req = {0};
3882 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3883 struct bnxt_pf_info *pf = bp->pf;
3886 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3888 req.port_id = rte_cpu_to_le_16(pf->port_id);
3889 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3890 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3891 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3893 HWRM_CHECK_RESULT();
3899 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3901 struct hwrm_port_clr_stats_input req = {0};
3902 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3903 struct bnxt_pf_info *pf = bp->pf;
3906 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3907 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3908 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3911 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3913 req.port_id = rte_cpu_to_le_16(pf->port_id);
3914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3916 HWRM_CHECK_RESULT();
3922 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3924 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3925 struct hwrm_port_led_qcaps_input req = {0};
3931 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3932 req.port_id = bp->pf->port_id;
3933 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3935 HWRM_CHECK_RESULT();
3937 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3940 bp->leds->num_leds = resp->num_leds;
3941 memcpy(bp->leds, &resp->led0_id,
3942 sizeof(bp->leds[0]) * bp->leds->num_leds);
3943 for (i = 0; i < bp->leds->num_leds; i++) {
3944 struct bnxt_led_info *led = &bp->leds[i];
3946 uint16_t caps = led->led_state_caps;
3948 if (!led->led_group_id ||
3949 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3950 bp->leds->num_leds = 0;
3961 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3963 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3964 struct hwrm_port_led_cfg_input req = {0};
3965 struct bnxt_led_cfg *led_cfg;
3966 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3967 uint16_t duration = 0;
3970 if (!bp->leds->num_leds || BNXT_VF(bp))
3973 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3976 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3977 duration = rte_cpu_to_le_16(500);
3979 req.port_id = bp->pf->port_id;
3980 req.num_leds = bp->leds->num_leds;
3981 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3982 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
3983 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3984 led_cfg->led_id = bp->leds[i].led_id;
3985 led_cfg->led_state = led_state;
3986 led_cfg->led_blink_on = duration;
3987 led_cfg->led_blink_off = duration;
3988 led_cfg->led_group_id = bp->leds[i].led_group_id;
3991 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3993 HWRM_CHECK_RESULT();
3999 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4003 struct hwrm_nvm_get_dir_info_input req = {0};
4004 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4006 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4008 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4010 HWRM_CHECK_RESULT();
4012 *entries = rte_le_to_cpu_32(resp->entries);
4013 *length = rte_le_to_cpu_32(resp->entry_length);
4019 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4022 uint32_t dir_entries;
4023 uint32_t entry_length;
4026 rte_iova_t dma_handle;
4027 struct hwrm_nvm_get_dir_entries_input req = {0};
4028 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4030 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4034 *data++ = dir_entries;
4035 *data++ = entry_length;
4037 memset(data, 0xff, len);
4039 buflen = dir_entries * entry_length;
4040 buf = rte_malloc("nvm_dir", buflen, 0);
4043 dma_handle = rte_malloc_virt2iova(buf);
4044 if (dma_handle == RTE_BAD_IOVA) {
4046 "unable to map response address to physical memory\n");
4049 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4050 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4051 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4054 memcpy(data, buf, len > buflen ? buflen : len);
4057 HWRM_CHECK_RESULT();
4063 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4064 uint32_t offset, uint32_t length,
4069 rte_iova_t dma_handle;
4070 struct hwrm_nvm_read_input req = {0};
4071 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4073 buf = rte_malloc("nvm_item", length, 0);
4077 dma_handle = rte_malloc_virt2iova(buf);
4078 if (dma_handle == RTE_BAD_IOVA) {
4080 "unable to map response address to physical memory\n");
4083 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4084 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4085 req.dir_idx = rte_cpu_to_le_16(index);
4086 req.offset = rte_cpu_to_le_32(offset);
4087 req.len = rte_cpu_to_le_32(length);
4088 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4090 memcpy(data, buf, length);
4093 HWRM_CHECK_RESULT();
4099 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4102 struct hwrm_nvm_erase_dir_entry_input req = {0};
4103 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4105 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4106 req.dir_idx = rte_cpu_to_le_16(index);
4107 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4108 HWRM_CHECK_RESULT();
4115 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4116 uint16_t dir_ordinal, uint16_t dir_ext,
4117 uint16_t dir_attr, const uint8_t *data,
4121 struct hwrm_nvm_write_input req = {0};
4122 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4123 rte_iova_t dma_handle;
4126 buf = rte_malloc("nvm_write", data_len, 0);
4130 dma_handle = rte_malloc_virt2iova(buf);
4131 if (dma_handle == RTE_BAD_IOVA) {
4133 "unable to map response address to physical memory\n");
4136 memcpy(buf, data, data_len);
4138 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4140 req.dir_type = rte_cpu_to_le_16(dir_type);
4141 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4142 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4143 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4144 req.dir_data_length = rte_cpu_to_le_32(data_len);
4145 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4147 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4150 HWRM_CHECK_RESULT();
4157 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4159 uint32_t *count = cbdata;
4161 *count = *count + 1;
4164 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4165 struct bnxt_vnic_info *vnic __rte_unused)
4170 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4174 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4175 &count, bnxt_vnic_count_hwrm_stub);
4180 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4183 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4184 struct hwrm_func_vf_vnic_ids_query_output *resp =
4185 bp->hwrm_cmd_resp_addr;
4188 /* First query all VNIC ids */
4189 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4191 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4192 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4193 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4195 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4198 "unable to map VNIC ID table address to physical memory\n");
4201 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4202 HWRM_CHECK_RESULT();
4203 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4211 * This function queries the VNIC IDs for a specified VF. It then calls
4212 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4213 * Then it calls the hwrm_cb function to program this new vnic configuration.
4215 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4216 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4217 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4219 struct bnxt_vnic_info vnic;
4221 int i, num_vnic_ids;
4226 /* First query all VNIC ids */
4227 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4228 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4229 RTE_CACHE_LINE_SIZE);
4230 if (vnic_ids == NULL)
4233 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4234 rte_mem_lock_page(((char *)vnic_ids) + sz);
4236 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4238 if (num_vnic_ids < 0)
4239 return num_vnic_ids;
4241 /* Retrieve VNIC, update bd_stall then update */
4243 for (i = 0; i < num_vnic_ids; i++) {
4244 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4245 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4246 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4249 if (vnic.mru <= 4) /* Indicates unallocated */
4252 vnic_cb(&vnic, cbdata);
4254 rc = hwrm_cb(bp, &vnic);
4264 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4267 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4268 struct hwrm_func_cfg_input req = {0};
4271 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4273 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4274 req.enables |= rte_cpu_to_le_32(
4275 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4276 req.vlan_antispoof_mode = on ?
4277 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4278 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4279 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4281 HWRM_CHECK_RESULT();
4287 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4289 struct bnxt_vnic_info vnic;
4292 int num_vnic_ids, i;
4296 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4297 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4298 RTE_CACHE_LINE_SIZE);
4299 if (vnic_ids == NULL)
4302 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4303 rte_mem_lock_page(((char *)vnic_ids) + sz);
4305 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4311 * Loop through to find the default VNIC ID.
4312 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4313 * by sending the hwrm_func_qcfg command to the firmware.
4315 for (i = 0; i < num_vnic_ids; i++) {
4316 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4317 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4318 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4319 bp->pf->first_vf_id + vf);
4322 if (vnic.func_default) {
4324 return vnic.fw_vnic_id;
4327 /* Could not find a default VNIC. */
4328 PMD_DRV_LOG(ERR, "No default VNIC\n");
4334 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4336 struct bnxt_filter_info *filter)
4339 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4340 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4341 uint32_t enables = 0;
4343 if (filter->fw_em_filter_id != UINT64_MAX)
4344 bnxt_hwrm_clear_em_filter(bp, filter);
4346 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4348 req.flags = rte_cpu_to_le_32(filter->flags);
4350 enables = filter->enables |
4351 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4352 req.dst_id = rte_cpu_to_le_16(dst_id);
4354 if (filter->ip_addr_type) {
4355 req.ip_addr_type = filter->ip_addr_type;
4356 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4359 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4360 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4362 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4363 memcpy(req.src_macaddr, filter->src_macaddr,
4364 RTE_ETHER_ADDR_LEN);
4366 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4367 memcpy(req.dst_macaddr, filter->dst_macaddr,
4368 RTE_ETHER_ADDR_LEN);
4370 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4371 req.ovlan_vid = filter->l2_ovlan;
4373 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4374 req.ivlan_vid = filter->l2_ivlan;
4376 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4377 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4379 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4380 req.ip_protocol = filter->ip_protocol;
4382 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4383 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4385 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4386 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4388 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4389 req.src_port = rte_cpu_to_be_16(filter->src_port);
4391 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4392 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4394 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4395 req.mirror_vnic_id = filter->mirror_vnic_id;
4397 req.enables = rte_cpu_to_le_32(enables);
4399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4401 HWRM_CHECK_RESULT();
4403 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4409 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4412 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4413 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4415 if (filter->fw_em_filter_id == UINT64_MAX)
4418 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4420 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4422 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4424 HWRM_CHECK_RESULT();
4427 filter->fw_em_filter_id = UINT64_MAX;
4428 filter->fw_l2_filter_id = UINT64_MAX;
4433 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4435 struct bnxt_filter_info *filter)
4438 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4439 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4440 bp->hwrm_cmd_resp_addr;
4441 uint32_t enables = 0;
4443 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4444 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4446 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4448 req.flags = rte_cpu_to_le_32(filter->flags);
4450 enables = filter->enables |
4451 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4452 req.dst_id = rte_cpu_to_le_16(dst_id);
4454 if (filter->ip_addr_type) {
4455 req.ip_addr_type = filter->ip_addr_type;
4457 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4460 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4461 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4463 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4464 memcpy(req.src_macaddr, filter->src_macaddr,
4465 RTE_ETHER_ADDR_LEN);
4467 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4468 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4470 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4471 req.ip_protocol = filter->ip_protocol;
4473 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4474 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4476 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4477 req.src_ipaddr_mask[0] =
4478 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4480 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4481 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4483 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4484 req.dst_ipaddr_mask[0] =
4485 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4487 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4488 req.src_port = rte_cpu_to_le_16(filter->src_port);
4490 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4491 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4493 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4494 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4496 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4497 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4499 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4500 req.mirror_vnic_id = filter->mirror_vnic_id;
4502 req.enables = rte_cpu_to_le_32(enables);
4504 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4506 HWRM_CHECK_RESULT();
4508 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4509 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4515 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4516 struct bnxt_filter_info *filter)
4519 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4520 struct hwrm_cfa_ntuple_filter_free_output *resp =
4521 bp->hwrm_cmd_resp_addr;
4523 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4526 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4528 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4530 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4532 HWRM_CHECK_RESULT();
4535 filter->fw_ntuple_filter_id = UINT64_MAX;
4541 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4543 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4544 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4545 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4546 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4547 uint16_t *ring_tbl = vnic->rss_table;
4548 int nr_ctxs = vnic->num_lb_ctxts;
4549 int max_rings = bp->rx_nr_rings;
4553 for (i = 0, k = 0; i < nr_ctxs; i++) {
4554 struct bnxt_rx_ring_info *rxr;
4555 struct bnxt_cp_ring_info *cpr;
4557 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4559 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4560 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4561 req.hash_mode_flags = vnic->hash_mode;
4563 req.ring_grp_tbl_addr =
4564 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4565 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4566 2 * sizeof(*ring_tbl));
4567 req.hash_key_tbl_addr =
4568 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4570 req.ring_table_pair_index = i;
4571 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4573 for (j = 0; j < 64; j++) {
4576 /* Find next active ring. */
4577 for (cnt = 0; cnt < max_rings; cnt++) {
4578 if (rx_queue_state[k] !=
4579 RTE_ETH_QUEUE_STATE_STOPPED)
4581 if (++k == max_rings)
4585 /* Return if no rings are active. */
4586 if (cnt == max_rings) {
4591 /* Add rx/cp ring pair to RSS table. */
4592 rxr = rxqs[k]->rx_ring;
4593 cpr = rxqs[k]->cp_ring;
4595 ring_id = rxr->rx_ring_struct->fw_ring_id;
4596 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4597 ring_id = cpr->cp_ring_struct->fw_ring_id;
4598 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4600 if (++k == max_rings)
4603 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4606 HWRM_CHECK_RESULT();
4613 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4615 unsigned int rss_idx, fw_idx, i;
4617 if (!(vnic->rss_table && vnic->hash_type))
4620 if (BNXT_CHIP_THOR(bp))
4621 return bnxt_vnic_rss_configure_thor(bp, vnic);
4623 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4626 if (vnic->rss_table && vnic->hash_type) {
4628 * Fill the RSS hash & redirection table with
4629 * ring group ids for all VNICs
4631 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4632 rss_idx++, fw_idx++) {
4633 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4634 fw_idx %= bp->rx_cp_nr_rings;
4635 if (vnic->fw_grp_ids[fw_idx] !=
4640 if (i == bp->rx_cp_nr_rings)
4642 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4644 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4650 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4651 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4655 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4657 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4658 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4660 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4661 req->num_cmpl_dma_aggr_during_int =
4662 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4664 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4666 /* min timer set to 1/2 of interrupt timer */
4667 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4669 /* buf timer set to 1/4 of interrupt timer */
4670 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4672 req->cmpl_aggr_dma_tmr_during_int =
4673 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4675 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4676 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4677 req->flags = rte_cpu_to_le_16(flags);
4680 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4681 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4683 struct hwrm_ring_aggint_qcaps_input req = {0};
4684 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4689 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4690 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4691 HWRM_CHECK_RESULT();
4693 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4694 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4696 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4697 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4698 agg_req->flags = rte_cpu_to_le_16(flags);
4700 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4701 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4702 agg_req->enables = rte_cpu_to_le_32(enables);
4708 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4709 struct bnxt_coal *coal, uint16_t ring_id)
4711 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4712 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4713 bp->hwrm_cmd_resp_addr;
4716 /* Set ring coalesce parameters only for 100G NICs */
4717 if (BNXT_CHIP_THOR(bp)) {
4718 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4720 } else if (bnxt_stratus_device(bp)) {
4721 bnxt_hwrm_set_coal_params(coal, &req);
4727 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4729 req.ring_id = rte_cpu_to_le_16(ring_id);
4730 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4731 HWRM_CHECK_RESULT();
4736 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4737 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4739 struct hwrm_func_backing_store_qcaps_input req = {0};
4740 struct hwrm_func_backing_store_qcaps_output *resp =
4741 bp->hwrm_cmd_resp_addr;
4742 struct bnxt_ctx_pg_info *ctx_pg;
4743 struct bnxt_ctx_mem_info *ctx;
4744 int total_alloc_len;
4745 int rc, i, tqm_rings;
4747 if (!BNXT_CHIP_THOR(bp) ||
4748 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4753 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4754 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4755 HWRM_CHECK_RESULT_SILENT();
4757 total_alloc_len = sizeof(*ctx);
4758 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4759 RTE_CACHE_LINE_SIZE);
4765 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4766 ctx->qp_min_qp1_entries =
4767 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4768 ctx->qp_max_l2_entries =
4769 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4770 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4771 ctx->srq_max_l2_entries =
4772 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4773 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4774 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4775 ctx->cq_max_l2_entries =
4776 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4777 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4778 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4779 ctx->vnic_max_vnic_entries =
4780 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4781 ctx->vnic_max_ring_table_entries =
4782 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4783 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4784 ctx->stat_max_entries =
4785 rte_le_to_cpu_32(resp->stat_max_entries);
4786 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4787 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4788 ctx->tqm_min_entries_per_ring =
4789 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4790 ctx->tqm_max_entries_per_ring =
4791 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4792 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4793 if (!ctx->tqm_entries_multiple)
4794 ctx->tqm_entries_multiple = 1;
4795 ctx->mrav_max_entries =
4796 rte_le_to_cpu_32(resp->mrav_max_entries);
4797 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4798 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4799 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4800 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4802 if (!ctx->tqm_fp_rings_count)
4803 ctx->tqm_fp_rings_count = bp->max_q;
4805 tqm_rings = ctx->tqm_fp_rings_count + 1;
4807 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4808 sizeof(*ctx_pg) * tqm_rings,
4809 RTE_CACHE_LINE_SIZE);
4814 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4815 ctx->tqm_mem[i] = ctx_pg;
4823 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4825 struct hwrm_func_backing_store_cfg_input req = {0};
4826 struct hwrm_func_backing_store_cfg_output *resp =
4827 bp->hwrm_cmd_resp_addr;
4828 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4829 struct bnxt_ctx_pg_info *ctx_pg;
4830 uint32_t *num_entries;
4839 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4840 req.enables = rte_cpu_to_le_32(enables);
4842 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4843 ctx_pg = &ctx->qp_mem;
4844 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4845 req.qp_num_qp1_entries =
4846 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4847 req.qp_num_l2_entries =
4848 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4849 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4850 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4851 &req.qpc_pg_size_qpc_lvl,
4855 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4856 ctx_pg = &ctx->srq_mem;
4857 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4858 req.srq_num_l2_entries =
4859 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4860 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4861 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4862 &req.srq_pg_size_srq_lvl,
4866 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4867 ctx_pg = &ctx->cq_mem;
4868 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4869 req.cq_num_l2_entries =
4870 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4871 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4872 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4873 &req.cq_pg_size_cq_lvl,
4877 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4878 ctx_pg = &ctx->vnic_mem;
4879 req.vnic_num_vnic_entries =
4880 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4881 req.vnic_num_ring_table_entries =
4882 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4883 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4884 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4885 &req.vnic_pg_size_vnic_lvl,
4886 &req.vnic_page_dir);
4889 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4890 ctx_pg = &ctx->stat_mem;
4891 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4892 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4893 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4894 &req.stat_pg_size_stat_lvl,
4895 &req.stat_page_dir);
4898 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4899 num_entries = &req.tqm_sp_num_entries;
4900 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4901 pg_dir = &req.tqm_sp_page_dir;
4902 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4903 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4904 if (!(enables & ena))
4907 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4909 ctx_pg = ctx->tqm_mem[i];
4910 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4911 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4914 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4915 HWRM_CHECK_RESULT();
4921 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4923 struct hwrm_port_qstats_ext_input req = {0};
4924 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4925 struct bnxt_pf_info *pf = bp->pf;
4928 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4929 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4932 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4934 req.port_id = rte_cpu_to_le_16(pf->port_id);
4935 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4936 req.tx_stat_host_addr =
4937 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4939 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4941 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4942 req.rx_stat_host_addr =
4943 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4945 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4947 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4950 bp->fw_rx_port_stats_ext_size = 0;
4951 bp->fw_tx_port_stats_ext_size = 0;
4953 bp->fw_rx_port_stats_ext_size =
4954 rte_le_to_cpu_16(resp->rx_stat_size);
4955 bp->fw_tx_port_stats_ext_size =
4956 rte_le_to_cpu_16(resp->tx_stat_size);
4959 HWRM_CHECK_RESULT();
4966 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4968 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4969 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4970 bp->hwrm_cmd_resp_addr;
4973 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4974 req.tunnel_type = type;
4975 req.dest_fid = bp->fw_fid;
4976 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4977 HWRM_CHECK_RESULT();
4985 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4987 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4988 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4989 bp->hwrm_cmd_resp_addr;
4992 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4993 req.tunnel_type = type;
4994 req.dest_fid = bp->fw_fid;
4995 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4996 HWRM_CHECK_RESULT();
5003 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5005 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5006 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5007 bp->hwrm_cmd_resp_addr;
5010 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5011 req.src_fid = bp->fw_fid;
5012 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5013 HWRM_CHECK_RESULT();
5016 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5023 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5026 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5027 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5028 bp->hwrm_cmd_resp_addr;
5031 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5032 req.src_fid = bp->fw_fid;
5033 req.tunnel_type = tun_type;
5034 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5035 HWRM_CHECK_RESULT();
5038 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5040 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5047 int bnxt_hwrm_set_mac(struct bnxt *bp)
5049 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5050 struct hwrm_func_vf_cfg_input req = {0};
5056 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5059 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5060 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5062 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5064 HWRM_CHECK_RESULT();
5071 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5073 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5074 struct hwrm_func_drv_if_change_input req = {0};
5078 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5081 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5082 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5083 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5085 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5088 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5092 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5094 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5096 HWRM_CHECK_RESULT();
5097 flags = rte_le_to_cpu_32(resp->flags);
5103 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5104 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5105 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5111 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5113 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5114 struct bnxt_error_recovery_info *info = bp->recovery_info;
5115 struct hwrm_error_recovery_qcfg_input req = {0};
5120 /* Older FW does not have error recovery support */
5121 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5124 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5126 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5128 HWRM_CHECK_RESULT();
5130 flags = rte_le_to_cpu_32(resp->flags);
5131 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5132 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5133 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5134 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5136 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5137 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5142 /* FW returned values are in units of 100msec */
5143 info->driver_polling_freq =
5144 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5145 info->master_func_wait_period =
5146 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5147 info->normal_func_wait_period =
5148 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5149 info->master_func_wait_period_after_reset =
5150 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5151 info->max_bailout_time_after_reset =
5152 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5153 info->status_regs[BNXT_FW_STATUS_REG] =
5154 rte_le_to_cpu_32(resp->fw_health_status_reg);
5155 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5156 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5157 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5158 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5159 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5160 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5161 info->reg_array_cnt =
5162 rte_le_to_cpu_32(resp->reg_array_cnt);
5164 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5169 for (i = 0; i < info->reg_array_cnt; i++) {
5170 info->reset_reg[i] =
5171 rte_le_to_cpu_32(resp->reset_reg[i]);
5172 info->reset_reg_val[i] =
5173 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5174 info->delay_after_reset[i] =
5175 resp->delay_after_reset[i];
5180 /* Map the FW status registers */
5182 rc = bnxt_map_fw_health_status_regs(bp);
5185 rte_free(bp->recovery_info);
5186 bp->recovery_info = NULL;
5191 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5193 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5194 struct hwrm_fw_reset_input req = {0};
5200 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5202 req.embedded_proc_type =
5203 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5204 req.selfrst_status =
5205 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5206 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5208 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5211 HWRM_CHECK_RESULT();
5217 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5219 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5220 struct hwrm_port_ts_query_input req = {0};
5221 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5228 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5231 case BNXT_PTP_FLAGS_PATH_TX:
5232 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5234 case BNXT_PTP_FLAGS_PATH_RX:
5235 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5237 case BNXT_PTP_FLAGS_CURRENT_TIME:
5238 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5242 req.flags = rte_cpu_to_le_32(flags);
5243 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5247 HWRM_CHECK_RESULT();
5250 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5252 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5259 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5261 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5262 bp->hwrm_cmd_resp_addr;
5263 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5267 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5270 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5272 "Not a PF or trusted VF. Command not supported\n");
5276 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5277 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5279 HWRM_CHECK_RESULT();
5280 flags = rte_le_to_cpu_32(resp->flags);
5283 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5284 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5285 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5291 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5295 struct hwrm_cfa_counter_qcaps_input req = {0};
5296 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5298 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5300 "Not a PF or trusted VF. Command not supported\n");
5304 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5305 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5306 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5308 HWRM_CHECK_RESULT();
5310 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5316 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5319 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5320 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5322 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5324 "Not a PF or trusted VF. Command not supported\n");
5328 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5330 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5331 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5332 req.page_dir = rte_cpu_to_le_64(dma_addr);
5334 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5336 HWRM_CHECK_RESULT();
5338 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5339 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5346 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5349 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5350 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5352 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5354 "Not a PF or trusted VF. Command not supported\n");
5358 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5360 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5362 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5364 HWRM_CHECK_RESULT();
5370 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5371 uint16_t cntr, uint16_t ctx_id,
5372 uint32_t num_entries, bool enable)
5374 struct hwrm_cfa_counter_cfg_input req = {0};
5375 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5379 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5381 "Not a PF or trusted VF. Command not supported\n");
5385 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5387 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5388 req.counter_type = rte_cpu_to_le_16(cntr);
5389 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5390 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5391 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5392 if (dir == BNXT_DIR_RX)
5393 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5394 else if (dir == BNXT_DIR_TX)
5395 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5396 req.flags = rte_cpu_to_le_16(flags);
5397 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5398 req.num_entries = rte_cpu_to_le_32(num_entries);
5400 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5401 HWRM_CHECK_RESULT();
5407 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5408 enum bnxt_flow_dir dir,
5410 uint16_t num_entries)
5412 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5413 struct hwrm_cfa_counter_qstats_input req = {0};
5414 uint16_t flow_ctx_id = 0;
5418 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5420 "Not a PF or trusted VF. Command not supported\n");
5424 if (dir == BNXT_DIR_RX) {
5425 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5426 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5427 } else if (dir == BNXT_DIR_TX) {
5428 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5429 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5432 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5433 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5434 req.counter_type = rte_cpu_to_le_16(cntr);
5435 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5436 req.num_entries = rte_cpu_to_le_16(num_entries);
5437 req.flags = rte_cpu_to_le_16(flags);
5438 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5440 HWRM_CHECK_RESULT();