drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SHORT_CMD_TIMEOUT          50000
  31 #define HWRM_SPEC_CODE_1_8_3            0x10803
  32 #define HWRM_VERSION_1_9_1              0x10901
  33 #define HWRM_VERSION_1_9_2              0x10903
  34
  35 struct bnxt_plcmodes_cfg {
  36         uint32_t        flags;
  37         uint16_t        jumbo_thresh;
  38         uint16_t        hds_offset;
  39         uint16_t        hds_threshold;
  40 };
  41
  42 static int page_getenum(size_t size)
  43 {
  44         if (size <= 1 << 4)
  45                 return 4;
  46         if (size <= 1 << 12)
  47                 return 12;
  48         if (size <= 1 << 13)
  49                 return 13;
  50         if (size <= 1 << 16)
  51                 return 16;
  52         if (size <= 1 << 21)
  53                 return 21;
  54         if (size <= 1 << 22)
  55                 return 22;
  56         if (size <= 1 << 30)
  57                 return 30;
  58         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  59         return sizeof(void *) * 8 - 1;
  60 }
  61
  62 static int page_roundup(size_t size)
  63 {
  64         return 1 << page_getenum(size);
  65 }
  66
  67 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  68                                   uint8_t *pg_attr,
  69                                   uint64_t *pg_dir)
  70 {
  71         if (rmem->nr_pages > 1) {
  72                 *pg_attr = 1;
  73                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  74         } else {
  75                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  76         }
  77 }
  78
  79 /*
  80  * HWRM Functions (sent to HWRM)
  81  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  82  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  83  * command was failed by the ChiMP.
  84  */
  85
  86 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  87                                   uint32_t msg_len, bool use_kong_mb)
  88 {
  89         unsigned int i;
  90         struct input *req = msg;
  91         struct output *resp = bp->hwrm_cmd_resp_addr;
  92         uint32_t *data = msg;
  93         uint8_t *bar;
  94         uint8_t *valid;
  95         uint16_t max_req_len = bp->max_req_len;
  96         struct hwrm_short_input short_input = { 0 };
  97         uint16_t bar_offset = use_kong_mb ?
  98                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  99         uint16_t mb_trigger_offset = use_kong_mb ?
 100                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 101         uint32_t timeout;
 102
 103         /* Do not send HWRM commands to firmware in error state */
 104         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 105                 return 0;
 106
 107         /* For VER_GET command, set timeout as 50ms */
 108         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 109                 timeout = HWRM_SHORT_CMD_TIMEOUT;
 110         else
 111                 timeout = HWRM_CMD_TIMEOUT;
 112
 113         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 114             msg_len > bp->max_req_len) {
 115                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 116
 117                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 118                 memcpy(short_cmd_req, req, msg_len);
 119
 120                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 121                 short_input.signature = rte_cpu_to_le_16(
 122                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 123                 short_input.size = rte_cpu_to_le_16(msg_len);
 124                 short_input.req_addr =
 125                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 126
 127                 data = (uint32_t *)&short_input;
 128                 msg_len = sizeof(short_input);
 129
 130                 /* Sync memory write before updating doorbell */
 131                 rte_wmb();
 132
 133                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 134         }
 135
 136         /* Write request msg to hwrm channel */
 137         for (i = 0; i < msg_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(*data, bar);
 140                 data++;
 141         }
 142
 143         /* Zero the rest of the request space */
 144         for (; i < max_req_len; i += 4) {
 145                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 146                 rte_write32(0, bar);
 147         }
 148
 149         /* Ring channel doorbell */
 150         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 151         rte_write32(1, bar);
 152
 153         /* Poll for the valid bit */
 154         for (i = 0; i < timeout; i++) {
 155                 /* Sanity check on the resp->resp_len */
 156                 rte_rmb();
 157                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 158                         /* Last byte of resp contains the valid key */
 159                         valid = (uint8_t *)resp + resp->resp_len - 1;
 160                         if (*valid == HWRM_RESP_VALID_KEY)
 161                                 break;
 162                 }
 163                 rte_delay_us(1);
 164         }
 165
 166         if (i >= timeout) {
 167                 /* Suppress VER_GET timeout messages during reset recovery */
 168                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 169                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 170                         return -ETIMEDOUT;
 171
 172                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 173                             req->req_type);
 174                 return -ETIMEDOUT;
 175         }
 176         return 0;
 177 }
 178
 179 /*
 180  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 181  * spinlock, and does initial processing.
 182  *
 183  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 184  * releases the spinlock only if it returns.  If the regular int return codes
 185  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 186  * directly, rather it should be copied and modified to suit the function.
 187  *
 188  * HWRM_UNLOCK() must be called after all response processing is completed.
 189  */
 190 #define HWRM_PREP(req, type, kong) do { \
 191         rte_spinlock_lock(&bp->hwrm_lock); \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 194         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 195         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 197         req.target_id = rte_cpu_to_le_16(0xffff); \
 198         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc > 0) \
 220                         rc = -EINVAL; \
 221                 return rc; \
 222         } \
 223         if (resp->error_code) { \
 224                 rc = rte_le_to_cpu_16(resp->error_code); \
 225                 if (resp->resp_len >= 16) { \
 226                         struct hwrm_err_output *tmp_hwrm_err_op = \
 227                                                 (void *)resp; \
 228                         PMD_DRV_LOG(ERR, \
 229                                 "error %d:%d:%08x:%04x\n", \
 230                                 rc, tmp_hwrm_err_op->cmd_err, \
 231                                 rte_le_to_cpu_32(\
 232                                         tmp_hwrm_err_op->opaque_0), \
 233                                 rte_le_to_cpu_16(\
 234                                         tmp_hwrm_err_op->opaque_1)); \
 235                 } else { \
 236                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 237                 } \
 238                 rte_spinlock_unlock(&bp->hwrm_lock); \
 239                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 240                         rc = -EACCES; \
 241                 else if (rc > 0) \
 242                         rc = -EINVAL; \
 243                 return rc; \
 244         } \
 245 } while (0)
 246
 247 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 248
 249 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 250 {
 251         int rc = 0;
 252         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 253         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 254
 255         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 257         req.mask = 0;
 258
 259         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 260
 261         HWRM_CHECK_RESULT();
 262         HWRM_UNLOCK();
 263
 264         return rc;
 265 }
 266
 267 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 268                                  struct bnxt_vnic_info *vnic,
 269                                  uint16_t vlan_count,
 270                                  struct bnxt_vlan_table_entry *vlan_table)
 271 {
 272         int rc = 0;
 273         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 274         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 275         uint32_t mask = 0;
 276
 277         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 278                 return rc;
 279
 280         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 281         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 282
 283         /* FIXME add multicast flag, when multicast adding options is supported
 284          * by ethtool.
 285          */
 286         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 287                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 288         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 289                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 290         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 291                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 292         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 293                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 294         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 296         if (vnic->mc_addr_cnt) {
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 298                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 299                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 300         }
 301         if (vlan_table) {
 302                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 303                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 304                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 305                          rte_mem_virt2iova(vlan_table));
 306                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 307         }
 308         req.mask = rte_cpu_to_le_32(mask);
 309
 310         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 311
 312         HWRM_CHECK_RESULT();
 313         HWRM_UNLOCK();
 314
 315         return rc;
 316 }
 317
 318 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 319                         uint16_t vlan_count,
 320                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 321 {
 322         int rc = 0;
 323         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 324         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 325                                                 bp->hwrm_cmd_resp_addr;
 326
 327         /*
 328          * Older HWRM versions did not support this command, and the set_rx_mask
 329          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 330          * removed from set_rx_mask call, and this command was added.
 331          *
 332          * This command is also present from 1.7.8.11 and higher,
 333          * as well as 1.7.8.0
 334          */
 335         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 336                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 337                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 338                                         (11)))
 339                                 return 0;
 340                 }
 341         }
 342         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 343         req.fid = rte_cpu_to_le_16(fid);
 344
 345         req.vlan_tag_mask_tbl_addr =
 346                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 347         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 348
 349         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 350
 351         HWRM_CHECK_RESULT();
 352         HWRM_UNLOCK();
 353
 354         return rc;
 355 }
 356
 357 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 358                            struct bnxt_filter_info *filter)
 359 {
 360         int rc = 0;
 361         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 362         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 363
 364         if (filter->fw_l2_filter_id == UINT64_MAX)
 365                 return 0;
 366
 367         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 368
 369         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 370
 371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 372
 373         HWRM_CHECK_RESULT();
 374         HWRM_UNLOCK();
 375
 376         filter->fw_l2_filter_id = UINT64_MAX;
 377
 378         return 0;
 379 }
 380
 381 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 382                          uint16_t dst_id,
 383                          struct bnxt_filter_info *filter)
 384 {
 385         int rc = 0;
 386         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 387         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 388         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 389         const struct rte_eth_vmdq_rx_conf *conf =
 390                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 391         uint32_t enables = 0;
 392         uint16_t j = dst_id - 1;
 393
 394         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 395         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 396             conf->pool_map[j].pools & (1UL << j)) {
 397                 PMD_DRV_LOG(DEBUG,
 398                         "Add vlan %u to vmdq pool %u\n",
 399                         conf->pool_map[j].vlan_id, j);
 400
 401                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 402                 filter->enables |=
 403                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 404                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 405         }
 406
 407         if (filter->fw_l2_filter_id != UINT64_MAX)
 408                 bnxt_hwrm_clear_l2_filter(bp, filter);
 409
 410         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 411
 412         req.flags = rte_cpu_to_le_32(filter->flags);
 413         req.flags |=
 414         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 415
 416         enables = filter->enables |
 417               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 418         req.dst_id = rte_cpu_to_le_16(dst_id);
 419
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 422                 memcpy(req.l2_addr, filter->l2_addr,
 423                        RTE_ETHER_ADDR_LEN);
 424         if (enables &
 425             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 426                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 427                        RTE_ETHER_ADDR_LEN);
 428         if (enables &
 429             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 430                 req.l2_ovlan = filter->l2_ovlan;
 431         if (enables &
 432             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 433                 req.l2_ivlan = filter->l2_ivlan;
 434         if (enables &
 435             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 436                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 437         if (enables &
 438             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 439                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 440         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 441                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 442         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 443                 req.src_type = filter->src_type;
 444
 445         req.enables = rte_cpu_to_le_32(enables);
 446
 447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 448
 449         HWRM_CHECK_RESULT();
 450
 451         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 452         HWRM_UNLOCK();
 453
 454         return rc;
 455 }
 456
 457 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 458 {
 459         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 460         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 461         uint32_t flags = 0;
 462         int rc;
 463
 464         if (!ptp)
 465                 return 0;
 466
 467         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 468
 469         if (ptp->rx_filter)
 470                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 471         else
 472                 flags |=
 473                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 474         if (ptp->tx_tstamp_en)
 475                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 476         else
 477                 flags |=
 478                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 479         req.flags = rte_cpu_to_le_32(flags);
 480         req.enables = rte_cpu_to_le_32
 481                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 482         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485         HWRM_UNLOCK();
 486
 487         return rc;
 488 }
 489
 490 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 491 {
 492         int rc = 0;
 493         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 494         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 495         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 496
 497 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 498         if (ptp)
 499                 return 0;
 500
 501         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 502
 503         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 504
 505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 506
 507         HWRM_CHECK_RESULT();
 508
 509         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 510                 return 0;
 511
 512         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 513         if (!ptp)
 514                 return -ENOMEM;
 515
 516         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 517                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 518         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 519                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 520         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 521                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 522         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 523                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 524         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 525                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 526         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 527                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 528         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 529                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 530         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 531                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 532         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 533                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 534
 535         ptp->bp = bp;
 536         bp->ptp_cfg = ptp;
 537
 538         return 0;
 539 }
 540
 541 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 542 {
 543         int rc = 0;
 544         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 545         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 546         uint16_t new_max_vfs;
 547         uint32_t flags;
 548         int i;
 549
 550         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 551
 552         req.fid = rte_cpu_to_le_16(0xffff);
 553
 554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 555
 556         HWRM_CHECK_RESULT();
 557
 558         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 559         flags = rte_le_to_cpu_32(resp->flags);
 560         if (BNXT_PF(bp)) {
 561                 bp->pf.port_id = resp->port_id;
 562                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 563                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 564                 new_max_vfs = bp->pdev->max_vfs;
 565                 if (new_max_vfs != bp->pf.max_vfs) {
 566                         if (bp->pf.vf_info)
 567                                 rte_free(bp->pf.vf_info);
 568                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 569                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 570                         bp->pf.max_vfs = new_max_vfs;
 571                         for (i = 0; i < new_max_vfs; i++) {
 572                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 573                                 bp->pf.vf_info[i].vlan_table =
 574                                         rte_zmalloc("VF VLAN table",
 575                                                     getpagesize(),
 576                                                     getpagesize());
 577                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 578                                         PMD_DRV_LOG(ERR,
 579                                         "Fail to alloc VLAN table for VF %d\n",
 580                                         i);
 581                                 else
 582                                         rte_mem_lock_page(
 583                                                 bp->pf.vf_info[i].vlan_table);
 584                                 bp->pf.vf_info[i].vlan_as_table =
 585                                         rte_zmalloc("VF VLAN AS table",
 586                                                     getpagesize(),
 587                                                     getpagesize());
 588                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 589                                         PMD_DRV_LOG(ERR,
 590                                         "Alloc VLAN AS table for VF %d fail\n",
 591                                         i);
 592                                 else
 593                                         rte_mem_lock_page(
 594                                                bp->pf.vf_info[i].vlan_as_table);
 595                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 596                         }
 597                 }
 598         }
 599
 600         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 601         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 602         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 603         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 604         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 605         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 606         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 607         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 608         bp->max_l2_ctx =
 609                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 610         /* TODO: For now, do not support VMDq/RFS on VFs. */
 611         if (BNXT_PF(bp)) {
 612                 if (bp->pf.max_vfs)
 613                         bp->max_vnics = 1;
 614                 else
 615                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 616         } else {
 617                 bp->max_vnics = 1;
 618         }
 619         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 620         if (BNXT_PF(bp)) {
 621                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 622                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 623                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 624                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 625                         HWRM_UNLOCK();
 626                         bnxt_hwrm_ptp_qcfg(bp);
 627                 }
 628         }
 629
 630         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 631                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 632
 633         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 634                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 635                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 636         } else {
 637                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 638         }
 639
 640         HWRM_UNLOCK();
 641
 642         return rc;
 643 }
 644
 645 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 646 {
 647         int rc;
 648
 649         rc = __bnxt_hwrm_func_qcaps(bp);
 650         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 651                 rc = bnxt_alloc_ctx_mem(bp);
 652                 if (rc)
 653                         return rc;
 654
 655                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 656                 if (!rc)
 657                         bp->flags |= BNXT_FLAG_NEW_RM;
 658         }
 659
 660         return rc;
 661 }
 662
 663 int bnxt_hwrm_func_reset(struct bnxt *bp)
 664 {
 665         int rc = 0;
 666         struct hwrm_func_reset_input req = {.req_type = 0 };
 667         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 668
 669         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 670
 671         req.enables = rte_cpu_to_le_32(0);
 672
 673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 674
 675         HWRM_CHECK_RESULT();
 676         HWRM_UNLOCK();
 677
 678         return rc;
 679 }
 680
 681 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 682 {
 683         int rc;
 684         uint32_t flags = 0;
 685         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 686         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 687
 688         if (bp->flags & BNXT_FLAG_REGISTERED)
 689                 return 0;
 690
 691         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 692
 693         /* PFs and trusted VFs should indicate the support of the
 694          * Master capability on non Stingray platform
 695          */
 696         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 697                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 698
 699         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 700         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 701                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 702         req.ver_maj = RTE_VER_YEAR;
 703         req.ver_min = RTE_VER_MONTH;
 704         req.ver_upd = RTE_VER_MINOR;
 705
 706         if (BNXT_PF(bp)) {
 707                 req.enables |= rte_cpu_to_le_32(
 708                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 709                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 710                        RTE_MIN(sizeof(req.vf_req_fwd),
 711                                sizeof(bp->pf.vf_req_fwd)));
 712
 713                 /*
 714                  * PF can sniff HWRM API issued by VF. This can be set up by
 715                  * linux driver and inherited by the DPDK PF driver. Clear
 716                  * this HWRM sniffer list in FW because DPDK PF driver does
 717                  * not support this.
 718                  */
 719                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 720         }
 721
 722         req.flags = rte_cpu_to_le_32(flags);
 723
 724         req.async_event_fwd[0] |=
 725                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 726                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 727                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 728                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 729         req.async_event_fwd[1] |=
 730                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 731                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 732
 733         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 734
 735         HWRM_CHECK_RESULT();
 736
 737         flags = rte_le_to_cpu_32(resp->flags);
 738         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 739                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 740
 741         HWRM_UNLOCK();
 742
 743         bp->flags |= BNXT_FLAG_REGISTERED;
 744
 745         return rc;
 746 }
 747
 748 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 749 {
 750         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 751                 return 0;
 752
 753         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 754 }
 755
 756 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 757 {
 758         int rc;
 759         uint32_t flags = 0;
 760         uint32_t enables;
 761         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 762         struct hwrm_func_vf_cfg_input req = {0};
 763
 764         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 765
 766         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 767                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 768                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 769                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 770                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 771
 772         if (BNXT_HAS_RING_GRPS(bp)) {
 773                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 774                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 775         }
 776
 777         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 778         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 779                                             AGG_RING_MULTIPLIER);
 780         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings +
 781                                              bp->tx_nr_rings +
 782                                              BNXT_NUM_ASYNC_CPR(bp));
 783         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 784                                               bp->tx_nr_rings +
 785                                               BNXT_NUM_ASYNC_CPR(bp));
 786         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 787         if (bp->vf_resv_strategy ==
 788             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 789                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 790                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 791                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 792                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 793                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 794                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 795         }
 796
 797         if (test)
 798                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 799                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 800                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 801                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 802                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 803                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 804
 805         if (test && BNXT_HAS_RING_GRPS(bp))
 806                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 807
 808         req.flags = rte_cpu_to_le_32(flags);
 809         req.enables |= rte_cpu_to_le_32(enables);
 810
 811         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 812
 813         if (test)
 814                 HWRM_CHECK_RESULT_SILENT();
 815         else
 816                 HWRM_CHECK_RESULT();
 817
 818         HWRM_UNLOCK();
 819         return rc;
 820 }
 821
 822 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 823 {
 824         int rc;
 825         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 826         struct hwrm_func_resource_qcaps_input req = {0};
 827
 828         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 829         req.fid = rte_cpu_to_le_16(0xffff);
 830
 831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 832
 833         HWRM_CHECK_RESULT();
 834
 835         if (BNXT_VF(bp)) {
 836                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 837                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 838                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 839                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 840                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 841                 /* func_resource_qcaps does not return max_rx_em_flows.
 842                  * So use the value provided by func_qcaps.
 843                  */
 844                 bp->max_l2_ctx =
 845                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 846                         bp->max_rx_em_flows;
 847                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 848                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 849         }
 850         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 851         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 852         if (bp->vf_resv_strategy >
 853             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 854                 bp->vf_resv_strategy =
 855                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 856
 857         HWRM_UNLOCK();
 858         return rc;
 859 }
 860
 861 int bnxt_hwrm_ver_get(struct bnxt *bp)
 862 {
 863         int rc = 0;
 864         struct hwrm_ver_get_input req = {.req_type = 0 };
 865         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 866         uint32_t fw_version;
 867         uint16_t max_resp_len;
 868         char type[RTE_MEMZONE_NAMESIZE];
 869         uint32_t dev_caps_cfg;
 870
 871         bp->max_req_len = HWRM_MAX_REQ_LEN;
 872         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 873
 874         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 875         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 876         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 877
 878         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 879
 880         if (bp->flags & BNXT_FLAG_FW_RESET)
 881                 HWRM_CHECK_RESULT_SILENT();
 882         else
 883                 HWRM_CHECK_RESULT();
 884
 885         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 886                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 887                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 888                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 889         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 890                      (resp->hwrm_fw_min_8b << 16) |
 891                      (resp->hwrm_fw_bld_8b << 8) |
 892                      resp->hwrm_fw_rsvd_8b;
 893         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 894                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 895
 896         fw_version = resp->hwrm_intf_maj_8b << 16;
 897         fw_version |= resp->hwrm_intf_min_8b << 8;
 898         fw_version |= resp->hwrm_intf_upd_8b;
 899         bp->hwrm_spec_code = fw_version;
 900
 901         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 902                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 903                 rc = -EINVAL;
 904                 goto error;
 905         }
 906
 907         if (bp->max_req_len > resp->max_req_win_len) {
 908                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 909                 rc = -EINVAL;
 910         }
 911         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 912         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 913         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 914                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 915
 916         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 917         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 918
 919         if (bp->max_resp_len != max_resp_len) {
 920                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 921                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 922                         bp->pdev->addr.devid, bp->pdev->addr.function);
 923
 924                 rte_free(bp->hwrm_cmd_resp_addr);
 925
 926                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 927                 if (bp->hwrm_cmd_resp_addr == NULL) {
 928                         rc = -ENOMEM;
 929                         goto error;
 930                 }
 931                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 932                 bp->hwrm_cmd_resp_dma_addr =
 933                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 934                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 935                         PMD_DRV_LOG(ERR,
 936                         "Unable to map response buffer to physical memory.\n");
 937                         rc = -ENOMEM;
 938                         goto error;
 939                 }
 940                 bp->max_resp_len = max_resp_len;
 941         }
 942
 943         if ((dev_caps_cfg &
 944                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 945             (dev_caps_cfg &
 946              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 947                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 948                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 949         }
 950
 951         if (((dev_caps_cfg &
 952               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 953              (dev_caps_cfg &
 954               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 955             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 956                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 957                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 958                         bp->pdev->addr.devid, bp->pdev->addr.function);
 959
 960                 rte_free(bp->hwrm_short_cmd_req_addr);
 961
 962                 bp->hwrm_short_cmd_req_addr =
 963                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 964                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 965                         rc = -ENOMEM;
 966                         goto error;
 967                 }
 968                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 969                 bp->hwrm_short_cmd_req_dma_addr =
 970                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 971                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 972                         rte_free(bp->hwrm_short_cmd_req_addr);
 973                         PMD_DRV_LOG(ERR,
 974                                 "Unable to map buffer to physical memory.\n");
 975                         rc = -ENOMEM;
 976                         goto error;
 977                 }
 978         }
 979         if (dev_caps_cfg &
 980             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 981                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 982                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 983         }
 984         if (dev_caps_cfg &
 985             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 986                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 987
 988 error:
 989         HWRM_UNLOCK();
 990         return rc;
 991 }
 992
 993 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 994 {
 995         int rc;
 996         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 997         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 998
 999         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1000                 return 0;
1001
1002         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1003         req.flags = flags;
1004
1005         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1006
1007         HWRM_CHECK_RESULT();
1008         HWRM_UNLOCK();
1009
1010         return rc;
1011 }
1012
1013 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1014 {
1015         int rc = 0;
1016         struct hwrm_port_phy_cfg_input req = {0};
1017         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1018         uint32_t enables = 0;
1019
1020         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1021
1022         if (conf->link_up) {
1023                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1024                 if (bp->link_info.auto_mode && conf->link_speed) {
1025                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1026                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1027                 }
1028
1029                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1030                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1031                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1032                 /*
1033                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1034                  * any auto mode, even "none".
1035                  */
1036                 if (!conf->link_speed) {
1037                         /* No speeds specified. Enable AutoNeg - all speeds */
1038                         req.auto_mode =
1039                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1040                 }
1041                 /* AutoNeg - Advertise speeds specified. */
1042                 if (conf->auto_link_speed_mask &&
1043                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1044                         req.auto_mode =
1045                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1046                         req.auto_link_speed_mask =
1047                                 conf->auto_link_speed_mask;
1048                         enables |=
1049                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1050                 }
1051
1052                 req.auto_duplex = conf->duplex;
1053                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1054                 req.auto_pause = conf->auto_pause;
1055                 req.force_pause = conf->force_pause;
1056                 /* Set force_pause if there is no auto or if there is a force */
1057                 if (req.auto_pause && !req.force_pause)
1058                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1059                 else
1060                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1061
1062                 req.enables = rte_cpu_to_le_32(enables);
1063         } else {
1064                 req.flags =
1065                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1066                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1067         }
1068
1069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1070
1071         HWRM_CHECK_RESULT();
1072         HWRM_UNLOCK();
1073
1074         return rc;
1075 }
1076
1077 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1078                                    struct bnxt_link_info *link_info)
1079 {
1080         int rc = 0;
1081         struct hwrm_port_phy_qcfg_input req = {0};
1082         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1083
1084         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1085
1086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1087
1088         HWRM_CHECK_RESULT();
1089
1090         link_info->phy_link_status = resp->link;
1091         link_info->link_up =
1092                 (link_info->phy_link_status ==
1093                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1094         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1095         link_info->duplex = resp->duplex_cfg;
1096         link_info->pause = resp->pause;
1097         link_info->auto_pause = resp->auto_pause;
1098         link_info->force_pause = resp->force_pause;
1099         link_info->auto_mode = resp->auto_mode;
1100         link_info->phy_type = resp->phy_type;
1101         link_info->media_type = resp->media_type;
1102
1103         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1104         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1105         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1106         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1107         link_info->phy_ver[0] = resp->phy_maj;
1108         link_info->phy_ver[1] = resp->phy_min;
1109         link_info->phy_ver[2] = resp->phy_bld;
1110
1111         HWRM_UNLOCK();
1112
1113         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1114         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1115         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1116         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1117         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1118                     link_info->auto_link_speed_mask);
1119         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1120                     link_info->force_link_speed);
1121
1122         return rc;
1123 }
1124
1125 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1126 {
1127         int rc = 0;
1128         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1129         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1130         int i;
1131
1132         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1133
1134         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1135         /* HWRM Version >= 1.9.1 */
1136         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1137                 req.drv_qmap_cap =
1138                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1139         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1140
1141         HWRM_CHECK_RESULT();
1142
1143 #define GET_QUEUE_INFO(x) \
1144         bp->cos_queue[x].id = resp->queue_id##x; \
1145         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1146
1147         GET_QUEUE_INFO(0);
1148         GET_QUEUE_INFO(1);
1149         GET_QUEUE_INFO(2);
1150         GET_QUEUE_INFO(3);
1151         GET_QUEUE_INFO(4);
1152         GET_QUEUE_INFO(5);
1153         GET_QUEUE_INFO(6);
1154         GET_QUEUE_INFO(7);
1155
1156         HWRM_UNLOCK();
1157
1158         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1159                 bp->tx_cosq_id = bp->cos_queue[0].id;
1160         } else {
1161                 /* iterate and find the COSq profile to use for Tx */
1162                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1163                         if (bp->cos_queue[i].profile ==
1164                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1165                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1166                                 break;
1167                         }
1168                 }
1169         }
1170
1171         bp->max_tc = resp->max_configurable_queues;
1172         bp->max_lltc = resp->max_configurable_lossless_queues;
1173         if (bp->max_tc > BNXT_MAX_QUEUE)
1174                 bp->max_tc = BNXT_MAX_QUEUE;
1175         bp->max_q = bp->max_tc;
1176
1177         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1178
1179         return rc;
1180 }
1181
1182 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1183                          struct bnxt_ring *ring,
1184                          uint32_t ring_type, uint32_t map_index,
1185                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1186 {
1187         int rc = 0;
1188         uint32_t enables = 0;
1189         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1190         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1191         struct rte_mempool *mb_pool;
1192         uint16_t rx_buf_size;
1193
1194         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1195
1196         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1197         req.fbo = rte_cpu_to_le_32(0);
1198         /* Association of ring index with doorbell index */
1199         req.logical_id = rte_cpu_to_le_16(map_index);
1200         req.length = rte_cpu_to_le_32(ring->ring_size);
1201
1202         switch (ring_type) {
1203         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1204                 req.ring_type = ring_type;
1205                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1206                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1207                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1208                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1209                         enables |=
1210                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1211                 break;
1212         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1213                 req.ring_type = ring_type;
1214                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1215                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1216                 if (BNXT_CHIP_THOR(bp)) {
1217                         mb_pool = bp->rx_queues[0]->mb_pool;
1218                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1219                                       RTE_PKTMBUF_HEADROOM;
1220                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1221                         enables |=
1222                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1223                 }
1224                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1225                         enables |=
1226                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1227                 break;
1228         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1229                 req.ring_type = ring_type;
1230                 if (BNXT_HAS_NQ(bp)) {
1231                         /* Association of cp ring with nq */
1232                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1233                         enables |=
1234                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1235                 }
1236                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1237                 break;
1238         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1239                 req.ring_type = ring_type;
1240                 req.page_size = BNXT_PAGE_SHFT;
1241                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1242                 break;
1243         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1244                 req.ring_type = ring_type;
1245                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1246
1247                 mb_pool = bp->rx_queues[0]->mb_pool;
1248                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1249                               RTE_PKTMBUF_HEADROOM;
1250                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1251
1252                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1253                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1254                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1255                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1256                 break;
1257         default:
1258                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1259                         ring_type);
1260                 HWRM_UNLOCK();
1261                 return -EINVAL;
1262         }
1263         req.enables = rte_cpu_to_le_32(enables);
1264
1265         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1266
1267         if (rc || resp->error_code) {
1268                 if (rc == 0 && resp->error_code)
1269                         rc = rte_le_to_cpu_16(resp->error_code);
1270                 switch (ring_type) {
1271                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1272                         PMD_DRV_LOG(ERR,
1273                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1274                         HWRM_UNLOCK();
1275                         return rc;
1276                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1277                         PMD_DRV_LOG(ERR,
1278                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1279                         HWRM_UNLOCK();
1280                         return rc;
1281                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1282                         PMD_DRV_LOG(ERR,
1283                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1284                                     rc);
1285                         HWRM_UNLOCK();
1286                         return rc;
1287                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1288                         PMD_DRV_LOG(ERR,
1289                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1290                         HWRM_UNLOCK();
1291                         return rc;
1292                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1293                         PMD_DRV_LOG(ERR,
1294                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1295                         HWRM_UNLOCK();
1296                         return rc;
1297                 default:
1298                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1299                         HWRM_UNLOCK();
1300                         return rc;
1301                 }
1302         }
1303
1304         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1305         HWRM_UNLOCK();
1306         return rc;
1307 }
1308
1309 int bnxt_hwrm_ring_free(struct bnxt *bp,
1310                         struct bnxt_ring *ring, uint32_t ring_type)
1311 {
1312         int rc;
1313         struct hwrm_ring_free_input req = {.req_type = 0 };
1314         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1315
1316         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1317
1318         req.ring_type = ring_type;
1319         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1320
1321         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1322
1323         if (rc || resp->error_code) {
1324                 if (rc == 0 && resp->error_code)
1325                         rc = rte_le_to_cpu_16(resp->error_code);
1326                 HWRM_UNLOCK();
1327
1328                 switch (ring_type) {
1329                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1330                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1331                                 rc);
1332                         return rc;
1333                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1334                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1335                                 rc);
1336                         return rc;
1337                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1338                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1339                                 rc);
1340                         return rc;
1341                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1342                         PMD_DRV_LOG(ERR,
1343                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1344                         return rc;
1345                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1346                         PMD_DRV_LOG(ERR,
1347                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1348                         return rc;
1349                 default:
1350                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1351                         return rc;
1352                 }
1353         }
1354         HWRM_UNLOCK();
1355         return 0;
1356 }
1357
1358 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1359 {
1360         int rc = 0;
1361         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1362         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1363
1364         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1365
1366         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1367         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1368         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1369         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1370
1371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1372
1373         HWRM_CHECK_RESULT();
1374
1375         bp->grp_info[idx].fw_grp_id =
1376             rte_le_to_cpu_16(resp->ring_group_id);
1377
1378         HWRM_UNLOCK();
1379
1380         return rc;
1381 }
1382
1383 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1384 {
1385         int rc;
1386         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1387         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1388
1389         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1390
1391         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1392
1393         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1394
1395         HWRM_CHECK_RESULT();
1396         HWRM_UNLOCK();
1397
1398         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1399         return rc;
1400 }
1401
1402 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1403 {
1404         int rc = 0;
1405         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1406         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1407
1408         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1409                 return rc;
1410
1411         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1412
1413         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1414
1415         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1416
1417         HWRM_CHECK_RESULT();
1418         HWRM_UNLOCK();
1419
1420         return rc;
1421 }
1422
1423 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1424                                 unsigned int idx __rte_unused)
1425 {
1426         int rc;
1427         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1428         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1429
1430         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1431
1432         req.update_period_ms = rte_cpu_to_le_32(0);
1433
1434         req.stats_dma_addr =
1435             rte_cpu_to_le_64(cpr->hw_stats_map);
1436
1437         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1438
1439         HWRM_CHECK_RESULT();
1440
1441         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1442
1443         HWRM_UNLOCK();
1444
1445         return rc;
1446 }
1447
1448 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1449                                 unsigned int idx __rte_unused)
1450 {
1451         int rc;
1452         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1453         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1454
1455         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1456
1457         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1458
1459         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1460
1461         HWRM_CHECK_RESULT();
1462         HWRM_UNLOCK();
1463
1464         return rc;
1465 }
1466
1467 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1468 {
1469         int rc = 0, i, j;
1470         struct hwrm_vnic_alloc_input req = { 0 };
1471         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1472
1473         if (!BNXT_HAS_RING_GRPS(bp))
1474                 goto skip_ring_grps;
1475
1476         /* map ring groups to this vnic */
1477         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1478                 vnic->start_grp_id, vnic->end_grp_id);
1479         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1480                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1481
1482         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1483         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1484         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1485         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1486
1487 skip_ring_grps:
1488         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1489                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1490         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1491
1492         if (vnic->func_default)
1493                 req.flags =
1494                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1495         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1496
1497         HWRM_CHECK_RESULT();
1498
1499         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1500         HWRM_UNLOCK();
1501         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1502         return rc;
1503 }
1504
1505 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1506                                         struct bnxt_vnic_info *vnic,
1507                                         struct bnxt_plcmodes_cfg *pmode)
1508 {
1509         int rc = 0;
1510         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1511         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1512
1513         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1514
1515         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1516
1517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1518
1519         HWRM_CHECK_RESULT();
1520
1521         pmode->flags = rte_le_to_cpu_32(resp->flags);
1522         /* dflt_vnic bit doesn't exist in the _cfg command */
1523         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1524         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1525         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1526         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1527
1528         HWRM_UNLOCK();
1529
1530         return rc;
1531 }
1532
1533 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1534                                        struct bnxt_vnic_info *vnic,
1535                                        struct bnxt_plcmodes_cfg *pmode)
1536 {
1537         int rc = 0;
1538         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1539         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1540
1541         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1542                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1543                 return rc;
1544         }
1545
1546         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1547
1548         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1549         req.flags = rte_cpu_to_le_32(pmode->flags);
1550         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1551         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1552         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1553         req.enables = rte_cpu_to_le_32(
1554             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1555             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1556             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1557         );
1558
1559         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1560
1561         HWRM_CHECK_RESULT();
1562         HWRM_UNLOCK();
1563
1564         return rc;
1565 }
1566
1567 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1568 {
1569         int rc = 0;
1570         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1571         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1572         struct bnxt_plcmodes_cfg pmodes = { 0 };
1573         uint32_t ctx_enable_flag = 0;
1574         uint32_t enables = 0;
1575
1576         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1577                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1578                 return rc;
1579         }
1580
1581         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1582         if (rc)
1583                 return rc;
1584
1585         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1586
1587         if (BNXT_CHIP_THOR(bp)) {
1588                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1589                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1590                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1591
1592                 req.default_rx_ring_id =
1593                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1594                 req.default_cmpl_ring_id =
1595                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1596                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1597                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1598                 goto config_mru;
1599         }
1600
1601         /* Only RSS support for now TBD: COS & LB */
1602         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1603         if (vnic->lb_rule != 0xffff)
1604                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1605         if (vnic->cos_rule != 0xffff)
1606                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1607         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1608                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1609                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1610         }
1611         enables |= ctx_enable_flag;
1612         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1613         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1614         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1615         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1616
1617 config_mru:
1618         req.enables = rte_cpu_to_le_32(enables);
1619         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1620         req.mru = rte_cpu_to_le_16(vnic->mru);
1621         /* Configure default VNIC only once. */
1622         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1623                 req.flags |=
1624                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1625                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1626         }
1627         if (vnic->vlan_strip)
1628                 req.flags |=
1629                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1630         if (vnic->bd_stall)
1631                 req.flags |=
1632                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1633         if (vnic->roce_dual)
1634                 req.flags |= rte_cpu_to_le_32(
1635                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1636         if (vnic->roce_only)
1637                 req.flags |= rte_cpu_to_le_32(
1638                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1639         if (vnic->rss_dflt_cr)
1640                 req.flags |= rte_cpu_to_le_32(
1641                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1642
1643         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1644
1645         HWRM_CHECK_RESULT();
1646         HWRM_UNLOCK();
1647
1648         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1649
1650         return rc;
1651 }
1652
1653 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1654                 int16_t fw_vf_id)
1655 {
1656         int rc = 0;
1657         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1658         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1659
1660         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1661                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1662                 return rc;
1663         }
1664         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1665
1666         req.enables =
1667                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1668         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1669         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1670
1671         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1672
1673         HWRM_CHECK_RESULT();
1674
1675         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1676         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1677         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1678         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1679         vnic->mru = rte_le_to_cpu_16(resp->mru);
1680         vnic->func_default = rte_le_to_cpu_32(
1681                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1682         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1683                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1684         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1685                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1686         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1687                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1688         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1689                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1690         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1691                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1692
1693         HWRM_UNLOCK();
1694
1695         return rc;
1696 }
1697
1698 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1699                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1700 {
1701         int rc = 0;
1702         uint16_t ctx_id;
1703         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1704         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1705                                                 bp->hwrm_cmd_resp_addr;
1706
1707         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1708
1709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1710         HWRM_CHECK_RESULT();
1711
1712         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1713         if (!BNXT_HAS_RING_GRPS(bp))
1714                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1715         else if (ctx_idx == 0)
1716                 vnic->rss_rule = ctx_id;
1717
1718         HWRM_UNLOCK();
1719
1720         return rc;
1721 }
1722
1723 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1724                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1725 {
1726         int rc = 0;
1727         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1728         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1729                                                 bp->hwrm_cmd_resp_addr;
1730
1731         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1732                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1733                 return rc;
1734         }
1735         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1736
1737         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1738
1739         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1740
1741         HWRM_CHECK_RESULT();
1742         HWRM_UNLOCK();
1743
1744         return rc;
1745 }
1746
1747 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1748 {
1749         int rc = 0;
1750         struct hwrm_vnic_free_input req = {.req_type = 0 };
1751         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1752
1753         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1754                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1755                 return rc;
1756         }
1757
1758         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1759
1760         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1761
1762         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1763
1764         HWRM_CHECK_RESULT();
1765         HWRM_UNLOCK();
1766
1767         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1768         /* Configure default VNIC again if necessary. */
1769         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1770                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1771
1772         return rc;
1773 }
1774
1775 static int
1776 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1777 {
1778         int i;
1779         int rc = 0;
1780         int nr_ctxs = vnic->num_lb_ctxts;
1781         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1782         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1783
1784         for (i = 0; i < nr_ctxs; i++) {
1785                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1786
1787                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1788                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1789                 req.hash_mode_flags = vnic->hash_mode;
1790
1791                 req.hash_key_tbl_addr =
1792                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1793
1794                 req.ring_grp_tbl_addr =
1795                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1796                                          i * HW_HASH_INDEX_SIZE);
1797                 req.ring_table_pair_index = i;
1798                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1799
1800                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1801                                             BNXT_USE_CHIMP_MB);
1802
1803                 HWRM_CHECK_RESULT();
1804                 HWRM_UNLOCK();
1805         }
1806
1807         return rc;
1808 }
1809
1810 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1811                            struct bnxt_vnic_info *vnic)
1812 {
1813         int rc = 0;
1814         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1815         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1816
1817         if (!vnic->rss_table)
1818                 return 0;
1819
1820         if (BNXT_CHIP_THOR(bp))
1821                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1822
1823         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1824
1825         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1826         req.hash_mode_flags = vnic->hash_mode;
1827
1828         req.ring_grp_tbl_addr =
1829             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1830         req.hash_key_tbl_addr =
1831             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1832         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1833         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1834
1835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1836
1837         HWRM_CHECK_RESULT();
1838         HWRM_UNLOCK();
1839
1840         return rc;
1841 }
1842
1843 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1844                         struct bnxt_vnic_info *vnic)
1845 {
1846         int rc = 0;
1847         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1848         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1849         uint16_t size;
1850
1851         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1852                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1853                 return rc;
1854         }
1855
1856         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1857
1858         req.flags = rte_cpu_to_le_32(
1859                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1860
1861         req.enables = rte_cpu_to_le_32(
1862                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1863
1864         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1865         size -= RTE_PKTMBUF_HEADROOM;
1866
1867         req.jumbo_thresh = rte_cpu_to_le_16(size);
1868         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1869
1870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1871
1872         HWRM_CHECK_RESULT();
1873         HWRM_UNLOCK();
1874
1875         return rc;
1876 }
1877
1878 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1879                         struct bnxt_vnic_info *vnic, bool enable)
1880 {
1881         int rc = 0;
1882         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1883         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1884
1885         if (BNXT_CHIP_THOR(bp))
1886                 return 0;
1887
1888         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1889
1890         if (enable) {
1891                 req.enables = rte_cpu_to_le_32(
1892                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1893                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1894                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1895                 req.flags = rte_cpu_to_le_32(
1896                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1897                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1898                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1899                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1900                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1901                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1902                 req.max_agg_segs = rte_cpu_to_le_16(5);
1903                 req.max_aggs =
1904                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1905                 req.min_agg_len = rte_cpu_to_le_32(512);
1906         }
1907         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1908
1909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1910
1911         HWRM_CHECK_RESULT();
1912         HWRM_UNLOCK();
1913
1914         return rc;
1915 }
1916
1917 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1918 {
1919         struct hwrm_func_cfg_input req = {0};
1920         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1921         int rc;
1922
1923         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1924         req.enables = rte_cpu_to_le_32(
1925                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1926         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1927         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1928
1929         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1930
1931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1932         HWRM_CHECK_RESULT();
1933         HWRM_UNLOCK();
1934
1935         bp->pf.vf_info[vf].random_mac = false;
1936
1937         return rc;
1938 }
1939
1940 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1941                                   uint64_t *dropped)
1942 {
1943         int rc = 0;
1944         struct hwrm_func_qstats_input req = {.req_type = 0};
1945         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1946
1947         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1948
1949         req.fid = rte_cpu_to_le_16(fid);
1950
1951         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1952
1953         HWRM_CHECK_RESULT();
1954
1955         if (dropped)
1956                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1957
1958         HWRM_UNLOCK();
1959
1960         return rc;
1961 }
1962
1963 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1964                           struct rte_eth_stats *stats)
1965 {
1966         int rc = 0;
1967         struct hwrm_func_qstats_input req = {.req_type = 0};
1968         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1969
1970         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1971
1972         req.fid = rte_cpu_to_le_16(fid);
1973
1974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1975
1976         HWRM_CHECK_RESULT();
1977
1978         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1979         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1980         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1981         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1982         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1983         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1984
1985         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1986         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1987         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1988         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1989         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1990         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1991
1992         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1993         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1994         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1995
1996         HWRM_UNLOCK();
1997
1998         return rc;
1999 }
2000
2001 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2002 {
2003         int rc = 0;
2004         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2005         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2006
2007         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2008
2009         req.fid = rte_cpu_to_le_16(fid);
2010
2011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2012
2013         HWRM_CHECK_RESULT();
2014         HWRM_UNLOCK();
2015
2016         return rc;
2017 }
2018
2019 /*
2020  * HWRM utility functions
2021  */
2022
2023 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2024 {
2025         unsigned int i;
2026         int rc = 0;
2027
2028         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2029                 struct bnxt_tx_queue *txq;
2030                 struct bnxt_rx_queue *rxq;
2031                 struct bnxt_cp_ring_info *cpr;
2032
2033                 if (i >= bp->rx_cp_nr_rings) {
2034                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2035                         cpr = txq->cp_ring;
2036                 } else {
2037                         rxq = bp->rx_queues[i];
2038                         cpr = rxq->cp_ring;
2039                 }
2040
2041                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2042                 if (rc)
2043                         return rc;
2044         }
2045         return 0;
2046 }
2047
2048 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2049 {
2050         int rc;
2051         unsigned int i;
2052         struct bnxt_cp_ring_info *cpr;
2053
2054         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2055
2056                 if (i >= bp->rx_cp_nr_rings) {
2057                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2058                 } else {
2059                         cpr = bp->rx_queues[i]->cp_ring;
2060                         if (BNXT_HAS_RING_GRPS(bp))
2061                                 bp->grp_info[i].fw_stats_ctx = -1;
2062                 }
2063                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2064                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2065                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2066                         if (rc)
2067                                 return rc;
2068                 }
2069         }
2070         return 0;
2071 }
2072
2073 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2074 {
2075         unsigned int i;
2076         int rc = 0;
2077
2078         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2079                 struct bnxt_tx_queue *txq;
2080                 struct bnxt_rx_queue *rxq;
2081                 struct bnxt_cp_ring_info *cpr;
2082
2083                 if (i >= bp->rx_cp_nr_rings) {
2084                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2085                         cpr = txq->cp_ring;
2086                 } else {
2087                         rxq = bp->rx_queues[i];
2088                         cpr = rxq->cp_ring;
2089                 }
2090
2091                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2092
2093                 if (rc)
2094                         return rc;
2095         }
2096         return rc;
2097 }
2098
2099 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2100 {
2101         uint16_t idx;
2102         uint32_t rc = 0;
2103
2104         if (!BNXT_HAS_RING_GRPS(bp))
2105                 return 0;
2106
2107         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2108
2109                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2110                         continue;
2111
2112                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2113
2114                 if (rc)
2115                         return rc;
2116         }
2117         return rc;
2118 }
2119
2120 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2121 {
2122         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2123
2124         bnxt_hwrm_ring_free(bp, cp_ring,
2125                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2126         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2127         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2128                                      sizeof(*cpr->cp_desc_ring));
2129         cpr->cp_raw_cons = 0;
2130         cpr->valid = 0;
2131 }
2132
2133 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2134 {
2135         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2136
2137         bnxt_hwrm_ring_free(bp, cp_ring,
2138                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2139         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2140         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2141                         sizeof(*cpr->cp_desc_ring));
2142         cpr->cp_raw_cons = 0;
2143         cpr->valid = 0;
2144 }
2145
2146 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2147 {
2148         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2149         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2150         struct bnxt_ring *ring = rxr->rx_ring_struct;
2151         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2152
2153         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2154                 bnxt_hwrm_ring_free(bp, ring,
2155                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2156                 ring->fw_ring_id = INVALID_HW_RING_ID;
2157                 if (BNXT_HAS_RING_GRPS(bp))
2158                         bp->grp_info[queue_index].rx_fw_ring_id =
2159                                                         INVALID_HW_RING_ID;
2160                 memset(rxr->rx_desc_ring, 0,
2161                        rxr->rx_ring_struct->ring_size *
2162                        sizeof(*rxr->rx_desc_ring));
2163                 memset(rxr->rx_buf_ring, 0,
2164                        rxr->rx_ring_struct->ring_size *
2165                        sizeof(*rxr->rx_buf_ring));
2166                 rxr->rx_prod = 0;
2167         }
2168         ring = rxr->ag_ring_struct;
2169         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2170                 bnxt_hwrm_ring_free(bp, ring,
2171                                     BNXT_CHIP_THOR(bp) ?
2172                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2173                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2174                 ring->fw_ring_id = INVALID_HW_RING_ID;
2175                 memset(rxr->ag_buf_ring, 0,
2176                        rxr->ag_ring_struct->ring_size *
2177                        sizeof(*rxr->ag_buf_ring));
2178                 rxr->ag_prod = 0;
2179                 if (BNXT_HAS_RING_GRPS(bp))
2180                         bp->grp_info[queue_index].ag_fw_ring_id =
2181                                                         INVALID_HW_RING_ID;
2182         }
2183         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2184                 bnxt_free_cp_ring(bp, cpr);
2185                 if (rxq->nq_ring)
2186                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2187         }
2188
2189         if (BNXT_HAS_RING_GRPS(bp))
2190                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2191 }
2192
2193 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2194 {
2195         unsigned int i;
2196
2197         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2198                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2199                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2200                 struct bnxt_ring *ring = txr->tx_ring_struct;
2201                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2202
2203                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2204                         bnxt_hwrm_ring_free(bp, ring,
2205                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2206                         ring->fw_ring_id = INVALID_HW_RING_ID;
2207                         memset(txr->tx_desc_ring, 0,
2208                                         txr->tx_ring_struct->ring_size *
2209                                         sizeof(*txr->tx_desc_ring));
2210                         memset(txr->tx_buf_ring, 0,
2211                                         txr->tx_ring_struct->ring_size *
2212                                         sizeof(*txr->tx_buf_ring));
2213                         txr->tx_prod = 0;
2214                         txr->tx_cons = 0;
2215                 }
2216                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2217                         bnxt_free_cp_ring(bp, cpr);
2218                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2219                         if (txq->nq_ring)
2220                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2221                 }
2222         }
2223
2224         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2225                 bnxt_free_hwrm_rx_ring(bp, i);
2226
2227         return 0;
2228 }
2229
2230 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2231 {
2232         uint16_t i;
2233         uint32_t rc = 0;
2234
2235         if (!BNXT_HAS_RING_GRPS(bp))
2236                 return 0;
2237
2238         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2239                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2240                 if (rc)
2241                         return rc;
2242         }
2243         return rc;
2244 }
2245
2246 void bnxt_free_hwrm_resources(struct bnxt *bp)
2247 {
2248         /* Release memzone */
2249         rte_free(bp->hwrm_cmd_resp_addr);
2250         rte_free(bp->hwrm_short_cmd_req_addr);
2251         bp->hwrm_cmd_resp_addr = NULL;
2252         bp->hwrm_short_cmd_req_addr = NULL;
2253         bp->hwrm_cmd_resp_dma_addr = 0;
2254         bp->hwrm_short_cmd_req_dma_addr = 0;
2255 }
2256
2257 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2258 {
2259         struct rte_pci_device *pdev = bp->pdev;
2260         char type[RTE_MEMZONE_NAMESIZE];
2261
2262         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2263                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2264         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2265         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2266         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2267         if (bp->hwrm_cmd_resp_addr == NULL)
2268                 return -ENOMEM;
2269         bp->hwrm_cmd_resp_dma_addr =
2270                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2271         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2272                 PMD_DRV_LOG(ERR,
2273                         "unable to map response address to physical memory\n");
2274                 return -ENOMEM;
2275         }
2276         rte_spinlock_init(&bp->hwrm_lock);
2277
2278         return 0;
2279 }
2280
2281 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2282 {
2283         struct bnxt_filter_info *filter;
2284         int rc = 0;
2285
2286         STAILQ_FOREACH(filter, &vnic->filter, next) {
2287                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2288                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2289                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2290                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2291                 else
2292                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2293                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2294                 //if (rc)
2295                         //break;
2296         }
2297         return rc;
2298 }
2299
2300 static int
2301 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2302 {
2303         struct bnxt_filter_info *filter;
2304         struct rte_flow *flow;
2305         int rc = 0;
2306
2307         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2308                 filter = flow->filter;
2309                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2310                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2311                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2312                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2313                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2314                 else
2315                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2316
2317                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2318                 rte_free(flow);
2319                 //if (rc)
2320                         //break;
2321         }
2322         return rc;
2323 }
2324
2325 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2326 {
2327         struct bnxt_filter_info *filter;
2328         int rc = 0;
2329
2330         STAILQ_FOREACH(filter, &vnic->filter, next) {
2331                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2332                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2333                                                      filter);
2334                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2335                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2336                                                          filter);
2337                 else
2338                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2339                                                      filter);
2340                 if (rc)
2341                         break;
2342         }
2343         return rc;
2344 }
2345
2346 void bnxt_free_tunnel_ports(struct bnxt *bp)
2347 {
2348         if (bp->vxlan_port_cnt)
2349                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2350                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2351         bp->vxlan_port = 0;
2352         if (bp->geneve_port_cnt)
2353                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2354                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2355         bp->geneve_port = 0;
2356 }
2357
2358 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2359 {
2360         int i, j;
2361
2362         if (bp->vnic_info == NULL)
2363                 return;
2364
2365         /*
2366          * Cleanup VNICs in reverse order, to make sure the L2 filter
2367          * from vnic0 is last to be cleaned up.
2368          */
2369         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2370                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2371
2372                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2373                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2374                         return;
2375                 }
2376
2377                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2378
2379                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2380
2381                 if (BNXT_CHIP_THOR(bp)) {
2382                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2383                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2384                                                         vnic->fw_grp_ids[j]);
2385                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2386                         }
2387                         vnic->num_lb_ctxts = 0;
2388                 } else {
2389                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2390                         vnic->rss_rule = INVALID_HW_RING_ID;
2391                 }
2392
2393                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2394
2395                 bnxt_hwrm_vnic_free(bp, vnic);
2396
2397                 rte_free(vnic->fw_grp_ids);
2398         }
2399         /* Ring resources */
2400         bnxt_free_all_hwrm_rings(bp);
2401         bnxt_free_all_hwrm_ring_grps(bp);
2402         bnxt_free_all_hwrm_stat_ctxs(bp);
2403         bnxt_free_tunnel_ports(bp);
2404 }
2405
2406 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2407 {
2408         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2409
2410         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2411                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2412
2413         switch (conf_link_speed) {
2414         case ETH_LINK_SPEED_10M_HD:
2415         case ETH_LINK_SPEED_100M_HD:
2416                 /* FALLTHROUGH */
2417                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2418         }
2419         return hw_link_duplex;
2420 }
2421
2422 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2423 {
2424         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2425 }
2426
2427 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2428 {
2429         uint16_t eth_link_speed = 0;
2430
2431         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2432                 return ETH_LINK_SPEED_AUTONEG;
2433
2434         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2435         case ETH_LINK_SPEED_100M:
2436         case ETH_LINK_SPEED_100M_HD:
2437                 /* FALLTHROUGH */
2438                 eth_link_speed =
2439                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2440                 break;
2441         case ETH_LINK_SPEED_1G:
2442                 eth_link_speed =
2443                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2444                 break;
2445         case ETH_LINK_SPEED_2_5G:
2446                 eth_link_speed =
2447                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2448                 break;
2449         case ETH_LINK_SPEED_10G:
2450                 eth_link_speed =
2451                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2452                 break;
2453         case ETH_LINK_SPEED_20G:
2454                 eth_link_speed =
2455                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2456                 break;
2457         case ETH_LINK_SPEED_25G:
2458                 eth_link_speed =
2459                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2460                 break;
2461         case ETH_LINK_SPEED_40G:
2462                 eth_link_speed =
2463                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2464                 break;
2465         case ETH_LINK_SPEED_50G:
2466                 eth_link_speed =
2467                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2468                 break;
2469         case ETH_LINK_SPEED_100G:
2470                 eth_link_speed =
2471                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2472                 break;
2473         default:
2474                 PMD_DRV_LOG(ERR,
2475                         "Unsupported link speed %d; default to AUTO\n",
2476                         conf_link_speed);
2477                 break;
2478         }
2479         return eth_link_speed;
2480 }
2481
2482 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2483                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2484                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2485                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2486
2487 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2488 {
2489         uint32_t one_speed;
2490
2491         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2492                 return 0;
2493
2494         if (link_speed & ETH_LINK_SPEED_FIXED) {
2495                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2496
2497                 if (one_speed & (one_speed - 1)) {
2498                         PMD_DRV_LOG(ERR,
2499                                 "Invalid advertised speeds (%u) for port %u\n",
2500                                 link_speed, port_id);
2501                         return -EINVAL;
2502                 }
2503                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2504                         PMD_DRV_LOG(ERR,
2505                                 "Unsupported advertised speed (%u) for port %u\n",
2506                                 link_speed, port_id);
2507                         return -EINVAL;
2508                 }
2509         } else {
2510                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2511                         PMD_DRV_LOG(ERR,
2512                                 "Unsupported advertised speeds (%u) for port %u\n",
2513                                 link_speed, port_id);
2514                         return -EINVAL;
2515                 }
2516         }
2517         return 0;
2518 }
2519
2520 static uint16_t
2521 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2522 {
2523         uint16_t ret = 0;
2524
2525         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2526                 if (bp->link_info.support_speeds)
2527                         return bp->link_info.support_speeds;
2528                 link_speed = BNXT_SUPPORTED_SPEEDS;
2529         }
2530
2531         if (link_speed & ETH_LINK_SPEED_100M)
2532                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2533         if (link_speed & ETH_LINK_SPEED_100M_HD)
2534                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2535         if (link_speed & ETH_LINK_SPEED_1G)
2536                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2537         if (link_speed & ETH_LINK_SPEED_2_5G)
2538                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2539         if (link_speed & ETH_LINK_SPEED_10G)
2540                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2541         if (link_speed & ETH_LINK_SPEED_20G)
2542                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2543         if (link_speed & ETH_LINK_SPEED_25G)
2544                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2545         if (link_speed & ETH_LINK_SPEED_40G)
2546                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2547         if (link_speed & ETH_LINK_SPEED_50G)
2548                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2549         if (link_speed & ETH_LINK_SPEED_100G)
2550                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2551         return ret;
2552 }
2553
2554 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2555 {
2556         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2557
2558         switch (hw_link_speed) {
2559         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2560                 eth_link_speed = ETH_SPEED_NUM_100M;
2561                 break;
2562         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2563                 eth_link_speed = ETH_SPEED_NUM_1G;
2564                 break;
2565         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2566                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2567                 break;
2568         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2569                 eth_link_speed = ETH_SPEED_NUM_10G;
2570                 break;
2571         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2572                 eth_link_speed = ETH_SPEED_NUM_20G;
2573                 break;
2574         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2575                 eth_link_speed = ETH_SPEED_NUM_25G;
2576                 break;
2577         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2578                 eth_link_speed = ETH_SPEED_NUM_40G;
2579                 break;
2580         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2581                 eth_link_speed = ETH_SPEED_NUM_50G;
2582                 break;
2583         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2584                 eth_link_speed = ETH_SPEED_NUM_100G;
2585                 break;
2586         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2587         default:
2588                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2589                         hw_link_speed);
2590                 break;
2591         }
2592         return eth_link_speed;
2593 }
2594
2595 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2596 {
2597         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2598
2599         switch (hw_link_duplex) {
2600         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2601         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2602                 /* FALLTHROUGH */
2603                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2604                 break;
2605         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2606                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2607                 break;
2608         default:
2609                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2610                         hw_link_duplex);
2611                 break;
2612         }
2613         return eth_link_duplex;
2614 }
2615
2616 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2617 {
2618         int rc = 0;
2619         struct bnxt_link_info *link_info = &bp->link_info;
2620
2621         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2622         if (rc) {
2623                 PMD_DRV_LOG(ERR,
2624                         "Get link config failed with rc %d\n", rc);
2625                 goto exit;
2626         }
2627         if (link_info->link_speed)
2628                 link->link_speed =
2629                         bnxt_parse_hw_link_speed(link_info->link_speed);
2630         else
2631                 link->link_speed = ETH_SPEED_NUM_NONE;
2632         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2633         link->link_status = link_info->link_up;
2634         link->link_autoneg = link_info->auto_mode ==
2635                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2636                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2637 exit:
2638         return rc;
2639 }
2640
2641 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2642 {
2643         int rc = 0;
2644         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2645         struct bnxt_link_info link_req;
2646         uint16_t speed, autoneg;
2647
2648         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2649                 return 0;
2650
2651         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2652                         bp->eth_dev->data->port_id);
2653         if (rc)
2654                 goto error;
2655
2656         memset(&link_req, 0, sizeof(link_req));
2657         link_req.link_up = link_up;
2658         if (!link_up)
2659                 goto port_phy_cfg;
2660
2661         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2662         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2663         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2664         /* Autoneg can be done only when the FW allows */
2665         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2666                                 bp->link_info.force_link_speed)) {
2667                 link_req.phy_flags |=
2668                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2669                 link_req.auto_link_speed_mask =
2670                         bnxt_parse_eth_link_speed_mask(bp,
2671                                                        dev_conf->link_speeds);
2672         } else {
2673                 if (bp->link_info.phy_type ==
2674                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2675                     bp->link_info.phy_type ==
2676                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2677                     bp->link_info.media_type ==
2678                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2679                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2680                         return -EINVAL;
2681                 }
2682
2683                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2684                 /* If user wants a particular speed try that first. */
2685                 if (speed)
2686                         link_req.link_speed = speed;
2687                 else if (bp->link_info.force_link_speed)
2688                         link_req.link_speed = bp->link_info.force_link_speed;
2689                 else
2690                         link_req.link_speed = bp->link_info.auto_link_speed;
2691         }
2692         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2693         link_req.auto_pause = bp->link_info.auto_pause;
2694         link_req.force_pause = bp->link_info.force_pause;
2695
2696 port_phy_cfg:
2697         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2698         if (rc) {
2699                 PMD_DRV_LOG(ERR,
2700                         "Set link config failed with rc %d\n", rc);
2701         }
2702
2703 error:
2704         return rc;
2705 }
2706
2707 /* JIRA 22088 */
2708 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2709 {
2710         struct hwrm_func_qcfg_input req = {0};
2711         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2712         uint16_t flags;
2713         int rc = 0;
2714
2715         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2716         req.fid = rte_cpu_to_le_16(0xffff);
2717
2718         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2719
2720         HWRM_CHECK_RESULT();
2721
2722         /* Hard Coded.. 0xfff VLAN ID mask */
2723         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2724         flags = rte_le_to_cpu_16(resp->flags);
2725         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2726                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2727
2728         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2729                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2730                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2731         } else if (BNXT_VF(bp) &&
2732                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2733                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2734                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2735         }
2736
2737         if (mtu)
2738                 *mtu = resp->mtu;
2739
2740         switch (resp->port_partition_type) {
2741         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2742         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2743         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2744                 /* FALLTHROUGH */
2745                 bp->port_partition_type = resp->port_partition_type;
2746                 break;
2747         default:
2748                 bp->port_partition_type = 0;
2749                 break;
2750         }
2751
2752         HWRM_UNLOCK();
2753
2754         return rc;
2755 }
2756
2757 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2758                                    struct hwrm_func_qcaps_output *qcaps)
2759 {
2760         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2761         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2762                sizeof(qcaps->mac_address));
2763         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2764         qcaps->max_rx_rings = fcfg->num_rx_rings;
2765         qcaps->max_tx_rings = fcfg->num_tx_rings;
2766         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2767         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2768         qcaps->max_vfs = 0;
2769         qcaps->first_vf_id = 0;
2770         qcaps->max_vnics = fcfg->num_vnics;
2771         qcaps->max_decap_records = 0;
2772         qcaps->max_encap_records = 0;
2773         qcaps->max_tx_wm_flows = 0;
2774         qcaps->max_tx_em_flows = 0;
2775         qcaps->max_rx_wm_flows = 0;
2776         qcaps->max_rx_em_flows = 0;
2777         qcaps->max_flow_id = 0;
2778         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2779         qcaps->max_sp_tx_rings = 0;
2780         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2781 }
2782
2783 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2784 {
2785         struct hwrm_func_cfg_input req = {0};
2786         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2787         uint32_t enables;
2788         int rc;
2789
2790         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2791                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2792                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2793                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2794                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2795                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2796                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2797                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2798                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2799
2800         if (BNXT_HAS_RING_GRPS(bp)) {
2801                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2802                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2803         } else if (BNXT_HAS_NQ(bp)) {
2804                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2805                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2806         }
2807
2808         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2809         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2810         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2811                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2812                                    BNXT_NUM_VLANS);
2813         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2814         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2815         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2816         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2817         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2818         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2819         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2820         req.fid = rte_cpu_to_le_16(0xffff);
2821         req.enables = rte_cpu_to_le_32(enables);
2822
2823         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2824
2825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2826
2827         HWRM_CHECK_RESULT();
2828         HWRM_UNLOCK();
2829
2830         return rc;
2831 }
2832
2833 static void populate_vf_func_cfg_req(struct bnxt *bp,
2834                                      struct hwrm_func_cfg_input *req,
2835                                      int num_vfs)
2836 {
2837         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2838                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2839                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2840                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2841                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2842                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2843                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2844                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2845                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2846                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2847
2848         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2849                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2850                                     BNXT_NUM_VLANS);
2851         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2852                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2853                                     BNXT_NUM_VLANS);
2854         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2855                                                 (num_vfs + 1));
2856         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2857         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2858                                                (num_vfs + 1));
2859         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2860         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2861         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2862         /* TODO: For now, do not support VMDq/RFS on VFs. */
2863         req->num_vnics = rte_cpu_to_le_16(1);
2864         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2865                                                  (num_vfs + 1));
2866 }
2867
2868 static void add_random_mac_if_needed(struct bnxt *bp,
2869                                      struct hwrm_func_cfg_input *cfg_req,
2870                                      int vf)
2871 {
2872         struct rte_ether_addr mac;
2873
2874         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2875                 return;
2876
2877         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2878                 cfg_req->enables |=
2879                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2880                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2881                 bp->pf.vf_info[vf].random_mac = true;
2882         } else {
2883                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2884                         RTE_ETHER_ADDR_LEN);
2885         }
2886 }
2887
2888 static void reserve_resources_from_vf(struct bnxt *bp,
2889                                       struct hwrm_func_cfg_input *cfg_req,
2890                                       int vf)
2891 {
2892         struct hwrm_func_qcaps_input req = {0};
2893         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2894         int rc;
2895
2896         /* Get the actual allocated values now */
2897         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2898         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2900
2901         if (rc) {
2902                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2903                 copy_func_cfg_to_qcaps(cfg_req, resp);
2904         } else if (resp->error_code) {
2905                 rc = rte_le_to_cpu_16(resp->error_code);
2906                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2907                 copy_func_cfg_to_qcaps(cfg_req, resp);
2908         }
2909
2910         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2911         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2912         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2913         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2914         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2915         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2916         /*
2917          * TODO: While not supporting VMDq with VFs, max_vnics is always
2918          * forced to 1 in this case
2919          */
2920         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2921         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2922
2923         HWRM_UNLOCK();
2924 }
2925
2926 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2927 {
2928         struct hwrm_func_qcfg_input req = {0};
2929         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2930         int rc;
2931
2932         /* Check for zero MAC address */
2933         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2934         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2936         HWRM_CHECK_RESULT();
2937         rc = rte_le_to_cpu_16(resp->vlan);
2938
2939         HWRM_UNLOCK();
2940
2941         return rc;
2942 }
2943
2944 static int update_pf_resource_max(struct bnxt *bp)
2945 {
2946         struct hwrm_func_qcfg_input req = {0};
2947         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2948         int rc;
2949
2950         /* And copy the allocated numbers into the pf struct */
2951         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2952         req.fid = rte_cpu_to_le_16(0xffff);
2953         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2954         HWRM_CHECK_RESULT();
2955
2956         /* Only TX ring value reflects actual allocation? TODO */
2957         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2958         bp->pf.evb_mode = resp->evb_mode;
2959
2960         HWRM_UNLOCK();
2961
2962         return rc;
2963 }
2964
2965 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2966 {
2967         int rc;
2968
2969         if (!BNXT_PF(bp)) {
2970                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2971                 return -EINVAL;
2972         }
2973
2974         rc = bnxt_hwrm_func_qcaps(bp);
2975         if (rc)
2976                 return rc;
2977
2978         bp->pf.func_cfg_flags &=
2979                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2980                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2981         bp->pf.func_cfg_flags |=
2982                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2983         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2984         rc = __bnxt_hwrm_func_qcaps(bp);
2985         return rc;
2986 }
2987
2988 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2989 {
2990         struct hwrm_func_cfg_input req = {0};
2991         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2992         int i;
2993         size_t sz;
2994         int rc = 0;
2995         size_t req_buf_sz;
2996
2997         if (!BNXT_PF(bp)) {
2998                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2999                 return -EINVAL;
3000         }
3001
3002         rc = bnxt_hwrm_func_qcaps(bp);
3003
3004         if (rc)
3005                 return rc;
3006
3007         bp->pf.active_vfs = num_vfs;
3008
3009         /*
3010          * First, configure the PF to only use one TX ring.  This ensures that
3011          * there are enough rings for all VFs.
3012          *
3013          * If we don't do this, when we call func_alloc() later, we will lock
3014          * extra rings to the PF that won't be available during func_cfg() of
3015          * the VFs.
3016          *
3017          * This has been fixed with firmware versions above 20.6.54
3018          */
3019         bp->pf.func_cfg_flags &=
3020                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3021                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3022         bp->pf.func_cfg_flags |=
3023                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3024         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3025         if (rc)
3026                 return rc;
3027
3028         /*
3029          * Now, create and register a buffer to hold forwarded VF requests
3030          */
3031         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3032         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3033                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3034         if (bp->pf.vf_req_buf == NULL) {
3035                 rc = -ENOMEM;
3036                 goto error_free;
3037         }
3038         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3039                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3040         for (i = 0; i < num_vfs; i++)
3041                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3042                                         (i * HWRM_MAX_REQ_LEN);
3043
3044         rc = bnxt_hwrm_func_buf_rgtr(bp);
3045         if (rc)
3046                 goto error_free;
3047
3048         populate_vf_func_cfg_req(bp, &req, num_vfs);
3049
3050         bp->pf.active_vfs = 0;
3051         for (i = 0; i < num_vfs; i++) {
3052                 add_random_mac_if_needed(bp, &req, i);
3053
3054                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3055                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3056                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3057                 rc = bnxt_hwrm_send_message(bp,
3058                                             &req,
3059                                             sizeof(req),
3060                                             BNXT_USE_CHIMP_MB);
3061
3062                 /* Clear enable flag for next pass */
3063                 req.enables &= ~rte_cpu_to_le_32(
3064                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3065
3066                 if (rc || resp->error_code) {
3067                         PMD_DRV_LOG(ERR,
3068                                 "Failed to initizlie VF %d\n", i);
3069                         PMD_DRV_LOG(ERR,
3070                                 "Not all VFs available. (%d, %d)\n",
3071                                 rc, resp->error_code);
3072                         HWRM_UNLOCK();
3073                         break;
3074                 }
3075
3076                 HWRM_UNLOCK();
3077
3078                 reserve_resources_from_vf(bp, &req, i);
3079                 bp->pf.active_vfs++;
3080                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3081         }
3082
3083         /*
3084          * Now configure the PF to use "the rest" of the resources
3085          * We're using STD_TX_RING_MODE here though which will limit the TX
3086          * rings.  This will allow QoS to function properly.  Not setting this
3087          * will cause PF rings to break bandwidth settings.
3088          */
3089         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3090         if (rc)
3091                 goto error_free;
3092
3093         rc = update_pf_resource_max(bp);
3094         if (rc)
3095                 goto error_free;
3096
3097         return rc;
3098
3099 error_free:
3100         bnxt_hwrm_func_buf_unrgtr(bp);
3101         return rc;
3102 }
3103
3104 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3105 {
3106         struct hwrm_func_cfg_input req = {0};
3107         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3108         int rc;
3109
3110         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3111
3112         req.fid = rte_cpu_to_le_16(0xffff);
3113         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3114         req.evb_mode = bp->pf.evb_mode;
3115
3116         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3117         HWRM_CHECK_RESULT();
3118         HWRM_UNLOCK();
3119
3120         return rc;
3121 }
3122
3123 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3124                                 uint8_t tunnel_type)
3125 {
3126         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3127         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3128         int rc = 0;
3129
3130         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3131         req.tunnel_type = tunnel_type;
3132         req.tunnel_dst_port_val = port;
3133         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3134         HWRM_CHECK_RESULT();
3135
3136         switch (tunnel_type) {
3137         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3138                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3139                 bp->vxlan_port = port;
3140                 break;
3141         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3142                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3143                 bp->geneve_port = port;
3144                 break;
3145         default:
3146                 break;
3147         }
3148
3149         HWRM_UNLOCK();
3150
3151         return rc;
3152 }
3153
3154 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3155                                 uint8_t tunnel_type)
3156 {
3157         struct hwrm_tunnel_dst_port_free_input req = {0};
3158         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3159         int rc = 0;
3160
3161         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3162
3163         req.tunnel_type = tunnel_type;
3164         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3165         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3166
3167         HWRM_CHECK_RESULT();
3168         HWRM_UNLOCK();
3169
3170         return rc;
3171 }
3172
3173 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3174                                         uint32_t flags)
3175 {
3176         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3177         struct hwrm_func_cfg_input req = {0};
3178         int rc;
3179
3180         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3181
3182         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3183         req.flags = rte_cpu_to_le_32(flags);
3184         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3185
3186         HWRM_CHECK_RESULT();
3187         HWRM_UNLOCK();
3188
3189         return rc;
3190 }
3191
3192 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3193 {
3194         uint32_t *flag = flagp;
3195
3196         vnic->flags = *flag;
3197 }
3198
3199 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3200 {
3201         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3202 }
3203
3204 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3205 {
3206         int rc = 0;
3207         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3208         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3209
3210         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3211
3212         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3213         req.req_buf_page_size = rte_cpu_to_le_16(
3214                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3215         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3216         req.req_buf_page_addr0 =
3217                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3218         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3219                 PMD_DRV_LOG(ERR,
3220                         "unable to map buffer address to physical memory\n");
3221                 return -ENOMEM;
3222         }
3223
3224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3225
3226         HWRM_CHECK_RESULT();
3227         HWRM_UNLOCK();
3228
3229         return rc;
3230 }
3231
3232 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3233 {
3234         int rc = 0;
3235         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3236         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3237
3238         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3239                 return 0;
3240
3241         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3242
3243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3244
3245         HWRM_CHECK_RESULT();
3246         HWRM_UNLOCK();
3247
3248         return rc;
3249 }
3250
3251 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3252 {
3253         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3254         struct hwrm_func_cfg_input req = {0};
3255         int rc;
3256
3257         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3258
3259         req.fid = rte_cpu_to_le_16(0xffff);
3260         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3261         req.enables = rte_cpu_to_le_32(
3262                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3263         req.async_event_cr = rte_cpu_to_le_16(
3264                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3265         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3266
3267         HWRM_CHECK_RESULT();
3268         HWRM_UNLOCK();
3269
3270         return rc;
3271 }
3272
3273 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3274 {
3275         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3276         struct hwrm_func_vf_cfg_input req = {0};
3277         int rc;
3278
3279         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3280
3281         req.enables = rte_cpu_to_le_32(
3282                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3283         req.async_event_cr = rte_cpu_to_le_16(
3284                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3286
3287         HWRM_CHECK_RESULT();
3288         HWRM_UNLOCK();
3289
3290         return rc;
3291 }
3292
3293 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3294 {
3295         struct hwrm_func_cfg_input req = {0};
3296         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3297         uint16_t dflt_vlan, fid;
3298         uint32_t func_cfg_flags;
3299         int rc = 0;
3300
3301         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3302
3303         if (is_vf) {
3304                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3305                 fid = bp->pf.vf_info[vf].fid;
3306                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3307         } else {
3308                 fid = rte_cpu_to_le_16(0xffff);
3309                 func_cfg_flags = bp->pf.func_cfg_flags;
3310                 dflt_vlan = bp->vlan;
3311         }
3312
3313         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3314         req.fid = rte_cpu_to_le_16(fid);
3315         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3316         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3317
3318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3319
3320         HWRM_CHECK_RESULT();
3321         HWRM_UNLOCK();
3322
3323         return rc;
3324 }
3325
3326 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3327                         uint16_t max_bw, uint16_t enables)
3328 {
3329         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3330         struct hwrm_func_cfg_input req = {0};
3331         int rc;
3332
3333         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3334
3335         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3336         req.enables |= rte_cpu_to_le_32(enables);
3337         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3338         req.max_bw = rte_cpu_to_le_32(max_bw);
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340
3341         HWRM_CHECK_RESULT();
3342         HWRM_UNLOCK();
3343
3344         return rc;
3345 }
3346
3347 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3348 {
3349         struct hwrm_func_cfg_input req = {0};
3350         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3351         int rc = 0;
3352
3353         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3354
3355         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3356         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3357         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3358         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3359
3360         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3361
3362         HWRM_CHECK_RESULT();
3363         HWRM_UNLOCK();
3364
3365         return rc;
3366 }
3367
3368 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3369 {
3370         int rc;
3371
3372         if (BNXT_PF(bp))
3373                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3374         else
3375                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3376
3377         return rc;
3378 }
3379
3380 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3381                               void *encaped, size_t ec_size)
3382 {
3383         int rc = 0;
3384         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3385         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3386
3387         if (ec_size > sizeof(req.encap_request))
3388                 return -1;
3389
3390         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3391
3392         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3393         memcpy(req.encap_request, encaped, ec_size);
3394
3395         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3396
3397         HWRM_CHECK_RESULT();
3398         HWRM_UNLOCK();
3399
3400         return rc;
3401 }
3402
3403 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3404                                        struct rte_ether_addr *mac)
3405 {
3406         struct hwrm_func_qcfg_input req = {0};
3407         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3408         int rc;
3409
3410         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3411
3412         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3413         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3414
3415         HWRM_CHECK_RESULT();
3416
3417         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3418
3419         HWRM_UNLOCK();
3420
3421         return rc;
3422 }
3423
3424 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3425                             void *encaped, size_t ec_size)
3426 {
3427         int rc = 0;
3428         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3429         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3430
3431         if (ec_size > sizeof(req.encap_request))
3432                 return -1;
3433
3434         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3435
3436         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3437         memcpy(req.encap_request, encaped, ec_size);
3438
3439         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3440
3441         HWRM_CHECK_RESULT();
3442         HWRM_UNLOCK();
3443
3444         return rc;
3445 }
3446
3447 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3448                          struct rte_eth_stats *stats, uint8_t rx)
3449 {
3450         int rc = 0;
3451         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3452         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3453
3454         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3455
3456         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3457
3458         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3459
3460         HWRM_CHECK_RESULT();
3461
3462         if (rx) {
3463                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3464                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3465                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3466                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3467                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3468                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3469                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3470                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3471         } else {
3472                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3473                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3474                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3475                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3476                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3477                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3478         }
3479
3480
3481         HWRM_UNLOCK();
3482
3483         return rc;
3484 }
3485
3486 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3487 {
3488         struct hwrm_port_qstats_input req = {0};
3489         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3490         struct bnxt_pf_info *pf = &bp->pf;
3491         int rc;
3492
3493         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3494
3495         req.port_id = rte_cpu_to_le_16(pf->port_id);
3496         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3497         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3499
3500         HWRM_CHECK_RESULT();
3501         HWRM_UNLOCK();
3502
3503         return rc;
3504 }
3505
3506 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3507 {
3508         struct hwrm_port_clr_stats_input req = {0};
3509         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3510         struct bnxt_pf_info *pf = &bp->pf;
3511         int rc;
3512
3513         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3514         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3515             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3516                 return 0;
3517
3518         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3519
3520         req.port_id = rte_cpu_to_le_16(pf->port_id);
3521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3522
3523         HWRM_CHECK_RESULT();
3524         HWRM_UNLOCK();
3525
3526         return rc;
3527 }
3528
3529 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3530 {
3531         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3532         struct hwrm_port_led_qcaps_input req = {0};
3533         int rc;
3534
3535         if (BNXT_VF(bp))
3536                 return 0;
3537
3538         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3539         req.port_id = bp->pf.port_id;
3540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3541
3542         HWRM_CHECK_RESULT();
3543
3544         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3545                 unsigned int i;
3546
3547                 bp->num_leds = resp->num_leds;
3548                 memcpy(bp->leds, &resp->led0_id,
3549                         sizeof(bp->leds[0]) * bp->num_leds);
3550                 for (i = 0; i < bp->num_leds; i++) {
3551                         struct bnxt_led_info *led = &bp->leds[i];
3552
3553                         uint16_t caps = led->led_state_caps;
3554
3555                         if (!led->led_group_id ||
3556                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3557                                 bp->num_leds = 0;
3558                                 break;
3559                         }
3560                 }
3561         }
3562
3563         HWRM_UNLOCK();
3564
3565         return rc;
3566 }
3567
3568 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3569 {
3570         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3571         struct hwrm_port_led_cfg_input req = {0};
3572         struct bnxt_led_cfg *led_cfg;
3573         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3574         uint16_t duration = 0;
3575         int rc, i;
3576
3577         if (!bp->num_leds || BNXT_VF(bp))
3578                 return -EOPNOTSUPP;
3579
3580         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3581
3582         if (led_on) {
3583                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3584                 duration = rte_cpu_to_le_16(500);
3585         }
3586         req.port_id = bp->pf.port_id;
3587         req.num_leds = bp->num_leds;
3588         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3589         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3590                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3591                 led_cfg->led_id = bp->leds[i].led_id;
3592                 led_cfg->led_state = led_state;
3593                 led_cfg->led_blink_on = duration;
3594                 led_cfg->led_blink_off = duration;
3595                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3596         }
3597
3598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3599
3600         HWRM_CHECK_RESULT();
3601         HWRM_UNLOCK();
3602
3603         return rc;
3604 }
3605
3606 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3607                                uint32_t *length)
3608 {
3609         int rc;
3610         struct hwrm_nvm_get_dir_info_input req = {0};
3611         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3612
3613         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3614
3615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3616
3617         HWRM_CHECK_RESULT();
3618
3619         *entries = rte_le_to_cpu_32(resp->entries);
3620         *length = rte_le_to_cpu_32(resp->entry_length);
3621
3622         HWRM_UNLOCK();
3623         return rc;
3624 }
3625
3626 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3627 {
3628         int rc;
3629         uint32_t dir_entries;
3630         uint32_t entry_length;
3631         uint8_t *buf;
3632         size_t buflen;
3633         rte_iova_t dma_handle;
3634         struct hwrm_nvm_get_dir_entries_input req = {0};
3635         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3636
3637         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3638         if (rc != 0)
3639                 return rc;
3640
3641         *data++ = dir_entries;
3642         *data++ = entry_length;
3643         len -= 2;
3644         memset(data, 0xff, len);
3645
3646         buflen = dir_entries * entry_length;
3647         buf = rte_malloc("nvm_dir", buflen, 0);
3648         rte_mem_lock_page(buf);
3649         if (buf == NULL)
3650                 return -ENOMEM;
3651         dma_handle = rte_mem_virt2iova(buf);
3652         if (dma_handle == RTE_BAD_IOVA) {
3653                 PMD_DRV_LOG(ERR,
3654                         "unable to map response address to physical memory\n");
3655                 return -ENOMEM;
3656         }
3657         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3658         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3659         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3660
3661         if (rc == 0)
3662                 memcpy(data, buf, len > buflen ? buflen : len);
3663
3664         rte_free(buf);
3665         HWRM_CHECK_RESULT();
3666         HWRM_UNLOCK();
3667
3668         return rc;
3669 }
3670
3671 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3672                              uint32_t offset, uint32_t length,
3673                              uint8_t *data)
3674 {
3675         int rc;
3676         uint8_t *buf;
3677         rte_iova_t dma_handle;
3678         struct hwrm_nvm_read_input req = {0};
3679         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3680
3681         buf = rte_malloc("nvm_item", length, 0);
3682         rte_mem_lock_page(buf);
3683         if (!buf)
3684                 return -ENOMEM;
3685
3686         dma_handle = rte_mem_virt2iova(buf);
3687         if (dma_handle == RTE_BAD_IOVA) {
3688                 PMD_DRV_LOG(ERR,
3689                         "unable to map response address to physical memory\n");
3690                 return -ENOMEM;
3691         }
3692         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3693         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3694         req.dir_idx = rte_cpu_to_le_16(index);
3695         req.offset = rte_cpu_to_le_32(offset);
3696         req.len = rte_cpu_to_le_32(length);
3697         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3698         if (rc == 0)
3699                 memcpy(data, buf, length);
3700
3701         rte_free(buf);
3702         HWRM_CHECK_RESULT();
3703         HWRM_UNLOCK();
3704
3705         return rc;
3706 }
3707
3708 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3709 {
3710         int rc;
3711         struct hwrm_nvm_erase_dir_entry_input req = {0};
3712         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3713
3714         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3715         req.dir_idx = rte_cpu_to_le_16(index);
3716         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3717         HWRM_CHECK_RESULT();
3718         HWRM_UNLOCK();
3719
3720         return rc;
3721 }
3722
3723
3724 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3725                           uint16_t dir_ordinal, uint16_t dir_ext,
3726                           uint16_t dir_attr, const uint8_t *data,
3727                           size_t data_len)
3728 {
3729         int rc;
3730         struct hwrm_nvm_write_input req = {0};
3731         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3732         rte_iova_t dma_handle;
3733         uint8_t *buf;
3734
3735         buf = rte_malloc("nvm_write", data_len, 0);
3736         rte_mem_lock_page(buf);
3737         if (!buf)
3738                 return -ENOMEM;
3739
3740         dma_handle = rte_mem_virt2iova(buf);
3741         if (dma_handle == RTE_BAD_IOVA) {
3742                 PMD_DRV_LOG(ERR,
3743                         "unable to map response address to physical memory\n");
3744                 return -ENOMEM;
3745         }
3746         memcpy(buf, data, data_len);
3747
3748         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3749
3750         req.dir_type = rte_cpu_to_le_16(dir_type);
3751         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3752         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3753         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3754         req.dir_data_length = rte_cpu_to_le_32(data_len);
3755         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3756
3757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3758
3759         rte_free(buf);
3760         HWRM_CHECK_RESULT();
3761         HWRM_UNLOCK();
3762
3763         return rc;
3764 }
3765
3766 static void
3767 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3768 {
3769         uint32_t *count = cbdata;
3770
3771         *count = *count + 1;
3772 }
3773
3774 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3775                                      struct bnxt_vnic_info *vnic __rte_unused)
3776 {
3777         return 0;
3778 }
3779
3780 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3781 {
3782         uint32_t count = 0;
3783
3784         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3785             &count, bnxt_vnic_count_hwrm_stub);
3786
3787         return count;
3788 }
3789
3790 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3791                                         uint16_t *vnic_ids)
3792 {
3793         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3794         struct hwrm_func_vf_vnic_ids_query_output *resp =
3795                                                 bp->hwrm_cmd_resp_addr;
3796         int rc;
3797
3798         /* First query all VNIC ids */
3799         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3800
3801         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3802         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3803         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3804
3805         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3806                 HWRM_UNLOCK();
3807                 PMD_DRV_LOG(ERR,
3808                 "unable to map VNIC ID table address to physical memory\n");
3809                 return -ENOMEM;
3810         }
3811         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3812         HWRM_CHECK_RESULT();
3813         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3814
3815         HWRM_UNLOCK();
3816
3817         return rc;
3818 }
3819
3820 /*
3821  * This function queries the VNIC IDs  for a specified VF. It then calls
3822  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3823  * Then it calls the hwrm_cb function to program this new vnic configuration.
3824  */
3825 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3826         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3827         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3828 {
3829         struct bnxt_vnic_info vnic;
3830         int rc = 0;
3831         int i, num_vnic_ids;
3832         uint16_t *vnic_ids;
3833         size_t vnic_id_sz;
3834         size_t sz;
3835
3836         /* First query all VNIC ids */
3837         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3838         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3839                         RTE_CACHE_LINE_SIZE);
3840         if (vnic_ids == NULL)
3841                 return -ENOMEM;
3842
3843         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3844                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3845
3846         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3847
3848         if (num_vnic_ids < 0)
3849                 return num_vnic_ids;
3850
3851         /* Retrieve VNIC, update bd_stall then update */
3852
3853         for (i = 0; i < num_vnic_ids; i++) {
3854                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3855                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3856                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3857                 if (rc)
3858                         break;
3859                 if (vnic.mru <= 4)      /* Indicates unallocated */
3860                         continue;
3861
3862                 vnic_cb(&vnic, cbdata);
3863
3864                 rc = hwrm_cb(bp, &vnic);
3865                 if (rc)
3866                         break;
3867         }
3868
3869         rte_free(vnic_ids);
3870
3871         return rc;
3872 }
3873
3874 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3875                                               bool on)
3876 {
3877         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3878         struct hwrm_func_cfg_input req = {0};
3879         int rc;
3880
3881         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3882
3883         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3884         req.enables |= rte_cpu_to_le_32(
3885                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3886         req.vlan_antispoof_mode = on ?
3887                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3888                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3889         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3890
3891         HWRM_CHECK_RESULT();
3892         HWRM_UNLOCK();
3893
3894         return rc;
3895 }
3896
3897 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3898 {
3899         struct bnxt_vnic_info vnic;
3900         uint16_t *vnic_ids;
3901         size_t vnic_id_sz;
3902         int num_vnic_ids, i;
3903         size_t sz;
3904         int rc;
3905
3906         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3907         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3908                         RTE_CACHE_LINE_SIZE);
3909         if (vnic_ids == NULL)
3910                 return -ENOMEM;
3911
3912         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3913                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3914
3915         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3916         if (rc <= 0)
3917                 goto exit;
3918         num_vnic_ids = rc;
3919
3920         /*
3921          * Loop through to find the default VNIC ID.
3922          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3923          * by sending the hwrm_func_qcfg command to the firmware.
3924          */
3925         for (i = 0; i < num_vnic_ids; i++) {
3926                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3927                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3928                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3929                                         bp->pf.first_vf_id + vf);
3930                 if (rc)
3931                         goto exit;
3932                 if (vnic.func_default) {
3933                         rte_free(vnic_ids);
3934                         return vnic.fw_vnic_id;
3935                 }
3936         }
3937         /* Could not find a default VNIC. */
3938         PMD_DRV_LOG(ERR, "No default VNIC\n");
3939 exit:
3940         rte_free(vnic_ids);
3941         return rc;
3942 }
3943
3944 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3945                          uint16_t dst_id,
3946                          struct bnxt_filter_info *filter)
3947 {
3948         int rc = 0;
3949         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3950         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3951         uint32_t enables = 0;
3952
3953         if (filter->fw_em_filter_id != UINT64_MAX)
3954                 bnxt_hwrm_clear_em_filter(bp, filter);
3955
3956         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3957
3958         req.flags = rte_cpu_to_le_32(filter->flags);
3959
3960         enables = filter->enables |
3961               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3962         req.dst_id = rte_cpu_to_le_16(dst_id);
3963
3964         if (filter->ip_addr_type) {
3965                 req.ip_addr_type = filter->ip_addr_type;
3966                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3967         }
3968         if (enables &
3969             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3970                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3971         if (enables &
3972             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3973                 memcpy(req.src_macaddr, filter->src_macaddr,
3974                        RTE_ETHER_ADDR_LEN);
3975         if (enables &
3976             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3977                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3978                        RTE_ETHER_ADDR_LEN);
3979         if (enables &
3980             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3981                 req.ovlan_vid = filter->l2_ovlan;
3982         if (enables &
3983             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3984                 req.ivlan_vid = filter->l2_ivlan;
3985         if (enables &
3986             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3987                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3988         if (enables &
3989             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3990                 req.ip_protocol = filter->ip_protocol;
3991         if (enables &
3992             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3993                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3994         if (enables &
3995             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3996                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3997         if (enables &
3998             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3999                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4000         if (enables &
4001             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4002                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4003         if (enables &
4004             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4005                 req.mirror_vnic_id = filter->mirror_vnic_id;
4006
4007         req.enables = rte_cpu_to_le_32(enables);
4008
4009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4010
4011         HWRM_CHECK_RESULT();
4012
4013         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4014         HWRM_UNLOCK();
4015
4016         return rc;
4017 }
4018
4019 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4020 {
4021         int rc = 0;
4022         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4023         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4024
4025         if (filter->fw_em_filter_id == UINT64_MAX)
4026                 return 0;
4027
4028         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4029         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4030
4031         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4032
4033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4034
4035         HWRM_CHECK_RESULT();
4036         HWRM_UNLOCK();
4037
4038         filter->fw_em_filter_id = UINT64_MAX;
4039         filter->fw_l2_filter_id = UINT64_MAX;
4040
4041         return 0;
4042 }
4043
4044 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4045                          uint16_t dst_id,
4046                          struct bnxt_filter_info *filter)
4047 {
4048         int rc = 0;
4049         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4050         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4051                                                 bp->hwrm_cmd_resp_addr;
4052         uint32_t enables = 0;
4053
4054         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4055                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4056
4057         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4058
4059         req.flags = rte_cpu_to_le_32(filter->flags);
4060
4061         enables = filter->enables |
4062               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4063         req.dst_id = rte_cpu_to_le_16(dst_id);
4064
4065
4066         if (filter->ip_addr_type) {
4067                 req.ip_addr_type = filter->ip_addr_type;
4068                 enables |=
4069                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4070         }
4071         if (enables &
4072             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4073                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4074         if (enables &
4075             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4076                 memcpy(req.src_macaddr, filter->src_macaddr,
4077                        RTE_ETHER_ADDR_LEN);
4078         //if (enables &
4079             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4080                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4081                        //RTE_ETHER_ADDR_LEN);
4082         if (enables &
4083             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4084                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4085         if (enables &
4086             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4087                 req.ip_protocol = filter->ip_protocol;
4088         if (enables &
4089             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4090                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4091         if (enables &
4092             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4093                 req.src_ipaddr_mask[0] =
4094                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4095         if (enables &
4096             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4097                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4098         if (enables &
4099             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4100                 req.dst_ipaddr_mask[0] =
4101                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4102         if (enables &
4103             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4104                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4105         if (enables &
4106             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4107                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4108         if (enables &
4109             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4110                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4111         if (enables &
4112             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4113                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4114         if (enables &
4115             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4116                 req.mirror_vnic_id = filter->mirror_vnic_id;
4117
4118         req.enables = rte_cpu_to_le_32(enables);
4119
4120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4121
4122         HWRM_CHECK_RESULT();
4123
4124         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4125         HWRM_UNLOCK();
4126
4127         return rc;
4128 }
4129
4130 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4131                                 struct bnxt_filter_info *filter)
4132 {
4133         int rc = 0;
4134         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4135         struct hwrm_cfa_ntuple_filter_free_output *resp =
4136                                                 bp->hwrm_cmd_resp_addr;
4137
4138         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4139                 return 0;
4140
4141         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4142
4143         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4144
4145         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4146
4147         HWRM_CHECK_RESULT();
4148         HWRM_UNLOCK();
4149
4150         filter->fw_ntuple_filter_id = UINT64_MAX;
4151
4152         return 0;
4153 }
4154
4155 static int
4156 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4157 {
4158         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4159         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4160         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4161         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4162         uint16_t *ring_tbl = vnic->rss_table;
4163         int nr_ctxs = vnic->num_lb_ctxts;
4164         int max_rings = bp->rx_nr_rings;
4165         int i, j, k, cnt;
4166         int rc = 0;
4167
4168         for (i = 0, k = 0; i < nr_ctxs; i++) {
4169                 struct bnxt_rx_ring_info *rxr;
4170                 struct bnxt_cp_ring_info *cpr;
4171
4172                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4173
4174                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4175                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4176                 req.hash_mode_flags = vnic->hash_mode;
4177
4178                 req.ring_grp_tbl_addr =
4179                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4180                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4181                                      2 * sizeof(*ring_tbl));
4182                 req.hash_key_tbl_addr =
4183                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4184
4185                 req.ring_table_pair_index = i;
4186                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4187
4188                 for (j = 0; j < 64; j++) {
4189                         uint16_t ring_id;
4190
4191                         /* Find next active ring. */
4192                         for (cnt = 0; cnt < max_rings; cnt++) {
4193                                 if (rx_queue_state[k] !=
4194                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4195                                         break;
4196                                 if (++k == max_rings)
4197                                         k = 0;
4198                         }
4199
4200                         /* Return if no rings are active. */
4201                         if (cnt == max_rings)
4202                                 return 0;
4203
4204                         /* Add rx/cp ring pair to RSS table. */
4205                         rxr = rxqs[k]->rx_ring;
4206                         cpr = rxqs[k]->cp_ring;
4207
4208                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4209                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4210                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4211                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4212
4213                         if (++k == max_rings)
4214                                 k = 0;
4215                 }
4216                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4217                                             BNXT_USE_CHIMP_MB);
4218
4219                 HWRM_CHECK_RESULT();
4220                 HWRM_UNLOCK();
4221         }
4222
4223         return rc;
4224 }
4225
4226 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4227 {
4228         unsigned int rss_idx, fw_idx, i;
4229
4230         if (!(vnic->rss_table && vnic->hash_type))
4231                 return 0;
4232
4233         if (BNXT_CHIP_THOR(bp))
4234                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4235
4236         /*
4237          * Fill the RSS hash & redirection table with
4238          * ring group ids for all VNICs
4239          */
4240         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4241                 rss_idx++, fw_idx++) {
4242                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4243                         fw_idx %= bp->rx_cp_nr_rings;
4244                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4245                                 break;
4246                         fw_idx++;
4247                 }
4248                 if (i == bp->rx_cp_nr_rings)
4249                         return 0;
4250                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4251         }
4252         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4253 }
4254
4255 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4256         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4257 {
4258         uint16_t flags;
4259
4260         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4261
4262         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4263         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4264
4265         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4266         req->num_cmpl_dma_aggr_during_int =
4267                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4268
4269         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4270
4271         /* min timer set to 1/2 of interrupt timer */
4272         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4273
4274         /* buf timer set to 1/4 of interrupt timer */
4275         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4276
4277         req->cmpl_aggr_dma_tmr_during_int =
4278                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4279
4280         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4281                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4282         req->flags = rte_cpu_to_le_16(flags);
4283 }
4284
4285 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4286                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4287 {
4288         struct hwrm_ring_aggint_qcaps_input req = {0};
4289         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4290         uint32_t enables;
4291         uint16_t flags;
4292         int rc;
4293
4294         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4296         HWRM_CHECK_RESULT();
4297
4298         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4299         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4300
4301         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4302                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4303         agg_req->flags = rte_cpu_to_le_16(flags);
4304         enables =
4305          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4306          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4307         agg_req->enables = rte_cpu_to_le_32(enables);
4308
4309         HWRM_UNLOCK();
4310         return rc;
4311 }
4312
4313 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4314                         struct bnxt_coal *coal, uint16_t ring_id)
4315 {
4316         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4317         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4318                                                 bp->hwrm_cmd_resp_addr;
4319         int rc;
4320
4321         /* Set ring coalesce parameters only for 100G NICs */
4322         if (BNXT_CHIP_THOR(bp)) {
4323                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4324                         return -1;
4325         } else if (bnxt_stratus_device(bp)) {
4326                 bnxt_hwrm_set_coal_params(coal, &req);
4327         } else {
4328                 return 0;
4329         }
4330
4331         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4332         req.ring_id = rte_cpu_to_le_16(ring_id);
4333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4334         HWRM_CHECK_RESULT();
4335         HWRM_UNLOCK();
4336         return 0;
4337 }
4338
4339 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4340 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4341 {
4342         struct hwrm_func_backing_store_qcaps_input req = {0};
4343         struct hwrm_func_backing_store_qcaps_output *resp =
4344                 bp->hwrm_cmd_resp_addr;
4345         int rc;
4346
4347         if (!BNXT_CHIP_THOR(bp) ||
4348             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4349             BNXT_VF(bp) ||
4350             bp->ctx)
4351                 return 0;
4352
4353         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4355         HWRM_CHECK_RESULT_SILENT();
4356
4357         if (!rc) {
4358                 struct bnxt_ctx_pg_info *ctx_pg;
4359                 struct bnxt_ctx_mem_info *ctx;
4360                 int total_alloc_len;
4361                 int i;
4362
4363                 total_alloc_len = sizeof(*ctx);
4364                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4365                                  RTE_CACHE_LINE_SIZE);
4366                 if (!ctx) {
4367                         rc = -ENOMEM;
4368                         goto ctx_err;
4369                 }
4370                 memset(ctx, 0, total_alloc_len);
4371
4372                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4373                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4374                                     RTE_CACHE_LINE_SIZE);
4375                 if (!ctx_pg) {
4376                         rc = -ENOMEM;
4377                         goto ctx_err;
4378                 }
4379                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4380                         ctx->tqm_mem[i] = ctx_pg;
4381
4382                 bp->ctx = ctx;
4383                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4384                 ctx->qp_min_qp1_entries =
4385                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4386                 ctx->qp_max_l2_entries =
4387                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4388                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4389                 ctx->srq_max_l2_entries =
4390                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4391                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4392                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4393                 ctx->cq_max_l2_entries =
4394                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4395                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4396                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4397                 ctx->vnic_max_vnic_entries =
4398                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4399                 ctx->vnic_max_ring_table_entries =
4400                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4401                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4402                 ctx->stat_max_entries =
4403                         rte_le_to_cpu_32(resp->stat_max_entries);
4404                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4405                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4406                 ctx->tqm_min_entries_per_ring =
4407                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4408                 ctx->tqm_max_entries_per_ring =
4409                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4410                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4411                 if (!ctx->tqm_entries_multiple)
4412                         ctx->tqm_entries_multiple = 1;
4413                 ctx->mrav_max_entries =
4414                         rte_le_to_cpu_32(resp->mrav_max_entries);
4415                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4416                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4417                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4418         } else {
4419                 rc = 0;
4420         }
4421 ctx_err:
4422         HWRM_UNLOCK();
4423         return rc;
4424 }
4425
4426 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4427 {
4428         struct hwrm_func_backing_store_cfg_input req = {0};
4429         struct hwrm_func_backing_store_cfg_output *resp =
4430                 bp->hwrm_cmd_resp_addr;
4431         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4432         struct bnxt_ctx_pg_info *ctx_pg;
4433         uint32_t *num_entries;
4434         uint64_t *pg_dir;
4435         uint8_t *pg_attr;
4436         uint32_t ena;
4437         int i, rc;
4438
4439         if (!ctx)
4440                 return 0;
4441
4442         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4443         req.enables = rte_cpu_to_le_32(enables);
4444
4445         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4446                 ctx_pg = &ctx->qp_mem;
4447                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4448                 req.qp_num_qp1_entries =
4449                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4450                 req.qp_num_l2_entries =
4451                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4452                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4453                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4454                                       &req.qpc_pg_size_qpc_lvl,
4455                                       &req.qpc_page_dir);
4456         }
4457
4458         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4459                 ctx_pg = &ctx->srq_mem;
4460                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4461                 req.srq_num_l2_entries =
4462                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4463                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4464                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4465                                       &req.srq_pg_size_srq_lvl,
4466                                       &req.srq_page_dir);
4467         }
4468
4469         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4470                 ctx_pg = &ctx->cq_mem;
4471                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4472                 req.cq_num_l2_entries =
4473                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4474                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4475                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4476                                       &req.cq_pg_size_cq_lvl,
4477                                       &req.cq_page_dir);
4478         }
4479
4480         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4481                 ctx_pg = &ctx->vnic_mem;
4482                 req.vnic_num_vnic_entries =
4483                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4484                 req.vnic_num_ring_table_entries =
4485                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4486                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4487                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4488                                       &req.vnic_pg_size_vnic_lvl,
4489                                       &req.vnic_page_dir);
4490         }
4491
4492         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4493                 ctx_pg = &ctx->stat_mem;
4494                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4495                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4496                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4497                                       &req.stat_pg_size_stat_lvl,
4498                                       &req.stat_page_dir);
4499         }
4500
4501         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4502         num_entries = &req.tqm_sp_num_entries;
4503         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4504         pg_dir = &req.tqm_sp_page_dir;
4505         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4506         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4507                 if (!(enables & ena))
4508                         continue;
4509
4510                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4511
4512                 ctx_pg = ctx->tqm_mem[i];
4513                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4514                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4515         }
4516
4517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4518         HWRM_CHECK_RESULT();
4519         HWRM_UNLOCK();
4520
4521         return rc;
4522 }
4523
4524 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4525 {
4526         struct hwrm_port_qstats_ext_input req = {0};
4527         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4528         struct bnxt_pf_info *pf = &bp->pf;
4529         int rc;
4530
4531         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4532               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4533                 return 0;
4534
4535         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4536
4537         req.port_id = rte_cpu_to_le_16(pf->port_id);
4538         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4539                 req.tx_stat_host_addr =
4540                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4541                 req.tx_stat_size =
4542                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4543         }
4544         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4545                 req.rx_stat_host_addr =
4546                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4547                 req.rx_stat_size =
4548                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4549         }
4550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4551
4552         if (rc) {
4553                 bp->fw_rx_port_stats_ext_size = 0;
4554                 bp->fw_tx_port_stats_ext_size = 0;
4555         } else {
4556                 bp->fw_rx_port_stats_ext_size =
4557                         rte_le_to_cpu_16(resp->rx_stat_size);
4558                 bp->fw_tx_port_stats_ext_size =
4559                         rte_le_to_cpu_16(resp->tx_stat_size);
4560         }
4561
4562         HWRM_CHECK_RESULT();
4563         HWRM_UNLOCK();
4564
4565         return rc;
4566 }
4567
4568 int
4569 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4570 {
4571         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4572         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4573                 bp->hwrm_cmd_resp_addr;
4574         int rc = 0;
4575
4576         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4577         req.tunnel_type = type;
4578         req.dest_fid = bp->fw_fid;
4579         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4580         HWRM_CHECK_RESULT();
4581
4582         HWRM_UNLOCK();
4583
4584         return rc;
4585 }
4586
4587 int
4588 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4589 {
4590         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4591         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4592                 bp->hwrm_cmd_resp_addr;
4593         int rc = 0;
4594
4595         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4596         req.tunnel_type = type;
4597         req.dest_fid = bp->fw_fid;
4598         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4599         HWRM_CHECK_RESULT();
4600
4601         HWRM_UNLOCK();
4602
4603         return rc;
4604 }
4605
4606 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4607 {
4608         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4609         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4610                 bp->hwrm_cmd_resp_addr;
4611         int rc = 0;
4612
4613         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4614         req.src_fid = bp->fw_fid;
4615         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4616         HWRM_CHECK_RESULT();
4617
4618         if (type)
4619                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4620
4621         HWRM_UNLOCK();
4622
4623         return rc;
4624 }
4625
4626 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4627                                    uint16_t *dst_fid)
4628 {
4629         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4630         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4631                 bp->hwrm_cmd_resp_addr;
4632         int rc = 0;
4633
4634         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4635         req.src_fid = bp->fw_fid;
4636         req.tunnel_type = tun_type;
4637         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4638         HWRM_CHECK_RESULT();
4639
4640         if (dst_fid)
4641                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4642
4643         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4644
4645         HWRM_UNLOCK();
4646
4647         return rc;
4648 }
4649
4650 int bnxt_hwrm_set_mac(struct bnxt *bp)
4651 {
4652         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4653         struct hwrm_func_vf_cfg_input req = {0};
4654         int rc = 0;
4655
4656         if (!BNXT_VF(bp))
4657                 return 0;
4658
4659         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4660
4661         req.enables =
4662                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4663         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4664
4665         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4666
4667         HWRM_CHECK_RESULT();
4668
4669         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4670         HWRM_UNLOCK();
4671
4672         return rc;
4673 }
4674
4675 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4676 {
4677         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4678         struct hwrm_func_drv_if_change_input req = {0};
4679         uint32_t flags;
4680         int rc;
4681
4682         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4683                 return 0;
4684
4685         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4686          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4687          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4688          */
4689         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4690                 return 0;
4691
4692         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4693
4694         if (up)
4695                 req.flags =
4696                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4697
4698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4699
4700         HWRM_CHECK_RESULT();
4701         flags = rte_le_to_cpu_32(resp->flags);
4702         HWRM_UNLOCK();
4703
4704         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4705                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4706                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4707         }
4708
4709         return 0;
4710 }
4711
4712 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4713 {
4714         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4715         struct bnxt_error_recovery_info *info = bp->recovery_info;
4716         struct hwrm_error_recovery_qcfg_input req = {0};
4717         uint32_t flags = 0;
4718         unsigned int i;
4719         int rc;
4720
4721         /* Older FW does not have error recovery support */
4722         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4723                 return 0;
4724
4725         if (!info) {
4726                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4727                                    sizeof(*info), 0);
4728                 bp->recovery_info = info;
4729                 if (info == NULL)
4730                         return -ENOMEM;
4731         } else {
4732                 memset(info, 0, sizeof(*info));
4733         }
4734
4735         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4736
4737         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4738
4739         HWRM_CHECK_RESULT();
4740
4741         flags = rte_le_to_cpu_32(resp->flags);
4742         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4743                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4744         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4745                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4746
4747         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4748             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4749                 rc = -EINVAL;
4750                 goto err;
4751         }
4752
4753         /* FW returned values are in units of 100msec */
4754         info->driver_polling_freq =
4755                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4756         info->master_func_wait_period =
4757                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4758         info->normal_func_wait_period =
4759                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4760         info->master_func_wait_period_after_reset =
4761                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4762         info->max_bailout_time_after_reset =
4763                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4764         info->status_regs[BNXT_FW_STATUS_REG] =
4765                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4766         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4767                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4768         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4769                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4770         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4771                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4772         info->reg_array_cnt =
4773                 rte_le_to_cpu_32(resp->reg_array_cnt);
4774
4775         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4776                 rc = -EINVAL;
4777                 goto err;
4778         }
4779
4780         for (i = 0; i < info->reg_array_cnt; i++) {
4781                 info->reset_reg[i] =
4782                         rte_le_to_cpu_32(resp->reset_reg[i]);
4783                 info->reset_reg_val[i] =
4784                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4785                 info->delay_after_reset[i] =
4786                         resp->delay_after_reset[i];
4787         }
4788 err:
4789         HWRM_UNLOCK();
4790
4791         if (rc) {
4792                 rte_free(bp->recovery_info);
4793                 bp->recovery_info = NULL;
4794         }
4795         return rc;
4796 }