drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
  78  * HWRM command times out, or a negative error code if the HWRM
  79  * command was failed by the FW.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         timeout = bp->hwrm_cmd_timeout;
 104
 105         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 106             msg_len > bp->max_req_len) {
 107                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 108
 109                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 110                 memcpy(short_cmd_req, req, msg_len);
 111
 112                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 113                 short_input.signature = rte_cpu_to_le_16(
 114                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 115                 short_input.size = rte_cpu_to_le_16(msg_len);
 116                 short_input.req_addr =
 117                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 118
 119                 data = (uint32_t *)&short_input;
 120                 msg_len = sizeof(short_input);
 121
 122                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 123         }
 124
 125         /* Write request msg to hwrm channel */
 126         for (i = 0; i < msg_len; i += 4) {
 127                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 128                 rte_write32(*data, bar);
 129                 data++;
 130         }
 131
 132         /* Zero the rest of the request space */
 133         for (; i < max_req_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 135                 rte_write32(0, bar);
 136         }
 137
 138         /* Ring channel doorbell */
 139         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 140         rte_write32(1, bar);
 141         /*
 142          * Make sure the channel doorbell ring command complete before
 143          * reading the response to avoid getting stale or invalid
 144          * responses.
 145          */
 146         rte_io_mb();
 147
 148         /* Poll for the valid bit */
 149         for (i = 0; i < timeout; i++) {
 150                 /* Sanity check on the resp->resp_len */
 151                 rte_cio_rmb();
 152                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 153                         /* Last byte of resp contains the valid key */
 154                         valid = (uint8_t *)resp + resp->resp_len - 1;
 155                         if (*valid == HWRM_RESP_VALID_KEY)
 156                                 break;
 157                 }
 158                 rte_delay_us(1);
 159         }
 160
 161         if (i >= timeout) {
 162                 /* Suppress VER_GET timeout messages during reset recovery */
 163                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 164                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 165                         return -ETIMEDOUT;
 166
 167                 PMD_DRV_LOG(ERR,
 168                             "Error(timeout) sending msg 0x%04x, seq_id %d\n",
 169                             req->req_type, req->seq_id);
 170                 return -ETIMEDOUT;
 171         }
 172         return 0;
 173 }
 174
 175 /*
 176  * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
 177  * spinlock, and does initial processing.
 178  *
 179  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 180  * releases the spinlock only if it returns. If the regular int return codes
 181  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 182  * directly, rather it should be copied and modified to suit the function.
 183  *
 184  * HWRM_UNLOCK() must be called after all response processing is completed.
 185  */
 186 #define HWRM_PREP(req, type, kong) do { \
 187         rte_spinlock_lock(&bp->hwrm_lock); \
 188         if (bp->hwrm_cmd_resp_addr == NULL) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return -EACCES; \
 191         } \
 192         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 193         (req)->req_type = rte_cpu_to_le_16(type); \
 194         (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
 195         (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 196                 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
 197         (req)->target_id = rte_cpu_to_le_16(0xffff); \
 198         (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 199 } while (0)
 200
 201 #define HWRM_CHECK_RESULT_SILENT() do {\
 202         if (rc) { \
 203                 rte_spinlock_unlock(&bp->hwrm_lock); \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 rte_spinlock_unlock(&bp->hwrm_lock); \
 209                 return rc; \
 210         } \
 211 } while (0)
 212
 213 #define HWRM_CHECK_RESULT() do {\
 214         if (rc) { \
 215                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 216                 rte_spinlock_unlock(&bp->hwrm_lock); \
 217                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 218                         rc = -EACCES; \
 219                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 220                         rc = -ENOSPC; \
 221                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 222                         rc = -EINVAL; \
 223                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 224                         rc = -ENOTSUP; \
 225                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 226                         rc = -EAGAIN; \
 227                 else if (rc > 0) \
 228                         rc = -EIO; \
 229                 return rc; \
 230         } \
 231         if (resp->error_code) { \
 232                 rc = rte_le_to_cpu_16(resp->error_code); \
 233                 if (resp->resp_len >= 16) { \
 234                         struct hwrm_err_output *tmp_hwrm_err_op = \
 235                                                 (void *)resp; \
 236                         PMD_DRV_LOG(ERR, \
 237                                 "error %d:%d:%08x:%04x\n", \
 238                                 rc, tmp_hwrm_err_op->cmd_err, \
 239                                 rte_le_to_cpu_32(\
 240                                         tmp_hwrm_err_op->opaque_0), \
 241                                 rte_le_to_cpu_16(\
 242                                         tmp_hwrm_err_op->opaque_1)); \
 243                 } else { \
 244                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 245                 } \
 246                 rte_spinlock_unlock(&bp->hwrm_lock); \
 247                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 248                         rc = -EACCES; \
 249                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 250                         rc = -ENOSPC; \
 251                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 252                         rc = -EINVAL; \
 253                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 254                         rc = -ENOTSUP; \
 255                 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
 256                         rc = -EAGAIN; \
 257                 else if (rc > 0) \
 258                         rc = -EIO; \
 259                 return rc; \
 260         } \
 261 } while (0)
 262
 263 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 264
 265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
 266                                 bool use_kong_mb,
 267                                 uint16_t msg_type,
 268                                 void *msg,
 269                                 uint32_t msg_len,
 270                                 void *resp_msg,
 271                                 uint32_t resp_len)
 272 {
 273         int rc = 0;
 274         bool mailbox = BNXT_USE_CHIMP_MB;
 275         struct input *req = msg;
 276         struct output *resp = bp->hwrm_cmd_resp_addr;
 277
 278         if (use_kong_mb)
 279                 mailbox = BNXT_USE_KONG(bp);
 280
 281         HWRM_PREP(req, msg_type, mailbox);
 282
 283         rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
 284
 285         HWRM_CHECK_RESULT();
 286
 287         if (resp_msg)
 288                 memcpy(resp_msg, resp, resp_len);
 289
 290         HWRM_UNLOCK();
 291
 292         return rc;
 293 }
 294
 295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
 296                                   bool use_kong_mb,
 297                                   uint16_t tf_type,
 298                                   uint16_t tf_subtype,
 299                                   uint32_t *tf_response_code,
 300                                   void *msg,
 301                                   uint32_t msg_len,
 302                                   void *response,
 303                                   uint32_t response_len)
 304 {
 305         int rc = 0;
 306         struct hwrm_cfa_tflib_input req = { .req_type = 0 };
 307         struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
 308         bool mailbox = BNXT_USE_CHIMP_MB;
 309
 310         if (msg_len > sizeof(req.tf_req))
 311                 return -ENOMEM;
 312
 313         if (use_kong_mb)
 314                 mailbox = BNXT_USE_KONG(bp);
 315
 316         HWRM_PREP(&req, HWRM_TF, mailbox);
 317         /* Build request using the user supplied request payload.
 318          * TLV request size is checked at build time against HWRM
 319          * request max size, thus no checking required.
 320          */
 321         req.tf_type = tf_type;
 322         req.tf_subtype = tf_subtype;
 323         memcpy(req.tf_req, msg, msg_len);
 324
 325         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
 326         HWRM_CHECK_RESULT();
 327
 328         /* Copy the resp to user provided response buffer */
 329         if (response != NULL)
 330                 /* Post process response data. We need to copy only
 331                  * the 'payload' as the HWRM data structure really is
 332                  * HWRM header + msg header + payload and the TFLIB
 333                  * only provided a payload place holder.
 334                  */
 335                 if (response_len != 0) {
 336                         memcpy(response,
 337                                resp->tf_resp,
 338                                response_len);
 339                 }
 340
 341         /* Extract the internal tflib response code */
 342         *tf_response_code = resp->tf_resp_code;
 343         HWRM_UNLOCK();
 344
 345         return rc;
 346 }
 347
 348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 353
 354         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 355         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 356         req.mask = 0;
 357
 358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 359
 360         HWRM_CHECK_RESULT();
 361         HWRM_UNLOCK();
 362
 363         return rc;
 364 }
 365
 366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 367                                  struct bnxt_vnic_info *vnic,
 368                                  uint16_t vlan_count,
 369                                  struct bnxt_vlan_table_entry *vlan_table)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 374         uint32_t mask = 0;
 375
 376         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 377                 return rc;
 378
 379         HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 380         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 381
 382         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 383                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 384         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 385                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 386
 387         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 388                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 389
 390         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 391                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 392         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 393                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 394                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 395                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 396         }
 397         if (vlan_table) {
 398                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 399                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 400                 req.vlan_tag_tbl_addr =
 401                         rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 402                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 403         }
 404         req.mask = rte_cpu_to_le_32(mask);
 405
 406         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 407
 408         HWRM_CHECK_RESULT();
 409         HWRM_UNLOCK();
 410
 411         return rc;
 412 }
 413
 414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 415                         uint16_t vlan_count,
 416                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 417 {
 418         int rc = 0;
 419         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 420         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 421                                                 bp->hwrm_cmd_resp_addr;
 422
 423         /*
 424          * Older HWRM versions did not support this command, and the set_rx_mask
 425          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 426          * removed from set_rx_mask call, and this command was added.
 427          *
 428          * This command is also present from 1.7.8.11 and higher,
 429          * as well as 1.7.8.0
 430          */
 431         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 432                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 433                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 434                                         (11)))
 435                                 return 0;
 436                 }
 437         }
 438         HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 439         req.fid = rte_cpu_to_le_16(fid);
 440
 441         req.vlan_tag_mask_tbl_addr =
 442                 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
 443         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 446
 447         HWRM_CHECK_RESULT();
 448         HWRM_UNLOCK();
 449
 450         return rc;
 451 }
 452
 453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 454                              struct bnxt_filter_info *filter)
 455 {
 456         int rc = 0;
 457         struct bnxt_filter_info *l2_filter = filter;
 458         struct bnxt_vnic_info *vnic = NULL;
 459         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 460         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 461
 462         if (filter->fw_l2_filter_id == UINT64_MAX)
 463                 return 0;
 464
 465         if (filter->matching_l2_fltr_ptr)
 466                 l2_filter = filter->matching_l2_fltr_ptr;
 467
 468         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 469                     filter, l2_filter, l2_filter->l2_ref_cnt);
 470
 471         if (l2_filter->l2_ref_cnt == 0)
 472                 return 0;
 473
 474         if (l2_filter->l2_ref_cnt > 0)
 475                 l2_filter->l2_ref_cnt--;
 476
 477         if (l2_filter->l2_ref_cnt > 0)
 478                 return 0;
 479
 480         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 481
 482         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 483
 484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 485
 486         HWRM_CHECK_RESULT();
 487         HWRM_UNLOCK();
 488
 489         filter->fw_l2_filter_id = UINT64_MAX;
 490         if (l2_filter->l2_ref_cnt == 0) {
 491                 vnic = l2_filter->vnic;
 492                 if (vnic) {
 493                         STAILQ_REMOVE(&vnic->filter, l2_filter,
 494                                       bnxt_filter_info, next);
 495                         bnxt_free_filter(bp, l2_filter);
 496                 }
 497         }
 498
 499         return 0;
 500 }
 501
 502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 503                          uint16_t dst_id,
 504                          struct bnxt_filter_info *filter)
 505 {
 506         int rc = 0;
 507         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 508         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 509         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 510         const struct rte_eth_vmdq_rx_conf *conf =
 511                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 512         uint32_t enables = 0;
 513         uint16_t j = dst_id - 1;
 514
 515         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 516         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 517             conf->pool_map[j].pools & (1UL << j)) {
 518                 PMD_DRV_LOG(DEBUG,
 519                         "Add vlan %u to vmdq pool %u\n",
 520                         conf->pool_map[j].vlan_id, j);
 521
 522                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 523                 filter->enables |=
 524                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 525                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 526         }
 527
 528         if (filter->fw_l2_filter_id != UINT64_MAX)
 529                 bnxt_hwrm_clear_l2_filter(bp, filter);
 530
 531         HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 532
 533         req.flags = rte_cpu_to_le_32(filter->flags);
 534
 535         enables = filter->enables |
 536               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 537         req.dst_id = rte_cpu_to_le_16(dst_id);
 538
 539         if (enables &
 540             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 541                 memcpy(req.l2_addr, filter->l2_addr,
 542                        RTE_ETHER_ADDR_LEN);
 543         if (enables &
 544             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 545                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 546                        RTE_ETHER_ADDR_LEN);
 547         if (enables &
 548             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 549                 req.l2_ovlan = filter->l2_ovlan;
 550         if (enables &
 551             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 552                 req.l2_ivlan = filter->l2_ivlan;
 553         if (enables &
 554             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 555                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 556         if (enables &
 557             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 558                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 559         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 560                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 561         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 562                 req.src_type = filter->src_type;
 563         if (filter->pri_hint) {
 564                 req.pri_hint = filter->pri_hint;
 565                 req.l2_filter_id_hint =
 566                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 567         }
 568
 569         req.enables = rte_cpu_to_le_32(enables);
 570
 571         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 572
 573         HWRM_CHECK_RESULT();
 574
 575         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 576         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
 577         HWRM_UNLOCK();
 578
 579         filter->l2_ref_cnt++;
 580
 581         return rc;
 582 }
 583
 584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 585 {
 586         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 588         uint32_t flags = 0;
 589         int rc;
 590
 591         if (!ptp)
 592                 return 0;
 593
 594         HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 595
 596         if (ptp->rx_filter)
 597                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 598         else
 599                 flags |=
 600                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 601         if (ptp->tx_tstamp_en)
 602                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 603         else
 604                 flags |=
 605                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 606         req.flags = rte_cpu_to_le_32(flags);
 607         req.enables = rte_cpu_to_le_32
 608                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 609         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 610
 611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 612         HWRM_UNLOCK();
 613
 614         return rc;
 615 }
 616
 617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 618 {
 619         int rc = 0;
 620         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 621         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 623
 624         if (ptp)
 625                 return 0;
 626
 627         HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 628
 629         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
 630
 631         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 632
 633         HWRM_CHECK_RESULT();
 634
 635         if (!BNXT_CHIP_THOR(bp) &&
 636             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 637                 return 0;
 638
 639         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 640                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 641
 642         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 643         if (!ptp)
 644                 return -ENOMEM;
 645
 646         if (!BNXT_CHIP_THOR(bp)) {
 647                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 648                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 649                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 650                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 651                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 652                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 653                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 654                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 655                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 656                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 657                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 658                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 659                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 660                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 661                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 662                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 663                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 664                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 665         }
 666
 667         ptp->bp = bp;
 668         bp->ptp_cfg = ptp;
 669
 670         return 0;
 671 }
 672
 673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 674 {
 675         int rc = 0;
 676         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 677         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 678         uint16_t new_max_vfs;
 679         uint32_t flags;
 680         int i;
 681
 682         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 683
 684         req.fid = rte_cpu_to_le_16(0xffff);
 685
 686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 687
 688         HWRM_CHECK_RESULT();
 689
 690         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 691         flags = rte_le_to_cpu_32(resp->flags);
 692         if (BNXT_PF(bp)) {
 693                 bp->pf->port_id = resp->port_id;
 694                 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 695                 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 696                 new_max_vfs = bp->pdev->max_vfs;
 697                 if (new_max_vfs != bp->pf->max_vfs) {
 698                         if (bp->pf->vf_info)
 699                                 rte_free(bp->pf->vf_info);
 700                         bp->pf->vf_info = rte_malloc("bnxt_vf_info",
 701                             sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
 702                         bp->pf->max_vfs = new_max_vfs;
 703                         for (i = 0; i < new_max_vfs; i++) {
 704                                 bp->pf->vf_info[i].fid =
 705                                         bp->pf->first_vf_id + i;
 706                                 bp->pf->vf_info[i].vlan_table =
 707                                         rte_zmalloc("VF VLAN table",
 708                                                     getpagesize(),
 709                                                     getpagesize());
 710                                 if (bp->pf->vf_info[i].vlan_table == NULL)
 711                                         PMD_DRV_LOG(ERR,
 712                                         "Fail to alloc VLAN table for VF %d\n",
 713                                         i);
 714                                 else
 715                                         rte_mem_lock_page(
 716                                                 bp->pf->vf_info[i].vlan_table);
 717                                 bp->pf->vf_info[i].vlan_as_table =
 718                                         rte_zmalloc("VF VLAN AS table",
 719                                                     getpagesize(),
 720                                                     getpagesize());
 721                                 if (bp->pf->vf_info[i].vlan_as_table == NULL)
 722                                         PMD_DRV_LOG(ERR,
 723                                         "Alloc VLAN AS table for VF %d fail\n",
 724                                         i);
 725                                 else
 726                                         rte_mem_lock_page(
 727                                               bp->pf->vf_info[i].vlan_as_table);
 728                                 STAILQ_INIT(&bp->pf->vf_info[i].filter);
 729                         }
 730                 }
 731         }
 732
 733         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 734         if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
 735                 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
 736                 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 737         } else {
 738                 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
 739         }
 740         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 741         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 742         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 743         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 744         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 745         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 746         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 747         if (!BNXT_CHIP_THOR(bp))
 748                 bp->max_l2_ctx += bp->max_rx_em_flows;
 749         /* TODO: For now, do not support VMDq/RFS on VFs. */
 750         if (BNXT_PF(bp)) {
 751                 if (bp->pf->max_vfs)
 752                         bp->max_vnics = 1;
 753                 else
 754                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 755         } else {
 756                 bp->max_vnics = 1;
 757         }
 758         PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
 759                     bp->max_l2_ctx, bp->max_vnics);
 760         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 761         if (BNXT_PF(bp)) {
 762                 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 763                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 764                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 765                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 766                         HWRM_UNLOCK();
 767                         bnxt_hwrm_ptp_qcfg(bp);
 768                 }
 769         }
 770
 771         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 772                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 773
 774         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 775                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
 776                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 777         }
 778
 779         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 780                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
 781
 782         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
 783                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
 784
 785         HWRM_UNLOCK();
 786
 787         return rc;
 788 }
 789
 790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 791 {
 792         int rc;
 793
 794         rc = __bnxt_hwrm_func_qcaps(bp);
 795         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 796                 rc = bnxt_alloc_ctx_mem(bp);
 797                 if (rc)
 798                         return rc;
 799
 800                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 801                 if (!rc)
 802                         bp->flags |= BNXT_FLAG_NEW_RM;
 803         }
 804
 805         /* On older FW,
 806          * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
 807          * But the error can be ignored. Return success.
 808          */
 809
 810         return 0;
 811 }
 812
 813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 815 {
 816         int rc = 0;
 817         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 818         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 819
 820         HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 821
 822         req.target_id = rte_cpu_to_le_16(0xffff);
 823
 824         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 825
 826         HWRM_CHECK_RESULT();
 827
 828         if (rte_le_to_cpu_32(resp->flags) &
 829             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 830                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 831                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 832         }
 833
 834         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 835
 836         HWRM_UNLOCK();
 837
 838         return rc;
 839 }
 840
 841 int bnxt_hwrm_func_reset(struct bnxt *bp)
 842 {
 843         int rc = 0;
 844         struct hwrm_func_reset_input req = {.req_type = 0 };
 845         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 846
 847         HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
 848
 849         req.enables = rte_cpu_to_le_32(0);
 850
 851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 852
 853         HWRM_CHECK_RESULT();
 854         HWRM_UNLOCK();
 855
 856         return rc;
 857 }
 858
 859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 860 {
 861         int rc;
 862         uint32_t flags = 0;
 863         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 864         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 865
 866         if (bp->flags & BNXT_FLAG_REGISTERED)
 867                 return 0;
 868
 869         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
 870                 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 871         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 872                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 873
 874         /* PFs and trusted VFs should indicate the support of the
 875          * Master capability on non Stingray platform
 876          */
 877         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 878                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 879
 880         HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 881         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 882                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 883         req.ver_maj = RTE_VER_YEAR;
 884         req.ver_min = RTE_VER_MONTH;
 885         req.ver_upd = RTE_VER_MINOR;
 886
 887         if (BNXT_PF(bp)) {
 888                 req.enables |= rte_cpu_to_le_32(
 889                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 890                 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
 891                        RTE_MIN(sizeof(req.vf_req_fwd),
 892                                sizeof(bp->pf->vf_req_fwd)));
 893
 894                 /*
 895                  * PF can sniff HWRM API issued by VF. This can be set up by
 896                  * linux driver and inherited by the DPDK PF driver. Clear
 897                  * this HWRM sniffer list in FW because DPDK PF driver does
 898                  * not support this.
 899                  */
 900                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 901         }
 902
 903         req.flags = rte_cpu_to_le_32(flags);
 904
 905         req.async_event_fwd[0] |=
 906                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 907                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 908                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 909                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 910                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 911         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
 912                 req.async_event_fwd[0] |=
 913                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 914         req.async_event_fwd[1] |=
 915                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 916                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 917         if (BNXT_PF(bp))
 918                 req.async_event_fwd[1] |=
 919                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 920
 921         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 922
 923         HWRM_CHECK_RESULT();
 924
 925         flags = rte_le_to_cpu_32(resp->flags);
 926         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 927                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
 928
 929         HWRM_UNLOCK();
 930
 931         bp->flags |= BNXT_FLAG_REGISTERED;
 932
 933         return rc;
 934 }
 935
 936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 937 {
 938         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 939                 return 0;
 940
 941         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 942 }
 943
 944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 945 {
 946         int rc;
 947         uint32_t flags = 0;
 948         uint32_t enables;
 949         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 950         struct hwrm_func_vf_cfg_input req = {0};
 951
 952         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 953
 954         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 955                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 956                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 957                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 958                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 959
 960         if (BNXT_HAS_RING_GRPS(bp)) {
 961                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 962                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 963         }
 964
 965         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 966         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 967                                             AGG_RING_MULTIPLIER);
 968         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 969         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 970                                               bp->tx_nr_rings +
 971                                               BNXT_NUM_ASYNC_CPR(bp));
 972         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 973         if (bp->vf_resv_strategy ==
 974             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 975                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 976                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 977                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 978                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 979                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 980                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 981         } else if (bp->vf_resv_strategy ==
 982                    HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
 983                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 984                 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
 985         }
 986
 987         if (test)
 988                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 989                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 990                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 991                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 992                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 993                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 994
 995         if (test && BNXT_HAS_RING_GRPS(bp))
 996                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 997
 998         req.flags = rte_cpu_to_le_32(flags);
 999         req.enables |= rte_cpu_to_le_32(enables);
1000
1001         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1002
1003         if (test)
1004                 HWRM_CHECK_RESULT_SILENT();
1005         else
1006                 HWRM_CHECK_RESULT();
1007
1008         HWRM_UNLOCK();
1009         return rc;
1010 }
1011
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1013 {
1014         int rc;
1015         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016         struct hwrm_func_resource_qcaps_input req = {0};
1017
1018         HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019         req.fid = rte_cpu_to_le_16(0xffff);
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT_SILENT();
1024
1025         if (BNXT_VF(bp)) {
1026                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031                 /* func_resource_qcaps does not return max_rx_em_flows.
1032                  * So use the value provided by func_qcaps.
1033                  */
1034                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035                 if (!BNXT_CHIP_THOR(bp))
1036                         bp->max_l2_ctx += bp->max_rx_em_flows;
1037                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1039         }
1040         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042         if (bp->vf_resv_strategy >
1043             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044                 bp->vf_resv_strategy =
1045                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1046
1047         HWRM_UNLOCK();
1048         return rc;
1049 }
1050
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1052 {
1053         int rc = 0;
1054         struct hwrm_ver_get_input req = {.req_type = 0 };
1055         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056         uint32_t fw_version;
1057         uint16_t max_resp_len;
1058         char type[RTE_MEMZONE_NAMESIZE];
1059         uint32_t dev_caps_cfg;
1060
1061         bp->max_req_len = HWRM_MAX_REQ_LEN;
1062         bp->hwrm_cmd_timeout = timeout;
1063         HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1064
1065         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066         req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1068
1069         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1070
1071         if (bp->flags & BNXT_FLAG_FW_RESET)
1072                 HWRM_CHECK_RESULT_SILENT();
1073         else
1074                 HWRM_CHECK_RESULT();
1075
1076         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081                      (resp->hwrm_fw_min_8b << 16) |
1082                      (resp->hwrm_fw_bld_8b << 8) |
1083                      resp->hwrm_fw_rsvd_8b;
1084         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1086
1087         fw_version = resp->hwrm_intf_maj_8b << 16;
1088         fw_version |= resp->hwrm_intf_min_8b << 8;
1089         fw_version |= resp->hwrm_intf_upd_8b;
1090         bp->hwrm_spec_code = fw_version;
1091
1092         /* def_req_timeout value is in milliseconds */
1093         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094         /* convert timeout to usec */
1095         bp->hwrm_cmd_timeout *= 1000;
1096         if (!bp->hwrm_cmd_timeout)
1097                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1098
1099         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1101                 rc = -EINVAL;
1102                 goto error;
1103         }
1104
1105         if (bp->max_req_len > resp->max_req_win_len) {
1106                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1107                 rc = -EINVAL;
1108         }
1109         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1113
1114         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1116
1117         if (bp->max_resp_len != max_resp_len) {
1118                 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1120                         bp->pdev->addr.devid, bp->pdev->addr.function);
1121
1122                 rte_free(bp->hwrm_cmd_resp_addr);
1123
1124                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125                 if (bp->hwrm_cmd_resp_addr == NULL) {
1126                         rc = -ENOMEM;
1127                         goto error;
1128                 }
1129                 bp->hwrm_cmd_resp_dma_addr =
1130                         rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1132                         PMD_DRV_LOG(ERR,
1133                         "Unable to map response buffer to physical memory.\n");
1134                         rc = -ENOMEM;
1135                         goto error;
1136                 }
1137                 bp->max_resp_len = max_resp_len;
1138         }
1139
1140         if ((dev_caps_cfg &
1141                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1142             (dev_caps_cfg &
1143              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1146         }
1147
1148         if (((dev_caps_cfg &
1149               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1150              (dev_caps_cfg &
1151               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153                 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1155                         bp->pdev->addr.devid, bp->pdev->addr.function);
1156
1157                 rte_free(bp->hwrm_short_cmd_req_addr);
1158
1159                 bp->hwrm_short_cmd_req_addr =
1160                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1162                         rc = -ENOMEM;
1163                         goto error;
1164                 }
1165                 bp->hwrm_short_cmd_req_dma_addr =
1166                         rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168                         rte_free(bp->hwrm_short_cmd_req_addr);
1169                         PMD_DRV_LOG(ERR,
1170                                 "Unable to map buffer to physical memory.\n");
1171                         rc = -ENOMEM;
1172                         goto error;
1173                 }
1174         }
1175         if (dev_caps_cfg &
1176             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1179         }
1180         if (dev_caps_cfg &
1181             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1183         if (dev_caps_cfg &
1184             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1187         }
1188
1189         if (dev_caps_cfg &
1190             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192                 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1193         }
1194
1195
1196 error:
1197         HWRM_UNLOCK();
1198         return rc;
1199 }
1200
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1202 {
1203         int rc;
1204         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1206
1207         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1208                 return 0;
1209
1210         HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1211         req.flags = flags;
1212
1213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1214
1215         HWRM_CHECK_RESULT();
1216         HWRM_UNLOCK();
1217
1218         return rc;
1219 }
1220
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1222 {
1223         int rc = 0;
1224         struct hwrm_port_phy_cfg_input req = {0};
1225         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226         uint32_t enables = 0;
1227
1228         HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1229
1230         if (conf->link_up) {
1231                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232                 if (bp->link_info->auto_mode && conf->link_speed) {
1233                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1235                 }
1236
1237                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1240                 /*
1241                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242                  * any auto mode, even "none".
1243                  */
1244                 if (!conf->link_speed) {
1245                         /* No speeds specified. Enable AutoNeg - all speeds */
1246                         req.auto_mode =
1247                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1248                 }
1249                 /* AutoNeg - Advertise speeds specified. */
1250                 if (conf->auto_link_speed_mask &&
1251                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1252                         req.auto_mode =
1253                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254                         req.auto_link_speed_mask =
1255                                 conf->auto_link_speed_mask;
1256                         enables |=
1257                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1258                 }
1259
1260                 req.auto_duplex = conf->duplex;
1261                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262                 req.auto_pause = conf->auto_pause;
1263                 req.force_pause = conf->force_pause;
1264                 /* Set force_pause if there is no auto or if there is a force */
1265                 if (req.auto_pause && !req.force_pause)
1266                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1267                 else
1268                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1269
1270                 req.enables = rte_cpu_to_le_32(enables);
1271         } else {
1272                 req.flags =
1273                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1275         }
1276
1277         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279         HWRM_CHECK_RESULT();
1280         HWRM_UNLOCK();
1281
1282         return rc;
1283 }
1284
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286                                    struct bnxt_link_info *link_info)
1287 {
1288         int rc = 0;
1289         struct hwrm_port_phy_qcfg_input req = {0};
1290         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1291
1292         HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1293
1294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1295
1296         HWRM_CHECK_RESULT();
1297
1298         link_info->phy_link_status = resp->link;
1299         link_info->link_up =
1300                 (link_info->phy_link_status ==
1301                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303         link_info->duplex = resp->duplex_cfg;
1304         link_info->pause = resp->pause;
1305         link_info->auto_pause = resp->auto_pause;
1306         link_info->force_pause = resp->force_pause;
1307         link_info->auto_mode = resp->auto_mode;
1308         link_info->phy_type = resp->phy_type;
1309         link_info->media_type = resp->media_type;
1310
1311         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315         link_info->phy_ver[0] = resp->phy_maj;
1316         link_info->phy_ver[1] = resp->phy_min;
1317         link_info->phy_ver[2] = resp->phy_bld;
1318
1319         HWRM_UNLOCK();
1320
1321         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326                     link_info->auto_link_speed_mask);
1327         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328                     link_info->force_link_speed);
1329
1330         return rc;
1331 }
1332
1333 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1334 {
1335         int rc = 0;
1336         struct hwrm_port_phy_qcaps_input req = {0};
1337         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1338
1339         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1340                 return 0;
1341
1342         HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1343
1344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1345
1346         HWRM_CHECK_RESULT();
1347
1348         bp->port_cnt = resp->port_cnt;
1349
1350         HWRM_UNLOCK();
1351
1352         return 0;
1353 }
1354
1355 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1356 {
1357         int i = 0;
1358
1359         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1360                 if (bp->tx_cos_queue[i].profile ==
1361                     HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1362                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1363                         return true;
1364                 }
1365         }
1366         return false;
1367 }
1368
1369 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1370 {
1371         int i = 0;
1372
1373         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1374                 if (bp->tx_cos_queue[i].profile !=
1375                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1376                     bp->tx_cos_queue[i].id !=
1377                     HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1378                         bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1379                         break;
1380                 }
1381         }
1382 }
1383
1384 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1385 {
1386         int rc = 0;
1387         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1388         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1389         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1390         int i;
1391
1392 get_rx_info:
1393         HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1394
1395         req.flags = rte_cpu_to_le_32(dir);
1396         /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1397         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1398             !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1399                 req.drv_qmap_cap =
1400                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1401         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1402
1403         HWRM_CHECK_RESULT();
1404
1405         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1406                 GET_TX_QUEUE_INFO(0);
1407                 GET_TX_QUEUE_INFO(1);
1408                 GET_TX_QUEUE_INFO(2);
1409                 GET_TX_QUEUE_INFO(3);
1410                 GET_TX_QUEUE_INFO(4);
1411                 GET_TX_QUEUE_INFO(5);
1412                 GET_TX_QUEUE_INFO(6);
1413                 GET_TX_QUEUE_INFO(7);
1414         } else  {
1415                 GET_RX_QUEUE_INFO(0);
1416                 GET_RX_QUEUE_INFO(1);
1417                 GET_RX_QUEUE_INFO(2);
1418                 GET_RX_QUEUE_INFO(3);
1419                 GET_RX_QUEUE_INFO(4);
1420                 GET_RX_QUEUE_INFO(5);
1421                 GET_RX_QUEUE_INFO(6);
1422                 GET_RX_QUEUE_INFO(7);
1423         }
1424
1425         HWRM_UNLOCK();
1426
1427         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1428                 goto done;
1429
1430         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1431                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1432         } else {
1433                 int j;
1434
1435                 /* iterate and find the COSq profile to use for Tx */
1436                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1437                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1438                                 if (bp->tx_cos_queue[i].id != 0xff)
1439                                         bp->tx_cosq_id[j++] =
1440                                                 bp->tx_cos_queue[i].id;
1441                         }
1442                 } else {
1443                         /* When CoS classification is disabled, for normal NIC
1444                          * operations, ideally we should look to use LOSSY.
1445                          * If not found, fallback to the first valid profile
1446                          */
1447                         if (!bnxt_find_lossy_profile(bp))
1448                                 bnxt_find_first_valid_profile(bp);
1449
1450                 }
1451         }
1452
1453         bp->max_tc = resp->max_configurable_queues;
1454         bp->max_lltc = resp->max_configurable_lossless_queues;
1455         if (bp->max_tc > BNXT_MAX_QUEUE)
1456                 bp->max_tc = BNXT_MAX_QUEUE;
1457         bp->max_q = bp->max_tc;
1458
1459         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1460                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1461                 goto get_rx_info;
1462         }
1463
1464 done:
1465         return rc;
1466 }
1467
1468 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1469                          struct bnxt_ring *ring,
1470                          uint32_t ring_type, uint32_t map_index,
1471                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1472                          uint16_t tx_cosq_id)
1473 {
1474         int rc = 0;
1475         uint32_t enables = 0;
1476         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1477         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1478         struct rte_mempool *mb_pool;
1479         uint16_t rx_buf_size;
1480
1481         HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1482
1483         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1484         req.fbo = rte_cpu_to_le_32(0);
1485         /* Association of ring index with doorbell index */
1486         req.logical_id = rte_cpu_to_le_16(map_index);
1487         req.length = rte_cpu_to_le_32(ring->ring_size);
1488
1489         switch (ring_type) {
1490         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1491                 req.ring_type = ring_type;
1492                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1493                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1494                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1495                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1496                         enables |=
1497                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1498                 break;
1499         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1500                 req.ring_type = ring_type;
1501                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1502                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1503                 if (BNXT_CHIP_THOR(bp)) {
1504                         mb_pool = bp->rx_queues[0]->mb_pool;
1505                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1506                                       RTE_PKTMBUF_HEADROOM;
1507                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1508                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1509                         enables |=
1510                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1511                 }
1512                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1513                         enables |=
1514                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1515                 break;
1516         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1517                 req.ring_type = ring_type;
1518                 if (BNXT_HAS_NQ(bp)) {
1519                         /* Association of cp ring with nq */
1520                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1521                         enables |=
1522                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1523                 }
1524                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1525                 break;
1526         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1527                 req.ring_type = ring_type;
1528                 req.page_size = BNXT_PAGE_SHFT;
1529                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1530                 break;
1531         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1532                 req.ring_type = ring_type;
1533                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1534
1535                 mb_pool = bp->rx_queues[0]->mb_pool;
1536                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1537                               RTE_PKTMBUF_HEADROOM;
1538                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1539                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1540
1541                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1542                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1543                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1544                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1545                 break;
1546         default:
1547                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1548                         ring_type);
1549                 HWRM_UNLOCK();
1550                 return -EINVAL;
1551         }
1552         req.enables = rte_cpu_to_le_32(enables);
1553
1554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1555
1556         if (rc || resp->error_code) {
1557                 if (rc == 0 && resp->error_code)
1558                         rc = rte_le_to_cpu_16(resp->error_code);
1559                 switch (ring_type) {
1560                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1561                         PMD_DRV_LOG(ERR,
1562                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1563                         HWRM_UNLOCK();
1564                         return rc;
1565                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1566                         PMD_DRV_LOG(ERR,
1567                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1568                         HWRM_UNLOCK();
1569                         return rc;
1570                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1571                         PMD_DRV_LOG(ERR,
1572                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1573                                     rc);
1574                         HWRM_UNLOCK();
1575                         return rc;
1576                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1577                         PMD_DRV_LOG(ERR,
1578                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1579                         HWRM_UNLOCK();
1580                         return rc;
1581                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1582                         PMD_DRV_LOG(ERR,
1583                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1584                         HWRM_UNLOCK();
1585                         return rc;
1586                 default:
1587                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1588                         HWRM_UNLOCK();
1589                         return rc;
1590                 }
1591         }
1592
1593         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1594         HWRM_UNLOCK();
1595         return rc;
1596 }
1597
1598 int bnxt_hwrm_ring_free(struct bnxt *bp,
1599                         struct bnxt_ring *ring, uint32_t ring_type)
1600 {
1601         int rc;
1602         struct hwrm_ring_free_input req = {.req_type = 0 };
1603         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1604
1605         HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1606
1607         req.ring_type = ring_type;
1608         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1609
1610         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1611
1612         if (rc || resp->error_code) {
1613                 if (rc == 0 && resp->error_code)
1614                         rc = rte_le_to_cpu_16(resp->error_code);
1615                 HWRM_UNLOCK();
1616
1617                 switch (ring_type) {
1618                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1619                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1620                                 rc);
1621                         return rc;
1622                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1623                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1624                                 rc);
1625                         return rc;
1626                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1627                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1628                                 rc);
1629                         return rc;
1630                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1631                         PMD_DRV_LOG(ERR,
1632                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1633                         return rc;
1634                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1635                         PMD_DRV_LOG(ERR,
1636                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1637                         return rc;
1638                 default:
1639                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1640                         return rc;
1641                 }
1642         }
1643         HWRM_UNLOCK();
1644         return 0;
1645 }
1646
1647 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1648 {
1649         int rc = 0;
1650         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1651         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1652
1653         HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1654
1655         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1656         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1657         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1658         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1659
1660         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1661
1662         HWRM_CHECK_RESULT();
1663
1664         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1665
1666         HWRM_UNLOCK();
1667
1668         return rc;
1669 }
1670
1671 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1672 {
1673         int rc;
1674         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1675         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1676
1677         HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1678
1679         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1680
1681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1682
1683         HWRM_CHECK_RESULT();
1684         HWRM_UNLOCK();
1685
1686         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1687         return rc;
1688 }
1689
1690 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1691 {
1692         int rc = 0;
1693         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1694         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1695
1696         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1697                 return rc;
1698
1699         HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1700
1701         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1702
1703         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1704
1705         HWRM_CHECK_RESULT();
1706         HWRM_UNLOCK();
1707
1708         return rc;
1709 }
1710
1711 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1712                                 unsigned int idx __rte_unused)
1713 {
1714         int rc;
1715         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1716         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1717
1718         HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1719
1720         req.update_period_ms = rte_cpu_to_le_32(0);
1721
1722         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1723
1724         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1725
1726         HWRM_CHECK_RESULT();
1727
1728         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1729
1730         HWRM_UNLOCK();
1731
1732         return rc;
1733 }
1734
1735 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1736                                 unsigned int idx __rte_unused)
1737 {
1738         int rc;
1739         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1740         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1741
1742         HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1743
1744         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1745
1746         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1747
1748         HWRM_CHECK_RESULT();
1749         HWRM_UNLOCK();
1750
1751         return rc;
1752 }
1753
1754 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1755 {
1756         int rc = 0, i, j;
1757         struct hwrm_vnic_alloc_input req = { 0 };
1758         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1759
1760         if (!BNXT_HAS_RING_GRPS(bp))
1761                 goto skip_ring_grps;
1762
1763         /* map ring groups to this vnic */
1764         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1765                 vnic->start_grp_id, vnic->end_grp_id);
1766         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1767                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1768
1769         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1770         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1771         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1772         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1773
1774 skip_ring_grps:
1775         vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1776         HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1777
1778         if (vnic->func_default)
1779                 req.flags =
1780                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1781         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1782
1783         HWRM_CHECK_RESULT();
1784
1785         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1786         HWRM_UNLOCK();
1787         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1788         return rc;
1789 }
1790
1791 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1792                                         struct bnxt_vnic_info *vnic,
1793                                         struct bnxt_plcmodes_cfg *pmode)
1794 {
1795         int rc = 0;
1796         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1797         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1798
1799         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1800
1801         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1802
1803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1804
1805         HWRM_CHECK_RESULT();
1806
1807         pmode->flags = rte_le_to_cpu_32(resp->flags);
1808         /* dflt_vnic bit doesn't exist in the _cfg command */
1809         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1810         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1811         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1812         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1813
1814         HWRM_UNLOCK();
1815
1816         return rc;
1817 }
1818
1819 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1820                                        struct bnxt_vnic_info *vnic,
1821                                        struct bnxt_plcmodes_cfg *pmode)
1822 {
1823         int rc = 0;
1824         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1825         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1826
1827         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1828                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1829                 return rc;
1830         }
1831
1832         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1833
1834         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1835         req.flags = rte_cpu_to_le_32(pmode->flags);
1836         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1837         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1838         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1839         req.enables = rte_cpu_to_le_32(
1840             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1841             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1842             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1843         );
1844
1845         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1846
1847         HWRM_CHECK_RESULT();
1848         HWRM_UNLOCK();
1849
1850         return rc;
1851 }
1852
1853 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1854 {
1855         int rc = 0;
1856         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1857         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1858         struct bnxt_plcmodes_cfg pmodes = { 0 };
1859         uint32_t ctx_enable_flag = 0;
1860         uint32_t enables = 0;
1861
1862         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1863                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1864                 return rc;
1865         }
1866
1867         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1868         if (rc)
1869                 return rc;
1870
1871         HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1872
1873         if (BNXT_CHIP_THOR(bp)) {
1874                 int dflt_rxq = vnic->start_grp_id;
1875                 struct bnxt_rx_ring_info *rxr;
1876                 struct bnxt_cp_ring_info *cpr;
1877                 struct bnxt_rx_queue *rxq;
1878                 int i;
1879
1880                 /*
1881                  * The first active receive ring is used as the VNIC
1882                  * default receive ring. If there are no active receive
1883                  * rings (all corresponding receive queues are stopped),
1884                  * the first receive ring is used.
1885                  */
1886                 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1887                         rxq = bp->eth_dev->data->rx_queues[i];
1888                         if (rxq->rx_started) {
1889                                 dflt_rxq = i;
1890                                 break;
1891                         }
1892                 }
1893
1894                 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1895                 rxr = rxq->rx_ring;
1896                 cpr = rxq->cp_ring;
1897
1898                 req.default_rx_ring_id =
1899                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1900                 req.default_cmpl_ring_id =
1901                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1902                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1903                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1904                 goto config_mru;
1905         }
1906
1907         /* Only RSS support for now TBD: COS & LB */
1908         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1909         if (vnic->lb_rule != 0xffff)
1910                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1911         if (vnic->cos_rule != 0xffff)
1912                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1913         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1914                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1915                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1916         }
1917         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1918                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1919                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1920         }
1921
1922         enables |= ctx_enable_flag;
1923         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1924         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1925         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1926         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1927
1928 config_mru:
1929         req.enables = rte_cpu_to_le_32(enables);
1930         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1931         req.mru = rte_cpu_to_le_16(vnic->mru);
1932         /* Configure default VNIC only once. */
1933         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1934                 req.flags |=
1935                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1936                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1937         }
1938         if (vnic->vlan_strip)
1939                 req.flags |=
1940                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1941         if (vnic->bd_stall)
1942                 req.flags |=
1943                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1944         if (vnic->roce_dual)
1945                 req.flags |= rte_cpu_to_le_32(
1946                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1947         if (vnic->roce_only)
1948                 req.flags |= rte_cpu_to_le_32(
1949                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1950         if (vnic->rss_dflt_cr)
1951                 req.flags |= rte_cpu_to_le_32(
1952                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1953
1954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1955
1956         HWRM_CHECK_RESULT();
1957         HWRM_UNLOCK();
1958
1959         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1960
1961         return rc;
1962 }
1963
1964 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1965                 int16_t fw_vf_id)
1966 {
1967         int rc = 0;
1968         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1969         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1970
1971         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1972                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1973                 return rc;
1974         }
1975         HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1976
1977         req.enables =
1978                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1979         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1980         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1981
1982         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1983
1984         HWRM_CHECK_RESULT();
1985
1986         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1987         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1988         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1989         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1990         vnic->mru = rte_le_to_cpu_16(resp->mru);
1991         vnic->func_default = rte_le_to_cpu_32(
1992                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1993         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1994                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1995         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1996                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1997         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1998                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1999         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
2000                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
2001         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2002                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2003
2004         HWRM_UNLOCK();
2005
2006         return rc;
2007 }
2008
2009 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2010                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2011 {
2012         int rc = 0;
2013         uint16_t ctx_id;
2014         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2015         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2016                                                 bp->hwrm_cmd_resp_addr;
2017
2018         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2019
2020         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2021         HWRM_CHECK_RESULT();
2022
2023         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2024         if (!BNXT_HAS_RING_GRPS(bp))
2025                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2026         else if (ctx_idx == 0)
2027                 vnic->rss_rule = ctx_id;
2028
2029         HWRM_UNLOCK();
2030
2031         return rc;
2032 }
2033
2034 static
2035 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2036                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2037 {
2038         int rc = 0;
2039         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2040         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2041                                                 bp->hwrm_cmd_resp_addr;
2042
2043         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2044                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2045                 return rc;
2046         }
2047         HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2048
2049         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2050
2051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2052
2053         HWRM_CHECK_RESULT();
2054         HWRM_UNLOCK();
2055
2056         return rc;
2057 }
2058
2059 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2060 {
2061         int rc = 0;
2062
2063         if (BNXT_CHIP_THOR(bp)) {
2064                 int j;
2065
2066                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2067                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
2068                                                       vnic,
2069                                                       vnic->fw_grp_ids[j]);
2070                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2071                 }
2072                 vnic->num_lb_ctxts = 0;
2073         } else {
2074                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2075                 vnic->rss_rule = INVALID_HW_RING_ID;
2076         }
2077
2078         return rc;
2079 }
2080
2081 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2082 {
2083         int rc = 0;
2084         struct hwrm_vnic_free_input req = {.req_type = 0 };
2085         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2086
2087         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2088                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2089                 return rc;
2090         }
2091
2092         HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2093
2094         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2095
2096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2097
2098         HWRM_CHECK_RESULT();
2099         HWRM_UNLOCK();
2100
2101         vnic->fw_vnic_id = INVALID_HW_RING_ID;
2102         /* Configure default VNIC again if necessary. */
2103         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2104                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2105
2106         return rc;
2107 }
2108
2109 static int
2110 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2111 {
2112         int i;
2113         int rc = 0;
2114         int nr_ctxs = vnic->num_lb_ctxts;
2115         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2116         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2117
2118         for (i = 0; i < nr_ctxs; i++) {
2119                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2120
2121                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2122                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2123                 req.hash_mode_flags = vnic->hash_mode;
2124
2125                 req.hash_key_tbl_addr =
2126                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2127
2128                 req.ring_grp_tbl_addr =
2129                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2130                                          i * HW_HASH_INDEX_SIZE);
2131                 req.ring_table_pair_index = i;
2132                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2133
2134                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2135                                             BNXT_USE_CHIMP_MB);
2136
2137                 HWRM_CHECK_RESULT();
2138                 HWRM_UNLOCK();
2139         }
2140
2141         return rc;
2142 }
2143
2144 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2145                            struct bnxt_vnic_info *vnic)
2146 {
2147         int rc = 0;
2148         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2149         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2150
2151         if (!vnic->rss_table)
2152                 return 0;
2153
2154         if (BNXT_CHIP_THOR(bp))
2155                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2156
2157         HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2158
2159         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2160         req.hash_mode_flags = vnic->hash_mode;
2161
2162         req.ring_grp_tbl_addr =
2163             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2164         req.hash_key_tbl_addr =
2165             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2166         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2167         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2168
2169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2170
2171         HWRM_CHECK_RESULT();
2172         HWRM_UNLOCK();
2173
2174         return rc;
2175 }
2176
2177 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2178                         struct bnxt_vnic_info *vnic)
2179 {
2180         int rc = 0;
2181         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2182         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2183         uint16_t size;
2184
2185         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2186                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2187                 return rc;
2188         }
2189
2190         HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2191
2192         req.flags = rte_cpu_to_le_32(
2193                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2194
2195         req.enables = rte_cpu_to_le_32(
2196                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2197
2198         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2199         size -= RTE_PKTMBUF_HEADROOM;
2200         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2201
2202         req.jumbo_thresh = rte_cpu_to_le_16(size);
2203         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2204
2205         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2206
2207         HWRM_CHECK_RESULT();
2208         HWRM_UNLOCK();
2209
2210         return rc;
2211 }
2212
2213 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2214                         struct bnxt_vnic_info *vnic, bool enable)
2215 {
2216         int rc = 0;
2217         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2218         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2219
2220         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2221                 if (enable)
2222                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2223                 return -ENOTSUP;
2224         }
2225
2226         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2227                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2228                 return 0;
2229         }
2230
2231         HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2232
2233         if (enable) {
2234                 req.enables = rte_cpu_to_le_32(
2235                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2236                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2237                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2238                 req.flags = rte_cpu_to_le_32(
2239                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2240                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2241                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2242                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2243                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2244                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2245                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2246                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2247                 req.min_agg_len = rte_cpu_to_le_32(512);
2248         }
2249         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2250
2251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252
2253         HWRM_CHECK_RESULT();
2254         HWRM_UNLOCK();
2255
2256         return rc;
2257 }
2258
2259 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2260 {
2261         struct hwrm_func_cfg_input req = {0};
2262         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2263         int rc;
2264
2265         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2266         req.enables = rte_cpu_to_le_32(
2267                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2268         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2269         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2270
2271         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2272
2273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2274         HWRM_CHECK_RESULT();
2275         HWRM_UNLOCK();
2276
2277         bp->pf->vf_info[vf].random_mac = false;
2278
2279         return rc;
2280 }
2281
2282 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2283                                   uint64_t *dropped)
2284 {
2285         int rc = 0;
2286         struct hwrm_func_qstats_input req = {.req_type = 0};
2287         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2288
2289         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2290
2291         req.fid = rte_cpu_to_le_16(fid);
2292
2293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2294
2295         HWRM_CHECK_RESULT();
2296
2297         if (dropped)
2298                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2299
2300         HWRM_UNLOCK();
2301
2302         return rc;
2303 }
2304
2305 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2306                           struct rte_eth_stats *stats,
2307                           struct hwrm_func_qstats_output *func_qstats)
2308 {
2309         int rc = 0;
2310         struct hwrm_func_qstats_input req = {.req_type = 0};
2311         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2312
2313         HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2314
2315         req.fid = rte_cpu_to_le_16(fid);
2316
2317         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2318
2319         HWRM_CHECK_RESULT();
2320         if (func_qstats)
2321                 memcpy(func_qstats, resp,
2322                        sizeof(struct hwrm_func_qstats_output));
2323
2324         if (!stats)
2325                 goto exit;
2326
2327         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2328         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2329         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2330         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2331         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2332         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2333
2334         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2335         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2336         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2337         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2338         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2339         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2340
2341         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2342         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2343         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2344
2345 exit:
2346         HWRM_UNLOCK();
2347
2348         return rc;
2349 }
2350
2351 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2352 {
2353         int rc = 0;
2354         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2355         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2356
2357         HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2358
2359         req.fid = rte_cpu_to_le_16(fid);
2360
2361         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2362
2363         HWRM_CHECK_RESULT();
2364         HWRM_UNLOCK();
2365
2366         return rc;
2367 }
2368
2369 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2370 {
2371         unsigned int i;
2372         int rc = 0;
2373
2374         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2375                 struct bnxt_tx_queue *txq;
2376                 struct bnxt_rx_queue *rxq;
2377                 struct bnxt_cp_ring_info *cpr;
2378
2379                 if (i >= bp->rx_cp_nr_rings) {
2380                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2381                         cpr = txq->cp_ring;
2382                 } else {
2383                         rxq = bp->rx_queues[i];
2384                         cpr = rxq->cp_ring;
2385                 }
2386
2387                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2388                 if (rc)
2389                         return rc;
2390         }
2391         return 0;
2392 }
2393
2394 static int
2395 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2396 {
2397         int rc;
2398         unsigned int i;
2399         struct bnxt_cp_ring_info *cpr;
2400
2401         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2402
2403                 if (i >= bp->rx_cp_nr_rings) {
2404                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2405                 } else {
2406                         cpr = bp->rx_queues[i]->cp_ring;
2407                         if (BNXT_HAS_RING_GRPS(bp))
2408                                 bp->grp_info[i].fw_stats_ctx = -1;
2409                 }
2410                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2411                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2412                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2413                         if (rc)
2414                                 return rc;
2415                 }
2416         }
2417         return 0;
2418 }
2419
2420 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2421 {
2422         unsigned int i;
2423         int rc = 0;
2424
2425         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2426                 struct bnxt_tx_queue *txq;
2427                 struct bnxt_rx_queue *rxq;
2428                 struct bnxt_cp_ring_info *cpr;
2429
2430                 if (i >= bp->rx_cp_nr_rings) {
2431                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2432                         cpr = txq->cp_ring;
2433                 } else {
2434                         rxq = bp->rx_queues[i];
2435                         cpr = rxq->cp_ring;
2436                 }
2437
2438                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2439
2440                 if (rc)
2441                         return rc;
2442         }
2443         return rc;
2444 }
2445
2446 static int
2447 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2448 {
2449         uint16_t idx;
2450         uint32_t rc = 0;
2451
2452         if (!BNXT_HAS_RING_GRPS(bp))
2453                 return 0;
2454
2455         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2456
2457                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2458                         continue;
2459
2460                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2461
2462                 if (rc)
2463                         return rc;
2464         }
2465         return rc;
2466 }
2467
2468 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2469 {
2470         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2471
2472         bnxt_hwrm_ring_free(bp, cp_ring,
2473                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2474         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2475         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2476                                      sizeof(*cpr->cp_desc_ring));
2477         cpr->cp_raw_cons = 0;
2478         cpr->valid = 0;
2479 }
2480
2481 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2482 {
2483         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2484
2485         bnxt_hwrm_ring_free(bp, cp_ring,
2486                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2487         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2488         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2489                         sizeof(*cpr->cp_desc_ring));
2490         cpr->cp_raw_cons = 0;
2491         cpr->valid = 0;
2492 }
2493
2494 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2495 {
2496         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2497         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2498         struct bnxt_ring *ring = rxr->rx_ring_struct;
2499         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2500
2501         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2502                 bnxt_hwrm_ring_free(bp, ring,
2503                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2504                 ring->fw_ring_id = INVALID_HW_RING_ID;
2505                 if (BNXT_HAS_RING_GRPS(bp))
2506                         bp->grp_info[queue_index].rx_fw_ring_id =
2507                                                         INVALID_HW_RING_ID;
2508         }
2509         ring = rxr->ag_ring_struct;
2510         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2511                 bnxt_hwrm_ring_free(bp, ring,
2512                                     BNXT_CHIP_THOR(bp) ?
2513                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2514                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2515                 if (BNXT_HAS_RING_GRPS(bp))
2516                         bp->grp_info[queue_index].ag_fw_ring_id =
2517                                                         INVALID_HW_RING_ID;
2518         }
2519         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2520                 bnxt_free_cp_ring(bp, cpr);
2521
2522         if (BNXT_HAS_RING_GRPS(bp))
2523                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2524 }
2525
2526 static int
2527 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2528 {
2529         unsigned int i;
2530
2531         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2532                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2533                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2534                 struct bnxt_ring *ring = txr->tx_ring_struct;
2535                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2536
2537                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2538                         bnxt_hwrm_ring_free(bp, ring,
2539                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2540                         ring->fw_ring_id = INVALID_HW_RING_ID;
2541                         memset(txr->tx_desc_ring, 0,
2542                                         txr->tx_ring_struct->ring_size *
2543                                         sizeof(*txr->tx_desc_ring));
2544                         memset(txr->tx_buf_ring, 0,
2545                                         txr->tx_ring_struct->ring_size *
2546                                         sizeof(*txr->tx_buf_ring));
2547                         txr->tx_prod = 0;
2548                         txr->tx_cons = 0;
2549                 }
2550                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2551                         bnxt_free_cp_ring(bp, cpr);
2552                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2553                 }
2554         }
2555
2556         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2557                 bnxt_free_hwrm_rx_ring(bp, i);
2558
2559         return 0;
2560 }
2561
2562 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2563 {
2564         uint16_t i;
2565         uint32_t rc = 0;
2566
2567         if (!BNXT_HAS_RING_GRPS(bp))
2568                 return 0;
2569
2570         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2571                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2572                 if (rc)
2573                         return rc;
2574         }
2575         return rc;
2576 }
2577
2578 /*
2579  * HWRM utility functions
2580  */
2581
2582 void bnxt_free_hwrm_resources(struct bnxt *bp)
2583 {
2584         /* Release memzone */
2585         rte_free(bp->hwrm_cmd_resp_addr);
2586         rte_free(bp->hwrm_short_cmd_req_addr);
2587         bp->hwrm_cmd_resp_addr = NULL;
2588         bp->hwrm_short_cmd_req_addr = NULL;
2589         bp->hwrm_cmd_resp_dma_addr = 0;
2590         bp->hwrm_short_cmd_req_dma_addr = 0;
2591 }
2592
2593 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2594 {
2595         struct rte_pci_device *pdev = bp->pdev;
2596         char type[RTE_MEMZONE_NAMESIZE];
2597
2598         sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2599                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2600         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2601         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2602         if (bp->hwrm_cmd_resp_addr == NULL)
2603                 return -ENOMEM;
2604         bp->hwrm_cmd_resp_dma_addr =
2605                 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2606         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2607                 PMD_DRV_LOG(ERR,
2608                         "unable to map response address to physical memory\n");
2609                 return -ENOMEM;
2610         }
2611         rte_spinlock_init(&bp->hwrm_lock);
2612
2613         return 0;
2614 }
2615
2616 int
2617 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2618 {
2619         int rc = 0;
2620
2621         if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2622                 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2623                 if (rc)
2624                         return rc;
2625         } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2626                 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627                 if (rc)
2628                         return rc;
2629         }
2630
2631         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2632         return rc;
2633 }
2634
2635 static int
2636 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2637 {
2638         struct bnxt_filter_info *filter;
2639         int rc = 0;
2640
2641         STAILQ_FOREACH(filter, &vnic->filter, next) {
2642                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2643                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2644                 bnxt_free_filter(bp, filter);
2645         }
2646         return rc;
2647 }
2648
2649 static int
2650 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2651 {
2652         struct bnxt_filter_info *filter;
2653         struct rte_flow *flow;
2654         int rc = 0;
2655
2656         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2657                 flow = STAILQ_FIRST(&vnic->flow_list);
2658                 filter = flow->filter;
2659                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2660                 rc = bnxt_clear_one_vnic_filter(bp, filter);
2661
2662                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2663                 rte_free(flow);
2664         }
2665         return rc;
2666 }
2667
2668 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2669 {
2670         struct bnxt_filter_info *filter;
2671         int rc = 0;
2672
2673         STAILQ_FOREACH(filter, &vnic->filter, next) {
2674                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2675                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2676                                                      filter);
2677                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2678                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2679                                                          filter);
2680                 else
2681                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2682                                                      filter);
2683                 if (rc)
2684                         break;
2685         }
2686         return rc;
2687 }
2688
2689 static void
2690 bnxt_free_tunnel_ports(struct bnxt *bp)
2691 {
2692         if (bp->vxlan_port_cnt)
2693                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2694                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2695         bp->vxlan_port = 0;
2696         if (bp->geneve_port_cnt)
2697                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2698                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2699         bp->geneve_port = 0;
2700 }
2701
2702 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2703 {
2704         int i;
2705
2706         if (bp->vnic_info == NULL)
2707                 return;
2708
2709         /*
2710          * Cleanup VNICs in reverse order, to make sure the L2 filter
2711          * from vnic0 is last to be cleaned up.
2712          */
2713         for (i = bp->max_vnics - 1; i >= 0; i--) {
2714                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2715
2716                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2717                         continue;
2718
2719                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2720
2721                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2722
2723                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2724
2725                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2726
2727                 bnxt_hwrm_vnic_free(bp, vnic);
2728
2729                 rte_free(vnic->fw_grp_ids);
2730         }
2731         /* Ring resources */
2732         bnxt_free_all_hwrm_rings(bp);
2733         bnxt_free_all_hwrm_ring_grps(bp);
2734         bnxt_free_all_hwrm_stat_ctxs(bp);
2735         bnxt_free_tunnel_ports(bp);
2736 }
2737
2738 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2739 {
2740         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2741
2742         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2743                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2744
2745         switch (conf_link_speed) {
2746         case ETH_LINK_SPEED_10M_HD:
2747         case ETH_LINK_SPEED_100M_HD:
2748                 /* FALLTHROUGH */
2749                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2750         }
2751         return hw_link_duplex;
2752 }
2753
2754 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2755 {
2756         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2757 }
2758
2759 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2760 {
2761         uint16_t eth_link_speed = 0;
2762
2763         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2764                 return ETH_LINK_SPEED_AUTONEG;
2765
2766         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2767         case ETH_LINK_SPEED_100M:
2768         case ETH_LINK_SPEED_100M_HD:
2769                 /* FALLTHROUGH */
2770                 eth_link_speed =
2771                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2772                 break;
2773         case ETH_LINK_SPEED_1G:
2774                 eth_link_speed =
2775                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2776                 break;
2777         case ETH_LINK_SPEED_2_5G:
2778                 eth_link_speed =
2779                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2780                 break;
2781         case ETH_LINK_SPEED_10G:
2782                 eth_link_speed =
2783                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2784                 break;
2785         case ETH_LINK_SPEED_20G:
2786                 eth_link_speed =
2787                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2788                 break;
2789         case ETH_LINK_SPEED_25G:
2790                 eth_link_speed =
2791                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2792                 break;
2793         case ETH_LINK_SPEED_40G:
2794                 eth_link_speed =
2795                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2796                 break;
2797         case ETH_LINK_SPEED_50G:
2798                 eth_link_speed =
2799                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2800                 break;
2801         case ETH_LINK_SPEED_100G:
2802                 eth_link_speed =
2803                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2804                 break;
2805         case ETH_LINK_SPEED_200G:
2806                 eth_link_speed =
2807                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2808                 break;
2809         default:
2810                 PMD_DRV_LOG(ERR,
2811                         "Unsupported link speed %d; default to AUTO\n",
2812                         conf_link_speed);
2813                 break;
2814         }
2815         return eth_link_speed;
2816 }
2817
2818 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2819                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2820                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2821                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2822                 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2823
2824 static int bnxt_validate_link_speed(struct bnxt *bp)
2825 {
2826         uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2827         uint16_t port_id = bp->eth_dev->data->port_id;
2828         uint32_t link_speed_capa;
2829         uint32_t one_speed;
2830
2831         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2832                 return 0;
2833
2834         link_speed_capa = bnxt_get_speed_capabilities(bp);
2835
2836         if (link_speed & ETH_LINK_SPEED_FIXED) {
2837                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2838
2839                 if (one_speed & (one_speed - 1)) {
2840                         PMD_DRV_LOG(ERR,
2841                                 "Invalid advertised speeds (%u) for port %u\n",
2842                                 link_speed, port_id);
2843                         return -EINVAL;
2844                 }
2845                 if ((one_speed & link_speed_capa) != one_speed) {
2846                         PMD_DRV_LOG(ERR,
2847                                 "Unsupported advertised speed (%u) for port %u\n",
2848                                 link_speed, port_id);
2849                         return -EINVAL;
2850                 }
2851         } else {
2852                 if (!(link_speed & link_speed_capa)) {
2853                         PMD_DRV_LOG(ERR,
2854                                 "Unsupported advertised speeds (%u) for port %u\n",
2855                                 link_speed, port_id);
2856                         return -EINVAL;
2857                 }
2858         }
2859         return 0;
2860 }
2861
2862 static uint16_t
2863 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2864 {
2865         uint16_t ret = 0;
2866
2867         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2868                 if (bp->link_info->support_speeds)
2869                         return bp->link_info->support_speeds;
2870                 link_speed = BNXT_SUPPORTED_SPEEDS;
2871         }
2872
2873         if (link_speed & ETH_LINK_SPEED_100M)
2874                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2875         if (link_speed & ETH_LINK_SPEED_100M_HD)
2876                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2877         if (link_speed & ETH_LINK_SPEED_1G)
2878                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2879         if (link_speed & ETH_LINK_SPEED_2_5G)
2880                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2881         if (link_speed & ETH_LINK_SPEED_10G)
2882                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2883         if (link_speed & ETH_LINK_SPEED_20G)
2884                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2885         if (link_speed & ETH_LINK_SPEED_25G)
2886                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2887         if (link_speed & ETH_LINK_SPEED_40G)
2888                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2889         if (link_speed & ETH_LINK_SPEED_50G)
2890                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2891         if (link_speed & ETH_LINK_SPEED_100G)
2892                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2893         if (link_speed & ETH_LINK_SPEED_200G)
2894                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2895         return ret;
2896 }
2897
2898 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2899 {
2900         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2901
2902         switch (hw_link_speed) {
2903         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2904                 eth_link_speed = ETH_SPEED_NUM_100M;
2905                 break;
2906         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2907                 eth_link_speed = ETH_SPEED_NUM_1G;
2908                 break;
2909         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2910                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2911                 break;
2912         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2913                 eth_link_speed = ETH_SPEED_NUM_10G;
2914                 break;
2915         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2916                 eth_link_speed = ETH_SPEED_NUM_20G;
2917                 break;
2918         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2919                 eth_link_speed = ETH_SPEED_NUM_25G;
2920                 break;
2921         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2922                 eth_link_speed = ETH_SPEED_NUM_40G;
2923                 break;
2924         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2925                 eth_link_speed = ETH_SPEED_NUM_50G;
2926                 break;
2927         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2928                 eth_link_speed = ETH_SPEED_NUM_100G;
2929                 break;
2930         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2931                 eth_link_speed = ETH_SPEED_NUM_200G;
2932                 break;
2933         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2934         default:
2935                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2936                         hw_link_speed);
2937                 break;
2938         }
2939         return eth_link_speed;
2940 }
2941
2942 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2943 {
2944         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2945
2946         switch (hw_link_duplex) {
2947         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2948         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2949                 /* FALLTHROUGH */
2950                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2951                 break;
2952         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2953                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2954                 break;
2955         default:
2956                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2957                         hw_link_duplex);
2958                 break;
2959         }
2960         return eth_link_duplex;
2961 }
2962
2963 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2964 {
2965         int rc = 0;
2966         struct bnxt_link_info *link_info = bp->link_info;
2967
2968         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2969         if (rc) {
2970                 PMD_DRV_LOG(ERR,
2971                         "Get link config failed with rc %d\n", rc);
2972                 goto exit;
2973         }
2974         if (link_info->link_speed)
2975                 link->link_speed =
2976                         bnxt_parse_hw_link_speed(link_info->link_speed);
2977         else
2978                 link->link_speed = ETH_SPEED_NUM_NONE;
2979         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2980         link->link_status = link_info->link_up;
2981         link->link_autoneg = link_info->auto_mode ==
2982                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2983                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2984 exit:
2985         return rc;
2986 }
2987
2988 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2989 {
2990         int rc = 0;
2991         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2992         struct bnxt_link_info link_req;
2993         uint16_t speed, autoneg;
2994
2995         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2996                 return 0;
2997
2998         rc = bnxt_validate_link_speed(bp);
2999         if (rc)
3000                 goto error;
3001
3002         memset(&link_req, 0, sizeof(link_req));
3003         link_req.link_up = link_up;
3004         if (!link_up)
3005                 goto port_phy_cfg;
3006
3007         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3008         if (BNXT_CHIP_THOR(bp) &&
3009             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
3010                 /* 40G is not supported as part of media auto detect.
3011                  * The speed should be forced and autoneg disabled
3012                  * to configure 40G speed.
3013                  */
3014                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3015                 autoneg = 0;
3016         }
3017
3018         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
3019         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3020         /* Autoneg can be done only when the FW allows.
3021          * When user configures fixed speed of 40G and later changes to
3022          * any other speed, auto_link_speed/force_link_speed is still set
3023          * to 40G until link comes up at new speed.
3024          */
3025         if (autoneg == 1 &&
3026             !(!BNXT_CHIP_THOR(bp) &&
3027               (bp->link_info->auto_link_speed ||
3028                bp->link_info->force_link_speed))) {
3029                 link_req.phy_flags |=
3030                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3031                 link_req.auto_link_speed_mask =
3032                         bnxt_parse_eth_link_speed_mask(bp,
3033                                                        dev_conf->link_speeds);
3034         } else {
3035                 if (bp->link_info->phy_type ==
3036                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3037                     bp->link_info->phy_type ==
3038                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3039                     bp->link_info->media_type ==
3040                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3041                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3042                         return -EINVAL;
3043                 }
3044
3045                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3046                 /* If user wants a particular speed try that first. */
3047                 if (speed)
3048                         link_req.link_speed = speed;
3049                 else if (bp->link_info->force_link_speed)
3050                         link_req.link_speed = bp->link_info->force_link_speed;
3051                 else
3052                         link_req.link_speed = bp->link_info->auto_link_speed;
3053         }
3054         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3055         link_req.auto_pause = bp->link_info->auto_pause;
3056         link_req.force_pause = bp->link_info->force_pause;
3057
3058 port_phy_cfg:
3059         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3060         if (rc) {
3061                 PMD_DRV_LOG(ERR,
3062                         "Set link config failed with rc %d\n", rc);
3063         }
3064
3065 error:
3066         return rc;
3067 }
3068
3069 /* JIRA 22088 */
3070 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3071 {
3072         struct hwrm_func_qcfg_input req = {0};
3073         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3074         uint16_t flags;
3075         int rc = 0;
3076         bp->func_svif = BNXT_SVIF_INVALID;
3077         uint16_t svif_info;
3078
3079         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3080         req.fid = rte_cpu_to_le_16(0xffff);
3081
3082         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3083
3084         HWRM_CHECK_RESULT();
3085
3086         /* Hard Coded.. 0xfff VLAN ID mask */
3087         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3088
3089         svif_info = rte_le_to_cpu_16(resp->svif_info);
3090         if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3091                 bp->func_svif = svif_info &
3092                                      HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3093
3094         flags = rte_le_to_cpu_16(resp->flags);
3095         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3096                 bp->flags |= BNXT_FLAG_MULTI_HOST;
3097
3098         if (BNXT_VF(bp) &&
3099             !BNXT_VF_IS_TRUSTED(bp) &&
3100             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3101                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3102                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3103         } else if (BNXT_VF(bp) &&
3104                    BNXT_VF_IS_TRUSTED(bp) &&
3105                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3106                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3107                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3108         }
3109
3110         if (mtu)
3111                 *mtu = rte_le_to_cpu_16(resp->mtu);
3112
3113         switch (resp->port_partition_type) {
3114         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3115         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3116         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3117                 /* FALLTHROUGH */
3118                 bp->flags |= BNXT_FLAG_NPAR_PF;
3119                 break;
3120         default:
3121                 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3122                 break;
3123         }
3124
3125         HWRM_UNLOCK();
3126
3127         return rc;
3128 }
3129
3130 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3131 {
3132         struct hwrm_func_qcfg_input req = {0};
3133         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3134         int rc;
3135
3136         if (!BNXT_VF_IS_TRUSTED(bp))
3137                 return 0;
3138
3139         if (!bp->parent)
3140                 return -EINVAL;
3141
3142         bp->parent->fid = BNXT_PF_FID_INVALID;
3143
3144         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3145
3146         req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3147
3148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3149
3150         HWRM_CHECK_RESULT();
3151
3152         memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3153         bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3154         bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3155         bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3156
3157         /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3158         if (bp->parent->vnic == 0) {
3159                 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3160                 /* Use hard-coded values appropriate for current Wh+ fw. */
3161                 if (bp->parent->fid == 2)
3162                         bp->parent->vnic = 0x100;
3163                 else
3164                         bp->parent->vnic = 1;
3165         }
3166
3167         HWRM_UNLOCK();
3168
3169         return 0;
3170 }
3171
3172 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3173                                  uint16_t *vnic_id, uint16_t *svif)
3174 {
3175         struct hwrm_func_qcfg_input req = {0};
3176         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3177         uint16_t svif_info;
3178         int rc = 0;
3179
3180         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3181         req.fid = rte_cpu_to_le_16(fid);
3182
3183         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3184
3185         HWRM_CHECK_RESULT();
3186
3187         if (vnic_id)
3188                 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3189
3190         svif_info = rte_le_to_cpu_16(resp->svif_info);
3191         if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3192                 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3193
3194         HWRM_UNLOCK();
3195
3196         return rc;
3197 }
3198
3199 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3200 {
3201         struct hwrm_port_mac_qcfg_input req = {0};
3202         struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3203         uint16_t port_svif_info;
3204         int rc;
3205
3206         bp->port_svif = BNXT_SVIF_INVALID;
3207
3208         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3209                 return 0;
3210
3211         HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3212
3213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3214
3215         HWRM_CHECK_RESULT_SILENT();
3216
3217         port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3218         if (port_svif_info &
3219             HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3220                 bp->port_svif = port_svif_info &
3221                         HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3222
3223         HWRM_UNLOCK();
3224
3225         return 0;
3226 }
3227
3228 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3229                                    struct hwrm_func_qcaps_output *qcaps)
3230 {
3231         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3232         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3233                sizeof(qcaps->mac_address));
3234         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3235         qcaps->max_rx_rings = fcfg->num_rx_rings;
3236         qcaps->max_tx_rings = fcfg->num_tx_rings;
3237         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3238         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3239         qcaps->max_vfs = 0;
3240         qcaps->first_vf_id = 0;
3241         qcaps->max_vnics = fcfg->num_vnics;
3242         qcaps->max_decap_records = 0;
3243         qcaps->max_encap_records = 0;
3244         qcaps->max_tx_wm_flows = 0;
3245         qcaps->max_tx_em_flows = 0;
3246         qcaps->max_rx_wm_flows = 0;
3247         qcaps->max_rx_em_flows = 0;
3248         qcaps->max_flow_id = 0;
3249         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3250         qcaps->max_sp_tx_rings = 0;
3251         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3252 }
3253
3254 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3255 {
3256         struct hwrm_func_cfg_input req = {0};
3257         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3258         uint32_t enables;
3259         int rc;
3260
3261         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3262                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3263                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3264                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3265                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3266                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3267                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3268                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3269                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3270
3271         if (BNXT_HAS_RING_GRPS(bp)) {
3272                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3273                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3274         } else if (BNXT_HAS_NQ(bp)) {
3275                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3276                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3277         }
3278
3279         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3280         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3281         req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3282         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3283         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3284         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3285         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3286         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3287         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3288         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3289         req.fid = rte_cpu_to_le_16(0xffff);
3290         req.enables = rte_cpu_to_le_32(enables);
3291
3292         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3293
3294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3295
3296         HWRM_CHECK_RESULT();
3297         HWRM_UNLOCK();
3298
3299         return rc;
3300 }
3301
3302 static void populate_vf_func_cfg_req(struct bnxt *bp,
3303                                      struct hwrm_func_cfg_input *req,
3304                                      int num_vfs)
3305 {
3306         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3307                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3308                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3309                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3310                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3311                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3312                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3313                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3314                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3315                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3316
3317         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3318                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3319                                     BNXT_NUM_VLANS);
3320         req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3321         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3322                                                 (num_vfs + 1));
3323         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3324         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3325                                                (num_vfs + 1));
3326         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3327         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3328         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3329         /* TODO: For now, do not support VMDq/RFS on VFs. */
3330         req->num_vnics = rte_cpu_to_le_16(1);
3331         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3332                                                  (num_vfs + 1));
3333 }
3334
3335 static void add_random_mac_if_needed(struct bnxt *bp,
3336                                      struct hwrm_func_cfg_input *cfg_req,
3337                                      int vf)
3338 {
3339         struct rte_ether_addr mac;
3340
3341         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3342                 return;
3343
3344         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3345                 cfg_req->enables |=
3346                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3347                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3348                 bp->pf->vf_info[vf].random_mac = true;
3349         } else {
3350                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3351                         RTE_ETHER_ADDR_LEN);
3352         }
3353 }
3354
3355 static int reserve_resources_from_vf(struct bnxt *bp,
3356                                      struct hwrm_func_cfg_input *cfg_req,
3357                                      int vf)
3358 {
3359         struct hwrm_func_qcaps_input req = {0};
3360         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3361         int rc;
3362
3363         /* Get the actual allocated values now */
3364         HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3365         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3366         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3367
3368         if (rc) {
3369                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3370                 copy_func_cfg_to_qcaps(cfg_req, resp);
3371         } else if (resp->error_code) {
3372                 rc = rte_le_to_cpu_16(resp->error_code);
3373                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3374                 copy_func_cfg_to_qcaps(cfg_req, resp);
3375         }
3376
3377         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3378         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3379         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3380         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3381         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3382         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3383         /*
3384          * TODO: While not supporting VMDq with VFs, max_vnics is always
3385          * forced to 1 in this case
3386          */
3387         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3388         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3389
3390         HWRM_UNLOCK();
3391
3392         return 0;
3393 }
3394
3395 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3396 {
3397         struct hwrm_func_qcfg_input req = {0};
3398         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3399         int rc;
3400
3401         /* Check for zero MAC address */
3402         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3403         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3404         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3405         HWRM_CHECK_RESULT();
3406         rc = rte_le_to_cpu_16(resp->vlan);
3407
3408         HWRM_UNLOCK();
3409
3410         return rc;
3411 }
3412
3413 static int update_pf_resource_max(struct bnxt *bp)
3414 {
3415         struct hwrm_func_qcfg_input req = {0};
3416         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3417         int rc;
3418
3419         /* And copy the allocated numbers into the pf struct */
3420         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3421         req.fid = rte_cpu_to_le_16(0xffff);
3422         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3423         HWRM_CHECK_RESULT();
3424
3425         /* Only TX ring value reflects actual allocation? TODO */
3426         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3427         bp->pf->evb_mode = resp->evb_mode;
3428
3429         HWRM_UNLOCK();
3430
3431         return rc;
3432 }
3433
3434 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3435 {
3436         int rc;
3437
3438         if (!BNXT_PF(bp)) {
3439                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3440                 return -EINVAL;
3441         }
3442
3443         rc = bnxt_hwrm_func_qcaps(bp);
3444         if (rc)
3445                 return rc;
3446
3447         bp->pf->func_cfg_flags &=
3448                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3449                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3450         bp->pf->func_cfg_flags |=
3451                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3452         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3453         rc = __bnxt_hwrm_func_qcaps(bp);
3454         return rc;
3455 }
3456
3457 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3458 {
3459         struct hwrm_func_cfg_input req = {0};
3460         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3461         int i;
3462         size_t sz;
3463         int rc = 0;
3464         size_t req_buf_sz;
3465
3466         if (!BNXT_PF(bp)) {
3467                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3468                 return -EINVAL;
3469         }
3470
3471         rc = bnxt_hwrm_func_qcaps(bp);
3472
3473         if (rc)
3474                 return rc;
3475
3476         bp->pf->active_vfs = num_vfs;
3477
3478         /*
3479          * First, configure the PF to only use one TX ring.  This ensures that
3480          * there are enough rings for all VFs.
3481          *
3482          * If we don't do this, when we call func_alloc() later, we will lock
3483          * extra rings to the PF that won't be available during func_cfg() of
3484          * the VFs.
3485          *
3486          * This has been fixed with firmware versions above 20.6.54
3487          */
3488         bp->pf->func_cfg_flags &=
3489                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3490                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3491         bp->pf->func_cfg_flags |=
3492                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3493         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3494         if (rc)
3495                 return rc;
3496
3497         /*
3498          * Now, create and register a buffer to hold forwarded VF requests
3499          */
3500         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3501         bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3502                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3503         if (bp->pf->vf_req_buf == NULL) {
3504                 rc = -ENOMEM;
3505                 goto error_free;
3506         }
3507         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3508                 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3509         for (i = 0; i < num_vfs; i++)
3510                 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3511                                         (i * HWRM_MAX_REQ_LEN);
3512
3513         rc = bnxt_hwrm_func_buf_rgtr(bp);
3514         if (rc)
3515                 goto error_free;
3516
3517         populate_vf_func_cfg_req(bp, &req, num_vfs);
3518
3519         bp->pf->active_vfs = 0;
3520         for (i = 0; i < num_vfs; i++) {
3521                 add_random_mac_if_needed(bp, &req, i);
3522
3523                 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3524                 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3525                 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3526                 rc = bnxt_hwrm_send_message(bp,
3527                                             &req,
3528                                             sizeof(req),
3529                                             BNXT_USE_CHIMP_MB);
3530
3531                 /* Clear enable flag for next pass */
3532                 req.enables &= ~rte_cpu_to_le_32(
3533                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3534
3535                 if (rc || resp->error_code) {
3536                         PMD_DRV_LOG(ERR,
3537                                 "Failed to initizlie VF %d\n", i);
3538                         PMD_DRV_LOG(ERR,
3539                                 "Not all VFs available. (%d, %d)\n",
3540                                 rc, resp->error_code);
3541                         HWRM_UNLOCK();
3542                         break;
3543                 }
3544
3545                 HWRM_UNLOCK();
3546
3547                 reserve_resources_from_vf(bp, &req, i);
3548                 bp->pf->active_vfs++;
3549                 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3550         }
3551
3552         /*
3553          * Now configure the PF to use "the rest" of the resources
3554          * We're using STD_TX_RING_MODE here though which will limit the TX
3555          * rings.  This will allow QoS to function properly.  Not setting this
3556          * will cause PF rings to break bandwidth settings.
3557          */
3558         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3559         if (rc)
3560                 goto error_free;
3561
3562         rc = update_pf_resource_max(bp);
3563         if (rc)
3564                 goto error_free;
3565
3566         return rc;
3567
3568 error_free:
3569         bnxt_hwrm_func_buf_unrgtr(bp);
3570         return rc;
3571 }
3572
3573 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3574 {
3575         struct hwrm_func_cfg_input req = {0};
3576         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3577         int rc;
3578
3579         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3580
3581         req.fid = rte_cpu_to_le_16(0xffff);
3582         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3583         req.evb_mode = bp->pf->evb_mode;
3584
3585         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3586         HWRM_CHECK_RESULT();
3587         HWRM_UNLOCK();
3588
3589         return rc;
3590 }
3591
3592 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3593                                 uint8_t tunnel_type)
3594 {
3595         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3596         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3597         int rc = 0;
3598
3599         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3600         req.tunnel_type = tunnel_type;
3601         req.tunnel_dst_port_val = port;
3602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3603         HWRM_CHECK_RESULT();
3604
3605         switch (tunnel_type) {
3606         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3607                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3608                 bp->vxlan_port = port;
3609                 break;
3610         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3611                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3612                 bp->geneve_port = port;
3613                 break;
3614         default:
3615                 break;
3616         }
3617
3618         HWRM_UNLOCK();
3619
3620         return rc;
3621 }
3622
3623 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3624                                 uint8_t tunnel_type)
3625 {
3626         struct hwrm_tunnel_dst_port_free_input req = {0};
3627         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3628         int rc = 0;
3629
3630         HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3631
3632         req.tunnel_type = tunnel_type;
3633         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3634         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3635
3636         HWRM_CHECK_RESULT();
3637         HWRM_UNLOCK();
3638
3639         return rc;
3640 }
3641
3642 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3643                                         uint32_t flags)
3644 {
3645         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3646         struct hwrm_func_cfg_input req = {0};
3647         int rc;
3648
3649         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3650
3651         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3652         req.flags = rte_cpu_to_le_32(flags);
3653         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3654
3655         HWRM_CHECK_RESULT();
3656         HWRM_UNLOCK();
3657
3658         return rc;
3659 }
3660
3661 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3662 {
3663         uint32_t *flag = flagp;
3664
3665         vnic->flags = *flag;
3666 }
3667
3668 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3669 {
3670         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3671 }
3672
3673 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3674 {
3675         int rc = 0;
3676         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3677         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3678
3679         HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3680
3681         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3682         req.req_buf_page_size = rte_cpu_to_le_16(
3683                          page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3684         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3685         req.req_buf_page_addr0 =
3686                 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3687         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3688                 PMD_DRV_LOG(ERR,
3689                         "unable to map buffer address to physical memory\n");
3690                 return -ENOMEM;
3691         }
3692
3693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3694
3695         HWRM_CHECK_RESULT();
3696         HWRM_UNLOCK();
3697
3698         return rc;
3699 }
3700
3701 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3702 {
3703         int rc = 0;
3704         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3705         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3706
3707         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3708                 return 0;
3709
3710         HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3711
3712         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3713
3714         HWRM_CHECK_RESULT();
3715         HWRM_UNLOCK();
3716
3717         return rc;
3718 }
3719
3720 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3721 {
3722         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3723         struct hwrm_func_cfg_input req = {0};
3724         int rc;
3725
3726         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3727
3728         req.fid = rte_cpu_to_le_16(0xffff);
3729         req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3730         req.enables = rte_cpu_to_le_32(
3731                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3732         req.async_event_cr = rte_cpu_to_le_16(
3733                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3734         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3735
3736         HWRM_CHECK_RESULT();
3737         HWRM_UNLOCK();
3738
3739         return rc;
3740 }
3741
3742 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3743 {
3744         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3745         struct hwrm_func_vf_cfg_input req = {0};
3746         int rc;
3747
3748         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3749
3750         req.enables = rte_cpu_to_le_32(
3751                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3752         req.async_event_cr = rte_cpu_to_le_16(
3753                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3754         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3755
3756         HWRM_CHECK_RESULT();
3757         HWRM_UNLOCK();
3758
3759         return rc;
3760 }
3761
3762 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3763 {
3764         struct hwrm_func_cfg_input req = {0};
3765         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3766         uint16_t dflt_vlan, fid;
3767         uint32_t func_cfg_flags;
3768         int rc = 0;
3769
3770         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3771
3772         if (is_vf) {
3773                 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3774                 fid = bp->pf->vf_info[vf].fid;
3775                 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3776         } else {
3777                 fid = rte_cpu_to_le_16(0xffff);
3778                 func_cfg_flags = bp->pf->func_cfg_flags;
3779                 dflt_vlan = bp->vlan;
3780         }
3781
3782         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3783         req.fid = rte_cpu_to_le_16(fid);
3784         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3785         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3786
3787         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3788
3789         HWRM_CHECK_RESULT();
3790         HWRM_UNLOCK();
3791
3792         return rc;
3793 }
3794
3795 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3796                         uint16_t max_bw, uint16_t enables)
3797 {
3798         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3799         struct hwrm_func_cfg_input req = {0};
3800         int rc;
3801
3802         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3803
3804         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3805         req.enables |= rte_cpu_to_le_32(enables);
3806         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3807         req.max_bw = rte_cpu_to_le_32(max_bw);
3808         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3809
3810         HWRM_CHECK_RESULT();
3811         HWRM_UNLOCK();
3812
3813         return rc;
3814 }
3815
3816 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3817 {
3818         struct hwrm_func_cfg_input req = {0};
3819         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3820         int rc = 0;
3821
3822         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3823
3824         req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3825         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3826         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3827         req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3828
3829         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3830
3831         HWRM_CHECK_RESULT();
3832         HWRM_UNLOCK();
3833
3834         return rc;
3835 }
3836
3837 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3838 {
3839         int rc;
3840
3841         if (BNXT_PF(bp))
3842                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3843         else
3844                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3845
3846         return rc;
3847 }
3848
3849 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3850                               void *encaped, size_t ec_size)
3851 {
3852         int rc = 0;
3853         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3854         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3855
3856         if (ec_size > sizeof(req.encap_request))
3857                 return -1;
3858
3859         HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3860
3861         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3862         memcpy(req.encap_request, encaped, ec_size);
3863
3864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3865
3866         HWRM_CHECK_RESULT();
3867         HWRM_UNLOCK();
3868
3869         return rc;
3870 }
3871
3872 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3873                                        struct rte_ether_addr *mac)
3874 {
3875         struct hwrm_func_qcfg_input req = {0};
3876         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3877         int rc;
3878
3879         HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3880
3881         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3882         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3883
3884         HWRM_CHECK_RESULT();
3885
3886         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3887
3888         HWRM_UNLOCK();
3889
3890         return rc;
3891 }
3892
3893 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3894                             void *encaped, size_t ec_size)
3895 {
3896         int rc = 0;
3897         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3898         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3899
3900         if (ec_size > sizeof(req.encap_request))
3901                 return -1;
3902
3903         HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3904
3905         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3906         memcpy(req.encap_request, encaped, ec_size);
3907
3908         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3909
3910         HWRM_CHECK_RESULT();
3911         HWRM_UNLOCK();
3912
3913         return rc;
3914 }
3915
3916 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3917                          struct rte_eth_stats *stats, uint8_t rx)
3918 {
3919         int rc = 0;
3920         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3921         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3922
3923         HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3924
3925         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3926
3927         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3928
3929         HWRM_CHECK_RESULT();
3930
3931         if (rx) {
3932                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3933                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3934                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3935                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3936                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3937                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3938                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3939                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3940         } else {
3941                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3942                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3943                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3944                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3945                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3946                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3947         }
3948
3949         HWRM_UNLOCK();
3950
3951         return rc;
3952 }
3953
3954 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3955 {
3956         struct hwrm_port_qstats_input req = {0};
3957         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3958         struct bnxt_pf_info *pf = bp->pf;
3959         int rc;
3960
3961         HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3962
3963         req.port_id = rte_cpu_to_le_16(pf->port_id);
3964         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3965         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3967
3968         HWRM_CHECK_RESULT();
3969         HWRM_UNLOCK();
3970
3971         return rc;
3972 }
3973
3974 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3975 {
3976         struct hwrm_port_clr_stats_input req = {0};
3977         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3978         struct bnxt_pf_info *pf = bp->pf;
3979         int rc;
3980
3981         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3982         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3983             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3984                 return 0;
3985
3986         HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3987
3988         req.port_id = rte_cpu_to_le_16(pf->port_id);
3989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3990
3991         HWRM_CHECK_RESULT();
3992         HWRM_UNLOCK();
3993
3994         return rc;
3995 }
3996
3997 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3998 {
3999         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4000         struct hwrm_port_led_qcaps_input req = {0};
4001         int rc;
4002
4003         if (BNXT_VF(bp))
4004                 return 0;
4005
4006         HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4007         req.port_id = bp->pf->port_id;
4008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4009
4010         HWRM_CHECK_RESULT();
4011
4012         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4013                 unsigned int i;
4014
4015                 bp->leds->num_leds = resp->num_leds;
4016                 memcpy(bp->leds, &resp->led0_id,
4017                         sizeof(bp->leds[0]) * bp->leds->num_leds);
4018                 for (i = 0; i < bp->leds->num_leds; i++) {
4019                         struct bnxt_led_info *led = &bp->leds[i];
4020
4021                         uint16_t caps = led->led_state_caps;
4022
4023                         if (!led->led_group_id ||
4024                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4025                                 bp->leds->num_leds = 0;
4026                                 break;
4027                         }
4028                 }
4029         }
4030
4031         HWRM_UNLOCK();
4032
4033         return rc;
4034 }
4035
4036 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4037 {
4038         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4039         struct hwrm_port_led_cfg_input req = {0};
4040         struct bnxt_led_cfg *led_cfg;
4041         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4042         uint16_t duration = 0;
4043         int rc, i;
4044
4045         if (!bp->leds->num_leds || BNXT_VF(bp))
4046                 return -EOPNOTSUPP;
4047
4048         HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4049
4050         if (led_on) {
4051                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4052                 duration = rte_cpu_to_le_16(500);
4053         }
4054         req.port_id = bp->pf->port_id;
4055         req.num_leds = bp->leds->num_leds;
4056         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4057         for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4058                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4059                 led_cfg->led_id = bp->leds[i].led_id;
4060                 led_cfg->led_state = led_state;
4061                 led_cfg->led_blink_on = duration;
4062                 led_cfg->led_blink_off = duration;
4063                 led_cfg->led_group_id = bp->leds[i].led_group_id;
4064         }
4065
4066         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4067
4068         HWRM_CHECK_RESULT();
4069         HWRM_UNLOCK();
4070
4071         return rc;
4072 }
4073
4074 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4075                                uint32_t *length)
4076 {
4077         int rc;
4078         struct hwrm_nvm_get_dir_info_input req = {0};
4079         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4080
4081         HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4082
4083         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4084
4085         HWRM_CHECK_RESULT();
4086
4087         *entries = rte_le_to_cpu_32(resp->entries);
4088         *length = rte_le_to_cpu_32(resp->entry_length);
4089
4090         HWRM_UNLOCK();
4091         return rc;
4092 }
4093
4094 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4095 {
4096         int rc;
4097         uint32_t dir_entries;
4098         uint32_t entry_length;
4099         uint8_t *buf;
4100         size_t buflen;
4101         rte_iova_t dma_handle;
4102         struct hwrm_nvm_get_dir_entries_input req = {0};
4103         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4104
4105         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4106         if (rc != 0)
4107                 return rc;
4108
4109         *data++ = dir_entries;
4110         *data++ = entry_length;
4111         len -= 2;
4112         memset(data, 0xff, len);
4113
4114         buflen = dir_entries * entry_length;
4115         buf = rte_malloc("nvm_dir", buflen, 0);
4116         if (buf == NULL)
4117                 return -ENOMEM;
4118         dma_handle = rte_malloc_virt2iova(buf);
4119         if (dma_handle == RTE_BAD_IOVA) {
4120                 PMD_DRV_LOG(ERR,
4121                         "unable to map response address to physical memory\n");
4122                 return -ENOMEM;
4123         }
4124         HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4125         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4126         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4127
4128         if (rc == 0)
4129                 memcpy(data, buf, len > buflen ? buflen : len);
4130
4131         rte_free(buf);
4132         HWRM_CHECK_RESULT();
4133         HWRM_UNLOCK();
4134
4135         return rc;
4136 }
4137
4138 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4139                              uint32_t offset, uint32_t length,
4140                              uint8_t *data)
4141 {
4142         int rc;
4143         uint8_t *buf;
4144         rte_iova_t dma_handle;
4145         struct hwrm_nvm_read_input req = {0};
4146         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4147
4148         buf = rte_malloc("nvm_item", length, 0);
4149         if (!buf)
4150                 return -ENOMEM;
4151
4152         dma_handle = rte_malloc_virt2iova(buf);
4153         if (dma_handle == RTE_BAD_IOVA) {
4154                 PMD_DRV_LOG(ERR,
4155                         "unable to map response address to physical memory\n");
4156                 return -ENOMEM;
4157         }
4158         HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4159         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4160         req.dir_idx = rte_cpu_to_le_16(index);
4161         req.offset = rte_cpu_to_le_32(offset);
4162         req.len = rte_cpu_to_le_32(length);
4163         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4164         if (rc == 0)
4165                 memcpy(data, buf, length);
4166
4167         rte_free(buf);
4168         HWRM_CHECK_RESULT();
4169         HWRM_UNLOCK();
4170
4171         return rc;
4172 }
4173
4174 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4175 {
4176         int rc;
4177         struct hwrm_nvm_erase_dir_entry_input req = {0};
4178         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4179
4180         HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4181         req.dir_idx = rte_cpu_to_le_16(index);
4182         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4183         HWRM_CHECK_RESULT();
4184         HWRM_UNLOCK();
4185
4186         return rc;
4187 }
4188
4189
4190 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4191                           uint16_t dir_ordinal, uint16_t dir_ext,
4192                           uint16_t dir_attr, const uint8_t *data,
4193                           size_t data_len)
4194 {
4195         int rc;
4196         struct hwrm_nvm_write_input req = {0};
4197         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4198         rte_iova_t dma_handle;
4199         uint8_t *buf;
4200
4201         buf = rte_malloc("nvm_write", data_len, 0);
4202         if (!buf)
4203                 return -ENOMEM;
4204
4205         dma_handle = rte_malloc_virt2iova(buf);
4206         if (dma_handle == RTE_BAD_IOVA) {
4207                 PMD_DRV_LOG(ERR,
4208                         "unable to map response address to physical memory\n");
4209                 return -ENOMEM;
4210         }
4211         memcpy(buf, data, data_len);
4212
4213         HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4214
4215         req.dir_type = rte_cpu_to_le_16(dir_type);
4216         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4217         req.dir_ext = rte_cpu_to_le_16(dir_ext);
4218         req.dir_attr = rte_cpu_to_le_16(dir_attr);
4219         req.dir_data_length = rte_cpu_to_le_32(data_len);
4220         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4221
4222         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4223
4224         rte_free(buf);
4225         HWRM_CHECK_RESULT();
4226         HWRM_UNLOCK();
4227
4228         return rc;
4229 }
4230
4231 static void
4232 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4233 {
4234         uint32_t *count = cbdata;
4235
4236         *count = *count + 1;
4237 }
4238
4239 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4240                                      struct bnxt_vnic_info *vnic __rte_unused)
4241 {
4242         return 0;
4243 }
4244
4245 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4246 {
4247         uint32_t count = 0;
4248
4249         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4250             &count, bnxt_vnic_count_hwrm_stub);
4251
4252         return count;
4253 }
4254
4255 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4256                                         uint16_t *vnic_ids)
4257 {
4258         struct hwrm_func_vf_vnic_ids_query_input req = {0};
4259         struct hwrm_func_vf_vnic_ids_query_output *resp =
4260                                                 bp->hwrm_cmd_resp_addr;
4261         int rc;
4262
4263         /* First query all VNIC ids */
4264         HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4265
4266         req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4267         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4268         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4269
4270         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4271                 HWRM_UNLOCK();
4272                 PMD_DRV_LOG(ERR,
4273                 "unable to map VNIC ID table address to physical memory\n");
4274                 return -ENOMEM;
4275         }
4276         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4277         HWRM_CHECK_RESULT();
4278         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4279
4280         HWRM_UNLOCK();
4281
4282         return rc;
4283 }
4284
4285 /*
4286  * This function queries the VNIC IDs  for a specified VF. It then calls
4287  * the vnic_cb to update the necessary field in vnic_info with cbdata.
4288  * Then it calls the hwrm_cb function to program this new vnic configuration.
4289  */
4290 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4291         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4292         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4293 {
4294         struct bnxt_vnic_info vnic;
4295         int rc = 0;
4296         int i, num_vnic_ids;
4297         uint16_t *vnic_ids;
4298         size_t vnic_id_sz;
4299         size_t sz;
4300
4301         /* First query all VNIC ids */
4302         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4303         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4304                         RTE_CACHE_LINE_SIZE);
4305         if (vnic_ids == NULL)
4306                 return -ENOMEM;
4307
4308         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4309                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4310
4311         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4312
4313         if (num_vnic_ids < 0)
4314                 return num_vnic_ids;
4315
4316         /* Retrieve VNIC, update bd_stall then update */
4317
4318         for (i = 0; i < num_vnic_ids; i++) {
4319                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4320                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4321                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4322                 if (rc)
4323                         break;
4324                 if (vnic.mru <= 4)      /* Indicates unallocated */
4325                         continue;
4326
4327                 vnic_cb(&vnic, cbdata);
4328
4329                 rc = hwrm_cb(bp, &vnic);
4330                 if (rc)
4331                         break;
4332         }
4333
4334         rte_free(vnic_ids);
4335
4336         return rc;
4337 }
4338
4339 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4340                                               bool on)
4341 {
4342         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4343         struct hwrm_func_cfg_input req = {0};
4344         int rc;
4345
4346         HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4347
4348         req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4349         req.enables |= rte_cpu_to_le_32(
4350                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4351         req.vlan_antispoof_mode = on ?
4352                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4353                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4354         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4355
4356         HWRM_CHECK_RESULT();
4357         HWRM_UNLOCK();
4358
4359         return rc;
4360 }
4361
4362 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4363 {
4364         struct bnxt_vnic_info vnic;
4365         uint16_t *vnic_ids;
4366         size_t vnic_id_sz;
4367         int num_vnic_ids, i;
4368         size_t sz;
4369         int rc;
4370
4371         vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4372         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4373                         RTE_CACHE_LINE_SIZE);
4374         if (vnic_ids == NULL)
4375                 return -ENOMEM;
4376
4377         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4378                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4379
4380         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4381         if (rc <= 0)
4382                 goto exit;
4383         num_vnic_ids = rc;
4384
4385         /*
4386          * Loop through to find the default VNIC ID.
4387          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4388          * by sending the hwrm_func_qcfg command to the firmware.
4389          */
4390         for (i = 0; i < num_vnic_ids; i++) {
4391                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4392                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4393                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4394                                         bp->pf->first_vf_id + vf);
4395                 if (rc)
4396                         goto exit;
4397                 if (vnic.func_default) {
4398                         rte_free(vnic_ids);
4399                         return vnic.fw_vnic_id;
4400                 }
4401         }
4402         /* Could not find a default VNIC. */
4403         PMD_DRV_LOG(ERR, "No default VNIC\n");
4404 exit:
4405         rte_free(vnic_ids);
4406         return rc;
4407 }
4408
4409 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4410                          uint16_t dst_id,
4411                          struct bnxt_filter_info *filter)
4412 {
4413         int rc = 0;
4414         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4415         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4416         uint32_t enables = 0;
4417
4418         if (filter->fw_em_filter_id != UINT64_MAX)
4419                 bnxt_hwrm_clear_em_filter(bp, filter);
4420
4421         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4422
4423         req.flags = rte_cpu_to_le_32(filter->flags);
4424
4425         enables = filter->enables |
4426               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4427         req.dst_id = rte_cpu_to_le_16(dst_id);
4428
4429         if (filter->ip_addr_type) {
4430                 req.ip_addr_type = filter->ip_addr_type;
4431                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4432         }
4433         if (enables &
4434             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4435                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4436         if (enables &
4437             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4438                 memcpy(req.src_macaddr, filter->src_macaddr,
4439                        RTE_ETHER_ADDR_LEN);
4440         if (enables &
4441             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4442                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4443                        RTE_ETHER_ADDR_LEN);
4444         if (enables &
4445             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4446                 req.ovlan_vid = filter->l2_ovlan;
4447         if (enables &
4448             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4449                 req.ivlan_vid = filter->l2_ivlan;
4450         if (enables &
4451             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4452                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4453         if (enables &
4454             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4455                 req.ip_protocol = filter->ip_protocol;
4456         if (enables &
4457             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4458                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4459         if (enables &
4460             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4461                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4462         if (enables &
4463             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4464                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4465         if (enables &
4466             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4467                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4468         if (enables &
4469             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4470                 req.mirror_vnic_id = filter->mirror_vnic_id;
4471
4472         req.enables = rte_cpu_to_le_32(enables);
4473
4474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4475
4476         HWRM_CHECK_RESULT();
4477
4478         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4479         HWRM_UNLOCK();
4480
4481         return rc;
4482 }
4483
4484 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4485 {
4486         int rc = 0;
4487         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4488         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4489
4490         if (filter->fw_em_filter_id == UINT64_MAX)
4491                 return 0;
4492
4493         HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4494
4495         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4496
4497         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4498
4499         HWRM_CHECK_RESULT();
4500         HWRM_UNLOCK();
4501
4502         filter->fw_em_filter_id = UINT64_MAX;
4503         filter->fw_l2_filter_id = UINT64_MAX;
4504
4505         return 0;
4506 }
4507
4508 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4509                          uint16_t dst_id,
4510                          struct bnxt_filter_info *filter)
4511 {
4512         int rc = 0;
4513         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4514         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4515                                                 bp->hwrm_cmd_resp_addr;
4516         uint32_t enables = 0;
4517
4518         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4519                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4520
4521         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4522
4523         req.flags = rte_cpu_to_le_32(filter->flags);
4524
4525         enables = filter->enables |
4526               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4527         req.dst_id = rte_cpu_to_le_16(dst_id);
4528
4529         if (filter->ip_addr_type) {
4530                 req.ip_addr_type = filter->ip_addr_type;
4531                 enables |=
4532                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4533         }
4534         if (enables &
4535             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4536                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4537         if (enables &
4538             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4539                 memcpy(req.src_macaddr, filter->src_macaddr,
4540                        RTE_ETHER_ADDR_LEN);
4541         if (enables &
4542             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4543                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4544         if (enables &
4545             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4546                 req.ip_protocol = filter->ip_protocol;
4547         if (enables &
4548             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4549                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4550         if (enables &
4551             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4552                 req.src_ipaddr_mask[0] =
4553                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4554         if (enables &
4555             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4556                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4557         if (enables &
4558             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4559                 req.dst_ipaddr_mask[0] =
4560                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4561         if (enables &
4562             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4563                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4564         if (enables &
4565             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4566                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4567         if (enables &
4568             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4569                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4570         if (enables &
4571             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4572                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4573         if (enables &
4574             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4575                 req.mirror_vnic_id = filter->mirror_vnic_id;
4576
4577         req.enables = rte_cpu_to_le_32(enables);
4578
4579         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4580
4581         HWRM_CHECK_RESULT();
4582
4583         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4584         filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4585         HWRM_UNLOCK();
4586
4587         return rc;
4588 }
4589
4590 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4591                                 struct bnxt_filter_info *filter)
4592 {
4593         int rc = 0;
4594         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4595         struct hwrm_cfa_ntuple_filter_free_output *resp =
4596                                                 bp->hwrm_cmd_resp_addr;
4597
4598         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4599                 return 0;
4600
4601         HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4602
4603         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4604
4605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4606
4607         HWRM_CHECK_RESULT();
4608         HWRM_UNLOCK();
4609
4610         filter->fw_ntuple_filter_id = UINT64_MAX;
4611
4612         return 0;
4613 }
4614
4615 static int
4616 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4617 {
4618         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4619         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4620         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4621         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4622         uint16_t *ring_tbl = vnic->rss_table;
4623         int nr_ctxs = vnic->num_lb_ctxts;
4624         int max_rings = bp->rx_nr_rings;
4625         int i, j, k, cnt;
4626         int rc = 0;
4627
4628         for (i = 0, k = 0; i < nr_ctxs; i++) {
4629                 struct bnxt_rx_ring_info *rxr;
4630                 struct bnxt_cp_ring_info *cpr;
4631
4632                 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4633
4634                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4635                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4636                 req.hash_mode_flags = vnic->hash_mode;
4637
4638                 req.ring_grp_tbl_addr =
4639                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4640                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4641                                      2 * sizeof(*ring_tbl));
4642                 req.hash_key_tbl_addr =
4643                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4644
4645                 req.ring_table_pair_index = i;
4646                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4647
4648                 for (j = 0; j < 64; j++) {
4649                         uint16_t ring_id;
4650
4651                         /* Find next active ring. */
4652                         for (cnt = 0; cnt < max_rings; cnt++) {
4653                                 if (rx_queue_state[k] !=
4654                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4655                                         break;
4656                                 if (++k == max_rings)
4657                                         k = 0;
4658                         }
4659
4660                         /* Return if no rings are active. */
4661                         if (cnt == max_rings) {
4662                                 HWRM_UNLOCK();
4663                                 return 0;
4664                         }
4665
4666                         /* Add rx/cp ring pair to RSS table. */
4667                         rxr = rxqs[k]->rx_ring;
4668                         cpr = rxqs[k]->cp_ring;
4669
4670                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4671                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4672                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4673                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4674
4675                         if (++k == max_rings)
4676                                 k = 0;
4677                 }
4678                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4679                                             BNXT_USE_CHIMP_MB);
4680
4681                 HWRM_CHECK_RESULT();
4682                 HWRM_UNLOCK();
4683         }
4684
4685         return rc;
4686 }
4687
4688 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4689 {
4690         unsigned int rss_idx, fw_idx, i;
4691
4692         if (!(vnic->rss_table && vnic->hash_type))
4693                 return 0;
4694
4695         if (BNXT_CHIP_THOR(bp))
4696                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4697
4698         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4699                 return 0;
4700
4701         if (vnic->rss_table && vnic->hash_type) {
4702                 /*
4703                  * Fill the RSS hash & redirection table with
4704                  * ring group ids for all VNICs
4705                  */
4706                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4707                         rss_idx++, fw_idx++) {
4708                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4709                                 fw_idx %= bp->rx_cp_nr_rings;
4710                                 if (vnic->fw_grp_ids[fw_idx] !=
4711                                     INVALID_HW_RING_ID)
4712                                         break;
4713                                 fw_idx++;
4714                         }
4715                         if (i == bp->rx_cp_nr_rings)
4716                                 return 0;
4717                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4718                 }
4719                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4720         }
4721
4722         return 0;
4723 }
4724
4725 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4726         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4727 {
4728         uint16_t flags;
4729
4730         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4731
4732         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4733         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4734
4735         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4736         req->num_cmpl_dma_aggr_during_int =
4737                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4738
4739         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4740
4741         /* min timer set to 1/2 of interrupt timer */
4742         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4743
4744         /* buf timer set to 1/4 of interrupt timer */
4745         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4746
4747         req->cmpl_aggr_dma_tmr_during_int =
4748                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4749
4750         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4751                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4752         req->flags = rte_cpu_to_le_16(flags);
4753 }
4754
4755 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4756                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4757 {
4758         struct hwrm_ring_aggint_qcaps_input req = {0};
4759         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4760         uint32_t enables;
4761         uint16_t flags;
4762         int rc;
4763
4764         HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4766         HWRM_CHECK_RESULT();
4767
4768         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4769         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4770
4771         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4772                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4773         agg_req->flags = rte_cpu_to_le_16(flags);
4774         enables =
4775          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4776          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4777         agg_req->enables = rte_cpu_to_le_32(enables);
4778
4779         HWRM_UNLOCK();
4780         return rc;
4781 }
4782
4783 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4784                         struct bnxt_coal *coal, uint16_t ring_id)
4785 {
4786         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4787         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4788                                                 bp->hwrm_cmd_resp_addr;
4789         int rc;
4790
4791         /* Set ring coalesce parameters only for 100G NICs */
4792         if (BNXT_CHIP_THOR(bp)) {
4793                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4794                         return -1;
4795         } else if (bnxt_stratus_device(bp)) {
4796                 bnxt_hwrm_set_coal_params(coal, &req);
4797         } else {
4798                 return 0;
4799         }
4800
4801         HWRM_PREP(&req,
4802                   HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4803                   BNXT_USE_CHIMP_MB);
4804         req.ring_id = rte_cpu_to_le_16(ring_id);
4805         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4806         HWRM_CHECK_RESULT();
4807         HWRM_UNLOCK();
4808         return 0;
4809 }
4810
4811 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4812 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4813 {
4814         struct hwrm_func_backing_store_qcaps_input req = {0};
4815         struct hwrm_func_backing_store_qcaps_output *resp =
4816                 bp->hwrm_cmd_resp_addr;
4817         struct bnxt_ctx_pg_info *ctx_pg;
4818         struct bnxt_ctx_mem_info *ctx;
4819         int total_alloc_len;
4820         int rc, i, tqm_rings;
4821
4822         if (!BNXT_CHIP_THOR(bp) ||
4823             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4824             BNXT_VF(bp) ||
4825             bp->ctx)
4826                 return 0;
4827
4828         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4829         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4830         HWRM_CHECK_RESULT_SILENT();
4831
4832         total_alloc_len = sizeof(*ctx);
4833         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4834                           RTE_CACHE_LINE_SIZE);
4835         if (!ctx) {
4836                 rc = -ENOMEM;
4837                 goto ctx_err;
4838         }
4839
4840         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4841         ctx->qp_min_qp1_entries =
4842                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4843         ctx->qp_max_l2_entries =
4844                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4845         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4846         ctx->srq_max_l2_entries =
4847                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4848         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4849         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4850         ctx->cq_max_l2_entries =
4851                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4852         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4853         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4854         ctx->vnic_max_vnic_entries =
4855                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4856         ctx->vnic_max_ring_table_entries =
4857                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4858         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4859         ctx->stat_max_entries =
4860                 rte_le_to_cpu_32(resp->stat_max_entries);
4861         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4862         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4863         ctx->tqm_min_entries_per_ring =
4864                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4865         ctx->tqm_max_entries_per_ring =
4866                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4867         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4868         if (!ctx->tqm_entries_multiple)
4869                 ctx->tqm_entries_multiple = 1;
4870         ctx->mrav_max_entries =
4871                 rte_le_to_cpu_32(resp->mrav_max_entries);
4872         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4873         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4874         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4875         ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4876
4877         if (!ctx->tqm_fp_rings_count)
4878                 ctx->tqm_fp_rings_count = bp->max_q;
4879
4880         tqm_rings = ctx->tqm_fp_rings_count + 1;
4881
4882         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4883                             sizeof(*ctx_pg) * tqm_rings,
4884                             RTE_CACHE_LINE_SIZE);
4885         if (!ctx_pg) {
4886                 rc = -ENOMEM;
4887                 goto ctx_err;
4888         }
4889         for (i = 0; i < tqm_rings; i++, ctx_pg++)
4890                 ctx->tqm_mem[i] = ctx_pg;
4891
4892         bp->ctx = ctx;
4893 ctx_err:
4894         HWRM_UNLOCK();
4895         return rc;
4896 }
4897
4898 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4899 {
4900         struct hwrm_func_backing_store_cfg_input req = {0};
4901         struct hwrm_func_backing_store_cfg_output *resp =
4902                 bp->hwrm_cmd_resp_addr;
4903         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4904         struct bnxt_ctx_pg_info *ctx_pg;
4905         uint32_t *num_entries;
4906         uint64_t *pg_dir;
4907         uint8_t *pg_attr;
4908         uint32_t ena;
4909         int i, rc;
4910
4911         if (!ctx)
4912                 return 0;
4913
4914         HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4915         req.enables = rte_cpu_to_le_32(enables);
4916
4917         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4918                 ctx_pg = &ctx->qp_mem;
4919                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4920                 req.qp_num_qp1_entries =
4921                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4922                 req.qp_num_l2_entries =
4923                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4924                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4925                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4926                                       &req.qpc_pg_size_qpc_lvl,
4927                                       &req.qpc_page_dir);
4928         }
4929
4930         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4931                 ctx_pg = &ctx->srq_mem;
4932                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4933                 req.srq_num_l2_entries =
4934                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4935                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4936                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4937                                       &req.srq_pg_size_srq_lvl,
4938                                       &req.srq_page_dir);
4939         }
4940
4941         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4942                 ctx_pg = &ctx->cq_mem;
4943                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4944                 req.cq_num_l2_entries =
4945                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4946                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4947                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4948                                       &req.cq_pg_size_cq_lvl,
4949                                       &req.cq_page_dir);
4950         }
4951
4952         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4953                 ctx_pg = &ctx->vnic_mem;
4954                 req.vnic_num_vnic_entries =
4955                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4956                 req.vnic_num_ring_table_entries =
4957                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4958                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4959                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4960                                       &req.vnic_pg_size_vnic_lvl,
4961                                       &req.vnic_page_dir);
4962         }
4963
4964         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4965                 ctx_pg = &ctx->stat_mem;
4966                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4967                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4968                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4969                                       &req.stat_pg_size_stat_lvl,
4970                                       &req.stat_page_dir);
4971         }
4972
4973         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4974         num_entries = &req.tqm_sp_num_entries;
4975         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4976         pg_dir = &req.tqm_sp_page_dir;
4977         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4978         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4979                 if (!(enables & ena))
4980                         continue;
4981
4982                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4983
4984                 ctx_pg = ctx->tqm_mem[i];
4985                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4986                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4987         }
4988
4989         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4990         HWRM_CHECK_RESULT();
4991         HWRM_UNLOCK();
4992
4993         return rc;
4994 }
4995
4996 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4997 {
4998         struct hwrm_port_qstats_ext_input req = {0};
4999         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5000         struct bnxt_pf_info *pf = bp->pf;
5001         int rc;
5002
5003         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5004               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5005                 return 0;
5006
5007         HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5008
5009         req.port_id = rte_cpu_to_le_16(pf->port_id);
5010         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5011                 req.tx_stat_host_addr =
5012                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5013                 req.tx_stat_size =
5014                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5015         }
5016         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5017                 req.rx_stat_host_addr =
5018                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5019                 req.rx_stat_size =
5020                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5021         }
5022         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5023
5024         if (rc) {
5025                 bp->fw_rx_port_stats_ext_size = 0;
5026                 bp->fw_tx_port_stats_ext_size = 0;
5027         } else {
5028                 bp->fw_rx_port_stats_ext_size =
5029                         rte_le_to_cpu_16(resp->rx_stat_size);
5030                 bp->fw_tx_port_stats_ext_size =
5031                         rte_le_to_cpu_16(resp->tx_stat_size);
5032         }
5033
5034         HWRM_CHECK_RESULT();
5035         HWRM_UNLOCK();
5036
5037         return rc;
5038 }
5039
5040 int
5041 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5042 {
5043         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5044         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5045                 bp->hwrm_cmd_resp_addr;
5046         int rc = 0;
5047
5048         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5049         req.tunnel_type = type;
5050         req.dest_fid = bp->fw_fid;
5051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5052         HWRM_CHECK_RESULT();
5053
5054         HWRM_UNLOCK();
5055
5056         return rc;
5057 }
5058
5059 int
5060 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5061 {
5062         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5063         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5064                 bp->hwrm_cmd_resp_addr;
5065         int rc = 0;
5066
5067         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5068         req.tunnel_type = type;
5069         req.dest_fid = bp->fw_fid;
5070         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5071         HWRM_CHECK_RESULT();
5072
5073         HWRM_UNLOCK();
5074
5075         return rc;
5076 }
5077
5078 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5079 {
5080         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5081         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5082                 bp->hwrm_cmd_resp_addr;
5083         int rc = 0;
5084
5085         HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5086         req.src_fid = bp->fw_fid;
5087         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5088         HWRM_CHECK_RESULT();
5089
5090         if (type)
5091                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5092
5093         HWRM_UNLOCK();
5094
5095         return rc;
5096 }
5097
5098 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5099                                    uint16_t *dst_fid)
5100 {
5101         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5102         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5103                 bp->hwrm_cmd_resp_addr;
5104         int rc = 0;
5105
5106         HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5107         req.src_fid = bp->fw_fid;
5108         req.tunnel_type = tun_type;
5109         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5110         HWRM_CHECK_RESULT();
5111
5112         if (dst_fid)
5113                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5114
5115         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5116
5117         HWRM_UNLOCK();
5118
5119         return rc;
5120 }
5121
5122 int bnxt_hwrm_set_mac(struct bnxt *bp)
5123 {
5124         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5125         struct hwrm_func_vf_cfg_input req = {0};
5126         int rc = 0;
5127
5128         if (!BNXT_VF(bp))
5129                 return 0;
5130
5131         HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5132
5133         req.enables =
5134                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5135         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5136
5137         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5138
5139         HWRM_CHECK_RESULT();
5140
5141         HWRM_UNLOCK();
5142
5143         return rc;
5144 }
5145
5146 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5147 {
5148         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5149         struct hwrm_func_drv_if_change_input req = {0};
5150         uint32_t flags;
5151         int rc;
5152
5153         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5154                 return 0;
5155
5156         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5157          * If we issue FUNC_DRV_IF_CHANGE with flags down before
5158          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5159          */
5160         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5161                 return 0;
5162
5163         HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5164
5165         if (up)
5166                 req.flags =
5167                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5168
5169         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5170
5171         HWRM_CHECK_RESULT();
5172         flags = rte_le_to_cpu_32(resp->flags);
5173         HWRM_UNLOCK();
5174
5175         if (!up)
5176                 return 0;
5177
5178         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5179                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5180                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5181         }
5182
5183         return 0;
5184 }
5185
5186 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5187 {
5188         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5189         struct bnxt_error_recovery_info *info = bp->recovery_info;
5190         struct hwrm_error_recovery_qcfg_input req = {0};
5191         uint32_t flags = 0;
5192         unsigned int i;
5193         int rc;
5194
5195         /* Older FW does not have error recovery support */
5196         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5197                 return 0;
5198
5199         HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5200
5201         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5202
5203         HWRM_CHECK_RESULT();
5204
5205         flags = rte_le_to_cpu_32(resp->flags);
5206         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5207                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5208         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5209                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5210
5211         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5212             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5213                 rc = -EINVAL;
5214                 goto err;
5215         }
5216
5217         /* FW returned values are in units of 100msec */
5218         info->driver_polling_freq =
5219                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5220         info->master_func_wait_period =
5221                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5222         info->normal_func_wait_period =
5223                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5224         info->master_func_wait_period_after_reset =
5225                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5226         info->max_bailout_time_after_reset =
5227                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5228         info->status_regs[BNXT_FW_STATUS_REG] =
5229                 rte_le_to_cpu_32(resp->fw_health_status_reg);
5230         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5231                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5232         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5233                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5234         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5235                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5236         info->reg_array_cnt =
5237                 rte_le_to_cpu_32(resp->reg_array_cnt);
5238
5239         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5240                 rc = -EINVAL;
5241                 goto err;
5242         }
5243
5244         for (i = 0; i < info->reg_array_cnt; i++) {
5245                 info->reset_reg[i] =
5246                         rte_le_to_cpu_32(resp->reset_reg[i]);
5247                 info->reset_reg_val[i] =
5248                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
5249                 info->delay_after_reset[i] =
5250                         resp->delay_after_reset[i];
5251         }
5252 err:
5253         HWRM_UNLOCK();
5254
5255         /* Map the FW status registers */
5256         if (!rc)
5257                 rc = bnxt_map_fw_health_status_regs(bp);
5258
5259         if (rc) {
5260                 rte_free(bp->recovery_info);
5261                 bp->recovery_info = NULL;
5262         }
5263         return rc;
5264 }
5265
5266 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5267 {
5268         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5269         struct hwrm_fw_reset_input req = {0};
5270         int rc;
5271
5272         if (!BNXT_PF(bp))
5273                 return -EOPNOTSUPP;
5274
5275         HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5276
5277         req.embedded_proc_type =
5278                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5279         req.selfrst_status =
5280                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5281         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5282
5283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5284                                     BNXT_USE_KONG(bp));
5285
5286         HWRM_CHECK_RESULT();
5287         HWRM_UNLOCK();
5288
5289         return rc;
5290 }
5291
5292 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5293 {
5294         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5295         struct hwrm_port_ts_query_input req = {0};
5296         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5297         uint32_t flags = 0;
5298         int rc;
5299
5300         if (!ptp)
5301                 return 0;
5302
5303         HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5304
5305         switch (path) {
5306         case BNXT_PTP_FLAGS_PATH_TX:
5307                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5308                 break;
5309         case BNXT_PTP_FLAGS_PATH_RX:
5310                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5311                 break;
5312         case BNXT_PTP_FLAGS_CURRENT_TIME:
5313                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5314                 break;
5315         }
5316
5317         req.flags = rte_cpu_to_le_32(flags);
5318         req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5319
5320         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5321
5322         HWRM_CHECK_RESULT();
5323
5324         if (timestamp) {
5325                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5326                 *timestamp |=
5327                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5328         }
5329         HWRM_UNLOCK();
5330
5331         return rc;
5332 }
5333
5334 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5335 {
5336         int rc = 0;
5337
5338         struct hwrm_cfa_counter_qcaps_input req = {0};
5339         struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5340
5341         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5342                 PMD_DRV_LOG(DEBUG,
5343                             "Not a PF or trusted VF. Command not supported\n");
5344                 return 0;
5345         }
5346
5347         HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5348         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5349         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5350
5351         HWRM_CHECK_RESULT();
5352         if (max_fc)
5353                 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5354         HWRM_UNLOCK();
5355
5356         return 0;
5357 }
5358
5359 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5360 {
5361         int rc = 0;
5362         struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5363         struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5364
5365         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5366                 PMD_DRV_LOG(DEBUG,
5367                             "Not a PF or trusted VF. Command not supported\n");
5368                 return 0;
5369         }
5370
5371         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5372
5373         req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5374         req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5375         req.page_dir = rte_cpu_to_le_64(dma_addr);
5376
5377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5378
5379         HWRM_CHECK_RESULT();
5380         if (ctx_id) {
5381                 *ctx_id  = rte_le_to_cpu_16(resp->ctx_id);
5382                 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5383         }
5384         HWRM_UNLOCK();
5385
5386         return 0;
5387 }
5388
5389 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5390 {
5391         int rc = 0;
5392         struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5393         struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5394
5395         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5396                 PMD_DRV_LOG(DEBUG,
5397                             "Not a PF or trusted VF. Command not supported\n");
5398                 return 0;
5399         }
5400
5401         HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5402
5403         req.ctx_id = rte_cpu_to_le_16(ctx_id);
5404
5405         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5406
5407         HWRM_CHECK_RESULT();
5408         HWRM_UNLOCK();
5409
5410         return rc;
5411 }
5412
5413 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5414                               uint16_t cntr, uint16_t ctx_id,
5415                               uint32_t num_entries, bool enable)
5416 {
5417         struct hwrm_cfa_counter_cfg_input req = {0};
5418         struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5419         uint16_t flags = 0;
5420         int rc;
5421
5422         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5423                 PMD_DRV_LOG(DEBUG,
5424                             "Not a PF or trusted VF. Command not supported\n");
5425                 return 0;
5426         }
5427
5428         HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5429
5430         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5431         req.counter_type = rte_cpu_to_le_16(cntr);
5432         flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5433                 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5434         flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5435         if (dir == BNXT_DIR_RX)
5436                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5437         else if (dir == BNXT_DIR_TX)
5438                 flags |=  HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5439         req.flags = rte_cpu_to_le_16(flags);
5440         req.ctx_id =  rte_cpu_to_le_16(ctx_id);
5441         req.num_entries = rte_cpu_to_le_32(num_entries);
5442
5443         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5444         HWRM_CHECK_RESULT();
5445         HWRM_UNLOCK();
5446
5447         return 0;
5448 }
5449
5450 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5451                                  enum bnxt_flow_dir dir,
5452                                  uint16_t cntr,
5453                                  uint16_t num_entries)
5454 {
5455         struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5456         struct hwrm_cfa_counter_qstats_input req = {0};
5457         uint16_t flow_ctx_id = 0;
5458         uint16_t flags = 0;
5459         int rc = 0;
5460
5461         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5462                 PMD_DRV_LOG(DEBUG,
5463                             "Not a PF or trusted VF. Command not supported\n");
5464                 return 0;
5465         }
5466
5467         if (dir == BNXT_DIR_RX) {
5468                 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5469                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5470         } else if (dir == BNXT_DIR_TX) {
5471                 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5472                 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5473         }
5474
5475         HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5476         req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5477         req.counter_type = rte_cpu_to_le_16(cntr);
5478         req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5479         req.num_entries = rte_cpu_to_le_16(num_entries);
5480         req.flags = rte_cpu_to_le_16(flags);
5481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5482
5483         HWRM_CHECK_RESULT();
5484         HWRM_UNLOCK();
5485
5486         return 0;
5487 }
5488
5489 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
5490 {
5491         struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5492         struct hwrm_cfa_vfr_alloc_input req = {0};
5493         int rc;
5494
5495         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5496                 PMD_DRV_LOG(DEBUG,
5497                             "Not a PF or trusted VF. Command not supported\n");
5498                 return 0;
5499         }
5500
5501         HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
5502         req.vf_id = rte_cpu_to_le_16(vf_idx);
5503         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5504                  bp->eth_dev->data->name, vf_idx);
5505
5506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5507         HWRM_CHECK_RESULT();
5508
5509         HWRM_UNLOCK();
5510         PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
5511         return rc;
5512 }
5513
5514 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
5515 {
5516         struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
5517         struct hwrm_cfa_vfr_free_input req = {0};
5518         int rc;
5519
5520         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5521                 PMD_DRV_LOG(DEBUG,
5522                             "Not a PF or trusted VF. Command not supported\n");
5523                 return 0;
5524         }
5525
5526         HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
5527         req.vf_id = rte_cpu_to_le_16(vf_idx);
5528         snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
5529                  bp->eth_dev->data->name, vf_idx);
5530
5531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5532         HWRM_CHECK_RESULT();
5533         HWRM_UNLOCK();
5534         PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
5535         return rc;
5536 }
5537
5538 #ifdef RTE_LIBRTE_BNXT_PMD_SYSTEM
5539 int
5540 bnxt_hwrm_oem_cmd(struct bnxt *bp, uint32_t entry_num)
5541 {
5542         struct hwrm_oem_cmd_input req = {0};
5543         struct hwrm_oem_cmd_output *resp = bp->hwrm_cmd_resp_addr;
5544         struct bnxt_dmabuf_info oem_data;
5545         int rc = 0;
5546
5547         HWRM_PREP(&req, HWRM_OEM_CMD, BNXT_USE_CHIMP_MB);
5548         req.IANA = 0x14e4;
5549
5550         memset(&oem_data, 0, sizeof(struct bnxt_dmabuf_info));
5551         oem_data.entry_num = (entry_num);
5552         memcpy(&req.oem_data[0], &oem_data, sizeof(struct bnxt_dmabuf_info));
5553
5554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5555         HWRM_CHECK_RESULT();
5556
5557         bp->dmabuf.entry_num = entry_num;
5558
5559         HWRM_UNLOCK();
5560
5561         return rc;
5562 }
5563 #endif /* RTE_LIBRTE_BNXT_PMD_SYSTEM */