drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 156                         req->req_type);
 157                 goto err_ret;
 158         }
 159         return 0;
 160
 161 err_ret:
 162         return -1;
 163 }
 164
 165 /*
 166  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 167  * spinlock, and does initial processing.
 168  *
 169  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 170  * releases the spinlock only if it returns.  If the regular int return codes
 171  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 172  * directly, rather it should be copied and modified to suit the function.
 173  *
 174  * HWRM_UNLOCK() must be called after all response processing is completed.
 175  */
 176 #define HWRM_PREP(req, type, kong) do { \
 177         rte_spinlock_lock(&bp->hwrm_lock); \
 178         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 179         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 180         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 181         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 182                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 183         req.target_id = rte_cpu_to_le_16(0xffff); \
 184         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 185 } while (0)
 186
 187 #define HWRM_CHECK_RESULT_SILENT() do {\
 188         if (rc) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192         if (resp->error_code) { \
 193                 rc = rte_le_to_cpu_16(resp->error_code); \
 194                 rte_spinlock_unlock(&bp->hwrm_lock); \
 195                 return rc; \
 196         } \
 197 } while (0)
 198
 199 #define HWRM_CHECK_RESULT() do {\
 200         if (rc) { \
 201                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 204                         rc = -EACCES; \
 205                 else if (rc > 0) \
 206                         rc = -EINVAL; \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 if (resp->resp_len >= 16) { \
 212                         struct hwrm_err_output *tmp_hwrm_err_op = \
 213                                                 (void *)resp; \
 214                         PMD_DRV_LOG(ERR, \
 215                                 "error %d:%d:%08x:%04x\n", \
 216                                 rc, tmp_hwrm_err_op->cmd_err, \
 217                                 rte_le_to_cpu_32(\
 218                                         tmp_hwrm_err_op->opaque_0), \
 219                                 rte_le_to_cpu_16(\
 220                                         tmp_hwrm_err_op->opaque_1)); \
 221                 } else { \
 222                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = UINT64_MAX;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 PMD_DRV_LOG(DEBUG,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399         req.flags |=
 400         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 401
 402         enables = filter->enables |
 403               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 404         req.dst_id = rte_cpu_to_le_16(dst_id);
 405
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 408                 memcpy(req.l2_addr, filter->l2_addr,
 409                        RTE_ETHER_ADDR_LEN);
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 412                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 413                        RTE_ETHER_ADDR_LEN);
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 416                 req.l2_ovlan = filter->l2_ovlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 419                 req.l2_ivlan = filter->l2_ivlan;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 422                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 425                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 427                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 428         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 429                 req.src_type = filter->src_type;
 430
 431         req.enables = rte_cpu_to_le_32(enables);
 432
 433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 434
 435         HWRM_CHECK_RESULT();
 436
 437         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 438         HWRM_UNLOCK();
 439
 440         return rc;
 441 }
 442
 443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 444 {
 445         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 447         uint32_t flags = 0;
 448         int rc;
 449
 450         if (!ptp)
 451                 return 0;
 452
 453         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 454
 455         if (ptp->rx_filter)
 456                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 457         else
 458                 flags |=
 459                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 460         if (ptp->tx_tstamp_en)
 461                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 462         else
 463                 flags |=
 464                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 465         req.flags = rte_cpu_to_le_32(flags);
 466         req.enables = rte_cpu_to_le_32
 467                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 468         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 471         HWRM_UNLOCK();
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 480         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 482
 483 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 484         if (ptp)
 485                 return 0;
 486
 487         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 488
 489         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 490
 491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 492
 493         HWRM_CHECK_RESULT();
 494
 495         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 496                 return 0;
 497
 498         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 499         if (!ptp)
 500                 return -ENOMEM;
 501
 502         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 503                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 504         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 505                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 506         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 507                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 508         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 509                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 510         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 511                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 512         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 513                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 514         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 515                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 516         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 517                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 518         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 519                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 520
 521         ptp->bp = bp;
 522         bp->ptp_cfg = ptp;
 523
 524         return 0;
 525 }
 526
 527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 531         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 532         uint16_t new_max_vfs;
 533         uint32_t flags;
 534         int i;
 535
 536         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 537
 538         req.fid = rte_cpu_to_le_16(0xffff);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 545         flags = rte_le_to_cpu_32(resp->flags);
 546         if (BNXT_PF(bp)) {
 547                 bp->pf.port_id = resp->port_id;
 548                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 549                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 550                 new_max_vfs = bp->pdev->max_vfs;
 551                 if (new_max_vfs != bp->pf.max_vfs) {
 552                         if (bp->pf.vf_info)
 553                                 rte_free(bp->pf.vf_info);
 554                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 555                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 556                         bp->pf.max_vfs = new_max_vfs;
 557                         for (i = 0; i < new_max_vfs; i++) {
 558                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 559                                 bp->pf.vf_info[i].vlan_table =
 560                                         rte_zmalloc("VF VLAN table",
 561                                                     getpagesize(),
 562                                                     getpagesize());
 563                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 564                                         PMD_DRV_LOG(ERR,
 565                                         "Fail to alloc VLAN table for VF %d\n",
 566                                         i);
 567                                 else
 568                                         rte_mem_lock_page(
 569                                                 bp->pf.vf_info[i].vlan_table);
 570                                 bp->pf.vf_info[i].vlan_as_table =
 571                                         rte_zmalloc("VF VLAN AS table",
 572                                                     getpagesize(),
 573                                                     getpagesize());
 574                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 575                                         PMD_DRV_LOG(ERR,
 576                                         "Alloc VLAN AS table for VF %d fail\n",
 577                                         i);
 578                                 else
 579                                         rte_mem_lock_page(
 580                                                bp->pf.vf_info[i].vlan_as_table);
 581                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 582                         }
 583                 }
 584         }
 585
 586         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 587         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 588         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 589         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 590         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 591         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 592         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 593         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 594         /* TODO: For now, do not support VMDq/RFS on VFs. */
 595         if (BNXT_PF(bp)) {
 596                 if (bp->pf.max_vfs)
 597                         bp->max_vnics = 1;
 598                 else
 599                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 600         } else {
 601                 bp->max_vnics = 1;
 602         }
 603         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 604         if (BNXT_PF(bp)) {
 605                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 606                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 607                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 608                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 609                         HWRM_UNLOCK();
 610                         bnxt_hwrm_ptp_qcfg(bp);
 611                 }
 612         }
 613
 614         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 615                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 616
 617         HWRM_UNLOCK();
 618
 619         return rc;
 620 }
 621
 622 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 623 {
 624         int rc;
 625
 626         rc = __bnxt_hwrm_func_qcaps(bp);
 627         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 628                 rc = bnxt_alloc_ctx_mem(bp);
 629                 if (rc)
 630                         return rc;
 631
 632                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 633                 if (!rc)
 634                         bp->flags |= BNXT_FLAG_NEW_RM;
 635         }
 636
 637         return rc;
 638 }
 639
 640 int bnxt_hwrm_func_reset(struct bnxt *bp)
 641 {
 642         int rc = 0;
 643         struct hwrm_func_reset_input req = {.req_type = 0 };
 644         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 645
 646         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 647
 648         req.enables = rte_cpu_to_le_32(0);
 649
 650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 651
 652         HWRM_CHECK_RESULT();
 653         HWRM_UNLOCK();
 654
 655         return rc;
 656 }
 657
 658 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 659 {
 660         int rc;
 661         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 662         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 663
 664         if (bp->flags & BNXT_FLAG_REGISTERED)
 665                 return 0;
 666
 667         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 668         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 669                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 670         req.ver_maj = RTE_VER_YEAR;
 671         req.ver_min = RTE_VER_MONTH;
 672         req.ver_upd = RTE_VER_MINOR;
 673
 674         if (BNXT_PF(bp)) {
 675                 req.enables |= rte_cpu_to_le_32(
 676                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 677                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 678                        RTE_MIN(sizeof(req.vf_req_fwd),
 679                                sizeof(bp->pf.vf_req_fwd)));
 680
 681                 /*
 682                  * PF can sniff HWRM API issued by VF. This can be set up by
 683                  * linux driver and inherited by the DPDK PF driver. Clear
 684                  * this HWRM sniffer list in FW because DPDK PF driver does
 685                  * not support this.
 686                  */
 687                 req.flags =
 688                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 689         }
 690
 691         req.async_event_fwd[0] |=
 692                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 693                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 694                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 695         req.async_event_fwd[1] |=
 696                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 697                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 698
 699         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 700
 701         HWRM_CHECK_RESULT();
 702         HWRM_UNLOCK();
 703
 704         bp->flags |= BNXT_FLAG_REGISTERED;
 705
 706         return rc;
 707 }
 708
 709 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 710 {
 711         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 712                 return 0;
 713
 714         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 715 }
 716
 717 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 718 {
 719         int rc;
 720         uint32_t flags = 0;
 721         uint32_t enables;
 722         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 723         struct hwrm_func_vf_cfg_input req = {0};
 724
 725         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 726
 727         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 728                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 729                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 730                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 731                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 732
 733         if (BNXT_HAS_RING_GRPS(bp)) {
 734                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 735                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 736         }
 737
 738         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 739         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 740                                             AGG_RING_MULTIPLIER);
 741         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 742         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 743                                               bp->tx_nr_rings);
 744         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 745         if (bp->vf_resv_strategy ==
 746             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 747                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 748                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 749                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 750                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 751                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 752                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 753         }
 754
 755         if (test)
 756                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 757                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 758                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 759                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 760                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 761                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 762
 763         if (test && BNXT_HAS_RING_GRPS(bp))
 764                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 765
 766         req.flags = rte_cpu_to_le_32(flags);
 767         req.enables |= rte_cpu_to_le_32(enables);
 768
 769         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 770
 771         if (test)
 772                 HWRM_CHECK_RESULT_SILENT();
 773         else
 774                 HWRM_CHECK_RESULT();
 775
 776         HWRM_UNLOCK();
 777         return rc;
 778 }
 779
 780 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 781 {
 782         int rc;
 783         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 784         struct hwrm_func_resource_qcaps_input req = {0};
 785
 786         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 787         req.fid = rte_cpu_to_le_16(0xffff);
 788
 789         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 790
 791         HWRM_CHECK_RESULT();
 792
 793         if (BNXT_VF(bp)) {
 794                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 795                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 796                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 797                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 798                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 799                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 800                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 801                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 802         }
 803         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 804         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 805         if (bp->vf_resv_strategy >
 806             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 807                 bp->vf_resv_strategy =
 808                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 809
 810         HWRM_UNLOCK();
 811         return rc;
 812 }
 813
 814 int bnxt_hwrm_ver_get(struct bnxt *bp)
 815 {
 816         int rc = 0;
 817         struct hwrm_ver_get_input req = {.req_type = 0 };
 818         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 819         uint32_t fw_version;
 820         uint16_t max_resp_len;
 821         char type[RTE_MEMZONE_NAMESIZE];
 822         uint32_t dev_caps_cfg;
 823
 824         bp->max_req_len = HWRM_MAX_REQ_LEN;
 825         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 826
 827         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 828         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 829         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 830
 831         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 832
 833         HWRM_CHECK_RESULT();
 834
 835         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 836                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 837                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 838                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 839         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 840                      (resp->hwrm_fw_min_8b << 16) |
 841                      (resp->hwrm_fw_bld_8b << 8) |
 842                      resp->hwrm_fw_rsvd_8b;
 843         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 844                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 845
 846         fw_version = resp->hwrm_intf_maj_8b << 16;
 847         fw_version |= resp->hwrm_intf_min_8b << 8;
 848         fw_version |= resp->hwrm_intf_upd_8b;
 849         bp->hwrm_spec_code = fw_version;
 850
 851         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 852                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 853                 rc = -EINVAL;
 854                 goto error;
 855         }
 856
 857         if (bp->max_req_len > resp->max_req_win_len) {
 858                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 859                 rc = -EINVAL;
 860         }
 861         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 862         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 863         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 864                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 865
 866         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 867         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 868
 869         if (bp->max_resp_len != max_resp_len) {
 870                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 871                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 872                         bp->pdev->addr.devid, bp->pdev->addr.function);
 873
 874                 rte_free(bp->hwrm_cmd_resp_addr);
 875
 876                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 877                 if (bp->hwrm_cmd_resp_addr == NULL) {
 878                         rc = -ENOMEM;
 879                         goto error;
 880                 }
 881                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 882                 bp->hwrm_cmd_resp_dma_addr =
 883                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 884                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 885                         PMD_DRV_LOG(ERR,
 886                         "Unable to map response buffer to physical memory.\n");
 887                         rc = -ENOMEM;
 888                         goto error;
 889                 }
 890                 bp->max_resp_len = max_resp_len;
 891         }
 892
 893         if ((dev_caps_cfg &
 894                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 895             (dev_caps_cfg &
 896              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 897                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 898                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 899         }
 900
 901         if (((dev_caps_cfg &
 902               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 903              (dev_caps_cfg &
 904               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 905             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 906                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 907                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 908                         bp->pdev->addr.devid, bp->pdev->addr.function);
 909
 910                 rte_free(bp->hwrm_short_cmd_req_addr);
 911
 912                 bp->hwrm_short_cmd_req_addr =
 913                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 914                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 915                         rc = -ENOMEM;
 916                         goto error;
 917                 }
 918                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 919                 bp->hwrm_short_cmd_req_dma_addr =
 920                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 921                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 922                         rte_free(bp->hwrm_short_cmd_req_addr);
 923                         PMD_DRV_LOG(ERR,
 924                                 "Unable to map buffer to physical memory.\n");
 925                         rc = -ENOMEM;
 926                         goto error;
 927                 }
 928         }
 929         if (dev_caps_cfg &
 930             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 931                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 932                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 933         }
 934         if (dev_caps_cfg &
 935             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 936                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 937
 938 error:
 939         HWRM_UNLOCK();
 940         return rc;
 941 }
 942
 943 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 944 {
 945         int rc;
 946         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 947         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 948
 949         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 950                 return 0;
 951
 952         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 953         req.flags = flags;
 954
 955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 956
 957         HWRM_CHECK_RESULT();
 958         HWRM_UNLOCK();
 959
 960         bp->flags &= ~BNXT_FLAG_REGISTERED;
 961
 962         return rc;
 963 }
 964
 965 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 966 {
 967         int rc = 0;
 968         struct hwrm_port_phy_cfg_input req = {0};
 969         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 970         uint32_t enables = 0;
 971
 972         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 973
 974         if (conf->link_up) {
 975                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 976                 if (bp->link_info.auto_mode && conf->link_speed) {
 977                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 978                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 979                 }
 980
 981                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 982                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 983                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 984                 /*
 985                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 986                  * any auto mode, even "none".
 987                  */
 988                 if (!conf->link_speed) {
 989                         /* No speeds specified. Enable AutoNeg - all speeds */
 990                         req.auto_mode =
 991                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 992                 }
 993                 /* AutoNeg - Advertise speeds specified. */
 994                 if (conf->auto_link_speed_mask &&
 995                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 996                         req.auto_mode =
 997                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 998                         req.auto_link_speed_mask =
 999                                 conf->auto_link_speed_mask;
1000                         enables |=
1001                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1002                 }
1003
1004                 req.auto_duplex = conf->duplex;
1005                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1006                 req.auto_pause = conf->auto_pause;
1007                 req.force_pause = conf->force_pause;
1008                 /* Set force_pause if there is no auto or if there is a force */
1009                 if (req.auto_pause && !req.force_pause)
1010                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1011                 else
1012                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1013
1014                 req.enables = rte_cpu_to_le_32(enables);
1015         } else {
1016                 req.flags =
1017                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1018                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1019         }
1020
1021         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023         HWRM_CHECK_RESULT();
1024         HWRM_UNLOCK();
1025
1026         return rc;
1027 }
1028
1029 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1030                                    struct bnxt_link_info *link_info)
1031 {
1032         int rc = 0;
1033         struct hwrm_port_phy_qcfg_input req = {0};
1034         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1035
1036         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1037
1038         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1039
1040         HWRM_CHECK_RESULT();
1041
1042         link_info->phy_link_status = resp->link;
1043         link_info->link_up =
1044                 (link_info->phy_link_status ==
1045                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1046         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1047         link_info->duplex = resp->duplex_cfg;
1048         link_info->pause = resp->pause;
1049         link_info->auto_pause = resp->auto_pause;
1050         link_info->force_pause = resp->force_pause;
1051         link_info->auto_mode = resp->auto_mode;
1052         link_info->phy_type = resp->phy_type;
1053         link_info->media_type = resp->media_type;
1054
1055         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1056         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1057         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1058         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1059         link_info->phy_ver[0] = resp->phy_maj;
1060         link_info->phy_ver[1] = resp->phy_min;
1061         link_info->phy_ver[2] = resp->phy_bld;
1062
1063         HWRM_UNLOCK();
1064
1065         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1066         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1067         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1068         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1069         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1070                     link_info->auto_link_speed_mask);
1071         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1072                     link_info->force_link_speed);
1073
1074         return rc;
1075 }
1076
1077 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1078 {
1079         int rc = 0;
1080         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1081         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1082         int i;
1083
1084         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1085
1086         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1087         /* HWRM Version >= 1.9.1 */
1088         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1089                 req.drv_qmap_cap =
1090                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1091         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1092
1093         HWRM_CHECK_RESULT();
1094
1095 #define GET_QUEUE_INFO(x) \
1096         bp->cos_queue[x].id = resp->queue_id##x; \
1097         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1098
1099         GET_QUEUE_INFO(0);
1100         GET_QUEUE_INFO(1);
1101         GET_QUEUE_INFO(2);
1102         GET_QUEUE_INFO(3);
1103         GET_QUEUE_INFO(4);
1104         GET_QUEUE_INFO(5);
1105         GET_QUEUE_INFO(6);
1106         GET_QUEUE_INFO(7);
1107
1108         HWRM_UNLOCK();
1109
1110         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1111                 bp->tx_cosq_id = bp->cos_queue[0].id;
1112         } else {
1113                 /* iterate and find the COSq profile to use for Tx */
1114                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1115                         if (bp->cos_queue[i].profile ==
1116                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1117                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1118                                 break;
1119                         }
1120                 }
1121         }
1122
1123         bp->max_tc = resp->max_configurable_queues;
1124         bp->max_lltc = resp->max_configurable_lossless_queues;
1125         if (bp->max_tc > BNXT_MAX_QUEUE)
1126                 bp->max_tc = BNXT_MAX_QUEUE;
1127         bp->max_q = bp->max_tc;
1128
1129         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1130
1131         return rc;
1132 }
1133
1134 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1135                          struct bnxt_ring *ring,
1136                          uint32_t ring_type, uint32_t map_index,
1137                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1138 {
1139         int rc = 0;
1140         uint32_t enables = 0;
1141         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1142         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1143         struct rte_mempool *mb_pool;
1144         uint16_t rx_buf_size;
1145
1146         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1147
1148         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1149         req.fbo = rte_cpu_to_le_32(0);
1150         /* Association of ring index with doorbell index */
1151         req.logical_id = rte_cpu_to_le_16(map_index);
1152         req.length = rte_cpu_to_le_32(ring->ring_size);
1153
1154         switch (ring_type) {
1155         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1156                 req.ring_type = ring_type;
1157                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1158                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1159                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1160                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1161                         enables |=
1162                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1163                 break;
1164         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1165                 req.ring_type = ring_type;
1166                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1167                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1168                 if (BNXT_CHIP_THOR(bp)) {
1169                         mb_pool = bp->rx_queues[0]->mb_pool;
1170                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1171                                       RTE_PKTMBUF_HEADROOM;
1172                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1173                         enables |=
1174                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1175                 }
1176                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1177                         enables |=
1178                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1179                 break;
1180         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1181                 req.ring_type = ring_type;
1182                 if (BNXT_HAS_NQ(bp)) {
1183                         /* Association of cp ring with nq */
1184                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1185                         enables |=
1186                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1187                 }
1188                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1189                 break;
1190         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1191                 req.ring_type = ring_type;
1192                 req.page_size = BNXT_PAGE_SHFT;
1193                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1194                 break;
1195         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1196                 req.ring_type = ring_type;
1197                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1198
1199                 mb_pool = bp->rx_queues[0]->mb_pool;
1200                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1201                               RTE_PKTMBUF_HEADROOM;
1202                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1203
1204                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1205                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1206                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1207                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1208                 break;
1209         default:
1210                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1211                         ring_type);
1212                 HWRM_UNLOCK();
1213                 return -1;
1214         }
1215         req.enables = rte_cpu_to_le_32(enables);
1216
1217         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1218
1219         if (rc || resp->error_code) {
1220                 if (rc == 0 && resp->error_code)
1221                         rc = rte_le_to_cpu_16(resp->error_code);
1222                 switch (ring_type) {
1223                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1224                         PMD_DRV_LOG(ERR,
1225                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1226                         HWRM_UNLOCK();
1227                         return rc;
1228                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1229                         PMD_DRV_LOG(ERR,
1230                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1231                         HWRM_UNLOCK();
1232                         return rc;
1233                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1234                         PMD_DRV_LOG(ERR,
1235                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1236                                     rc);
1237                         HWRM_UNLOCK();
1238                         return rc;
1239                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1240                         PMD_DRV_LOG(ERR,
1241                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1242                         HWRM_UNLOCK();
1243                         return rc;
1244                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1245                         PMD_DRV_LOG(ERR,
1246                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1247                         HWRM_UNLOCK();
1248                         return rc;
1249                 default:
1250                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1251                         HWRM_UNLOCK();
1252                         return rc;
1253                 }
1254         }
1255
1256         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1257         HWRM_UNLOCK();
1258         return rc;
1259 }
1260
1261 int bnxt_hwrm_ring_free(struct bnxt *bp,
1262                         struct bnxt_ring *ring, uint32_t ring_type)
1263 {
1264         int rc;
1265         struct hwrm_ring_free_input req = {.req_type = 0 };
1266         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1267
1268         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1269
1270         req.ring_type = ring_type;
1271         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1272
1273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1274
1275         if (rc || resp->error_code) {
1276                 if (rc == 0 && resp->error_code)
1277                         rc = rte_le_to_cpu_16(resp->error_code);
1278                 HWRM_UNLOCK();
1279
1280                 switch (ring_type) {
1281                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1282                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1283                                 rc);
1284                         return rc;
1285                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1286                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1287                                 rc);
1288                         return rc;
1289                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1290                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1291                                 rc);
1292                         return rc;
1293                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1294                         PMD_DRV_LOG(ERR,
1295                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1296                         return rc;
1297                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1298                         PMD_DRV_LOG(ERR,
1299                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1300                         return rc;
1301                 default:
1302                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1303                         return rc;
1304                 }
1305         }
1306         HWRM_UNLOCK();
1307         return 0;
1308 }
1309
1310 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1311 {
1312         int rc = 0;
1313         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1314         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1315
1316         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1317
1318         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1319         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1320         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1321         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1322
1323         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1324
1325         HWRM_CHECK_RESULT();
1326
1327         bp->grp_info[idx].fw_grp_id =
1328             rte_le_to_cpu_16(resp->ring_group_id);
1329
1330         HWRM_UNLOCK();
1331
1332         return rc;
1333 }
1334
1335 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1336 {
1337         int rc;
1338         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1339         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1340
1341         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1342
1343         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1344
1345         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1346
1347         HWRM_CHECK_RESULT();
1348         HWRM_UNLOCK();
1349
1350         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1351         return rc;
1352 }
1353
1354 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1355 {
1356         int rc = 0;
1357         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1358         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1359
1360         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1361                 return rc;
1362
1363         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1364
1365         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1366
1367         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1368
1369         HWRM_CHECK_RESULT();
1370         HWRM_UNLOCK();
1371
1372         return rc;
1373 }
1374
1375 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1376                                 unsigned int idx __rte_unused)
1377 {
1378         int rc;
1379         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1380         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1381
1382         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1383
1384         req.update_period_ms = rte_cpu_to_le_32(0);
1385
1386         req.stats_dma_addr =
1387             rte_cpu_to_le_64(cpr->hw_stats_map);
1388
1389         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1390
1391         HWRM_CHECK_RESULT();
1392
1393         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1394
1395         HWRM_UNLOCK();
1396
1397         return rc;
1398 }
1399
1400 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1401                                 unsigned int idx __rte_unused)
1402 {
1403         int rc;
1404         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1405         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1406
1407         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1408
1409         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1410
1411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1412
1413         HWRM_CHECK_RESULT();
1414         HWRM_UNLOCK();
1415
1416         return rc;
1417 }
1418
1419 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1420 {
1421         int rc = 0, i, j;
1422         struct hwrm_vnic_alloc_input req = { 0 };
1423         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1424
1425         if (!BNXT_HAS_RING_GRPS(bp))
1426                 goto skip_ring_grps;
1427
1428         /* map ring groups to this vnic */
1429         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1430                 vnic->start_grp_id, vnic->end_grp_id);
1431         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1432                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1433
1434         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1435         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1436         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1437         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1438
1439 skip_ring_grps:
1440         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1441                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1442         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1443
1444         if (vnic->func_default)
1445                 req.flags =
1446                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1448
1449         HWRM_CHECK_RESULT();
1450
1451         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1452         HWRM_UNLOCK();
1453         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1454         return rc;
1455 }
1456
1457 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1458                                         struct bnxt_vnic_info *vnic,
1459                                         struct bnxt_plcmodes_cfg *pmode)
1460 {
1461         int rc = 0;
1462         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1463         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1464
1465         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1466
1467         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1468
1469         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1470
1471         HWRM_CHECK_RESULT();
1472
1473         pmode->flags = rte_le_to_cpu_32(resp->flags);
1474         /* dflt_vnic bit doesn't exist in the _cfg command */
1475         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1476         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1477         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1478         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1479
1480         HWRM_UNLOCK();
1481
1482         return rc;
1483 }
1484
1485 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1486                                        struct bnxt_vnic_info *vnic,
1487                                        struct bnxt_plcmodes_cfg *pmode)
1488 {
1489         int rc = 0;
1490         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1491         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1492
1493         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1494
1495         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1496         req.flags = rte_cpu_to_le_32(pmode->flags);
1497         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1498         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1499         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1500         req.enables = rte_cpu_to_le_32(
1501             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1502             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1503             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1504         );
1505
1506         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1507
1508         HWRM_CHECK_RESULT();
1509         HWRM_UNLOCK();
1510
1511         return rc;
1512 }
1513
1514 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1515 {
1516         int rc = 0;
1517         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1518         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1519         uint32_t ctx_enable_flag = 0;
1520         struct bnxt_plcmodes_cfg pmodes;
1521         uint32_t enables = 0;
1522
1523         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1524                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1525                 return rc;
1526         }
1527
1528         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1529         if (rc)
1530                 return rc;
1531
1532         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1533
1534         if (BNXT_CHIP_THOR(bp)) {
1535                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1536                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1537                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1538
1539                 req.default_rx_ring_id =
1540                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1541                 req.default_cmpl_ring_id =
1542                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1543                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1544                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1545                 goto config_mru;
1546         }
1547
1548         /* Only RSS support for now TBD: COS & LB */
1549         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1550         if (vnic->lb_rule != 0xffff)
1551                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1552         if (vnic->cos_rule != 0xffff)
1553                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1554         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1555                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1556                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1557         }
1558         enables |= ctx_enable_flag;
1559         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1560         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1561         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1562         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1563
1564 config_mru:
1565         req.enables = rte_cpu_to_le_32(enables);
1566         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1567         req.mru = rte_cpu_to_le_16(vnic->mru);
1568         /* Configure default VNIC only once. */
1569         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1570                 req.flags |=
1571                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1572                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1573         }
1574         if (vnic->vlan_strip)
1575                 req.flags |=
1576                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1577         if (vnic->bd_stall)
1578                 req.flags |=
1579                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1580         if (vnic->roce_dual)
1581                 req.flags |= rte_cpu_to_le_32(
1582                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1583         if (vnic->roce_only)
1584                 req.flags |= rte_cpu_to_le_32(
1585                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1586         if (vnic->rss_dflt_cr)
1587                 req.flags |= rte_cpu_to_le_32(
1588                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1589
1590         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1591
1592         HWRM_CHECK_RESULT();
1593         HWRM_UNLOCK();
1594
1595         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1596
1597         return rc;
1598 }
1599
1600 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1601                 int16_t fw_vf_id)
1602 {
1603         int rc = 0;
1604         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1605         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1606
1607         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1608                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1609                 return rc;
1610         }
1611         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1612
1613         req.enables =
1614                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1615         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1616         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1617
1618         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1619
1620         HWRM_CHECK_RESULT();
1621
1622         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1623         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1624         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1625         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1626         vnic->mru = rte_le_to_cpu_16(resp->mru);
1627         vnic->func_default = rte_le_to_cpu_32(
1628                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1629         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1630                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1631         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1632                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1633         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1634                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1635         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1636                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1637         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1638                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1639
1640         HWRM_UNLOCK();
1641
1642         return rc;
1643 }
1644
1645 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1646                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1647 {
1648         int rc = 0;
1649         uint16_t ctx_id;
1650         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1651         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1652                                                 bp->hwrm_cmd_resp_addr;
1653
1654         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1655
1656         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1657         HWRM_CHECK_RESULT();
1658
1659         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1660         if (!BNXT_HAS_RING_GRPS(bp))
1661                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1662         else if (ctx_idx == 0)
1663                 vnic->rss_rule = ctx_id;
1664
1665         HWRM_UNLOCK();
1666
1667         return rc;
1668 }
1669
1670 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1671                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1672 {
1673         int rc = 0;
1674         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1675         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1676                                                 bp->hwrm_cmd_resp_addr;
1677
1678         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1679                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1680                 return rc;
1681         }
1682         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1683
1684         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1685
1686         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1687
1688         HWRM_CHECK_RESULT();
1689         HWRM_UNLOCK();
1690
1691         return rc;
1692 }
1693
1694 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1695 {
1696         int rc = 0;
1697         struct hwrm_vnic_free_input req = {.req_type = 0 };
1698         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1699
1700         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1701                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1702                 return rc;
1703         }
1704
1705         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1706
1707         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1708
1709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1710
1711         HWRM_CHECK_RESULT();
1712         HWRM_UNLOCK();
1713
1714         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1715         /* Configure default VNIC again if necessary. */
1716         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1717                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1718
1719         return rc;
1720 }
1721
1722 static int
1723 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1724 {
1725         int i;
1726         int rc = 0;
1727         int nr_ctxs = bp->max_ring_grps;
1728         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1729         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1730
1731         if (!(vnic->rss_table && vnic->hash_type))
1732                 return 0;
1733
1734         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1735
1736         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1737         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1738         req.hash_mode_flags = vnic->hash_mode;
1739
1740         req.hash_key_tbl_addr =
1741             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1742
1743         for (i = 0; i < nr_ctxs; i++) {
1744                 req.ring_grp_tbl_addr =
1745                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1746                                          i * HW_HASH_INDEX_SIZE);
1747                 req.ring_table_pair_index = i;
1748                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1749
1750                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1751                                             BNXT_USE_CHIMP_MB);
1752
1753                 HWRM_CHECK_RESULT();
1754                 if (rc)
1755                         break;
1756         }
1757
1758         HWRM_UNLOCK();
1759
1760         return rc;
1761 }
1762
1763 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1764                            struct bnxt_vnic_info *vnic)
1765 {
1766         int rc = 0;
1767         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1768         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1769
1770         if (BNXT_CHIP_THOR(bp))
1771                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1772
1773         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1774
1775         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1776         req.hash_mode_flags = vnic->hash_mode;
1777
1778         req.ring_grp_tbl_addr =
1779             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1780         req.hash_key_tbl_addr =
1781             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1782         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1783         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1784
1785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786
1787         HWRM_CHECK_RESULT();
1788         HWRM_UNLOCK();
1789
1790         return rc;
1791 }
1792
1793 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1794                         struct bnxt_vnic_info *vnic)
1795 {
1796         int rc = 0;
1797         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1798         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1799         uint16_t size;
1800
1801         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1802                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1803                 return rc;
1804         }
1805
1806         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1807
1808         req.flags = rte_cpu_to_le_32(
1809                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1810
1811         req.enables = rte_cpu_to_le_32(
1812                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1813
1814         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1815         size -= RTE_PKTMBUF_HEADROOM;
1816
1817         req.jumbo_thresh = rte_cpu_to_le_16(size);
1818         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1819
1820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1821
1822         HWRM_CHECK_RESULT();
1823         HWRM_UNLOCK();
1824
1825         return rc;
1826 }
1827
1828 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1829                         struct bnxt_vnic_info *vnic, bool enable)
1830 {
1831         int rc = 0;
1832         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1833         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1834
1835         if (BNXT_CHIP_THOR(bp))
1836                 return 0;
1837
1838         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1839
1840         if (enable) {
1841                 req.enables = rte_cpu_to_le_32(
1842                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1843                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1844                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1845                 req.flags = rte_cpu_to_le_32(
1846                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1847                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1848                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1849                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1850                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1851                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1852                 req.max_agg_segs = rte_cpu_to_le_16(5);
1853                 req.max_aggs =
1854                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1855                 req.min_agg_len = rte_cpu_to_le_32(512);
1856         }
1857         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1858
1859         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1860
1861         HWRM_CHECK_RESULT();
1862         HWRM_UNLOCK();
1863
1864         return rc;
1865 }
1866
1867 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1868 {
1869         struct hwrm_func_cfg_input req = {0};
1870         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1871         int rc;
1872
1873         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1874         req.enables = rte_cpu_to_le_32(
1875                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1876         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1877         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1878
1879         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1880
1881         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1882         HWRM_CHECK_RESULT();
1883         HWRM_UNLOCK();
1884
1885         bp->pf.vf_info[vf].random_mac = false;
1886
1887         return rc;
1888 }
1889
1890 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1891                                   uint64_t *dropped)
1892 {
1893         int rc = 0;
1894         struct hwrm_func_qstats_input req = {.req_type = 0};
1895         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1896
1897         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1898
1899         req.fid = rte_cpu_to_le_16(fid);
1900
1901         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1902
1903         HWRM_CHECK_RESULT();
1904
1905         if (dropped)
1906                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1907
1908         HWRM_UNLOCK();
1909
1910         return rc;
1911 }
1912
1913 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1914                           struct rte_eth_stats *stats)
1915 {
1916         int rc = 0;
1917         struct hwrm_func_qstats_input req = {.req_type = 0};
1918         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1919
1920         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1921
1922         req.fid = rte_cpu_to_le_16(fid);
1923
1924         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1925
1926         HWRM_CHECK_RESULT();
1927
1928         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1929         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1930         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1931         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1932         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1933         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1934
1935         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1936         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1937         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1938         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1939         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1940         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1941
1942         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1943         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1944         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1945
1946         HWRM_UNLOCK();
1947
1948         return rc;
1949 }
1950
1951 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1952 {
1953         int rc = 0;
1954         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1955         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1956
1957         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1958
1959         req.fid = rte_cpu_to_le_16(fid);
1960
1961         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1962
1963         HWRM_CHECK_RESULT();
1964         HWRM_UNLOCK();
1965
1966         return rc;
1967 }
1968
1969 /*
1970  * HWRM utility functions
1971  */
1972
1973 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1974 {
1975         unsigned int i;
1976         int rc = 0;
1977
1978         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1979                 struct bnxt_tx_queue *txq;
1980                 struct bnxt_rx_queue *rxq;
1981                 struct bnxt_cp_ring_info *cpr;
1982
1983                 if (i >= bp->rx_cp_nr_rings) {
1984                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1985                         cpr = txq->cp_ring;
1986                 } else {
1987                         rxq = bp->rx_queues[i];
1988                         cpr = rxq->cp_ring;
1989                 }
1990
1991                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1992                 if (rc)
1993                         return rc;
1994         }
1995         return 0;
1996 }
1997
1998 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1999 {
2000         int rc;
2001         unsigned int i;
2002         struct bnxt_cp_ring_info *cpr;
2003
2004         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2005
2006                 if (i >= bp->rx_cp_nr_rings) {
2007                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2008                 } else {
2009                         cpr = bp->rx_queues[i]->cp_ring;
2010                         if (BNXT_HAS_RING_GRPS(bp))
2011                                 bp->grp_info[i].fw_stats_ctx = -1;
2012                 }
2013                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2014                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2015                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2016                         if (rc)
2017                                 return rc;
2018                 }
2019         }
2020         return 0;
2021 }
2022
2023 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2024 {
2025         unsigned int i;
2026         int rc = 0;
2027
2028         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2029                 struct bnxt_tx_queue *txq;
2030                 struct bnxt_rx_queue *rxq;
2031                 struct bnxt_cp_ring_info *cpr;
2032
2033                 if (i >= bp->rx_cp_nr_rings) {
2034                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2035                         cpr = txq->cp_ring;
2036                 } else {
2037                         rxq = bp->rx_queues[i];
2038                         cpr = rxq->cp_ring;
2039                 }
2040
2041                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2042
2043                 if (rc)
2044                         return rc;
2045         }
2046         return rc;
2047 }
2048
2049 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2050 {
2051         uint16_t idx;
2052         uint32_t rc = 0;
2053
2054         if (!BNXT_HAS_RING_GRPS(bp))
2055                 return 0;
2056
2057         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2058
2059                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2060                         continue;
2061
2062                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2063
2064                 if (rc)
2065                         return rc;
2066         }
2067         return rc;
2068 }
2069
2070 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2071 {
2072         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2073
2074         bnxt_hwrm_ring_free(bp, cp_ring,
2075                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2076         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2077         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2078                                      sizeof(*cpr->cp_desc_ring));
2079         cpr->cp_raw_cons = 0;
2080 }
2081
2082 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2083 {
2084         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2085
2086         bnxt_hwrm_ring_free(bp, cp_ring,
2087                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2088         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2089         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2090                         sizeof(*cpr->cp_desc_ring));
2091         cpr->cp_raw_cons = 0;
2092         cpr->valid = 0;
2093 }
2094
2095 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2096 {
2097         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2098         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2099         struct bnxt_ring *ring = rxr->rx_ring_struct;
2100         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2101
2102         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2103                 bnxt_hwrm_ring_free(bp, ring,
2104                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2105                 ring->fw_ring_id = INVALID_HW_RING_ID;
2106                 if (BNXT_HAS_RING_GRPS(bp))
2107                         bp->grp_info[queue_index].rx_fw_ring_id =
2108                                                         INVALID_HW_RING_ID;
2109                 memset(rxr->rx_desc_ring, 0,
2110                        rxr->rx_ring_struct->ring_size *
2111                        sizeof(*rxr->rx_desc_ring));
2112                 memset(rxr->rx_buf_ring, 0,
2113                        rxr->rx_ring_struct->ring_size *
2114                        sizeof(*rxr->rx_buf_ring));
2115                 rxr->rx_prod = 0;
2116         }
2117         ring = rxr->ag_ring_struct;
2118         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2119                 bnxt_hwrm_ring_free(bp, ring,
2120                                     BNXT_CHIP_THOR(bp) ?
2121                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2122                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2123                 ring->fw_ring_id = INVALID_HW_RING_ID;
2124                 memset(rxr->ag_buf_ring, 0,
2125                        rxr->ag_ring_struct->ring_size *
2126                        sizeof(*rxr->ag_buf_ring));
2127                 rxr->ag_prod = 0;
2128                 if (BNXT_HAS_RING_GRPS(bp))
2129                         bp->grp_info[queue_index].ag_fw_ring_id =
2130                                                         INVALID_HW_RING_ID;
2131         }
2132         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2133                 bnxt_free_cp_ring(bp, cpr);
2134                 if (rxq->nq_ring)
2135                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2136         }
2137
2138         if (BNXT_HAS_RING_GRPS(bp))
2139                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2140 }
2141
2142 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2143 {
2144         unsigned int i;
2145
2146         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2147                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2148                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2149                 struct bnxt_ring *ring = txr->tx_ring_struct;
2150                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2151
2152                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2153                         bnxt_hwrm_ring_free(bp, ring,
2154                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2155                         ring->fw_ring_id = INVALID_HW_RING_ID;
2156                         memset(txr->tx_desc_ring, 0,
2157                                         txr->tx_ring_struct->ring_size *
2158                                         sizeof(*txr->tx_desc_ring));
2159                         memset(txr->tx_buf_ring, 0,
2160                                         txr->tx_ring_struct->ring_size *
2161                                         sizeof(*txr->tx_buf_ring));
2162                         txr->tx_prod = 0;
2163                         txr->tx_cons = 0;
2164                 }
2165                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2166                         bnxt_free_cp_ring(bp, cpr);
2167                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2168                         if (txq->nq_ring)
2169                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2170                 }
2171         }
2172
2173         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2174                 bnxt_free_hwrm_rx_ring(bp, i);
2175
2176         return 0;
2177 }
2178
2179 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2180 {
2181         uint16_t i;
2182         uint32_t rc = 0;
2183
2184         if (!BNXT_HAS_RING_GRPS(bp))
2185                 return 0;
2186
2187         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2188                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2189                 if (rc)
2190                         return rc;
2191         }
2192         return rc;
2193 }
2194
2195 void bnxt_free_hwrm_resources(struct bnxt *bp)
2196 {
2197         /* Release memzone */
2198         rte_free(bp->hwrm_cmd_resp_addr);
2199         rte_free(bp->hwrm_short_cmd_req_addr);
2200         bp->hwrm_cmd_resp_addr = NULL;
2201         bp->hwrm_short_cmd_req_addr = NULL;
2202         bp->hwrm_cmd_resp_dma_addr = 0;
2203         bp->hwrm_short_cmd_req_dma_addr = 0;
2204 }
2205
2206 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2207 {
2208         struct rte_pci_device *pdev = bp->pdev;
2209         char type[RTE_MEMZONE_NAMESIZE];
2210
2211         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2212                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2213         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2214         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2215         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2216         if (bp->hwrm_cmd_resp_addr == NULL)
2217                 return -ENOMEM;
2218         bp->hwrm_cmd_resp_dma_addr =
2219                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2220         if (bp->hwrm_cmd_resp_dma_addr == 0) {
2221                 PMD_DRV_LOG(ERR,
2222                         "unable to map response address to physical memory\n");
2223                 return -ENOMEM;
2224         }
2225         rte_spinlock_init(&bp->hwrm_lock);
2226
2227         return 0;
2228 }
2229
2230 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2231 {
2232         struct bnxt_filter_info *filter;
2233         int rc = 0;
2234
2235         STAILQ_FOREACH(filter, &vnic->filter, next) {
2236                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2237                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2238                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2239                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2240                 else
2241                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2242                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2243                 //if (rc)
2244                         //break;
2245         }
2246         return rc;
2247 }
2248
2249 static int
2250 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2251 {
2252         struct bnxt_filter_info *filter;
2253         struct rte_flow *flow;
2254         int rc = 0;
2255
2256         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2257                 filter = flow->filter;
2258                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2259                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2260                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2261                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2262                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2263                 else
2264                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2265
2266                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2267                 rte_free(flow);
2268                 //if (rc)
2269                         //break;
2270         }
2271         return rc;
2272 }
2273
2274 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2275 {
2276         struct bnxt_filter_info *filter;
2277         int rc = 0;
2278
2279         STAILQ_FOREACH(filter, &vnic->filter, next) {
2280                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2281                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2282                                                      filter);
2283                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2284                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2285                                                          filter);
2286                 else
2287                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2288                                                      filter);
2289                 if (rc)
2290                         break;
2291         }
2292         return rc;
2293 }
2294
2295 void bnxt_free_tunnel_ports(struct bnxt *bp)
2296 {
2297         if (bp->vxlan_port_cnt)
2298                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2299                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2300         bp->vxlan_port = 0;
2301         if (bp->geneve_port_cnt)
2302                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2303                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2304         bp->geneve_port = 0;
2305 }
2306
2307 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2308 {
2309         int i, j;
2310
2311         if (bp->vnic_info == NULL)
2312                 return;
2313
2314         /*
2315          * Cleanup VNICs in reverse order, to make sure the L2 filter
2316          * from vnic0 is last to be cleaned up.
2317          */
2318         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2319                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2320
2321                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2322
2323                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2324
2325                 if (BNXT_CHIP_THOR(bp)) {
2326                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2327                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2328                                                         vnic->fw_grp_ids[j]);
2329                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2330                         }
2331                         vnic->num_lb_ctxts = 0;
2332                 } else {
2333                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2334                         vnic->rss_rule = INVALID_HW_RING_ID;
2335                 }
2336
2337                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2338
2339                 bnxt_hwrm_vnic_free(bp, vnic);
2340
2341                 rte_free(vnic->fw_grp_ids);
2342         }
2343         /* Ring resources */
2344         bnxt_free_all_hwrm_rings(bp);
2345         bnxt_free_all_hwrm_ring_grps(bp);
2346         bnxt_free_all_hwrm_stat_ctxs(bp);
2347         bnxt_free_tunnel_ports(bp);
2348 }
2349
2350 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2351 {
2352         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2353
2354         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2355                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2356
2357         switch (conf_link_speed) {
2358         case ETH_LINK_SPEED_10M_HD:
2359         case ETH_LINK_SPEED_100M_HD:
2360                 /* FALLTHROUGH */
2361                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2362         }
2363         return hw_link_duplex;
2364 }
2365
2366 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2367 {
2368         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2369 }
2370
2371 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2372 {
2373         uint16_t eth_link_speed = 0;
2374
2375         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2376                 return ETH_LINK_SPEED_AUTONEG;
2377
2378         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2379         case ETH_LINK_SPEED_100M:
2380         case ETH_LINK_SPEED_100M_HD:
2381                 /* FALLTHROUGH */
2382                 eth_link_speed =
2383                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2384                 break;
2385         case ETH_LINK_SPEED_1G:
2386                 eth_link_speed =
2387                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2388                 break;
2389         case ETH_LINK_SPEED_2_5G:
2390                 eth_link_speed =
2391                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2392                 break;
2393         case ETH_LINK_SPEED_10G:
2394                 eth_link_speed =
2395                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2396                 break;
2397         case ETH_LINK_SPEED_20G:
2398                 eth_link_speed =
2399                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2400                 break;
2401         case ETH_LINK_SPEED_25G:
2402                 eth_link_speed =
2403                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2404                 break;
2405         case ETH_LINK_SPEED_40G:
2406                 eth_link_speed =
2407                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2408                 break;
2409         case ETH_LINK_SPEED_50G:
2410                 eth_link_speed =
2411                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2412                 break;
2413         case ETH_LINK_SPEED_100G:
2414                 eth_link_speed =
2415                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2416                 break;
2417         default:
2418                 PMD_DRV_LOG(ERR,
2419                         "Unsupported link speed %d; default to AUTO\n",
2420                         conf_link_speed);
2421                 break;
2422         }
2423         return eth_link_speed;
2424 }
2425
2426 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2427                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2428                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2429                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2430
2431 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2432 {
2433         uint32_t one_speed;
2434
2435         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2436                 return 0;
2437
2438         if (link_speed & ETH_LINK_SPEED_FIXED) {
2439                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2440
2441                 if (one_speed & (one_speed - 1)) {
2442                         PMD_DRV_LOG(ERR,
2443                                 "Invalid advertised speeds (%u) for port %u\n",
2444                                 link_speed, port_id);
2445                         return -EINVAL;
2446                 }
2447                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2448                         PMD_DRV_LOG(ERR,
2449                                 "Unsupported advertised speed (%u) for port %u\n",
2450                                 link_speed, port_id);
2451                         return -EINVAL;
2452                 }
2453         } else {
2454                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2455                         PMD_DRV_LOG(ERR,
2456                                 "Unsupported advertised speeds (%u) for port %u\n",
2457                                 link_speed, port_id);
2458                         return -EINVAL;
2459                 }
2460         }
2461         return 0;
2462 }
2463
2464 static uint16_t
2465 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2466 {
2467         uint16_t ret = 0;
2468
2469         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2470                 if (bp->link_info.support_speeds)
2471                         return bp->link_info.support_speeds;
2472                 link_speed = BNXT_SUPPORTED_SPEEDS;
2473         }
2474
2475         if (link_speed & ETH_LINK_SPEED_100M)
2476                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2477         if (link_speed & ETH_LINK_SPEED_100M_HD)
2478                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2479         if (link_speed & ETH_LINK_SPEED_1G)
2480                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2481         if (link_speed & ETH_LINK_SPEED_2_5G)
2482                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2483         if (link_speed & ETH_LINK_SPEED_10G)
2484                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2485         if (link_speed & ETH_LINK_SPEED_20G)
2486                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2487         if (link_speed & ETH_LINK_SPEED_25G)
2488                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2489         if (link_speed & ETH_LINK_SPEED_40G)
2490                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2491         if (link_speed & ETH_LINK_SPEED_50G)
2492                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2493         if (link_speed & ETH_LINK_SPEED_100G)
2494                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2495         return ret;
2496 }
2497
2498 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2499 {
2500         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2501
2502         switch (hw_link_speed) {
2503         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2504                 eth_link_speed = ETH_SPEED_NUM_100M;
2505                 break;
2506         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2507                 eth_link_speed = ETH_SPEED_NUM_1G;
2508                 break;
2509         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2510                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2511                 break;
2512         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2513                 eth_link_speed = ETH_SPEED_NUM_10G;
2514                 break;
2515         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2516                 eth_link_speed = ETH_SPEED_NUM_20G;
2517                 break;
2518         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2519                 eth_link_speed = ETH_SPEED_NUM_25G;
2520                 break;
2521         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2522                 eth_link_speed = ETH_SPEED_NUM_40G;
2523                 break;
2524         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2525                 eth_link_speed = ETH_SPEED_NUM_50G;
2526                 break;
2527         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2528                 eth_link_speed = ETH_SPEED_NUM_100G;
2529                 break;
2530         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2531         default:
2532                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2533                         hw_link_speed);
2534                 break;
2535         }
2536         return eth_link_speed;
2537 }
2538
2539 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2540 {
2541         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2542
2543         switch (hw_link_duplex) {
2544         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2545         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2546                 /* FALLTHROUGH */
2547                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2548                 break;
2549         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2550                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2551                 break;
2552         default:
2553                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2554                         hw_link_duplex);
2555                 break;
2556         }
2557         return eth_link_duplex;
2558 }
2559
2560 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2561 {
2562         int rc = 0;
2563         struct bnxt_link_info *link_info = &bp->link_info;
2564
2565         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2566         if (rc) {
2567                 PMD_DRV_LOG(ERR,
2568                         "Get link config failed with rc %d\n", rc);
2569                 goto exit;
2570         }
2571         if (link_info->link_speed)
2572                 link->link_speed =
2573                         bnxt_parse_hw_link_speed(link_info->link_speed);
2574         else
2575                 link->link_speed = ETH_SPEED_NUM_NONE;
2576         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2577         link->link_status = link_info->link_up;
2578         link->link_autoneg = link_info->auto_mode ==
2579                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2580                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2581 exit:
2582         return rc;
2583 }
2584
2585 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2586 {
2587         int rc = 0;
2588         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2589         struct bnxt_link_info link_req;
2590         uint16_t speed, autoneg;
2591
2592         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2593                 return 0;
2594
2595         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2596                         bp->eth_dev->data->port_id);
2597         if (rc)
2598                 goto error;
2599
2600         memset(&link_req, 0, sizeof(link_req));
2601         link_req.link_up = link_up;
2602         if (!link_up)
2603                 goto port_phy_cfg;
2604
2605         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2606         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2607         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2608         /* Autoneg can be done only when the FW allows */
2609         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2610                                 bp->link_info.force_link_speed)) {
2611                 link_req.phy_flags |=
2612                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2613                 link_req.auto_link_speed_mask =
2614                         bnxt_parse_eth_link_speed_mask(bp,
2615                                                        dev_conf->link_speeds);
2616         } else {
2617                 if (bp->link_info.phy_type ==
2618                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2619                     bp->link_info.phy_type ==
2620                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2621                     bp->link_info.media_type ==
2622                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2623                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2624                         return -EINVAL;
2625                 }
2626
2627                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2628                 /* If user wants a particular speed try that first. */
2629                 if (speed)
2630                         link_req.link_speed = speed;
2631                 else if (bp->link_info.force_link_speed)
2632                         link_req.link_speed = bp->link_info.force_link_speed;
2633                 else
2634                         link_req.link_speed = bp->link_info.auto_link_speed;
2635         }
2636         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2637         link_req.auto_pause = bp->link_info.auto_pause;
2638         link_req.force_pause = bp->link_info.force_pause;
2639
2640 port_phy_cfg:
2641         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2642         if (rc) {
2643                 PMD_DRV_LOG(ERR,
2644                         "Set link config failed with rc %d\n", rc);
2645         }
2646
2647 error:
2648         return rc;
2649 }
2650
2651 /* JIRA 22088 */
2652 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2653 {
2654         struct hwrm_func_qcfg_input req = {0};
2655         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2656         uint16_t flags;
2657         int rc = 0;
2658
2659         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2660         req.fid = rte_cpu_to_le_16(0xffff);
2661
2662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2663
2664         HWRM_CHECK_RESULT();
2665
2666         /* Hard Coded.. 0xfff VLAN ID mask */
2667         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2668         flags = rte_le_to_cpu_16(resp->flags);
2669         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2670                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2671
2672         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2673                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2674                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2675         }
2676
2677         if (mtu)
2678                 *mtu = resp->mtu;
2679
2680         switch (resp->port_partition_type) {
2681         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2682         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2683         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2684                 /* FALLTHROUGH */
2685                 bp->port_partition_type = resp->port_partition_type;
2686                 break;
2687         default:
2688                 bp->port_partition_type = 0;
2689                 break;
2690         }
2691
2692         HWRM_UNLOCK();
2693
2694         return rc;
2695 }
2696
2697 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2698                                    struct hwrm_func_qcaps_output *qcaps)
2699 {
2700         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2701         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2702                sizeof(qcaps->mac_address));
2703         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2704         qcaps->max_rx_rings = fcfg->num_rx_rings;
2705         qcaps->max_tx_rings = fcfg->num_tx_rings;
2706         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2707         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2708         qcaps->max_vfs = 0;
2709         qcaps->first_vf_id = 0;
2710         qcaps->max_vnics = fcfg->num_vnics;
2711         qcaps->max_decap_records = 0;
2712         qcaps->max_encap_records = 0;
2713         qcaps->max_tx_wm_flows = 0;
2714         qcaps->max_tx_em_flows = 0;
2715         qcaps->max_rx_wm_flows = 0;
2716         qcaps->max_rx_em_flows = 0;
2717         qcaps->max_flow_id = 0;
2718         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2719         qcaps->max_sp_tx_rings = 0;
2720         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2721 }
2722
2723 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2724 {
2725         struct hwrm_func_cfg_input req = {0};
2726         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2727         uint32_t enables;
2728         int rc;
2729
2730         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2731                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2732                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2733                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2734                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2735                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2736                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2737                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2738                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2739
2740         if (BNXT_HAS_RING_GRPS(bp)) {
2741                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2742                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2743         } else if (BNXT_HAS_NQ(bp)) {
2744                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2745                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2746         }
2747
2748         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2749         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2750         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2751                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2752                                    BNXT_NUM_VLANS);
2753         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2754         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2755         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2756         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2757         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2758         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2759         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2760         req.fid = rte_cpu_to_le_16(0xffff);
2761         req.enables = rte_cpu_to_le_32(enables);
2762
2763         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2764
2765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2766
2767         HWRM_CHECK_RESULT();
2768         HWRM_UNLOCK();
2769
2770         return rc;
2771 }
2772
2773 static void populate_vf_func_cfg_req(struct bnxt *bp,
2774                                      struct hwrm_func_cfg_input *req,
2775                                      int num_vfs)
2776 {
2777         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2778                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2779                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2780                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2781                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2782                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2783                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2784                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2785                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2786                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2787
2788         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2789                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2790                                     BNXT_NUM_VLANS);
2791         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2792                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2793                                     BNXT_NUM_VLANS);
2794         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2795                                                 (num_vfs + 1));
2796         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2797         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2798                                                (num_vfs + 1));
2799         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2800         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2801         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2802         /* TODO: For now, do not support VMDq/RFS on VFs. */
2803         req->num_vnics = rte_cpu_to_le_16(1);
2804         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2805                                                  (num_vfs + 1));
2806 }
2807
2808 static void add_random_mac_if_needed(struct bnxt *bp,
2809                                      struct hwrm_func_cfg_input *cfg_req,
2810                                      int vf)
2811 {
2812         struct rte_ether_addr mac;
2813
2814         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2815                 return;
2816
2817         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2818                 cfg_req->enables |=
2819                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2820                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2821                 bp->pf.vf_info[vf].random_mac = true;
2822         } else {
2823                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2824                         RTE_ETHER_ADDR_LEN);
2825         }
2826 }
2827
2828 static void reserve_resources_from_vf(struct bnxt *bp,
2829                                       struct hwrm_func_cfg_input *cfg_req,
2830                                       int vf)
2831 {
2832         struct hwrm_func_qcaps_input req = {0};
2833         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2834         int rc;
2835
2836         /* Get the actual allocated values now */
2837         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2838         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2839         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2840
2841         if (rc) {
2842                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2843                 copy_func_cfg_to_qcaps(cfg_req, resp);
2844         } else if (resp->error_code) {
2845                 rc = rte_le_to_cpu_16(resp->error_code);
2846                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2847                 copy_func_cfg_to_qcaps(cfg_req, resp);
2848         }
2849
2850         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2851         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2852         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2853         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2854         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2855         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2856         /*
2857          * TODO: While not supporting VMDq with VFs, max_vnics is always
2858          * forced to 1 in this case
2859          */
2860         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2861         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2862
2863         HWRM_UNLOCK();
2864 }
2865
2866 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2867 {
2868         struct hwrm_func_qcfg_input req = {0};
2869         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2870         int rc;
2871
2872         /* Check for zero MAC address */
2873         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2874         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2875         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2876         if (rc) {
2877                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2878                 return -1;
2879         } else if (resp->error_code) {
2880                 rc = rte_le_to_cpu_16(resp->error_code);
2881                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2882                 return -1;
2883         }
2884         rc = rte_le_to_cpu_16(resp->vlan);
2885
2886         HWRM_UNLOCK();
2887
2888         return rc;
2889 }
2890
2891 static int update_pf_resource_max(struct bnxt *bp)
2892 {
2893         struct hwrm_func_qcfg_input req = {0};
2894         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2895         int rc;
2896
2897         /* And copy the allocated numbers into the pf struct */
2898         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2899         req.fid = rte_cpu_to_le_16(0xffff);
2900         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2901         HWRM_CHECK_RESULT();
2902
2903         /* Only TX ring value reflects actual allocation? TODO */
2904         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2905         bp->pf.evb_mode = resp->evb_mode;
2906
2907         HWRM_UNLOCK();
2908
2909         return rc;
2910 }
2911
2912 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2913 {
2914         int rc;
2915
2916         if (!BNXT_PF(bp)) {
2917                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2918                 return -1;
2919         }
2920
2921         rc = bnxt_hwrm_func_qcaps(bp);
2922         if (rc)
2923                 return rc;
2924
2925         bp->pf.func_cfg_flags &=
2926                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2927                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2928         bp->pf.func_cfg_flags |=
2929                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2930         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2931         rc = __bnxt_hwrm_func_qcaps(bp);
2932         return rc;
2933 }
2934
2935 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2936 {
2937         struct hwrm_func_cfg_input req = {0};
2938         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2939         int i;
2940         size_t sz;
2941         int rc = 0;
2942         size_t req_buf_sz;
2943
2944         if (!BNXT_PF(bp)) {
2945                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2946                 return -1;
2947         }
2948
2949         rc = bnxt_hwrm_func_qcaps(bp);
2950
2951         if (rc)
2952                 return rc;
2953
2954         bp->pf.active_vfs = num_vfs;
2955
2956         /*
2957          * First, configure the PF to only use one TX ring.  This ensures that
2958          * there are enough rings for all VFs.
2959          *
2960          * If we don't do this, when we call func_alloc() later, we will lock
2961          * extra rings to the PF that won't be available during func_cfg() of
2962          * the VFs.
2963          *
2964          * This has been fixed with firmware versions above 20.6.54
2965          */
2966         bp->pf.func_cfg_flags &=
2967                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2968                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2969         bp->pf.func_cfg_flags |=
2970                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2971         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2972         if (rc)
2973                 return rc;
2974
2975         /*
2976          * Now, create and register a buffer to hold forwarded VF requests
2977          */
2978         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2979         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2980                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2981         if (bp->pf.vf_req_buf == NULL) {
2982                 rc = -ENOMEM;
2983                 goto error_free;
2984         }
2985         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2986                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2987         for (i = 0; i < num_vfs; i++)
2988                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2989                                         (i * HWRM_MAX_REQ_LEN);
2990
2991         rc = bnxt_hwrm_func_buf_rgtr(bp);
2992         if (rc)
2993                 goto error_free;
2994
2995         populate_vf_func_cfg_req(bp, &req, num_vfs);
2996
2997         bp->pf.active_vfs = 0;
2998         for (i = 0; i < num_vfs; i++) {
2999                 add_random_mac_if_needed(bp, &req, i);
3000
3001                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3002                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3003                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3004                 rc = bnxt_hwrm_send_message(bp,
3005                                             &req,
3006                                             sizeof(req),
3007                                             BNXT_USE_CHIMP_MB);
3008
3009                 /* Clear enable flag for next pass */
3010                 req.enables &= ~rte_cpu_to_le_32(
3011                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3012
3013                 if (rc || resp->error_code) {
3014                         PMD_DRV_LOG(ERR,
3015                                 "Failed to initizlie VF %d\n", i);
3016                         PMD_DRV_LOG(ERR,
3017                                 "Not all VFs available. (%d, %d)\n",
3018                                 rc, resp->error_code);
3019                         HWRM_UNLOCK();
3020                         break;
3021                 }
3022
3023                 HWRM_UNLOCK();
3024
3025                 reserve_resources_from_vf(bp, &req, i);
3026                 bp->pf.active_vfs++;
3027                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3028         }
3029
3030         /*
3031          * Now configure the PF to use "the rest" of the resources
3032          * We're using STD_TX_RING_MODE here though which will limit the TX
3033          * rings.  This will allow QoS to function properly.  Not setting this
3034          * will cause PF rings to break bandwidth settings.
3035          */
3036         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3037         if (rc)
3038                 goto error_free;
3039
3040         rc = update_pf_resource_max(bp);
3041         if (rc)
3042                 goto error_free;
3043
3044         return rc;
3045
3046 error_free:
3047         bnxt_hwrm_func_buf_unrgtr(bp);
3048         return rc;
3049 }
3050
3051 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3052 {
3053         struct hwrm_func_cfg_input req = {0};
3054         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3055         int rc;
3056
3057         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3058
3059         req.fid = rte_cpu_to_le_16(0xffff);
3060         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3061         req.evb_mode = bp->pf.evb_mode;
3062
3063         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3064         HWRM_CHECK_RESULT();
3065         HWRM_UNLOCK();
3066
3067         return rc;
3068 }
3069
3070 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3071                                 uint8_t tunnel_type)
3072 {
3073         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3074         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3075         int rc = 0;
3076
3077         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3078         req.tunnel_type = tunnel_type;
3079         req.tunnel_dst_port_val = port;
3080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3081         HWRM_CHECK_RESULT();
3082
3083         switch (tunnel_type) {
3084         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3085                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3086                 bp->vxlan_port = port;
3087                 break;
3088         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3089                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3090                 bp->geneve_port = port;
3091                 break;
3092         default:
3093                 break;
3094         }
3095
3096         HWRM_UNLOCK();
3097
3098         return rc;
3099 }
3100
3101 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3102                                 uint8_t tunnel_type)
3103 {
3104         struct hwrm_tunnel_dst_port_free_input req = {0};
3105         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3106         int rc = 0;
3107
3108         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3109
3110         req.tunnel_type = tunnel_type;
3111         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3112         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3113
3114         HWRM_CHECK_RESULT();
3115         HWRM_UNLOCK();
3116
3117         return rc;
3118 }
3119
3120 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3121                                         uint32_t flags)
3122 {
3123         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3124         struct hwrm_func_cfg_input req = {0};
3125         int rc;
3126
3127         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3128
3129         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3130         req.flags = rte_cpu_to_le_32(flags);
3131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3132
3133         HWRM_CHECK_RESULT();
3134         HWRM_UNLOCK();
3135
3136         return rc;
3137 }
3138
3139 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3140 {
3141         uint32_t *flag = flagp;
3142
3143         vnic->flags = *flag;
3144 }
3145
3146 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3147 {
3148         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3149 }
3150
3151 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3152 {
3153         int rc = 0;
3154         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3155         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3156
3157         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3158
3159         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3160         req.req_buf_page_size = rte_cpu_to_le_16(
3161                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3162         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3163         req.req_buf_page_addr0 =
3164                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3165         if (req.req_buf_page_addr0 == 0) {
3166                 PMD_DRV_LOG(ERR,
3167                         "unable to map buffer address to physical memory\n");
3168                 return -ENOMEM;
3169         }
3170
3171         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3172
3173         HWRM_CHECK_RESULT();
3174         HWRM_UNLOCK();
3175
3176         return rc;
3177 }
3178
3179 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3180 {
3181         int rc = 0;
3182         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3183         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3184
3185         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3186
3187         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3188
3189         HWRM_CHECK_RESULT();
3190         HWRM_UNLOCK();
3191
3192         return rc;
3193 }
3194
3195 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3196 {
3197         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3198         struct hwrm_func_cfg_input req = {0};
3199         int rc;
3200
3201         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3202
3203         req.fid = rte_cpu_to_le_16(0xffff);
3204         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3205         req.enables = rte_cpu_to_le_32(
3206                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3207         req.async_event_cr = rte_cpu_to_le_16(
3208                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3210
3211         HWRM_CHECK_RESULT();
3212         HWRM_UNLOCK();
3213
3214         return rc;
3215 }
3216
3217 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3218 {
3219         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3220         struct hwrm_func_vf_cfg_input req = {0};
3221         int rc;
3222
3223         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3224
3225         req.enables = rte_cpu_to_le_32(
3226                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3227         req.async_event_cr = rte_cpu_to_le_16(
3228                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3230
3231         HWRM_CHECK_RESULT();
3232         HWRM_UNLOCK();
3233
3234         return rc;
3235 }
3236
3237 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3238 {
3239         struct hwrm_func_cfg_input req = {0};
3240         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3241         uint16_t dflt_vlan, fid;
3242         uint32_t func_cfg_flags;
3243         int rc = 0;
3244
3245         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3246
3247         if (is_vf) {
3248                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3249                 fid = bp->pf.vf_info[vf].fid;
3250                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3251         } else {
3252                 fid = rte_cpu_to_le_16(0xffff);
3253                 func_cfg_flags = bp->pf.func_cfg_flags;
3254                 dflt_vlan = bp->vlan;
3255         }
3256
3257         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3258         req.fid = rte_cpu_to_le_16(fid);
3259         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3260         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3261
3262         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3263
3264         HWRM_CHECK_RESULT();
3265         HWRM_UNLOCK();
3266
3267         return rc;
3268 }
3269
3270 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3271                         uint16_t max_bw, uint16_t enables)
3272 {
3273         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3274         struct hwrm_func_cfg_input req = {0};
3275         int rc;
3276
3277         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3278
3279         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3280         req.enables |= rte_cpu_to_le_32(enables);
3281         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3282         req.max_bw = rte_cpu_to_le_32(max_bw);
3283         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3284
3285         HWRM_CHECK_RESULT();
3286         HWRM_UNLOCK();
3287
3288         return rc;
3289 }
3290
3291 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3292 {
3293         struct hwrm_func_cfg_input req = {0};
3294         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3295         int rc = 0;
3296
3297         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3298
3299         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3300         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3301         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3302         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3303
3304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3305
3306         HWRM_CHECK_RESULT();
3307         HWRM_UNLOCK();
3308
3309         return rc;
3310 }
3311
3312 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3313 {
3314         int rc;
3315
3316         if (BNXT_PF(bp))
3317                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3318         else
3319                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3320
3321         return rc;
3322 }
3323
3324 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3325                               void *encaped, size_t ec_size)
3326 {
3327         int rc = 0;
3328         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3329         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3330
3331         if (ec_size > sizeof(req.encap_request))
3332                 return -1;
3333
3334         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3335
3336         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3337         memcpy(req.encap_request, encaped, ec_size);
3338
3339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3340
3341         HWRM_CHECK_RESULT();
3342         HWRM_UNLOCK();
3343
3344         return rc;
3345 }
3346
3347 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3348                                        struct rte_ether_addr *mac)
3349 {
3350         struct hwrm_func_qcfg_input req = {0};
3351         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3352         int rc;
3353
3354         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3355
3356         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3358
3359         HWRM_CHECK_RESULT();
3360
3361         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3362
3363         HWRM_UNLOCK();
3364
3365         return rc;
3366 }
3367
3368 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3369                             void *encaped, size_t ec_size)
3370 {
3371         int rc = 0;
3372         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3373         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3374
3375         if (ec_size > sizeof(req.encap_request))
3376                 return -1;
3377
3378         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3379
3380         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3381         memcpy(req.encap_request, encaped, ec_size);
3382
3383         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3384
3385         HWRM_CHECK_RESULT();
3386         HWRM_UNLOCK();
3387
3388         return rc;
3389 }
3390
3391 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3392                          struct rte_eth_stats *stats, uint8_t rx)
3393 {
3394         int rc = 0;
3395         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3396         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3397
3398         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3399
3400         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3401
3402         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3403
3404         HWRM_CHECK_RESULT();
3405
3406         if (rx) {
3407                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3408                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3409                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3410                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3411                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3412                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3413                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3414                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3415         } else {
3416                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3417                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3418                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3419                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3420                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3421                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3422         }
3423
3424
3425         HWRM_UNLOCK();
3426
3427         return rc;
3428 }
3429
3430 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3431 {
3432         struct hwrm_port_qstats_input req = {0};
3433         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3434         struct bnxt_pf_info *pf = &bp->pf;
3435         int rc;
3436
3437         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3438
3439         req.port_id = rte_cpu_to_le_16(pf->port_id);
3440         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3441         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3443
3444         HWRM_CHECK_RESULT();
3445         HWRM_UNLOCK();
3446
3447         return rc;
3448 }
3449
3450 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3451 {
3452         struct hwrm_port_clr_stats_input req = {0};
3453         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3454         struct bnxt_pf_info *pf = &bp->pf;
3455         int rc;
3456
3457         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3458         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3459             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3460                 return 0;
3461
3462         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3463
3464         req.port_id = rte_cpu_to_le_16(pf->port_id);
3465         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3466
3467         HWRM_CHECK_RESULT();
3468         HWRM_UNLOCK();
3469
3470         return rc;
3471 }
3472
3473 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3474 {
3475         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3476         struct hwrm_port_led_qcaps_input req = {0};
3477         int rc;
3478
3479         if (BNXT_VF(bp))
3480                 return 0;
3481
3482         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3483         req.port_id = bp->pf.port_id;
3484         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3485
3486         HWRM_CHECK_RESULT();
3487
3488         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3489                 unsigned int i;
3490
3491                 bp->num_leds = resp->num_leds;
3492                 memcpy(bp->leds, &resp->led0_id,
3493                         sizeof(bp->leds[0]) * bp->num_leds);
3494                 for (i = 0; i < bp->num_leds; i++) {
3495                         struct bnxt_led_info *led = &bp->leds[i];
3496
3497                         uint16_t caps = led->led_state_caps;
3498
3499                         if (!led->led_group_id ||
3500                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3501                                 bp->num_leds = 0;
3502                                 break;
3503                         }
3504                 }
3505         }
3506
3507         HWRM_UNLOCK();
3508
3509         return rc;
3510 }
3511
3512 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3513 {
3514         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3515         struct hwrm_port_led_cfg_input req = {0};
3516         struct bnxt_led_cfg *led_cfg;
3517         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3518         uint16_t duration = 0;
3519         int rc, i;
3520
3521         if (!bp->num_leds || BNXT_VF(bp))
3522                 return -EOPNOTSUPP;
3523
3524         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3525
3526         if (led_on) {
3527                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3528                 duration = rte_cpu_to_le_16(500);
3529         }
3530         req.port_id = bp->pf.port_id;
3531         req.num_leds = bp->num_leds;
3532         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3533         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3534                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3535                 led_cfg->led_id = bp->leds[i].led_id;
3536                 led_cfg->led_state = led_state;
3537                 led_cfg->led_blink_on = duration;
3538                 led_cfg->led_blink_off = duration;
3539                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3540         }
3541
3542         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3543
3544         HWRM_CHECK_RESULT();
3545         HWRM_UNLOCK();
3546
3547         return rc;
3548 }
3549
3550 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3551                                uint32_t *length)
3552 {
3553         int rc;
3554         struct hwrm_nvm_get_dir_info_input req = {0};
3555         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3556
3557         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3558
3559         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3560
3561         HWRM_CHECK_RESULT();
3562         HWRM_UNLOCK();
3563
3564         if (!rc) {
3565                 *entries = rte_le_to_cpu_32(resp->entries);
3566                 *length = rte_le_to_cpu_32(resp->entry_length);
3567         }
3568         return rc;
3569 }
3570
3571 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3572 {
3573         int rc;
3574         uint32_t dir_entries;
3575         uint32_t entry_length;
3576         uint8_t *buf;
3577         size_t buflen;
3578         rte_iova_t dma_handle;
3579         struct hwrm_nvm_get_dir_entries_input req = {0};
3580         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3581
3582         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3583         if (rc != 0)
3584                 return rc;
3585
3586         *data++ = dir_entries;
3587         *data++ = entry_length;
3588         len -= 2;
3589         memset(data, 0xff, len);
3590
3591         buflen = dir_entries * entry_length;
3592         buf = rte_malloc("nvm_dir", buflen, 0);
3593         rte_mem_lock_page(buf);
3594         if (buf == NULL)
3595                 return -ENOMEM;
3596         dma_handle = rte_mem_virt2iova(buf);
3597         if (dma_handle == 0) {
3598                 PMD_DRV_LOG(ERR,
3599                         "unable to map response address to physical memory\n");
3600                 return -ENOMEM;
3601         }
3602         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3603         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3604         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3605
3606         if (rc == 0)
3607                 memcpy(data, buf, len > buflen ? buflen : len);
3608
3609         rte_free(buf);
3610         HWRM_CHECK_RESULT();
3611         HWRM_UNLOCK();
3612
3613         return rc;
3614 }
3615
3616 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3617                              uint32_t offset, uint32_t length,
3618                              uint8_t *data)
3619 {
3620         int rc;
3621         uint8_t *buf;
3622         rte_iova_t dma_handle;
3623         struct hwrm_nvm_read_input req = {0};
3624         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3625
3626         buf = rte_malloc("nvm_item", length, 0);
3627         rte_mem_lock_page(buf);
3628         if (!buf)
3629                 return -ENOMEM;
3630
3631         dma_handle = rte_mem_virt2iova(buf);
3632         if (dma_handle == 0) {
3633                 PMD_DRV_LOG(ERR,
3634                         "unable to map response address to physical memory\n");
3635                 return -ENOMEM;
3636         }
3637         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3638         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3639         req.dir_idx = rte_cpu_to_le_16(index);
3640         req.offset = rte_cpu_to_le_32(offset);
3641         req.len = rte_cpu_to_le_32(length);
3642         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3643         if (rc == 0)
3644                 memcpy(data, buf, length);
3645
3646         rte_free(buf);
3647         HWRM_CHECK_RESULT();
3648         HWRM_UNLOCK();
3649
3650         return rc;
3651 }
3652
3653 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3654 {
3655         int rc;
3656         struct hwrm_nvm_erase_dir_entry_input req = {0};
3657         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3658
3659         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3660         req.dir_idx = rte_cpu_to_le_16(index);
3661         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662         HWRM_CHECK_RESULT();
3663         HWRM_UNLOCK();
3664
3665         return rc;
3666 }
3667
3668
3669 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3670                           uint16_t dir_ordinal, uint16_t dir_ext,
3671                           uint16_t dir_attr, const uint8_t *data,
3672                           size_t data_len)
3673 {
3674         int rc;
3675         struct hwrm_nvm_write_input req = {0};
3676         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3677         rte_iova_t dma_handle;
3678         uint8_t *buf;
3679
3680         buf = rte_malloc("nvm_write", data_len, 0);
3681         rte_mem_lock_page(buf);
3682         if (!buf)
3683                 return -ENOMEM;
3684
3685         dma_handle = rte_mem_virt2iova(buf);
3686         if (dma_handle == 0) {
3687                 PMD_DRV_LOG(ERR,
3688                         "unable to map response address to physical memory\n");
3689                 return -ENOMEM;
3690         }
3691         memcpy(buf, data, data_len);
3692
3693         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3694
3695         req.dir_type = rte_cpu_to_le_16(dir_type);
3696         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3697         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3698         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3699         req.dir_data_length = rte_cpu_to_le_32(data_len);
3700         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3701
3702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3703
3704         rte_free(buf);
3705         HWRM_CHECK_RESULT();
3706         HWRM_UNLOCK();
3707
3708         return rc;
3709 }
3710
3711 static void
3712 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3713 {
3714         uint32_t *count = cbdata;
3715
3716         *count = *count + 1;
3717 }
3718
3719 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3720                                      struct bnxt_vnic_info *vnic __rte_unused)
3721 {
3722         return 0;
3723 }
3724
3725 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3726 {
3727         uint32_t count = 0;
3728
3729         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3730             &count, bnxt_vnic_count_hwrm_stub);
3731
3732         return count;
3733 }
3734
3735 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3736                                         uint16_t *vnic_ids)
3737 {
3738         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3739         struct hwrm_func_vf_vnic_ids_query_output *resp =
3740                                                 bp->hwrm_cmd_resp_addr;
3741         int rc;
3742
3743         /* First query all VNIC ids */
3744         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3745
3746         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3747         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3748         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3749
3750         if (req.vnic_id_tbl_addr == 0) {
3751                 HWRM_UNLOCK();
3752                 PMD_DRV_LOG(ERR,
3753                 "unable to map VNIC ID table address to physical memory\n");
3754                 return -ENOMEM;
3755         }
3756         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3757         if (rc) {
3758                 HWRM_UNLOCK();
3759                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3760                 return -1;
3761         } else if (resp->error_code) {
3762                 rc = rte_le_to_cpu_16(resp->error_code);
3763                 HWRM_UNLOCK();
3764                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3765                 return -1;
3766         }
3767         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3768
3769         HWRM_UNLOCK();
3770
3771         return rc;
3772 }
3773
3774 /*
3775  * This function queries the VNIC IDs  for a specified VF. It then calls
3776  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3777  * Then it calls the hwrm_cb function to program this new vnic configuration.
3778  */
3779 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3780         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3781         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3782 {
3783         struct bnxt_vnic_info vnic;
3784         int rc = 0;
3785         int i, num_vnic_ids;
3786         uint16_t *vnic_ids;
3787         size_t vnic_id_sz;
3788         size_t sz;
3789
3790         /* First query all VNIC ids */
3791         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3792         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3793                         RTE_CACHE_LINE_SIZE);
3794         if (vnic_ids == NULL) {
3795                 rc = -ENOMEM;
3796                 return rc;
3797         }
3798         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3799                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3800
3801         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3802
3803         if (num_vnic_ids < 0)
3804                 return num_vnic_ids;
3805
3806         /* Retrieve VNIC, update bd_stall then update */
3807
3808         for (i = 0; i < num_vnic_ids; i++) {
3809                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3810                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3811                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3812                 if (rc)
3813                         break;
3814                 if (vnic.mru <= 4)      /* Indicates unallocated */
3815                         continue;
3816
3817                 vnic_cb(&vnic, cbdata);
3818
3819                 rc = hwrm_cb(bp, &vnic);
3820                 if (rc)
3821                         break;
3822         }
3823
3824         rte_free(vnic_ids);
3825
3826         return rc;
3827 }
3828
3829 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3830                                               bool on)
3831 {
3832         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3833         struct hwrm_func_cfg_input req = {0};
3834         int rc;
3835
3836         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3837
3838         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3839         req.enables |= rte_cpu_to_le_32(
3840                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3841         req.vlan_antispoof_mode = on ?
3842                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3843                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3845
3846         HWRM_CHECK_RESULT();
3847         HWRM_UNLOCK();
3848
3849         return rc;
3850 }
3851
3852 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3853 {
3854         struct bnxt_vnic_info vnic;
3855         uint16_t *vnic_ids;
3856         size_t vnic_id_sz;
3857         int num_vnic_ids, i;
3858         size_t sz;
3859         int rc;
3860
3861         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3862         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3863                         RTE_CACHE_LINE_SIZE);
3864         if (vnic_ids == NULL) {
3865                 rc = -ENOMEM;
3866                 return rc;
3867         }
3868
3869         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3870                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3871
3872         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3873         if (rc <= 0)
3874                 goto exit;
3875         num_vnic_ids = rc;
3876
3877         /*
3878          * Loop through to find the default VNIC ID.
3879          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3880          * by sending the hwrm_func_qcfg command to the firmware.
3881          */
3882         for (i = 0; i < num_vnic_ids; i++) {
3883                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3884                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3885                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3886                                         bp->pf.first_vf_id + vf);
3887                 if (rc)
3888                         goto exit;
3889                 if (vnic.func_default) {
3890                         rte_free(vnic_ids);
3891                         return vnic.fw_vnic_id;
3892                 }
3893         }
3894         /* Could not find a default VNIC. */
3895         PMD_DRV_LOG(ERR, "No default VNIC\n");
3896 exit:
3897         rte_free(vnic_ids);
3898         return -1;
3899 }
3900
3901 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3902                          uint16_t dst_id,
3903                          struct bnxt_filter_info *filter)
3904 {
3905         int rc = 0;
3906         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3907         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3908         uint32_t enables = 0;
3909
3910         if (filter->fw_em_filter_id != UINT64_MAX)
3911                 bnxt_hwrm_clear_em_filter(bp, filter);
3912
3913         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3914
3915         req.flags = rte_cpu_to_le_32(filter->flags);
3916
3917         enables = filter->enables |
3918               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3919         req.dst_id = rte_cpu_to_le_16(dst_id);
3920
3921         if (filter->ip_addr_type) {
3922                 req.ip_addr_type = filter->ip_addr_type;
3923                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3924         }
3925         if (enables &
3926             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3927                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3928         if (enables &
3929             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3930                 memcpy(req.src_macaddr, filter->src_macaddr,
3931                        RTE_ETHER_ADDR_LEN);
3932         if (enables &
3933             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3934                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3935                        RTE_ETHER_ADDR_LEN);
3936         if (enables &
3937             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3938                 req.ovlan_vid = filter->l2_ovlan;
3939         if (enables &
3940             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3941                 req.ivlan_vid = filter->l2_ivlan;
3942         if (enables &
3943             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3944                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3945         if (enables &
3946             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3947                 req.ip_protocol = filter->ip_protocol;
3948         if (enables &
3949             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3950                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3951         if (enables &
3952             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3953                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3954         if (enables &
3955             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3956                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3957         if (enables &
3958             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3959                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3960         if (enables &
3961             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3962                 req.mirror_vnic_id = filter->mirror_vnic_id;
3963
3964         req.enables = rte_cpu_to_le_32(enables);
3965
3966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3967
3968         HWRM_CHECK_RESULT();
3969
3970         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3971         HWRM_UNLOCK();
3972
3973         return rc;
3974 }
3975
3976 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3977 {
3978         int rc = 0;
3979         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3980         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3981
3982         if (filter->fw_em_filter_id == UINT64_MAX)
3983                 return 0;
3984
3985         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3986         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
3987
3988         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3989
3990         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3991
3992         HWRM_CHECK_RESULT();
3993         HWRM_UNLOCK();
3994
3995         filter->fw_em_filter_id = UINT64_MAX;
3996         filter->fw_l2_filter_id = UINT64_MAX;
3997
3998         return 0;
3999 }
4000
4001 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4002                          uint16_t dst_id,
4003                          struct bnxt_filter_info *filter)
4004 {
4005         int rc = 0;
4006         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4007         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4008                                                 bp->hwrm_cmd_resp_addr;
4009         uint32_t enables = 0;
4010
4011         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4012                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4013
4014         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4015
4016         req.flags = rte_cpu_to_le_32(filter->flags);
4017
4018         enables = filter->enables |
4019               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4020         req.dst_id = rte_cpu_to_le_16(dst_id);
4021
4022
4023         if (filter->ip_addr_type) {
4024                 req.ip_addr_type = filter->ip_addr_type;
4025                 enables |=
4026                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4027         }
4028         if (enables &
4029             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4030                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4031         if (enables &
4032             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4033                 memcpy(req.src_macaddr, filter->src_macaddr,
4034                        RTE_ETHER_ADDR_LEN);
4035         //if (enables &
4036             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4037                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4038                        //RTE_ETHER_ADDR_LEN);
4039         if (enables &
4040             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4041                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4042         if (enables &
4043             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4044                 req.ip_protocol = filter->ip_protocol;
4045         if (enables &
4046             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4047                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4048         if (enables &
4049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4050                 req.src_ipaddr_mask[0] =
4051                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4052         if (enables &
4053             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4054                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4055         if (enables &
4056             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4057                 req.dst_ipaddr_mask[0] =
4058                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4059         if (enables &
4060             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4061                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4062         if (enables &
4063             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4064                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4065         if (enables &
4066             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4067                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4068         if (enables &
4069             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4070                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4071         if (enables &
4072             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4073                 req.mirror_vnic_id = filter->mirror_vnic_id;
4074
4075         req.enables = rte_cpu_to_le_32(enables);
4076
4077         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4078
4079         HWRM_CHECK_RESULT();
4080
4081         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4082         HWRM_UNLOCK();
4083
4084         return rc;
4085 }
4086
4087 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4088                                 struct bnxt_filter_info *filter)
4089 {
4090         int rc = 0;
4091         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4092         struct hwrm_cfa_ntuple_filter_free_output *resp =
4093                                                 bp->hwrm_cmd_resp_addr;
4094
4095         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4096                 return 0;
4097
4098         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4099
4100         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4101
4102         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4103
4104         HWRM_CHECK_RESULT();
4105         HWRM_UNLOCK();
4106
4107         filter->fw_ntuple_filter_id = UINT64_MAX;
4108
4109         return 0;
4110 }
4111
4112 static int
4113 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4114 {
4115         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4116         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4117         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4118         int nr_ctxs = bp->max_ring_grps;
4119         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4120         uint16_t *ring_tbl = vnic->rss_table;
4121         int max_rings = bp->rx_nr_rings;
4122         int i, j, k, cnt;
4123         int rc = 0;
4124
4125         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4126
4127         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4128         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4129         req.hash_mode_flags = vnic->hash_mode;
4130
4131         req.ring_grp_tbl_addr =
4132             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4133         req.hash_key_tbl_addr =
4134             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4135
4136         for (i = 0, k = 0; i < nr_ctxs; i++) {
4137                 struct bnxt_rx_ring_info *rxr;
4138                 struct bnxt_cp_ring_info *cpr;
4139
4140                 req.ring_table_pair_index = i;
4141                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4142
4143                 for (j = 0; j < 64; j++) {
4144                         uint16_t ring_id;
4145
4146                         /* Find next active ring. */
4147                         for (cnt = 0; cnt < max_rings; cnt++) {
4148                                 if (rx_queue_state[k] !=
4149                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4150                                         break;
4151                                 if (++k == max_rings)
4152                                         k = 0;
4153                         }
4154
4155                         /* Return if no rings are active. */
4156                         if (cnt == max_rings)
4157                                 return 0;
4158
4159                         /* Add rx/cp ring pair to RSS table. */
4160                         rxr = rxqs[k]->rx_ring;
4161                         cpr = rxqs[k]->cp_ring;
4162
4163                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4164                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4165                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4166                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4167
4168                         if (++k == max_rings)
4169                                 k = 0;
4170                 }
4171                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4172                                             BNXT_USE_CHIMP_MB);
4173
4174                 HWRM_CHECK_RESULT();
4175                 if (rc)
4176                         break;
4177         }
4178
4179         HWRM_UNLOCK();
4180
4181         return rc;
4182 }
4183
4184 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4185 {
4186         unsigned int rss_idx, fw_idx, i;
4187
4188         if (!(vnic->rss_table && vnic->hash_type))
4189                 return 0;
4190
4191         if (BNXT_CHIP_THOR(bp))
4192                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4193
4194         /*
4195          * Fill the RSS hash & redirection table with
4196          * ring group ids for all VNICs
4197          */
4198         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4199                 rss_idx++, fw_idx++) {
4200                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4201                         fw_idx %= bp->rx_cp_nr_rings;
4202                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4203                                 break;
4204                         fw_idx++;
4205                 }
4206                 if (i == bp->rx_cp_nr_rings)
4207                         return 0;
4208                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4209         }
4210         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4211 }
4212
4213 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4214         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4215 {
4216         uint16_t flags;
4217
4218         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4219
4220         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4221         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4222
4223         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4224         req->num_cmpl_dma_aggr_during_int =
4225                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4226
4227         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4228
4229         /* min timer set to 1/2 of interrupt timer */
4230         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4231
4232         /* buf timer set to 1/4 of interrupt timer */
4233         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4234
4235         req->cmpl_aggr_dma_tmr_during_int =
4236                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4237
4238         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4239                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4240         req->flags = rte_cpu_to_le_16(flags);
4241 }
4242
4243 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4244                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4245 {
4246         struct hwrm_ring_aggint_qcaps_input req = {0};
4247         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4248         uint32_t enables;
4249         uint16_t flags;
4250         int rc;
4251
4252         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4253         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4254         if (rc)
4255                 goto out;
4256
4257         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4258         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4259
4260         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4261                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4262         agg_req->flags = rte_cpu_to_le_16(flags);
4263         enables =
4264          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4265          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4266         agg_req->enables = rte_cpu_to_le_32(enables);
4267
4268 out:
4269         HWRM_CHECK_RESULT();
4270         HWRM_UNLOCK();
4271         return rc;
4272 }
4273
4274 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4275                         struct bnxt_coal *coal, uint16_t ring_id)
4276 {
4277         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4278         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4279                                                 bp->hwrm_cmd_resp_addr;
4280         int rc;
4281
4282         /* Set ring coalesce parameters only for 100G NICs */
4283         if (BNXT_CHIP_THOR(bp)) {
4284                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4285                         return -1;
4286         } else if (bnxt_stratus_device(bp)) {
4287                 bnxt_hwrm_set_coal_params(coal, &req);
4288         } else {
4289                 return 0;
4290         }
4291
4292         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4293         req.ring_id = rte_cpu_to_le_16(ring_id);
4294         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4295         HWRM_CHECK_RESULT();
4296         HWRM_UNLOCK();
4297         return 0;
4298 }
4299
4300 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4301 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4302 {
4303         struct hwrm_func_backing_store_qcaps_input req = {0};
4304         struct hwrm_func_backing_store_qcaps_output *resp =
4305                 bp->hwrm_cmd_resp_addr;
4306         int rc;
4307
4308         if (!BNXT_CHIP_THOR(bp) ||
4309             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4310             BNXT_VF(bp) ||
4311             bp->ctx)
4312                 return 0;
4313
4314         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4316         HWRM_CHECK_RESULT_SILENT();
4317
4318         if (!rc) {
4319                 struct bnxt_ctx_pg_info *ctx_pg;
4320                 struct bnxt_ctx_mem_info *ctx;
4321                 int total_alloc_len;
4322                 int i;
4323
4324                 total_alloc_len = sizeof(*ctx);
4325                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4326                                  RTE_CACHE_LINE_SIZE);
4327                 if (!ctx) {
4328                         rc = -ENOMEM;
4329                         goto ctx_err;
4330                 }
4331                 memset(ctx, 0, total_alloc_len);
4332
4333                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4334                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4335                                     RTE_CACHE_LINE_SIZE);
4336                 if (!ctx_pg) {
4337                         rc = -ENOMEM;
4338                         goto ctx_err;
4339                 }
4340                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4341                         ctx->tqm_mem[i] = ctx_pg;
4342
4343                 bp->ctx = ctx;
4344                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4345                 ctx->qp_min_qp1_entries =
4346                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4347                 ctx->qp_max_l2_entries =
4348                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4349                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4350                 ctx->srq_max_l2_entries =
4351                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4352                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4353                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4354                 ctx->cq_max_l2_entries =
4355                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4356                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4357                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4358                 ctx->vnic_max_vnic_entries =
4359                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4360                 ctx->vnic_max_ring_table_entries =
4361                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4362                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4363                 ctx->stat_max_entries =
4364                         rte_le_to_cpu_32(resp->stat_max_entries);
4365                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4366                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4367                 ctx->tqm_min_entries_per_ring =
4368                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4369                 ctx->tqm_max_entries_per_ring =
4370                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4371                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4372                 if (!ctx->tqm_entries_multiple)
4373                         ctx->tqm_entries_multiple = 1;
4374                 ctx->mrav_max_entries =
4375                         rte_le_to_cpu_32(resp->mrav_max_entries);
4376                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4377                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4378                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4379         } else {
4380                 rc = 0;
4381         }
4382 ctx_err:
4383         HWRM_UNLOCK();
4384         return rc;
4385 }
4386
4387 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4388 {
4389         struct hwrm_func_backing_store_cfg_input req = {0};
4390         struct hwrm_func_backing_store_cfg_output *resp =
4391                 bp->hwrm_cmd_resp_addr;
4392         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4393         struct bnxt_ctx_pg_info *ctx_pg;
4394         uint32_t *num_entries;
4395         uint64_t *pg_dir;
4396         uint8_t *pg_attr;
4397         uint32_t ena;
4398         int i, rc;
4399
4400         if (!ctx)
4401                 return 0;
4402
4403         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4404         req.enables = rte_cpu_to_le_32(enables);
4405
4406         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4407                 ctx_pg = &ctx->qp_mem;
4408                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4409                 req.qp_num_qp1_entries =
4410                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4411                 req.qp_num_l2_entries =
4412                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4413                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4414                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4415                                       &req.qpc_pg_size_qpc_lvl,
4416                                       &req.qpc_page_dir);
4417         }
4418
4419         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4420                 ctx_pg = &ctx->srq_mem;
4421                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4422                 req.srq_num_l2_entries =
4423                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4424                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4425                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4426                                       &req.srq_pg_size_srq_lvl,
4427                                       &req.srq_page_dir);
4428         }
4429
4430         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4431                 ctx_pg = &ctx->cq_mem;
4432                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4433                 req.cq_num_l2_entries =
4434                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4435                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4436                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4437                                       &req.cq_pg_size_cq_lvl,
4438                                       &req.cq_page_dir);
4439         }
4440
4441         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4442                 ctx_pg = &ctx->vnic_mem;
4443                 req.vnic_num_vnic_entries =
4444                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4445                 req.vnic_num_ring_table_entries =
4446                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4447                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4448                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4449                                       &req.vnic_pg_size_vnic_lvl,
4450                                       &req.vnic_page_dir);
4451         }
4452
4453         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4454                 ctx_pg = &ctx->stat_mem;
4455                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4456                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4457                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4458                                       &req.stat_pg_size_stat_lvl,
4459                                       &req.stat_page_dir);
4460         }
4461
4462         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4463         num_entries = &req.tqm_sp_num_entries;
4464         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4465         pg_dir = &req.tqm_sp_page_dir;
4466         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4467         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4468                 if (!(enables & ena))
4469                         continue;
4470
4471                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4472
4473                 ctx_pg = ctx->tqm_mem[i];
4474                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4475                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4476         }
4477
4478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4479         HWRM_CHECK_RESULT();
4480         HWRM_UNLOCK();
4481         if (rc)
4482                 rc = -EIO;
4483         return rc;
4484 }
4485
4486 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4487 {
4488         struct hwrm_port_qstats_ext_input req = {0};
4489         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4490         struct bnxt_pf_info *pf = &bp->pf;
4491         int rc;
4492
4493         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4494               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4495                 return 0;
4496
4497         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4498
4499         req.port_id = rte_cpu_to_le_16(pf->port_id);
4500         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4501                 req.tx_stat_host_addr =
4502                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4503                 req.tx_stat_size =
4504                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4505         }
4506         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4507                 req.rx_stat_host_addr =
4508                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4509                 req.rx_stat_size =
4510                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4511         }
4512         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4513
4514         if (rc) {
4515                 bp->fw_rx_port_stats_ext_size = 0;
4516                 bp->fw_tx_port_stats_ext_size = 0;
4517         } else {
4518                 bp->fw_rx_port_stats_ext_size =
4519                         rte_le_to_cpu_16(resp->rx_stat_size);
4520                 bp->fw_tx_port_stats_ext_size =
4521                         rte_le_to_cpu_16(resp->tx_stat_size);
4522         }
4523
4524         HWRM_CHECK_RESULT();
4525         HWRM_UNLOCK();
4526
4527         return rc;
4528 }
4529
4530 int
4531 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4532 {
4533         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4534         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4535                 bp->hwrm_cmd_resp_addr;
4536         int rc = 0;
4537
4538         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4539         req.tunnel_type = type;
4540         req.dest_fid = bp->fw_fid;
4541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4542         HWRM_CHECK_RESULT();
4543
4544         HWRM_UNLOCK();
4545
4546         return rc;
4547 }
4548
4549 int
4550 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4551 {
4552         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4553         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4554                 bp->hwrm_cmd_resp_addr;
4555         int rc = 0;
4556
4557         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4558         req.tunnel_type = type;
4559         req.dest_fid = bp->fw_fid;
4560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4561         HWRM_CHECK_RESULT();
4562
4563         HWRM_UNLOCK();
4564
4565         return rc;
4566 }
4567
4568 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4569 {
4570         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4571         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4572                 bp->hwrm_cmd_resp_addr;
4573         int rc = 0;
4574
4575         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4576         req.src_fid = bp->fw_fid;
4577         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4578         HWRM_CHECK_RESULT();
4579
4580         if (type)
4581                 *type = resp->tunnel_mask;
4582
4583         HWRM_UNLOCK();
4584
4585         return rc;
4586 }
4587
4588 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4589                                    uint16_t *dst_fid)
4590 {
4591         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4592         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4593                 bp->hwrm_cmd_resp_addr;
4594         int rc = 0;
4595
4596         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4597         req.src_fid = bp->fw_fid;
4598         req.tunnel_type = tun_type;
4599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4600         HWRM_CHECK_RESULT();
4601
4602         if (dst_fid)
4603                 *dst_fid = resp->dest_fid;
4604
4605         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4606
4607         HWRM_UNLOCK();
4608
4609         return rc;
4610 }
4611
4612 int bnxt_hwrm_set_mac(struct bnxt *bp)
4613 {
4614         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4615         struct hwrm_func_vf_cfg_input req = {0};
4616         int rc = 0;
4617
4618         if (!BNXT_VF(bp))
4619                 return 0;
4620
4621         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4622
4623         req.enables =
4624                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4625         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4626
4627         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4628
4629         HWRM_CHECK_RESULT();
4630
4631         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4632         HWRM_UNLOCK();
4633
4634         return rc;
4635 }