drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                10000
  30 #define HWRM_VERSION_1_9_1              0x10901
  31
  32 struct bnxt_plcmodes_cfg {
  33         uint32_t        flags;
  34         uint16_t        jumbo_thresh;
  35         uint16_t        hds_offset;
  36         uint16_t        hds_threshold;
  37 };
  38
  39 static int page_getenum(size_t size)
  40 {
  41         if (size <= 1 << 4)
  42                 return 4;
  43         if (size <= 1 << 12)
  44                 return 12;
  45         if (size <= 1 << 13)
  46                 return 13;
  47         if (size <= 1 << 16)
  48                 return 16;
  49         if (size <= 1 << 21)
  50                 return 21;
  51         if (size <= 1 << 22)
  52                 return 22;
  53         if (size <= 1 << 30)
  54                 return 30;
  55         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  56         return sizeof(void *) * 8 - 1;
  57 }
  58
  59 static int page_roundup(size_t size)
  60 {
  61         return 1 << page_getenum(size);
  62 }
  63
  64 /*
  65  * HWRM Functions (sent to HWRM)
  66  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  67  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  68  * command was failed by the ChiMP.
  69  */
  70
  71 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  72                                         uint32_t msg_len)
  73 {
  74         unsigned int i;
  75         struct input *req = msg;
  76         struct output *resp = bp->hwrm_cmd_resp_addr;
  77         uint32_t *data = msg;
  78         uint8_t *bar;
  79         uint8_t *valid;
  80         uint16_t max_req_len = bp->max_req_len;
  81         struct hwrm_short_input short_input = { 0 };
  82
  83         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
  84                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
  85
  86                 memset(short_cmd_req, 0, bp->max_req_len);
  87                 memcpy(short_cmd_req, req, msg_len);
  88
  89                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
  90                 short_input.signature = rte_cpu_to_le_16(
  91                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
  92                 short_input.size = rte_cpu_to_le_16(msg_len);
  93                 short_input.req_addr =
  94                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
  95
  96                 data = (uint32_t *)&short_input;
  97                 msg_len = sizeof(short_input);
  98
  99                 /* Sync memory write before updating doorbell */
 100                 rte_wmb();
 101
 102                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 103         }
 104
 105         /* Write request msg to hwrm channel */
 106         for (i = 0; i < msg_len; i += 4) {
 107                 bar = (uint8_t *)bp->bar0 + i;
 108                 rte_write32(*data, bar);
 109                 data++;
 110         }
 111
 112         /* Zero the rest of the request space */
 113         for (; i < max_req_len; i += 4) {
 114                 bar = (uint8_t *)bp->bar0 + i;
 115                 rte_write32(0, bar);
 116         }
 117
 118         /* Ring channel doorbell */
 119         bar = (uint8_t *)bp->bar0 + 0x100;
 120         rte_write32(1, bar);
 121
 122         /* Poll for the valid bit */
 123         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 124                 /* Sanity check on the resp->resp_len */
 125                 rte_rmb();
 126                 if (resp->resp_len && resp->resp_len <=
 127                                 bp->max_resp_len) {
 128                         /* Last byte of resp contains the valid key */
 129                         valid = (uint8_t *)resp + resp->resp_len - 1;
 130                         if (*valid == HWRM_RESP_VALID_KEY)
 131                                 break;
 132                 }
 133                 rte_delay_us(600);
 134         }
 135
 136         if (i >= HWRM_CMD_TIMEOUT) {
 137                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 138                         req->req_type);
 139                 goto err_ret;
 140         }
 141         return 0;
 142
 143 err_ret:
 144         return -1;
 145 }
 146
 147 /*
 148  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 149  * spinlock, and does initial processing.
 150  *
 151  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 152  * releases the spinlock only if it returns.  If the regular int return codes
 153  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 154  * directly, rather it should be copied and modified to suit the function.
 155  *
 156  * HWRM_UNLOCK() must be called after all response processing is completed.
 157  */
 158 #define HWRM_PREP(req, type) do { \
 159         rte_spinlock_lock(&bp->hwrm_lock); \
 160         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 161         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 162         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 163         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 164         req.target_id = rte_cpu_to_le_16(0xffff); \
 165         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 166 } while (0)
 167
 168 #define HWRM_CHECK_RESULT() do {\
 169         if (rc) { \
 170                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 171                 rte_spinlock_unlock(&bp->hwrm_lock); \
 172                 return rc; \
 173         } \
 174         if (resp->error_code) { \
 175                 rc = rte_le_to_cpu_16(resp->error_code); \
 176                 if (resp->resp_len >= 16) { \
 177                         struct hwrm_err_output *tmp_hwrm_err_op = \
 178                                                 (void *)resp; \
 179                         PMD_DRV_LOG(ERR, \
 180                                 "error %d:%d:%08x:%04x\n", \
 181                                 rc, tmp_hwrm_err_op->cmd_err, \
 182                                 rte_le_to_cpu_32(\
 183                                         tmp_hwrm_err_op->opaque_0), \
 184                                 rte_le_to_cpu_16(\
 185                                         tmp_hwrm_err_op->opaque_1)); \
 186                 } else { \
 187                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 188                 } \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192 } while (0)
 193
 194 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 195
 196 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 197 {
 198         int rc = 0;
 199         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 200         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 201
 202         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 203         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 204         req.mask = 0;
 205
 206         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 207
 208         HWRM_CHECK_RESULT();
 209         HWRM_UNLOCK();
 210
 211         return rc;
 212 }
 213
 214 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 215                                  struct bnxt_vnic_info *vnic,
 216                                  uint16_t vlan_count,
 217                                  struct bnxt_vlan_table_entry *vlan_table)
 218 {
 219         int rc = 0;
 220         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 221         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 222         uint32_t mask = 0;
 223
 224         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 225         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 226
 227         /* FIXME add multicast flag, when multicast adding options is supported
 228          * by ethtool.
 229          */
 230         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 231                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 232         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 233                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 234         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 235                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 236         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 237                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 238         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 239                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 240         if (vnic->mc_addr_cnt) {
 241                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 242                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 243                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 244         }
 245         if (vlan_table) {
 246                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 247                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 248                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 249                          rte_mem_virt2iova(vlan_table));
 250                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 251         }
 252         req.mask = rte_cpu_to_le_32(mask);
 253
 254         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 255
 256         HWRM_CHECK_RESULT();
 257         HWRM_UNLOCK();
 258
 259         return rc;
 260 }
 261
 262 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 263                         uint16_t vlan_count,
 264                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 265 {
 266         int rc = 0;
 267         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 268         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 269                                                 bp->hwrm_cmd_resp_addr;
 270
 271         /*
 272          * Older HWRM versions did not support this command, and the set_rx_mask
 273          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 274          * removed from set_rx_mask call, and this command was added.
 275          *
 276          * This command is also present from 1.7.8.11 and higher,
 277          * as well as 1.7.8.0
 278          */
 279         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 280                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 281                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 282                                         (11)))
 283                                 return 0;
 284                 }
 285         }
 286         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 287         req.fid = rte_cpu_to_le_16(fid);
 288
 289         req.vlan_tag_mask_tbl_addr =
 290                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 291         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 292
 293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 294
 295         HWRM_CHECK_RESULT();
 296         HWRM_UNLOCK();
 297
 298         return rc;
 299 }
 300
 301 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 302                            struct bnxt_filter_info *filter)
 303 {
 304         int rc = 0;
 305         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 306         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 307
 308         if (filter->fw_l2_filter_id == UINT64_MAX)
 309                 return 0;
 310
 311         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 312
 313         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 314
 315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 316
 317         HWRM_CHECK_RESULT();
 318         HWRM_UNLOCK();
 319
 320         filter->fw_l2_filter_id = -1;
 321
 322         return 0;
 323 }
 324
 325 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 326                          uint16_t dst_id,
 327                          struct bnxt_filter_info *filter)
 328 {
 329         int rc = 0;
 330         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 331         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 332         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 333         const struct rte_eth_vmdq_rx_conf *conf =
 334                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 335         uint32_t enables = 0;
 336         uint16_t j = dst_id - 1;
 337
 338         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 339         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 340             conf->pool_map[j].pools & (1UL << j)) {
 341                 PMD_DRV_LOG(DEBUG,
 342                         "Add vlan %u to vmdq pool %u\n",
 343                         conf->pool_map[j].vlan_id, j);
 344
 345                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 346                 filter->enables |=
 347                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 348                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 349         }
 350
 351         if (filter->fw_l2_filter_id != UINT64_MAX)
 352                 bnxt_hwrm_clear_l2_filter(bp, filter);
 353
 354         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 355
 356         req.flags = rte_cpu_to_le_32(filter->flags);
 357
 358         enables = filter->enables |
 359               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 360         req.dst_id = rte_cpu_to_le_16(dst_id);
 361
 362         if (enables &
 363             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 364                 memcpy(req.l2_addr, filter->l2_addr,
 365                        ETHER_ADDR_LEN);
 366         if (enables &
 367             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 368                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 369                        ETHER_ADDR_LEN);
 370         if (enables &
 371             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 372                 req.l2_ovlan = filter->l2_ovlan;
 373         if (enables &
 374             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 375                 req.l2_ovlan = filter->l2_ivlan;
 376         if (enables &
 377             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 378                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 379         if (enables &
 380             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 381                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 382         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 383                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 384         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 385                 req.src_type = filter->src_type;
 386
 387         req.enables = rte_cpu_to_le_32(enables);
 388
 389         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 390
 391         HWRM_CHECK_RESULT();
 392
 393         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 394         HWRM_UNLOCK();
 395
 396         return rc;
 397 }
 398
 399 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 400 {
 401         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 402         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 403         uint32_t flags = 0;
 404         int rc;
 405
 406         if (!ptp)
 407                 return 0;
 408
 409         HWRM_PREP(req, PORT_MAC_CFG);
 410
 411         if (ptp->rx_filter)
 412                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 413         else
 414                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 415         if (ptp->tx_tstamp_en)
 416                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 417         else
 418                 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 419         req.flags = rte_cpu_to_le_32(flags);
 420         req.enables =
 421         rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 422         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 423
 424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 425         HWRM_UNLOCK();
 426
 427         return rc;
 428 }
 429
 430 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 431 {
 432         int rc = 0;
 433         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 434         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 435         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 436
 437 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 438         if (ptp)
 439                 return 0;
 440
 441         HWRM_PREP(req, PORT_MAC_PTP_QCFG);
 442
 443         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 444
 445         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 446
 447         HWRM_CHECK_RESULT();
 448
 449         if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
 450                 return 0;
 451
 452         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 453         if (!ptp)
 454                 return -ENOMEM;
 455
 456         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 457                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 458         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 459                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 460         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 461                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 462         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 463                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 464         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 465                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 466         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 467                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 468         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 469                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 470         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 471                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 472         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 473                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 474
 475         ptp->bp = bp;
 476         bp->ptp_cfg = ptp;
 477
 478         return 0;
 479 }
 480
 481 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 482 {
 483         int rc = 0;
 484         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 485         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 486         uint16_t new_max_vfs;
 487         uint32_t flags;
 488         int i;
 489
 490         HWRM_PREP(req, FUNC_QCAPS);
 491
 492         req.fid = rte_cpu_to_le_16(0xffff);
 493
 494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 495
 496         HWRM_CHECK_RESULT();
 497
 498         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 499         flags = rte_le_to_cpu_32(resp->flags);
 500         if (BNXT_PF(bp)) {
 501                 bp->pf.port_id = resp->port_id;
 502                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 503                 new_max_vfs = bp->pdev->max_vfs;
 504                 if (new_max_vfs != bp->pf.max_vfs) {
 505                         if (bp->pf.vf_info)
 506                                 rte_free(bp->pf.vf_info);
 507                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 508                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 509                         bp->pf.max_vfs = new_max_vfs;
 510                         for (i = 0; i < new_max_vfs; i++) {
 511                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 512                                 bp->pf.vf_info[i].vlan_table =
 513                                         rte_zmalloc("VF VLAN table",
 514                                                     getpagesize(),
 515                                                     getpagesize());
 516                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 517                                         PMD_DRV_LOG(ERR,
 518                                         "Fail to alloc VLAN table for VF %d\n",
 519                                         i);
 520                                 else
 521                                         rte_mem_lock_page(
 522                                                 bp->pf.vf_info[i].vlan_table);
 523                                 bp->pf.vf_info[i].vlan_as_table =
 524                                         rte_zmalloc("VF VLAN AS table",
 525                                                     getpagesize(),
 526                                                     getpagesize());
 527                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 528                                         PMD_DRV_LOG(ERR,
 529                                         "Alloc VLAN AS table for VF %d fail\n",
 530                                         i);
 531                                 else
 532                                         rte_mem_lock_page(
 533                                                bp->pf.vf_info[i].vlan_as_table);
 534                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 535                         }
 536                 }
 537         }
 538
 539         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 540         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 541         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 542         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 543         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 544         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 545         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 546         /* TODO: For now, do not support VMDq/RFS on VFs. */
 547         if (BNXT_PF(bp)) {
 548                 if (bp->pf.max_vfs)
 549                         bp->max_vnics = 1;
 550                 else
 551                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 552         } else {
 553                 bp->max_vnics = 1;
 554         }
 555         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 556         if (BNXT_PF(bp)) {
 557                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 558                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 559                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 560                         PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
 561                         HWRM_UNLOCK();
 562                         bnxt_hwrm_ptp_qcfg(bp);
 563                 }
 564         }
 565
 566         HWRM_UNLOCK();
 567
 568         return rc;
 569 }
 570
 571 int bnxt_hwrm_func_reset(struct bnxt *bp)
 572 {
 573         int rc = 0;
 574         struct hwrm_func_reset_input req = {.req_type = 0 };
 575         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 576
 577         HWRM_PREP(req, FUNC_RESET);
 578
 579         req.enables = rte_cpu_to_le_32(0);
 580
 581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 582
 583         HWRM_CHECK_RESULT();
 584         HWRM_UNLOCK();
 585
 586         return rc;
 587 }
 588
 589 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 590 {
 591         int rc;
 592         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 593         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 594
 595         if (bp->flags & BNXT_FLAG_REGISTERED)
 596                 return 0;
 597
 598         HWRM_PREP(req, FUNC_DRV_RGTR);
 599         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 600                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 601         req.ver_maj = RTE_VER_YEAR;
 602         req.ver_min = RTE_VER_MONTH;
 603         req.ver_upd = RTE_VER_MINOR;
 604
 605         if (BNXT_PF(bp)) {
 606                 req.enables |= rte_cpu_to_le_32(
 607                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 608                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 609                        RTE_MIN(sizeof(req.vf_req_fwd),
 610                                sizeof(bp->pf.vf_req_fwd)));
 611         }
 612
 613         req.async_event_fwd[0] |=
 614                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 615                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 616                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 617         req.async_event_fwd[1] |=
 618                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 619                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 620
 621         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 622
 623         HWRM_CHECK_RESULT();
 624         HWRM_UNLOCK();
 625
 626         bp->flags |= BNXT_FLAG_REGISTERED;
 627
 628         return rc;
 629 }
 630
 631 int bnxt_hwrm_ver_get(struct bnxt *bp)
 632 {
 633         int rc = 0;
 634         struct hwrm_ver_get_input req = {.req_type = 0 };
 635         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 636         uint32_t my_version;
 637         uint32_t fw_version;
 638         uint16_t max_resp_len;
 639         char type[RTE_MEMZONE_NAMESIZE];
 640         uint32_t dev_caps_cfg;
 641
 642         bp->max_req_len = HWRM_MAX_REQ_LEN;
 643         HWRM_PREP(req, VER_GET);
 644
 645         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 646         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 647         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 648
 649         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 650
 651         HWRM_CHECK_RESULT();
 652
 653         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 654                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 655                 resp->hwrm_intf_upd,
 656                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 657         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 658                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 659         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 660                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 661
 662         my_version = HWRM_VERSION_MAJOR << 16;
 663         my_version |= HWRM_VERSION_MINOR << 8;
 664         my_version |= HWRM_VERSION_UPDATE;
 665
 666         fw_version = resp->hwrm_intf_maj << 16;
 667         fw_version |= resp->hwrm_intf_min << 8;
 668         fw_version |= resp->hwrm_intf_upd;
 669         bp->hwrm_spec_code = fw_version;
 670
 671         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 672                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 673                 rc = -EINVAL;
 674                 goto error;
 675         }
 676
 677         if (my_version != fw_version) {
 678                 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
 679                 if (my_version < fw_version) {
 680                         PMD_DRV_LOG(INFO,
 681                                 "Firmware API version is newer than driver.\n");
 682                         PMD_DRV_LOG(INFO,
 683                                 "The driver may be missing features.\n");
 684                 } else {
 685                         PMD_DRV_LOG(INFO,
 686                                 "Firmware API version is older than driver.\n");
 687                         PMD_DRV_LOG(INFO,
 688                                 "Not all driver features may be functional.\n");
 689                 }
 690         }
 691
 692         if (bp->max_req_len > resp->max_req_win_len) {
 693                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 694                 rc = -EINVAL;
 695         }
 696         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 697         max_resp_len = resp->max_resp_len;
 698         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 699
 700         if (bp->max_resp_len != max_resp_len) {
 701                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 702                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 703                         bp->pdev->addr.devid, bp->pdev->addr.function);
 704
 705                 rte_free(bp->hwrm_cmd_resp_addr);
 706
 707                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 708                 if (bp->hwrm_cmd_resp_addr == NULL) {
 709                         rc = -ENOMEM;
 710                         goto error;
 711                 }
 712                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 713                 bp->hwrm_cmd_resp_dma_addr =
 714                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 715                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 716                         PMD_DRV_LOG(ERR,
 717                         "Unable to map response buffer to physical memory.\n");
 718                         rc = -ENOMEM;
 719                         goto error;
 720                 }
 721                 bp->max_resp_len = max_resp_len;
 722         }
 723
 724         if ((dev_caps_cfg &
 725                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 726             (dev_caps_cfg &
 727              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 728                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 729
 730                 rte_free(bp->hwrm_short_cmd_req_addr);
 731
 732                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 733                                                         bp->max_req_len, 0);
 734                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 735                         rc = -ENOMEM;
 736                         goto error;
 737                 }
 738                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 739                 bp->hwrm_short_cmd_req_dma_addr =
 740                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 741                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 742                         rte_free(bp->hwrm_short_cmd_req_addr);
 743                         PMD_DRV_LOG(ERR,
 744                                 "Unable to map buffer to physical memory.\n");
 745                         rc = -ENOMEM;
 746                         goto error;
 747                 }
 748
 749                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 750         }
 751
 752 error:
 753         HWRM_UNLOCK();
 754         return rc;
 755 }
 756
 757 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 758 {
 759         int rc;
 760         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 761         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 762
 763         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 764                 return 0;
 765
 766         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 767         req.flags = flags;
 768
 769         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 770
 771         HWRM_CHECK_RESULT();
 772         HWRM_UNLOCK();
 773
 774         bp->flags &= ~BNXT_FLAG_REGISTERED;
 775
 776         return rc;
 777 }
 778
 779 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 780 {
 781         int rc = 0;
 782         struct hwrm_port_phy_cfg_input req = {0};
 783         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 784         uint32_t enables = 0;
 785
 786         HWRM_PREP(req, PORT_PHY_CFG);
 787
 788         if (conf->link_up) {
 789                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 790                 if (bp->link_info.auto_mode && conf->link_speed) {
 791                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 792                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 793                 }
 794
 795                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 796                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 797                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 798                 /*
 799                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 800                  * any auto mode, even "none".
 801                  */
 802                 if (!conf->link_speed) {
 803                         /* No speeds specified. Enable AutoNeg - all speeds */
 804                         req.auto_mode =
 805                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 806                 }
 807                 /* AutoNeg - Advertise speeds specified. */
 808                 if (conf->auto_link_speed_mask &&
 809                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 810                         req.auto_mode =
 811                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 812                         req.auto_link_speed_mask =
 813                                 conf->auto_link_speed_mask;
 814                         enables |=
 815                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 816                 }
 817
 818                 req.auto_duplex = conf->duplex;
 819                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 820                 req.auto_pause = conf->auto_pause;
 821                 req.force_pause = conf->force_pause;
 822                 /* Set force_pause if there is no auto or if there is a force */
 823                 if (req.auto_pause && !req.force_pause)
 824                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 825                 else
 826                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 827
 828                 req.enables = rte_cpu_to_le_32(enables);
 829         } else {
 830                 req.flags =
 831                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 832                 PMD_DRV_LOG(INFO, "Force Link Down\n");
 833         }
 834
 835         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 836
 837         HWRM_CHECK_RESULT();
 838         HWRM_UNLOCK();
 839
 840         return rc;
 841 }
 842
 843 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 844                                    struct bnxt_link_info *link_info)
 845 {
 846         int rc = 0;
 847         struct hwrm_port_phy_qcfg_input req = {0};
 848         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 849
 850         HWRM_PREP(req, PORT_PHY_QCFG);
 851
 852         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 853
 854         HWRM_CHECK_RESULT();
 855
 856         link_info->phy_link_status = resp->link;
 857         link_info->link_up =
 858                 (link_info->phy_link_status ==
 859                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 860         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 861         link_info->duplex = resp->duplex_cfg;
 862         link_info->pause = resp->pause;
 863         link_info->auto_pause = resp->auto_pause;
 864         link_info->force_pause = resp->force_pause;
 865         link_info->auto_mode = resp->auto_mode;
 866         link_info->phy_type = resp->phy_type;
 867         link_info->media_type = resp->media_type;
 868
 869         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 870         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 871         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 872         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
 873         link_info->phy_ver[0] = resp->phy_maj;
 874         link_info->phy_ver[1] = resp->phy_min;
 875         link_info->phy_ver[2] = resp->phy_bld;
 876
 877         HWRM_UNLOCK();
 878
 879         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
 880         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
 881         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
 882         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
 883         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
 884                     link_info->auto_link_speed_mask);
 885         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
 886                     link_info->force_link_speed);
 887
 888         return rc;
 889 }
 890
 891 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 892 {
 893         int rc = 0;
 894         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 895         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 896         int i;
 897
 898         HWRM_PREP(req, QUEUE_QPORTCFG);
 899
 900         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
 901         /* HWRM Version >= 1.9.1 */
 902         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
 903                 req.drv_qmap_cap =
 904                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
 905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 906
 907         HWRM_CHECK_RESULT();
 908
 909 #define GET_QUEUE_INFO(x) \
 910         bp->cos_queue[x].id = resp->queue_id##x; \
 911         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 912
 913         GET_QUEUE_INFO(0);
 914         GET_QUEUE_INFO(1);
 915         GET_QUEUE_INFO(2);
 916         GET_QUEUE_INFO(3);
 917         GET_QUEUE_INFO(4);
 918         GET_QUEUE_INFO(5);
 919         GET_QUEUE_INFO(6);
 920         GET_QUEUE_INFO(7);
 921
 922         HWRM_UNLOCK();
 923
 924         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
 925                 bp->tx_cosq_id = bp->cos_queue[0].id;
 926         } else {
 927                 /* iterate and find the COSq profile to use for Tx */
 928                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 929                         if (bp->cos_queue[i].profile ==
 930                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
 931                                 bp->tx_cosq_id = bp->cos_queue[i].id;
 932                                 break;
 933                         }
 934                 }
 935         }
 936         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
 937
 938         return rc;
 939 }
 940
 941 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 942                          struct bnxt_ring *ring,
 943                          uint32_t ring_type, uint32_t map_index,
 944                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 945 {
 946         int rc = 0;
 947         uint32_t enables = 0;
 948         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 949         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 950
 951         HWRM_PREP(req, RING_ALLOC);
 952
 953         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 954         req.fbo = rte_cpu_to_le_32(0);
 955         /* Association of ring index with doorbell index */
 956         req.logical_id = rte_cpu_to_le_16(map_index);
 957         req.length = rte_cpu_to_le_32(ring->ring_size);
 958
 959         switch (ring_type) {
 960         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 961                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
 962                 /* FALLTHROUGH */
 963         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 964                 req.ring_type = ring_type;
 965                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 966                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 967                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 968                         enables |=
 969                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 970                 break;
 971         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 972                 req.ring_type = ring_type;
 973                 /*
 974                  * TODO: Some HWRM versions crash with
 975                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 976                  */
 977                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 978                 break;
 979         default:
 980                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
 981                         ring_type);
 982                 HWRM_UNLOCK();
 983                 return -1;
 984         }
 985         req.enables = rte_cpu_to_le_32(enables);
 986
 987         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 988
 989         if (rc || resp->error_code) {
 990                 if (rc == 0 && resp->error_code)
 991                         rc = rte_le_to_cpu_16(resp->error_code);
 992                 switch (ring_type) {
 993                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 994                         PMD_DRV_LOG(ERR,
 995                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 996                         HWRM_UNLOCK();
 997                         return rc;
 998                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 999                         PMD_DRV_LOG(ERR,
1000                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1001                         HWRM_UNLOCK();
1002                         return rc;
1003                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1004                         PMD_DRV_LOG(ERR,
1005                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1006                         HWRM_UNLOCK();
1007                         return rc;
1008                 default:
1009                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1010                         HWRM_UNLOCK();
1011                         return rc;
1012                 }
1013         }
1014
1015         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1016         HWRM_UNLOCK();
1017         return rc;
1018 }
1019
1020 int bnxt_hwrm_ring_free(struct bnxt *bp,
1021                         struct bnxt_ring *ring, uint32_t ring_type)
1022 {
1023         int rc;
1024         struct hwrm_ring_free_input req = {.req_type = 0 };
1025         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1026
1027         HWRM_PREP(req, RING_FREE);
1028
1029         req.ring_type = ring_type;
1030         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1031
1032         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1033
1034         if (rc || resp->error_code) {
1035                 if (rc == 0 && resp->error_code)
1036                         rc = rte_le_to_cpu_16(resp->error_code);
1037                 HWRM_UNLOCK();
1038
1039                 switch (ring_type) {
1040                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1041                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1042                                 rc);
1043                         return rc;
1044                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1045                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1046                                 rc);
1047                         return rc;
1048                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1049                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1050                                 rc);
1051                         return rc;
1052                 default:
1053                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1054                         return rc;
1055                 }
1056         }
1057         HWRM_UNLOCK();
1058         return 0;
1059 }
1060
1061 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1062 {
1063         int rc = 0;
1064         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1065         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1066
1067         HWRM_PREP(req, RING_GRP_ALLOC);
1068
1069         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1070         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1071         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1072         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1073
1074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1075
1076         HWRM_CHECK_RESULT();
1077
1078         bp->grp_info[idx].fw_grp_id =
1079             rte_le_to_cpu_16(resp->ring_group_id);
1080
1081         HWRM_UNLOCK();
1082
1083         return rc;
1084 }
1085
1086 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1087 {
1088         int rc;
1089         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1090         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1091
1092         HWRM_PREP(req, RING_GRP_FREE);
1093
1094         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1095
1096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1097
1098         HWRM_CHECK_RESULT();
1099         HWRM_UNLOCK();
1100
1101         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1102         return rc;
1103 }
1104
1105 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1106 {
1107         int rc = 0;
1108         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1109         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1110
1111         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1112                 return rc;
1113
1114         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1115
1116         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1117
1118         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1119
1120         HWRM_CHECK_RESULT();
1121         HWRM_UNLOCK();
1122
1123         return rc;
1124 }
1125
1126 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1127                                 unsigned int idx __rte_unused)
1128 {
1129         int rc;
1130         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1131         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1132
1133         HWRM_PREP(req, STAT_CTX_ALLOC);
1134
1135         req.update_period_ms = rte_cpu_to_le_32(0);
1136
1137         req.stats_dma_addr =
1138             rte_cpu_to_le_64(cpr->hw_stats_map);
1139
1140         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1141
1142         HWRM_CHECK_RESULT();
1143
1144         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1145
1146         HWRM_UNLOCK();
1147
1148         return rc;
1149 }
1150
1151 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1152                                 unsigned int idx __rte_unused)
1153 {
1154         int rc;
1155         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1156         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1157
1158         HWRM_PREP(req, STAT_CTX_FREE);
1159
1160         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1161
1162         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1163
1164         HWRM_CHECK_RESULT();
1165         HWRM_UNLOCK();
1166
1167         return rc;
1168 }
1169
1170 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1171 {
1172         int rc = 0, i, j;
1173         struct hwrm_vnic_alloc_input req = { 0 };
1174         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1175
1176         /* map ring groups to this vnic */
1177         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1178                 vnic->start_grp_id, vnic->end_grp_id);
1179         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1180                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1181         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1182         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1183         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1184         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1185         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1186                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1187         HWRM_PREP(req, VNIC_ALLOC);
1188
1189         if (vnic->func_default)
1190                 req.flags =
1191                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1192         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1193
1194         HWRM_CHECK_RESULT();
1195
1196         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1197         HWRM_UNLOCK();
1198         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1199         return rc;
1200 }
1201
1202 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1203                                         struct bnxt_vnic_info *vnic,
1204                                         struct bnxt_plcmodes_cfg *pmode)
1205 {
1206         int rc = 0;
1207         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1208         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1209
1210         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1211
1212         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1213
1214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1215
1216         HWRM_CHECK_RESULT();
1217
1218         pmode->flags = rte_le_to_cpu_32(resp->flags);
1219         /* dflt_vnic bit doesn't exist in the _cfg command */
1220         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1221         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1222         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1223         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1224
1225         HWRM_UNLOCK();
1226
1227         return rc;
1228 }
1229
1230 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1231                                        struct bnxt_vnic_info *vnic,
1232                                        struct bnxt_plcmodes_cfg *pmode)
1233 {
1234         int rc = 0;
1235         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1236         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1237
1238         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1239
1240         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1241         req.flags = rte_cpu_to_le_32(pmode->flags);
1242         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1243         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1244         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1245         req.enables = rte_cpu_to_le_32(
1246             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1247             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1248             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1249         );
1250
1251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1252
1253         HWRM_CHECK_RESULT();
1254         HWRM_UNLOCK();
1255
1256         return rc;
1257 }
1258
1259 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1260 {
1261         int rc = 0;
1262         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1263         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1264         uint32_t ctx_enable_flag = 0;
1265         struct bnxt_plcmodes_cfg pmodes;
1266
1267         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1268                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1269                 return rc;
1270         }
1271
1272         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1273         if (rc)
1274                 return rc;
1275
1276         HWRM_PREP(req, VNIC_CFG);
1277
1278         /* Only RSS support for now TBD: COS & LB */
1279         req.enables =
1280             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1281         if (vnic->lb_rule != 0xffff)
1282                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1283         if (vnic->cos_rule != 0xffff)
1284                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1285         if (vnic->rss_rule != 0xffff) {
1286                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1287                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1288         }
1289         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1290         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1291         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1292         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1293         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1294         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1295         req.mru = rte_cpu_to_le_16(vnic->mru);
1296         if (vnic->func_default)
1297                 req.flags |=
1298                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1299         if (vnic->vlan_strip)
1300                 req.flags |=
1301                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1302         if (vnic->bd_stall)
1303                 req.flags |=
1304                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1305         if (vnic->roce_dual)
1306                 req.flags |= rte_cpu_to_le_32(
1307                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1308         if (vnic->roce_only)
1309                 req.flags |= rte_cpu_to_le_32(
1310                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1311         if (vnic->rss_dflt_cr)
1312                 req.flags |= rte_cpu_to_le_32(
1313                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1314
1315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1316
1317         HWRM_CHECK_RESULT();
1318         HWRM_UNLOCK();
1319
1320         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1321
1322         return rc;
1323 }
1324
1325 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1326                 int16_t fw_vf_id)
1327 {
1328         int rc = 0;
1329         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1330         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1331
1332         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1333                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1334                 return rc;
1335         }
1336         HWRM_PREP(req, VNIC_QCFG);
1337
1338         req.enables =
1339                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1340         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1341         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1342
1343         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1344
1345         HWRM_CHECK_RESULT();
1346
1347         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1348         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1349         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1350         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1351         vnic->mru = rte_le_to_cpu_16(resp->mru);
1352         vnic->func_default = rte_le_to_cpu_32(
1353                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1354         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1355                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1356         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1357                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1358         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1359                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1360         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1361                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1362         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1363                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1364
1365         HWRM_UNLOCK();
1366
1367         return rc;
1368 }
1369
1370 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1371 {
1372         int rc = 0;
1373         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1374         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1375                                                 bp->hwrm_cmd_resp_addr;
1376
1377         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1378
1379         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1380
1381         HWRM_CHECK_RESULT();
1382
1383         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1384         HWRM_UNLOCK();
1385         PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1386
1387         return rc;
1388 }
1389
1390 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1391 {
1392         int rc = 0;
1393         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1394         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1395                                                 bp->hwrm_cmd_resp_addr;
1396
1397         if (vnic->rss_rule == 0xffff) {
1398                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1399                 return rc;
1400         }
1401         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1402
1403         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1404
1405         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1406
1407         HWRM_CHECK_RESULT();
1408         HWRM_UNLOCK();
1409
1410         vnic->rss_rule = INVALID_HW_RING_ID;
1411
1412         return rc;
1413 }
1414
1415 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1416 {
1417         int rc = 0;
1418         struct hwrm_vnic_free_input req = {.req_type = 0 };
1419         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1420
1421         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1422                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1423                 return rc;
1424         }
1425
1426         HWRM_PREP(req, VNIC_FREE);
1427
1428         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1429
1430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1431
1432         HWRM_CHECK_RESULT();
1433         HWRM_UNLOCK();
1434
1435         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1436         return rc;
1437 }
1438
1439 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1440                            struct bnxt_vnic_info *vnic)
1441 {
1442         int rc = 0;
1443         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1444         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1445
1446         HWRM_PREP(req, VNIC_RSS_CFG);
1447
1448         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1449
1450         req.ring_grp_tbl_addr =
1451             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1452         req.hash_key_tbl_addr =
1453             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1454         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1455
1456         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1457
1458         HWRM_CHECK_RESULT();
1459         HWRM_UNLOCK();
1460
1461         return rc;
1462 }
1463
1464 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1465                         struct bnxt_vnic_info *vnic)
1466 {
1467         int rc = 0;
1468         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1469         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1470         uint16_t size;
1471
1472         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1473
1474         req.flags = rte_cpu_to_le_32(
1475                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1476
1477         req.enables = rte_cpu_to_le_32(
1478                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1479
1480         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1481         size -= RTE_PKTMBUF_HEADROOM;
1482
1483         req.jumbo_thresh = rte_cpu_to_le_16(size);
1484         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1485
1486         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1487
1488         HWRM_CHECK_RESULT();
1489         HWRM_UNLOCK();
1490
1491         return rc;
1492 }
1493
1494 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1495                         struct bnxt_vnic_info *vnic, bool enable)
1496 {
1497         int rc = 0;
1498         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1499         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1500
1501         HWRM_PREP(req, VNIC_TPA_CFG);
1502
1503         if (enable) {
1504                 req.enables = rte_cpu_to_le_32(
1505                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1506                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1507                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1508                 req.flags = rte_cpu_to_le_32(
1509                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1510                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1511                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1512                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1513                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1514                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1515                 req.max_agg_segs = rte_cpu_to_le_16(5);
1516                 req.max_aggs =
1517                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1518                 req.min_agg_len = rte_cpu_to_le_32(512);
1519         }
1520         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1521
1522         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1523
1524         HWRM_CHECK_RESULT();
1525         HWRM_UNLOCK();
1526
1527         return rc;
1528 }
1529
1530 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1531 {
1532         struct hwrm_func_cfg_input req = {0};
1533         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1534         int rc;
1535
1536         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1537         req.enables = rte_cpu_to_le_32(
1538                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1539         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1540         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1541
1542         HWRM_PREP(req, FUNC_CFG);
1543
1544         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1545         HWRM_CHECK_RESULT();
1546         HWRM_UNLOCK();
1547
1548         bp->pf.vf_info[vf].random_mac = false;
1549
1550         return rc;
1551 }
1552
1553 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1554                                   uint64_t *dropped)
1555 {
1556         int rc = 0;
1557         struct hwrm_func_qstats_input req = {.req_type = 0};
1558         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1559
1560         HWRM_PREP(req, FUNC_QSTATS);
1561
1562         req.fid = rte_cpu_to_le_16(fid);
1563
1564         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1565
1566         HWRM_CHECK_RESULT();
1567
1568         if (dropped)
1569                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1570
1571         HWRM_UNLOCK();
1572
1573         return rc;
1574 }
1575
1576 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1577                           struct rte_eth_stats *stats)
1578 {
1579         int rc = 0;
1580         struct hwrm_func_qstats_input req = {.req_type = 0};
1581         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1582
1583         HWRM_PREP(req, FUNC_QSTATS);
1584
1585         req.fid = rte_cpu_to_le_16(fid);
1586
1587         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1588
1589         HWRM_CHECK_RESULT();
1590
1591         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1592         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1593         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1594         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1595         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1596         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1597
1598         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1599         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1600         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1601         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1602         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1603         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1604
1605         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1606         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1607
1608         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1609
1610         HWRM_UNLOCK();
1611
1612         return rc;
1613 }
1614
1615 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1616 {
1617         int rc = 0;
1618         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1619         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1620
1621         HWRM_PREP(req, FUNC_CLR_STATS);
1622
1623         req.fid = rte_cpu_to_le_16(fid);
1624
1625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1626
1627         HWRM_CHECK_RESULT();
1628         HWRM_UNLOCK();
1629
1630         return rc;
1631 }
1632
1633 /*
1634  * HWRM utility functions
1635  */
1636
1637 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1638 {
1639         unsigned int i;
1640         int rc = 0;
1641
1642         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1643                 struct bnxt_tx_queue *txq;
1644                 struct bnxt_rx_queue *rxq;
1645                 struct bnxt_cp_ring_info *cpr;
1646
1647                 if (i >= bp->rx_cp_nr_rings) {
1648                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1649                         cpr = txq->cp_ring;
1650                 } else {
1651                         rxq = bp->rx_queues[i];
1652                         cpr = rxq->cp_ring;
1653                 }
1654
1655                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1656                 if (rc)
1657                         return rc;
1658         }
1659         return 0;
1660 }
1661
1662 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1663 {
1664         int rc;
1665         unsigned int i;
1666         struct bnxt_cp_ring_info *cpr;
1667
1668         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1669
1670                 if (i >= bp->rx_cp_nr_rings) {
1671                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1672                 } else {
1673                         cpr = bp->rx_queues[i]->cp_ring;
1674                         bp->grp_info[i].fw_stats_ctx = -1;
1675                 }
1676                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1677                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1678                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1679                         if (rc)
1680                                 return rc;
1681                 }
1682         }
1683         return 0;
1684 }
1685
1686 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1687 {
1688         unsigned int i;
1689         int rc = 0;
1690
1691         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1692                 struct bnxt_tx_queue *txq;
1693                 struct bnxt_rx_queue *rxq;
1694                 struct bnxt_cp_ring_info *cpr;
1695
1696                 if (i >= bp->rx_cp_nr_rings) {
1697                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1698                         cpr = txq->cp_ring;
1699                 } else {
1700                         rxq = bp->rx_queues[i];
1701                         cpr = rxq->cp_ring;
1702                 }
1703
1704                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1705
1706                 if (rc)
1707                         return rc;
1708         }
1709         return rc;
1710 }
1711
1712 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1713 {
1714         uint16_t idx;
1715         uint32_t rc = 0;
1716
1717         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1718
1719                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1720                         continue;
1721
1722                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1723
1724                 if (rc)
1725                         return rc;
1726         }
1727         return rc;
1728 }
1729
1730 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1731                                 unsigned int idx __rte_unused)
1732 {
1733         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1734
1735         bnxt_hwrm_ring_free(bp, cp_ring,
1736                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1737         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1738         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1739                         sizeof(*cpr->cp_desc_ring));
1740         cpr->cp_raw_cons = 0;
1741 }
1742
1743 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1744 {
1745         unsigned int i;
1746         int rc = 0;
1747
1748         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1749                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1750                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1751                 struct bnxt_ring *ring = txr->tx_ring_struct;
1752                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1753                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1754
1755                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1756                         bnxt_hwrm_ring_free(bp, ring,
1757                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1758                         ring->fw_ring_id = INVALID_HW_RING_ID;
1759                         memset(txr->tx_desc_ring, 0,
1760                                         txr->tx_ring_struct->ring_size *
1761                                         sizeof(*txr->tx_desc_ring));
1762                         memset(txr->tx_buf_ring, 0,
1763                                         txr->tx_ring_struct->ring_size *
1764                                         sizeof(*txr->tx_buf_ring));
1765                         txr->tx_prod = 0;
1766                         txr->tx_cons = 0;
1767                 }
1768                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1769                         bnxt_free_cp_ring(bp, cpr, idx);
1770                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1771                 }
1772         }
1773
1774         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1775                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1776                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1777                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1778                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1779                 unsigned int idx = i + 1;
1780
1781                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1782                         bnxt_hwrm_ring_free(bp, ring,
1783                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1784                         ring->fw_ring_id = INVALID_HW_RING_ID;
1785                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1786                         memset(rxr->rx_desc_ring, 0,
1787                                         rxr->rx_ring_struct->ring_size *
1788                                         sizeof(*rxr->rx_desc_ring));
1789                         memset(rxr->rx_buf_ring, 0,
1790                                         rxr->rx_ring_struct->ring_size *
1791                                         sizeof(*rxr->rx_buf_ring));
1792                         rxr->rx_prod = 0;
1793                 }
1794                 ring = rxr->ag_ring_struct;
1795                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1796                         bnxt_hwrm_ring_free(bp, ring,
1797                                             HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1798                         ring->fw_ring_id = INVALID_HW_RING_ID;
1799                         memset(rxr->ag_buf_ring, 0,
1800                                rxr->ag_ring_struct->ring_size *
1801                                sizeof(*rxr->ag_buf_ring));
1802                         rxr->ag_prod = 0;
1803                         bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1804                 }
1805                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1806                         bnxt_free_cp_ring(bp, cpr, idx);
1807                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1808                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1809                 }
1810         }
1811
1812         /* Default completion ring */
1813         {
1814                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1815
1816                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1817                         bnxt_free_cp_ring(bp, cpr, 0);
1818                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1819                 }
1820         }
1821
1822         return rc;
1823 }
1824
1825 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1826 {
1827         uint16_t i;
1828         uint32_t rc = 0;
1829
1830         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1831                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1832                 if (rc)
1833                         return rc;
1834         }
1835         return rc;
1836 }
1837
1838 void bnxt_free_hwrm_resources(struct bnxt *bp)
1839 {
1840         /* Release memzone */
1841         rte_free(bp->hwrm_cmd_resp_addr);
1842         rte_free(bp->hwrm_short_cmd_req_addr);
1843         bp->hwrm_cmd_resp_addr = NULL;
1844         bp->hwrm_short_cmd_req_addr = NULL;
1845         bp->hwrm_cmd_resp_dma_addr = 0;
1846         bp->hwrm_short_cmd_req_dma_addr = 0;
1847 }
1848
1849 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1850 {
1851         struct rte_pci_device *pdev = bp->pdev;
1852         char type[RTE_MEMZONE_NAMESIZE];
1853
1854         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1855                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1856         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1857         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1858         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1859         if (bp->hwrm_cmd_resp_addr == NULL)
1860                 return -ENOMEM;
1861         bp->hwrm_cmd_resp_dma_addr =
1862                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1863         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1864                 PMD_DRV_LOG(ERR,
1865                         "unable to map response address to physical memory\n");
1866                 return -ENOMEM;
1867         }
1868         rte_spinlock_init(&bp->hwrm_lock);
1869
1870         return 0;
1871 }
1872
1873 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1874 {
1875         struct bnxt_filter_info *filter;
1876         int rc = 0;
1877
1878         STAILQ_FOREACH(filter, &vnic->filter, next) {
1879                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1880                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1881                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1882                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1883                 else
1884                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1885                 //if (rc)
1886                         //break;
1887         }
1888         return rc;
1889 }
1890
1891 static int
1892 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1893 {
1894         struct bnxt_filter_info *filter;
1895         struct rte_flow *flow;
1896         int rc = 0;
1897
1898         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1899                 filter = flow->filter;
1900                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1901                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1902                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1903                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1904                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1905                 else
1906                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1907
1908                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1909                 rte_free(flow);
1910                 //if (rc)
1911                         //break;
1912         }
1913         return rc;
1914 }
1915
1916 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1917 {
1918         struct bnxt_filter_info *filter;
1919         int rc = 0;
1920
1921         STAILQ_FOREACH(filter, &vnic->filter, next) {
1922                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1923                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1924                                                      filter);
1925                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1926                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1927                                                          filter);
1928                 else
1929                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1930                                                      filter);
1931                 if (rc)
1932                         break;
1933         }
1934         return rc;
1935 }
1936
1937 void bnxt_free_tunnel_ports(struct bnxt *bp)
1938 {
1939         if (bp->vxlan_port_cnt)
1940                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1941                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1942         bp->vxlan_port = 0;
1943         if (bp->geneve_port_cnt)
1944                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1945                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1946         bp->geneve_port = 0;
1947 }
1948
1949 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1950 {
1951         int i;
1952
1953         if (bp->vnic_info == NULL)
1954                 return;
1955
1956         /*
1957          * Cleanup VNICs in reverse order, to make sure the L2 filter
1958          * from vnic0 is last to be cleaned up.
1959          */
1960         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1961                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1962
1963                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1964
1965                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1966
1967                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1968
1969                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1970
1971                 bnxt_hwrm_vnic_free(bp, vnic);
1972         }
1973         /* Ring resources */
1974         bnxt_free_all_hwrm_rings(bp);
1975         bnxt_free_all_hwrm_ring_grps(bp);
1976         bnxt_free_all_hwrm_stat_ctxs(bp);
1977         bnxt_free_tunnel_ports(bp);
1978 }
1979
1980 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1981 {
1982         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1983
1984         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1985                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1986
1987         switch (conf_link_speed) {
1988         case ETH_LINK_SPEED_10M_HD:
1989         case ETH_LINK_SPEED_100M_HD:
1990                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1991         }
1992         return hw_link_duplex;
1993 }
1994
1995 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1996 {
1997         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1998 }
1999
2000 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2001 {
2002         uint16_t eth_link_speed = 0;
2003
2004         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2005                 return ETH_LINK_SPEED_AUTONEG;
2006
2007         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2008         case ETH_LINK_SPEED_100M:
2009         case ETH_LINK_SPEED_100M_HD:
2010                 eth_link_speed =
2011                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2012                 break;
2013         case ETH_LINK_SPEED_1G:
2014                 eth_link_speed =
2015                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2016                 break;
2017         case ETH_LINK_SPEED_2_5G:
2018                 eth_link_speed =
2019                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2020                 break;
2021         case ETH_LINK_SPEED_10G:
2022                 eth_link_speed =
2023                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2024                 break;
2025         case ETH_LINK_SPEED_20G:
2026                 eth_link_speed =
2027                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2028                 break;
2029         case ETH_LINK_SPEED_25G:
2030                 eth_link_speed =
2031                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2032                 break;
2033         case ETH_LINK_SPEED_40G:
2034                 eth_link_speed =
2035                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2036                 break;
2037         case ETH_LINK_SPEED_50G:
2038                 eth_link_speed =
2039                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2040                 break;
2041         case ETH_LINK_SPEED_100G:
2042                 eth_link_speed =
2043                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2044                 break;
2045         default:
2046                 PMD_DRV_LOG(ERR,
2047                         "Unsupported link speed %d; default to AUTO\n",
2048                         conf_link_speed);
2049                 break;
2050         }
2051         return eth_link_speed;
2052 }
2053
2054 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2055                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2056                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2057                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2058
2059 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2060 {
2061         uint32_t one_speed;
2062
2063         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2064                 return 0;
2065
2066         if (link_speed & ETH_LINK_SPEED_FIXED) {
2067                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2068
2069                 if (one_speed & (one_speed - 1)) {
2070                         PMD_DRV_LOG(ERR,
2071                                 "Invalid advertised speeds (%u) for port %u\n",
2072                                 link_speed, port_id);
2073                         return -EINVAL;
2074                 }
2075                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2076                         PMD_DRV_LOG(ERR,
2077                                 "Unsupported advertised speed (%u) for port %u\n",
2078                                 link_speed, port_id);
2079                         return -EINVAL;
2080                 }
2081         } else {
2082                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2083                         PMD_DRV_LOG(ERR,
2084                                 "Unsupported advertised speeds (%u) for port %u\n",
2085                                 link_speed, port_id);
2086                         return -EINVAL;
2087                 }
2088         }
2089         return 0;
2090 }
2091
2092 static uint16_t
2093 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2094 {
2095         uint16_t ret = 0;
2096
2097         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2098                 if (bp->link_info.support_speeds)
2099                         return bp->link_info.support_speeds;
2100                 link_speed = BNXT_SUPPORTED_SPEEDS;
2101         }
2102
2103         if (link_speed & ETH_LINK_SPEED_100M)
2104                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2105         if (link_speed & ETH_LINK_SPEED_100M_HD)
2106                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2107         if (link_speed & ETH_LINK_SPEED_1G)
2108                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2109         if (link_speed & ETH_LINK_SPEED_2_5G)
2110                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2111         if (link_speed & ETH_LINK_SPEED_10G)
2112                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2113         if (link_speed & ETH_LINK_SPEED_20G)
2114                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2115         if (link_speed & ETH_LINK_SPEED_25G)
2116                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2117         if (link_speed & ETH_LINK_SPEED_40G)
2118                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2119         if (link_speed & ETH_LINK_SPEED_50G)
2120                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2121         if (link_speed & ETH_LINK_SPEED_100G)
2122                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2123         return ret;
2124 }
2125
2126 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2127 {
2128         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2129
2130         switch (hw_link_speed) {
2131         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2132                 eth_link_speed = ETH_SPEED_NUM_100M;
2133                 break;
2134         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2135                 eth_link_speed = ETH_SPEED_NUM_1G;
2136                 break;
2137         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2138                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2139                 break;
2140         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2141                 eth_link_speed = ETH_SPEED_NUM_10G;
2142                 break;
2143         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2144                 eth_link_speed = ETH_SPEED_NUM_20G;
2145                 break;
2146         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2147                 eth_link_speed = ETH_SPEED_NUM_25G;
2148                 break;
2149         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2150                 eth_link_speed = ETH_SPEED_NUM_40G;
2151                 break;
2152         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2153                 eth_link_speed = ETH_SPEED_NUM_50G;
2154                 break;
2155         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2156                 eth_link_speed = ETH_SPEED_NUM_100G;
2157                 break;
2158         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2159         default:
2160                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2161                         hw_link_speed);
2162                 break;
2163         }
2164         return eth_link_speed;
2165 }
2166
2167 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2168 {
2169         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2170
2171         switch (hw_link_duplex) {
2172         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2173         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2174                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2175                 break;
2176         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2177                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2178                 break;
2179         default:
2180                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2181                         hw_link_duplex);
2182                 break;
2183         }
2184         return eth_link_duplex;
2185 }
2186
2187 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2188 {
2189         int rc = 0;
2190         struct bnxt_link_info *link_info = &bp->link_info;
2191
2192         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2193         if (rc) {
2194                 PMD_DRV_LOG(ERR,
2195                         "Get link config failed with rc %d\n", rc);
2196                 goto exit;
2197         }
2198         if (link_info->link_speed)
2199                 link->link_speed =
2200                         bnxt_parse_hw_link_speed(link_info->link_speed);
2201         else
2202                 link->link_speed = ETH_SPEED_NUM_NONE;
2203         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2204         link->link_status = link_info->link_up;
2205         link->link_autoneg = link_info->auto_mode ==
2206                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2207                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2208 exit:
2209         return rc;
2210 }
2211
2212 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2213 {
2214         int rc = 0;
2215         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2216         struct bnxt_link_info link_req;
2217         uint16_t speed, autoneg;
2218
2219         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2220                 return 0;
2221
2222         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2223                         bp->eth_dev->data->port_id);
2224         if (rc)
2225                 goto error;
2226
2227         memset(&link_req, 0, sizeof(link_req));
2228         link_req.link_up = link_up;
2229         if (!link_up)
2230                 goto port_phy_cfg;
2231
2232         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2233         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2234         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2235         /* Autoneg can be done only when the FW allows */
2236         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2237                                 bp->link_info.force_link_speed)) {
2238                 link_req.phy_flags |=
2239                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2240                 link_req.auto_link_speed_mask =
2241                         bnxt_parse_eth_link_speed_mask(bp,
2242                                                        dev_conf->link_speeds);
2243         } else {
2244                 if (bp->link_info.phy_type ==
2245                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2246                     bp->link_info.phy_type ==
2247                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2248                     bp->link_info.media_type ==
2249                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2250                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2251                         return -EINVAL;
2252                 }
2253
2254                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2255                 /* If user wants a particular speed try that first. */
2256                 if (speed)
2257                         link_req.link_speed = speed;
2258                 else if (bp->link_info.force_link_speed)
2259                         link_req.link_speed = bp->link_info.force_link_speed;
2260                 else
2261                         link_req.link_speed = bp->link_info.auto_link_speed;
2262         }
2263         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2264         link_req.auto_pause = bp->link_info.auto_pause;
2265         link_req.force_pause = bp->link_info.force_pause;
2266
2267 port_phy_cfg:
2268         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2269         if (rc) {
2270                 PMD_DRV_LOG(ERR,
2271                         "Set link config failed with rc %d\n", rc);
2272         }
2273
2274 error:
2275         return rc;
2276 }
2277
2278 /* JIRA 22088 */
2279 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2280 {
2281         struct hwrm_func_qcfg_input req = {0};
2282         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2283         uint16_t flags;
2284         int rc = 0;
2285
2286         HWRM_PREP(req, FUNC_QCFG);
2287         req.fid = rte_cpu_to_le_16(0xffff);
2288
2289         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2290
2291         HWRM_CHECK_RESULT();
2292
2293         /* Hard Coded.. 0xfff VLAN ID mask */
2294         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2295         flags = rte_le_to_cpu_16(resp->flags);
2296         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2297                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2298
2299         switch (resp->port_partition_type) {
2300         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2301         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2302         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2303                 bp->port_partition_type = resp->port_partition_type;
2304                 break;
2305         default:
2306                 bp->port_partition_type = 0;
2307                 break;
2308         }
2309
2310         HWRM_UNLOCK();
2311
2312         return rc;
2313 }
2314
2315 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2316                                    struct hwrm_func_qcaps_output *qcaps)
2317 {
2318         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2319         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2320                sizeof(qcaps->mac_address));
2321         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2322         qcaps->max_rx_rings = fcfg->num_rx_rings;
2323         qcaps->max_tx_rings = fcfg->num_tx_rings;
2324         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2325         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2326         qcaps->max_vfs = 0;
2327         qcaps->first_vf_id = 0;
2328         qcaps->max_vnics = fcfg->num_vnics;
2329         qcaps->max_decap_records = 0;
2330         qcaps->max_encap_records = 0;
2331         qcaps->max_tx_wm_flows = 0;
2332         qcaps->max_tx_em_flows = 0;
2333         qcaps->max_rx_wm_flows = 0;
2334         qcaps->max_rx_em_flows = 0;
2335         qcaps->max_flow_id = 0;
2336         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2337         qcaps->max_sp_tx_rings = 0;
2338         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2339 }
2340
2341 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2342 {
2343         struct hwrm_func_cfg_input req = {0};
2344         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2345         int rc;
2346
2347         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2348                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2349                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2350                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2351                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2352                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2353                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2354                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2355                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2356                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2357         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2358         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2359         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2360                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2361         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2362         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2363         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2364         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2365         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2366         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2367         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2368         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2369         req.fid = rte_cpu_to_le_16(0xffff);
2370
2371         HWRM_PREP(req, FUNC_CFG);
2372
2373         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2374
2375         HWRM_CHECK_RESULT();
2376         HWRM_UNLOCK();
2377
2378         return rc;
2379 }
2380
2381 static void populate_vf_func_cfg_req(struct bnxt *bp,
2382                                      struct hwrm_func_cfg_input *req,
2383                                      int num_vfs)
2384 {
2385         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2386                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2387                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2388                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2389                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2390                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2391                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2392                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2393                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2394                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2395
2396         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2397                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2398         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2399                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2400         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2401                                                 (num_vfs + 1));
2402         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2403         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2404                                                (num_vfs + 1));
2405         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2406         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2407         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2408         /* TODO: For now, do not support VMDq/RFS on VFs. */
2409         req->num_vnics = rte_cpu_to_le_16(1);
2410         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2411                                                  (num_vfs + 1));
2412 }
2413
2414 static void add_random_mac_if_needed(struct bnxt *bp,
2415                                      struct hwrm_func_cfg_input *cfg_req,
2416                                      int vf)
2417 {
2418         struct ether_addr mac;
2419
2420         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2421                 return;
2422
2423         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2424                 cfg_req->enables |=
2425                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2426                 eth_random_addr(cfg_req->dflt_mac_addr);
2427                 bp->pf.vf_info[vf].random_mac = true;
2428         } else {
2429                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2430         }
2431 }
2432
2433 static void reserve_resources_from_vf(struct bnxt *bp,
2434                                       struct hwrm_func_cfg_input *cfg_req,
2435                                       int vf)
2436 {
2437         struct hwrm_func_qcaps_input req = {0};
2438         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2439         int rc;
2440
2441         /* Get the actual allocated values now */
2442         HWRM_PREP(req, FUNC_QCAPS);
2443         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2445
2446         if (rc) {
2447                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2448                 copy_func_cfg_to_qcaps(cfg_req, resp);
2449         } else if (resp->error_code) {
2450                 rc = rte_le_to_cpu_16(resp->error_code);
2451                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2452                 copy_func_cfg_to_qcaps(cfg_req, resp);
2453         }
2454
2455         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2456         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2457         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2458         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2459         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2460         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2461         /*
2462          * TODO: While not supporting VMDq with VFs, max_vnics is always
2463          * forced to 1 in this case
2464          */
2465         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2466         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2467
2468         HWRM_UNLOCK();
2469 }
2470
2471 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2472 {
2473         struct hwrm_func_qcfg_input req = {0};
2474         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2475         int rc;
2476
2477         /* Check for zero MAC address */
2478         HWRM_PREP(req, FUNC_QCFG);
2479         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2480         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2481         if (rc) {
2482                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2483                 return -1;
2484         } else if (resp->error_code) {
2485                 rc = rte_le_to_cpu_16(resp->error_code);
2486                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2487                 return -1;
2488         }
2489         rc = rte_le_to_cpu_16(resp->vlan);
2490
2491         HWRM_UNLOCK();
2492
2493         return rc;
2494 }
2495
2496 static int update_pf_resource_max(struct bnxt *bp)
2497 {
2498         struct hwrm_func_qcfg_input req = {0};
2499         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2500         int rc;
2501
2502         /* And copy the allocated numbers into the pf struct */
2503         HWRM_PREP(req, FUNC_QCFG);
2504         req.fid = rte_cpu_to_le_16(0xffff);
2505         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2506         HWRM_CHECK_RESULT();
2507
2508         /* Only TX ring value reflects actual allocation? TODO */
2509         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2510         bp->pf.evb_mode = resp->evb_mode;
2511
2512         HWRM_UNLOCK();
2513
2514         return rc;
2515 }
2516
2517 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2518 {
2519         int rc;
2520
2521         if (!BNXT_PF(bp)) {
2522                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2523                 return -1;
2524         }
2525
2526         rc = bnxt_hwrm_func_qcaps(bp);
2527         if (rc)
2528                 return rc;
2529
2530         bp->pf.func_cfg_flags &=
2531                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2532                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2533         bp->pf.func_cfg_flags |=
2534                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2535         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2536         return rc;
2537 }
2538
2539 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2540 {
2541         struct hwrm_func_cfg_input req = {0};
2542         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2543         int i;
2544         size_t sz;
2545         int rc = 0;
2546         size_t req_buf_sz;
2547
2548         if (!BNXT_PF(bp)) {
2549                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2550                 return -1;
2551         }
2552
2553         rc = bnxt_hwrm_func_qcaps(bp);
2554
2555         if (rc)
2556                 return rc;
2557
2558         bp->pf.active_vfs = num_vfs;
2559
2560         /*
2561          * First, configure the PF to only use one TX ring.  This ensures that
2562          * there are enough rings for all VFs.
2563          *
2564          * If we don't do this, when we call func_alloc() later, we will lock
2565          * extra rings to the PF that won't be available during func_cfg() of
2566          * the VFs.
2567          *
2568          * This has been fixed with firmware versions above 20.6.54
2569          */
2570         bp->pf.func_cfg_flags &=
2571                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2572                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2573         bp->pf.func_cfg_flags |=
2574                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2575         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2576         if (rc)
2577                 return rc;
2578
2579         /*
2580          * Now, create and register a buffer to hold forwarded VF requests
2581          */
2582         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2583         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2584                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2585         if (bp->pf.vf_req_buf == NULL) {
2586                 rc = -ENOMEM;
2587                 goto error_free;
2588         }
2589         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2590                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2591         for (i = 0; i < num_vfs; i++)
2592                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2593                                         (i * HWRM_MAX_REQ_LEN);
2594
2595         rc = bnxt_hwrm_func_buf_rgtr(bp);
2596         if (rc)
2597                 goto error_free;
2598
2599         populate_vf_func_cfg_req(bp, &req, num_vfs);
2600
2601         bp->pf.active_vfs = 0;
2602         for (i = 0; i < num_vfs; i++) {
2603                 add_random_mac_if_needed(bp, &req, i);
2604
2605                 HWRM_PREP(req, FUNC_CFG);
2606                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2607                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2608                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2609
2610                 /* Clear enable flag for next pass */
2611                 req.enables &= ~rte_cpu_to_le_32(
2612                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2613
2614                 if (rc || resp->error_code) {
2615                         PMD_DRV_LOG(ERR,
2616                                 "Failed to initizlie VF %d\n", i);
2617                         PMD_DRV_LOG(ERR,
2618                                 "Not all VFs available. (%d, %d)\n",
2619                                 rc, resp->error_code);
2620                         HWRM_UNLOCK();
2621                         break;
2622                 }
2623
2624                 HWRM_UNLOCK();
2625
2626                 reserve_resources_from_vf(bp, &req, i);
2627                 bp->pf.active_vfs++;
2628                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2629         }
2630
2631         /*
2632          * Now configure the PF to use "the rest" of the resources
2633          * We're using STD_TX_RING_MODE here though which will limit the TX
2634          * rings.  This will allow QoS to function properly.  Not setting this
2635          * will cause PF rings to break bandwidth settings.
2636          */
2637         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2638         if (rc)
2639                 goto error_free;
2640
2641         rc = update_pf_resource_max(bp);
2642         if (rc)
2643                 goto error_free;
2644
2645         return rc;
2646
2647 error_free:
2648         bnxt_hwrm_func_buf_unrgtr(bp);
2649         return rc;
2650 }
2651
2652 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2653 {
2654         struct hwrm_func_cfg_input req = {0};
2655         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2656         int rc;
2657
2658         HWRM_PREP(req, FUNC_CFG);
2659
2660         req.fid = rte_cpu_to_le_16(0xffff);
2661         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2662         req.evb_mode = bp->pf.evb_mode;
2663
2664         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2665         HWRM_CHECK_RESULT();
2666         HWRM_UNLOCK();
2667
2668         return rc;
2669 }
2670
2671 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2672                                 uint8_t tunnel_type)
2673 {
2674         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2675         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2676         int rc = 0;
2677
2678         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2679         req.tunnel_type = tunnel_type;
2680         req.tunnel_dst_port_val = port;
2681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2682         HWRM_CHECK_RESULT();
2683
2684         switch (tunnel_type) {
2685         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2686                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2687                 bp->vxlan_port = port;
2688                 break;
2689         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2690                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2691                 bp->geneve_port = port;
2692                 break;
2693         default:
2694                 break;
2695         }
2696
2697         HWRM_UNLOCK();
2698
2699         return rc;
2700 }
2701
2702 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2703                                 uint8_t tunnel_type)
2704 {
2705         struct hwrm_tunnel_dst_port_free_input req = {0};
2706         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2707         int rc = 0;
2708
2709         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2710
2711         req.tunnel_type = tunnel_type;
2712         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2714
2715         HWRM_CHECK_RESULT();
2716         HWRM_UNLOCK();
2717
2718         return rc;
2719 }
2720
2721 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2722                                         uint32_t flags)
2723 {
2724         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2725         struct hwrm_func_cfg_input req = {0};
2726         int rc;
2727
2728         HWRM_PREP(req, FUNC_CFG);
2729
2730         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2731         req.flags = rte_cpu_to_le_32(flags);
2732         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2733
2734         HWRM_CHECK_RESULT();
2735         HWRM_UNLOCK();
2736
2737         return rc;
2738 }
2739
2740 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2741 {
2742         uint32_t *flag = flagp;
2743
2744         vnic->flags = *flag;
2745 }
2746
2747 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2748 {
2749         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2750 }
2751
2752 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2753 {
2754         int rc = 0;
2755         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2756         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2757
2758         HWRM_PREP(req, FUNC_BUF_RGTR);
2759
2760         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2761         req.req_buf_page_size = rte_cpu_to_le_16(
2762                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2763         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2764         req.req_buf_page_addr[0] =
2765                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2766         if (req.req_buf_page_addr[0] == 0) {
2767                 PMD_DRV_LOG(ERR,
2768                         "unable to map buffer address to physical memory\n");
2769                 return -ENOMEM;
2770         }
2771
2772         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2773
2774         HWRM_CHECK_RESULT();
2775         HWRM_UNLOCK();
2776
2777         return rc;
2778 }
2779
2780 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2781 {
2782         int rc = 0;
2783         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2784         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2785
2786         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2787
2788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2789
2790         HWRM_CHECK_RESULT();
2791         HWRM_UNLOCK();
2792
2793         return rc;
2794 }
2795
2796 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2797 {
2798         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2799         struct hwrm_func_cfg_input req = {0};
2800         int rc;
2801
2802         HWRM_PREP(req, FUNC_CFG);
2803
2804         req.fid = rte_cpu_to_le_16(0xffff);
2805         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2806         req.enables = rte_cpu_to_le_32(
2807                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2808         req.async_event_cr = rte_cpu_to_le_16(
2809                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2810         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2811
2812         HWRM_CHECK_RESULT();
2813         HWRM_UNLOCK();
2814
2815         return rc;
2816 }
2817
2818 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2819 {
2820         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2821         struct hwrm_func_vf_cfg_input req = {0};
2822         int rc;
2823
2824         HWRM_PREP(req, FUNC_VF_CFG);
2825
2826         req.enables = rte_cpu_to_le_32(
2827                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2828         req.async_event_cr = rte_cpu_to_le_16(
2829                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2830         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2831
2832         HWRM_CHECK_RESULT();
2833         HWRM_UNLOCK();
2834
2835         return rc;
2836 }
2837
2838 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2839 {
2840         struct hwrm_func_cfg_input req = {0};
2841         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2842         uint16_t dflt_vlan, fid;
2843         uint32_t func_cfg_flags;
2844         int rc = 0;
2845
2846         HWRM_PREP(req, FUNC_CFG);
2847
2848         if (is_vf) {
2849                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2850                 fid = bp->pf.vf_info[vf].fid;
2851                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2852         } else {
2853                 fid = rte_cpu_to_le_16(0xffff);
2854                 func_cfg_flags = bp->pf.func_cfg_flags;
2855                 dflt_vlan = bp->vlan;
2856         }
2857
2858         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2859         req.fid = rte_cpu_to_le_16(fid);
2860         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2861         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2862
2863         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2864
2865         HWRM_CHECK_RESULT();
2866         HWRM_UNLOCK();
2867
2868         return rc;
2869 }
2870
2871 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2872                         uint16_t max_bw, uint16_t enables)
2873 {
2874         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2875         struct hwrm_func_cfg_input req = {0};
2876         int rc;
2877
2878         HWRM_PREP(req, FUNC_CFG);
2879
2880         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2881         req.enables |= rte_cpu_to_le_32(enables);
2882         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2883         req.max_bw = rte_cpu_to_le_32(max_bw);
2884         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2885
2886         HWRM_CHECK_RESULT();
2887         HWRM_UNLOCK();
2888
2889         return rc;
2890 }
2891
2892 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2893 {
2894         struct hwrm_func_cfg_input req = {0};
2895         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2896         int rc = 0;
2897
2898         HWRM_PREP(req, FUNC_CFG);
2899
2900         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2901         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2902         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2903         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2904
2905         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2906
2907         HWRM_CHECK_RESULT();
2908         HWRM_UNLOCK();
2909
2910         return rc;
2911 }
2912
2913 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2914                               void *encaped, size_t ec_size)
2915 {
2916         int rc = 0;
2917         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2918         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2919
2920         if (ec_size > sizeof(req.encap_request))
2921                 return -1;
2922
2923         HWRM_PREP(req, REJECT_FWD_RESP);
2924
2925         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2926         memcpy(req.encap_request, encaped, ec_size);
2927
2928         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2929
2930         HWRM_CHECK_RESULT();
2931         HWRM_UNLOCK();
2932
2933         return rc;
2934 }
2935
2936 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2937                                        struct ether_addr *mac)
2938 {
2939         struct hwrm_func_qcfg_input req = {0};
2940         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2941         int rc;
2942
2943         HWRM_PREP(req, FUNC_QCFG);
2944
2945         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2947
2948         HWRM_CHECK_RESULT();
2949
2950         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2951
2952         HWRM_UNLOCK();
2953
2954         return rc;
2955 }
2956
2957 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2958                             void *encaped, size_t ec_size)
2959 {
2960         int rc = 0;
2961         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2962         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2963
2964         if (ec_size > sizeof(req.encap_request))
2965                 return -1;
2966
2967         HWRM_PREP(req, EXEC_FWD_RESP);
2968
2969         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2970         memcpy(req.encap_request, encaped, ec_size);
2971
2972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2973
2974         HWRM_CHECK_RESULT();
2975         HWRM_UNLOCK();
2976
2977         return rc;
2978 }
2979
2980 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2981                          struct rte_eth_stats *stats, uint8_t rx)
2982 {
2983         int rc = 0;
2984         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2985         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2986
2987         HWRM_PREP(req, STAT_CTX_QUERY);
2988
2989         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2990
2991         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2992
2993         HWRM_CHECK_RESULT();
2994
2995         if (rx) {
2996                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2997                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2998                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2999                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3000                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3001                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3002                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3003                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3004         } else {
3005                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3006                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3007                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3008                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3009                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3010                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3011                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
3012         }
3013
3014
3015         HWRM_UNLOCK();
3016
3017         return rc;
3018 }
3019
3020 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3021 {
3022         struct hwrm_port_qstats_input req = {0};
3023         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3024         struct bnxt_pf_info *pf = &bp->pf;
3025         int rc;
3026
3027         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3028                 return 0;
3029
3030         HWRM_PREP(req, PORT_QSTATS);
3031
3032         req.port_id = rte_cpu_to_le_16(pf->port_id);
3033         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3034         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3035         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3036
3037         HWRM_CHECK_RESULT();
3038         HWRM_UNLOCK();
3039
3040         return rc;
3041 }
3042
3043 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3044 {
3045         struct hwrm_port_clr_stats_input req = {0};
3046         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3047         struct bnxt_pf_info *pf = &bp->pf;
3048         int rc;
3049
3050         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3051                 return 0;
3052
3053         HWRM_PREP(req, PORT_CLR_STATS);
3054
3055         req.port_id = rte_cpu_to_le_16(pf->port_id);
3056         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3057
3058         HWRM_CHECK_RESULT();
3059         HWRM_UNLOCK();
3060
3061         return rc;
3062 }
3063
3064 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3065 {
3066         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3067         struct hwrm_port_led_qcaps_input req = {0};
3068         int rc;
3069
3070         if (BNXT_VF(bp))
3071                 return 0;
3072
3073         HWRM_PREP(req, PORT_LED_QCAPS);
3074         req.port_id = bp->pf.port_id;
3075         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3076
3077         HWRM_CHECK_RESULT();
3078
3079         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3080                 unsigned int i;
3081
3082                 bp->num_leds = resp->num_leds;
3083                 memcpy(bp->leds, &resp->led0_id,
3084                         sizeof(bp->leds[0]) * bp->num_leds);
3085                 for (i = 0; i < bp->num_leds; i++) {
3086                         struct bnxt_led_info *led = &bp->leds[i];
3087
3088                         uint16_t caps = led->led_state_caps;
3089
3090                         if (!led->led_group_id ||
3091                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3092                                 bp->num_leds = 0;
3093                                 break;
3094                         }
3095                 }
3096         }
3097
3098         HWRM_UNLOCK();
3099
3100         return rc;
3101 }
3102
3103 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3104 {
3105         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3106         struct hwrm_port_led_cfg_input req = {0};
3107         struct bnxt_led_cfg *led_cfg;
3108         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3109         uint16_t duration = 0;
3110         int rc, i;
3111
3112         if (!bp->num_leds || BNXT_VF(bp))
3113                 return -EOPNOTSUPP;
3114
3115         HWRM_PREP(req, PORT_LED_CFG);
3116
3117         if (led_on) {
3118                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3119                 duration = rte_cpu_to_le_16(500);
3120         }
3121         req.port_id = bp->pf.port_id;
3122         req.num_leds = bp->num_leds;
3123         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3124         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3125                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3126                 led_cfg->led_id = bp->leds[i].led_id;
3127                 led_cfg->led_state = led_state;
3128                 led_cfg->led_blink_on = duration;
3129                 led_cfg->led_blink_off = duration;
3130                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3131         }
3132
3133         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3134
3135         HWRM_CHECK_RESULT();
3136         HWRM_UNLOCK();
3137
3138         return rc;
3139 }
3140
3141 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3142                                uint32_t *length)
3143 {
3144         int rc;
3145         struct hwrm_nvm_get_dir_info_input req = {0};
3146         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3147
3148         HWRM_PREP(req, NVM_GET_DIR_INFO);
3149
3150         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3151
3152         HWRM_CHECK_RESULT();
3153         HWRM_UNLOCK();
3154
3155         if (!rc) {
3156                 *entries = rte_le_to_cpu_32(resp->entries);
3157                 *length = rte_le_to_cpu_32(resp->entry_length);
3158         }
3159         return rc;
3160 }
3161
3162 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3163 {
3164         int rc;
3165         uint32_t dir_entries;
3166         uint32_t entry_length;
3167         uint8_t *buf;
3168         size_t buflen;
3169         rte_iova_t dma_handle;
3170         struct hwrm_nvm_get_dir_entries_input req = {0};
3171         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3172
3173         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3174         if (rc != 0)
3175                 return rc;
3176
3177         *data++ = dir_entries;
3178         *data++ = entry_length;
3179         len -= 2;
3180         memset(data, 0xff, len);
3181
3182         buflen = dir_entries * entry_length;
3183         buf = rte_malloc("nvm_dir", buflen, 0);
3184         rte_mem_lock_page(buf);
3185         if (buf == NULL)
3186                 return -ENOMEM;
3187         dma_handle = rte_mem_virt2iova(buf);
3188         if (dma_handle == 0) {
3189                 PMD_DRV_LOG(ERR,
3190                         "unable to map response address to physical memory\n");
3191                 return -ENOMEM;
3192         }
3193         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3194         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3195         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3196
3197         HWRM_CHECK_RESULT();
3198         HWRM_UNLOCK();
3199
3200         if (rc == 0)
3201                 memcpy(data, buf, len > buflen ? buflen : len);
3202
3203         rte_free(buf);
3204
3205         return rc;
3206 }
3207
3208 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3209                              uint32_t offset, uint32_t length,
3210                              uint8_t *data)
3211 {
3212         int rc;
3213         uint8_t *buf;
3214         rte_iova_t dma_handle;
3215         struct hwrm_nvm_read_input req = {0};
3216         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3217
3218         buf = rte_malloc("nvm_item", length, 0);
3219         rte_mem_lock_page(buf);
3220         if (!buf)
3221                 return -ENOMEM;
3222
3223         dma_handle = rte_mem_virt2iova(buf);
3224         if (dma_handle == 0) {
3225                 PMD_DRV_LOG(ERR,
3226                         "unable to map response address to physical memory\n");
3227                 return -ENOMEM;
3228         }
3229         HWRM_PREP(req, NVM_READ);
3230         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3231         req.dir_idx = rte_cpu_to_le_16(index);
3232         req.offset = rte_cpu_to_le_32(offset);
3233         req.len = rte_cpu_to_le_32(length);
3234         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3235         HWRM_CHECK_RESULT();
3236         HWRM_UNLOCK();
3237         if (rc == 0)
3238                 memcpy(data, buf, length);
3239
3240         rte_free(buf);
3241         return rc;
3242 }
3243
3244 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3245 {
3246         int rc;
3247         struct hwrm_nvm_erase_dir_entry_input req = {0};
3248         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3249
3250         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3251         req.dir_idx = rte_cpu_to_le_16(index);
3252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3253         HWRM_CHECK_RESULT();
3254         HWRM_UNLOCK();
3255
3256         return rc;
3257 }
3258
3259
3260 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3261                           uint16_t dir_ordinal, uint16_t dir_ext,
3262                           uint16_t dir_attr, const uint8_t *data,
3263                           size_t data_len)
3264 {
3265         int rc;
3266         struct hwrm_nvm_write_input req = {0};
3267         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3268         rte_iova_t dma_handle;
3269         uint8_t *buf;
3270
3271         HWRM_PREP(req, NVM_WRITE);
3272
3273         req.dir_type = rte_cpu_to_le_16(dir_type);
3274         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3275         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3276         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3277         req.dir_data_length = rte_cpu_to_le_32(data_len);
3278
3279         buf = rte_malloc("nvm_write", data_len, 0);
3280         rte_mem_lock_page(buf);
3281         if (!buf)
3282                 return -ENOMEM;
3283
3284         dma_handle = rte_mem_virt2iova(buf);
3285         if (dma_handle == 0) {
3286                 PMD_DRV_LOG(ERR,
3287                         "unable to map response address to physical memory\n");
3288                 return -ENOMEM;
3289         }
3290         memcpy(buf, data, data_len);
3291         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3292
3293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3294
3295         HWRM_CHECK_RESULT();
3296         HWRM_UNLOCK();
3297
3298         rte_free(buf);
3299         return rc;
3300 }
3301
3302 static void
3303 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3304 {
3305         uint32_t *count = cbdata;
3306
3307         *count = *count + 1;
3308 }
3309
3310 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3311                                      struct bnxt_vnic_info *vnic __rte_unused)
3312 {
3313         return 0;
3314 }
3315
3316 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3317 {
3318         uint32_t count = 0;
3319
3320         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3321             &count, bnxt_vnic_count_hwrm_stub);
3322
3323         return count;
3324 }
3325
3326 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3327                                         uint16_t *vnic_ids)
3328 {
3329         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3330         struct hwrm_func_vf_vnic_ids_query_output *resp =
3331                                                 bp->hwrm_cmd_resp_addr;
3332         int rc;
3333
3334         /* First query all VNIC ids */
3335         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3336
3337         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3338         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3339         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3340
3341         if (req.vnic_id_tbl_addr == 0) {
3342                 HWRM_UNLOCK();
3343                 PMD_DRV_LOG(ERR,
3344                 "unable to map VNIC ID table address to physical memory\n");
3345                 return -ENOMEM;
3346         }
3347         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3348         if (rc) {
3349                 HWRM_UNLOCK();
3350                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3351                 return -1;
3352         } else if (resp->error_code) {
3353                 rc = rte_le_to_cpu_16(resp->error_code);
3354                 HWRM_UNLOCK();
3355                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3356                 return -1;
3357         }
3358         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3359
3360         HWRM_UNLOCK();
3361
3362         return rc;
3363 }
3364
3365 /*
3366  * This function queries the VNIC IDs  for a specified VF. It then calls
3367  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3368  * Then it calls the hwrm_cb function to program this new vnic configuration.
3369  */
3370 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3371         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3372         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3373 {
3374         struct bnxt_vnic_info vnic;
3375         int rc = 0;
3376         int i, num_vnic_ids;
3377         uint16_t *vnic_ids;
3378         size_t vnic_id_sz;
3379         size_t sz;
3380
3381         /* First query all VNIC ids */
3382         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3383         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3384                         RTE_CACHE_LINE_SIZE);
3385         if (vnic_ids == NULL) {
3386                 rc = -ENOMEM;
3387                 return rc;
3388         }
3389         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3390                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3391
3392         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3393
3394         if (num_vnic_ids < 0)
3395                 return num_vnic_ids;
3396
3397         /* Retrieve VNIC, update bd_stall then update */
3398
3399         for (i = 0; i < num_vnic_ids; i++) {
3400                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3401                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3402                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3403                 if (rc)
3404                         break;
3405                 if (vnic.mru <= 4)      /* Indicates unallocated */
3406                         continue;
3407
3408                 vnic_cb(&vnic, cbdata);
3409
3410                 rc = hwrm_cb(bp, &vnic);
3411                 if (rc)
3412                         break;
3413         }
3414
3415         rte_free(vnic_ids);
3416
3417         return rc;
3418 }
3419
3420 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3421                                               bool on)
3422 {
3423         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3424         struct hwrm_func_cfg_input req = {0};
3425         int rc;
3426
3427         HWRM_PREP(req, FUNC_CFG);
3428
3429         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3430         req.enables |= rte_cpu_to_le_32(
3431                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3432         req.vlan_antispoof_mode = on ?
3433                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3434                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3435         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3436
3437         HWRM_CHECK_RESULT();
3438         HWRM_UNLOCK();
3439
3440         return rc;
3441 }
3442
3443 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3444 {
3445         struct bnxt_vnic_info vnic;
3446         uint16_t *vnic_ids;
3447         size_t vnic_id_sz;
3448         int num_vnic_ids, i;
3449         size_t sz;
3450         int rc;
3451
3452         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3453         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3454                         RTE_CACHE_LINE_SIZE);
3455         if (vnic_ids == NULL) {
3456                 rc = -ENOMEM;
3457                 return rc;
3458         }
3459
3460         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3461                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3462
3463         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3464         if (rc <= 0)
3465                 goto exit;
3466         num_vnic_ids = rc;
3467
3468         /*
3469          * Loop through to find the default VNIC ID.
3470          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3471          * by sending the hwrm_func_qcfg command to the firmware.
3472          */
3473         for (i = 0; i < num_vnic_ids; i++) {
3474                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3475                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3476                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3477                                         bp->pf.first_vf_id + vf);
3478                 if (rc)
3479                         goto exit;
3480                 if (vnic.func_default) {
3481                         rte_free(vnic_ids);
3482                         return vnic.fw_vnic_id;
3483                 }
3484         }
3485         /* Could not find a default VNIC. */
3486         PMD_DRV_LOG(ERR, "No default VNIC\n");
3487 exit:
3488         rte_free(vnic_ids);
3489         return -1;
3490 }
3491
3492 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3493                          uint16_t dst_id,
3494                          struct bnxt_filter_info *filter)
3495 {
3496         int rc = 0;
3497         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3498         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3499         uint32_t enables = 0;
3500
3501         if (filter->fw_em_filter_id != UINT64_MAX)
3502                 bnxt_hwrm_clear_em_filter(bp, filter);
3503
3504         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3505
3506         req.flags = rte_cpu_to_le_32(filter->flags);
3507
3508         enables = filter->enables |
3509               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3510         req.dst_id = rte_cpu_to_le_16(dst_id);
3511
3512         if (filter->ip_addr_type) {
3513                 req.ip_addr_type = filter->ip_addr_type;
3514                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3515         }
3516         if (enables &
3517             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3518                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3519         if (enables &
3520             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3521                 memcpy(req.src_macaddr, filter->src_macaddr,
3522                        ETHER_ADDR_LEN);
3523         if (enables &
3524             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3525                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3526                        ETHER_ADDR_LEN);
3527         if (enables &
3528             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3529                 req.ovlan_vid = filter->l2_ovlan;
3530         if (enables &
3531             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3532                 req.ivlan_vid = filter->l2_ivlan;
3533         if (enables &
3534             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3535                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3536         if (enables &
3537             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3538                 req.ip_protocol = filter->ip_protocol;
3539         if (enables &
3540             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3541                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3542         if (enables &
3543             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3544                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3545         if (enables &
3546             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3547                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3548         if (enables &
3549             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3550                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3551         if (enables &
3552             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3553                 req.mirror_vnic_id = filter->mirror_vnic_id;
3554
3555         req.enables = rte_cpu_to_le_32(enables);
3556
3557         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3558
3559         HWRM_CHECK_RESULT();
3560
3561         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3562         HWRM_UNLOCK();
3563
3564         return rc;
3565 }
3566
3567 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3568 {
3569         int rc = 0;
3570         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3571         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3572
3573         if (filter->fw_em_filter_id == UINT64_MAX)
3574                 return 0;
3575
3576         PMD_DRV_LOG(ERR, "Clear EM filter\n");
3577         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3578
3579         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3580
3581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3582
3583         HWRM_CHECK_RESULT();
3584         HWRM_UNLOCK();
3585
3586         filter->fw_em_filter_id = -1;
3587         filter->fw_l2_filter_id = -1;
3588
3589         return 0;
3590 }
3591
3592 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3593                          uint16_t dst_id,
3594                          struct bnxt_filter_info *filter)
3595 {
3596         int rc = 0;
3597         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3598         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3599                                                 bp->hwrm_cmd_resp_addr;
3600         uint32_t enables = 0;
3601
3602         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3603                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3604
3605         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3606
3607         req.flags = rte_cpu_to_le_32(filter->flags);
3608
3609         enables = filter->enables |
3610               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3611         req.dst_id = rte_cpu_to_le_16(dst_id);
3612
3613
3614         if (filter->ip_addr_type) {
3615                 req.ip_addr_type = filter->ip_addr_type;
3616                 enables |=
3617                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3618         }
3619         if (enables &
3620             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3621                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3622         if (enables &
3623             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3624                 memcpy(req.src_macaddr, filter->src_macaddr,
3625                        ETHER_ADDR_LEN);
3626         //if (enables &
3627             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3628                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3629                        //ETHER_ADDR_LEN);
3630         if (enables &
3631             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3632                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3633         if (enables &
3634             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3635                 req.ip_protocol = filter->ip_protocol;
3636         if (enables &
3637             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3638                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3639         if (enables &
3640             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3641                 req.src_ipaddr_mask[0] =
3642                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3643         if (enables &
3644             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3645                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3646         if (enables &
3647             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3648                 req.dst_ipaddr_mask[0] =
3649                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3650         if (enables &
3651             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3652                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3653         if (enables &
3654             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3655                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3656         if (enables &
3657             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3658                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3659         if (enables &
3660             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3661                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3662         if (enables &
3663             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3664                 req.mirror_vnic_id = filter->mirror_vnic_id;
3665
3666         req.enables = rte_cpu_to_le_32(enables);
3667
3668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3669
3670         HWRM_CHECK_RESULT();
3671
3672         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3673         HWRM_UNLOCK();
3674
3675         return rc;
3676 }
3677
3678 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3679                                 struct bnxt_filter_info *filter)
3680 {
3681         int rc = 0;
3682         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3683         struct hwrm_cfa_ntuple_filter_free_output *resp =
3684                                                 bp->hwrm_cmd_resp_addr;
3685
3686         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3687                 return 0;
3688
3689         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3690
3691         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3692
3693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3694
3695         HWRM_CHECK_RESULT();
3696         HWRM_UNLOCK();
3697
3698         filter->fw_ntuple_filter_id = -1;
3699         filter->fw_l2_filter_id = UINT64_MAX;
3700
3701         return 0;
3702 }
3703
3704 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3705 {
3706         unsigned int rss_idx, fw_idx, i;
3707
3708         if (vnic->rss_table && vnic->hash_type) {
3709                 /*
3710                  * Fill the RSS hash & redirection table with
3711                  * ring group ids for all VNICs
3712                  */
3713                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3714                         rss_idx++, fw_idx++) {
3715                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3716                                 fw_idx %= bp->rx_cp_nr_rings;
3717                                 if (vnic->fw_grp_ids[fw_idx] !=
3718                                     INVALID_HW_RING_ID)
3719                                         break;
3720                                 fw_idx++;
3721                         }
3722                         if (i == bp->rx_cp_nr_rings)
3723                                 return 0;
3724                         vnic->rss_table[rss_idx] =
3725                                 vnic->fw_grp_ids[fw_idx];
3726                 }
3727                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
3728         }
3729         return 0;
3730 }