drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <unistd.h>
  37
  38 #include <rte_byteorder.h>
  39 #include <rte_common.h>
  40 #include <rte_cycles.h>
  41 #include <rte_malloc.h>
  42 #include <rte_memzone.h>
  43 #include <rte_version.h>
  44
  45 #include "bnxt.h"
  46 #include "bnxt_cpr.h"
  47 #include "bnxt_filter.h"
  48 #include "bnxt_hwrm.h"
  49 #include "bnxt_rxq.h"
  50 #include "bnxt_rxr.h"
  51 #include "bnxt_ring.h"
  52 #include "bnxt_txq.h"
  53 #include "bnxt_txr.h"
  54 #include "bnxt_vnic.h"
  55 #include "hsi_struct_def_dpdk.h"
  56
  57 #include <rte_io.h>
  58
  59 #define HWRM_CMD_TIMEOUT                2000
  60
  61 struct bnxt_plcmodes_cfg {
  62         uint32_t        flags;
  63         uint16_t        jumbo_thresh;
  64         uint16_t        hds_offset;
  65         uint16_t        hds_threshold;
  66 };
  67
  68 static int page_getenum(size_t size)
  69 {
  70         if (size <= 1 << 4)
  71                 return 4;
  72         if (size <= 1 << 12)
  73                 return 12;
  74         if (size <= 1 << 13)
  75                 return 13;
  76         if (size <= 1 << 16)
  77                 return 16;
  78         if (size <= 1 << 21)
  79                 return 21;
  80         if (size <= 1 << 22)
  81                 return 22;
  82         if (size <= 1 << 30)
  83                 return 30;
  84         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  85         return sizeof(void *) * 8 - 1;
  86 }
  87
  88 static int page_roundup(size_t size)
  89 {
  90         return 1 << page_getenum(size);
  91 }
  92
  93 /*
  94  * HWRM Functions (sent to HWRM)
  95  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  96  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  97  * command was failed by the ChiMP.
  98  */
  99
 100 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
 101                                         uint32_t msg_len)
 102 {
 103         unsigned int i;
 104         struct input *req = msg;
 105         struct output *resp = bp->hwrm_cmd_resp_addr;
 106         uint32_t *data = msg;
 107         uint8_t *bar;
 108         uint8_t *valid;
 109
 110         /* Write request msg to hwrm channel */
 111         for (i = 0; i < msg_len; i += 4) {
 112                 bar = (uint8_t *)bp->bar0 + i;
 113                 rte_write32(*data, bar);
 114                 data++;
 115         }
 116
 117         /* Zero the rest of the request space */
 118         for (; i < bp->max_req_len; i += 4) {
 119                 bar = (uint8_t *)bp->bar0 + i;
 120                 rte_write32(0, bar);
 121         }
 122
 123         /* Ring channel doorbell */
 124         bar = (uint8_t *)bp->bar0 + 0x100;
 125         rte_write32(1, bar);
 126
 127         /* Poll for the valid bit */
 128         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 129                 /* Sanity check on the resp->resp_len */
 130                 rte_rmb();
 131                 if (resp->resp_len && resp->resp_len <=
 132                                 bp->max_resp_len) {
 133                         /* Last byte of resp contains the valid key */
 134                         valid = (uint8_t *)resp + resp->resp_len - 1;
 135                         if (*valid == HWRM_RESP_VALID_KEY)
 136                                 break;
 137                 }
 138                 rte_delay_us(600);
 139         }
 140
 141         if (i >= HWRM_CMD_TIMEOUT) {
 142                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 143                         req->req_type);
 144                 goto err_ret;
 145         }
 146         return 0;
 147
 148 err_ret:
 149         return -1;
 150 }
 151
 152 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 153 {
 154         int rc;
 155
 156         rte_spinlock_lock(&bp->hwrm_lock);
 157         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 158         rte_spinlock_unlock(&bp->hwrm_lock);
 159         return rc;
 160 }
 161
 162 #define HWRM_PREP(req, type, cr, resp) \
 163         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 164         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 165         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 166         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 167         req.target_id = rte_cpu_to_le_16(0xffff); \
 168         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 169
 170 #define HWRM_CHECK_RESULT \
 171         { \
 172                 if (rc) { \
 173                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 174                                 __func__, rc); \
 175                         return rc; \
 176                 } \
 177                 if (resp->error_code) { \
 178                         rc = rte_le_to_cpu_16(resp->error_code); \
 179                         if (resp->resp_len >= 16) { \
 180                                 struct hwrm_err_output *tmp_hwrm_err_op = \
 181                                                         (void *)resp; \
 182                                 RTE_LOG(ERR, PMD, \
 183                                         "%s error %d:%d:%08x:%04x\n", \
 184                                         __func__, \
 185                                         rc, tmp_hwrm_err_op->cmd_err, \
 186                                         rte_le_to_cpu_32(\
 187                                                 tmp_hwrm_err_op->opaque_0), \
 188                                         rte_le_to_cpu_16(\
 189                                                 tmp_hwrm_err_op->opaque_1)); \
 190                         } \
 191                         else { \
 192                                 RTE_LOG(ERR, PMD, \
 193                                         "%s error %d\n", __func__, rc); \
 194                         } \
 195                         return rc; \
 196                 } \
 197         }
 198
 199 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 200 {
 201         int rc = 0;
 202         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 203         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 204
 205         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 206         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 207         req.mask = 0;
 208
 209         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 210
 211         HWRM_CHECK_RESULT;
 212
 213         return rc;
 214 }
 215
 216 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 217                                  struct bnxt_vnic_info *vnic,
 218                                  uint16_t vlan_count,
 219                                  struct bnxt_vlan_table_entry *vlan_table)
 220 {
 221         int rc = 0;
 222         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 223         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 224         uint32_t mask = 0;
 225
 226         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 227         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 228
 229         /* FIXME add multicast flag, when multicast adding options is supported
 230          * by ethtool.
 231          */
 232         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 233                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 234         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 235                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 236         if (vnic->mc_addr_cnt) {
 237                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 238                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 239                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 240         }
 241         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 242                                     mask);
 243         if (vlan_count && vlan_table) {
 244                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 245                 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
 246                          rte_mem_virt2phy(vlan_table));
 247                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 248         }
 249
 250         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 251
 252         HWRM_CHECK_RESULT;
 253
 254         return rc;
 255 }
 256
 257 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 258                            struct bnxt_filter_info *filter)
 259 {
 260         int rc = 0;
 261         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 262         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 263
 264         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 265
 266         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 267
 268         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 269
 270         HWRM_CHECK_RESULT;
 271
 272         filter->fw_l2_filter_id = -1;
 273
 274         return 0;
 275 }
 276
 277 int bnxt_hwrm_set_filter(struct bnxt *bp,
 278                          uint16_t dst_id,
 279                          struct bnxt_filter_info *filter)
 280 {
 281         int rc = 0;
 282         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 283         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 284         uint32_t enables = 0;
 285
 286         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 287
 288         req.flags = rte_cpu_to_le_32(filter->flags);
 289
 290         enables = filter->enables |
 291               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 292         req.dst_id = rte_cpu_to_le_16(dst_id);
 293
 294         if (enables &
 295             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 296                 memcpy(req.l2_addr, filter->l2_addr,
 297                        ETHER_ADDR_LEN);
 298         if (enables &
 299             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 300                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 301                        ETHER_ADDR_LEN);
 302         if (enables &
 303             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 304                 req.l2_ovlan = filter->l2_ovlan;
 305         if (enables &
 306             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 307                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 308         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 309                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 310         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 311                 req.src_type = filter->src_type;
 312
 313         req.enables = rte_cpu_to_le_32(enables);
 314
 315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 316
 317         HWRM_CHECK_RESULT;
 318
 319         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 320
 321         return rc;
 322 }
 323
 324 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 325 {
 326         int rc = 0;
 327         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 328         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 329         uint16_t new_max_vfs;
 330         int i;
 331
 332         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 333
 334         req.fid = rte_cpu_to_le_16(0xffff);
 335
 336         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 337
 338         HWRM_CHECK_RESULT;
 339
 340         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 341         if (BNXT_PF(bp)) {
 342                 bp->pf.port_id = resp->port_id;
 343                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 344                 new_max_vfs = bp->pdev->max_vfs;
 345                 if (new_max_vfs != bp->pf.max_vfs) {
 346                         if (bp->pf.vf_info)
 347                                 rte_free(bp->pf.vf_info);
 348                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 349                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 350                         bp->pf.max_vfs = new_max_vfs;
 351                         for (i = 0; i < new_max_vfs; i++) {
 352                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 353                                 bp->pf.vf_info[i].vlan_table =
 354                                         rte_zmalloc("VF VLAN table",
 355                                                     getpagesize(),
 356                                                     getpagesize());
 357                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 358                                         RTE_LOG(ERR, PMD,
 359                                         "Fail to alloc VLAN table for VF %d\n",
 360                                         i);
 361                                 else
 362                                         rte_mem_lock_page(
 363                                                 bp->pf.vf_info[i].vlan_table);
 364                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 365                         }
 366                 }
 367         }
 368
 369         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 370         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 371         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 372         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 373         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 374         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 375         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 376         /* TODO: For now, do not support VMDq/RFS on VFs. */
 377         if (BNXT_PF(bp)) {
 378                 if (bp->pf.max_vfs)
 379                         bp->max_vnics = 1;
 380                 else
 381                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 382         } else {
 383                 bp->max_vnics = 1;
 384         }
 385         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 386         if (BNXT_PF(bp))
 387                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 388
 389         return rc;
 390 }
 391
 392 int bnxt_hwrm_func_reset(struct bnxt *bp)
 393 {
 394         int rc = 0;
 395         struct hwrm_func_reset_input req = {.req_type = 0 };
 396         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 397
 398         HWRM_PREP(req, FUNC_RESET, -1, resp);
 399
 400         req.enables = rte_cpu_to_le_32(0);
 401
 402         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 403
 404         HWRM_CHECK_RESULT;
 405
 406         return rc;
 407 }
 408
 409 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 410 {
 411         int rc;
 412         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 413         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 414
 415         if (bp->flags & BNXT_FLAG_REGISTERED)
 416                 return 0;
 417
 418         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 419         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 420                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 421         req.ver_maj = RTE_VER_YEAR;
 422         req.ver_min = RTE_VER_MONTH;
 423         req.ver_upd = RTE_VER_MINOR;
 424
 425         if (BNXT_PF(bp)) {
 426                 req.enables |= rte_cpu_to_le_32(
 427                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 428                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 429                        RTE_MIN(sizeof(req.vf_req_fwd),
 430                                sizeof(bp->pf.vf_req_fwd)));
 431         }
 432
 433         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 434         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 435
 436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 437
 438         HWRM_CHECK_RESULT;
 439
 440         bp->flags |= BNXT_FLAG_REGISTERED;
 441
 442         return rc;
 443 }
 444
 445 int bnxt_hwrm_ver_get(struct bnxt *bp)
 446 {
 447         int rc = 0;
 448         struct hwrm_ver_get_input req = {.req_type = 0 };
 449         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 450         uint32_t my_version;
 451         uint32_t fw_version;
 452         uint16_t max_resp_len;
 453         char type[RTE_MEMZONE_NAMESIZE];
 454
 455         HWRM_PREP(req, VER_GET, -1, resp);
 456
 457         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 458         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 459         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 460
 461         /*
 462          * Hold the lock since we may be adjusting the response pointers.
 463          */
 464         rte_spinlock_lock(&bp->hwrm_lock);
 465         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 466
 467         HWRM_CHECK_RESULT;
 468
 469         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 470                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 471                 resp->hwrm_intf_upd,
 472                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 473         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 474                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 475         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 476                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 477
 478         my_version = HWRM_VERSION_MAJOR << 16;
 479         my_version |= HWRM_VERSION_MINOR << 8;
 480         my_version |= HWRM_VERSION_UPDATE;
 481
 482         fw_version = resp->hwrm_intf_maj << 16;
 483         fw_version |= resp->hwrm_intf_min << 8;
 484         fw_version |= resp->hwrm_intf_upd;
 485
 486         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 487                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 488                 rc = -EINVAL;
 489                 goto error;
 490         }
 491
 492         if (my_version != fw_version) {
 493                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 494                 if (my_version < fw_version) {
 495                         RTE_LOG(INFO, PMD,
 496                                 "Firmware API version is newer than driver.\n");
 497                         RTE_LOG(INFO, PMD,
 498                                 "The driver may be missing features.\n");
 499                 } else {
 500                         RTE_LOG(INFO, PMD,
 501                                 "Firmware API version is older than driver.\n");
 502                         RTE_LOG(INFO, PMD,
 503                                 "Not all driver features may be functional.\n");
 504                 }
 505         }
 506
 507         if (bp->max_req_len > resp->max_req_win_len) {
 508                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 509                 rc = -EINVAL;
 510         }
 511         bp->max_req_len = resp->max_req_win_len;
 512         max_resp_len = resp->max_resp_len;
 513         if (bp->max_resp_len != max_resp_len) {
 514                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 515                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 516                         bp->pdev->addr.devid, bp->pdev->addr.function);
 517
 518                 rte_free(bp->hwrm_cmd_resp_addr);
 519
 520                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 521                 if (bp->hwrm_cmd_resp_addr == NULL) {
 522                         rc = -ENOMEM;
 523                         goto error;
 524                 }
 525                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 526                 bp->hwrm_cmd_resp_dma_addr =
 527                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 528                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 529                         RTE_LOG(ERR, PMD,
 530                         "Unable to map response buffer to physical memory.\n");
 531                         rc = -ENOMEM;
 532                         goto error;
 533                 }
 534                 bp->max_resp_len = max_resp_len;
 535         }
 536
 537 error:
 538         rte_spinlock_unlock(&bp->hwrm_lock);
 539         return rc;
 540 }
 541
 542 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 543 {
 544         int rc;
 545         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 546         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 547
 548         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 549                 return 0;
 550
 551         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 552         req.flags = flags;
 553
 554         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 555
 556         HWRM_CHECK_RESULT;
 557
 558         bp->flags &= ~BNXT_FLAG_REGISTERED;
 559
 560         return rc;
 561 }
 562
 563 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 564 {
 565         int rc = 0;
 566         struct hwrm_port_phy_cfg_input req = {0};
 567         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 568         uint32_t enables = 0;
 569
 570         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 571
 572         if (conf->link_up) {
 573                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 574                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 575                 /*
 576                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 577                  * any auto mode, even "none".
 578                  */
 579                 if (!conf->link_speed) {
 580                         req.auto_mode |= conf->auto_mode;
 581                         enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 582                         req.auto_link_speed_mask = conf->auto_link_speed_mask;
 583                         enables |=
 584                            HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 585                         req.auto_link_speed = bp->link_info.auto_link_speed;
 586                         enables |=
 587                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 588                 }
 589                 req.auto_duplex = conf->duplex;
 590                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 591                 req.auto_pause = conf->auto_pause;
 592                 req.force_pause = conf->force_pause;
 593                 /* Set force_pause if there is no auto or if there is a force */
 594                 if (req.auto_pause && !req.force_pause)
 595                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 596                 else
 597                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 598
 599                 req.enables = rte_cpu_to_le_32(enables);
 600         } else {
 601                 req.flags =
 602                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 603                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 604         }
 605
 606         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 607
 608         HWRM_CHECK_RESULT;
 609
 610         return rc;
 611 }
 612
 613 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 614                                    struct bnxt_link_info *link_info)
 615 {
 616         int rc = 0;
 617         struct hwrm_port_phy_qcfg_input req = {0};
 618         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 619
 620         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
 621
 622         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 623
 624         HWRM_CHECK_RESULT;
 625
 626         link_info->phy_link_status = resp->link;
 627         if (link_info->phy_link_status != HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK) {
 628                 link_info->link_up = 1;
 629                 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 630         } else {
 631                 link_info->link_up = 0;
 632                 link_info->link_speed = 0;
 633         }
 634         link_info->duplex = resp->duplex;
 635         link_info->pause = resp->pause;
 636         link_info->auto_pause = resp->auto_pause;
 637         link_info->force_pause = resp->force_pause;
 638         link_info->auto_mode = resp->auto_mode;
 639
 640         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 641         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 642         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 643         link_info->phy_ver[0] = resp->phy_maj;
 644         link_info->phy_ver[1] = resp->phy_min;
 645         link_info->phy_ver[2] = resp->phy_bld;
 646
 647         return rc;
 648 }
 649
 650 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 651 {
 652         int rc = 0;
 653         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 654         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 655
 656         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 657
 658         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 659
 660         HWRM_CHECK_RESULT;
 661
 662 #define GET_QUEUE_INFO(x) \
 663         bp->cos_queue[x].id = resp->queue_id##x; \
 664         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 665
 666         GET_QUEUE_INFO(0);
 667         GET_QUEUE_INFO(1);
 668         GET_QUEUE_INFO(2);
 669         GET_QUEUE_INFO(3);
 670         GET_QUEUE_INFO(4);
 671         GET_QUEUE_INFO(5);
 672         GET_QUEUE_INFO(6);
 673         GET_QUEUE_INFO(7);
 674
 675         return rc;
 676 }
 677
 678 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 679                          struct bnxt_ring *ring,
 680                          uint32_t ring_type, uint32_t map_index,
 681                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 682 {
 683         int rc = 0;
 684         uint32_t enables = 0;
 685         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 686         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 687
 688         HWRM_PREP(req, RING_ALLOC, -1, resp);
 689
 690         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 691         req.fbo = rte_cpu_to_le_32(0);
 692         /* Association of ring index with doorbell index */
 693         req.logical_id = rte_cpu_to_le_16(map_index);
 694         req.length = rte_cpu_to_le_32(ring->ring_size);
 695
 696         switch (ring_type) {
 697         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 698                 req.queue_id = bp->cos_queue[0].id;
 699                 /* FALLTHROUGH */
 700         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 701                 req.ring_type = ring_type;
 702                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 703                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 704                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 705                         enables |=
 706                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 707                 break;
 708         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 709                 req.ring_type = ring_type;
 710                 /*
 711                  * TODO: Some HWRM versions crash with
 712                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 713                  */
 714                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 715                 break;
 716         default:
 717                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 718                         ring_type);
 719                 return -1;
 720         }
 721         req.enables = rte_cpu_to_le_32(enables);
 722
 723         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 724
 725         if (rc || resp->error_code) {
 726                 if (rc == 0 && resp->error_code)
 727                         rc = rte_le_to_cpu_16(resp->error_code);
 728                 switch (ring_type) {
 729                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 730                         RTE_LOG(ERR, PMD,
 731                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 732                         return rc;
 733                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 734                         RTE_LOG(ERR, PMD,
 735                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 736                         return rc;
 737                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 738                         RTE_LOG(ERR, PMD,
 739                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 740                         return rc;
 741                 default:
 742                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 743                         return rc;
 744                 }
 745         }
 746
 747         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 748         return rc;
 749 }
 750
 751 int bnxt_hwrm_ring_free(struct bnxt *bp,
 752                         struct bnxt_ring *ring, uint32_t ring_type)
 753 {
 754         int rc;
 755         struct hwrm_ring_free_input req = {.req_type = 0 };
 756         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 757
 758         HWRM_PREP(req, RING_FREE, -1, resp);
 759
 760         req.ring_type = ring_type;
 761         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 762
 763         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 764
 765         if (rc || resp->error_code) {
 766                 if (rc == 0 && resp->error_code)
 767                         rc = rte_le_to_cpu_16(resp->error_code);
 768
 769                 switch (ring_type) {
 770                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 771                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 772                                 rc);
 773                         return rc;
 774                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 775                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 776                                 rc);
 777                         return rc;
 778                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 779                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 780                                 rc);
 781                         return rc;
 782                 default:
 783                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 784                         return rc;
 785                 }
 786         }
 787         return 0;
 788 }
 789
 790 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 791 {
 792         int rc = 0;
 793         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 794         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 795
 796         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 797
 798         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 799         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 800         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 801         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 802
 803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 804
 805         HWRM_CHECK_RESULT;
 806
 807         bp->grp_info[idx].fw_grp_id =
 808             rte_le_to_cpu_16(resp->ring_group_id);
 809
 810         return rc;
 811 }
 812
 813 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 814 {
 815         int rc;
 816         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 817         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 818
 819         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 820
 821         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 822
 823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 824
 825         HWRM_CHECK_RESULT;
 826
 827         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 828         return rc;
 829 }
 830
 831 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 832 {
 833         int rc = 0;
 834         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 835         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 836
 837         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 838                 return rc;
 839
 840         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 841
 842         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 843
 844         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 845
 846         HWRM_CHECK_RESULT;
 847
 848         return rc;
 849 }
 850
 851 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 852                                 unsigned int idx __rte_unused)
 853 {
 854         int rc;
 855         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 856         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 857
 858         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 859
 860         req.update_period_ms = rte_cpu_to_le_32(0);
 861
 862         req.stats_dma_addr =
 863             rte_cpu_to_le_64(cpr->hw_stats_map);
 864
 865         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 866
 867         HWRM_CHECK_RESULT;
 868
 869         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 870
 871         return rc;
 872 }
 873
 874 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 875                                 unsigned int idx __rte_unused)
 876 {
 877         int rc;
 878         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 879         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 880
 881         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 882
 883         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 884
 885         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 886
 887         HWRM_CHECK_RESULT;
 888
 889         return rc;
 890 }
 891
 892 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 893 {
 894         int rc = 0, i, j;
 895         struct hwrm_vnic_alloc_input req = { 0 };
 896         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 897
 898         /* map ring groups to this vnic */
 899         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
 900                 vnic->start_grp_id, vnic->end_grp_id);
 901         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
 902                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 903         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
 904         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
 905         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
 906         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
 907         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 908                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
 909         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 910
 911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 912
 913         HWRM_CHECK_RESULT;
 914
 915         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 916         return rc;
 917 }
 918
 919 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
 920                                         struct bnxt_vnic_info *vnic,
 921                                         struct bnxt_plcmodes_cfg *pmode)
 922 {
 923         int rc = 0;
 924         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
 925         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 926
 927         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
 928
 929         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 930
 931         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 932
 933         HWRM_CHECK_RESULT;
 934
 935         pmode->flags = rte_le_to_cpu_32(resp->flags);
 936         /* dflt_vnic bit doesn't exist in the _cfg command */
 937         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
 938         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
 939         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
 940         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
 941
 942         return rc;
 943 }
 944
 945 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
 946                                        struct bnxt_vnic_info *vnic,
 947                                        struct bnxt_plcmodes_cfg *pmode)
 948 {
 949         int rc = 0;
 950         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
 951         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 952
 953         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
 954
 955         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 956         req.flags = rte_cpu_to_le_32(pmode->flags);
 957         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
 958         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
 959         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
 960         req.enables = rte_cpu_to_le_32(
 961             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
 962             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
 963             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
 964         );
 965
 966         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 967
 968         HWRM_CHECK_RESULT;
 969
 970         return rc;
 971 }
 972
 973 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 974 {
 975         int rc = 0;
 976         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
 977         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 978         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
 979         struct bnxt_plcmodes_cfg pmodes;
 980
 981         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
 982         if (rc)
 983                 return rc;
 984
 985         HWRM_PREP(req, VNIC_CFG, -1, resp);
 986
 987         /* Only RSS support for now TBD: COS & LB */
 988         req.enables =
 989             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
 990                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
 991         if (vnic->lb_rule != 0xffff)
 992                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
 993         if (vnic->cos_rule != 0xffff)
 994                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
 995         if (vnic->rss_rule != 0xffff)
 996                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
 997         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
 998         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 999         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1000         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1001         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1002         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1003         req.mru = rte_cpu_to_le_16(vnic->mru);
1004         if (vnic->func_default)
1005                 req.flags |=
1006                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1007         if (vnic->vlan_strip)
1008                 req.flags |=
1009                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1010         if (vnic->bd_stall)
1011                 req.flags |=
1012                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1013         if (vnic->roce_dual)
1014                 req.flags |= rte_cpu_to_le_32(
1015                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1016         if (vnic->roce_only)
1017                 req.flags |= rte_cpu_to_le_32(
1018                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1019         if (vnic->rss_dflt_cr)
1020                 req.flags |= rte_cpu_to_le_32(
1021                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1022
1023         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1024
1025         HWRM_CHECK_RESULT;
1026
1027         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1028
1029         return rc;
1030 }
1031
1032 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1033                 int16_t fw_vf_id)
1034 {
1035         int rc = 0;
1036         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1037         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1038
1039         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1040
1041         req.enables =
1042                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1043         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1044         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1045
1046         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1047
1048         HWRM_CHECK_RESULT;
1049
1050         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1051         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1052         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1053         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1054         vnic->mru = rte_le_to_cpu_16(resp->mru);
1055         vnic->func_default = rte_le_to_cpu_32(
1056                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1057         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1058                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1059         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1060                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1061         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1062                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1063         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1064                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1065         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1066                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1067
1068         return rc;
1069 }
1070
1071 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1072 {
1073         int rc = 0;
1074         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1075         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1076                                                 bp->hwrm_cmd_resp_addr;
1077
1078         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1079
1080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1081
1082         HWRM_CHECK_RESULT;
1083
1084         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1085
1086         return rc;
1087 }
1088
1089 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1090 {
1091         int rc = 0;
1092         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1093         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1094                                                 bp->hwrm_cmd_resp_addr;
1095
1096         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1097
1098         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1099
1100         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1101
1102         HWRM_CHECK_RESULT;
1103
1104         vnic->rss_rule = INVALID_HW_RING_ID;
1105
1106         return rc;
1107 }
1108
1109 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1110 {
1111         int rc = 0;
1112         struct hwrm_vnic_free_input req = {.req_type = 0 };
1113         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1114
1115         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1116                 return rc;
1117
1118         HWRM_PREP(req, VNIC_FREE, -1, resp);
1119
1120         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1121
1122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1123
1124         HWRM_CHECK_RESULT;
1125
1126         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1127         return rc;
1128 }
1129
1130 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1131                            struct bnxt_vnic_info *vnic)
1132 {
1133         int rc = 0;
1134         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1135         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1136
1137         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1138
1139         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1140
1141         req.ring_grp_tbl_addr =
1142             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1143         req.hash_key_tbl_addr =
1144             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1145         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1146
1147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1148
1149         HWRM_CHECK_RESULT;
1150
1151         return rc;
1152 }
1153
1154 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1155                         struct bnxt_vnic_info *vnic)
1156 {
1157         int rc = 0;
1158         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1159         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1160         uint16_t size;
1161
1162         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1163
1164         req.flags = rte_cpu_to_le_32(
1165                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1166
1167         req.enables = rte_cpu_to_le_32(
1168                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1169
1170         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1171         size -= RTE_PKTMBUF_HEADROOM;
1172
1173         req.jumbo_thresh = rte_cpu_to_le_16(size);
1174         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1175
1176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1177
1178         HWRM_CHECK_RESULT;
1179
1180         return rc;
1181 }
1182
1183 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1184                         struct bnxt_vnic_info *vnic, bool enable)
1185 {
1186         int rc = 0;
1187         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1188         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1189
1190         HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1191
1192         if (enable) {
1193                 req.enables = rte_cpu_to_le_32(
1194                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1195                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1196                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1197                 req.flags = rte_cpu_to_le_32(
1198                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1199                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1200                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1201                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1202                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1203                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1204                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1205                 req.max_agg_segs = rte_cpu_to_le_16(5);
1206                 req.max_aggs =
1207                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1208                 req.min_agg_len = rte_cpu_to_le_32(512);
1209         }
1210
1211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1212
1213         HWRM_CHECK_RESULT;
1214
1215         return rc;
1216 }
1217
1218 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1219 {
1220         struct hwrm_func_cfg_input req = {0};
1221         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1222         int rc;
1223
1224         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1225         req.enables = rte_cpu_to_le_32(
1226                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1227         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1228         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1229
1230         HWRM_PREP(req, FUNC_CFG, -1, resp);
1231
1232         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1233         HWRM_CHECK_RESULT;
1234
1235         bp->pf.vf_info[vf].random_mac = false;
1236
1237         return rc;
1238 }
1239
1240 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1241                           struct rte_eth_stats *stats)
1242 {
1243         int rc = 0;
1244         struct hwrm_func_qstats_input req = {.req_type = 0};
1245         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1246
1247         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1248
1249         req.fid = rte_cpu_to_le_16(fid);
1250
1251         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1252
1253         HWRM_CHECK_RESULT;
1254
1255         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1256         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1257         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1258         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1259         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1260         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1261
1262         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1263         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1264         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1265         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1266         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1267         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1268
1269         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1270         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1271
1272         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1273
1274         return rc;
1275 }
1276
1277 /*
1278  * HWRM utility functions
1279  */
1280
1281 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1282 {
1283         unsigned int i;
1284         int rc = 0;
1285
1286         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1287                 struct bnxt_tx_queue *txq;
1288                 struct bnxt_rx_queue *rxq;
1289                 struct bnxt_cp_ring_info *cpr;
1290
1291                 if (i >= bp->rx_cp_nr_rings) {
1292                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1293                         cpr = txq->cp_ring;
1294                 } else {
1295                         rxq = bp->rx_queues[i];
1296                         cpr = rxq->cp_ring;
1297                 }
1298
1299                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1300                 if (rc)
1301                         return rc;
1302         }
1303         return 0;
1304 }
1305
1306 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1307 {
1308         int rc;
1309         unsigned int i;
1310         struct bnxt_cp_ring_info *cpr;
1311
1312         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1313
1314                 if (i >= bp->rx_cp_nr_rings)
1315                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1316                 else
1317                         cpr = bp->rx_queues[i]->cp_ring;
1318                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1319                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1320                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1321                         /*
1322                          * TODO. Need a better way to reset grp_info.stats_ctx
1323                          * for Rx rings only. stats_ctx is not saved for Tx
1324                          * in grp_info.
1325                          */
1326                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1327                         if (rc)
1328                                 return rc;
1329                 }
1330         }
1331         return 0;
1332 }
1333
1334 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1335 {
1336         unsigned int i;
1337         int rc = 0;
1338
1339         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1340                 struct bnxt_tx_queue *txq;
1341                 struct bnxt_rx_queue *rxq;
1342                 struct bnxt_cp_ring_info *cpr;
1343
1344                 if (i >= bp->rx_cp_nr_rings) {
1345                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1346                         cpr = txq->cp_ring;
1347                 } else {
1348                         rxq = bp->rx_queues[i];
1349                         cpr = rxq->cp_ring;
1350                 }
1351
1352                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1353
1354                 if (rc)
1355                         return rc;
1356         }
1357         return rc;
1358 }
1359
1360 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1361 {
1362         uint16_t idx;
1363         uint32_t rc = 0;
1364
1365         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1366
1367                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1368                         RTE_LOG(ERR, PMD,
1369                                 "Attempt to free invalid ring group %d\n",
1370                                 idx);
1371                         continue;
1372                 }
1373
1374                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1375
1376                 if (rc)
1377                         return rc;
1378         }
1379         return rc;
1380 }
1381
1382 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1383                                 unsigned int idx __rte_unused)
1384 {
1385         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1386
1387         bnxt_hwrm_ring_free(bp, cp_ring,
1388                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1389         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1390         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1391         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1392                         sizeof(*cpr->cp_desc_ring));
1393         cpr->cp_raw_cons = 0;
1394 }
1395
1396 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1397 {
1398         unsigned int i;
1399         int rc = 0;
1400
1401         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1402                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1403                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1404                 struct bnxt_ring *ring = txr->tx_ring_struct;
1405                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1406                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1407
1408                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1409                         bnxt_hwrm_ring_free(bp, ring,
1410                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1411                         ring->fw_ring_id = INVALID_HW_RING_ID;
1412                         memset(txr->tx_desc_ring, 0,
1413                                         txr->tx_ring_struct->ring_size *
1414                                         sizeof(*txr->tx_desc_ring));
1415                         memset(txr->tx_buf_ring, 0,
1416                                         txr->tx_ring_struct->ring_size *
1417                                         sizeof(*txr->tx_buf_ring));
1418                         txr->tx_prod = 0;
1419                         txr->tx_cons = 0;
1420                 }
1421                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1422                         bnxt_free_cp_ring(bp, cpr, idx);
1423                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1424                 }
1425         }
1426
1427         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1428                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1429                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1430                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1431                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1432                 unsigned int idx = i + 1;
1433
1434                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1435                         bnxt_hwrm_ring_free(bp, ring,
1436                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1437                         ring->fw_ring_id = INVALID_HW_RING_ID;
1438                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1439                         memset(rxr->rx_desc_ring, 0,
1440                                         rxr->rx_ring_struct->ring_size *
1441                                         sizeof(*rxr->rx_desc_ring));
1442                         memset(rxr->rx_buf_ring, 0,
1443                                         rxr->rx_ring_struct->ring_size *
1444                                         sizeof(*rxr->rx_buf_ring));
1445                         rxr->rx_prod = 0;
1446                         memset(rxr->ag_buf_ring, 0,
1447                                         rxr->ag_ring_struct->ring_size *
1448                                         sizeof(*rxr->ag_buf_ring));
1449                         rxr->ag_prod = 0;
1450                 }
1451                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1452                         bnxt_free_cp_ring(bp, cpr, idx);
1453                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1454                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1455                 }
1456         }
1457
1458         /* Default completion ring */
1459         {
1460                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1461
1462                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1463                         bnxt_free_cp_ring(bp, cpr, 0);
1464                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1465                 }
1466         }
1467
1468         return rc;
1469 }
1470
1471 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1472 {
1473         uint16_t i;
1474         uint32_t rc = 0;
1475
1476         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1477                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1478                 if (rc)
1479                         return rc;
1480         }
1481         return rc;
1482 }
1483
1484 void bnxt_free_hwrm_resources(struct bnxt *bp)
1485 {
1486         /* Release memzone */
1487         rte_free(bp->hwrm_cmd_resp_addr);
1488         bp->hwrm_cmd_resp_addr = NULL;
1489         bp->hwrm_cmd_resp_dma_addr = 0;
1490 }
1491
1492 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1493 {
1494         struct rte_pci_device *pdev = bp->pdev;
1495         char type[RTE_MEMZONE_NAMESIZE];
1496
1497         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1498                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1499         bp->max_req_len = HWRM_MAX_REQ_LEN;
1500         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1501         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1502         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1503         if (bp->hwrm_cmd_resp_addr == NULL)
1504                 return -ENOMEM;
1505         bp->hwrm_cmd_resp_dma_addr =
1506                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1507         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1508                 RTE_LOG(ERR, PMD,
1509                         "unable to map response address to physical memory\n");
1510                 return -ENOMEM;
1511         }
1512         rte_spinlock_init(&bp->hwrm_lock);
1513
1514         return 0;
1515 }
1516
1517 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1518 {
1519         struct bnxt_filter_info *filter;
1520         int rc = 0;
1521
1522         STAILQ_FOREACH(filter, &vnic->filter, next) {
1523                 rc = bnxt_hwrm_clear_filter(bp, filter);
1524                 if (rc)
1525                         break;
1526         }
1527         return rc;
1528 }
1529
1530 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1531 {
1532         struct bnxt_filter_info *filter;
1533         int rc = 0;
1534
1535         STAILQ_FOREACH(filter, &vnic->filter, next) {
1536                 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1537                 if (rc)
1538                         break;
1539         }
1540         return rc;
1541 }
1542
1543 void bnxt_free_tunnel_ports(struct bnxt *bp)
1544 {
1545         if (bp->vxlan_port_cnt)
1546                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1547                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1548         bp->vxlan_port = 0;
1549         if (bp->geneve_port_cnt)
1550                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1551                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1552         bp->geneve_port = 0;
1553 }
1554
1555 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1556 {
1557         struct bnxt_vnic_info *vnic;
1558         unsigned int i;
1559
1560         if (bp->vnic_info == NULL)
1561                 return;
1562
1563         vnic = &bp->vnic_info[0];
1564         if (BNXT_PF(bp))
1565                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1566
1567         /* VNIC resources */
1568         for (i = 0; i < bp->nr_vnics; i++) {
1569                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1570
1571                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1572
1573                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1574
1575                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1576
1577                 bnxt_hwrm_vnic_free(bp, vnic);
1578         }
1579         /* Ring resources */
1580         bnxt_free_all_hwrm_rings(bp);
1581         bnxt_free_all_hwrm_ring_grps(bp);
1582         bnxt_free_all_hwrm_stat_ctxs(bp);
1583         bnxt_free_tunnel_ports(bp);
1584 }
1585
1586 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1587 {
1588         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1589
1590         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1591                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1592
1593         switch (conf_link_speed) {
1594         case ETH_LINK_SPEED_10M_HD:
1595         case ETH_LINK_SPEED_100M_HD:
1596                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1597         }
1598         return hw_link_duplex;
1599 }
1600
1601 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1602 {
1603         uint16_t eth_link_speed = 0;
1604
1605         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1606                 return ETH_LINK_SPEED_AUTONEG;
1607
1608         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1609         case ETH_LINK_SPEED_100M:
1610         case ETH_LINK_SPEED_100M_HD:
1611                 eth_link_speed =
1612                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1613                 break;
1614         case ETH_LINK_SPEED_1G:
1615                 eth_link_speed =
1616                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1617                 break;
1618         case ETH_LINK_SPEED_2_5G:
1619                 eth_link_speed =
1620                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1621                 break;
1622         case ETH_LINK_SPEED_10G:
1623                 eth_link_speed =
1624                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1625                 break;
1626         case ETH_LINK_SPEED_20G:
1627                 eth_link_speed =
1628                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1629                 break;
1630         case ETH_LINK_SPEED_25G:
1631                 eth_link_speed =
1632                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1633                 break;
1634         case ETH_LINK_SPEED_40G:
1635                 eth_link_speed =
1636                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1637                 break;
1638         case ETH_LINK_SPEED_50G:
1639                 eth_link_speed =
1640                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1641                 break;
1642         default:
1643                 RTE_LOG(ERR, PMD,
1644                         "Unsupported link speed %d; default to AUTO\n",
1645                         conf_link_speed);
1646                 break;
1647         }
1648         return eth_link_speed;
1649 }
1650
1651 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1652                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1653                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1654                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1655
1656 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1657 {
1658         uint32_t one_speed;
1659
1660         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1661                 return 0;
1662
1663         if (link_speed & ETH_LINK_SPEED_FIXED) {
1664                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1665
1666                 if (one_speed & (one_speed - 1)) {
1667                         RTE_LOG(ERR, PMD,
1668                                 "Invalid advertised speeds (%u) for port %u\n",
1669                                 link_speed, port_id);
1670                         return -EINVAL;
1671                 }
1672                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1673                         RTE_LOG(ERR, PMD,
1674                                 "Unsupported advertised speed (%u) for port %u\n",
1675                                 link_speed, port_id);
1676                         return -EINVAL;
1677                 }
1678         } else {
1679                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1680                         RTE_LOG(ERR, PMD,
1681                                 "Unsupported advertised speeds (%u) for port %u\n",
1682                                 link_speed, port_id);
1683                         return -EINVAL;
1684                 }
1685         }
1686         return 0;
1687 }
1688
1689 static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
1690 {
1691         uint16_t ret = 0;
1692
1693         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1694                 link_speed = BNXT_SUPPORTED_SPEEDS;
1695
1696         if (link_speed & ETH_LINK_SPEED_100M)
1697                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1698         if (link_speed & ETH_LINK_SPEED_100M_HD)
1699                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1700         if (link_speed & ETH_LINK_SPEED_1G)
1701                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1702         if (link_speed & ETH_LINK_SPEED_2_5G)
1703                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1704         if (link_speed & ETH_LINK_SPEED_10G)
1705                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1706         if (link_speed & ETH_LINK_SPEED_20G)
1707                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1708         if (link_speed & ETH_LINK_SPEED_25G)
1709                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1710         if (link_speed & ETH_LINK_SPEED_40G)
1711                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1712         if (link_speed & ETH_LINK_SPEED_50G)
1713                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1714         return ret;
1715 }
1716
1717 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1718 {
1719         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1720
1721         switch (hw_link_speed) {
1722         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1723                 eth_link_speed = ETH_SPEED_NUM_100M;
1724                 break;
1725         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1726                 eth_link_speed = ETH_SPEED_NUM_1G;
1727                 break;
1728         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1729                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1730                 break;
1731         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1732                 eth_link_speed = ETH_SPEED_NUM_10G;
1733                 break;
1734         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1735                 eth_link_speed = ETH_SPEED_NUM_20G;
1736                 break;
1737         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1738                 eth_link_speed = ETH_SPEED_NUM_25G;
1739                 break;
1740         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1741                 eth_link_speed = ETH_SPEED_NUM_40G;
1742                 break;
1743         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1744                 eth_link_speed = ETH_SPEED_NUM_50G;
1745                 break;
1746         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1747         default:
1748                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1749                         hw_link_speed);
1750                 break;
1751         }
1752         return eth_link_speed;
1753 }
1754
1755 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1756 {
1757         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1758
1759         switch (hw_link_duplex) {
1760         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1761         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1762                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1763                 break;
1764         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1765                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1766                 break;
1767         default:
1768                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1769                         hw_link_duplex);
1770                 break;
1771         }
1772         return eth_link_duplex;
1773 }
1774
1775 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1776 {
1777         int rc = 0;
1778         struct bnxt_link_info *link_info = &bp->link_info;
1779
1780         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1781         if (rc) {
1782                 RTE_LOG(ERR, PMD,
1783                         "Get link config failed with rc %d\n", rc);
1784                 goto exit;
1785         }
1786         if (link_info->link_up)
1787                 link->link_speed =
1788                         bnxt_parse_hw_link_speed(link_info->link_speed);
1789         else
1790                 link->link_speed = ETH_LINK_SPEED_10M;
1791         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1792         link->link_status = link_info->link_up;
1793         link->link_autoneg = link_info->auto_mode ==
1794                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1795                 ETH_LINK_SPEED_FIXED : ETH_LINK_SPEED_AUTONEG;
1796 exit:
1797         return rc;
1798 }
1799
1800 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1801 {
1802         int rc = 0;
1803         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1804         struct bnxt_link_info link_req;
1805         uint16_t speed;
1806
1807         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1808                 return 0;
1809
1810         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1811                         bp->eth_dev->data->port_id);
1812         if (rc)
1813                 goto error;
1814
1815         memset(&link_req, 0, sizeof(link_req));
1816         link_req.link_up = link_up;
1817         if (!link_up)
1818                 goto port_phy_cfg;
1819
1820         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1821         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1822         if (speed == 0) {
1823                 link_req.phy_flags |=
1824                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1825                 link_req.auto_mode =
1826                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1827                 link_req.auto_link_speed_mask =
1828                         bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
1829         } else {
1830                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1831                 link_req.link_speed = speed;
1832                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1833         }
1834         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1835         link_req.auto_pause = bp->link_info.auto_pause;
1836         link_req.force_pause = bp->link_info.force_pause;
1837
1838 port_phy_cfg:
1839         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1840         if (rc) {
1841                 RTE_LOG(ERR, PMD,
1842                         "Set link config failed with rc %d\n", rc);
1843         }
1844
1845         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1846 error:
1847         return rc;
1848 }
1849
1850 /* JIRA 22088 */
1851 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1852 {
1853         struct hwrm_func_qcfg_input req = {0};
1854         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1855         int rc = 0;
1856
1857         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1858         req.fid = rte_cpu_to_le_16(0xffff);
1859
1860         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1861
1862         HWRM_CHECK_RESULT;
1863
1864         /* Hard Coded.. 0xfff VLAN ID mask */
1865         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1866
1867         switch (resp->port_partition_type) {
1868         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1869         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1870         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1871                 bp->port_partition_type = resp->port_partition_type;
1872                 break;
1873         default:
1874                 bp->port_partition_type = 0;
1875                 break;
1876         }
1877
1878         return rc;
1879 }
1880
1881 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1882                                    struct hwrm_func_qcaps_output *qcaps)
1883 {
1884         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1885         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1886                sizeof(qcaps->mac_address));
1887         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
1888         qcaps->max_rx_rings = fcfg->num_rx_rings;
1889         qcaps->max_tx_rings = fcfg->num_tx_rings;
1890         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
1891         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
1892         qcaps->max_vfs = 0;
1893         qcaps->first_vf_id = 0;
1894         qcaps->max_vnics = fcfg->num_vnics;
1895         qcaps->max_decap_records = 0;
1896         qcaps->max_encap_records = 0;
1897         qcaps->max_tx_wm_flows = 0;
1898         qcaps->max_tx_em_flows = 0;
1899         qcaps->max_rx_wm_flows = 0;
1900         qcaps->max_rx_em_flows = 0;
1901         qcaps->max_flow_id = 0;
1902         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
1903         qcaps->max_sp_tx_rings = 0;
1904         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
1905 }
1906
1907 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
1908 {
1909         struct hwrm_func_cfg_input req = {0};
1910         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1911         int rc;
1912
1913         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1914                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1915                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1916                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1917                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1918                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1919                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1920                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1921                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1922                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1923         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
1924         req.mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1925                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
1926         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1927                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
1928         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1929         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
1930         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
1931         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
1932         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
1933         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
1934         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
1935         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
1936         req.fid = rte_cpu_to_le_16(0xffff);
1937
1938         HWRM_PREP(req, FUNC_CFG, -1, resp);
1939
1940         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1941         HWRM_CHECK_RESULT;
1942
1943         return rc;
1944 }
1945
1946 static void populate_vf_func_cfg_req(struct bnxt *bp,
1947                                      struct hwrm_func_cfg_input *req,
1948                                      int num_vfs)
1949 {
1950         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
1951                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
1952                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
1953                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1954                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1955                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1956                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1957                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1958                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
1959                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
1960
1961         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1962                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
1963         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1964                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
1965         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
1966                                                 (num_vfs + 1));
1967         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
1968         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
1969                                                (num_vfs + 1));
1970         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
1971         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
1972         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
1973         /* TODO: For now, do not support VMDq/RFS on VFs. */
1974         req->num_vnics = rte_cpu_to_le_16(1);
1975         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
1976                                                  (num_vfs + 1));
1977 }
1978
1979 static void add_random_mac_if_needed(struct bnxt *bp,
1980                                      struct hwrm_func_cfg_input *cfg_req,
1981                                      int vf)
1982 {
1983         struct ether_addr mac;
1984
1985         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
1986                 return;
1987
1988         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
1989                 cfg_req->enables |=
1990                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1991                 eth_random_addr(cfg_req->dflt_mac_addr);
1992                 bp->pf.vf_info[vf].random_mac = true;
1993         } else {
1994                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
1995         }
1996 }
1997
1998 static void reserve_resources_from_vf(struct bnxt *bp,
1999                                       struct hwrm_func_cfg_input *cfg_req,
2000                                       int vf)
2001 {
2002         struct hwrm_func_qcaps_input req = {0};
2003         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2004         int rc;
2005
2006         /* Get the actual allocated values now */
2007         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2008         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2009         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2010
2011         if (rc) {
2012                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2013                 copy_func_cfg_to_qcaps(cfg_req, resp);
2014         } else if (resp->error_code) {
2015                 rc = rte_le_to_cpu_16(resp->error_code);
2016                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2017                 copy_func_cfg_to_qcaps(cfg_req, resp);
2018         }
2019
2020         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2021         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2022         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2023         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2024         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2025         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2026         /*
2027          * TODO: While not supporting VMDq with VFs, max_vnics is always
2028          * forced to 1 in this case
2029          */
2030         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2031         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2032 }
2033
2034 static int update_pf_resource_max(struct bnxt *bp)
2035 {
2036         struct hwrm_func_qcfg_input req = {0};
2037         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2038         int rc;
2039
2040         /* And copy the allocated numbers into the pf struct */
2041         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2042         req.fid = rte_cpu_to_le_16(0xffff);
2043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2044         HWRM_CHECK_RESULT;
2045
2046         /* Only TX ring value reflects actual allocation? TODO */
2047         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2048         bp->pf.evb_mode = resp->evb_mode;
2049
2050         return rc;
2051 }
2052
2053 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2054 {
2055         int rc;
2056
2057         if (!BNXT_PF(bp)) {
2058                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2059                 return -1;
2060         }
2061
2062         rc = bnxt_hwrm_func_qcaps(bp);
2063         if (rc)
2064                 return rc;
2065
2066         bp->pf.func_cfg_flags &=
2067                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2068                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2069         bp->pf.func_cfg_flags |=
2070                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2071         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2072         return rc;
2073 }
2074
2075 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2076 {
2077         struct hwrm_func_cfg_input req = {0};
2078         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2079         int i;
2080         size_t sz;
2081         int rc = 0;
2082         size_t req_buf_sz;
2083
2084         if (!BNXT_PF(bp)) {
2085                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2086                 return -1;
2087         }
2088
2089         rc = bnxt_hwrm_func_qcaps(bp);
2090
2091         if (rc)
2092                 return rc;
2093
2094         bp->pf.active_vfs = num_vfs;
2095
2096         /*
2097          * First, configure the PF to only use one TX ring.  This ensures that
2098          * there are enough rings for all VFs.
2099          *
2100          * If we don't do this, when we call func_alloc() later, we will lock
2101          * extra rings to the PF that won't be available during func_cfg() of
2102          * the VFs.
2103          *
2104          * This has been fixed with firmware versions above 20.6.54
2105          */
2106         bp->pf.func_cfg_flags &=
2107                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2108                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2109         bp->pf.func_cfg_flags |=
2110                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2111         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2112         if (rc)
2113                 return rc;
2114
2115         /*
2116          * Now, create and register a buffer to hold forwarded VF requests
2117          */
2118         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2119         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2120                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2121         if (bp->pf.vf_req_buf == NULL) {
2122                 rc = -ENOMEM;
2123                 goto error_free;
2124         }
2125         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2126                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2127         for (i = 0; i < num_vfs; i++)
2128                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2129                                         (i * HWRM_MAX_REQ_LEN);
2130
2131         rc = bnxt_hwrm_func_buf_rgtr(bp);
2132         if (rc)
2133                 goto error_free;
2134
2135         populate_vf_func_cfg_req(bp, &req, num_vfs);
2136
2137         bp->pf.active_vfs = 0;
2138         for (i = 0; i < num_vfs; i++) {
2139                 add_random_mac_if_needed(bp, &req, i);
2140
2141                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2142                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2143                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2144                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2145
2146                 /* Clear enable flag for next pass */
2147                 req.enables &= ~rte_cpu_to_le_32(
2148                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2149
2150                 if (rc || resp->error_code) {
2151                         RTE_LOG(ERR, PMD,
2152                                 "Failed to initizlie VF %d\n", i);
2153                         RTE_LOG(ERR, PMD,
2154                                 "Not all VFs available. (%d, %d)\n",
2155                                 rc, resp->error_code);
2156                         break;
2157                 }
2158
2159                 reserve_resources_from_vf(bp, &req, i);
2160                 bp->pf.active_vfs++;
2161         }
2162
2163         /*
2164          * Now configure the PF to use "the rest" of the resources
2165          * We're using STD_TX_RING_MODE here though which will limit the TX
2166          * rings.  This will allow QoS to function properly.  Not setting this
2167          * will cause PF rings to break bandwidth settings.
2168          */
2169         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2170         if (rc)
2171                 goto error_free;
2172
2173         rc = update_pf_resource_max(bp);
2174         if (rc)
2175                 goto error_free;
2176
2177         return rc;
2178
2179 error_free:
2180         bnxt_hwrm_func_buf_unrgtr(bp);
2181         return rc;
2182 }
2183
2184 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2185 {
2186         struct hwrm_func_cfg_input req = {0};
2187         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2188         int rc;
2189
2190         HWRM_PREP(req, FUNC_CFG, -1, resp);
2191
2192         req.fid = rte_cpu_to_le_16(0xffff);
2193         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2194         req.evb_mode = bp->pf.evb_mode;
2195
2196         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2197         HWRM_CHECK_RESULT;
2198
2199         return rc;
2200 }
2201
2202 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2203                                 uint8_t tunnel_type)
2204 {
2205         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2206         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2207         int rc = 0;
2208
2209         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2210         req.tunnel_type = tunnel_type;
2211         req.tunnel_dst_port_val = port;
2212         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2213         HWRM_CHECK_RESULT;
2214
2215         switch (tunnel_type) {
2216         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2217                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2218                 bp->vxlan_port = port;
2219                 break;
2220         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2221                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2222                 bp->geneve_port = port;
2223                 break;
2224         default:
2225                 break;
2226         }
2227         return rc;
2228 }
2229
2230 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2231                                 uint8_t tunnel_type)
2232 {
2233         struct hwrm_tunnel_dst_port_free_input req = {0};
2234         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2235         int rc = 0;
2236
2237         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2238         req.tunnel_type = tunnel_type;
2239         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2241         HWRM_CHECK_RESULT;
2242
2243         return rc;
2244 }
2245
2246 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf)
2247 {
2248         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2249         struct hwrm_func_cfg_input req = {0};
2250         int rc;
2251
2252         HWRM_PREP(req, FUNC_CFG, -1, resp);
2253         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2254         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2255         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2256         HWRM_CHECK_RESULT;
2257
2258         return rc;
2259 }
2260
2261 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2262 {
2263         int rc = 0;
2264         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2265         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2266
2267         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2268
2269         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2270         req.req_buf_page_size = rte_cpu_to_le_16(
2271                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2272         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2273         req.req_buf_page_addr[0] =
2274                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2275         if (req.req_buf_page_addr[0] == 0) {
2276                 RTE_LOG(ERR, PMD,
2277                         "unable to map buffer address to physical memory\n");
2278                 return -ENOMEM;
2279         }
2280
2281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2282
2283         HWRM_CHECK_RESULT;
2284
2285         return rc;
2286 }
2287
2288 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2289 {
2290         int rc = 0;
2291         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2292         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2293
2294         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2295
2296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2297
2298         HWRM_CHECK_RESULT;
2299
2300         return rc;
2301 }
2302
2303 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2304 {
2305         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2306         struct hwrm_func_cfg_input req = {0};
2307         int rc;
2308
2309         HWRM_PREP(req, FUNC_CFG, -1, resp);
2310         req.fid = rte_cpu_to_le_16(0xffff);
2311         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2312         req.enables = rte_cpu_to_le_32(
2313                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2314         req.async_event_cr = rte_cpu_to_le_16(
2315                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2317         HWRM_CHECK_RESULT;
2318
2319         return rc;
2320 }
2321
2322 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2323 {
2324         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2325         struct hwrm_func_vf_cfg_input req = {0};
2326         int rc;
2327
2328         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2329         req.enables = rte_cpu_to_le_32(
2330                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2331         req.async_event_cr = rte_cpu_to_le_16(
2332                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2333         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2334         HWRM_CHECK_RESULT;
2335
2336         return rc;
2337 }
2338
2339 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2340 {
2341         struct hwrm_func_cfg_input req = {0};
2342         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2343         uint16_t dflt_vlan, fid;
2344         uint32_t func_cfg_flags;
2345         int rc = 0;
2346
2347         HWRM_PREP(req, FUNC_CFG, -1, resp);
2348
2349         if (is_vf) {
2350                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2351                 fid = bp->pf.vf_info[vf].fid;
2352                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2353         } else {
2354                 fid = rte_cpu_to_le_16(0xffff);
2355                 func_cfg_flags = bp->pf.func_cfg_flags;
2356                 dflt_vlan = bp->vlan;
2357         }
2358
2359         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2360         req.fid = rte_cpu_to_le_16(fid);
2361         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2362         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2363
2364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2365         HWRM_CHECK_RESULT;
2366
2367         return rc;
2368 }
2369
2370 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2371                         uint16_t max_bw, uint16_t enables)
2372 {
2373         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2374         struct hwrm_func_cfg_input req = {0};
2375         int rc;
2376
2377         HWRM_PREP(req, FUNC_CFG, -1, resp);
2378         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2379         req.enables |= rte_cpu_to_le_32(enables);
2380         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2381         req.max_bw = rte_cpu_to_le_32(max_bw);
2382         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2383         HWRM_CHECK_RESULT;
2384
2385         return rc;
2386 }
2387
2388 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2389                               void *encaped, size_t ec_size)
2390 {
2391         int rc = 0;
2392         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2393         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2394
2395         if (ec_size > sizeof(req.encap_request))
2396                 return -1;
2397
2398         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2399
2400         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2401         memcpy(req.encap_request, encaped, ec_size);
2402
2403         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2404
2405         HWRM_CHECK_RESULT;
2406
2407         return rc;
2408 }
2409
2410 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2411                                        struct ether_addr *mac)
2412 {
2413         struct hwrm_func_qcfg_input req = {0};
2414         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2415         int rc;
2416
2417         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2418         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2419         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2420
2421         HWRM_CHECK_RESULT;
2422
2423         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2424         return rc;
2425 }
2426
2427 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2428                             void *encaped, size_t ec_size)
2429 {
2430         int rc = 0;
2431         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2432         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2433
2434         if (ec_size > sizeof(req.encap_request))
2435                 return -1;
2436
2437         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2438
2439         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2440         memcpy(req.encap_request, encaped, ec_size);
2441
2442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2443
2444         HWRM_CHECK_RESULT;
2445
2446         return rc;
2447 }
2448
2449 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2450                          struct rte_eth_stats *stats)
2451 {
2452         int rc = 0;
2453         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2454         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2455
2456         HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2457
2458         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2459
2460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2461
2462         HWRM_CHECK_RESULT;
2463
2464         stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2465         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2466         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2467         stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2468         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2469         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2470
2471         stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2472         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2473         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2474         stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2475         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2476         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2477
2478         stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2479         stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2480         stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2481
2482         return rc;
2483 }
2484
2485 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2486 {
2487         struct hwrm_port_qstats_input req = {0};
2488         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2489         struct bnxt_pf_info *pf = &bp->pf;
2490         int rc;
2491
2492         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2493                 return 0;
2494
2495         HWRM_PREP(req, PORT_QSTATS, -1, resp);
2496         req.port_id = rte_cpu_to_le_16(pf->port_id);
2497         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2498         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2499         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2500         HWRM_CHECK_RESULT;
2501         return rc;
2502 }
2503
2504 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2505 {
2506         struct hwrm_port_clr_stats_input req = {0};
2507         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2508         struct bnxt_pf_info *pf = &bp->pf;
2509         int rc;
2510
2511         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2512                 return 0;
2513
2514         HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2515         req.port_id = rte_cpu_to_le_16(pf->port_id);
2516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2517         HWRM_CHECK_RESULT;
2518         return rc;
2519 }
2520
2521 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2522 {
2523         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2524         struct hwrm_port_led_qcaps_input req = {0};
2525         int rc;
2526
2527         if (BNXT_VF(bp))
2528                 return 0;
2529
2530         HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2531         req.port_id = bp->pf.port_id;
2532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2533         HWRM_CHECK_RESULT;
2534
2535         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2536                 unsigned int i;
2537
2538                 bp->num_leds = resp->num_leds;
2539                 memcpy(bp->leds, &resp->led0_id,
2540                         sizeof(bp->leds[0]) * bp->num_leds);
2541                 for (i = 0; i < bp->num_leds; i++) {
2542                         struct bnxt_led_info *led = &bp->leds[i];
2543
2544                         uint16_t caps = led->led_state_caps;
2545
2546                         if (!led->led_group_id ||
2547                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2548                                 bp->num_leds = 0;
2549                                 break;
2550                         }
2551                 }
2552         }
2553         return rc;
2554 }
2555
2556 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2557 {
2558         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2559         struct hwrm_port_led_cfg_input req = {0};
2560         struct bnxt_led_cfg *led_cfg;
2561         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2562         uint16_t duration = 0;
2563         int rc, i;
2564
2565         if (!bp->num_leds || BNXT_VF(bp))
2566                 return -EOPNOTSUPP;
2567
2568         HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2569         if (led_on) {
2570                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2571                 duration = rte_cpu_to_le_16(500);
2572         }
2573         req.port_id = bp->pf.port_id;
2574         req.num_leds = bp->num_leds;
2575         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2576         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2577                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2578                 led_cfg->led_id = bp->leds[i].led_id;
2579                 led_cfg->led_state = led_state;
2580                 led_cfg->led_blink_on = duration;
2581                 led_cfg->led_blink_off = duration;
2582                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2583         }
2584
2585         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2586         HWRM_CHECK_RESULT;
2587
2588         return rc;
2589 }
2590
2591 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2592                                         uint16_t *vnic_ids)
2593 {
2594         struct hwrm_func_vf_vnic_ids_query_input req = {0};
2595         struct hwrm_func_vf_vnic_ids_query_output *resp =
2596                                                 bp->hwrm_cmd_resp_addr;
2597         int rc;
2598
2599         /* First query all VNIC ids */
2600         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2601
2602         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2603         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2604         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2605
2606         if (req.vnic_id_tbl_addr == 0) {
2607                 RTE_LOG(ERR, PMD,
2608                 "unable to map VNIC ID table address to physical memory\n");
2609                 return -ENOMEM;
2610         }
2611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2612         if (rc) {
2613                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2614                 return -1;
2615         } else if (resp->error_code) {
2616                 rc = rte_le_to_cpu_16(resp->error_code);
2617                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2618                 return -1;
2619         }
2620
2621         return rte_le_to_cpu_32(resp->vnic_id_cnt);
2622 }
2623
2624 /*
2625  * This function queries the VNIC IDs  for a specified VF. It then calls
2626  * the vnic_cb to update the necessary field in vnic_info with cbdata.
2627  * Then it calls the hwrm_cb function to program this new vnic configuration.
2628  */
2629 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2630         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2631         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2632 {
2633         struct bnxt_vnic_info vnic;
2634         int rc = 0;
2635         int i, num_vnic_ids;
2636         uint16_t *vnic_ids;
2637         size_t vnic_id_sz;
2638         size_t sz;
2639
2640         /* First query all VNIC ids */
2641         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2642         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2643                         RTE_CACHE_LINE_SIZE);
2644         if (vnic_ids == NULL) {
2645                 rc = -ENOMEM;
2646                 return rc;
2647         }
2648         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2649                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2650
2651         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2652
2653         if (num_vnic_ids < 0)
2654                 return num_vnic_ids;
2655
2656         /* Retrieve VNIC, update bd_stall then update */
2657
2658         for (i = 0; i < num_vnic_ids; i++) {
2659                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2660                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2661                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2662                 if (rc)
2663                         break;
2664                 if (vnic.mru == 4)      /* Indicates unallocated */
2665                         continue;
2666
2667                 vnic_cb(&vnic, cbdata);
2668
2669                 rc = hwrm_cb(bp, &vnic);
2670                 if (rc)
2671                         break;
2672         }
2673
2674         rte_free(vnic_ids);
2675
2676         return rc;
2677 }
2678
2679 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2680                                               bool on)
2681 {
2682         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2683         struct hwrm_func_cfg_input req = {0};
2684         int rc;
2685
2686         HWRM_PREP(req, FUNC_CFG, -1, resp);
2687         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2688         req.enables |= rte_cpu_to_le_32(
2689                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2690         req.vlan_antispoof_mode = on ?
2691                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2692                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2693         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2694         HWRM_CHECK_RESULT;
2695
2696         return rc;
2697 }
2698
2699 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2700 {
2701         struct bnxt_vnic_info vnic;
2702         uint16_t *vnic_ids;
2703         size_t vnic_id_sz;
2704         int num_vnic_ids, i;
2705         size_t sz;
2706         int rc;
2707
2708         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2709         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2710                         RTE_CACHE_LINE_SIZE);
2711         if (vnic_ids == NULL) {
2712                 rc = -ENOMEM;
2713                 return rc;
2714         }
2715
2716         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2717                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2718
2719         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2720         if (rc <= 0)
2721                 goto exit;
2722         num_vnic_ids = rc;
2723
2724         /*
2725          * Loop through to find the default VNIC ID.
2726          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2727          * by sending the hwrm_func_qcfg command to the firmware.
2728          */
2729         for (i = 0; i < num_vnic_ids; i++) {
2730                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2731                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2732                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2733                                         bp->pf.first_vf_id + vf);
2734                 if (rc)
2735                         goto exit;
2736                 if (vnic.func_default) {
2737                         rte_free(vnic_ids);
2738                         return vnic.fw_vnic_id;
2739                 }
2740         }
2741         /* Could not find a default VNIC. */
2742         RTE_LOG(ERR, PMD, "No default VNIC\n");
2743 exit:
2744         rte_free(vnic_ids);
2745         return -1;
2746 }