drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                2000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 175 {
 176         int rc;
 177
 178         rte_spinlock_lock(&bp->hwrm_lock);
 179         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 180         rte_spinlock_unlock(&bp->hwrm_lock);
 181         return rc;
 182 }
 183
 184 #define HWRM_PREP(req, type, cr, resp) \
 185         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 186         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 187         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 188         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 189         req.target_id = rte_cpu_to_le_16(0xffff); \
 190         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 191
 192 #define HWRM_CHECK_RESULT \
 193         { \
 194                 if (rc) { \
 195                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 196                                 __func__, rc); \
 197                         return rc; \
 198                 } \
 199                 if (resp->error_code) { \
 200                         rc = rte_le_to_cpu_16(resp->error_code); \
 201                         if (resp->resp_len >= 16) { \
 202                                 struct hwrm_err_output *tmp_hwrm_err_op = \
 203                                                         (void *)resp; \
 204                                 RTE_LOG(ERR, PMD, \
 205                                         "%s error %d:%d:%08x:%04x\n", \
 206                                         __func__, \
 207                                         rc, tmp_hwrm_err_op->cmd_err, \
 208                                         rte_le_to_cpu_32(\
 209                                                 tmp_hwrm_err_op->opaque_0), \
 210                                         rte_le_to_cpu_16(\
 211                                                 tmp_hwrm_err_op->opaque_1)); \
 212                         } \
 213                         else { \
 214                                 RTE_LOG(ERR, PMD, \
 215                                         "%s error %d\n", __func__, rc); \
 216                         } \
 217                         return rc; \
 218                 } \
 219         }
 220
 221 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 222 {
 223         int rc = 0;
 224         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 225         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 226
 227         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 228         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 229         req.mask = 0;
 230
 231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 232
 233         HWRM_CHECK_RESULT;
 234
 235         return rc;
 236 }
 237
 238 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 239                                  struct bnxt_vnic_info *vnic,
 240                                  uint16_t vlan_count,
 241                                  struct bnxt_vlan_table_entry *vlan_table)
 242 {
 243         int rc = 0;
 244         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 245         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 246         uint32_t mask = 0;
 247
 248         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 249         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 250
 251         /* FIXME add multicast flag, when multicast adding options is supported
 252          * by ethtool.
 253          */
 254         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 255                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 256         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 257                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 258         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 259                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 260         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 261                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 262         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 263                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 264         if (vnic->mc_addr_cnt) {
 265                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 266                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 267                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 268         }
 269         if (vlan_count && vlan_table) {
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 271                 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
 272                          rte_mem_virt2phy(vlan_table));
 273                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 274         }
 275         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 276                                     mask);
 277
 278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 279
 280         HWRM_CHECK_RESULT;
 281
 282         return rc;
 283 }
 284
 285 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 286                         uint16_t vlan_count,
 287                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 288 {
 289         int rc = 0;
 290         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 291         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 292                                                 bp->hwrm_cmd_resp_addr;
 293
 294         /*
 295          * Older HWRM versions did not support this command, and the set_rx_mask
 296          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 297          * removed from set_rx_mask call, and this command was added.
 298          *
 299          * This command is also present from 1.7.8.11 and higher,
 300          * as well as 1.7.8.0
 301          */
 302         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 303                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 304                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 305                                         (11)))
 306                                 return 0;
 307                 }
 308         }
 309         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, -1, resp);
 310         req.fid = rte_cpu_to_le_16(fid);
 311
 312         req.vlan_tag_mask_tbl_addr =
 313                 rte_cpu_to_le_64(rte_mem_virt2phy(vlan_table));
 314         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 315
 316         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 317
 318         HWRM_CHECK_RESULT;
 319
 320         return rc;
 321 }
 322
 323 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 324                            struct bnxt_filter_info *filter)
 325 {
 326         int rc = 0;
 327         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 328         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 329
 330         if (filter->fw_l2_filter_id == UINT64_MAX)
 331                 return 0;
 332
 333         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 334
 335         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 336
 337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 338
 339         HWRM_CHECK_RESULT;
 340
 341         filter->fw_l2_filter_id = -1;
 342
 343         return 0;
 344 }
 345
 346 int bnxt_hwrm_set_filter(struct bnxt *bp,
 347                          uint16_t dst_id,
 348                          struct bnxt_filter_info *filter)
 349 {
 350         int rc = 0;
 351         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 352         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 353         uint32_t enables = 0;
 354
 355         if (filter->fw_l2_filter_id != UINT64_MAX)
 356                 bnxt_hwrm_clear_filter(bp, filter);
 357
 358         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 359
 360         req.flags = rte_cpu_to_le_32(filter->flags);
 361
 362         enables = filter->enables |
 363               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 364         req.dst_id = rte_cpu_to_le_16(dst_id);
 365
 366         if (enables &
 367             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 368                 memcpy(req.l2_addr, filter->l2_addr,
 369                        ETHER_ADDR_LEN);
 370         if (enables &
 371             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 372                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 373                        ETHER_ADDR_LEN);
 374         if (enables &
 375             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 376                 req.l2_ovlan = filter->l2_ovlan;
 377         if (enables &
 378             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 379                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 380         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 381                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 382         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 383                 req.src_type = filter->src_type;
 384
 385         req.enables = rte_cpu_to_le_32(enables);
 386
 387         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 388
 389         HWRM_CHECK_RESULT;
 390
 391         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 392
 393         return rc;
 394 }
 395
 396 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 397 {
 398         int rc = 0;
 399         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 400         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 401         uint16_t new_max_vfs;
 402         int i;
 403
 404         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 405
 406         req.fid = rte_cpu_to_le_16(0xffff);
 407
 408         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 409
 410         HWRM_CHECK_RESULT;
 411
 412         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 413         if (BNXT_PF(bp)) {
 414                 bp->pf.port_id = resp->port_id;
 415                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 416                 new_max_vfs = bp->pdev->max_vfs;
 417                 if (new_max_vfs != bp->pf.max_vfs) {
 418                         if (bp->pf.vf_info)
 419                                 rte_free(bp->pf.vf_info);
 420                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 421                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 422                         bp->pf.max_vfs = new_max_vfs;
 423                         for (i = 0; i < new_max_vfs; i++) {
 424                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 425                                 bp->pf.vf_info[i].vlan_table =
 426                                         rte_zmalloc("VF VLAN table",
 427                                                     getpagesize(),
 428                                                     getpagesize());
 429                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 430                                         RTE_LOG(ERR, PMD,
 431                                         "Fail to alloc VLAN table for VF %d\n",
 432                                         i);
 433                                 else
 434                                         rte_mem_lock_page(
 435                                                 bp->pf.vf_info[i].vlan_table);
 436                                 bp->pf.vf_info[i].vlan_as_table =
 437                                         rte_zmalloc("VF VLAN AS table",
 438                                                     getpagesize(),
 439                                                     getpagesize());
 440                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 441                                         RTE_LOG(ERR, PMD,
 442                                         "Alloc VLAN AS table for VF %d fail\n",
 443                                         i);
 444                                 else
 445                                         rte_mem_lock_page(
 446                                                bp->pf.vf_info[i].vlan_as_table);
 447                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 448                         }
 449                 }
 450         }
 451
 452         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 453         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 454         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 455         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 456         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 457         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 458         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 459         /* TODO: For now, do not support VMDq/RFS on VFs. */
 460         if (BNXT_PF(bp)) {
 461                 if (bp->pf.max_vfs)
 462                         bp->max_vnics = 1;
 463                 else
 464                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 465         } else {
 466                 bp->max_vnics = 1;
 467         }
 468         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 469         if (BNXT_PF(bp))
 470                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 471
 472         return rc;
 473 }
 474
 475 int bnxt_hwrm_func_reset(struct bnxt *bp)
 476 {
 477         int rc = 0;
 478         struct hwrm_func_reset_input req = {.req_type = 0 };
 479         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 480
 481         HWRM_PREP(req, FUNC_RESET, -1, resp);
 482
 483         req.enables = rte_cpu_to_le_32(0);
 484
 485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 486
 487         HWRM_CHECK_RESULT;
 488
 489         return rc;
 490 }
 491
 492 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 493 {
 494         int rc;
 495         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 496         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 497
 498         if (bp->flags & BNXT_FLAG_REGISTERED)
 499                 return 0;
 500
 501         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 502         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 503                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 504         req.ver_maj = RTE_VER_YEAR;
 505         req.ver_min = RTE_VER_MONTH;
 506         req.ver_upd = RTE_VER_MINOR;
 507
 508         if (BNXT_PF(bp)) {
 509                 req.enables |= rte_cpu_to_le_32(
 510                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 511                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 512                        RTE_MIN(sizeof(req.vf_req_fwd),
 513                                sizeof(bp->pf.vf_req_fwd)));
 514         }
 515
 516         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 517         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 518
 519         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 520
 521         HWRM_CHECK_RESULT;
 522
 523         bp->flags |= BNXT_FLAG_REGISTERED;
 524
 525         return rc;
 526 }
 527
 528 int bnxt_hwrm_ver_get(struct bnxt *bp)
 529 {
 530         int rc = 0;
 531         struct hwrm_ver_get_input req = {.req_type = 0 };
 532         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 533         uint32_t my_version;
 534         uint32_t fw_version;
 535         uint16_t max_resp_len;
 536         char type[RTE_MEMZONE_NAMESIZE];
 537         uint32_t dev_caps_cfg;
 538
 539         bp->max_req_len = HWRM_MAX_REQ_LEN;
 540         HWRM_PREP(req, VER_GET, -1, resp);
 541
 542         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 543         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 544         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 545
 546         /*
 547          * Hold the lock since we may be adjusting the response pointers.
 548          */
 549         rte_spinlock_lock(&bp->hwrm_lock);
 550         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 551
 552         HWRM_CHECK_RESULT;
 553
 554         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 555                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 556                 resp->hwrm_intf_upd,
 557                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 558         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 559                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 560         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 561                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 562
 563         my_version = HWRM_VERSION_MAJOR << 16;
 564         my_version |= HWRM_VERSION_MINOR << 8;
 565         my_version |= HWRM_VERSION_UPDATE;
 566
 567         fw_version = resp->hwrm_intf_maj << 16;
 568         fw_version |= resp->hwrm_intf_min << 8;
 569         fw_version |= resp->hwrm_intf_upd;
 570
 571         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 572                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 573                 rc = -EINVAL;
 574                 goto error;
 575         }
 576
 577         if (my_version != fw_version) {
 578                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 579                 if (my_version < fw_version) {
 580                         RTE_LOG(INFO, PMD,
 581                                 "Firmware API version is newer than driver.\n");
 582                         RTE_LOG(INFO, PMD,
 583                                 "The driver may be missing features.\n");
 584                 } else {
 585                         RTE_LOG(INFO, PMD,
 586                                 "Firmware API version is older than driver.\n");
 587                         RTE_LOG(INFO, PMD,
 588                                 "Not all driver features may be functional.\n");
 589                 }
 590         }
 591
 592         if (bp->max_req_len > resp->max_req_win_len) {
 593                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 594                 rc = -EINVAL;
 595         }
 596         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 597         max_resp_len = resp->max_resp_len;
 598         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 599
 600         if (bp->max_resp_len != max_resp_len) {
 601                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 602                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 603                         bp->pdev->addr.devid, bp->pdev->addr.function);
 604
 605                 rte_free(bp->hwrm_cmd_resp_addr);
 606
 607                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 608                 if (bp->hwrm_cmd_resp_addr == NULL) {
 609                         rc = -ENOMEM;
 610                         goto error;
 611                 }
 612                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 613                 bp->hwrm_cmd_resp_dma_addr =
 614                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 615                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 616                         RTE_LOG(ERR, PMD,
 617                         "Unable to map response buffer to physical memory.\n");
 618                         rc = -ENOMEM;
 619                         goto error;
 620                 }
 621                 bp->max_resp_len = max_resp_len;
 622         }
 623
 624         if ((dev_caps_cfg &
 625                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 626             (dev_caps_cfg &
 627              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 628                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 629
 630                 rte_free(bp->hwrm_short_cmd_req_addr);
 631
 632                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 633                                                         bp->max_req_len, 0);
 634                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 635                         rc = -ENOMEM;
 636                         goto error;
 637                 }
 638                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 639                 bp->hwrm_short_cmd_req_dma_addr =
 640                         rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
 641                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 642                         rte_free(bp->hwrm_short_cmd_req_addr);
 643                         RTE_LOG(ERR, PMD,
 644                                 "Unable to map buffer to physical memory.\n");
 645                         rc = -ENOMEM;
 646                         goto error;
 647                 }
 648
 649                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 650         }
 651
 652 error:
 653         rte_spinlock_unlock(&bp->hwrm_lock);
 654         return rc;
 655 }
 656
 657 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 658 {
 659         int rc;
 660         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 661         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 662
 663         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 664                 return 0;
 665
 666         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 667         req.flags = flags;
 668
 669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 670
 671         HWRM_CHECK_RESULT;
 672
 673         bp->flags &= ~BNXT_FLAG_REGISTERED;
 674
 675         return rc;
 676 }
 677
 678 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 679 {
 680         int rc = 0;
 681         struct hwrm_port_phy_cfg_input req = {0};
 682         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 683         uint32_t enables = 0;
 684         uint32_t link_speed_mask =
 685                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 686
 687         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 688
 689         if (conf->link_up) {
 690                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 691                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 692                 /*
 693                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 694                  * any auto mode, even "none".
 695                  */
 696                 if (!conf->link_speed) {
 697                         req.auto_mode = conf->auto_mode;
 698                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 699                         if (conf->auto_mode ==
 700                             HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
 701                                 req.auto_link_speed_mask =
 702                                         conf->auto_link_speed_mask;
 703                                 enables |= link_speed_mask;
 704                         }
 705                         if (bp->link_info.auto_link_speed) {
 706                                 req.auto_link_speed =
 707                                         bp->link_info.auto_link_speed;
 708                                 enables |=
 709                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 710                         }
 711                 }
 712                 req.auto_duplex = conf->duplex;
 713                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 714                 req.auto_pause = conf->auto_pause;
 715                 req.force_pause = conf->force_pause;
 716                 /* Set force_pause if there is no auto or if there is a force */
 717                 if (req.auto_pause && !req.force_pause)
 718                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 719                 else
 720                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 721
 722                 req.enables = rte_cpu_to_le_32(enables);
 723         } else {
 724                 req.flags =
 725                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 726                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 727         }
 728
 729         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 730
 731         HWRM_CHECK_RESULT;
 732
 733         return rc;
 734 }
 735
 736 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 737                                    struct bnxt_link_info *link_info)
 738 {
 739         int rc = 0;
 740         struct hwrm_port_phy_qcfg_input req = {0};
 741         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 742
 743         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
 744
 745         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 746
 747         HWRM_CHECK_RESULT;
 748
 749         link_info->phy_link_status = resp->link;
 750         link_info->link_up =
 751                 (link_info->phy_link_status ==
 752                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 753         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 754         link_info->duplex = resp->duplex;
 755         link_info->pause = resp->pause;
 756         link_info->auto_pause = resp->auto_pause;
 757         link_info->force_pause = resp->force_pause;
 758         link_info->auto_mode = resp->auto_mode;
 759
 760         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 761         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 762         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 763         link_info->phy_ver[0] = resp->phy_maj;
 764         link_info->phy_ver[1] = resp->phy_min;
 765         link_info->phy_ver[2] = resp->phy_bld;
 766
 767         return rc;
 768 }
 769
 770 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 771 {
 772         int rc = 0;
 773         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 774         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 775
 776         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 777
 778         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 779
 780         HWRM_CHECK_RESULT;
 781
 782 #define GET_QUEUE_INFO(x) \
 783         bp->cos_queue[x].id = resp->queue_id##x; \
 784         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 785
 786         GET_QUEUE_INFO(0);
 787         GET_QUEUE_INFO(1);
 788         GET_QUEUE_INFO(2);
 789         GET_QUEUE_INFO(3);
 790         GET_QUEUE_INFO(4);
 791         GET_QUEUE_INFO(5);
 792         GET_QUEUE_INFO(6);
 793         GET_QUEUE_INFO(7);
 794
 795         return rc;
 796 }
 797
 798 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 799                          struct bnxt_ring *ring,
 800                          uint32_t ring_type, uint32_t map_index,
 801                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 802 {
 803         int rc = 0;
 804         uint32_t enables = 0;
 805         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 806         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 807
 808         HWRM_PREP(req, RING_ALLOC, -1, resp);
 809
 810         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 811         req.fbo = rte_cpu_to_le_32(0);
 812         /* Association of ring index with doorbell index */
 813         req.logical_id = rte_cpu_to_le_16(map_index);
 814         req.length = rte_cpu_to_le_32(ring->ring_size);
 815
 816         switch (ring_type) {
 817         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 818                 req.queue_id = bp->cos_queue[0].id;
 819                 /* FALLTHROUGH */
 820         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 821                 req.ring_type = ring_type;
 822                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 823                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 824                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 825                         enables |=
 826                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 827                 break;
 828         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 829                 req.ring_type = ring_type;
 830                 /*
 831                  * TODO: Some HWRM versions crash with
 832                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 833                  */
 834                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 835                 break;
 836         default:
 837                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 838                         ring_type);
 839                 return -1;
 840         }
 841         req.enables = rte_cpu_to_le_32(enables);
 842
 843         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 844
 845         if (rc || resp->error_code) {
 846                 if (rc == 0 && resp->error_code)
 847                         rc = rte_le_to_cpu_16(resp->error_code);
 848                 switch (ring_type) {
 849                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 850                         RTE_LOG(ERR, PMD,
 851                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 852                         return rc;
 853                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 854                         RTE_LOG(ERR, PMD,
 855                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 856                         return rc;
 857                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 858                         RTE_LOG(ERR, PMD,
 859                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 860                         return rc;
 861                 default:
 862                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 863                         return rc;
 864                 }
 865         }
 866
 867         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 868         return rc;
 869 }
 870
 871 int bnxt_hwrm_ring_free(struct bnxt *bp,
 872                         struct bnxt_ring *ring, uint32_t ring_type)
 873 {
 874         int rc;
 875         struct hwrm_ring_free_input req = {.req_type = 0 };
 876         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 877
 878         HWRM_PREP(req, RING_FREE, -1, resp);
 879
 880         req.ring_type = ring_type;
 881         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 882
 883         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 884
 885         if (rc || resp->error_code) {
 886                 if (rc == 0 && resp->error_code)
 887                         rc = rte_le_to_cpu_16(resp->error_code);
 888
 889                 switch (ring_type) {
 890                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 891                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 892                                 rc);
 893                         return rc;
 894                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 895                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 896                                 rc);
 897                         return rc;
 898                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 899                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 900                                 rc);
 901                         return rc;
 902                 default:
 903                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 904                         return rc;
 905                 }
 906         }
 907         return 0;
 908 }
 909
 910 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 911 {
 912         int rc = 0;
 913         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 914         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 915
 916         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 917
 918         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 919         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 920         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 921         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 922
 923         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 924
 925         HWRM_CHECK_RESULT;
 926
 927         bp->grp_info[idx].fw_grp_id =
 928             rte_le_to_cpu_16(resp->ring_group_id);
 929
 930         return rc;
 931 }
 932
 933 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 934 {
 935         int rc;
 936         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 937         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 938
 939         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 940
 941         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 942
 943         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 944
 945         HWRM_CHECK_RESULT;
 946
 947         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 948         return rc;
 949 }
 950
 951 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 952 {
 953         int rc = 0;
 954         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 955         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 956
 957         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 958                 return rc;
 959
 960         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 961
 962         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 963
 964         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 965
 966         HWRM_CHECK_RESULT;
 967
 968         return rc;
 969 }
 970
 971 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 972                                 unsigned int idx __rte_unused)
 973 {
 974         int rc;
 975         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 976         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 977
 978         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 979
 980         req.update_period_ms = rte_cpu_to_le_32(0);
 981
 982         req.stats_dma_addr =
 983             rte_cpu_to_le_64(cpr->hw_stats_map);
 984
 985         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 986
 987         HWRM_CHECK_RESULT;
 988
 989         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 990
 991         return rc;
 992 }
 993
 994 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 995                                 unsigned int idx __rte_unused)
 996 {
 997         int rc;
 998         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 999         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1000
1001         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
1002
1003         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1004
1005         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1006
1007         HWRM_CHECK_RESULT;
1008
1009         return rc;
1010 }
1011
1012 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1013 {
1014         int rc = 0, i, j;
1015         struct hwrm_vnic_alloc_input req = { 0 };
1016         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1017
1018         /* map ring groups to this vnic */
1019         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1020                 vnic->start_grp_id, vnic->end_grp_id);
1021         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1022                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1023         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1024         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1025         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1026         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1027         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1028                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1029         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
1030
1031         if (vnic->func_default)
1032                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1034
1035         HWRM_CHECK_RESULT;
1036
1037         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1038         RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1039         return rc;
1040 }
1041
1042 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1043                                         struct bnxt_vnic_info *vnic,
1044                                         struct bnxt_plcmodes_cfg *pmode)
1045 {
1046         int rc = 0;
1047         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1048         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1049
1050         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
1051
1052         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1053
1054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1055
1056         HWRM_CHECK_RESULT;
1057
1058         pmode->flags = rte_le_to_cpu_32(resp->flags);
1059         /* dflt_vnic bit doesn't exist in the _cfg command */
1060         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1061         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1062         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1063         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1064
1065         return rc;
1066 }
1067
1068 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1069                                        struct bnxt_vnic_info *vnic,
1070                                        struct bnxt_plcmodes_cfg *pmode)
1071 {
1072         int rc = 0;
1073         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1074         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1075
1076         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1077
1078         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1079         req.flags = rte_cpu_to_le_32(pmode->flags);
1080         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1081         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1082         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1083         req.enables = rte_cpu_to_le_32(
1084             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1085             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1086             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1087         );
1088
1089         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1090
1091         HWRM_CHECK_RESULT;
1092
1093         return rc;
1094 }
1095
1096 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1097 {
1098         int rc = 0;
1099         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1100         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1101         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1102         struct bnxt_plcmodes_cfg pmodes;
1103
1104         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1105                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1106                 return rc;
1107         }
1108
1109         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1110         if (rc)
1111                 return rc;
1112
1113         HWRM_PREP(req, VNIC_CFG, -1, resp);
1114
1115         /* Only RSS support for now TBD: COS & LB */
1116         req.enables =
1117             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
1118                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
1119         if (vnic->lb_rule != 0xffff)
1120                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1121         if (vnic->cos_rule != 0xffff)
1122                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1123         if (vnic->rss_rule != 0xffff)
1124                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1125         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1126         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1127         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1128         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1129         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1130         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1131         req.mru = rte_cpu_to_le_16(vnic->mru);
1132         if (vnic->func_default)
1133                 req.flags |=
1134                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1135         if (vnic->vlan_strip)
1136                 req.flags |=
1137                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1138         if (vnic->bd_stall)
1139                 req.flags |=
1140                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1141         if (vnic->roce_dual)
1142                 req.flags |= rte_cpu_to_le_32(
1143                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1144         if (vnic->roce_only)
1145                 req.flags |= rte_cpu_to_le_32(
1146                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1147         if (vnic->rss_dflt_cr)
1148                 req.flags |= rte_cpu_to_le_32(
1149                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1150
1151         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1152
1153         HWRM_CHECK_RESULT;
1154
1155         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1156
1157         return rc;
1158 }
1159
1160 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1161                 int16_t fw_vf_id)
1162 {
1163         int rc = 0;
1164         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1165         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1166
1167         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1168                 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1169                 return rc;
1170         }
1171         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1172
1173         req.enables =
1174                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1175         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1176         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1177
1178         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1179
1180         HWRM_CHECK_RESULT;
1181
1182         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1183         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1184         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1185         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1186         vnic->mru = rte_le_to_cpu_16(resp->mru);
1187         vnic->func_default = rte_le_to_cpu_32(
1188                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1189         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1190                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1191         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1192                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1193         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1194                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1195         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1196                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1197         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1198                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1199
1200         return rc;
1201 }
1202
1203 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1204 {
1205         int rc = 0;
1206         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1207         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1208                                                 bp->hwrm_cmd_resp_addr;
1209
1210         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1211
1212         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1213
1214         HWRM_CHECK_RESULT;
1215
1216         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1217         RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1218
1219         return rc;
1220 }
1221
1222 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1223 {
1224         int rc = 0;
1225         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1226         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1227                                                 bp->hwrm_cmd_resp_addr;
1228
1229         if (vnic->rss_rule == 0xffff) {
1230                 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1231                 return rc;
1232         }
1233         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1234
1235         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1236
1237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1238
1239         HWRM_CHECK_RESULT;
1240
1241         vnic->rss_rule = INVALID_HW_RING_ID;
1242
1243         return rc;
1244 }
1245
1246 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1247 {
1248         int rc = 0;
1249         struct hwrm_vnic_free_input req = {.req_type = 0 };
1250         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1251
1252         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1253                 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1254                 return rc;
1255         }
1256
1257         HWRM_PREP(req, VNIC_FREE, -1, resp);
1258
1259         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1260
1261         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1262
1263         HWRM_CHECK_RESULT;
1264
1265         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1266         return rc;
1267 }
1268
1269 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1270                            struct bnxt_vnic_info *vnic)
1271 {
1272         int rc = 0;
1273         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1274         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1275
1276         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1277
1278         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1279
1280         req.ring_grp_tbl_addr =
1281             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1282         req.hash_key_tbl_addr =
1283             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1284         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1285
1286         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1287
1288         HWRM_CHECK_RESULT;
1289
1290         return rc;
1291 }
1292
1293 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1294                         struct bnxt_vnic_info *vnic)
1295 {
1296         int rc = 0;
1297         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1298         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1299         uint16_t size;
1300
1301         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1302
1303         req.flags = rte_cpu_to_le_32(
1304                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1305
1306         req.enables = rte_cpu_to_le_32(
1307                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1308
1309         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1310         size -= RTE_PKTMBUF_HEADROOM;
1311
1312         req.jumbo_thresh = rte_cpu_to_le_16(size);
1313         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1314
1315         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1316
1317         HWRM_CHECK_RESULT;
1318
1319         return rc;
1320 }
1321
1322 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1323                         struct bnxt_vnic_info *vnic, bool enable)
1324 {
1325         int rc = 0;
1326         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1327         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1328
1329         HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1330
1331         if (enable) {
1332                 req.enables = rte_cpu_to_le_32(
1333                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1334                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1335                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1336                 req.flags = rte_cpu_to_le_32(
1337                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1338                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1339                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1340                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1341                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1342                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1343                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1344                 req.max_agg_segs = rte_cpu_to_le_16(5);
1345                 req.max_aggs =
1346                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1347                 req.min_agg_len = rte_cpu_to_le_32(512);
1348         }
1349
1350         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1351
1352         HWRM_CHECK_RESULT;
1353
1354         return rc;
1355 }
1356
1357 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1358 {
1359         struct hwrm_func_cfg_input req = {0};
1360         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1361         int rc;
1362
1363         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1364         req.enables = rte_cpu_to_le_32(
1365                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1366         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1367         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1368
1369         HWRM_PREP(req, FUNC_CFG, -1, resp);
1370
1371         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1372         HWRM_CHECK_RESULT;
1373
1374         bp->pf.vf_info[vf].random_mac = false;
1375
1376         return rc;
1377 }
1378
1379 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1380                                   uint64_t *dropped)
1381 {
1382         int rc = 0;
1383         struct hwrm_func_qstats_input req = {.req_type = 0};
1384         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1385
1386         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1387
1388         req.fid = rte_cpu_to_le_16(fid);
1389
1390         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1391
1392         HWRM_CHECK_RESULT;
1393
1394         if (dropped)
1395                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1396
1397         return rc;
1398 }
1399
1400 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1401                           struct rte_eth_stats *stats)
1402 {
1403         int rc = 0;
1404         struct hwrm_func_qstats_input req = {.req_type = 0};
1405         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1406
1407         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1408
1409         req.fid = rte_cpu_to_le_16(fid);
1410
1411         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1412
1413         HWRM_CHECK_RESULT;
1414
1415         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1416         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1417         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1418         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1419         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1420         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1421
1422         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1423         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1424         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1425         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1426         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1427         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1428
1429         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1430         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1431
1432         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1433
1434         return rc;
1435 }
1436
1437 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1438 {
1439         int rc = 0;
1440         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1441         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1442
1443         HWRM_PREP(req, FUNC_CLR_STATS, -1, resp);
1444
1445         req.fid = rte_cpu_to_le_16(fid);
1446
1447         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1448
1449         HWRM_CHECK_RESULT;
1450
1451         return rc;
1452 }
1453
1454 /*
1455  * HWRM utility functions
1456  */
1457
1458 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1459 {
1460         unsigned int i;
1461         int rc = 0;
1462
1463         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1464                 struct bnxt_tx_queue *txq;
1465                 struct bnxt_rx_queue *rxq;
1466                 struct bnxt_cp_ring_info *cpr;
1467
1468                 if (i >= bp->rx_cp_nr_rings) {
1469                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1470                         cpr = txq->cp_ring;
1471                 } else {
1472                         rxq = bp->rx_queues[i];
1473                         cpr = rxq->cp_ring;
1474                 }
1475
1476                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1477                 if (rc)
1478                         return rc;
1479         }
1480         return 0;
1481 }
1482
1483 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1484 {
1485         int rc;
1486         unsigned int i;
1487         struct bnxt_cp_ring_info *cpr;
1488
1489         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1490
1491                 if (i >= bp->rx_cp_nr_rings)
1492                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1493                 else
1494                         cpr = bp->rx_queues[i]->cp_ring;
1495                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1496                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1497                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1498                         /*
1499                          * TODO. Need a better way to reset grp_info.stats_ctx
1500                          * for Rx rings only. stats_ctx is not saved for Tx
1501                          * in grp_info.
1502                          */
1503                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1504                         if (rc)
1505                                 return rc;
1506                 }
1507         }
1508         return 0;
1509 }
1510
1511 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1512 {
1513         unsigned int i;
1514         int rc = 0;
1515
1516         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1517                 struct bnxt_tx_queue *txq;
1518                 struct bnxt_rx_queue *rxq;
1519                 struct bnxt_cp_ring_info *cpr;
1520
1521                 if (i >= bp->rx_cp_nr_rings) {
1522                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1523                         cpr = txq->cp_ring;
1524                 } else {
1525                         rxq = bp->rx_queues[i];
1526                         cpr = rxq->cp_ring;
1527                 }
1528
1529                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1530
1531                 if (rc)
1532                         return rc;
1533         }
1534         return rc;
1535 }
1536
1537 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1538 {
1539         uint16_t idx;
1540         uint32_t rc = 0;
1541
1542         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1543
1544                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1545                         RTE_LOG(ERR, PMD,
1546                                 "Attempt to free invalid ring group %d\n",
1547                                 idx);
1548                         continue;
1549                 }
1550
1551                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1552
1553                 if (rc)
1554                         return rc;
1555         }
1556         return rc;
1557 }
1558
1559 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1560                                 unsigned int idx __rte_unused)
1561 {
1562         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1563
1564         bnxt_hwrm_ring_free(bp, cp_ring,
1565                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1566         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1567         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1568         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1569                         sizeof(*cpr->cp_desc_ring));
1570         cpr->cp_raw_cons = 0;
1571 }
1572
1573 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1574 {
1575         unsigned int i;
1576         int rc = 0;
1577
1578         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1579                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1580                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1581                 struct bnxt_ring *ring = txr->tx_ring_struct;
1582                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1583                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1584
1585                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1586                         bnxt_hwrm_ring_free(bp, ring,
1587                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1588                         ring->fw_ring_id = INVALID_HW_RING_ID;
1589                         memset(txr->tx_desc_ring, 0,
1590                                         txr->tx_ring_struct->ring_size *
1591                                         sizeof(*txr->tx_desc_ring));
1592                         memset(txr->tx_buf_ring, 0,
1593                                         txr->tx_ring_struct->ring_size *
1594                                         sizeof(*txr->tx_buf_ring));
1595                         txr->tx_prod = 0;
1596                         txr->tx_cons = 0;
1597                 }
1598                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1599                         bnxt_free_cp_ring(bp, cpr, idx);
1600                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1601                 }
1602         }
1603
1604         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1605                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1606                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1607                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1608                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1609                 unsigned int idx = i + 1;
1610
1611                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1612                         bnxt_hwrm_ring_free(bp, ring,
1613                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1614                         ring->fw_ring_id = INVALID_HW_RING_ID;
1615                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1616                         memset(rxr->rx_desc_ring, 0,
1617                                         rxr->rx_ring_struct->ring_size *
1618                                         sizeof(*rxr->rx_desc_ring));
1619                         memset(rxr->rx_buf_ring, 0,
1620                                         rxr->rx_ring_struct->ring_size *
1621                                         sizeof(*rxr->rx_buf_ring));
1622                         rxr->rx_prod = 0;
1623                         memset(rxr->ag_buf_ring, 0,
1624                                         rxr->ag_ring_struct->ring_size *
1625                                         sizeof(*rxr->ag_buf_ring));
1626                         rxr->ag_prod = 0;
1627                 }
1628                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1629                         bnxt_free_cp_ring(bp, cpr, idx);
1630                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1631                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1632                 }
1633         }
1634
1635         /* Default completion ring */
1636         {
1637                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1638
1639                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1640                         bnxt_free_cp_ring(bp, cpr, 0);
1641                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1642                 }
1643         }
1644
1645         return rc;
1646 }
1647
1648 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1649 {
1650         uint16_t i;
1651         uint32_t rc = 0;
1652
1653         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1654                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1655                 if (rc)
1656                         return rc;
1657         }
1658         return rc;
1659 }
1660
1661 void bnxt_free_hwrm_resources(struct bnxt *bp)
1662 {
1663         /* Release memzone */
1664         rte_free(bp->hwrm_cmd_resp_addr);
1665         rte_free(bp->hwrm_short_cmd_req_addr);
1666         bp->hwrm_cmd_resp_addr = NULL;
1667         bp->hwrm_short_cmd_req_addr = NULL;
1668         bp->hwrm_cmd_resp_dma_addr = 0;
1669         bp->hwrm_short_cmd_req_dma_addr = 0;
1670 }
1671
1672 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1673 {
1674         struct rte_pci_device *pdev = bp->pdev;
1675         char type[RTE_MEMZONE_NAMESIZE];
1676
1677         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1678                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1679         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1680         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1681         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1682         if (bp->hwrm_cmd_resp_addr == NULL)
1683                 return -ENOMEM;
1684         bp->hwrm_cmd_resp_dma_addr =
1685                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1686         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1687                 RTE_LOG(ERR, PMD,
1688                         "unable to map response address to physical memory\n");
1689                 return -ENOMEM;
1690         }
1691         rte_spinlock_init(&bp->hwrm_lock);
1692
1693         return 0;
1694 }
1695
1696 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1697 {
1698         struct bnxt_filter_info *filter;
1699         int rc = 0;
1700
1701         STAILQ_FOREACH(filter, &vnic->filter, next) {
1702                 rc = bnxt_hwrm_clear_filter(bp, filter);
1703                 if (rc)
1704                         break;
1705         }
1706         return rc;
1707 }
1708
1709 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1710 {
1711         struct bnxt_filter_info *filter;
1712         int rc = 0;
1713
1714         STAILQ_FOREACH(filter, &vnic->filter, next) {
1715                 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1716                 if (rc)
1717                         break;
1718         }
1719         return rc;
1720 }
1721
1722 void bnxt_free_tunnel_ports(struct bnxt *bp)
1723 {
1724         if (bp->vxlan_port_cnt)
1725                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1726                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1727         bp->vxlan_port = 0;
1728         if (bp->geneve_port_cnt)
1729                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1730                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1731         bp->geneve_port = 0;
1732 }
1733
1734 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1735 {
1736         struct bnxt_vnic_info *vnic;
1737         unsigned int i;
1738
1739         if (bp->vnic_info == NULL)
1740                 return;
1741
1742         vnic = &bp->vnic_info[0];
1743         if (BNXT_PF(bp))
1744                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1745
1746         /* VNIC resources */
1747         for (i = 0; i < bp->nr_vnics; i++) {
1748                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1749
1750                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1751
1752                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1753
1754                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1755
1756                 bnxt_hwrm_vnic_free(bp, vnic);
1757         }
1758         /* Ring resources */
1759         bnxt_free_all_hwrm_rings(bp);
1760         bnxt_free_all_hwrm_ring_grps(bp);
1761         bnxt_free_all_hwrm_stat_ctxs(bp);
1762         bnxt_free_tunnel_ports(bp);
1763 }
1764
1765 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1766 {
1767         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1768
1769         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1770                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1771
1772         switch (conf_link_speed) {
1773         case ETH_LINK_SPEED_10M_HD:
1774         case ETH_LINK_SPEED_100M_HD:
1775                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1776         }
1777         return hw_link_duplex;
1778 }
1779
1780 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1781 {
1782         uint16_t eth_link_speed = 0;
1783
1784         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1785                 return ETH_LINK_SPEED_AUTONEG;
1786
1787         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1788         case ETH_LINK_SPEED_100M:
1789         case ETH_LINK_SPEED_100M_HD:
1790                 eth_link_speed =
1791                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1792                 break;
1793         case ETH_LINK_SPEED_1G:
1794                 eth_link_speed =
1795                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1796                 break;
1797         case ETH_LINK_SPEED_2_5G:
1798                 eth_link_speed =
1799                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1800                 break;
1801         case ETH_LINK_SPEED_10G:
1802                 eth_link_speed =
1803                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1804                 break;
1805         case ETH_LINK_SPEED_20G:
1806                 eth_link_speed =
1807                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1808                 break;
1809         case ETH_LINK_SPEED_25G:
1810                 eth_link_speed =
1811                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1812                 break;
1813         case ETH_LINK_SPEED_40G:
1814                 eth_link_speed =
1815                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1816                 break;
1817         case ETH_LINK_SPEED_50G:
1818                 eth_link_speed =
1819                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1820                 break;
1821         default:
1822                 RTE_LOG(ERR, PMD,
1823                         "Unsupported link speed %d; default to AUTO\n",
1824                         conf_link_speed);
1825                 break;
1826         }
1827         return eth_link_speed;
1828 }
1829
1830 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1831                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1832                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1833                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1834
1835 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1836 {
1837         uint32_t one_speed;
1838
1839         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1840                 return 0;
1841
1842         if (link_speed & ETH_LINK_SPEED_FIXED) {
1843                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1844
1845                 if (one_speed & (one_speed - 1)) {
1846                         RTE_LOG(ERR, PMD,
1847                                 "Invalid advertised speeds (%u) for port %u\n",
1848                                 link_speed, port_id);
1849                         return -EINVAL;
1850                 }
1851                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1852                         RTE_LOG(ERR, PMD,
1853                                 "Unsupported advertised speed (%u) for port %u\n",
1854                                 link_speed, port_id);
1855                         return -EINVAL;
1856                 }
1857         } else {
1858                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1859                         RTE_LOG(ERR, PMD,
1860                                 "Unsupported advertised speeds (%u) for port %u\n",
1861                                 link_speed, port_id);
1862                         return -EINVAL;
1863                 }
1864         }
1865         return 0;
1866 }
1867
1868 static uint16_t
1869 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1870 {
1871         uint16_t ret = 0;
1872
1873         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1874                 if (bp->link_info.support_speeds)
1875                         return bp->link_info.support_speeds;
1876                 link_speed = BNXT_SUPPORTED_SPEEDS;
1877         }
1878
1879         if (link_speed & ETH_LINK_SPEED_100M)
1880                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1881         if (link_speed & ETH_LINK_SPEED_100M_HD)
1882                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1883         if (link_speed & ETH_LINK_SPEED_1G)
1884                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1885         if (link_speed & ETH_LINK_SPEED_2_5G)
1886                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1887         if (link_speed & ETH_LINK_SPEED_10G)
1888                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1889         if (link_speed & ETH_LINK_SPEED_20G)
1890                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1891         if (link_speed & ETH_LINK_SPEED_25G)
1892                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1893         if (link_speed & ETH_LINK_SPEED_40G)
1894                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1895         if (link_speed & ETH_LINK_SPEED_50G)
1896                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1897         return ret;
1898 }
1899
1900 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1901 {
1902         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1903
1904         switch (hw_link_speed) {
1905         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1906                 eth_link_speed = ETH_SPEED_NUM_100M;
1907                 break;
1908         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1909                 eth_link_speed = ETH_SPEED_NUM_1G;
1910                 break;
1911         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1912                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1913                 break;
1914         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1915                 eth_link_speed = ETH_SPEED_NUM_10G;
1916                 break;
1917         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1918                 eth_link_speed = ETH_SPEED_NUM_20G;
1919                 break;
1920         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1921                 eth_link_speed = ETH_SPEED_NUM_25G;
1922                 break;
1923         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1924                 eth_link_speed = ETH_SPEED_NUM_40G;
1925                 break;
1926         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1927                 eth_link_speed = ETH_SPEED_NUM_50G;
1928                 break;
1929         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1930         default:
1931                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1932                         hw_link_speed);
1933                 break;
1934         }
1935         return eth_link_speed;
1936 }
1937
1938 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1939 {
1940         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1941
1942         switch (hw_link_duplex) {
1943         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1944         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1945                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1946                 break;
1947         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1948                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1949                 break;
1950         default:
1951                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1952                         hw_link_duplex);
1953                 break;
1954         }
1955         return eth_link_duplex;
1956 }
1957
1958 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1959 {
1960         int rc = 0;
1961         struct bnxt_link_info *link_info = &bp->link_info;
1962
1963         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1964         if (rc) {
1965                 RTE_LOG(ERR, PMD,
1966                         "Get link config failed with rc %d\n", rc);
1967                 goto exit;
1968         }
1969         if (link_info->link_speed)
1970                 link->link_speed =
1971                         bnxt_parse_hw_link_speed(link_info->link_speed);
1972         else
1973                 link->link_speed = ETH_SPEED_NUM_NONE;
1974         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1975         link->link_status = link_info->link_up;
1976         link->link_autoneg = link_info->auto_mode ==
1977                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1978                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
1979 exit:
1980         return rc;
1981 }
1982
1983 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1984 {
1985         int rc = 0;
1986         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1987         struct bnxt_link_info link_req;
1988         uint16_t speed;
1989
1990         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1991                 return 0;
1992
1993         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1994                         bp->eth_dev->data->port_id);
1995         if (rc)
1996                 goto error;
1997
1998         memset(&link_req, 0, sizeof(link_req));
1999         link_req.link_up = link_up;
2000         if (!link_up)
2001                 goto port_phy_cfg;
2002
2003         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2004         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2005         if (speed == 0) {
2006                 link_req.phy_flags |=
2007                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2008                 link_req.auto_mode =
2009                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
2010                 link_req.auto_link_speed_mask =
2011                         bnxt_parse_eth_link_speed_mask(bp,
2012                                                        dev_conf->link_speeds);
2013         } else {
2014                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2015                 link_req.link_speed = speed;
2016                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
2017         }
2018         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2019         link_req.auto_pause = bp->link_info.auto_pause;
2020         link_req.force_pause = bp->link_info.force_pause;
2021
2022 port_phy_cfg:
2023         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2024         if (rc) {
2025                 RTE_LOG(ERR, PMD,
2026                         "Set link config failed with rc %d\n", rc);
2027         }
2028
2029 error:
2030         return rc;
2031 }
2032
2033 /* JIRA 22088 */
2034 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2035 {
2036         struct hwrm_func_qcfg_input req = {0};
2037         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2038         int rc = 0;
2039
2040         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2041         req.fid = rte_cpu_to_le_16(0xffff);
2042
2043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2044
2045         HWRM_CHECK_RESULT;
2046
2047         /* Hard Coded.. 0xfff VLAN ID mask */
2048         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2049
2050         switch (resp->port_partition_type) {
2051         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2052         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2053         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2054                 bp->port_partition_type = resp->port_partition_type;
2055                 break;
2056         default:
2057                 bp->port_partition_type = 0;
2058                 break;
2059         }
2060
2061         return rc;
2062 }
2063
2064 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2065                                    struct hwrm_func_qcaps_output *qcaps)
2066 {
2067         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2068         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2069                sizeof(qcaps->mac_address));
2070         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2071         qcaps->max_rx_rings = fcfg->num_rx_rings;
2072         qcaps->max_tx_rings = fcfg->num_tx_rings;
2073         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2074         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2075         qcaps->max_vfs = 0;
2076         qcaps->first_vf_id = 0;
2077         qcaps->max_vnics = fcfg->num_vnics;
2078         qcaps->max_decap_records = 0;
2079         qcaps->max_encap_records = 0;
2080         qcaps->max_tx_wm_flows = 0;
2081         qcaps->max_tx_em_flows = 0;
2082         qcaps->max_rx_wm_flows = 0;
2083         qcaps->max_rx_em_flows = 0;
2084         qcaps->max_flow_id = 0;
2085         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2086         qcaps->max_sp_tx_rings = 0;
2087         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2088 }
2089
2090 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2091 {
2092         struct hwrm_func_cfg_input req = {0};
2093         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2094         int rc;
2095
2096         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2097                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2098                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2099                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2100                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2101                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2102                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2103                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2104                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2105                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2106         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2107         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2108         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2109                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2110         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2111         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2112         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2113         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2114         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2115         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2116         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2117         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2118         req.fid = rte_cpu_to_le_16(0xffff);
2119
2120         HWRM_PREP(req, FUNC_CFG, -1, resp);
2121
2122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2123         HWRM_CHECK_RESULT;
2124
2125         return rc;
2126 }
2127
2128 static void populate_vf_func_cfg_req(struct bnxt *bp,
2129                                      struct hwrm_func_cfg_input *req,
2130                                      int num_vfs)
2131 {
2132         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2133                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2134                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2135                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2136                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2137                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2138                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2139                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2140                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2141                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2142
2143         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2144                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2145         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2146                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2147         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2148                                                 (num_vfs + 1));
2149         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2150         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2151                                                (num_vfs + 1));
2152         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2153         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2154         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2155         /* TODO: For now, do not support VMDq/RFS on VFs. */
2156         req->num_vnics = rte_cpu_to_le_16(1);
2157         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2158                                                  (num_vfs + 1));
2159 }
2160
2161 static void add_random_mac_if_needed(struct bnxt *bp,
2162                                      struct hwrm_func_cfg_input *cfg_req,
2163                                      int vf)
2164 {
2165         struct ether_addr mac;
2166
2167         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2168                 return;
2169
2170         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2171                 cfg_req->enables |=
2172                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2173                 eth_random_addr(cfg_req->dflt_mac_addr);
2174                 bp->pf.vf_info[vf].random_mac = true;
2175         } else {
2176                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2177         }
2178 }
2179
2180 static void reserve_resources_from_vf(struct bnxt *bp,
2181                                       struct hwrm_func_cfg_input *cfg_req,
2182                                       int vf)
2183 {
2184         struct hwrm_func_qcaps_input req = {0};
2185         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2186         int rc;
2187
2188         /* Get the actual allocated values now */
2189         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2190         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2191         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2192
2193         if (rc) {
2194                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2195                 copy_func_cfg_to_qcaps(cfg_req, resp);
2196         } else if (resp->error_code) {
2197                 rc = rte_le_to_cpu_16(resp->error_code);
2198                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2199                 copy_func_cfg_to_qcaps(cfg_req, resp);
2200         }
2201
2202         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2203         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2204         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2205         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2206         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2207         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2208         /*
2209          * TODO: While not supporting VMDq with VFs, max_vnics is always
2210          * forced to 1 in this case
2211          */
2212         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2213         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2214 }
2215
2216 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2217 {
2218         struct hwrm_func_qcfg_input req = {0};
2219         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2220         int rc;
2221
2222         /* Check for zero MAC address */
2223         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2224         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2225         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2226         if (rc) {
2227                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2228                 return -1;
2229         } else if (resp->error_code) {
2230                 rc = rte_le_to_cpu_16(resp->error_code);
2231                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2232                 return -1;
2233         }
2234         return rte_le_to_cpu_16(resp->vlan);
2235 }
2236
2237 static int update_pf_resource_max(struct bnxt *bp)
2238 {
2239         struct hwrm_func_qcfg_input req = {0};
2240         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2241         int rc;
2242
2243         /* And copy the allocated numbers into the pf struct */
2244         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2245         req.fid = rte_cpu_to_le_16(0xffff);
2246         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2247         HWRM_CHECK_RESULT;
2248
2249         /* Only TX ring value reflects actual allocation? TODO */
2250         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2251         bp->pf.evb_mode = resp->evb_mode;
2252
2253         return rc;
2254 }
2255
2256 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2257 {
2258         int rc;
2259
2260         if (!BNXT_PF(bp)) {
2261                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2262                 return -1;
2263         }
2264
2265         rc = bnxt_hwrm_func_qcaps(bp);
2266         if (rc)
2267                 return rc;
2268
2269         bp->pf.func_cfg_flags &=
2270                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2271                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2272         bp->pf.func_cfg_flags |=
2273                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2274         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2275         return rc;
2276 }
2277
2278 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2279 {
2280         struct hwrm_func_cfg_input req = {0};
2281         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2282         int i;
2283         size_t sz;
2284         int rc = 0;
2285         size_t req_buf_sz;
2286
2287         if (!BNXT_PF(bp)) {
2288                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2289                 return -1;
2290         }
2291
2292         rc = bnxt_hwrm_func_qcaps(bp);
2293
2294         if (rc)
2295                 return rc;
2296
2297         bp->pf.active_vfs = num_vfs;
2298
2299         /*
2300          * First, configure the PF to only use one TX ring.  This ensures that
2301          * there are enough rings for all VFs.
2302          *
2303          * If we don't do this, when we call func_alloc() later, we will lock
2304          * extra rings to the PF that won't be available during func_cfg() of
2305          * the VFs.
2306          *
2307          * This has been fixed with firmware versions above 20.6.54
2308          */
2309         bp->pf.func_cfg_flags &=
2310                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2311                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2312         bp->pf.func_cfg_flags |=
2313                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2314         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2315         if (rc)
2316                 return rc;
2317
2318         /*
2319          * Now, create and register a buffer to hold forwarded VF requests
2320          */
2321         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2322         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2323                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2324         if (bp->pf.vf_req_buf == NULL) {
2325                 rc = -ENOMEM;
2326                 goto error_free;
2327         }
2328         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2329                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2330         for (i = 0; i < num_vfs; i++)
2331                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2332                                         (i * HWRM_MAX_REQ_LEN);
2333
2334         rc = bnxt_hwrm_func_buf_rgtr(bp);
2335         if (rc)
2336                 goto error_free;
2337
2338         populate_vf_func_cfg_req(bp, &req, num_vfs);
2339
2340         bp->pf.active_vfs = 0;
2341         for (i = 0; i < num_vfs; i++) {
2342                 add_random_mac_if_needed(bp, &req, i);
2343
2344                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2345                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2346                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2347                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2348
2349                 /* Clear enable flag for next pass */
2350                 req.enables &= ~rte_cpu_to_le_32(
2351                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2352
2353                 if (rc || resp->error_code) {
2354                         RTE_LOG(ERR, PMD,
2355                                 "Failed to initizlie VF %d\n", i);
2356                         RTE_LOG(ERR, PMD,
2357                                 "Not all VFs available. (%d, %d)\n",
2358                                 rc, resp->error_code);
2359                         break;
2360                 }
2361
2362                 reserve_resources_from_vf(bp, &req, i);
2363                 bp->pf.active_vfs++;
2364                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2365         }
2366
2367         /*
2368          * Now configure the PF to use "the rest" of the resources
2369          * We're using STD_TX_RING_MODE here though which will limit the TX
2370          * rings.  This will allow QoS to function properly.  Not setting this
2371          * will cause PF rings to break bandwidth settings.
2372          */
2373         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2374         if (rc)
2375                 goto error_free;
2376
2377         rc = update_pf_resource_max(bp);
2378         if (rc)
2379                 goto error_free;
2380
2381         return rc;
2382
2383 error_free:
2384         bnxt_hwrm_func_buf_unrgtr(bp);
2385         return rc;
2386 }
2387
2388 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2389 {
2390         struct hwrm_func_cfg_input req = {0};
2391         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2392         int rc;
2393
2394         HWRM_PREP(req, FUNC_CFG, -1, resp);
2395
2396         req.fid = rte_cpu_to_le_16(0xffff);
2397         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2398         req.evb_mode = bp->pf.evb_mode;
2399
2400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2401         HWRM_CHECK_RESULT;
2402
2403         return rc;
2404 }
2405
2406 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2407                                 uint8_t tunnel_type)
2408 {
2409         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2410         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2411         int rc = 0;
2412
2413         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2414         req.tunnel_type = tunnel_type;
2415         req.tunnel_dst_port_val = port;
2416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2417         HWRM_CHECK_RESULT;
2418
2419         switch (tunnel_type) {
2420         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2421                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2422                 bp->vxlan_port = port;
2423                 break;
2424         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2425                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2426                 bp->geneve_port = port;
2427                 break;
2428         default:
2429                 break;
2430         }
2431         return rc;
2432 }
2433
2434 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2435                                 uint8_t tunnel_type)
2436 {
2437         struct hwrm_tunnel_dst_port_free_input req = {0};
2438         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2439         int rc = 0;
2440
2441         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2442         req.tunnel_type = tunnel_type;
2443         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2444         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2445         HWRM_CHECK_RESULT;
2446
2447         return rc;
2448 }
2449
2450 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2451                                         uint32_t flags)
2452 {
2453         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2454         struct hwrm_func_cfg_input req = {0};
2455         int rc;
2456
2457         HWRM_PREP(req, FUNC_CFG, -1, resp);
2458         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2459         req.flags = rte_cpu_to_le_32(flags);
2460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2461         HWRM_CHECK_RESULT;
2462
2463         return rc;
2464 }
2465
2466 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2467 {
2468         uint32_t *flag = flagp;
2469
2470         vnic->flags = *flag;
2471 }
2472
2473 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2474 {
2475         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2476 }
2477
2478 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2479 {
2480         int rc = 0;
2481         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2482         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2483
2484         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2485
2486         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2487         req.req_buf_page_size = rte_cpu_to_le_16(
2488                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2489         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2490         req.req_buf_page_addr[0] =
2491                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2492         if (req.req_buf_page_addr[0] == 0) {
2493                 RTE_LOG(ERR, PMD,
2494                         "unable to map buffer address to physical memory\n");
2495                 return -ENOMEM;
2496         }
2497
2498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2499
2500         HWRM_CHECK_RESULT;
2501
2502         return rc;
2503 }
2504
2505 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2506 {
2507         int rc = 0;
2508         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2509         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2510
2511         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2512
2513         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2514
2515         HWRM_CHECK_RESULT;
2516
2517         return rc;
2518 }
2519
2520 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2521 {
2522         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2523         struct hwrm_func_cfg_input req = {0};
2524         int rc;
2525
2526         HWRM_PREP(req, FUNC_CFG, -1, resp);
2527         req.fid = rte_cpu_to_le_16(0xffff);
2528         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2529         req.enables = rte_cpu_to_le_32(
2530                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2531         req.async_event_cr = rte_cpu_to_le_16(
2532                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2533         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2534         HWRM_CHECK_RESULT;
2535
2536         return rc;
2537 }
2538
2539 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2540 {
2541         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2542         struct hwrm_func_vf_cfg_input req = {0};
2543         int rc;
2544
2545         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2546         req.enables = rte_cpu_to_le_32(
2547                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2548         req.async_event_cr = rte_cpu_to_le_16(
2549                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2550         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2551         HWRM_CHECK_RESULT;
2552
2553         return rc;
2554 }
2555
2556 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2557 {
2558         struct hwrm_func_cfg_input req = {0};
2559         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2560         uint16_t dflt_vlan, fid;
2561         uint32_t func_cfg_flags;
2562         int rc = 0;
2563
2564         HWRM_PREP(req, FUNC_CFG, -1, resp);
2565
2566         if (is_vf) {
2567                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2568                 fid = bp->pf.vf_info[vf].fid;
2569                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2570         } else {
2571                 fid = rte_cpu_to_le_16(0xffff);
2572                 func_cfg_flags = bp->pf.func_cfg_flags;
2573                 dflt_vlan = bp->vlan;
2574         }
2575
2576         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2577         req.fid = rte_cpu_to_le_16(fid);
2578         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2579         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2580
2581         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2582         HWRM_CHECK_RESULT;
2583
2584         return rc;
2585 }
2586
2587 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2588                         uint16_t max_bw, uint16_t enables)
2589 {
2590         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2591         struct hwrm_func_cfg_input req = {0};
2592         int rc;
2593
2594         HWRM_PREP(req, FUNC_CFG, -1, resp);
2595         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2596         req.enables |= rte_cpu_to_le_32(enables);
2597         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2598         req.max_bw = rte_cpu_to_le_32(max_bw);
2599         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2600         HWRM_CHECK_RESULT;
2601
2602         return rc;
2603 }
2604
2605 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2606 {
2607         struct hwrm_func_cfg_input req = {0};
2608         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2609         int rc = 0;
2610
2611         HWRM_PREP(req, FUNC_CFG, -1, resp);
2612         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2613         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2614         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2615         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2616
2617         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2618         HWRM_CHECK_RESULT;
2619
2620         return rc;
2621 }
2622
2623 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2624                               void *encaped, size_t ec_size)
2625 {
2626         int rc = 0;
2627         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2628         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2629
2630         if (ec_size > sizeof(req.encap_request))
2631                 return -1;
2632
2633         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2634
2635         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2636         memcpy(req.encap_request, encaped, ec_size);
2637
2638         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2639
2640         HWRM_CHECK_RESULT;
2641
2642         return rc;
2643 }
2644
2645 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2646                                        struct ether_addr *mac)
2647 {
2648         struct hwrm_func_qcfg_input req = {0};
2649         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2650         int rc;
2651
2652         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2653         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2654         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2655
2656         HWRM_CHECK_RESULT;
2657
2658         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2659         return rc;
2660 }
2661
2662 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2663                             void *encaped, size_t ec_size)
2664 {
2665         int rc = 0;
2666         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2667         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2668
2669         if (ec_size > sizeof(req.encap_request))
2670                 return -1;
2671
2672         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2673
2674         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2675         memcpy(req.encap_request, encaped, ec_size);
2676
2677         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2678
2679         HWRM_CHECK_RESULT;
2680
2681         return rc;
2682 }
2683
2684 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2685                          struct rte_eth_stats *stats)
2686 {
2687         int rc = 0;
2688         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2689         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2690
2691         HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2692
2693         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2694
2695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2696
2697         HWRM_CHECK_RESULT;
2698
2699         stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2700         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2701         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2702         stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2703         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2704         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2705
2706         stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2707         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2708         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2709         stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2710         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2711         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2712
2713         stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2714         stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2715         stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2716
2717         return rc;
2718 }
2719
2720 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2721 {
2722         struct hwrm_port_qstats_input req = {0};
2723         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2724         struct bnxt_pf_info *pf = &bp->pf;
2725         int rc;
2726
2727         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2728                 return 0;
2729
2730         HWRM_PREP(req, PORT_QSTATS, -1, resp);
2731         req.port_id = rte_cpu_to_le_16(pf->port_id);
2732         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2733         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2734         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2735         HWRM_CHECK_RESULT;
2736         return rc;
2737 }
2738
2739 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2740 {
2741         struct hwrm_port_clr_stats_input req = {0};
2742         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2743         struct bnxt_pf_info *pf = &bp->pf;
2744         int rc;
2745
2746         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2747                 return 0;
2748
2749         HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2750         req.port_id = rte_cpu_to_le_16(pf->port_id);
2751         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2752         HWRM_CHECK_RESULT;
2753         return rc;
2754 }
2755
2756 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2757 {
2758         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2759         struct hwrm_port_led_qcaps_input req = {0};
2760         int rc;
2761
2762         if (BNXT_VF(bp))
2763                 return 0;
2764
2765         HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2766         req.port_id = bp->pf.port_id;
2767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2768         HWRM_CHECK_RESULT;
2769
2770         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2771                 unsigned int i;
2772
2773                 bp->num_leds = resp->num_leds;
2774                 memcpy(bp->leds, &resp->led0_id,
2775                         sizeof(bp->leds[0]) * bp->num_leds);
2776                 for (i = 0; i < bp->num_leds; i++) {
2777                         struct bnxt_led_info *led = &bp->leds[i];
2778
2779                         uint16_t caps = led->led_state_caps;
2780
2781                         if (!led->led_group_id ||
2782                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2783                                 bp->num_leds = 0;
2784                                 break;
2785                         }
2786                 }
2787         }
2788         return rc;
2789 }
2790
2791 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2792 {
2793         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2794         struct hwrm_port_led_cfg_input req = {0};
2795         struct bnxt_led_cfg *led_cfg;
2796         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2797         uint16_t duration = 0;
2798         int rc, i;
2799
2800         if (!bp->num_leds || BNXT_VF(bp))
2801                 return -EOPNOTSUPP;
2802
2803         HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2804         if (led_on) {
2805                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2806                 duration = rte_cpu_to_le_16(500);
2807         }
2808         req.port_id = bp->pf.port_id;
2809         req.num_leds = bp->num_leds;
2810         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2811         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2812                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2813                 led_cfg->led_id = bp->leds[i].led_id;
2814                 led_cfg->led_state = led_state;
2815                 led_cfg->led_blink_on = duration;
2816                 led_cfg->led_blink_off = duration;
2817                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2818         }
2819
2820         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2821         HWRM_CHECK_RESULT;
2822
2823         return rc;
2824 }
2825
2826 static void
2827 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
2828 {
2829         uint32_t *count = cbdata;
2830
2831         *count = *count + 1;
2832 }
2833
2834 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
2835                                      struct bnxt_vnic_info *vnic __rte_unused)
2836 {
2837         return 0;
2838 }
2839
2840 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
2841 {
2842         uint32_t count = 0;
2843
2844         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
2845             &count, bnxt_vnic_count_hwrm_stub);
2846
2847         return count;
2848 }
2849
2850 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2851                                         uint16_t *vnic_ids)
2852 {
2853         struct hwrm_func_vf_vnic_ids_query_input req = {0};
2854         struct hwrm_func_vf_vnic_ids_query_output *resp =
2855                                                 bp->hwrm_cmd_resp_addr;
2856         int rc;
2857
2858         /* First query all VNIC ids */
2859         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2860
2861         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2862         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2863         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2864
2865         if (req.vnic_id_tbl_addr == 0) {
2866                 RTE_LOG(ERR, PMD,
2867                 "unable to map VNIC ID table address to physical memory\n");
2868                 return -ENOMEM;
2869         }
2870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2871         if (rc) {
2872                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2873                 return -1;
2874         } else if (resp->error_code) {
2875                 rc = rte_le_to_cpu_16(resp->error_code);
2876                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2877                 return -1;
2878         }
2879
2880         return rte_le_to_cpu_32(resp->vnic_id_cnt);
2881 }
2882
2883 /*
2884  * This function queries the VNIC IDs  for a specified VF. It then calls
2885  * the vnic_cb to update the necessary field in vnic_info with cbdata.
2886  * Then it calls the hwrm_cb function to program this new vnic configuration.
2887  */
2888 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2889         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2890         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2891 {
2892         struct bnxt_vnic_info vnic;
2893         int rc = 0;
2894         int i, num_vnic_ids;
2895         uint16_t *vnic_ids;
2896         size_t vnic_id_sz;
2897         size_t sz;
2898
2899         /* First query all VNIC ids */
2900         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2901         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2902                         RTE_CACHE_LINE_SIZE);
2903         if (vnic_ids == NULL) {
2904                 rc = -ENOMEM;
2905                 return rc;
2906         }
2907         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2908                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2909
2910         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2911
2912         if (num_vnic_ids < 0)
2913                 return num_vnic_ids;
2914
2915         /* Retrieve VNIC, update bd_stall then update */
2916
2917         for (i = 0; i < num_vnic_ids; i++) {
2918                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2919                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2920                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2921                 if (rc)
2922                         break;
2923                 if (vnic.mru <= 4)      /* Indicates unallocated */
2924                         continue;
2925
2926                 vnic_cb(&vnic, cbdata);
2927
2928                 rc = hwrm_cb(bp, &vnic);
2929                 if (rc)
2930                         break;
2931         }
2932
2933         rte_free(vnic_ids);
2934
2935         return rc;
2936 }
2937
2938 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2939                                               bool on)
2940 {
2941         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2942         struct hwrm_func_cfg_input req = {0};
2943         int rc;
2944
2945         HWRM_PREP(req, FUNC_CFG, -1, resp);
2946         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2947         req.enables |= rte_cpu_to_le_32(
2948                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2949         req.vlan_antispoof_mode = on ?
2950                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2951                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2952         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2953         HWRM_CHECK_RESULT;
2954
2955         return rc;
2956 }
2957
2958 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2959 {
2960         struct bnxt_vnic_info vnic;
2961         uint16_t *vnic_ids;
2962         size_t vnic_id_sz;
2963         int num_vnic_ids, i;
2964         size_t sz;
2965         int rc;
2966
2967         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2968         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2969                         RTE_CACHE_LINE_SIZE);
2970         if (vnic_ids == NULL) {
2971                 rc = -ENOMEM;
2972                 return rc;
2973         }
2974
2975         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2976                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2977
2978         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2979         if (rc <= 0)
2980                 goto exit;
2981         num_vnic_ids = rc;
2982
2983         /*
2984          * Loop through to find the default VNIC ID.
2985          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2986          * by sending the hwrm_func_qcfg command to the firmware.
2987          */
2988         for (i = 0; i < num_vnic_ids; i++) {
2989                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2990                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2991                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2992                                         bp->pf.first_vf_id + vf);
2993                 if (rc)
2994                         goto exit;
2995                 if (vnic.func_default) {
2996                         rte_free(vnic_ids);
2997                         return vnic.fw_vnic_id;
2998                 }
2999         }
3000         /* Could not find a default VNIC. */
3001         RTE_LOG(ERR, PMD, "No default VNIC\n");
3002 exit:
3003         rte_free(vnic_ids);
3004         return -1;
3005 }