drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #include <rte_io.h>
  28
  29 #define HWRM_CMD_TIMEOUT                6000000
  30 #define HWRM_SPEC_CODE_1_8_3            0x10803
  31 #define HWRM_VERSION_1_9_1              0x10901
  32 #define HWRM_VERSION_1_9_2              0x10903
  33
  34 struct bnxt_plcmodes_cfg {
  35         uint32_t        flags;
  36         uint16_t        jumbo_thresh;
  37         uint16_t        hds_offset;
  38         uint16_t        hds_threshold;
  39 };
  40
  41 static int page_getenum(size_t size)
  42 {
  43         if (size <= 1 << 4)
  44                 return 4;
  45         if (size <= 1 << 12)
  46                 return 12;
  47         if (size <= 1 << 13)
  48                 return 13;
  49         if (size <= 1 << 16)
  50                 return 16;
  51         if (size <= 1 << 21)
  52                 return 21;
  53         if (size <= 1 << 22)
  54                 return 22;
  55         if (size <= 1 << 30)
  56                 return 30;
  57         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  58         return sizeof(void *) * 8 - 1;
  59 }
  60
  61 static int page_roundup(size_t size)
  62 {
  63         return 1 << page_getenum(size);
  64 }
  65
  66 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  67                                   uint8_t *pg_attr,
  68                                   uint64_t *pg_dir)
  69 {
  70         if (rmem->nr_pages > 1) {
  71                 *pg_attr = 1;
  72                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  73         } else {
  74                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  75         }
  76 }
  77
  78 /*
  79  * HWRM Functions (sent to HWRM)
  80  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  81  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  82  * command was failed by the ChiMP.
  83  */
  84
  85 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  86                                   uint32_t msg_len, bool use_kong_mb)
  87 {
  88         unsigned int i;
  89         struct input *req = msg;
  90         struct output *resp = bp->hwrm_cmd_resp_addr;
  91         uint32_t *data = msg;
  92         uint8_t *bar;
  93         uint8_t *valid;
  94         uint16_t max_req_len = bp->max_req_len;
  95         struct hwrm_short_input short_input = { 0 };
  96         uint16_t bar_offset = use_kong_mb ?
  97                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  98         uint16_t mb_trigger_offset = use_kong_mb ?
  99                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
 100
 101         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 102             msg_len > bp->max_req_len) {
 103                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 104
 105                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 106                 memcpy(short_cmd_req, req, msg_len);
 107
 108                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 109                 short_input.signature = rte_cpu_to_le_16(
 110                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 111                 short_input.size = rte_cpu_to_le_16(msg_len);
 112                 short_input.req_addr =
 113                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 114
 115                 data = (uint32_t *)&short_input;
 116                 msg_len = sizeof(short_input);
 117
 118                 /* Sync memory write before updating doorbell */
 119                 rte_wmb();
 120
 121                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 122         }
 123
 124         /* Write request msg to hwrm channel */
 125         for (i = 0; i < msg_len; i += 4) {
 126                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 127                 rte_write32(*data, bar);
 128                 data++;
 129         }
 130
 131         /* Zero the rest of the request space */
 132         for (; i < max_req_len; i += 4) {
 133                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 134                 rte_write32(0, bar);
 135         }
 136
 137         /* Ring channel doorbell */
 138         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 139         rte_write32(1, bar);
 140
 141         /* Poll for the valid bit */
 142         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 143                 /* Sanity check on the resp->resp_len */
 144                 rte_rmb();
 145                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 146                         /* Last byte of resp contains the valid key */
 147                         valid = (uint8_t *)resp + resp->resp_len - 1;
 148                         if (*valid == HWRM_RESP_VALID_KEY)
 149                                 break;
 150                 }
 151                 rte_delay_us(1);
 152         }
 153
 154         if (i >= HWRM_CMD_TIMEOUT) {
 155                 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
 156                         req->req_type);
 157                 goto err_ret;
 158         }
 159         return 0;
 160
 161 err_ret:
 162         return -1;
 163 }
 164
 165 /*
 166  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 167  * spinlock, and does initial processing.
 168  *
 169  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 170  * releases the spinlock only if it returns.  If the regular int return codes
 171  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 172  * directly, rather it should be copied and modified to suit the function.
 173  *
 174  * HWRM_UNLOCK() must be called after all response processing is completed.
 175  */
 176 #define HWRM_PREP(req, type, kong) do { \
 177         rte_spinlock_lock(&bp->hwrm_lock); \
 178         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 179         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 180         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 181         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 182                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 183         req.target_id = rte_cpu_to_le_16(0xffff); \
 184         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 185 } while (0)
 186
 187 #define HWRM_CHECK_RESULT_SILENT() do {\
 188         if (rc) { \
 189                 rte_spinlock_unlock(&bp->hwrm_lock); \
 190                 return rc; \
 191         } \
 192         if (resp->error_code) { \
 193                 rc = rte_le_to_cpu_16(resp->error_code); \
 194                 rte_spinlock_unlock(&bp->hwrm_lock); \
 195                 return rc; \
 196         } \
 197 } while (0)
 198
 199 #define HWRM_CHECK_RESULT() do {\
 200         if (rc) { \
 201                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 204                         rc = -EACCES; \
 205                 else if (rc > 0) \
 206                         rc = -EINVAL; \
 207                 return rc; \
 208         } \
 209         if (resp->error_code) { \
 210                 rc = rte_le_to_cpu_16(resp->error_code); \
 211                 if (resp->resp_len >= 16) { \
 212                         struct hwrm_err_output *tmp_hwrm_err_op = \
 213                                                 (void *)resp; \
 214                         PMD_DRV_LOG(ERR, \
 215                                 "error %d:%d:%08x:%04x\n", \
 216                                 rc, tmp_hwrm_err_op->cmd_err, \
 217                                 rte_le_to_cpu_32(\
 218                                         tmp_hwrm_err_op->opaque_0), \
 219                                 rte_le_to_cpu_16(\
 220                                         tmp_hwrm_err_op->opaque_1)); \
 221                 } else { \
 222                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = UINT64_MAX;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 PMD_DRV_LOG(DEBUG,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399         req.flags |=
 400         rte_cpu_to_le_32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST);
 401
 402         enables = filter->enables |
 403               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 404         req.dst_id = rte_cpu_to_le_16(dst_id);
 405
 406         if (enables &
 407             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 408                 memcpy(req.l2_addr, filter->l2_addr,
 409                        RTE_ETHER_ADDR_LEN);
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 412                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 413                        RTE_ETHER_ADDR_LEN);
 414         if (enables &
 415             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 416                 req.l2_ovlan = filter->l2_ovlan;
 417         if (enables &
 418             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 419                 req.l2_ivlan = filter->l2_ivlan;
 420         if (enables &
 421             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 422                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 423         if (enables &
 424             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 425                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 427                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 428         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 429                 req.src_type = filter->src_type;
 430
 431         req.enables = rte_cpu_to_le_32(enables);
 432
 433         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 434
 435         HWRM_CHECK_RESULT();
 436
 437         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 438         HWRM_UNLOCK();
 439
 440         return rc;
 441 }
 442
 443 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 444 {
 445         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 446         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 447         uint32_t flags = 0;
 448         int rc;
 449
 450         if (!ptp)
 451                 return 0;
 452
 453         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 454
 455         if (ptp->rx_filter)
 456                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 457         else
 458                 flags |=
 459                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 460         if (ptp->tx_tstamp_en)
 461                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 462         else
 463                 flags |=
 464                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 465         req.flags = rte_cpu_to_le_32(flags);
 466         req.enables = rte_cpu_to_le_32
 467                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 468         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 469
 470         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 471         HWRM_UNLOCK();
 472
 473         return rc;
 474 }
 475
 476 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 477 {
 478         int rc = 0;
 479         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 480         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 482
 483 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 484         if (ptp)
 485                 return 0;
 486
 487         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 488
 489         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 490
 491         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 492
 493         HWRM_CHECK_RESULT();
 494
 495         if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 496                 return 0;
 497
 498         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 499         if (!ptp)
 500                 return -ENOMEM;
 501
 502         ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 503                 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 504         ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 505                 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 506         ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 507                 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 508         ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 509                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 510         ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 511                 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 512         ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 513                 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 514         ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 515                 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 516         ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 517                 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 518         ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 519                 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 520
 521         ptp->bp = bp;
 522         bp->ptp_cfg = ptp;
 523
 524         return 0;
 525 }
 526
 527 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 528 {
 529         int rc = 0;
 530         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 531         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 532         uint16_t new_max_vfs;
 533         uint32_t flags;
 534         int i;
 535
 536         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 537
 538         req.fid = rte_cpu_to_le_16(0xffff);
 539
 540         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 541
 542         HWRM_CHECK_RESULT();
 543
 544         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 545         flags = rte_le_to_cpu_32(resp->flags);
 546         if (BNXT_PF(bp)) {
 547                 bp->pf.port_id = resp->port_id;
 548                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 549                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 550                 new_max_vfs = bp->pdev->max_vfs;
 551                 if (new_max_vfs != bp->pf.max_vfs) {
 552                         if (bp->pf.vf_info)
 553                                 rte_free(bp->pf.vf_info);
 554                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 555                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 556                         bp->pf.max_vfs = new_max_vfs;
 557                         for (i = 0; i < new_max_vfs; i++) {
 558                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 559                                 bp->pf.vf_info[i].vlan_table =
 560                                         rte_zmalloc("VF VLAN table",
 561                                                     getpagesize(),
 562                                                     getpagesize());
 563                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 564                                         PMD_DRV_LOG(ERR,
 565                                         "Fail to alloc VLAN table for VF %d\n",
 566                                         i);
 567                                 else
 568                                         rte_mem_lock_page(
 569                                                 bp->pf.vf_info[i].vlan_table);
 570                                 bp->pf.vf_info[i].vlan_as_table =
 571                                         rte_zmalloc("VF VLAN AS table",
 572                                                     getpagesize(),
 573                                                     getpagesize());
 574                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 575                                         PMD_DRV_LOG(ERR,
 576                                         "Alloc VLAN AS table for VF %d fail\n",
 577                                         i);
 578                                 else
 579                                         rte_mem_lock_page(
 580                                                bp->pf.vf_info[i].vlan_as_table);
 581                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 582                         }
 583                 }
 584         }
 585
 586         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 587         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 588         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 589         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 590         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 591         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 592         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 593         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 594         bp->max_l2_ctx =
 595                 rte_le_to_cpu_16(resp->max_l2_ctxs) + bp->max_rx_em_flows;
 596         /* TODO: For now, do not support VMDq/RFS on VFs. */
 597         if (BNXT_PF(bp)) {
 598                 if (bp->pf.max_vfs)
 599                         bp->max_vnics = 1;
 600                 else
 601                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 602         } else {
 603                 bp->max_vnics = 1;
 604         }
 605         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 606         if (BNXT_PF(bp)) {
 607                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 608                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 609                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 610                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 611                         HWRM_UNLOCK();
 612                         bnxt_hwrm_ptp_qcfg(bp);
 613                 }
 614         }
 615
 616         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 617                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 618
 619         HWRM_UNLOCK();
 620
 621         return rc;
 622 }
 623
 624 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 625 {
 626         int rc;
 627
 628         rc = __bnxt_hwrm_func_qcaps(bp);
 629         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 630                 rc = bnxt_alloc_ctx_mem(bp);
 631                 if (rc)
 632                         return rc;
 633
 634                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 635                 if (!rc)
 636                         bp->flags |= BNXT_FLAG_NEW_RM;
 637         }
 638
 639         return rc;
 640 }
 641
 642 int bnxt_hwrm_func_reset(struct bnxt *bp)
 643 {
 644         int rc = 0;
 645         struct hwrm_func_reset_input req = {.req_type = 0 };
 646         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 647
 648         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 649
 650         req.enables = rte_cpu_to_le_32(0);
 651
 652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 653
 654         HWRM_CHECK_RESULT();
 655         HWRM_UNLOCK();
 656
 657         return rc;
 658 }
 659
 660 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 661 {
 662         int rc;
 663         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 664         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 665
 666         if (bp->flags & BNXT_FLAG_REGISTERED)
 667                 return 0;
 668
 669         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 670         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 671                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 672         req.ver_maj = RTE_VER_YEAR;
 673         req.ver_min = RTE_VER_MONTH;
 674         req.ver_upd = RTE_VER_MINOR;
 675
 676         if (BNXT_PF(bp)) {
 677                 req.enables |= rte_cpu_to_le_32(
 678                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 679                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 680                        RTE_MIN(sizeof(req.vf_req_fwd),
 681                                sizeof(bp->pf.vf_req_fwd)));
 682
 683                 /*
 684                  * PF can sniff HWRM API issued by VF. This can be set up by
 685                  * linux driver and inherited by the DPDK PF driver. Clear
 686                  * this HWRM sniffer list in FW because DPDK PF driver does
 687                  * not support this.
 688                  */
 689                 req.flags =
 690                 rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE);
 691         }
 692
 693         req.async_event_fwd[0] |=
 694                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 695                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 696                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
 697         req.async_event_fwd[1] |=
 698                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 699                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 700
 701         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 702
 703         HWRM_CHECK_RESULT();
 704         HWRM_UNLOCK();
 705
 706         bp->flags |= BNXT_FLAG_REGISTERED;
 707
 708         return rc;
 709 }
 710
 711 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 712 {
 713         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 714                 return 0;
 715
 716         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 717 }
 718
 719 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 720 {
 721         int rc;
 722         uint32_t flags = 0;
 723         uint32_t enables;
 724         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 725         struct hwrm_func_vf_cfg_input req = {0};
 726
 727         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 728
 729         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 730                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 731                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 732                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 733                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 734
 735         if (BNXT_HAS_RING_GRPS(bp)) {
 736                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 737                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 738         }
 739
 740         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 741         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 742                                             AGG_RING_MULTIPLIER);
 743         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 744         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 745                                               bp->tx_nr_rings);
 746         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 747         if (bp->vf_resv_strategy ==
 748             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 749                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 750                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 751                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 752                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 753                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 754                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 755         }
 756
 757         if (test)
 758                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 759                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 760                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 761                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 762                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 763                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 764
 765         if (test && BNXT_HAS_RING_GRPS(bp))
 766                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 767
 768         req.flags = rte_cpu_to_le_32(flags);
 769         req.enables |= rte_cpu_to_le_32(enables);
 770
 771         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 772
 773         if (test)
 774                 HWRM_CHECK_RESULT_SILENT();
 775         else
 776                 HWRM_CHECK_RESULT();
 777
 778         HWRM_UNLOCK();
 779         return rc;
 780 }
 781
 782 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 783 {
 784         int rc;
 785         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 786         struct hwrm_func_resource_qcaps_input req = {0};
 787
 788         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 789         req.fid = rte_cpu_to_le_16(0xffff);
 790
 791         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 792
 793         HWRM_CHECK_RESULT();
 794
 795         if (BNXT_VF(bp)) {
 796                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 797                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 798                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 799                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 800                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 801                 /* func_resource_qcaps does not return max_rx_em_flows.
 802                  * So use the value provided by func_qcaps.
 803                  */
 804                 bp->max_l2_ctx =
 805                         rte_le_to_cpu_16(resp->max_l2_ctxs) +
 806                         bp->max_rx_em_flows;
 807                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 808                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 809         }
 810         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 811         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 812         if (bp->vf_resv_strategy >
 813             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 814                 bp->vf_resv_strategy =
 815                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 816
 817         HWRM_UNLOCK();
 818         return rc;
 819 }
 820
 821 int bnxt_hwrm_ver_get(struct bnxt *bp)
 822 {
 823         int rc = 0;
 824         struct hwrm_ver_get_input req = {.req_type = 0 };
 825         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 826         uint32_t fw_version;
 827         uint16_t max_resp_len;
 828         char type[RTE_MEMZONE_NAMESIZE];
 829         uint32_t dev_caps_cfg;
 830
 831         bp->max_req_len = HWRM_MAX_REQ_LEN;
 832         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 833
 834         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 835         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 836         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 837
 838         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 839
 840         HWRM_CHECK_RESULT();
 841
 842         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 843                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 844                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 845                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 846         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 847                      (resp->hwrm_fw_min_8b << 16) |
 848                      (resp->hwrm_fw_bld_8b << 8) |
 849                      resp->hwrm_fw_rsvd_8b;
 850         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 851                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 852
 853         fw_version = resp->hwrm_intf_maj_8b << 16;
 854         fw_version |= resp->hwrm_intf_min_8b << 8;
 855         fw_version |= resp->hwrm_intf_upd_8b;
 856         bp->hwrm_spec_code = fw_version;
 857
 858         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 859                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 860                 rc = -EINVAL;
 861                 goto error;
 862         }
 863
 864         if (bp->max_req_len > resp->max_req_win_len) {
 865                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 866                 rc = -EINVAL;
 867         }
 868         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 869         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 870         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 871                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 872
 873         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 874         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 875
 876         if (bp->max_resp_len != max_resp_len) {
 877                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 878                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 879                         bp->pdev->addr.devid, bp->pdev->addr.function);
 880
 881                 rte_free(bp->hwrm_cmd_resp_addr);
 882
 883                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 884                 if (bp->hwrm_cmd_resp_addr == NULL) {
 885                         rc = -ENOMEM;
 886                         goto error;
 887                 }
 888                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 889                 bp->hwrm_cmd_resp_dma_addr =
 890                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 891                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
 892                         PMD_DRV_LOG(ERR,
 893                         "Unable to map response buffer to physical memory.\n");
 894                         rc = -ENOMEM;
 895                         goto error;
 896                 }
 897                 bp->max_resp_len = max_resp_len;
 898         }
 899
 900         if ((dev_caps_cfg &
 901                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 902             (dev_caps_cfg &
 903              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
 904                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
 905                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 906         }
 907
 908         if (((dev_caps_cfg &
 909               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 910              (dev_caps_cfg &
 911               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
 912             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
 913                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
 914                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 915                         bp->pdev->addr.devid, bp->pdev->addr.function);
 916
 917                 rte_free(bp->hwrm_short_cmd_req_addr);
 918
 919                 bp->hwrm_short_cmd_req_addr =
 920                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
 921                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 922                         rc = -ENOMEM;
 923                         goto error;
 924                 }
 925                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 926                 bp->hwrm_short_cmd_req_dma_addr =
 927                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 928                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
 929                         rte_free(bp->hwrm_short_cmd_req_addr);
 930                         PMD_DRV_LOG(ERR,
 931                                 "Unable to map buffer to physical memory.\n");
 932                         rc = -ENOMEM;
 933                         goto error;
 934                 }
 935         }
 936         if (dev_caps_cfg &
 937             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
 938                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
 939                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
 940         }
 941         if (dev_caps_cfg &
 942             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
 943                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
 944
 945 error:
 946         HWRM_UNLOCK();
 947         return rc;
 948 }
 949
 950 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 951 {
 952         int rc;
 953         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 954         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 955
 956         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 957                 return 0;
 958
 959         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
 960         req.flags = flags;
 961
 962         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 963
 964         HWRM_CHECK_RESULT();
 965         HWRM_UNLOCK();
 966
 967         bp->flags &= ~BNXT_FLAG_REGISTERED;
 968
 969         return rc;
 970 }
 971
 972 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 973 {
 974         int rc = 0;
 975         struct hwrm_port_phy_cfg_input req = {0};
 976         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 977         uint32_t enables = 0;
 978
 979         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
 980
 981         if (conf->link_up) {
 982                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 983                 if (bp->link_info.auto_mode && conf->link_speed) {
 984                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 985                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
 986                 }
 987
 988                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 989                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 990                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 991                 /*
 992                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 993                  * any auto mode, even "none".
 994                  */
 995                 if (!conf->link_speed) {
 996                         /* No speeds specified. Enable AutoNeg - all speeds */
 997                         req.auto_mode =
 998                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 999                 }
1000                 /* AutoNeg - Advertise speeds specified. */
1001                 if (conf->auto_link_speed_mask &&
1002                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1003                         req.auto_mode =
1004                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1005                         req.auto_link_speed_mask =
1006                                 conf->auto_link_speed_mask;
1007                         enables |=
1008                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1009                 }
1010
1011                 req.auto_duplex = conf->duplex;
1012                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1013                 req.auto_pause = conf->auto_pause;
1014                 req.force_pause = conf->force_pause;
1015                 /* Set force_pause if there is no auto or if there is a force */
1016                 if (req.auto_pause && !req.force_pause)
1017                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1018                 else
1019                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1020
1021                 req.enables = rte_cpu_to_le_32(enables);
1022         } else {
1023                 req.flags =
1024                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1025                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1026         }
1027
1028         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1029
1030         HWRM_CHECK_RESULT();
1031         HWRM_UNLOCK();
1032
1033         return rc;
1034 }
1035
1036 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1037                                    struct bnxt_link_info *link_info)
1038 {
1039         int rc = 0;
1040         struct hwrm_port_phy_qcfg_input req = {0};
1041         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1042
1043         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1044
1045         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1046
1047         HWRM_CHECK_RESULT();
1048
1049         link_info->phy_link_status = resp->link;
1050         link_info->link_up =
1051                 (link_info->phy_link_status ==
1052                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1053         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1054         link_info->duplex = resp->duplex_cfg;
1055         link_info->pause = resp->pause;
1056         link_info->auto_pause = resp->auto_pause;
1057         link_info->force_pause = resp->force_pause;
1058         link_info->auto_mode = resp->auto_mode;
1059         link_info->phy_type = resp->phy_type;
1060         link_info->media_type = resp->media_type;
1061
1062         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1063         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1064         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1065         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1066         link_info->phy_ver[0] = resp->phy_maj;
1067         link_info->phy_ver[1] = resp->phy_min;
1068         link_info->phy_ver[2] = resp->phy_bld;
1069
1070         HWRM_UNLOCK();
1071
1072         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1073         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1074         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1075         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1076         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1077                     link_info->auto_link_speed_mask);
1078         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1079                     link_info->force_link_speed);
1080
1081         return rc;
1082 }
1083
1084 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1085 {
1086         int rc = 0;
1087         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1088         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1089         int i;
1090
1091         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1092
1093         req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1094         /* HWRM Version >= 1.9.1 */
1095         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1096                 req.drv_qmap_cap =
1097                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1098         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1099
1100         HWRM_CHECK_RESULT();
1101
1102 #define GET_QUEUE_INFO(x) \
1103         bp->cos_queue[x].id = resp->queue_id##x; \
1104         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
1105
1106         GET_QUEUE_INFO(0);
1107         GET_QUEUE_INFO(1);
1108         GET_QUEUE_INFO(2);
1109         GET_QUEUE_INFO(3);
1110         GET_QUEUE_INFO(4);
1111         GET_QUEUE_INFO(5);
1112         GET_QUEUE_INFO(6);
1113         GET_QUEUE_INFO(7);
1114
1115         HWRM_UNLOCK();
1116
1117         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1118                 bp->tx_cosq_id = bp->cos_queue[0].id;
1119         } else {
1120                 /* iterate and find the COSq profile to use for Tx */
1121                 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1122                         if (bp->cos_queue[i].profile ==
1123                                 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1124                                 bp->tx_cosq_id = bp->cos_queue[i].id;
1125                                 break;
1126                         }
1127                 }
1128         }
1129
1130         bp->max_tc = resp->max_configurable_queues;
1131         bp->max_lltc = resp->max_configurable_lossless_queues;
1132         if (bp->max_tc > BNXT_MAX_QUEUE)
1133                 bp->max_tc = BNXT_MAX_QUEUE;
1134         bp->max_q = bp->max_tc;
1135
1136         PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
1137
1138         return rc;
1139 }
1140
1141 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1142                          struct bnxt_ring *ring,
1143                          uint32_t ring_type, uint32_t map_index,
1144                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
1145 {
1146         int rc = 0;
1147         uint32_t enables = 0;
1148         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1149         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1150         struct rte_mempool *mb_pool;
1151         uint16_t rx_buf_size;
1152
1153         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1154
1155         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1156         req.fbo = rte_cpu_to_le_32(0);
1157         /* Association of ring index with doorbell index */
1158         req.logical_id = rte_cpu_to_le_16(map_index);
1159         req.length = rte_cpu_to_le_32(ring->ring_size);
1160
1161         switch (ring_type) {
1162         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1163                 req.ring_type = ring_type;
1164                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1165                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1166                 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
1167                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1168                         enables |=
1169                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1170                 break;
1171         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1172                 req.ring_type = ring_type;
1173                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1174                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1175                 if (BNXT_CHIP_THOR(bp)) {
1176                         mb_pool = bp->rx_queues[0]->mb_pool;
1177                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1178                                       RTE_PKTMBUF_HEADROOM;
1179                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1180                         enables |=
1181                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1182                 }
1183                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1184                         enables |=
1185                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1186                 break;
1187         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1188                 req.ring_type = ring_type;
1189                 if (BNXT_HAS_NQ(bp)) {
1190                         /* Association of cp ring with nq */
1191                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1192                         enables |=
1193                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1194                 }
1195                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1196                 break;
1197         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1198                 req.ring_type = ring_type;
1199                 req.page_size = BNXT_PAGE_SHFT;
1200                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1201                 break;
1202         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1203                 req.ring_type = ring_type;
1204                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1205
1206                 mb_pool = bp->rx_queues[0]->mb_pool;
1207                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1208                               RTE_PKTMBUF_HEADROOM;
1209                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1210
1211                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1212                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1213                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1214                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1215                 break;
1216         default:
1217                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1218                         ring_type);
1219                 HWRM_UNLOCK();
1220                 return -1;
1221         }
1222         req.enables = rte_cpu_to_le_32(enables);
1223
1224         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1225
1226         if (rc || resp->error_code) {
1227                 if (rc == 0 && resp->error_code)
1228                         rc = rte_le_to_cpu_16(resp->error_code);
1229                 switch (ring_type) {
1230                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1231                         PMD_DRV_LOG(ERR,
1232                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1233                         HWRM_UNLOCK();
1234                         return rc;
1235                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1236                         PMD_DRV_LOG(ERR,
1237                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1238                         HWRM_UNLOCK();
1239                         return rc;
1240                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1241                         PMD_DRV_LOG(ERR,
1242                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1243                                     rc);
1244                         HWRM_UNLOCK();
1245                         return rc;
1246                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1247                         PMD_DRV_LOG(ERR,
1248                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1249                         HWRM_UNLOCK();
1250                         return rc;
1251                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1252                         PMD_DRV_LOG(ERR,
1253                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1254                         HWRM_UNLOCK();
1255                         return rc;
1256                 default:
1257                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1258                         HWRM_UNLOCK();
1259                         return rc;
1260                 }
1261         }
1262
1263         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1264         HWRM_UNLOCK();
1265         return rc;
1266 }
1267
1268 int bnxt_hwrm_ring_free(struct bnxt *bp,
1269                         struct bnxt_ring *ring, uint32_t ring_type)
1270 {
1271         int rc;
1272         struct hwrm_ring_free_input req = {.req_type = 0 };
1273         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1274
1275         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1276
1277         req.ring_type = ring_type;
1278         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1279
1280         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1281
1282         if (rc || resp->error_code) {
1283                 if (rc == 0 && resp->error_code)
1284                         rc = rte_le_to_cpu_16(resp->error_code);
1285                 HWRM_UNLOCK();
1286
1287                 switch (ring_type) {
1288                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1289                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1290                                 rc);
1291                         return rc;
1292                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1293                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1294                                 rc);
1295                         return rc;
1296                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1297                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1298                                 rc);
1299                         return rc;
1300                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1301                         PMD_DRV_LOG(ERR,
1302                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1303                         return rc;
1304                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1305                         PMD_DRV_LOG(ERR,
1306                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1307                         return rc;
1308                 default:
1309                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1310                         return rc;
1311                 }
1312         }
1313         HWRM_UNLOCK();
1314         return 0;
1315 }
1316
1317 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1318 {
1319         int rc = 0;
1320         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1321         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1322
1323         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1324
1325         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1326         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1327         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1328         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1329
1330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1331
1332         HWRM_CHECK_RESULT();
1333
1334         bp->grp_info[idx].fw_grp_id =
1335             rte_le_to_cpu_16(resp->ring_group_id);
1336
1337         HWRM_UNLOCK();
1338
1339         return rc;
1340 }
1341
1342 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1343 {
1344         int rc;
1345         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1346         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1347
1348         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1349
1350         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1351
1352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1353
1354         HWRM_CHECK_RESULT();
1355         HWRM_UNLOCK();
1356
1357         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1358         return rc;
1359 }
1360
1361 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1362 {
1363         int rc = 0;
1364         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1365         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1366
1367         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1368                 return rc;
1369
1370         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1371
1372         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1373
1374         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1375
1376         HWRM_CHECK_RESULT();
1377         HWRM_UNLOCK();
1378
1379         return rc;
1380 }
1381
1382 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1383                                 unsigned int idx __rte_unused)
1384 {
1385         int rc;
1386         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1387         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1388
1389         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1390
1391         req.update_period_ms = rte_cpu_to_le_32(0);
1392
1393         req.stats_dma_addr =
1394             rte_cpu_to_le_64(cpr->hw_stats_map);
1395
1396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1397
1398         HWRM_CHECK_RESULT();
1399
1400         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1401
1402         HWRM_UNLOCK();
1403
1404         return rc;
1405 }
1406
1407 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1408                                 unsigned int idx __rte_unused)
1409 {
1410         int rc;
1411         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1412         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1413
1414         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1415
1416         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1417
1418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1419
1420         HWRM_CHECK_RESULT();
1421         HWRM_UNLOCK();
1422
1423         return rc;
1424 }
1425
1426 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1427 {
1428         int rc = 0, i, j;
1429         struct hwrm_vnic_alloc_input req = { 0 };
1430         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1431
1432         if (!BNXT_HAS_RING_GRPS(bp))
1433                 goto skip_ring_grps;
1434
1435         /* map ring groups to this vnic */
1436         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1437                 vnic->start_grp_id, vnic->end_grp_id);
1438         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1439                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1440
1441         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1442         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1443         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1444         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1445
1446 skip_ring_grps:
1447         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1448                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1449         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1450
1451         if (vnic->func_default)
1452                 req.flags =
1453                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1455
1456         HWRM_CHECK_RESULT();
1457
1458         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1459         HWRM_UNLOCK();
1460         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1461         return rc;
1462 }
1463
1464 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1465                                         struct bnxt_vnic_info *vnic,
1466                                         struct bnxt_plcmodes_cfg *pmode)
1467 {
1468         int rc = 0;
1469         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1470         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1471
1472         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1473
1474         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1475
1476         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1477
1478         HWRM_CHECK_RESULT();
1479
1480         pmode->flags = rte_le_to_cpu_32(resp->flags);
1481         /* dflt_vnic bit doesn't exist in the _cfg command */
1482         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1483         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1484         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1485         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1486
1487         HWRM_UNLOCK();
1488
1489         return rc;
1490 }
1491
1492 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1493                                        struct bnxt_vnic_info *vnic,
1494                                        struct bnxt_plcmodes_cfg *pmode)
1495 {
1496         int rc = 0;
1497         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1498         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1499
1500         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1501                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1502                 return rc;
1503         }
1504
1505         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1506
1507         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1508         req.flags = rte_cpu_to_le_32(pmode->flags);
1509         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1510         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1511         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1512         req.enables = rte_cpu_to_le_32(
1513             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1514             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1515             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1516         );
1517
1518         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1519
1520         HWRM_CHECK_RESULT();
1521         HWRM_UNLOCK();
1522
1523         return rc;
1524 }
1525
1526 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1527 {
1528         int rc = 0;
1529         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1530         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1531         struct bnxt_plcmodes_cfg pmodes = { 0 };
1532         uint32_t ctx_enable_flag = 0;
1533         uint32_t enables = 0;
1534
1535         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1536                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1537                 return rc;
1538         }
1539
1540         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1541         if (rc)
1542                 return rc;
1543
1544         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1545
1546         if (BNXT_CHIP_THOR(bp)) {
1547                 struct bnxt_rx_queue *rxq = bp->eth_dev->data->rx_queues[0];
1548                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1549                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1550
1551                 req.default_rx_ring_id =
1552                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1553                 req.default_cmpl_ring_id =
1554                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1555                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1556                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1557                 goto config_mru;
1558         }
1559
1560         /* Only RSS support for now TBD: COS & LB */
1561         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1562         if (vnic->lb_rule != 0xffff)
1563                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1564         if (vnic->cos_rule != 0xffff)
1565                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1566         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1567                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1568                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1569         }
1570         enables |= ctx_enable_flag;
1571         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1572         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1573         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1574         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1575
1576 config_mru:
1577         req.enables = rte_cpu_to_le_32(enables);
1578         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1579         req.mru = rte_cpu_to_le_16(vnic->mru);
1580         /* Configure default VNIC only once. */
1581         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1582                 req.flags |=
1583                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1584                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1585         }
1586         if (vnic->vlan_strip)
1587                 req.flags |=
1588                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1589         if (vnic->bd_stall)
1590                 req.flags |=
1591                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1592         if (vnic->roce_dual)
1593                 req.flags |= rte_cpu_to_le_32(
1594                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1595         if (vnic->roce_only)
1596                 req.flags |= rte_cpu_to_le_32(
1597                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1598         if (vnic->rss_dflt_cr)
1599                 req.flags |= rte_cpu_to_le_32(
1600                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1601
1602         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1603
1604         HWRM_CHECK_RESULT();
1605         HWRM_UNLOCK();
1606
1607         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1608
1609         return rc;
1610 }
1611
1612 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1613                 int16_t fw_vf_id)
1614 {
1615         int rc = 0;
1616         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1617         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1618
1619         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1620                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1621                 return rc;
1622         }
1623         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1624
1625         req.enables =
1626                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1627         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1628         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1629
1630         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1631
1632         HWRM_CHECK_RESULT();
1633
1634         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1635         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1636         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1637         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1638         vnic->mru = rte_le_to_cpu_16(resp->mru);
1639         vnic->func_default = rte_le_to_cpu_32(
1640                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1641         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1642                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1643         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1644                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1645         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1646                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1647         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1648                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1649         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1650                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1651
1652         HWRM_UNLOCK();
1653
1654         return rc;
1655 }
1656
1657 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1658                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1659 {
1660         int rc = 0;
1661         uint16_t ctx_id;
1662         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1663         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1664                                                 bp->hwrm_cmd_resp_addr;
1665
1666         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1667
1668         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1669         HWRM_CHECK_RESULT();
1670
1671         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1672         if (!BNXT_HAS_RING_GRPS(bp))
1673                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1674         else if (ctx_idx == 0)
1675                 vnic->rss_rule = ctx_id;
1676
1677         HWRM_UNLOCK();
1678
1679         return rc;
1680 }
1681
1682 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1683                             struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1684 {
1685         int rc = 0;
1686         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1687         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1688                                                 bp->hwrm_cmd_resp_addr;
1689
1690         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1691                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1692                 return rc;
1693         }
1694         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1695
1696         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1697
1698         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1699
1700         HWRM_CHECK_RESULT();
1701         HWRM_UNLOCK();
1702
1703         return rc;
1704 }
1705
1706 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1707 {
1708         int rc = 0;
1709         struct hwrm_vnic_free_input req = {.req_type = 0 };
1710         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1711
1712         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1713                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1714                 return rc;
1715         }
1716
1717         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1718
1719         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1720
1721         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1722
1723         HWRM_CHECK_RESULT();
1724         HWRM_UNLOCK();
1725
1726         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1727         /* Configure default VNIC again if necessary. */
1728         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1729                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1730
1731         return rc;
1732 }
1733
1734 static int
1735 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1736 {
1737         int i;
1738         int rc = 0;
1739         int nr_ctxs = bp->max_ring_grps;
1740         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1741         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1742
1743         if (!(vnic->rss_table && vnic->hash_type))
1744                 return 0;
1745
1746         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1747
1748         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1749         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1750         req.hash_mode_flags = vnic->hash_mode;
1751
1752         req.hash_key_tbl_addr =
1753             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1754
1755         for (i = 0; i < nr_ctxs; i++) {
1756                 req.ring_grp_tbl_addr =
1757                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1758                                          i * HW_HASH_INDEX_SIZE);
1759                 req.ring_table_pair_index = i;
1760                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1761
1762                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1763                                             BNXT_USE_CHIMP_MB);
1764
1765                 HWRM_CHECK_RESULT();
1766                 if (rc)
1767                         break;
1768         }
1769
1770         HWRM_UNLOCK();
1771
1772         return rc;
1773 }
1774
1775 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1776                            struct bnxt_vnic_info *vnic)
1777 {
1778         int rc = 0;
1779         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1780         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1781
1782         if (BNXT_CHIP_THOR(bp))
1783                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1784
1785         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1786
1787         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1788         req.hash_mode_flags = vnic->hash_mode;
1789
1790         req.ring_grp_tbl_addr =
1791             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1792         req.hash_key_tbl_addr =
1793             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1794         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1795         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1796
1797         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1798
1799         HWRM_CHECK_RESULT();
1800         HWRM_UNLOCK();
1801
1802         return rc;
1803 }
1804
1805 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1806                         struct bnxt_vnic_info *vnic)
1807 {
1808         int rc = 0;
1809         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1810         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1811         uint16_t size;
1812
1813         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1814                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1815                 return rc;
1816         }
1817
1818         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1819
1820         req.flags = rte_cpu_to_le_32(
1821                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1822
1823         req.enables = rte_cpu_to_le_32(
1824                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1825
1826         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1827         size -= RTE_PKTMBUF_HEADROOM;
1828
1829         req.jumbo_thresh = rte_cpu_to_le_16(size);
1830         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1831
1832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1833
1834         HWRM_CHECK_RESULT();
1835         HWRM_UNLOCK();
1836
1837         return rc;
1838 }
1839
1840 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1841                         struct bnxt_vnic_info *vnic, bool enable)
1842 {
1843         int rc = 0;
1844         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1845         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1846
1847         if (BNXT_CHIP_THOR(bp))
1848                 return 0;
1849
1850         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
1851
1852         if (enable) {
1853                 req.enables = rte_cpu_to_le_32(
1854                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1855                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1856                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1857                 req.flags = rte_cpu_to_le_32(
1858                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1859                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1860                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1861                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1862                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1863                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1864                 req.max_agg_segs = rte_cpu_to_le_16(5);
1865                 req.max_aggs =
1866                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1867                 req.min_agg_len = rte_cpu_to_le_32(512);
1868         }
1869         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1870
1871         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1872
1873         HWRM_CHECK_RESULT();
1874         HWRM_UNLOCK();
1875
1876         return rc;
1877 }
1878
1879 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1880 {
1881         struct hwrm_func_cfg_input req = {0};
1882         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1883         int rc;
1884
1885         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1886         req.enables = rte_cpu_to_le_32(
1887                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1888         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1889         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1890
1891         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
1892
1893         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1894         HWRM_CHECK_RESULT();
1895         HWRM_UNLOCK();
1896
1897         bp->pf.vf_info[vf].random_mac = false;
1898
1899         return rc;
1900 }
1901
1902 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1903                                   uint64_t *dropped)
1904 {
1905         int rc = 0;
1906         struct hwrm_func_qstats_input req = {.req_type = 0};
1907         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1908
1909         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1910
1911         req.fid = rte_cpu_to_le_16(fid);
1912
1913         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1914
1915         HWRM_CHECK_RESULT();
1916
1917         if (dropped)
1918                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1919
1920         HWRM_UNLOCK();
1921
1922         return rc;
1923 }
1924
1925 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1926                           struct rte_eth_stats *stats)
1927 {
1928         int rc = 0;
1929         struct hwrm_func_qstats_input req = {.req_type = 0};
1930         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1931
1932         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
1933
1934         req.fid = rte_cpu_to_le_16(fid);
1935
1936         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1937
1938         HWRM_CHECK_RESULT();
1939
1940         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1941         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1942         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1943         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1944         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1945         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1946
1947         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1948         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1949         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1950         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1951         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1952         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1953
1954         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
1955         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
1956         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
1957
1958         HWRM_UNLOCK();
1959
1960         return rc;
1961 }
1962
1963 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1964 {
1965         int rc = 0;
1966         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1967         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1968
1969         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
1970
1971         req.fid = rte_cpu_to_le_16(fid);
1972
1973         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1974
1975         HWRM_CHECK_RESULT();
1976         HWRM_UNLOCK();
1977
1978         return rc;
1979 }
1980
1981 /*
1982  * HWRM utility functions
1983  */
1984
1985 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1986 {
1987         unsigned int i;
1988         int rc = 0;
1989
1990         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1991                 struct bnxt_tx_queue *txq;
1992                 struct bnxt_rx_queue *rxq;
1993                 struct bnxt_cp_ring_info *cpr;
1994
1995                 if (i >= bp->rx_cp_nr_rings) {
1996                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1997                         cpr = txq->cp_ring;
1998                 } else {
1999                         rxq = bp->rx_queues[i];
2000                         cpr = rxq->cp_ring;
2001                 }
2002
2003                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2004                 if (rc)
2005                         return rc;
2006         }
2007         return 0;
2008 }
2009
2010 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2011 {
2012         int rc;
2013         unsigned int i;
2014         struct bnxt_cp_ring_info *cpr;
2015
2016         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2017
2018                 if (i >= bp->rx_cp_nr_rings) {
2019                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2020                 } else {
2021                         cpr = bp->rx_queues[i]->cp_ring;
2022                         if (BNXT_HAS_RING_GRPS(bp))
2023                                 bp->grp_info[i].fw_stats_ctx = -1;
2024                 }
2025                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2026                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2027                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2028                         if (rc)
2029                                 return rc;
2030                 }
2031         }
2032         return 0;
2033 }
2034
2035 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2036 {
2037         unsigned int i;
2038         int rc = 0;
2039
2040         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2041                 struct bnxt_tx_queue *txq;
2042                 struct bnxt_rx_queue *rxq;
2043                 struct bnxt_cp_ring_info *cpr;
2044
2045                 if (i >= bp->rx_cp_nr_rings) {
2046                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2047                         cpr = txq->cp_ring;
2048                 } else {
2049                         rxq = bp->rx_queues[i];
2050                         cpr = rxq->cp_ring;
2051                 }
2052
2053                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2054
2055                 if (rc)
2056                         return rc;
2057         }
2058         return rc;
2059 }
2060
2061 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2062 {
2063         uint16_t idx;
2064         uint32_t rc = 0;
2065
2066         if (!BNXT_HAS_RING_GRPS(bp))
2067                 return 0;
2068
2069         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2070
2071                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2072                         continue;
2073
2074                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2075
2076                 if (rc)
2077                         return rc;
2078         }
2079         return rc;
2080 }
2081
2082 static void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2083 {
2084         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2085
2086         bnxt_hwrm_ring_free(bp, cp_ring,
2087                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2088         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2089         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2090                                      sizeof(*cpr->cp_desc_ring));
2091         cpr->cp_raw_cons = 0;
2092 }
2093
2094 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2095 {
2096         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2097
2098         bnxt_hwrm_ring_free(bp, cp_ring,
2099                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2100         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2101         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2102                         sizeof(*cpr->cp_desc_ring));
2103         cpr->cp_raw_cons = 0;
2104         cpr->valid = 0;
2105 }
2106
2107 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2108 {
2109         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2110         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2111         struct bnxt_ring *ring = rxr->rx_ring_struct;
2112         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2113
2114         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2115                 bnxt_hwrm_ring_free(bp, ring,
2116                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2117                 ring->fw_ring_id = INVALID_HW_RING_ID;
2118                 if (BNXT_HAS_RING_GRPS(bp))
2119                         bp->grp_info[queue_index].rx_fw_ring_id =
2120                                                         INVALID_HW_RING_ID;
2121                 memset(rxr->rx_desc_ring, 0,
2122                        rxr->rx_ring_struct->ring_size *
2123                        sizeof(*rxr->rx_desc_ring));
2124                 memset(rxr->rx_buf_ring, 0,
2125                        rxr->rx_ring_struct->ring_size *
2126                        sizeof(*rxr->rx_buf_ring));
2127                 rxr->rx_prod = 0;
2128         }
2129         ring = rxr->ag_ring_struct;
2130         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2131                 bnxt_hwrm_ring_free(bp, ring,
2132                                     BNXT_CHIP_THOR(bp) ?
2133                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2134                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2135                 ring->fw_ring_id = INVALID_HW_RING_ID;
2136                 memset(rxr->ag_buf_ring, 0,
2137                        rxr->ag_ring_struct->ring_size *
2138                        sizeof(*rxr->ag_buf_ring));
2139                 rxr->ag_prod = 0;
2140                 if (BNXT_HAS_RING_GRPS(bp))
2141                         bp->grp_info[queue_index].ag_fw_ring_id =
2142                                                         INVALID_HW_RING_ID;
2143         }
2144         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2145                 bnxt_free_cp_ring(bp, cpr);
2146                 if (rxq->nq_ring)
2147                         bnxt_free_nq_ring(bp, rxq->nq_ring);
2148         }
2149
2150         if (BNXT_HAS_RING_GRPS(bp))
2151                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2152 }
2153
2154 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2155 {
2156         unsigned int i;
2157
2158         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2159                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2160                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2161                 struct bnxt_ring *ring = txr->tx_ring_struct;
2162                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2163
2164                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2165                         bnxt_hwrm_ring_free(bp, ring,
2166                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2167                         ring->fw_ring_id = INVALID_HW_RING_ID;
2168                         memset(txr->tx_desc_ring, 0,
2169                                         txr->tx_ring_struct->ring_size *
2170                                         sizeof(*txr->tx_desc_ring));
2171                         memset(txr->tx_buf_ring, 0,
2172                                         txr->tx_ring_struct->ring_size *
2173                                         sizeof(*txr->tx_buf_ring));
2174                         txr->tx_prod = 0;
2175                         txr->tx_cons = 0;
2176                 }
2177                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2178                         bnxt_free_cp_ring(bp, cpr);
2179                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2180                         if (txq->nq_ring)
2181                                 bnxt_free_nq_ring(bp, txq->nq_ring);
2182                 }
2183         }
2184
2185         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2186                 bnxt_free_hwrm_rx_ring(bp, i);
2187
2188         return 0;
2189 }
2190
2191 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2192 {
2193         uint16_t i;
2194         uint32_t rc = 0;
2195
2196         if (!BNXT_HAS_RING_GRPS(bp))
2197                 return 0;
2198
2199         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2200                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2201                 if (rc)
2202                         return rc;
2203         }
2204         return rc;
2205 }
2206
2207 void bnxt_free_hwrm_resources(struct bnxt *bp)
2208 {
2209         /* Release memzone */
2210         rte_free(bp->hwrm_cmd_resp_addr);
2211         rte_free(bp->hwrm_short_cmd_req_addr);
2212         bp->hwrm_cmd_resp_addr = NULL;
2213         bp->hwrm_short_cmd_req_addr = NULL;
2214         bp->hwrm_cmd_resp_dma_addr = 0;
2215         bp->hwrm_short_cmd_req_dma_addr = 0;
2216 }
2217
2218 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2219 {
2220         struct rte_pci_device *pdev = bp->pdev;
2221         char type[RTE_MEMZONE_NAMESIZE];
2222
2223         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2224                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2225         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2226         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2227         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2228         if (bp->hwrm_cmd_resp_addr == NULL)
2229                 return -ENOMEM;
2230         bp->hwrm_cmd_resp_dma_addr =
2231                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2232         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2233                 PMD_DRV_LOG(ERR,
2234                         "unable to map response address to physical memory\n");
2235                 return -ENOMEM;
2236         }
2237         rte_spinlock_init(&bp->hwrm_lock);
2238
2239         return 0;
2240 }
2241
2242 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2243 {
2244         struct bnxt_filter_info *filter;
2245         int rc = 0;
2246
2247         STAILQ_FOREACH(filter, &vnic->filter, next) {
2248                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2249                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2250                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2251                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2252                 else
2253                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2254                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2255                 //if (rc)
2256                         //break;
2257         }
2258         return rc;
2259 }
2260
2261 static int
2262 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2263 {
2264         struct bnxt_filter_info *filter;
2265         struct rte_flow *flow;
2266         int rc = 0;
2267
2268         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
2269                 filter = flow->filter;
2270                 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
2271                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2272                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2273                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2274                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2275                 else
2276                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2277
2278                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2279                 rte_free(flow);
2280                 //if (rc)
2281                         //break;
2282         }
2283         return rc;
2284 }
2285
2286 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2287 {
2288         struct bnxt_filter_info *filter;
2289         int rc = 0;
2290
2291         STAILQ_FOREACH(filter, &vnic->filter, next) {
2292                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2293                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2294                                                      filter);
2295                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2296                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2297                                                          filter);
2298                 else
2299                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2300                                                      filter);
2301                 if (rc)
2302                         break;
2303         }
2304         return rc;
2305 }
2306
2307 void bnxt_free_tunnel_ports(struct bnxt *bp)
2308 {
2309         if (bp->vxlan_port_cnt)
2310                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2311                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2312         bp->vxlan_port = 0;
2313         if (bp->geneve_port_cnt)
2314                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2315                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2316         bp->geneve_port = 0;
2317 }
2318
2319 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2320 {
2321         int i, j;
2322
2323         if (bp->vnic_info == NULL)
2324                 return;
2325
2326         /*
2327          * Cleanup VNICs in reverse order, to make sure the L2 filter
2328          * from vnic0 is last to be cleaned up.
2329          */
2330         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2331                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2332
2333                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2334                         PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2335                         return;
2336                 }
2337
2338                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2339
2340                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2341
2342                 if (BNXT_CHIP_THOR(bp)) {
2343                         for (j = 0; j < vnic->num_lb_ctxts; j++) {
2344                                 bnxt_hwrm_vnic_ctx_free(bp, vnic,
2345                                                         vnic->fw_grp_ids[j]);
2346                                 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2347                         }
2348                         vnic->num_lb_ctxts = 0;
2349                 } else {
2350                         bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2351                         vnic->rss_rule = INVALID_HW_RING_ID;
2352                 }
2353
2354                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2355
2356                 bnxt_hwrm_vnic_free(bp, vnic);
2357
2358                 rte_free(vnic->fw_grp_ids);
2359         }
2360         /* Ring resources */
2361         bnxt_free_all_hwrm_rings(bp);
2362         bnxt_free_all_hwrm_ring_grps(bp);
2363         bnxt_free_all_hwrm_stat_ctxs(bp);
2364         bnxt_free_tunnel_ports(bp);
2365 }
2366
2367 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2368 {
2369         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2370
2371         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2372                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2373
2374         switch (conf_link_speed) {
2375         case ETH_LINK_SPEED_10M_HD:
2376         case ETH_LINK_SPEED_100M_HD:
2377                 /* FALLTHROUGH */
2378                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2379         }
2380         return hw_link_duplex;
2381 }
2382
2383 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2384 {
2385         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2386 }
2387
2388 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2389 {
2390         uint16_t eth_link_speed = 0;
2391
2392         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2393                 return ETH_LINK_SPEED_AUTONEG;
2394
2395         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2396         case ETH_LINK_SPEED_100M:
2397         case ETH_LINK_SPEED_100M_HD:
2398                 /* FALLTHROUGH */
2399                 eth_link_speed =
2400                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2401                 break;
2402         case ETH_LINK_SPEED_1G:
2403                 eth_link_speed =
2404                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2405                 break;
2406         case ETH_LINK_SPEED_2_5G:
2407                 eth_link_speed =
2408                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2409                 break;
2410         case ETH_LINK_SPEED_10G:
2411                 eth_link_speed =
2412                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2413                 break;
2414         case ETH_LINK_SPEED_20G:
2415                 eth_link_speed =
2416                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2417                 break;
2418         case ETH_LINK_SPEED_25G:
2419                 eth_link_speed =
2420                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2421                 break;
2422         case ETH_LINK_SPEED_40G:
2423                 eth_link_speed =
2424                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2425                 break;
2426         case ETH_LINK_SPEED_50G:
2427                 eth_link_speed =
2428                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2429                 break;
2430         case ETH_LINK_SPEED_100G:
2431                 eth_link_speed =
2432                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2433                 break;
2434         default:
2435                 PMD_DRV_LOG(ERR,
2436                         "Unsupported link speed %d; default to AUTO\n",
2437                         conf_link_speed);
2438                 break;
2439         }
2440         return eth_link_speed;
2441 }
2442
2443 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2444                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2445                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2446                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2447
2448 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2449 {
2450         uint32_t one_speed;
2451
2452         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2453                 return 0;
2454
2455         if (link_speed & ETH_LINK_SPEED_FIXED) {
2456                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2457
2458                 if (one_speed & (one_speed - 1)) {
2459                         PMD_DRV_LOG(ERR,
2460                                 "Invalid advertised speeds (%u) for port %u\n",
2461                                 link_speed, port_id);
2462                         return -EINVAL;
2463                 }
2464                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2465                         PMD_DRV_LOG(ERR,
2466                                 "Unsupported advertised speed (%u) for port %u\n",
2467                                 link_speed, port_id);
2468                         return -EINVAL;
2469                 }
2470         } else {
2471                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2472                         PMD_DRV_LOG(ERR,
2473                                 "Unsupported advertised speeds (%u) for port %u\n",
2474                                 link_speed, port_id);
2475                         return -EINVAL;
2476                 }
2477         }
2478         return 0;
2479 }
2480
2481 static uint16_t
2482 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2483 {
2484         uint16_t ret = 0;
2485
2486         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2487                 if (bp->link_info.support_speeds)
2488                         return bp->link_info.support_speeds;
2489                 link_speed = BNXT_SUPPORTED_SPEEDS;
2490         }
2491
2492         if (link_speed & ETH_LINK_SPEED_100M)
2493                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2494         if (link_speed & ETH_LINK_SPEED_100M_HD)
2495                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2496         if (link_speed & ETH_LINK_SPEED_1G)
2497                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2498         if (link_speed & ETH_LINK_SPEED_2_5G)
2499                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2500         if (link_speed & ETH_LINK_SPEED_10G)
2501                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2502         if (link_speed & ETH_LINK_SPEED_20G)
2503                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2504         if (link_speed & ETH_LINK_SPEED_25G)
2505                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2506         if (link_speed & ETH_LINK_SPEED_40G)
2507                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2508         if (link_speed & ETH_LINK_SPEED_50G)
2509                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2510         if (link_speed & ETH_LINK_SPEED_100G)
2511                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2512         return ret;
2513 }
2514
2515 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2516 {
2517         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2518
2519         switch (hw_link_speed) {
2520         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2521                 eth_link_speed = ETH_SPEED_NUM_100M;
2522                 break;
2523         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2524                 eth_link_speed = ETH_SPEED_NUM_1G;
2525                 break;
2526         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2527                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2528                 break;
2529         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2530                 eth_link_speed = ETH_SPEED_NUM_10G;
2531                 break;
2532         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2533                 eth_link_speed = ETH_SPEED_NUM_20G;
2534                 break;
2535         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2536                 eth_link_speed = ETH_SPEED_NUM_25G;
2537                 break;
2538         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2539                 eth_link_speed = ETH_SPEED_NUM_40G;
2540                 break;
2541         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2542                 eth_link_speed = ETH_SPEED_NUM_50G;
2543                 break;
2544         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2545                 eth_link_speed = ETH_SPEED_NUM_100G;
2546                 break;
2547         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2548         default:
2549                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2550                         hw_link_speed);
2551                 break;
2552         }
2553         return eth_link_speed;
2554 }
2555
2556 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2557 {
2558         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2559
2560         switch (hw_link_duplex) {
2561         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2562         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2563                 /* FALLTHROUGH */
2564                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2565                 break;
2566         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2567                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2568                 break;
2569         default:
2570                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2571                         hw_link_duplex);
2572                 break;
2573         }
2574         return eth_link_duplex;
2575 }
2576
2577 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2578 {
2579         int rc = 0;
2580         struct bnxt_link_info *link_info = &bp->link_info;
2581
2582         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2583         if (rc) {
2584                 PMD_DRV_LOG(ERR,
2585                         "Get link config failed with rc %d\n", rc);
2586                 goto exit;
2587         }
2588         if (link_info->link_speed)
2589                 link->link_speed =
2590                         bnxt_parse_hw_link_speed(link_info->link_speed);
2591         else
2592                 link->link_speed = ETH_SPEED_NUM_NONE;
2593         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2594         link->link_status = link_info->link_up;
2595         link->link_autoneg = link_info->auto_mode ==
2596                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2597                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2598 exit:
2599         return rc;
2600 }
2601
2602 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2603 {
2604         int rc = 0;
2605         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2606         struct bnxt_link_info link_req;
2607         uint16_t speed, autoneg;
2608
2609         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2610                 return 0;
2611
2612         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2613                         bp->eth_dev->data->port_id);
2614         if (rc)
2615                 goto error;
2616
2617         memset(&link_req, 0, sizeof(link_req));
2618         link_req.link_up = link_up;
2619         if (!link_up)
2620                 goto port_phy_cfg;
2621
2622         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2623         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2624         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2625         /* Autoneg can be done only when the FW allows */
2626         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2627                                 bp->link_info.force_link_speed)) {
2628                 link_req.phy_flags |=
2629                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2630                 link_req.auto_link_speed_mask =
2631                         bnxt_parse_eth_link_speed_mask(bp,
2632                                                        dev_conf->link_speeds);
2633         } else {
2634                 if (bp->link_info.phy_type ==
2635                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2636                     bp->link_info.phy_type ==
2637                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2638                     bp->link_info.media_type ==
2639                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2640                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2641                         return -EINVAL;
2642                 }
2643
2644                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2645                 /* If user wants a particular speed try that first. */
2646                 if (speed)
2647                         link_req.link_speed = speed;
2648                 else if (bp->link_info.force_link_speed)
2649                         link_req.link_speed = bp->link_info.force_link_speed;
2650                 else
2651                         link_req.link_speed = bp->link_info.auto_link_speed;
2652         }
2653         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2654         link_req.auto_pause = bp->link_info.auto_pause;
2655         link_req.force_pause = bp->link_info.force_pause;
2656
2657 port_phy_cfg:
2658         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2659         if (rc) {
2660                 PMD_DRV_LOG(ERR,
2661                         "Set link config failed with rc %d\n", rc);
2662         }
2663
2664 error:
2665         return rc;
2666 }
2667
2668 /* JIRA 22088 */
2669 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2670 {
2671         struct hwrm_func_qcfg_input req = {0};
2672         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2673         uint16_t flags;
2674         int rc = 0;
2675
2676         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2677         req.fid = rte_cpu_to_le_16(0xffff);
2678
2679         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2680
2681         HWRM_CHECK_RESULT();
2682
2683         /* Hard Coded.. 0xfff VLAN ID mask */
2684         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2685         flags = rte_le_to_cpu_16(resp->flags);
2686         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2687                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2688
2689         if (BNXT_VF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2690                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2691                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2692         }
2693
2694         if (mtu)
2695                 *mtu = resp->mtu;
2696
2697         switch (resp->port_partition_type) {
2698         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2699         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2700         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2701                 /* FALLTHROUGH */
2702                 bp->port_partition_type = resp->port_partition_type;
2703                 break;
2704         default:
2705                 bp->port_partition_type = 0;
2706                 break;
2707         }
2708
2709         HWRM_UNLOCK();
2710
2711         return rc;
2712 }
2713
2714 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2715                                    struct hwrm_func_qcaps_output *qcaps)
2716 {
2717         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2718         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2719                sizeof(qcaps->mac_address));
2720         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2721         qcaps->max_rx_rings = fcfg->num_rx_rings;
2722         qcaps->max_tx_rings = fcfg->num_tx_rings;
2723         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2724         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2725         qcaps->max_vfs = 0;
2726         qcaps->first_vf_id = 0;
2727         qcaps->max_vnics = fcfg->num_vnics;
2728         qcaps->max_decap_records = 0;
2729         qcaps->max_encap_records = 0;
2730         qcaps->max_tx_wm_flows = 0;
2731         qcaps->max_tx_em_flows = 0;
2732         qcaps->max_rx_wm_flows = 0;
2733         qcaps->max_rx_em_flows = 0;
2734         qcaps->max_flow_id = 0;
2735         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2736         qcaps->max_sp_tx_rings = 0;
2737         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2738 }
2739
2740 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2741 {
2742         struct hwrm_func_cfg_input req = {0};
2743         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2744         uint32_t enables;
2745         int rc;
2746
2747         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2748                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2749                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2750                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2751                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2752                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2753                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2754                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2755                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2756
2757         if (BNXT_HAS_RING_GRPS(bp)) {
2758                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2759                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2760         } else if (BNXT_HAS_NQ(bp)) {
2761                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2762                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2763         }
2764
2765         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2766         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2767         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2768                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2769                                    BNXT_NUM_VLANS);
2770         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2771         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2772         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2773         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2774         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2775         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2776         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2777         req.fid = rte_cpu_to_le_16(0xffff);
2778         req.enables = rte_cpu_to_le_32(enables);
2779
2780         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2781
2782         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2783
2784         HWRM_CHECK_RESULT();
2785         HWRM_UNLOCK();
2786
2787         return rc;
2788 }
2789
2790 static void populate_vf_func_cfg_req(struct bnxt *bp,
2791                                      struct hwrm_func_cfg_input *req,
2792                                      int num_vfs)
2793 {
2794         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2795                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2796                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2797                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2798                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2799                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2800                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2801                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2802                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2803                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2804
2805         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2806                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2807                                     BNXT_NUM_VLANS);
2808         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2809                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2810                                     BNXT_NUM_VLANS);
2811         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2812                                                 (num_vfs + 1));
2813         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2814         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2815                                                (num_vfs + 1));
2816         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2817         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2818         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2819         /* TODO: For now, do not support VMDq/RFS on VFs. */
2820         req->num_vnics = rte_cpu_to_le_16(1);
2821         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2822                                                  (num_vfs + 1));
2823 }
2824
2825 static void add_random_mac_if_needed(struct bnxt *bp,
2826                                      struct hwrm_func_cfg_input *cfg_req,
2827                                      int vf)
2828 {
2829         struct rte_ether_addr mac;
2830
2831         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2832                 return;
2833
2834         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2835                 cfg_req->enables |=
2836                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2837                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
2838                 bp->pf.vf_info[vf].random_mac = true;
2839         } else {
2840                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
2841                         RTE_ETHER_ADDR_LEN);
2842         }
2843 }
2844
2845 static void reserve_resources_from_vf(struct bnxt *bp,
2846                                       struct hwrm_func_cfg_input *cfg_req,
2847                                       int vf)
2848 {
2849         struct hwrm_func_qcaps_input req = {0};
2850         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2851         int rc;
2852
2853         /* Get the actual allocated values now */
2854         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
2855         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2856         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2857
2858         if (rc) {
2859                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2860                 copy_func_cfg_to_qcaps(cfg_req, resp);
2861         } else if (resp->error_code) {
2862                 rc = rte_le_to_cpu_16(resp->error_code);
2863                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2864                 copy_func_cfg_to_qcaps(cfg_req, resp);
2865         }
2866
2867         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2868         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2869         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2870         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2871         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2872         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2873         /*
2874          * TODO: While not supporting VMDq with VFs, max_vnics is always
2875          * forced to 1 in this case
2876          */
2877         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2878         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2879
2880         HWRM_UNLOCK();
2881 }
2882
2883 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2884 {
2885         struct hwrm_func_qcfg_input req = {0};
2886         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2887         int rc;
2888
2889         /* Check for zero MAC address */
2890         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2891         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2893         if (rc) {
2894                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2895                 return -1;
2896         } else if (resp->error_code) {
2897                 rc = rte_le_to_cpu_16(resp->error_code);
2898                 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2899                 return -1;
2900         }
2901         rc = rte_le_to_cpu_16(resp->vlan);
2902
2903         HWRM_UNLOCK();
2904
2905         return rc;
2906 }
2907
2908 static int update_pf_resource_max(struct bnxt *bp)
2909 {
2910         struct hwrm_func_qcfg_input req = {0};
2911         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2912         int rc;
2913
2914         /* And copy the allocated numbers into the pf struct */
2915         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2916         req.fid = rte_cpu_to_le_16(0xffff);
2917         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2918         HWRM_CHECK_RESULT();
2919
2920         /* Only TX ring value reflects actual allocation? TODO */
2921         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2922         bp->pf.evb_mode = resp->evb_mode;
2923
2924         HWRM_UNLOCK();
2925
2926         return rc;
2927 }
2928
2929 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2930 {
2931         int rc;
2932
2933         if (!BNXT_PF(bp)) {
2934                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2935                 return -1;
2936         }
2937
2938         rc = bnxt_hwrm_func_qcaps(bp);
2939         if (rc)
2940                 return rc;
2941
2942         bp->pf.func_cfg_flags &=
2943                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2944                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2945         bp->pf.func_cfg_flags |=
2946                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2947         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2948         rc = __bnxt_hwrm_func_qcaps(bp);
2949         return rc;
2950 }
2951
2952 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2953 {
2954         struct hwrm_func_cfg_input req = {0};
2955         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2956         int i;
2957         size_t sz;
2958         int rc = 0;
2959         size_t req_buf_sz;
2960
2961         if (!BNXT_PF(bp)) {
2962                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2963                 return -1;
2964         }
2965
2966         rc = bnxt_hwrm_func_qcaps(bp);
2967
2968         if (rc)
2969                 return rc;
2970
2971         bp->pf.active_vfs = num_vfs;
2972
2973         /*
2974          * First, configure the PF to only use one TX ring.  This ensures that
2975          * there are enough rings for all VFs.
2976          *
2977          * If we don't do this, when we call func_alloc() later, we will lock
2978          * extra rings to the PF that won't be available during func_cfg() of
2979          * the VFs.
2980          *
2981          * This has been fixed with firmware versions above 20.6.54
2982          */
2983         bp->pf.func_cfg_flags &=
2984                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2985                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2986         bp->pf.func_cfg_flags |=
2987                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2988         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2989         if (rc)
2990                 return rc;
2991
2992         /*
2993          * Now, create and register a buffer to hold forwarded VF requests
2994          */
2995         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2996         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2997                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2998         if (bp->pf.vf_req_buf == NULL) {
2999                 rc = -ENOMEM;
3000                 goto error_free;
3001         }
3002         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3003                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3004         for (i = 0; i < num_vfs; i++)
3005                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3006                                         (i * HWRM_MAX_REQ_LEN);
3007
3008         rc = bnxt_hwrm_func_buf_rgtr(bp);
3009         if (rc)
3010                 goto error_free;
3011
3012         populate_vf_func_cfg_req(bp, &req, num_vfs);
3013
3014         bp->pf.active_vfs = 0;
3015         for (i = 0; i < num_vfs; i++) {
3016                 add_random_mac_if_needed(bp, &req, i);
3017
3018                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3019                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3020                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3021                 rc = bnxt_hwrm_send_message(bp,
3022                                             &req,
3023                                             sizeof(req),
3024                                             BNXT_USE_CHIMP_MB);
3025
3026                 /* Clear enable flag for next pass */
3027                 req.enables &= ~rte_cpu_to_le_32(
3028                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3029
3030                 if (rc || resp->error_code) {
3031                         PMD_DRV_LOG(ERR,
3032                                 "Failed to initizlie VF %d\n", i);
3033                         PMD_DRV_LOG(ERR,
3034                                 "Not all VFs available. (%d, %d)\n",
3035                                 rc, resp->error_code);
3036                         HWRM_UNLOCK();
3037                         break;
3038                 }
3039
3040                 HWRM_UNLOCK();
3041
3042                 reserve_resources_from_vf(bp, &req, i);
3043                 bp->pf.active_vfs++;
3044                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3045         }
3046
3047         /*
3048          * Now configure the PF to use "the rest" of the resources
3049          * We're using STD_TX_RING_MODE here though which will limit the TX
3050          * rings.  This will allow QoS to function properly.  Not setting this
3051          * will cause PF rings to break bandwidth settings.
3052          */
3053         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3054         if (rc)
3055                 goto error_free;
3056
3057         rc = update_pf_resource_max(bp);
3058         if (rc)
3059                 goto error_free;
3060
3061         return rc;
3062
3063 error_free:
3064         bnxt_hwrm_func_buf_unrgtr(bp);
3065         return rc;
3066 }
3067
3068 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3069 {
3070         struct hwrm_func_cfg_input req = {0};
3071         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3072         int rc;
3073
3074         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3075
3076         req.fid = rte_cpu_to_le_16(0xffff);
3077         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3078         req.evb_mode = bp->pf.evb_mode;
3079
3080         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3081         HWRM_CHECK_RESULT();
3082         HWRM_UNLOCK();
3083
3084         return rc;
3085 }
3086
3087 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3088                                 uint8_t tunnel_type)
3089 {
3090         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3091         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3092         int rc = 0;
3093
3094         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3095         req.tunnel_type = tunnel_type;
3096         req.tunnel_dst_port_val = port;
3097         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3098         HWRM_CHECK_RESULT();
3099
3100         switch (tunnel_type) {
3101         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3102                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3103                 bp->vxlan_port = port;
3104                 break;
3105         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3106                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3107                 bp->geneve_port = port;
3108                 break;
3109         default:
3110                 break;
3111         }
3112
3113         HWRM_UNLOCK();
3114
3115         return rc;
3116 }
3117
3118 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3119                                 uint8_t tunnel_type)
3120 {
3121         struct hwrm_tunnel_dst_port_free_input req = {0};
3122         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3123         int rc = 0;
3124
3125         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3126
3127         req.tunnel_type = tunnel_type;
3128         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3129         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3130
3131         HWRM_CHECK_RESULT();
3132         HWRM_UNLOCK();
3133
3134         return rc;
3135 }
3136
3137 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3138                                         uint32_t flags)
3139 {
3140         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3141         struct hwrm_func_cfg_input req = {0};
3142         int rc;
3143
3144         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3145
3146         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3147         req.flags = rte_cpu_to_le_32(flags);
3148         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3149
3150         HWRM_CHECK_RESULT();
3151         HWRM_UNLOCK();
3152
3153         return rc;
3154 }
3155
3156 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3157 {
3158         uint32_t *flag = flagp;
3159
3160         vnic->flags = *flag;
3161 }
3162
3163 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3164 {
3165         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3166 }
3167
3168 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3169 {
3170         int rc = 0;
3171         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3172         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3173
3174         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3175
3176         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3177         req.req_buf_page_size = rte_cpu_to_le_16(
3178                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3179         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3180         req.req_buf_page_addr0 =
3181                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3182         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3183                 PMD_DRV_LOG(ERR,
3184                         "unable to map buffer address to physical memory\n");
3185                 return -ENOMEM;
3186         }
3187
3188         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3189
3190         HWRM_CHECK_RESULT();
3191         HWRM_UNLOCK();
3192
3193         return rc;
3194 }
3195
3196 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3197 {
3198         int rc = 0;
3199         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3200         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3201
3202         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3203                 return 0;
3204
3205         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3206
3207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3208
3209         HWRM_CHECK_RESULT();
3210         HWRM_UNLOCK();
3211
3212         return rc;
3213 }
3214
3215 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3216 {
3217         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3218         struct hwrm_func_cfg_input req = {0};
3219         int rc;
3220
3221         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3222
3223         req.fid = rte_cpu_to_le_16(0xffff);
3224         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3225         req.enables = rte_cpu_to_le_32(
3226                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3227         req.async_event_cr = rte_cpu_to_le_16(
3228                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3229         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3230
3231         HWRM_CHECK_RESULT();
3232         HWRM_UNLOCK();
3233
3234         return rc;
3235 }
3236
3237 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3238 {
3239         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3240         struct hwrm_func_vf_cfg_input req = {0};
3241         int rc;
3242
3243         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3244
3245         req.enables = rte_cpu_to_le_32(
3246                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3247         req.async_event_cr = rte_cpu_to_le_16(
3248                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
3249         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3250
3251         HWRM_CHECK_RESULT();
3252         HWRM_UNLOCK();
3253
3254         return rc;
3255 }
3256
3257 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3258 {
3259         struct hwrm_func_cfg_input req = {0};
3260         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3261         uint16_t dflt_vlan, fid;
3262         uint32_t func_cfg_flags;
3263         int rc = 0;
3264
3265         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3266
3267         if (is_vf) {
3268                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3269                 fid = bp->pf.vf_info[vf].fid;
3270                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3271         } else {
3272                 fid = rte_cpu_to_le_16(0xffff);
3273                 func_cfg_flags = bp->pf.func_cfg_flags;
3274                 dflt_vlan = bp->vlan;
3275         }
3276
3277         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3278         req.fid = rte_cpu_to_le_16(fid);
3279         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3280         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3281
3282         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3283
3284         HWRM_CHECK_RESULT();
3285         HWRM_UNLOCK();
3286
3287         return rc;
3288 }
3289
3290 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3291                         uint16_t max_bw, uint16_t enables)
3292 {
3293         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3294         struct hwrm_func_cfg_input req = {0};
3295         int rc;
3296
3297         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3298
3299         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3300         req.enables |= rte_cpu_to_le_32(enables);
3301         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3302         req.max_bw = rte_cpu_to_le_32(max_bw);
3303         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3304
3305         HWRM_CHECK_RESULT();
3306         HWRM_UNLOCK();
3307
3308         return rc;
3309 }
3310
3311 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3312 {
3313         struct hwrm_func_cfg_input req = {0};
3314         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3315         int rc = 0;
3316
3317         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3318
3319         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3320         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3321         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3322         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3323
3324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3325
3326         HWRM_CHECK_RESULT();
3327         HWRM_UNLOCK();
3328
3329         return rc;
3330 }
3331
3332 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3333 {
3334         int rc;
3335
3336         if (BNXT_PF(bp))
3337                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3338         else
3339                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3340
3341         return rc;
3342 }
3343
3344 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3345                               void *encaped, size_t ec_size)
3346 {
3347         int rc = 0;
3348         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3349         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3350
3351         if (ec_size > sizeof(req.encap_request))
3352                 return -1;
3353
3354         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3355
3356         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3357         memcpy(req.encap_request, encaped, ec_size);
3358
3359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3360
3361         HWRM_CHECK_RESULT();
3362         HWRM_UNLOCK();
3363
3364         return rc;
3365 }
3366
3367 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3368                                        struct rte_ether_addr *mac)
3369 {
3370         struct hwrm_func_qcfg_input req = {0};
3371         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3372         int rc;
3373
3374         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3375
3376         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3378
3379         HWRM_CHECK_RESULT();
3380
3381         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3382
3383         HWRM_UNLOCK();
3384
3385         return rc;
3386 }
3387
3388 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3389                             void *encaped, size_t ec_size)
3390 {
3391         int rc = 0;
3392         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3393         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3394
3395         if (ec_size > sizeof(req.encap_request))
3396                 return -1;
3397
3398         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3399
3400         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3401         memcpy(req.encap_request, encaped, ec_size);
3402
3403         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3404
3405         HWRM_CHECK_RESULT();
3406         HWRM_UNLOCK();
3407
3408         return rc;
3409 }
3410
3411 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3412                          struct rte_eth_stats *stats, uint8_t rx)
3413 {
3414         int rc = 0;
3415         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3416         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3417
3418         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3419
3420         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3421
3422         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3423
3424         HWRM_CHECK_RESULT();
3425
3426         if (rx) {
3427                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3428                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3429                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3430                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3431                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3432                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3433                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3434                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3435         } else {
3436                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3437                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3438                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3439                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3440                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3441                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3442         }
3443
3444
3445         HWRM_UNLOCK();
3446
3447         return rc;
3448 }
3449
3450 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3451 {
3452         struct hwrm_port_qstats_input req = {0};
3453         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3454         struct bnxt_pf_info *pf = &bp->pf;
3455         int rc;
3456
3457         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3458
3459         req.port_id = rte_cpu_to_le_16(pf->port_id);
3460         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3461         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3462         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3463
3464         HWRM_CHECK_RESULT();
3465         HWRM_UNLOCK();
3466
3467         return rc;
3468 }
3469
3470 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3471 {
3472         struct hwrm_port_clr_stats_input req = {0};
3473         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3474         struct bnxt_pf_info *pf = &bp->pf;
3475         int rc;
3476
3477         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3478         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3479             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3480                 return 0;
3481
3482         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3483
3484         req.port_id = rte_cpu_to_le_16(pf->port_id);
3485         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3486
3487         HWRM_CHECK_RESULT();
3488         HWRM_UNLOCK();
3489
3490         return rc;
3491 }
3492
3493 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3494 {
3495         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3496         struct hwrm_port_led_qcaps_input req = {0};
3497         int rc;
3498
3499         if (BNXT_VF(bp))
3500                 return 0;
3501
3502         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3503         req.port_id = bp->pf.port_id;
3504         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3505
3506         HWRM_CHECK_RESULT();
3507
3508         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3509                 unsigned int i;
3510
3511                 bp->num_leds = resp->num_leds;
3512                 memcpy(bp->leds, &resp->led0_id,
3513                         sizeof(bp->leds[0]) * bp->num_leds);
3514                 for (i = 0; i < bp->num_leds; i++) {
3515                         struct bnxt_led_info *led = &bp->leds[i];
3516
3517                         uint16_t caps = led->led_state_caps;
3518
3519                         if (!led->led_group_id ||
3520                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3521                                 bp->num_leds = 0;
3522                                 break;
3523                         }
3524                 }
3525         }
3526
3527         HWRM_UNLOCK();
3528
3529         return rc;
3530 }
3531
3532 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3533 {
3534         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3535         struct hwrm_port_led_cfg_input req = {0};
3536         struct bnxt_led_cfg *led_cfg;
3537         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3538         uint16_t duration = 0;
3539         int rc, i;
3540
3541         if (!bp->num_leds || BNXT_VF(bp))
3542                 return -EOPNOTSUPP;
3543
3544         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3545
3546         if (led_on) {
3547                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3548                 duration = rte_cpu_to_le_16(500);
3549         }
3550         req.port_id = bp->pf.port_id;
3551         req.num_leds = bp->num_leds;
3552         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3553         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3554                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3555                 led_cfg->led_id = bp->leds[i].led_id;
3556                 led_cfg->led_state = led_state;
3557                 led_cfg->led_blink_on = duration;
3558                 led_cfg->led_blink_off = duration;
3559                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3560         }
3561
3562         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3563
3564         HWRM_CHECK_RESULT();
3565         HWRM_UNLOCK();
3566
3567         return rc;
3568 }
3569
3570 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3571                                uint32_t *length)
3572 {
3573         int rc;
3574         struct hwrm_nvm_get_dir_info_input req = {0};
3575         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3576
3577         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3578
3579         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3580
3581         HWRM_CHECK_RESULT();
3582         HWRM_UNLOCK();
3583
3584         if (!rc) {
3585                 *entries = rte_le_to_cpu_32(resp->entries);
3586                 *length = rte_le_to_cpu_32(resp->entry_length);
3587         }
3588         return rc;
3589 }
3590
3591 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3592 {
3593         int rc;
3594         uint32_t dir_entries;
3595         uint32_t entry_length;
3596         uint8_t *buf;
3597         size_t buflen;
3598         rte_iova_t dma_handle;
3599         struct hwrm_nvm_get_dir_entries_input req = {0};
3600         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3601
3602         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3603         if (rc != 0)
3604                 return rc;
3605
3606         *data++ = dir_entries;
3607         *data++ = entry_length;
3608         len -= 2;
3609         memset(data, 0xff, len);
3610
3611         buflen = dir_entries * entry_length;
3612         buf = rte_malloc("nvm_dir", buflen, 0);
3613         rte_mem_lock_page(buf);
3614         if (buf == NULL)
3615                 return -ENOMEM;
3616         dma_handle = rte_mem_virt2iova(buf);
3617         if (dma_handle == RTE_BAD_IOVA) {
3618                 PMD_DRV_LOG(ERR,
3619                         "unable to map response address to physical memory\n");
3620                 return -ENOMEM;
3621         }
3622         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3623         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3624         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3625
3626         if (rc == 0)
3627                 memcpy(data, buf, len > buflen ? buflen : len);
3628
3629         rte_free(buf);
3630         HWRM_CHECK_RESULT();
3631         HWRM_UNLOCK();
3632
3633         return rc;
3634 }
3635
3636 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3637                              uint32_t offset, uint32_t length,
3638                              uint8_t *data)
3639 {
3640         int rc;
3641         uint8_t *buf;
3642         rte_iova_t dma_handle;
3643         struct hwrm_nvm_read_input req = {0};
3644         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3645
3646         buf = rte_malloc("nvm_item", length, 0);
3647         rte_mem_lock_page(buf);
3648         if (!buf)
3649                 return -ENOMEM;
3650
3651         dma_handle = rte_mem_virt2iova(buf);
3652         if (dma_handle == RTE_BAD_IOVA) {
3653                 PMD_DRV_LOG(ERR,
3654                         "unable to map response address to physical memory\n");
3655                 return -ENOMEM;
3656         }
3657         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3658         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3659         req.dir_idx = rte_cpu_to_le_16(index);
3660         req.offset = rte_cpu_to_le_32(offset);
3661         req.len = rte_cpu_to_le_32(length);
3662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3663         if (rc == 0)
3664                 memcpy(data, buf, length);
3665
3666         rte_free(buf);
3667         HWRM_CHECK_RESULT();
3668         HWRM_UNLOCK();
3669
3670         return rc;
3671 }
3672
3673 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3674 {
3675         int rc;
3676         struct hwrm_nvm_erase_dir_entry_input req = {0};
3677         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3678
3679         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3680         req.dir_idx = rte_cpu_to_le_16(index);
3681         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3682         HWRM_CHECK_RESULT();
3683         HWRM_UNLOCK();
3684
3685         return rc;
3686 }
3687
3688
3689 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3690                           uint16_t dir_ordinal, uint16_t dir_ext,
3691                           uint16_t dir_attr, const uint8_t *data,
3692                           size_t data_len)
3693 {
3694         int rc;
3695         struct hwrm_nvm_write_input req = {0};
3696         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3697         rte_iova_t dma_handle;
3698         uint8_t *buf;
3699
3700         buf = rte_malloc("nvm_write", data_len, 0);
3701         rte_mem_lock_page(buf);
3702         if (!buf)
3703                 return -ENOMEM;
3704
3705         dma_handle = rte_mem_virt2iova(buf);
3706         if (dma_handle == RTE_BAD_IOVA) {
3707                 PMD_DRV_LOG(ERR,
3708                         "unable to map response address to physical memory\n");
3709                 return -ENOMEM;
3710         }
3711         memcpy(buf, data, data_len);
3712
3713         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3714
3715         req.dir_type = rte_cpu_to_le_16(dir_type);
3716         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3717         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3718         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3719         req.dir_data_length = rte_cpu_to_le_32(data_len);
3720         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3721
3722         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3723
3724         rte_free(buf);
3725         HWRM_CHECK_RESULT();
3726         HWRM_UNLOCK();
3727
3728         return rc;
3729 }
3730
3731 static void
3732 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3733 {
3734         uint32_t *count = cbdata;
3735
3736         *count = *count + 1;
3737 }
3738
3739 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3740                                      struct bnxt_vnic_info *vnic __rte_unused)
3741 {
3742         return 0;
3743 }
3744
3745 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3746 {
3747         uint32_t count = 0;
3748
3749         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3750             &count, bnxt_vnic_count_hwrm_stub);
3751
3752         return count;
3753 }
3754
3755 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3756                                         uint16_t *vnic_ids)
3757 {
3758         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3759         struct hwrm_func_vf_vnic_ids_query_output *resp =
3760                                                 bp->hwrm_cmd_resp_addr;
3761         int rc;
3762
3763         /* First query all VNIC ids */
3764         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3765
3766         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3767         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3768         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3769
3770         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3771                 HWRM_UNLOCK();
3772                 PMD_DRV_LOG(ERR,
3773                 "unable to map VNIC ID table address to physical memory\n");
3774                 return -ENOMEM;
3775         }
3776         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3777         if (rc) {
3778                 HWRM_UNLOCK();
3779                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3780                 return -1;
3781         } else if (resp->error_code) {
3782                 rc = rte_le_to_cpu_16(resp->error_code);
3783                 HWRM_UNLOCK();
3784                 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3785                 return -1;
3786         }
3787         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3788
3789         HWRM_UNLOCK();
3790
3791         return rc;
3792 }
3793
3794 /*
3795  * This function queries the VNIC IDs  for a specified VF. It then calls
3796  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3797  * Then it calls the hwrm_cb function to program this new vnic configuration.
3798  */
3799 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3800         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3801         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3802 {
3803         struct bnxt_vnic_info vnic;
3804         int rc = 0;
3805         int i, num_vnic_ids;
3806         uint16_t *vnic_ids;
3807         size_t vnic_id_sz;
3808         size_t sz;
3809
3810         /* First query all VNIC ids */
3811         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3812         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3813                         RTE_CACHE_LINE_SIZE);
3814         if (vnic_ids == NULL) {
3815                 rc = -ENOMEM;
3816                 return rc;
3817         }
3818         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3819                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3820
3821         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3822
3823         if (num_vnic_ids < 0)
3824                 return num_vnic_ids;
3825
3826         /* Retrieve VNIC, update bd_stall then update */
3827
3828         for (i = 0; i < num_vnic_ids; i++) {
3829                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3830                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3831                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3832                 if (rc)
3833                         break;
3834                 if (vnic.mru <= 4)      /* Indicates unallocated */
3835                         continue;
3836
3837                 vnic_cb(&vnic, cbdata);
3838
3839                 rc = hwrm_cb(bp, &vnic);
3840                 if (rc)
3841                         break;
3842         }
3843
3844         rte_free(vnic_ids);
3845
3846         return rc;
3847 }
3848
3849 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3850                                               bool on)
3851 {
3852         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3853         struct hwrm_func_cfg_input req = {0};
3854         int rc;
3855
3856         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3857
3858         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3859         req.enables |= rte_cpu_to_le_32(
3860                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3861         req.vlan_antispoof_mode = on ?
3862                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3863                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3864         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3865
3866         HWRM_CHECK_RESULT();
3867         HWRM_UNLOCK();
3868
3869         return rc;
3870 }
3871
3872 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3873 {
3874         struct bnxt_vnic_info vnic;
3875         uint16_t *vnic_ids;
3876         size_t vnic_id_sz;
3877         int num_vnic_ids, i;
3878         size_t sz;
3879         int rc;
3880
3881         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3882         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3883                         RTE_CACHE_LINE_SIZE);
3884         if (vnic_ids == NULL) {
3885                 rc = -ENOMEM;
3886                 return rc;
3887         }
3888
3889         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3890                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3891
3892         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3893         if (rc <= 0)
3894                 goto exit;
3895         num_vnic_ids = rc;
3896
3897         /*
3898          * Loop through to find the default VNIC ID.
3899          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3900          * by sending the hwrm_func_qcfg command to the firmware.
3901          */
3902         for (i = 0; i < num_vnic_ids; i++) {
3903                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3904                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3905                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3906                                         bp->pf.first_vf_id + vf);
3907                 if (rc)
3908                         goto exit;
3909                 if (vnic.func_default) {
3910                         rte_free(vnic_ids);
3911                         return vnic.fw_vnic_id;
3912                 }
3913         }
3914         /* Could not find a default VNIC. */
3915         PMD_DRV_LOG(ERR, "No default VNIC\n");
3916 exit:
3917         rte_free(vnic_ids);
3918         return -1;
3919 }
3920
3921 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3922                          uint16_t dst_id,
3923                          struct bnxt_filter_info *filter)
3924 {
3925         int rc = 0;
3926         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3927         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3928         uint32_t enables = 0;
3929
3930         if (filter->fw_em_filter_id != UINT64_MAX)
3931                 bnxt_hwrm_clear_em_filter(bp, filter);
3932
3933         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
3934
3935         req.flags = rte_cpu_to_le_32(filter->flags);
3936
3937         enables = filter->enables |
3938               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3939         req.dst_id = rte_cpu_to_le_16(dst_id);
3940
3941         if (filter->ip_addr_type) {
3942                 req.ip_addr_type = filter->ip_addr_type;
3943                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3944         }
3945         if (enables &
3946             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3947                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3948         if (enables &
3949             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3950                 memcpy(req.src_macaddr, filter->src_macaddr,
3951                        RTE_ETHER_ADDR_LEN);
3952         if (enables &
3953             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3954                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3955                        RTE_ETHER_ADDR_LEN);
3956         if (enables &
3957             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3958                 req.ovlan_vid = filter->l2_ovlan;
3959         if (enables &
3960             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3961                 req.ivlan_vid = filter->l2_ivlan;
3962         if (enables &
3963             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3964                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3965         if (enables &
3966             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3967                 req.ip_protocol = filter->ip_protocol;
3968         if (enables &
3969             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3970                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3971         if (enables &
3972             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3973                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3974         if (enables &
3975             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3976                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3977         if (enables &
3978             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3979                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3980         if (enables &
3981             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3982                 req.mirror_vnic_id = filter->mirror_vnic_id;
3983
3984         req.enables = rte_cpu_to_le_32(enables);
3985
3986         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
3987
3988         HWRM_CHECK_RESULT();
3989
3990         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3991         HWRM_UNLOCK();
3992
3993         return rc;
3994 }
3995
3996 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3997 {
3998         int rc = 0;
3999         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4000         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4001
4002         if (filter->fw_em_filter_id == UINT64_MAX)
4003                 return 0;
4004
4005         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4006         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4007
4008         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4009
4010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4011
4012         HWRM_CHECK_RESULT();
4013         HWRM_UNLOCK();
4014
4015         filter->fw_em_filter_id = UINT64_MAX;
4016         filter->fw_l2_filter_id = UINT64_MAX;
4017
4018         return 0;
4019 }
4020
4021 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4022                          uint16_t dst_id,
4023                          struct bnxt_filter_info *filter)
4024 {
4025         int rc = 0;
4026         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4027         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4028                                                 bp->hwrm_cmd_resp_addr;
4029         uint32_t enables = 0;
4030
4031         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4032                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4033
4034         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4035
4036         req.flags = rte_cpu_to_le_32(filter->flags);
4037
4038         enables = filter->enables |
4039               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4040         req.dst_id = rte_cpu_to_le_16(dst_id);
4041
4042
4043         if (filter->ip_addr_type) {
4044                 req.ip_addr_type = filter->ip_addr_type;
4045                 enables |=
4046                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4047         }
4048         if (enables &
4049             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4050                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4051         if (enables &
4052             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4053                 memcpy(req.src_macaddr, filter->src_macaddr,
4054                        RTE_ETHER_ADDR_LEN);
4055         //if (enables &
4056             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4057                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4058                        //RTE_ETHER_ADDR_LEN);
4059         if (enables &
4060             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4061                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4062         if (enables &
4063             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4064                 req.ip_protocol = filter->ip_protocol;
4065         if (enables &
4066             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4067                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4068         if (enables &
4069             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4070                 req.src_ipaddr_mask[0] =
4071                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4072         if (enables &
4073             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4074                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4075         if (enables &
4076             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4077                 req.dst_ipaddr_mask[0] =
4078                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4079         if (enables &
4080             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4081                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4082         if (enables &
4083             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4084                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4085         if (enables &
4086             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4087                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4088         if (enables &
4089             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4090                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4091         if (enables &
4092             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4093                 req.mirror_vnic_id = filter->mirror_vnic_id;
4094
4095         req.enables = rte_cpu_to_le_32(enables);
4096
4097         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4098
4099         HWRM_CHECK_RESULT();
4100
4101         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4102         HWRM_UNLOCK();
4103
4104         return rc;
4105 }
4106
4107 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4108                                 struct bnxt_filter_info *filter)
4109 {
4110         int rc = 0;
4111         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4112         struct hwrm_cfa_ntuple_filter_free_output *resp =
4113                                                 bp->hwrm_cmd_resp_addr;
4114
4115         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4116                 return 0;
4117
4118         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4119
4120         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4121
4122         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4123
4124         HWRM_CHECK_RESULT();
4125         HWRM_UNLOCK();
4126
4127         filter->fw_ntuple_filter_id = UINT64_MAX;
4128
4129         return 0;
4130 }
4131
4132 static int
4133 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4134 {
4135         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4136         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4137         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4138         int nr_ctxs = bp->max_ring_grps;
4139         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4140         uint16_t *ring_tbl = vnic->rss_table;
4141         int max_rings = bp->rx_nr_rings;
4142         int i, j, k, cnt;
4143         int rc = 0;
4144
4145         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4146
4147         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4148         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4149         req.hash_mode_flags = vnic->hash_mode;
4150
4151         req.ring_grp_tbl_addr =
4152             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
4153         req.hash_key_tbl_addr =
4154             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4155
4156         for (i = 0, k = 0; i < nr_ctxs; i++) {
4157                 struct bnxt_rx_ring_info *rxr;
4158                 struct bnxt_cp_ring_info *cpr;
4159
4160                 req.ring_table_pair_index = i;
4161                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4162
4163                 for (j = 0; j < 64; j++) {
4164                         uint16_t ring_id;
4165
4166                         /* Find next active ring. */
4167                         for (cnt = 0; cnt < max_rings; cnt++) {
4168                                 if (rx_queue_state[k] !=
4169                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4170                                         break;
4171                                 if (++k == max_rings)
4172                                         k = 0;
4173                         }
4174
4175                         /* Return if no rings are active. */
4176                         if (cnt == max_rings)
4177                                 return 0;
4178
4179                         /* Add rx/cp ring pair to RSS table. */
4180                         rxr = rxqs[k]->rx_ring;
4181                         cpr = rxqs[k]->cp_ring;
4182
4183                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4184                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4185                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4186                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4187
4188                         if (++k == max_rings)
4189                                 k = 0;
4190                 }
4191                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4192                                             BNXT_USE_CHIMP_MB);
4193
4194                 HWRM_CHECK_RESULT();
4195                 if (rc)
4196                         break;
4197         }
4198
4199         HWRM_UNLOCK();
4200
4201         return rc;
4202 }
4203
4204 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4205 {
4206         unsigned int rss_idx, fw_idx, i;
4207
4208         if (!(vnic->rss_table && vnic->hash_type))
4209                 return 0;
4210
4211         if (BNXT_CHIP_THOR(bp))
4212                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4213
4214         /*
4215          * Fill the RSS hash & redirection table with
4216          * ring group ids for all VNICs
4217          */
4218         for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4219                 rss_idx++, fw_idx++) {
4220                 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4221                         fw_idx %= bp->rx_cp_nr_rings;
4222                         if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
4223                                 break;
4224                         fw_idx++;
4225                 }
4226                 if (i == bp->rx_cp_nr_rings)
4227                         return 0;
4228                 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4229         }
4230         return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4231 }
4232
4233 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4234         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4235 {
4236         uint16_t flags;
4237
4238         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4239
4240         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4241         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4242
4243         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4244         req->num_cmpl_dma_aggr_during_int =
4245                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4246
4247         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4248
4249         /* min timer set to 1/2 of interrupt timer */
4250         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4251
4252         /* buf timer set to 1/4 of interrupt timer */
4253         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4254
4255         req->cmpl_aggr_dma_tmr_during_int =
4256                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4257
4258         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4259                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4260         req->flags = rte_cpu_to_le_16(flags);
4261 }
4262
4263 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4264                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4265 {
4266         struct hwrm_ring_aggint_qcaps_input req = {0};
4267         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4268         uint32_t enables;
4269         uint16_t flags;
4270         int rc;
4271
4272         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4273         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4274         if (rc)
4275                 goto out;
4276
4277         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4278         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4279
4280         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4281                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4282         agg_req->flags = rte_cpu_to_le_16(flags);
4283         enables =
4284          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4285          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4286         agg_req->enables = rte_cpu_to_le_32(enables);
4287
4288 out:
4289         HWRM_CHECK_RESULT();
4290         HWRM_UNLOCK();
4291         return rc;
4292 }
4293
4294 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4295                         struct bnxt_coal *coal, uint16_t ring_id)
4296 {
4297         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4298         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4299                                                 bp->hwrm_cmd_resp_addr;
4300         int rc;
4301
4302         /* Set ring coalesce parameters only for 100G NICs */
4303         if (BNXT_CHIP_THOR(bp)) {
4304                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4305                         return -1;
4306         } else if (bnxt_stratus_device(bp)) {
4307                 bnxt_hwrm_set_coal_params(coal, &req);
4308         } else {
4309                 return 0;
4310         }
4311
4312         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4313         req.ring_id = rte_cpu_to_le_16(ring_id);
4314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4315         HWRM_CHECK_RESULT();
4316         HWRM_UNLOCK();
4317         return 0;
4318 }
4319
4320 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4321 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4322 {
4323         struct hwrm_func_backing_store_qcaps_input req = {0};
4324         struct hwrm_func_backing_store_qcaps_output *resp =
4325                 bp->hwrm_cmd_resp_addr;
4326         int rc;
4327
4328         if (!BNXT_CHIP_THOR(bp) ||
4329             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4330             BNXT_VF(bp) ||
4331             bp->ctx)
4332                 return 0;
4333
4334         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4336         HWRM_CHECK_RESULT_SILENT();
4337
4338         if (!rc) {
4339                 struct bnxt_ctx_pg_info *ctx_pg;
4340                 struct bnxt_ctx_mem_info *ctx;
4341                 int total_alloc_len;
4342                 int i;
4343
4344                 total_alloc_len = sizeof(*ctx);
4345                 ctx = rte_malloc("bnxt_ctx_mem", total_alloc_len,
4346                                  RTE_CACHE_LINE_SIZE);
4347                 if (!ctx) {
4348                         rc = -ENOMEM;
4349                         goto ctx_err;
4350                 }
4351                 memset(ctx, 0, total_alloc_len);
4352
4353                 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4354                                     sizeof(*ctx_pg) * BNXT_MAX_Q,
4355                                     RTE_CACHE_LINE_SIZE);
4356                 if (!ctx_pg) {
4357                         rc = -ENOMEM;
4358                         goto ctx_err;
4359                 }
4360                 for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4361                         ctx->tqm_mem[i] = ctx_pg;
4362
4363                 bp->ctx = ctx;
4364                 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4365                 ctx->qp_min_qp1_entries =
4366                         rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4367                 ctx->qp_max_l2_entries =
4368                         rte_le_to_cpu_16(resp->qp_max_l2_entries);
4369                 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4370                 ctx->srq_max_l2_entries =
4371                         rte_le_to_cpu_16(resp->srq_max_l2_entries);
4372                 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4373                 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4374                 ctx->cq_max_l2_entries =
4375                         rte_le_to_cpu_16(resp->cq_max_l2_entries);
4376                 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4377                 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4378                 ctx->vnic_max_vnic_entries =
4379                         rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4380                 ctx->vnic_max_ring_table_entries =
4381                         rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4382                 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4383                 ctx->stat_max_entries =
4384                         rte_le_to_cpu_32(resp->stat_max_entries);
4385                 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4386                 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4387                 ctx->tqm_min_entries_per_ring =
4388                         rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4389                 ctx->tqm_max_entries_per_ring =
4390                         rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4391                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4392                 if (!ctx->tqm_entries_multiple)
4393                         ctx->tqm_entries_multiple = 1;
4394                 ctx->mrav_max_entries =
4395                         rte_le_to_cpu_32(resp->mrav_max_entries);
4396                 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4397                 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4398                 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4399         } else {
4400                 rc = 0;
4401         }
4402 ctx_err:
4403         HWRM_UNLOCK();
4404         return rc;
4405 }
4406
4407 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4408 {
4409         struct hwrm_func_backing_store_cfg_input req = {0};
4410         struct hwrm_func_backing_store_cfg_output *resp =
4411                 bp->hwrm_cmd_resp_addr;
4412         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4413         struct bnxt_ctx_pg_info *ctx_pg;
4414         uint32_t *num_entries;
4415         uint64_t *pg_dir;
4416         uint8_t *pg_attr;
4417         uint32_t ena;
4418         int i, rc;
4419
4420         if (!ctx)
4421                 return 0;
4422
4423         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4424         req.enables = rte_cpu_to_le_32(enables);
4425
4426         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4427                 ctx_pg = &ctx->qp_mem;
4428                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4429                 req.qp_num_qp1_entries =
4430                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4431                 req.qp_num_l2_entries =
4432                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4433                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4434                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4435                                       &req.qpc_pg_size_qpc_lvl,
4436                                       &req.qpc_page_dir);
4437         }
4438
4439         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4440                 ctx_pg = &ctx->srq_mem;
4441                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4442                 req.srq_num_l2_entries =
4443                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4444                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4445                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4446                                       &req.srq_pg_size_srq_lvl,
4447                                       &req.srq_page_dir);
4448         }
4449
4450         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4451                 ctx_pg = &ctx->cq_mem;
4452                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4453                 req.cq_num_l2_entries =
4454                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4455                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4456                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4457                                       &req.cq_pg_size_cq_lvl,
4458                                       &req.cq_page_dir);
4459         }
4460
4461         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4462                 ctx_pg = &ctx->vnic_mem;
4463                 req.vnic_num_vnic_entries =
4464                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4465                 req.vnic_num_ring_table_entries =
4466                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4467                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4468                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4469                                       &req.vnic_pg_size_vnic_lvl,
4470                                       &req.vnic_page_dir);
4471         }
4472
4473         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4474                 ctx_pg = &ctx->stat_mem;
4475                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4476                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4477                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4478                                       &req.stat_pg_size_stat_lvl,
4479                                       &req.stat_page_dir);
4480         }
4481
4482         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4483         num_entries = &req.tqm_sp_num_entries;
4484         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4485         pg_dir = &req.tqm_sp_page_dir;
4486         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4487         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4488                 if (!(enables & ena))
4489                         continue;
4490
4491                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4492
4493                 ctx_pg = ctx->tqm_mem[i];
4494                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4495                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4496         }
4497
4498         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4499         HWRM_CHECK_RESULT();
4500         HWRM_UNLOCK();
4501         if (rc)
4502                 rc = -EIO;
4503         return rc;
4504 }
4505
4506 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4507 {
4508         struct hwrm_port_qstats_ext_input req = {0};
4509         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4510         struct bnxt_pf_info *pf = &bp->pf;
4511         int rc;
4512
4513         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4514               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4515                 return 0;
4516
4517         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4518
4519         req.port_id = rte_cpu_to_le_16(pf->port_id);
4520         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4521                 req.tx_stat_host_addr =
4522                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4523                 req.tx_stat_size =
4524                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4525         }
4526         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4527                 req.rx_stat_host_addr =
4528                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4529                 req.rx_stat_size =
4530                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4531         }
4532         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4533
4534         if (rc) {
4535                 bp->fw_rx_port_stats_ext_size = 0;
4536                 bp->fw_tx_port_stats_ext_size = 0;
4537         } else {
4538                 bp->fw_rx_port_stats_ext_size =
4539                         rte_le_to_cpu_16(resp->rx_stat_size);
4540                 bp->fw_tx_port_stats_ext_size =
4541                         rte_le_to_cpu_16(resp->tx_stat_size);
4542         }
4543
4544         HWRM_CHECK_RESULT();
4545         HWRM_UNLOCK();
4546
4547         return rc;
4548 }
4549
4550 int
4551 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4552 {
4553         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4554         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4555                 bp->hwrm_cmd_resp_addr;
4556         int rc = 0;
4557
4558         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_KONG(bp));
4559         req.tunnel_type = type;
4560         req.dest_fid = bp->fw_fid;
4561         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4562         HWRM_CHECK_RESULT();
4563
4564         HWRM_UNLOCK();
4565
4566         return rc;
4567 }
4568
4569 int
4570 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4571 {
4572         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4573         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4574                 bp->hwrm_cmd_resp_addr;
4575         int rc = 0;
4576
4577         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_KONG(bp));
4578         req.tunnel_type = type;
4579         req.dest_fid = bp->fw_fid;
4580         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4581         HWRM_CHECK_RESULT();
4582
4583         HWRM_UNLOCK();
4584
4585         return rc;
4586 }
4587
4588 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4589 {
4590         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4591         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4592                 bp->hwrm_cmd_resp_addr;
4593         int rc = 0;
4594
4595         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_KONG(bp));
4596         req.src_fid = bp->fw_fid;
4597         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4598         HWRM_CHECK_RESULT();
4599
4600         if (type)
4601                 *type = resp->tunnel_mask;
4602
4603         HWRM_UNLOCK();
4604
4605         return rc;
4606 }
4607
4608 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4609                                    uint16_t *dst_fid)
4610 {
4611         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4612         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4613                 bp->hwrm_cmd_resp_addr;
4614         int rc = 0;
4615
4616         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_KONG(bp));
4617         req.src_fid = bp->fw_fid;
4618         req.tunnel_type = tun_type;
4619         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4620         HWRM_CHECK_RESULT();
4621
4622         if (dst_fid)
4623                 *dst_fid = resp->dest_fid;
4624
4625         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4626
4627         HWRM_UNLOCK();
4628
4629         return rc;
4630 }
4631
4632 int bnxt_hwrm_set_mac(struct bnxt *bp)
4633 {
4634         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4635         struct hwrm_func_vf_cfg_input req = {0};
4636         int rc = 0;
4637
4638         if (!BNXT_VF(bp))
4639                 return 0;
4640
4641         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4642
4643         req.enables =
4644                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4645         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4646
4647         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4648
4649         HWRM_CHECK_RESULT();
4650
4651         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4652         HWRM_UNLOCK();
4653
4654         return rc;
4655 }