drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                2000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message_locked(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg, uint32_t msg_len)
 175 {
 176         int rc;
 177
 178         rte_spinlock_lock(&bp->hwrm_lock);
 179         rc = bnxt_hwrm_send_message_locked(bp, msg, msg_len);
 180         rte_spinlock_unlock(&bp->hwrm_lock);
 181         return rc;
 182 }
 183
 184 #define HWRM_PREP(req, type, cr, resp) \
 185         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 186         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 187         req.cmpl_ring = rte_cpu_to_le_16(cr); \
 188         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 189         req.target_id = rte_cpu_to_le_16(0xffff); \
 190         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr)
 191
 192 #define HWRM_CHECK_RESULT \
 193         { \
 194                 if (rc) { \
 195                         RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 196                                 __func__, rc); \
 197                         return rc; \
 198                 } \
 199                 if (resp->error_code) { \
 200                         rc = rte_le_to_cpu_16(resp->error_code); \
 201                         if (resp->resp_len >= 16) { \
 202                                 struct hwrm_err_output *tmp_hwrm_err_op = \
 203                                                         (void *)resp; \
 204                                 RTE_LOG(ERR, PMD, \
 205                                         "%s error %d:%d:%08x:%04x\n", \
 206                                         __func__, \
 207                                         rc, tmp_hwrm_err_op->cmd_err, \
 208                                         rte_le_to_cpu_32(\
 209                                                 tmp_hwrm_err_op->opaque_0), \
 210                                         rte_le_to_cpu_16(\
 211                                                 tmp_hwrm_err_op->opaque_1)); \
 212                         } \
 213                         else { \
 214                                 RTE_LOG(ERR, PMD, \
 215                                         "%s error %d\n", __func__, rc); \
 216                         } \
 217                         return rc; \
 218                 } \
 219         }
 220
 221 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 222 {
 223         int rc = 0;
 224         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 225         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 226
 227         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 228         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 229         req.mask = 0;
 230
 231         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 232
 233         HWRM_CHECK_RESULT;
 234
 235         return rc;
 236 }
 237
 238 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 239                                  struct bnxt_vnic_info *vnic,
 240                                  uint16_t vlan_count,
 241                                  struct bnxt_vlan_table_entry *vlan_table)
 242 {
 243         int rc = 0;
 244         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 245         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 246         uint32_t mask = 0;
 247
 248         HWRM_PREP(req, CFA_L2_SET_RX_MASK, -1, resp);
 249         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 250
 251         /* FIXME add multicast flag, when multicast adding options is supported
 252          * by ethtool.
 253          */
 254         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 255                 mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 256         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 257                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 258         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 259                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 260         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 261                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 262         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 263                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 264         if (vnic->mc_addr_cnt) {
 265                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 266                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 267                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 268         }
 269         if (vlan_count && vlan_table) {
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 271                 req.vlan_tag_tbl_addr = rte_cpu_to_le_16(
 272                          rte_mem_virt2phy(vlan_table));
 273                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 274         }
 275         req.mask = rte_cpu_to_le_32(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST |
 276                                     mask);
 277
 278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 279
 280         HWRM_CHECK_RESULT;
 281
 282         return rc;
 283 }
 284
 285 int bnxt_hwrm_clear_filter(struct bnxt *bp,
 286                            struct bnxt_filter_info *filter)
 287 {
 288         int rc = 0;
 289         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 290         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 291
 292         HWRM_PREP(req, CFA_L2_FILTER_FREE, -1, resp);
 293
 294         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 297
 298         HWRM_CHECK_RESULT;
 299
 300         filter->fw_l2_filter_id = -1;
 301
 302         return 0;
 303 }
 304
 305 int bnxt_hwrm_set_filter(struct bnxt *bp,
 306                          uint16_t dst_id,
 307                          struct bnxt_filter_info *filter)
 308 {
 309         int rc = 0;
 310         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 311         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 312         uint32_t enables = 0;
 313
 314         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, -1, resp);
 315
 316         req.flags = rte_cpu_to_le_32(filter->flags);
 317
 318         enables = filter->enables |
 319               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 320         req.dst_id = rte_cpu_to_le_16(dst_id);
 321
 322         if (enables &
 323             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 324                 memcpy(req.l2_addr, filter->l2_addr,
 325                        ETHER_ADDR_LEN);
 326         if (enables &
 327             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 328                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 329                        ETHER_ADDR_LEN);
 330         if (enables &
 331             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 332                 req.l2_ovlan = filter->l2_ovlan;
 333         if (enables &
 334             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 335                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 336         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 337                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 338         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 339                 req.src_type = filter->src_type;
 340
 341         req.enables = rte_cpu_to_le_32(enables);
 342
 343         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 344
 345         HWRM_CHECK_RESULT;
 346
 347         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 348
 349         return rc;
 350 }
 351
 352 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 353 {
 354         int rc = 0;
 355         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 356         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 357         uint16_t new_max_vfs;
 358         int i;
 359
 360         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
 361
 362         req.fid = rte_cpu_to_le_16(0xffff);
 363
 364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 365
 366         HWRM_CHECK_RESULT;
 367
 368         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 369         if (BNXT_PF(bp)) {
 370                 bp->pf.port_id = resp->port_id;
 371                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 372                 new_max_vfs = bp->pdev->max_vfs;
 373                 if (new_max_vfs != bp->pf.max_vfs) {
 374                         if (bp->pf.vf_info)
 375                                 rte_free(bp->pf.vf_info);
 376                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 377                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 378                         bp->pf.max_vfs = new_max_vfs;
 379                         for (i = 0; i < new_max_vfs; i++) {
 380                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 381                                 bp->pf.vf_info[i].vlan_table =
 382                                         rte_zmalloc("VF VLAN table",
 383                                                     getpagesize(),
 384                                                     getpagesize());
 385                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 386                                         RTE_LOG(ERR, PMD,
 387                                         "Fail to alloc VLAN table for VF %d\n",
 388                                         i);
 389                                 else
 390                                         rte_mem_lock_page(
 391                                                 bp->pf.vf_info[i].vlan_table);
 392                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 393                         }
 394                 }
 395         }
 396
 397         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 398         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 399         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 400         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 401         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 402         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 403         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 404         /* TODO: For now, do not support VMDq/RFS on VFs. */
 405         if (BNXT_PF(bp)) {
 406                 if (bp->pf.max_vfs)
 407                         bp->max_vnics = 1;
 408                 else
 409                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 410         } else {
 411                 bp->max_vnics = 1;
 412         }
 413         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 414         if (BNXT_PF(bp))
 415                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 416
 417         return rc;
 418 }
 419
 420 int bnxt_hwrm_func_reset(struct bnxt *bp)
 421 {
 422         int rc = 0;
 423         struct hwrm_func_reset_input req = {.req_type = 0 };
 424         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 425
 426         HWRM_PREP(req, FUNC_RESET, -1, resp);
 427
 428         req.enables = rte_cpu_to_le_32(0);
 429
 430         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 431
 432         HWRM_CHECK_RESULT;
 433
 434         return rc;
 435 }
 436
 437 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 438 {
 439         int rc;
 440         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 441         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 442
 443         if (bp->flags & BNXT_FLAG_REGISTERED)
 444                 return 0;
 445
 446         HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
 447         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 448                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 449         req.ver_maj = RTE_VER_YEAR;
 450         req.ver_min = RTE_VER_MONTH;
 451         req.ver_upd = RTE_VER_MINOR;
 452
 453         if (BNXT_PF(bp)) {
 454                 req.enables |= rte_cpu_to_le_32(
 455                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 456                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 457                        RTE_MIN(sizeof(req.vf_req_fwd),
 458                                sizeof(bp->pf.vf_req_fwd)));
 459         }
 460
 461         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 462         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 463
 464         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 465
 466         HWRM_CHECK_RESULT;
 467
 468         bp->flags |= BNXT_FLAG_REGISTERED;
 469
 470         return rc;
 471 }
 472
 473 int bnxt_hwrm_ver_get(struct bnxt *bp)
 474 {
 475         int rc = 0;
 476         struct hwrm_ver_get_input req = {.req_type = 0 };
 477         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 478         uint32_t my_version;
 479         uint32_t fw_version;
 480         uint16_t max_resp_len;
 481         char type[RTE_MEMZONE_NAMESIZE];
 482         uint32_t dev_caps_cfg;
 483
 484         bp->max_req_len = HWRM_MAX_REQ_LEN;
 485         HWRM_PREP(req, VER_GET, -1, resp);
 486
 487         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 488         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 489         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 490
 491         /*
 492          * Hold the lock since we may be adjusting the response pointers.
 493          */
 494         rte_spinlock_lock(&bp->hwrm_lock);
 495         rc = bnxt_hwrm_send_message_locked(bp, &req, sizeof(req));
 496
 497         HWRM_CHECK_RESULT;
 498
 499         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 500                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 501                 resp->hwrm_intf_upd,
 502                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 503         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 504                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 505         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 506                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 507
 508         my_version = HWRM_VERSION_MAJOR << 16;
 509         my_version |= HWRM_VERSION_MINOR << 8;
 510         my_version |= HWRM_VERSION_UPDATE;
 511
 512         fw_version = resp->hwrm_intf_maj << 16;
 513         fw_version |= resp->hwrm_intf_min << 8;
 514         fw_version |= resp->hwrm_intf_upd;
 515
 516         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 517                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 518                 rc = -EINVAL;
 519                 goto error;
 520         }
 521
 522         if (my_version != fw_version) {
 523                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 524                 if (my_version < fw_version) {
 525                         RTE_LOG(INFO, PMD,
 526                                 "Firmware API version is newer than driver.\n");
 527                         RTE_LOG(INFO, PMD,
 528                                 "The driver may be missing features.\n");
 529                 } else {
 530                         RTE_LOG(INFO, PMD,
 531                                 "Firmware API version is older than driver.\n");
 532                         RTE_LOG(INFO, PMD,
 533                                 "Not all driver features may be functional.\n");
 534                 }
 535         }
 536
 537         if (bp->max_req_len > resp->max_req_win_len) {
 538                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 539                 rc = -EINVAL;
 540         }
 541         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 542         max_resp_len = resp->max_resp_len;
 543         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 544
 545         if (bp->max_resp_len != max_resp_len) {
 546                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 547                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 548                         bp->pdev->addr.devid, bp->pdev->addr.function);
 549
 550                 rte_free(bp->hwrm_cmd_resp_addr);
 551
 552                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 553                 if (bp->hwrm_cmd_resp_addr == NULL) {
 554                         rc = -ENOMEM;
 555                         goto error;
 556                 }
 557                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 558                 bp->hwrm_cmd_resp_dma_addr =
 559                         rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
 560                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 561                         RTE_LOG(ERR, PMD,
 562                         "Unable to map response buffer to physical memory.\n");
 563                         rc = -ENOMEM;
 564                         goto error;
 565                 }
 566                 bp->max_resp_len = max_resp_len;
 567         }
 568
 569         if ((dev_caps_cfg &
 570                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 571             (dev_caps_cfg &
 572              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 573                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 574
 575                 rte_free(bp->hwrm_short_cmd_req_addr);
 576
 577                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 578                                                         bp->max_req_len, 0);
 579                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 580                         rc = -ENOMEM;
 581                         goto error;
 582                 }
 583                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 584                 bp->hwrm_short_cmd_req_dma_addr =
 585                         rte_mem_virt2phy(bp->hwrm_short_cmd_req_addr);
 586                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 587                         rte_free(bp->hwrm_short_cmd_req_addr);
 588                         RTE_LOG(ERR, PMD,
 589                                 "Unable to map buffer to physical memory.\n");
 590                         rc = -ENOMEM;
 591                         goto error;
 592                 }
 593
 594                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 595         }
 596
 597 error:
 598         rte_spinlock_unlock(&bp->hwrm_lock);
 599         return rc;
 600 }
 601
 602 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 603 {
 604         int rc;
 605         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 606         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 607
 608         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 609                 return 0;
 610
 611         HWRM_PREP(req, FUNC_DRV_UNRGTR, -1, resp);
 612         req.flags = flags;
 613
 614         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 615
 616         HWRM_CHECK_RESULT;
 617
 618         bp->flags &= ~BNXT_FLAG_REGISTERED;
 619
 620         return rc;
 621 }
 622
 623 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 624 {
 625         int rc = 0;
 626         struct hwrm_port_phy_cfg_input req = {0};
 627         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 628         uint32_t enables = 0;
 629         uint32_t link_speed_mask =
 630                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 631
 632         HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
 633
 634         if (conf->link_up) {
 635                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 636                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 637                 /*
 638                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 639                  * any auto mode, even "none".
 640                  */
 641                 if (!conf->link_speed) {
 642                         req.auto_mode = conf->auto_mode;
 643                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 644                         if (conf->auto_mode ==
 645                             HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
 646                                 req.auto_link_speed_mask =
 647                                         conf->auto_link_speed_mask;
 648                                 enables |= link_speed_mask;
 649                         }
 650                         if (bp->link_info.auto_link_speed) {
 651                                 req.auto_link_speed =
 652                                         bp->link_info.auto_link_speed;
 653                                 enables |=
 654                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 655                         }
 656                 }
 657                 req.auto_duplex = conf->duplex;
 658                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 659                 req.auto_pause = conf->auto_pause;
 660                 req.force_pause = conf->force_pause;
 661                 /* Set force_pause if there is no auto or if there is a force */
 662                 if (req.auto_pause && !req.force_pause)
 663                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 664                 else
 665                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 666
 667                 req.enables = rte_cpu_to_le_32(enables);
 668         } else {
 669                 req.flags =
 670                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 671                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 672         }
 673
 674         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 675
 676         HWRM_CHECK_RESULT;
 677
 678         return rc;
 679 }
 680
 681 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 682                                    struct bnxt_link_info *link_info)
 683 {
 684         int rc = 0;
 685         struct hwrm_port_phy_qcfg_input req = {0};
 686         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 687
 688         HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
 689
 690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 691
 692         HWRM_CHECK_RESULT;
 693
 694         link_info->phy_link_status = resp->link;
 695         link_info->link_up =
 696                 (link_info->phy_link_status ==
 697                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 698         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 699         link_info->duplex = resp->duplex;
 700         link_info->pause = resp->pause;
 701         link_info->auto_pause = resp->auto_pause;
 702         link_info->force_pause = resp->force_pause;
 703         link_info->auto_mode = resp->auto_mode;
 704
 705         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 706         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 707         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 708         link_info->phy_ver[0] = resp->phy_maj;
 709         link_info->phy_ver[1] = resp->phy_min;
 710         link_info->phy_ver[2] = resp->phy_bld;
 711
 712         return rc;
 713 }
 714
 715 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 716 {
 717         int rc = 0;
 718         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 719         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 720
 721         HWRM_PREP(req, QUEUE_QPORTCFG, -1, resp);
 722
 723         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 724
 725         HWRM_CHECK_RESULT;
 726
 727 #define GET_QUEUE_INFO(x) \
 728         bp->cos_queue[x].id = resp->queue_id##x; \
 729         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 730
 731         GET_QUEUE_INFO(0);
 732         GET_QUEUE_INFO(1);
 733         GET_QUEUE_INFO(2);
 734         GET_QUEUE_INFO(3);
 735         GET_QUEUE_INFO(4);
 736         GET_QUEUE_INFO(5);
 737         GET_QUEUE_INFO(6);
 738         GET_QUEUE_INFO(7);
 739
 740         return rc;
 741 }
 742
 743 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 744                          struct bnxt_ring *ring,
 745                          uint32_t ring_type, uint32_t map_index,
 746                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 747 {
 748         int rc = 0;
 749         uint32_t enables = 0;
 750         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 751         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 752
 753         HWRM_PREP(req, RING_ALLOC, -1, resp);
 754
 755         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 756         req.fbo = rte_cpu_to_le_32(0);
 757         /* Association of ring index with doorbell index */
 758         req.logical_id = rte_cpu_to_le_16(map_index);
 759         req.length = rte_cpu_to_le_32(ring->ring_size);
 760
 761         switch (ring_type) {
 762         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 763                 req.queue_id = bp->cos_queue[0].id;
 764                 /* FALLTHROUGH */
 765         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 766                 req.ring_type = ring_type;
 767                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 768                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 769                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 770                         enables |=
 771                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 772                 break;
 773         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 774                 req.ring_type = ring_type;
 775                 /*
 776                  * TODO: Some HWRM versions crash with
 777                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 778                  */
 779                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 780                 break;
 781         default:
 782                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 783                         ring_type);
 784                 return -1;
 785         }
 786         req.enables = rte_cpu_to_le_32(enables);
 787
 788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 789
 790         if (rc || resp->error_code) {
 791                 if (rc == 0 && resp->error_code)
 792                         rc = rte_le_to_cpu_16(resp->error_code);
 793                 switch (ring_type) {
 794                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 795                         RTE_LOG(ERR, PMD,
 796                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 797                         return rc;
 798                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 799                         RTE_LOG(ERR, PMD,
 800                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 801                         return rc;
 802                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 803                         RTE_LOG(ERR, PMD,
 804                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 805                         return rc;
 806                 default:
 807                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 808                         return rc;
 809                 }
 810         }
 811
 812         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 813         return rc;
 814 }
 815
 816 int bnxt_hwrm_ring_free(struct bnxt *bp,
 817                         struct bnxt_ring *ring, uint32_t ring_type)
 818 {
 819         int rc;
 820         struct hwrm_ring_free_input req = {.req_type = 0 };
 821         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 822
 823         HWRM_PREP(req, RING_FREE, -1, resp);
 824
 825         req.ring_type = ring_type;
 826         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 827
 828         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 829
 830         if (rc || resp->error_code) {
 831                 if (rc == 0 && resp->error_code)
 832                         rc = rte_le_to_cpu_16(resp->error_code);
 833
 834                 switch (ring_type) {
 835                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 836                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 837                                 rc);
 838                         return rc;
 839                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 840                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 841                                 rc);
 842                         return rc;
 843                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 844                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 845                                 rc);
 846                         return rc;
 847                 default:
 848                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 849                         return rc;
 850                 }
 851         }
 852         return 0;
 853 }
 854
 855 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 856 {
 857         int rc = 0;
 858         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 859         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 860
 861         HWRM_PREP(req, RING_GRP_ALLOC, -1, resp);
 862
 863         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 864         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 865         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 866         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 867
 868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 869
 870         HWRM_CHECK_RESULT;
 871
 872         bp->grp_info[idx].fw_grp_id =
 873             rte_le_to_cpu_16(resp->ring_group_id);
 874
 875         return rc;
 876 }
 877
 878 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 879 {
 880         int rc;
 881         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 882         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 883
 884         HWRM_PREP(req, RING_GRP_FREE, -1, resp);
 885
 886         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 887
 888         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 889
 890         HWRM_CHECK_RESULT;
 891
 892         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 893         return rc;
 894 }
 895
 896 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
 897 {
 898         int rc = 0;
 899         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
 900         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
 901
 902         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
 903                 return rc;
 904
 905         HWRM_PREP(req, STAT_CTX_CLR_STATS, -1, resp);
 906
 907         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 908
 909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 910
 911         HWRM_CHECK_RESULT;
 912
 913         return rc;
 914 }
 915
 916 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 917                                 unsigned int idx __rte_unused)
 918 {
 919         int rc;
 920         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
 921         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 922
 923         HWRM_PREP(req, STAT_CTX_ALLOC, -1, resp);
 924
 925         req.update_period_ms = rte_cpu_to_le_32(0);
 926
 927         req.stats_dma_addr =
 928             rte_cpu_to_le_64(cpr->hw_stats_map);
 929
 930         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 931
 932         HWRM_CHECK_RESULT;
 933
 934         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
 935
 936         return rc;
 937 }
 938
 939 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 940                                 unsigned int idx __rte_unused)
 941 {
 942         int rc;
 943         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
 944         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
 945
 946         HWRM_PREP(req, STAT_CTX_FREE, -1, resp);
 947
 948         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
 949
 950         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 951
 952         HWRM_CHECK_RESULT;
 953
 954         return rc;
 955 }
 956
 957 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 958 {
 959         int rc = 0, i, j;
 960         struct hwrm_vnic_alloc_input req = { 0 };
 961         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 962
 963         /* map ring groups to this vnic */
 964         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
 965                 vnic->start_grp_id, vnic->end_grp_id);
 966         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
 967                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
 968         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
 969         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
 970         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
 971         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
 972         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
 973                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
 974         HWRM_PREP(req, VNIC_ALLOC, -1, resp);
 975
 976         if (vnic->func_default)
 977                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
 978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 979
 980         HWRM_CHECK_RESULT;
 981
 982         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
 983         return rc;
 984 }
 985
 986 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
 987                                         struct bnxt_vnic_info *vnic,
 988                                         struct bnxt_plcmodes_cfg *pmode)
 989 {
 990         int rc = 0;
 991         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
 992         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 993
 994         HWRM_PREP(req, VNIC_PLCMODES_QCFG, -1, resp);
 995
 996         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
 997
 998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 999
1000         HWRM_CHECK_RESULT;
1001
1002         pmode->flags = rte_le_to_cpu_32(resp->flags);
1003         /* dflt_vnic bit doesn't exist in the _cfg command */
1004         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1005         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1006         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1007         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1008
1009         return rc;
1010 }
1011
1012 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1013                                        struct bnxt_vnic_info *vnic,
1014                                        struct bnxt_plcmodes_cfg *pmode)
1015 {
1016         int rc = 0;
1017         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1018         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1019
1020         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1021
1022         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1023         req.flags = rte_cpu_to_le_32(pmode->flags);
1024         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1025         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1026         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1027         req.enables = rte_cpu_to_le_32(
1028             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1029             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1030             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1031         );
1032
1033         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1034
1035         HWRM_CHECK_RESULT;
1036
1037         return rc;
1038 }
1039
1040 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1041 {
1042         int rc = 0;
1043         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1044         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1045         uint32_t ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1046         struct bnxt_plcmodes_cfg pmodes;
1047
1048         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1049         if (rc)
1050                 return rc;
1051
1052         HWRM_PREP(req, VNIC_CFG, -1, resp);
1053
1054         /* Only RSS support for now TBD: COS & LB */
1055         req.enables =
1056             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP |
1057                              HWRM_VNIC_CFG_INPUT_ENABLES_MRU);
1058         if (vnic->lb_rule != 0xffff)
1059                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1060         if (vnic->cos_rule != 0xffff)
1061                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1062         if (vnic->rss_rule != 0xffff)
1063                 ctx_enable_flag = HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1064         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1065         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1066         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1067         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1068         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1069         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1070         req.mru = rte_cpu_to_le_16(vnic->mru);
1071         if (vnic->func_default)
1072                 req.flags |=
1073                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1074         if (vnic->vlan_strip)
1075                 req.flags |=
1076                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1077         if (vnic->bd_stall)
1078                 req.flags |=
1079                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1080         if (vnic->roce_dual)
1081                 req.flags |= rte_cpu_to_le_32(
1082                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1083         if (vnic->roce_only)
1084                 req.flags |= rte_cpu_to_le_32(
1085                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1086         if (vnic->rss_dflt_cr)
1087                 req.flags |= rte_cpu_to_le_32(
1088                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1089
1090         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1091
1092         HWRM_CHECK_RESULT;
1093
1094         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1095
1096         return rc;
1097 }
1098
1099 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1100                 int16_t fw_vf_id)
1101 {
1102         int rc = 0;
1103         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1104         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1105
1106         HWRM_PREP(req, VNIC_QCFG, -1, resp);
1107
1108         req.enables =
1109                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1110         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1111         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1112
1113         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1114
1115         HWRM_CHECK_RESULT;
1116
1117         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1118         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1119         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1120         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1121         vnic->mru = rte_le_to_cpu_16(resp->mru);
1122         vnic->func_default = rte_le_to_cpu_32(
1123                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1124         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1125                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1126         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1127                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1128         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1129                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1130         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1131                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1132         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1133                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1134
1135         return rc;
1136 }
1137
1138 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1139 {
1140         int rc = 0;
1141         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1142         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1143                                                 bp->hwrm_cmd_resp_addr;
1144
1145         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, -1, resp);
1146
1147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1148
1149         HWRM_CHECK_RESULT;
1150
1151         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1152
1153         return rc;
1154 }
1155
1156 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1157 {
1158         int rc = 0;
1159         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1160         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1161                                                 bp->hwrm_cmd_resp_addr;
1162
1163         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, -1, resp);
1164
1165         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1166
1167         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1168
1169         HWRM_CHECK_RESULT;
1170
1171         vnic->rss_rule = INVALID_HW_RING_ID;
1172
1173         return rc;
1174 }
1175
1176 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1177 {
1178         int rc = 0;
1179         struct hwrm_vnic_free_input req = {.req_type = 0 };
1180         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1181
1182         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
1183                 return rc;
1184
1185         HWRM_PREP(req, VNIC_FREE, -1, resp);
1186
1187         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1188
1189         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1190
1191         HWRM_CHECK_RESULT;
1192
1193         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1194         return rc;
1195 }
1196
1197 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1198                            struct bnxt_vnic_info *vnic)
1199 {
1200         int rc = 0;
1201         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1202         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1203
1204         HWRM_PREP(req, VNIC_RSS_CFG, -1, resp);
1205
1206         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1207
1208         req.ring_grp_tbl_addr =
1209             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1210         req.hash_key_tbl_addr =
1211             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1212         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1213
1214         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1215
1216         HWRM_CHECK_RESULT;
1217
1218         return rc;
1219 }
1220
1221 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1222                         struct bnxt_vnic_info *vnic)
1223 {
1224         int rc = 0;
1225         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1226         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1227         uint16_t size;
1228
1229         HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp);
1230
1231         req.flags = rte_cpu_to_le_32(
1232                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1233
1234         req.enables = rte_cpu_to_le_32(
1235                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1236
1237         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1238         size -= RTE_PKTMBUF_HEADROOM;
1239
1240         req.jumbo_thresh = rte_cpu_to_le_16(size);
1241         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1242
1243         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1244
1245         HWRM_CHECK_RESULT;
1246
1247         return rc;
1248 }
1249
1250 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1251                         struct bnxt_vnic_info *vnic, bool enable)
1252 {
1253         int rc = 0;
1254         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1255         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1256
1257         HWRM_PREP(req, VNIC_TPA_CFG, -1, resp);
1258
1259         if (enable) {
1260                 req.enables = rte_cpu_to_le_32(
1261                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1262                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1263                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1264                 req.flags = rte_cpu_to_le_32(
1265                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1266                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1267                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1268                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1269                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1270                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1271                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1272                 req.max_agg_segs = rte_cpu_to_le_16(5);
1273                 req.max_aggs =
1274                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1275                 req.min_agg_len = rte_cpu_to_le_32(512);
1276         }
1277
1278         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1279
1280         HWRM_CHECK_RESULT;
1281
1282         return rc;
1283 }
1284
1285 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1286 {
1287         struct hwrm_func_cfg_input req = {0};
1288         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1289         int rc;
1290
1291         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1292         req.enables = rte_cpu_to_le_32(
1293                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1294         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1295         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1296
1297         HWRM_PREP(req, FUNC_CFG, -1, resp);
1298
1299         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1300         HWRM_CHECK_RESULT;
1301
1302         bp->pf.vf_info[vf].random_mac = false;
1303
1304         return rc;
1305 }
1306
1307 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1308                                   uint64_t *dropped)
1309 {
1310         int rc = 0;
1311         struct hwrm_func_qstats_input req = {.req_type = 0};
1312         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1313
1314         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1315
1316         req.fid = rte_cpu_to_le_16(fid);
1317
1318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1319
1320         HWRM_CHECK_RESULT;
1321
1322         if (dropped)
1323                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1324
1325         return rc;
1326 }
1327
1328 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1329                           struct rte_eth_stats *stats)
1330 {
1331         int rc = 0;
1332         struct hwrm_func_qstats_input req = {.req_type = 0};
1333         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1334
1335         HWRM_PREP(req, FUNC_QSTATS, -1, resp);
1336
1337         req.fid = rte_cpu_to_le_16(fid);
1338
1339         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1340
1341         HWRM_CHECK_RESULT;
1342
1343         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1344         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1345         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1346         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1347         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1348         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1349
1350         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1351         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1352         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1353         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1354         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1355         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1356
1357         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1358         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1359
1360         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1361
1362         return rc;
1363 }
1364
1365 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1366 {
1367         int rc = 0;
1368         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1369         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1370
1371         HWRM_PREP(req, FUNC_CLR_STATS, -1, resp);
1372
1373         req.fid = rte_cpu_to_le_16(fid);
1374
1375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1376
1377         HWRM_CHECK_RESULT;
1378
1379         return rc;
1380 }
1381
1382 /*
1383  * HWRM utility functions
1384  */
1385
1386 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1387 {
1388         unsigned int i;
1389         int rc = 0;
1390
1391         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1392                 struct bnxt_tx_queue *txq;
1393                 struct bnxt_rx_queue *rxq;
1394                 struct bnxt_cp_ring_info *cpr;
1395
1396                 if (i >= bp->rx_cp_nr_rings) {
1397                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1398                         cpr = txq->cp_ring;
1399                 } else {
1400                         rxq = bp->rx_queues[i];
1401                         cpr = rxq->cp_ring;
1402                 }
1403
1404                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1405                 if (rc)
1406                         return rc;
1407         }
1408         return 0;
1409 }
1410
1411 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1412 {
1413         int rc;
1414         unsigned int i;
1415         struct bnxt_cp_ring_info *cpr;
1416
1417         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1418
1419                 if (i >= bp->rx_cp_nr_rings)
1420                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1421                 else
1422                         cpr = bp->rx_queues[i]->cp_ring;
1423                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1424                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1425                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1426                         /*
1427                          * TODO. Need a better way to reset grp_info.stats_ctx
1428                          * for Rx rings only. stats_ctx is not saved for Tx
1429                          * in grp_info.
1430                          */
1431                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1432                         if (rc)
1433                                 return rc;
1434                 }
1435         }
1436         return 0;
1437 }
1438
1439 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1440 {
1441         unsigned int i;
1442         int rc = 0;
1443
1444         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1445                 struct bnxt_tx_queue *txq;
1446                 struct bnxt_rx_queue *rxq;
1447                 struct bnxt_cp_ring_info *cpr;
1448
1449                 if (i >= bp->rx_cp_nr_rings) {
1450                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1451                         cpr = txq->cp_ring;
1452                 } else {
1453                         rxq = bp->rx_queues[i];
1454                         cpr = rxq->cp_ring;
1455                 }
1456
1457                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1458
1459                 if (rc)
1460                         return rc;
1461         }
1462         return rc;
1463 }
1464
1465 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1466 {
1467         uint16_t idx;
1468         uint32_t rc = 0;
1469
1470         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1471
1472                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID) {
1473                         RTE_LOG(ERR, PMD,
1474                                 "Attempt to free invalid ring group %d\n",
1475                                 idx);
1476                         continue;
1477                 }
1478
1479                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1480
1481                 if (rc)
1482                         return rc;
1483         }
1484         return rc;
1485 }
1486
1487 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1488                                 unsigned int idx __rte_unused)
1489 {
1490         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1491
1492         bnxt_hwrm_ring_free(bp, cp_ring,
1493                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1494         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1495         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1496         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1497                         sizeof(*cpr->cp_desc_ring));
1498         cpr->cp_raw_cons = 0;
1499 }
1500
1501 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1502 {
1503         unsigned int i;
1504         int rc = 0;
1505
1506         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1507                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1508                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1509                 struct bnxt_ring *ring = txr->tx_ring_struct;
1510                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1511                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1512
1513                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1514                         bnxt_hwrm_ring_free(bp, ring,
1515                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1516                         ring->fw_ring_id = INVALID_HW_RING_ID;
1517                         memset(txr->tx_desc_ring, 0,
1518                                         txr->tx_ring_struct->ring_size *
1519                                         sizeof(*txr->tx_desc_ring));
1520                         memset(txr->tx_buf_ring, 0,
1521                                         txr->tx_ring_struct->ring_size *
1522                                         sizeof(*txr->tx_buf_ring));
1523                         txr->tx_prod = 0;
1524                         txr->tx_cons = 0;
1525                 }
1526                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1527                         bnxt_free_cp_ring(bp, cpr, idx);
1528                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1529                 }
1530         }
1531
1532         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1533                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1534                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1535                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1536                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1537                 unsigned int idx = i + 1;
1538
1539                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1540                         bnxt_hwrm_ring_free(bp, ring,
1541                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1542                         ring->fw_ring_id = INVALID_HW_RING_ID;
1543                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1544                         memset(rxr->rx_desc_ring, 0,
1545                                         rxr->rx_ring_struct->ring_size *
1546                                         sizeof(*rxr->rx_desc_ring));
1547                         memset(rxr->rx_buf_ring, 0,
1548                                         rxr->rx_ring_struct->ring_size *
1549                                         sizeof(*rxr->rx_buf_ring));
1550                         rxr->rx_prod = 0;
1551                         memset(rxr->ag_buf_ring, 0,
1552                                         rxr->ag_ring_struct->ring_size *
1553                                         sizeof(*rxr->ag_buf_ring));
1554                         rxr->ag_prod = 0;
1555                 }
1556                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1557                         bnxt_free_cp_ring(bp, cpr, idx);
1558                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1559                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1560                 }
1561         }
1562
1563         /* Default completion ring */
1564         {
1565                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1566
1567                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1568                         bnxt_free_cp_ring(bp, cpr, 0);
1569                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1570                 }
1571         }
1572
1573         return rc;
1574 }
1575
1576 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1577 {
1578         uint16_t i;
1579         uint32_t rc = 0;
1580
1581         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1582                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1583                 if (rc)
1584                         return rc;
1585         }
1586         return rc;
1587 }
1588
1589 void bnxt_free_hwrm_resources(struct bnxt *bp)
1590 {
1591         /* Release memzone */
1592         rte_free(bp->hwrm_cmd_resp_addr);
1593         rte_free(bp->hwrm_short_cmd_req_addr);
1594         bp->hwrm_cmd_resp_addr = NULL;
1595         bp->hwrm_short_cmd_req_addr = NULL;
1596         bp->hwrm_cmd_resp_dma_addr = 0;
1597         bp->hwrm_short_cmd_req_dma_addr = 0;
1598 }
1599
1600 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1601 {
1602         struct rte_pci_device *pdev = bp->pdev;
1603         char type[RTE_MEMZONE_NAMESIZE];
1604
1605         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1607         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1608         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1609         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1610         if (bp->hwrm_cmd_resp_addr == NULL)
1611                 return -ENOMEM;
1612         bp->hwrm_cmd_resp_dma_addr =
1613                 rte_mem_virt2phy(bp->hwrm_cmd_resp_addr);
1614         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1615                 RTE_LOG(ERR, PMD,
1616                         "unable to map response address to physical memory\n");
1617                 return -ENOMEM;
1618         }
1619         rte_spinlock_init(&bp->hwrm_lock);
1620
1621         return 0;
1622 }
1623
1624 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1625 {
1626         struct bnxt_filter_info *filter;
1627         int rc = 0;
1628
1629         STAILQ_FOREACH(filter, &vnic->filter, next) {
1630                 rc = bnxt_hwrm_clear_filter(bp, filter);
1631                 if (rc)
1632                         break;
1633         }
1634         return rc;
1635 }
1636
1637 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1638 {
1639         struct bnxt_filter_info *filter;
1640         int rc = 0;
1641
1642         STAILQ_FOREACH(filter, &vnic->filter, next) {
1643                 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1644                 if (rc)
1645                         break;
1646         }
1647         return rc;
1648 }
1649
1650 void bnxt_free_tunnel_ports(struct bnxt *bp)
1651 {
1652         if (bp->vxlan_port_cnt)
1653                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1654                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1655         bp->vxlan_port = 0;
1656         if (bp->geneve_port_cnt)
1657                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1658                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1659         bp->geneve_port = 0;
1660 }
1661
1662 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1663 {
1664         struct bnxt_vnic_info *vnic;
1665         unsigned int i;
1666
1667         if (bp->vnic_info == NULL)
1668                 return;
1669
1670         vnic = &bp->vnic_info[0];
1671         if (BNXT_PF(bp))
1672                 bnxt_hwrm_cfa_l2_clear_rx_mask(bp, vnic);
1673
1674         /* VNIC resources */
1675         for (i = 0; i < bp->nr_vnics; i++) {
1676                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1677
1678                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1679
1680                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1681
1682                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1683
1684                 bnxt_hwrm_vnic_free(bp, vnic);
1685         }
1686         /* Ring resources */
1687         bnxt_free_all_hwrm_rings(bp);
1688         bnxt_free_all_hwrm_ring_grps(bp);
1689         bnxt_free_all_hwrm_stat_ctxs(bp);
1690         bnxt_free_tunnel_ports(bp);
1691 }
1692
1693 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1694 {
1695         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1696
1697         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1698                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1699
1700         switch (conf_link_speed) {
1701         case ETH_LINK_SPEED_10M_HD:
1702         case ETH_LINK_SPEED_100M_HD:
1703                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1704         }
1705         return hw_link_duplex;
1706 }
1707
1708 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1709 {
1710         uint16_t eth_link_speed = 0;
1711
1712         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1713                 return ETH_LINK_SPEED_AUTONEG;
1714
1715         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1716         case ETH_LINK_SPEED_100M:
1717         case ETH_LINK_SPEED_100M_HD:
1718                 eth_link_speed =
1719                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1720                 break;
1721         case ETH_LINK_SPEED_1G:
1722                 eth_link_speed =
1723                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1724                 break;
1725         case ETH_LINK_SPEED_2_5G:
1726                 eth_link_speed =
1727                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1728                 break;
1729         case ETH_LINK_SPEED_10G:
1730                 eth_link_speed =
1731                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1732                 break;
1733         case ETH_LINK_SPEED_20G:
1734                 eth_link_speed =
1735                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1736                 break;
1737         case ETH_LINK_SPEED_25G:
1738                 eth_link_speed =
1739                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1740                 break;
1741         case ETH_LINK_SPEED_40G:
1742                 eth_link_speed =
1743                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1744                 break;
1745         case ETH_LINK_SPEED_50G:
1746                 eth_link_speed =
1747                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1748                 break;
1749         default:
1750                 RTE_LOG(ERR, PMD,
1751                         "Unsupported link speed %d; default to AUTO\n",
1752                         conf_link_speed);
1753                 break;
1754         }
1755         return eth_link_speed;
1756 }
1757
1758 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1759                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1760                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1761                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1762
1763 static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
1764 {
1765         uint32_t one_speed;
1766
1767         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1768                 return 0;
1769
1770         if (link_speed & ETH_LINK_SPEED_FIXED) {
1771                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1772
1773                 if (one_speed & (one_speed - 1)) {
1774                         RTE_LOG(ERR, PMD,
1775                                 "Invalid advertised speeds (%u) for port %u\n",
1776                                 link_speed, port_id);
1777                         return -EINVAL;
1778                 }
1779                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1780                         RTE_LOG(ERR, PMD,
1781                                 "Unsupported advertised speed (%u) for port %u\n",
1782                                 link_speed, port_id);
1783                         return -EINVAL;
1784                 }
1785         } else {
1786                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1787                         RTE_LOG(ERR, PMD,
1788                                 "Unsupported advertised speeds (%u) for port %u\n",
1789                                 link_speed, port_id);
1790                         return -EINVAL;
1791                 }
1792         }
1793         return 0;
1794 }
1795
1796 static uint16_t
1797 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1798 {
1799         uint16_t ret = 0;
1800
1801         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1802                 if (bp->link_info.support_speeds)
1803                         return bp->link_info.support_speeds;
1804                 link_speed = BNXT_SUPPORTED_SPEEDS;
1805         }
1806
1807         if (link_speed & ETH_LINK_SPEED_100M)
1808                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1809         if (link_speed & ETH_LINK_SPEED_100M_HD)
1810                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1811         if (link_speed & ETH_LINK_SPEED_1G)
1812                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1813         if (link_speed & ETH_LINK_SPEED_2_5G)
1814                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1815         if (link_speed & ETH_LINK_SPEED_10G)
1816                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1817         if (link_speed & ETH_LINK_SPEED_20G)
1818                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
1819         if (link_speed & ETH_LINK_SPEED_25G)
1820                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
1821         if (link_speed & ETH_LINK_SPEED_40G)
1822                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
1823         if (link_speed & ETH_LINK_SPEED_50G)
1824                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
1825         return ret;
1826 }
1827
1828 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
1829 {
1830         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
1831
1832         switch (hw_link_speed) {
1833         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
1834                 eth_link_speed = ETH_SPEED_NUM_100M;
1835                 break;
1836         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
1837                 eth_link_speed = ETH_SPEED_NUM_1G;
1838                 break;
1839         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
1840                 eth_link_speed = ETH_SPEED_NUM_2_5G;
1841                 break;
1842         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
1843                 eth_link_speed = ETH_SPEED_NUM_10G;
1844                 break;
1845         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
1846                 eth_link_speed = ETH_SPEED_NUM_20G;
1847                 break;
1848         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
1849                 eth_link_speed = ETH_SPEED_NUM_25G;
1850                 break;
1851         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
1852                 eth_link_speed = ETH_SPEED_NUM_40G;
1853                 break;
1854         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
1855                 eth_link_speed = ETH_SPEED_NUM_50G;
1856                 break;
1857         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
1858         default:
1859                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
1860                         hw_link_speed);
1861                 break;
1862         }
1863         return eth_link_speed;
1864 }
1865
1866 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
1867 {
1868         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1869
1870         switch (hw_link_duplex) {
1871         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
1872         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
1873                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
1874                 break;
1875         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
1876                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
1877                 break;
1878         default:
1879                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
1880                         hw_link_duplex);
1881                 break;
1882         }
1883         return eth_link_duplex;
1884 }
1885
1886 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
1887 {
1888         int rc = 0;
1889         struct bnxt_link_info *link_info = &bp->link_info;
1890
1891         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
1892         if (rc) {
1893                 RTE_LOG(ERR, PMD,
1894                         "Get link config failed with rc %d\n", rc);
1895                 goto exit;
1896         }
1897         if (link_info->link_speed)
1898                 link->link_speed =
1899                         bnxt_parse_hw_link_speed(link_info->link_speed);
1900         else
1901                 link->link_speed = ETH_SPEED_NUM_NONE;
1902         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
1903         link->link_status = link_info->link_up;
1904         link->link_autoneg = link_info->auto_mode ==
1905                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
1906                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
1907 exit:
1908         return rc;
1909 }
1910
1911 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
1912 {
1913         int rc = 0;
1914         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1915         struct bnxt_link_info link_req;
1916         uint16_t speed;
1917
1918         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
1919                 return 0;
1920
1921         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
1922                         bp->eth_dev->data->port_id);
1923         if (rc)
1924                 goto error;
1925
1926         memset(&link_req, 0, sizeof(link_req));
1927         link_req.link_up = link_up;
1928         if (!link_up)
1929                 goto port_phy_cfg;
1930
1931         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
1932         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
1933         if (speed == 0) {
1934                 link_req.phy_flags |=
1935                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
1936                 link_req.auto_mode =
1937                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1938                 link_req.auto_link_speed_mask =
1939                         bnxt_parse_eth_link_speed_mask(bp,
1940                                                        dev_conf->link_speeds);
1941         } else {
1942                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
1943                 link_req.link_speed = speed;
1944                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
1945         }
1946         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
1947         link_req.auto_pause = bp->link_info.auto_pause;
1948         link_req.force_pause = bp->link_info.force_pause;
1949
1950 port_phy_cfg:
1951         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
1952         if (rc) {
1953                 RTE_LOG(ERR, PMD,
1954                         "Set link config failed with rc %d\n", rc);
1955         }
1956
1957         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1958 error:
1959         return rc;
1960 }
1961
1962 /* JIRA 22088 */
1963 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
1964 {
1965         struct hwrm_func_qcfg_input req = {0};
1966         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1967         int rc = 0;
1968
1969         HWRM_PREP(req, FUNC_QCFG, -1, resp);
1970         req.fid = rte_cpu_to_le_16(0xffff);
1971
1972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1973
1974         HWRM_CHECK_RESULT;
1975
1976         /* Hard Coded.. 0xfff VLAN ID mask */
1977         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
1978
1979         switch (resp->port_partition_type) {
1980         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
1981         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
1982         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
1983                 bp->port_partition_type = resp->port_partition_type;
1984                 break;
1985         default:
1986                 bp->port_partition_type = 0;
1987                 break;
1988         }
1989
1990         return rc;
1991 }
1992
1993 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
1994                                    struct hwrm_func_qcaps_output *qcaps)
1995 {
1996         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
1997         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
1998                sizeof(qcaps->mac_address));
1999         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2000         qcaps->max_rx_rings = fcfg->num_rx_rings;
2001         qcaps->max_tx_rings = fcfg->num_tx_rings;
2002         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2003         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2004         qcaps->max_vfs = 0;
2005         qcaps->first_vf_id = 0;
2006         qcaps->max_vnics = fcfg->num_vnics;
2007         qcaps->max_decap_records = 0;
2008         qcaps->max_encap_records = 0;
2009         qcaps->max_tx_wm_flows = 0;
2010         qcaps->max_tx_em_flows = 0;
2011         qcaps->max_rx_wm_flows = 0;
2012         qcaps->max_rx_em_flows = 0;
2013         qcaps->max_flow_id = 0;
2014         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2015         qcaps->max_sp_tx_rings = 0;
2016         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2017 }
2018
2019 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2020 {
2021         struct hwrm_func_cfg_input req = {0};
2022         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2023         int rc;
2024
2025         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2026                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2027                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2028                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2029                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2030                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2031                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2032                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2033                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2034                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2035         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2036         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2037         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2038                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2039         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2040         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2041         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2042         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2043         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2044         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2045         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2046         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2047         req.fid = rte_cpu_to_le_16(0xffff);
2048
2049         HWRM_PREP(req, FUNC_CFG, -1, resp);
2050
2051         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2052         HWRM_CHECK_RESULT;
2053
2054         return rc;
2055 }
2056
2057 static void populate_vf_func_cfg_req(struct bnxt *bp,
2058                                      struct hwrm_func_cfg_input *req,
2059                                      int num_vfs)
2060 {
2061         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2062                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2063                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2064                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2065                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2066                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2067                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2068                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2069                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2070                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2071
2072         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2073                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2074         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2075                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2076         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2077                                                 (num_vfs + 1));
2078         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2079         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2080                                                (num_vfs + 1));
2081         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2082         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2083         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2084         /* TODO: For now, do not support VMDq/RFS on VFs. */
2085         req->num_vnics = rte_cpu_to_le_16(1);
2086         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2087                                                  (num_vfs + 1));
2088 }
2089
2090 static void add_random_mac_if_needed(struct bnxt *bp,
2091                                      struct hwrm_func_cfg_input *cfg_req,
2092                                      int vf)
2093 {
2094         struct ether_addr mac;
2095
2096         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2097                 return;
2098
2099         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2100                 cfg_req->enables |=
2101                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2102                 eth_random_addr(cfg_req->dflt_mac_addr);
2103                 bp->pf.vf_info[vf].random_mac = true;
2104         } else {
2105                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2106         }
2107 }
2108
2109 static void reserve_resources_from_vf(struct bnxt *bp,
2110                                       struct hwrm_func_cfg_input *cfg_req,
2111                                       int vf)
2112 {
2113         struct hwrm_func_qcaps_input req = {0};
2114         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2115         int rc;
2116
2117         /* Get the actual allocated values now */
2118         HWRM_PREP(req, FUNC_QCAPS, -1, resp);
2119         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2120         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2121
2122         if (rc) {
2123                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2124                 copy_func_cfg_to_qcaps(cfg_req, resp);
2125         } else if (resp->error_code) {
2126                 rc = rte_le_to_cpu_16(resp->error_code);
2127                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2128                 copy_func_cfg_to_qcaps(cfg_req, resp);
2129         }
2130
2131         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2132         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2133         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2134         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2135         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2136         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2137         /*
2138          * TODO: While not supporting VMDq with VFs, max_vnics is always
2139          * forced to 1 in this case
2140          */
2141         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2142         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2143 }
2144
2145 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2146 {
2147         struct hwrm_func_qcfg_input req = {0};
2148         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2149         int rc;
2150
2151         /* Check for zero MAC address */
2152         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2153         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2154         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2155         if (rc) {
2156                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2157                 return -1;
2158         } else if (resp->error_code) {
2159                 rc = rte_le_to_cpu_16(resp->error_code);
2160                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2161                 return -1;
2162         }
2163         return rte_le_to_cpu_16(resp->vlan);
2164 }
2165
2166 static int update_pf_resource_max(struct bnxt *bp)
2167 {
2168         struct hwrm_func_qcfg_input req = {0};
2169         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2170         int rc;
2171
2172         /* And copy the allocated numbers into the pf struct */
2173         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2174         req.fid = rte_cpu_to_le_16(0xffff);
2175         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2176         HWRM_CHECK_RESULT;
2177
2178         /* Only TX ring value reflects actual allocation? TODO */
2179         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2180         bp->pf.evb_mode = resp->evb_mode;
2181
2182         return rc;
2183 }
2184
2185 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2186 {
2187         int rc;
2188
2189         if (!BNXT_PF(bp)) {
2190                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2191                 return -1;
2192         }
2193
2194         rc = bnxt_hwrm_func_qcaps(bp);
2195         if (rc)
2196                 return rc;
2197
2198         bp->pf.func_cfg_flags &=
2199                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2200                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2201         bp->pf.func_cfg_flags |=
2202                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2203         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2204         return rc;
2205 }
2206
2207 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2208 {
2209         struct hwrm_func_cfg_input req = {0};
2210         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2211         int i;
2212         size_t sz;
2213         int rc = 0;
2214         size_t req_buf_sz;
2215
2216         if (!BNXT_PF(bp)) {
2217                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2218                 return -1;
2219         }
2220
2221         rc = bnxt_hwrm_func_qcaps(bp);
2222
2223         if (rc)
2224                 return rc;
2225
2226         bp->pf.active_vfs = num_vfs;
2227
2228         /*
2229          * First, configure the PF to only use one TX ring.  This ensures that
2230          * there are enough rings for all VFs.
2231          *
2232          * If we don't do this, when we call func_alloc() later, we will lock
2233          * extra rings to the PF that won't be available during func_cfg() of
2234          * the VFs.
2235          *
2236          * This has been fixed with firmware versions above 20.6.54
2237          */
2238         bp->pf.func_cfg_flags &=
2239                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2240                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2241         bp->pf.func_cfg_flags |=
2242                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2243         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2244         if (rc)
2245                 return rc;
2246
2247         /*
2248          * Now, create and register a buffer to hold forwarded VF requests
2249          */
2250         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2251         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2252                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2253         if (bp->pf.vf_req_buf == NULL) {
2254                 rc = -ENOMEM;
2255                 goto error_free;
2256         }
2257         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2258                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2259         for (i = 0; i < num_vfs; i++)
2260                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2261                                         (i * HWRM_MAX_REQ_LEN);
2262
2263         rc = bnxt_hwrm_func_buf_rgtr(bp);
2264         if (rc)
2265                 goto error_free;
2266
2267         populate_vf_func_cfg_req(bp, &req, num_vfs);
2268
2269         bp->pf.active_vfs = 0;
2270         for (i = 0; i < num_vfs; i++) {
2271                 add_random_mac_if_needed(bp, &req, i);
2272
2273                 HWRM_PREP(req, FUNC_CFG, -1, resp);
2274                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2275                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2276                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2277
2278                 /* Clear enable flag for next pass */
2279                 req.enables &= ~rte_cpu_to_le_32(
2280                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2281
2282                 if (rc || resp->error_code) {
2283                         RTE_LOG(ERR, PMD,
2284                                 "Failed to initizlie VF %d\n", i);
2285                         RTE_LOG(ERR, PMD,
2286                                 "Not all VFs available. (%d, %d)\n",
2287                                 rc, resp->error_code);
2288                         break;
2289                 }
2290
2291                 reserve_resources_from_vf(bp, &req, i);
2292                 bp->pf.active_vfs++;
2293         }
2294
2295         /*
2296          * Now configure the PF to use "the rest" of the resources
2297          * We're using STD_TX_RING_MODE here though which will limit the TX
2298          * rings.  This will allow QoS to function properly.  Not setting this
2299          * will cause PF rings to break bandwidth settings.
2300          */
2301         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2302         if (rc)
2303                 goto error_free;
2304
2305         rc = update_pf_resource_max(bp);
2306         if (rc)
2307                 goto error_free;
2308
2309         return rc;
2310
2311 error_free:
2312         bnxt_hwrm_func_buf_unrgtr(bp);
2313         return rc;
2314 }
2315
2316 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2317 {
2318         struct hwrm_func_cfg_input req = {0};
2319         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2320         int rc;
2321
2322         HWRM_PREP(req, FUNC_CFG, -1, resp);
2323
2324         req.fid = rte_cpu_to_le_16(0xffff);
2325         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2326         req.evb_mode = bp->pf.evb_mode;
2327
2328         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2329         HWRM_CHECK_RESULT;
2330
2331         return rc;
2332 }
2333
2334 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2335                                 uint8_t tunnel_type)
2336 {
2337         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2338         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2339         int rc = 0;
2340
2341         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, -1, resp);
2342         req.tunnel_type = tunnel_type;
2343         req.tunnel_dst_port_val = port;
2344         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2345         HWRM_CHECK_RESULT;
2346
2347         switch (tunnel_type) {
2348         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2349                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2350                 bp->vxlan_port = port;
2351                 break;
2352         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2353                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2354                 bp->geneve_port = port;
2355                 break;
2356         default:
2357                 break;
2358         }
2359         return rc;
2360 }
2361
2362 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2363                                 uint8_t tunnel_type)
2364 {
2365         struct hwrm_tunnel_dst_port_free_input req = {0};
2366         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2367         int rc = 0;
2368
2369         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, -1, resp);
2370         req.tunnel_type = tunnel_type;
2371         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2372         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2373         HWRM_CHECK_RESULT;
2374
2375         return rc;
2376 }
2377
2378 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2379                                         uint32_t flags)
2380 {
2381         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2382         struct hwrm_func_cfg_input req = {0};
2383         int rc;
2384
2385         HWRM_PREP(req, FUNC_CFG, -1, resp);
2386         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2387         req.flags = rte_cpu_to_le_32(flags);
2388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2389         HWRM_CHECK_RESULT;
2390
2391         return rc;
2392 }
2393
2394 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2395 {
2396         uint32_t *flag = flagp;
2397
2398         vnic->flags = *flag;
2399 }
2400
2401 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2402 {
2403         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2404 }
2405
2406 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2407 {
2408         int rc = 0;
2409         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2410         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2411
2412         HWRM_PREP(req, FUNC_BUF_RGTR, -1, resp);
2413
2414         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2415         req.req_buf_page_size = rte_cpu_to_le_16(
2416                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2417         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2418         req.req_buf_page_addr[0] =
2419                 rte_cpu_to_le_64(rte_mem_virt2phy(bp->pf.vf_req_buf));
2420         if (req.req_buf_page_addr[0] == 0) {
2421                 RTE_LOG(ERR, PMD,
2422                         "unable to map buffer address to physical memory\n");
2423                 return -ENOMEM;
2424         }
2425
2426         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2427
2428         HWRM_CHECK_RESULT;
2429
2430         return rc;
2431 }
2432
2433 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2434 {
2435         int rc = 0;
2436         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2437         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2438
2439         HWRM_PREP(req, FUNC_BUF_UNRGTR, -1, resp);
2440
2441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2442
2443         HWRM_CHECK_RESULT;
2444
2445         return rc;
2446 }
2447
2448 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2449 {
2450         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2451         struct hwrm_func_cfg_input req = {0};
2452         int rc;
2453
2454         HWRM_PREP(req, FUNC_CFG, -1, resp);
2455         req.fid = rte_cpu_to_le_16(0xffff);
2456         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2457         req.enables = rte_cpu_to_le_32(
2458                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2459         req.async_event_cr = rte_cpu_to_le_16(
2460                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2461         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2462         HWRM_CHECK_RESULT;
2463
2464         return rc;
2465 }
2466
2467 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2468 {
2469         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2470         struct hwrm_func_vf_cfg_input req = {0};
2471         int rc;
2472
2473         HWRM_PREP(req, FUNC_VF_CFG, -1, resp);
2474         req.enables = rte_cpu_to_le_32(
2475                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2476         req.async_event_cr = rte_cpu_to_le_16(
2477                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2478         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2479         HWRM_CHECK_RESULT;
2480
2481         return rc;
2482 }
2483
2484 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2485 {
2486         struct hwrm_func_cfg_input req = {0};
2487         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2488         uint16_t dflt_vlan, fid;
2489         uint32_t func_cfg_flags;
2490         int rc = 0;
2491
2492         HWRM_PREP(req, FUNC_CFG, -1, resp);
2493
2494         if (is_vf) {
2495                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2496                 fid = bp->pf.vf_info[vf].fid;
2497                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2498         } else {
2499                 fid = rte_cpu_to_le_16(0xffff);
2500                 func_cfg_flags = bp->pf.func_cfg_flags;
2501                 dflt_vlan = bp->vlan;
2502         }
2503
2504         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2505         req.fid = rte_cpu_to_le_16(fid);
2506         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2507         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2508
2509         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2510         HWRM_CHECK_RESULT;
2511
2512         return rc;
2513 }
2514
2515 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2516                         uint16_t max_bw, uint16_t enables)
2517 {
2518         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2519         struct hwrm_func_cfg_input req = {0};
2520         int rc;
2521
2522         HWRM_PREP(req, FUNC_CFG, -1, resp);
2523         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2524         req.enables |= rte_cpu_to_le_32(enables);
2525         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2526         req.max_bw = rte_cpu_to_le_32(max_bw);
2527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2528         HWRM_CHECK_RESULT;
2529
2530         return rc;
2531 }
2532
2533 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2534 {
2535         struct hwrm_func_cfg_input req = {0};
2536         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2537         int rc = 0;
2538
2539         HWRM_PREP(req, FUNC_CFG, -1, resp);
2540         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2541         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2542         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2543         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2544
2545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2546         HWRM_CHECK_RESULT;
2547
2548         return rc;
2549 }
2550
2551 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2552                               void *encaped, size_t ec_size)
2553 {
2554         int rc = 0;
2555         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2556         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2557
2558         if (ec_size > sizeof(req.encap_request))
2559                 return -1;
2560
2561         HWRM_PREP(req, REJECT_FWD_RESP, -1, resp);
2562
2563         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2564         memcpy(req.encap_request, encaped, ec_size);
2565
2566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2567
2568         HWRM_CHECK_RESULT;
2569
2570         return rc;
2571 }
2572
2573 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2574                                        struct ether_addr *mac)
2575 {
2576         struct hwrm_func_qcfg_input req = {0};
2577         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2578         int rc;
2579
2580         HWRM_PREP(req, FUNC_QCFG, -1, resp);
2581         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2582         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2583
2584         HWRM_CHECK_RESULT;
2585
2586         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2587         return rc;
2588 }
2589
2590 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2591                             void *encaped, size_t ec_size)
2592 {
2593         int rc = 0;
2594         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2595         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2596
2597         if (ec_size > sizeof(req.encap_request))
2598                 return -1;
2599
2600         HWRM_PREP(req, EXEC_FWD_RESP, -1, resp);
2601
2602         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2603         memcpy(req.encap_request, encaped, ec_size);
2604
2605         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2606
2607         HWRM_CHECK_RESULT;
2608
2609         return rc;
2610 }
2611
2612 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2613                          struct rte_eth_stats *stats)
2614 {
2615         int rc = 0;
2616         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2617         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2618
2619         HWRM_PREP(req, STAT_CTX_QUERY, -1, resp);
2620
2621         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2622
2623         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2624
2625         HWRM_CHECK_RESULT;
2626
2627         stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2628         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2629         stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2630         stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2631         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2632         stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2633
2634         stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2635         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2636         stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2637         stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2638         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2639         stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2640
2641         stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2642         stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2643         stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2644
2645         return rc;
2646 }
2647
2648 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2649 {
2650         struct hwrm_port_qstats_input req = {0};
2651         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2652         struct bnxt_pf_info *pf = &bp->pf;
2653         int rc;
2654
2655         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2656                 return 0;
2657
2658         HWRM_PREP(req, PORT_QSTATS, -1, resp);
2659         req.port_id = rte_cpu_to_le_16(pf->port_id);
2660         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2661         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2662         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2663         HWRM_CHECK_RESULT;
2664         return rc;
2665 }
2666
2667 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2668 {
2669         struct hwrm_port_clr_stats_input req = {0};
2670         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2671         struct bnxt_pf_info *pf = &bp->pf;
2672         int rc;
2673
2674         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2675                 return 0;
2676
2677         HWRM_PREP(req, PORT_CLR_STATS, -1, resp);
2678         req.port_id = rte_cpu_to_le_16(pf->port_id);
2679         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2680         HWRM_CHECK_RESULT;
2681         return rc;
2682 }
2683
2684 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2685 {
2686         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2687         struct hwrm_port_led_qcaps_input req = {0};
2688         int rc;
2689
2690         if (BNXT_VF(bp))
2691                 return 0;
2692
2693         HWRM_PREP(req, PORT_LED_QCAPS, -1, resp);
2694         req.port_id = bp->pf.port_id;
2695         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2696         HWRM_CHECK_RESULT;
2697
2698         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2699                 unsigned int i;
2700
2701                 bp->num_leds = resp->num_leds;
2702                 memcpy(bp->leds, &resp->led0_id,
2703                         sizeof(bp->leds[0]) * bp->num_leds);
2704                 for (i = 0; i < bp->num_leds; i++) {
2705                         struct bnxt_led_info *led = &bp->leds[i];
2706
2707                         uint16_t caps = led->led_state_caps;
2708
2709                         if (!led->led_group_id ||
2710                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2711                                 bp->num_leds = 0;
2712                                 break;
2713                         }
2714                 }
2715         }
2716         return rc;
2717 }
2718
2719 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2720 {
2721         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2722         struct hwrm_port_led_cfg_input req = {0};
2723         struct bnxt_led_cfg *led_cfg;
2724         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2725         uint16_t duration = 0;
2726         int rc, i;
2727
2728         if (!bp->num_leds || BNXT_VF(bp))
2729                 return -EOPNOTSUPP;
2730
2731         HWRM_PREP(req, PORT_LED_CFG, -1, resp);
2732         if (led_on) {
2733                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2734                 duration = rte_cpu_to_le_16(500);
2735         }
2736         req.port_id = bp->pf.port_id;
2737         req.num_leds = bp->num_leds;
2738         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2739         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2740                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2741                 led_cfg->led_id = bp->leds[i].led_id;
2742                 led_cfg->led_state = led_state;
2743                 led_cfg->led_blink_on = duration;
2744                 led_cfg->led_blink_off = duration;
2745                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2746         }
2747
2748         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2749         HWRM_CHECK_RESULT;
2750
2751         return rc;
2752 }
2753
2754 static void
2755 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
2756 {
2757         uint32_t *count = cbdata;
2758
2759         *count = *count + 1;
2760 }
2761
2762 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
2763                                      struct bnxt_vnic_info *vnic __rte_unused)
2764 {
2765         return 0;
2766 }
2767
2768 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
2769 {
2770         uint32_t count = 0;
2771
2772         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
2773             &count, bnxt_vnic_count_hwrm_stub);
2774
2775         return count;
2776 }
2777
2778 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
2779                                         uint16_t *vnic_ids)
2780 {
2781         struct hwrm_func_vf_vnic_ids_query_input req = {0};
2782         struct hwrm_func_vf_vnic_ids_query_output *resp =
2783                                                 bp->hwrm_cmd_resp_addr;
2784         int rc;
2785
2786         /* First query all VNIC ids */
2787         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, -1, resp_vf_vnic_ids);
2788
2789         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
2790         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
2791         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2phy(vnic_ids));
2792
2793         if (req.vnic_id_tbl_addr == 0) {
2794                 RTE_LOG(ERR, PMD,
2795                 "unable to map VNIC ID table address to physical memory\n");
2796                 return -ENOMEM;
2797         }
2798         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2799         if (rc) {
2800                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
2801                 return -1;
2802         } else if (resp->error_code) {
2803                 rc = rte_le_to_cpu_16(resp->error_code);
2804                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
2805                 return -1;
2806         }
2807
2808         return rte_le_to_cpu_32(resp->vnic_id_cnt);
2809 }
2810
2811 /*
2812  * This function queries the VNIC IDs  for a specified VF. It then calls
2813  * the vnic_cb to update the necessary field in vnic_info with cbdata.
2814  * Then it calls the hwrm_cb function to program this new vnic configuration.
2815  */
2816 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
2817         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
2818         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
2819 {
2820         struct bnxt_vnic_info vnic;
2821         int rc = 0;
2822         int i, num_vnic_ids;
2823         uint16_t *vnic_ids;
2824         size_t vnic_id_sz;
2825         size_t sz;
2826
2827         /* First query all VNIC ids */
2828         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2829         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2830                         RTE_CACHE_LINE_SIZE);
2831         if (vnic_ids == NULL) {
2832                 rc = -ENOMEM;
2833                 return rc;
2834         }
2835         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2836                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2837
2838         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2839
2840         if (num_vnic_ids < 0)
2841                 return num_vnic_ids;
2842
2843         /* Retrieve VNIC, update bd_stall then update */
2844
2845         for (i = 0; i < num_vnic_ids; i++) {
2846                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2847                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2848                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
2849                 if (rc)
2850                         break;
2851                 if (vnic.mru <= 4)      /* Indicates unallocated */
2852                         continue;
2853
2854                 vnic_cb(&vnic, cbdata);
2855
2856                 rc = hwrm_cb(bp, &vnic);
2857                 if (rc)
2858                         break;
2859         }
2860
2861         rte_free(vnic_ids);
2862
2863         return rc;
2864 }
2865
2866 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
2867                                               bool on)
2868 {
2869         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2870         struct hwrm_func_cfg_input req = {0};
2871         int rc;
2872
2873         HWRM_PREP(req, FUNC_CFG, -1, resp);
2874         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2875         req.enables |= rte_cpu_to_le_32(
2876                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
2877         req.vlan_antispoof_mode = on ?
2878                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
2879                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
2880         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2881         HWRM_CHECK_RESULT;
2882
2883         return rc;
2884 }
2885
2886 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
2887 {
2888         struct bnxt_vnic_info vnic;
2889         uint16_t *vnic_ids;
2890         size_t vnic_id_sz;
2891         int num_vnic_ids, i;
2892         size_t sz;
2893         int rc;
2894
2895         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
2896         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
2897                         RTE_CACHE_LINE_SIZE);
2898         if (vnic_ids == NULL) {
2899                 rc = -ENOMEM;
2900                 return rc;
2901         }
2902
2903         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
2904                 rte_mem_lock_page(((char *)vnic_ids) + sz);
2905
2906         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
2907         if (rc <= 0)
2908                 goto exit;
2909         num_vnic_ids = rc;
2910
2911         /*
2912          * Loop through to find the default VNIC ID.
2913          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
2914          * by sending the hwrm_func_qcfg command to the firmware.
2915          */
2916         for (i = 0; i < num_vnic_ids; i++) {
2917                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
2918                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
2919                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
2920                                         bp->pf.first_vf_id + vf);
2921                 if (rc)
2922                         goto exit;
2923                 if (vnic.func_default) {
2924                         rte_free(vnic_ids);
2925                         return vnic.fw_vnic_id;
2926                 }
2927         }
2928         /* Could not find a default VNIC. */
2929         RTE_LOG(ERR, PMD, "No default VNIC\n");
2930 exit:
2931         rte_free(vnic_ids);
2932         return -1;
2933 }