drivers/net/bnxt/bnxt_hwrm.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <unistd.h>
   7
   8 #include <rte_byteorder.h>
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_malloc.h>
  12 #include <rte_memzone.h>
  13 #include <rte_version.h>
  14 #include <rte_io.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_rxq.h"
  20 #include "bnxt_rxr.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_txq.h"
  23 #include "bnxt_txr.h"
  24 #include "bnxt_vnic.h"
  25 #include "hsi_struct_def_dpdk.h"
  26
  27 #define HWRM_SPEC_CODE_1_8_3            0x10803
  28 #define HWRM_VERSION_1_9_1              0x10901
  29 #define HWRM_VERSION_1_9_2              0x10903
  30
  31 struct bnxt_plcmodes_cfg {
  32         uint32_t        flags;
  33         uint16_t        jumbo_thresh;
  34         uint16_t        hds_offset;
  35         uint16_t        hds_threshold;
  36 };
  37
  38 static int page_getenum(size_t size)
  39 {
  40         if (size <= 1 << 4)
  41                 return 4;
  42         if (size <= 1 << 12)
  43                 return 12;
  44         if (size <= 1 << 13)
  45                 return 13;
  46         if (size <= 1 << 16)
  47                 return 16;
  48         if (size <= 1 << 21)
  49                 return 21;
  50         if (size <= 1 << 22)
  51                 return 22;
  52         if (size <= 1 << 30)
  53                 return 30;
  54         PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
  55         return sizeof(void *) * 8 - 1;
  56 }
  57
  58 static int page_roundup(size_t size)
  59 {
  60         return 1 << page_getenum(size);
  61 }
  62
  63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
  64                                   uint8_t *pg_attr,
  65                                   uint64_t *pg_dir)
  66 {
  67         if (rmem->nr_pages > 1) {
  68                 *pg_attr = 1;
  69                 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
  70         } else {
  71                 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
  72         }
  73 }
  74
  75 /*
  76  * HWRM Functions (sent to HWRM)
  77  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  78  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  79  * command was failed by the ChiMP.
  80  */
  81
  82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  83                                   uint32_t msg_len, bool use_kong_mb)
  84 {
  85         unsigned int i;
  86         struct input *req = msg;
  87         struct output *resp = bp->hwrm_cmd_resp_addr;
  88         uint32_t *data = msg;
  89         uint8_t *bar;
  90         uint8_t *valid;
  91         uint16_t max_req_len = bp->max_req_len;
  92         struct hwrm_short_input short_input = { 0 };
  93         uint16_t bar_offset = use_kong_mb ?
  94                 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
  95         uint16_t mb_trigger_offset = use_kong_mb ?
  96                 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
  97         uint32_t timeout;
  98
  99         /* Do not send HWRM commands to firmware in error state */
 100         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 101                 return 0;
 102
 103         /* For VER_GET command, set timeout as 50ms */
 104         if (rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 105                 timeout = HWRM_CMD_TIMEOUT;
 106         else
 107                 timeout = bp->hwrm_cmd_timeout;
 108
 109         if (bp->flags & BNXT_FLAG_SHORT_CMD ||
 110             msg_len > bp->max_req_len) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 127         }
 128
 129         /* Write request msg to hwrm channel */
 130         for (i = 0; i < msg_len; i += 4) {
 131                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 132                 rte_write32(*data, bar);
 133                 data++;
 134         }
 135
 136         /* Zero the rest of the request space */
 137         for (; i < max_req_len; i += 4) {
 138                 bar = (uint8_t *)bp->bar0 + bar_offset + i;
 139                 rte_write32(0, bar);
 140         }
 141
 142         /* Ring channel doorbell */
 143         bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
 144         rte_write32(1, bar);
 145         /*
 146          * Make sure the channel doorbell ring command complete before
 147          * reading the response to avoid getting stale or invalid
 148          * responses.
 149          */
 150         rte_io_mb();
 151
 152         /* Poll for the valid bit */
 153         for (i = 0; i < timeout; i++) {
 154                 /* Sanity check on the resp->resp_len */
 155                 rte_cio_rmb();
 156                 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
 157                         /* Last byte of resp contains the valid key */
 158                         valid = (uint8_t *)resp + resp->resp_len - 1;
 159                         if (*valid == HWRM_RESP_VALID_KEY)
 160                                 break;
 161                 }
 162                 rte_delay_us(1);
 163         }
 164
 165         if (i >= timeout) {
 166                 /* Suppress VER_GET timeout messages during reset recovery */
 167                 if (bp->flags & BNXT_FLAG_FW_RESET &&
 168                     rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
 169                         return -ETIMEDOUT;
 170
 171                 PMD_DRV_LOG(ERR, "Error(timeout) sending msg 0x%04x\n",
 172                             req->req_type);
 173                 return -ETIMEDOUT;
 174         }
 175         return 0;
 176 }
 177
 178 /*
 179  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 180  * spinlock, and does initial processing.
 181  *
 182  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 183  * releases the spinlock only if it returns.  If the regular int return codes
 184  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 185  * directly, rather it should be copied and modified to suit the function.
 186  *
 187  * HWRM_UNLOCK() must be called after all response processing is completed.
 188  */
 189 #define HWRM_PREP(req, type, kong) do { \
 190         rte_spinlock_lock(&bp->hwrm_lock); \
 191         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 192         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 193         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 194         req.seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
 195                 rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 196         req.target_id = rte_cpu_to_le_16(0xffff); \
 197         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 198 } while (0)
 199
 200 #define HWRM_CHECK_RESULT_SILENT() do {\
 201         if (rc) { \
 202                 rte_spinlock_unlock(&bp->hwrm_lock); \
 203                 return rc; \
 204         } \
 205         if (resp->error_code) { \
 206                 rc = rte_le_to_cpu_16(resp->error_code); \
 207                 rte_spinlock_unlock(&bp->hwrm_lock); \
 208                 return rc; \
 209         } \
 210 } while (0)
 211
 212 #define HWRM_CHECK_RESULT() do {\
 213         if (rc) { \
 214                 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
 215                 rte_spinlock_unlock(&bp->hwrm_lock); \
 216                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 217                         rc = -EACCES; \
 218                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 219                         rc = -ENOSPC; \
 220                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 221                         rc = -EINVAL; \
 222                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 223                         rc = -ENOTSUP; \
 224                 else if (rc > 0) \
 225                         rc = -EIO; \
 226                 return rc; \
 227         } \
 228         if (resp->error_code) { \
 229                 rc = rte_le_to_cpu_16(resp->error_code); \
 230                 if (resp->resp_len >= 16) { \
 231                         struct hwrm_err_output *tmp_hwrm_err_op = \
 232                                                 (void *)resp; \
 233                         PMD_DRV_LOG(ERR, \
 234                                 "error %d:%d:%08x:%04x\n", \
 235                                 rc, tmp_hwrm_err_op->cmd_err, \
 236                                 rte_le_to_cpu_32(\
 237                                         tmp_hwrm_err_op->opaque_0), \
 238                                 rte_le_to_cpu_16(\
 239                                         tmp_hwrm_err_op->opaque_1)); \
 240                 } else { \
 241                         PMD_DRV_LOG(ERR, "error %d\n", rc); \
 242                 } \
 243                 rte_spinlock_unlock(&bp->hwrm_lock); \
 244                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 245                         rc = -EACCES; \
 246                 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
 247                         rc = -ENOSPC; \
 248                 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
 249                         rc = -EINVAL; \
 250                 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
 251                         rc = -ENOTSUP; \
 252                 else if (rc > 0) \
 253                         rc = -EIO; \
 254                 return rc; \
 255         } \
 256 } while (0)
 257
 258 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 259
 260 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 261 {
 262         int rc = 0;
 263         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 264         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268         req.mask = 0;
 269
 270         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 271
 272         HWRM_CHECK_RESULT();
 273         HWRM_UNLOCK();
 274
 275         return rc;
 276 }
 277
 278 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 279                                  struct bnxt_vnic_info *vnic,
 280                                  uint16_t vlan_count,
 281                                  struct bnxt_vlan_table_entry *vlan_table)
 282 {
 283         int rc = 0;
 284         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 285         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 286         uint32_t mask = 0;
 287
 288         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 289                 return rc;
 290
 291         HWRM_PREP(req, CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
 292         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 293
 294         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 295                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 296         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 297                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 298
 299         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 300                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 301
 302         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
 303                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 304         } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
 305                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 306                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 307                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 308         }
 309         if (vlan_table) {
 310                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 311                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 312                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 313                          rte_mem_virt2iova(vlan_table));
 314                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 315         }
 316         req.mask = rte_cpu_to_le_32(mask);
 317
 318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 319
 320         HWRM_CHECK_RESULT();
 321         HWRM_UNLOCK();
 322
 323         return rc;
 324 }
 325
 326 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 327                         uint16_t vlan_count,
 328                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 329 {
 330         int rc = 0;
 331         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 332         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 333                                                 bp->hwrm_cmd_resp_addr;
 334
 335         /*
 336          * Older HWRM versions did not support this command, and the set_rx_mask
 337          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 338          * removed from set_rx_mask call, and this command was added.
 339          *
 340          * This command is also present from 1.7.8.11 and higher,
 341          * as well as 1.7.8.0
 342          */
 343         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 344                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 345                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 346                                         (11)))
 347                                 return 0;
 348                 }
 349         }
 350         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
 351         req.fid = rte_cpu_to_le_16(fid);
 352
 353         req.vlan_tag_mask_tbl_addr =
 354                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 355         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         return rc;
 363 }
 364
 365 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 366                            struct bnxt_filter_info *filter)
 367 {
 368         int rc = 0;
 369         struct bnxt_filter_info *l2_filter = filter;
 370         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 371         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 372
 373         if (filter->fw_l2_filter_id == UINT64_MAX)
 374                 return 0;
 375
 376         if (filter->matching_l2_fltr_ptr)
 377                 l2_filter = filter->matching_l2_fltr_ptr;
 378
 379         PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
 380                     filter, l2_filter, l2_filter->l2_ref_cnt);
 381
 382         if (l2_filter->l2_ref_cnt > 0)
 383                 l2_filter->l2_ref_cnt--;
 384
 385         if (l2_filter->l2_ref_cnt > 0)
 386                 return 0;
 387
 388         HWRM_PREP(req, CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
 389
 390         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 391
 392         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 393
 394         HWRM_CHECK_RESULT();
 395         HWRM_UNLOCK();
 396
 397         filter->fw_l2_filter_id = UINT64_MAX;
 398
 399         return 0;
 400 }
 401
 402 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 403                          uint16_t dst_id,
 404                          struct bnxt_filter_info *filter)
 405 {
 406         int rc = 0;
 407         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 408         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 409         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 410         const struct rte_eth_vmdq_rx_conf *conf =
 411                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 412         uint32_t enables = 0;
 413         uint16_t j = dst_id - 1;
 414
 415         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 416         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 417             conf->pool_map[j].pools & (1UL << j)) {
 418                 PMD_DRV_LOG(DEBUG,
 419                         "Add vlan %u to vmdq pool %u\n",
 420                         conf->pool_map[j].vlan_id, j);
 421
 422                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 423                 filter->enables |=
 424                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 425                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 426         }
 427
 428         if (filter->fw_l2_filter_id != UINT64_MAX)
 429                 bnxt_hwrm_clear_l2_filter(bp, filter);
 430
 431         HWRM_PREP(req, CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
 432
 433         req.flags = rte_cpu_to_le_32(filter->flags);
 434
 435         enables = filter->enables |
 436               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 437         req.dst_id = rte_cpu_to_le_16(dst_id);
 438
 439         if (enables &
 440             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 441                 memcpy(req.l2_addr, filter->l2_addr,
 442                        RTE_ETHER_ADDR_LEN);
 443         if (enables &
 444             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 445                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 446                        RTE_ETHER_ADDR_LEN);
 447         if (enables &
 448             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 449                 req.l2_ovlan = filter->l2_ovlan;
 450         if (enables &
 451             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 452                 req.l2_ivlan = filter->l2_ivlan;
 453         if (enables &
 454             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 455                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 456         if (enables &
 457             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 458                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 459         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 460                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 461         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 462                 req.src_type = filter->src_type;
 463         if (filter->pri_hint) {
 464                 req.pri_hint = filter->pri_hint;
 465                 req.l2_filter_id_hint =
 466                         rte_cpu_to_le_64(filter->l2_filter_id_hint);
 467         }
 468
 469         req.enables = rte_cpu_to_le_32(enables);
 470
 471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 472
 473         HWRM_CHECK_RESULT();
 474
 475         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 476         HWRM_UNLOCK();
 477
 478         return rc;
 479 }
 480
 481 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
 482 {
 483         struct hwrm_port_mac_cfg_input req = {.req_type = 0};
 484         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 485         uint32_t flags = 0;
 486         int rc;
 487
 488         if (!ptp)
 489                 return 0;
 490
 491         HWRM_PREP(req, PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
 492
 493         if (ptp->rx_filter)
 494                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
 495         else
 496                 flags |=
 497                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
 498         if (ptp->tx_tstamp_en)
 499                 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
 500         else
 501                 flags |=
 502                         HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
 503         req.flags = rte_cpu_to_le_32(flags);
 504         req.enables = rte_cpu_to_le_32
 505                 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
 506         req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
 507
 508         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 509         HWRM_UNLOCK();
 510
 511         return rc;
 512 }
 513
 514 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
 515 {
 516         int rc = 0;
 517         struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
 518         struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 520
 521 /*      if (bp->hwrm_spec_code < 0x10801 || ptp)  TBD  */
 522         if (ptp)
 523                 return 0;
 524
 525         HWRM_PREP(req, PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
 526
 527         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
 528
 529         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 530
 531         HWRM_CHECK_RESULT();
 532
 533         if (!BNXT_CHIP_THOR(bp) &&
 534             !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
 535                 return 0;
 536
 537         if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
 538                 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
 539
 540         ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
 541         if (!ptp)
 542                 return -ENOMEM;
 543
 544         if (!BNXT_CHIP_THOR(bp)) {
 545                 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
 546                         rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
 547                 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
 548                         rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
 549                 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
 550                         rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
 551                 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
 552                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
 553                 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
 554                         rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
 555                 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
 556                         rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
 557                 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
 558                         rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
 559                 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
 560                         rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
 561                 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
 562                         rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
 563         }
 564
 565         ptp->bp = bp;
 566         bp->ptp_cfg = ptp;
 567
 568         return 0;
 569 }
 570
 571 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
 572 {
 573         int rc = 0;
 574         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 575         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 576         uint16_t new_max_vfs;
 577         uint32_t flags;
 578         int i;
 579
 580         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
 581
 582         req.fid = rte_cpu_to_le_16(0xffff);
 583
 584         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 585
 586         HWRM_CHECK_RESULT();
 587
 588         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 589         flags = rte_le_to_cpu_32(resp->flags);
 590         if (BNXT_PF(bp)) {
 591                 bp->pf.port_id = resp->port_id;
 592                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 593                 bp->pf.total_vfs = rte_le_to_cpu_16(resp->max_vfs);
 594                 new_max_vfs = bp->pdev->max_vfs;
 595                 if (new_max_vfs != bp->pf.max_vfs) {
 596                         if (bp->pf.vf_info)
 597                                 rte_free(bp->pf.vf_info);
 598                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 599                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 600                         bp->pf.max_vfs = new_max_vfs;
 601                         for (i = 0; i < new_max_vfs; i++) {
 602                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 603                                 bp->pf.vf_info[i].vlan_table =
 604                                         rte_zmalloc("VF VLAN table",
 605                                                     getpagesize(),
 606                                                     getpagesize());
 607                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 608                                         PMD_DRV_LOG(ERR,
 609                                         "Fail to alloc VLAN table for VF %d\n",
 610                                         i);
 611                                 else
 612                                         rte_mem_lock_page(
 613                                                 bp->pf.vf_info[i].vlan_table);
 614                                 bp->pf.vf_info[i].vlan_as_table =
 615                                         rte_zmalloc("VF VLAN AS table",
 616                                                     getpagesize(),
 617                                                     getpagesize());
 618                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 619                                         PMD_DRV_LOG(ERR,
 620                                         "Alloc VLAN AS table for VF %d fail\n",
 621                                         i);
 622                                 else
 623                                         rte_mem_lock_page(
 624                                                bp->pf.vf_info[i].vlan_as_table);
 625                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 626                         }
 627                 }
 628         }
 629
 630         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 631         memcpy(bp->dflt_mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
 632         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 633         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 634         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 635         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 636         bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 637         bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
 638         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 639         if (!BNXT_CHIP_THOR(bp))
 640                 bp->max_l2_ctx += bp->max_rx_em_flows;
 641         /* TODO: For now, do not support VMDq/RFS on VFs. */
 642         if (BNXT_PF(bp)) {
 643                 if (bp->pf.max_vfs)
 644                         bp->max_vnics = 1;
 645                 else
 646                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 647         } else {
 648                 bp->max_vnics = 1;
 649         }
 650         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 651         if (BNXT_PF(bp)) {
 652                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 653                 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
 654                         bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
 655                         PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
 656                         HWRM_UNLOCK();
 657                         bnxt_hwrm_ptp_qcfg(bp);
 658                 }
 659         }
 660
 661         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
 662                 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
 663
 664         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
 665                 bp->flags |= BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 666                 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
 667         } else {
 668                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
 669         }
 670
 671         if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
 672                 bp->flags |= BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 673         else
 674                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD;
 675
 676         HWRM_UNLOCK();
 677
 678         return rc;
 679 }
 680
 681 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 682 {
 683         int rc;
 684
 685         rc = __bnxt_hwrm_func_qcaps(bp);
 686         if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
 687                 rc = bnxt_alloc_ctx_mem(bp);
 688                 if (rc)
 689                         return rc;
 690
 691                 rc = bnxt_hwrm_func_resc_qcaps(bp);
 692                 if (!rc)
 693                         bp->flags |= BNXT_FLAG_NEW_RM;
 694         }
 695
 696         return rc;
 697 }
 698
 699 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
 700 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
 701 {
 702         int rc = 0;
 703         struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
 704         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 705
 706         HWRM_PREP(req, VNIC_QCAPS, BNXT_USE_CHIMP_MB);
 707
 708         req.target_id = rte_cpu_to_le_16(0xffff);
 709
 710         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 711
 712         HWRM_CHECK_RESULT();
 713
 714         if (rte_le_to_cpu_32(resp->flags) &
 715             HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
 716                 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
 717                 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
 718         }
 719
 720         bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
 721
 722         HWRM_UNLOCK();
 723
 724         return rc;
 725 }
 726
 727 int bnxt_hwrm_func_reset(struct bnxt *bp)
 728 {
 729         int rc = 0;
 730         struct hwrm_func_reset_input req = {.req_type = 0 };
 731         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 732
 733         HWRM_PREP(req, FUNC_RESET, BNXT_USE_CHIMP_MB);
 734
 735         req.enables = rte_cpu_to_le_32(0);
 736
 737         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 738
 739         HWRM_CHECK_RESULT();
 740         HWRM_UNLOCK();
 741
 742         return rc;
 743 }
 744
 745 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 746 {
 747         int rc;
 748         uint32_t flags = 0;
 749         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 750         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 751
 752         if (bp->flags & BNXT_FLAG_REGISTERED)
 753                 return 0;
 754
 755         flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
 756         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 757                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
 758
 759         /* PFs and trusted VFs should indicate the support of the
 760          * Master capability on non Stingray platform
 761          */
 762         if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
 763                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
 764
 765         HWRM_PREP(req, FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
 766         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 767                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 768         req.ver_maj = RTE_VER_YEAR;
 769         req.ver_min = RTE_VER_MONTH;
 770         req.ver_upd = RTE_VER_MINOR;
 771
 772         if (BNXT_PF(bp)) {
 773                 req.enables |= rte_cpu_to_le_32(
 774                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
 775                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 776                        RTE_MIN(sizeof(req.vf_req_fwd),
 777                                sizeof(bp->pf.vf_req_fwd)));
 778
 779                 /*
 780                  * PF can sniff HWRM API issued by VF. This can be set up by
 781                  * linux driver and inherited by the DPDK PF driver. Clear
 782                  * this HWRM sniffer list in FW because DPDK PF driver does
 783                  * not support this.
 784                  */
 785                 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
 786         }
 787
 788         req.flags = rte_cpu_to_le_32(flags);
 789
 790         req.async_event_fwd[0] |=
 791                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
 792                                  ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
 793                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
 794                                  ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
 795                                  ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
 796         if (bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY)
 797                 req.async_event_fwd[0] |=
 798                         rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
 799         req.async_event_fwd[1] |=
 800                 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
 801                                  ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
 802
 803         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 804
 805         HWRM_CHECK_RESULT();
 806
 807         flags = rte_le_to_cpu_32(resp->flags);
 808         if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
 809                 bp->flags |= BNXT_FLAG_FW_CAP_IF_CHANGE;
 810
 811         HWRM_UNLOCK();
 812
 813         bp->flags |= BNXT_FLAG_REGISTERED;
 814
 815         return rc;
 816 }
 817
 818 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
 819 {
 820         if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
 821                 return 0;
 822
 823         return bnxt_hwrm_func_reserve_vf_resc(bp, true);
 824 }
 825
 826 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
 827 {
 828         int rc;
 829         uint32_t flags = 0;
 830         uint32_t enables;
 831         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 832         struct hwrm_func_vf_cfg_input req = {0};
 833
 834         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
 835
 836         enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS  |
 837                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS   |
 838                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS  |
 839                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
 840                   HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
 841
 842         if (BNXT_HAS_RING_GRPS(bp)) {
 843                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
 844                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
 845         }
 846
 847         req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
 848         req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
 849                                             AGG_RING_MULTIPLIER);
 850         req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
 851         req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
 852                                               bp->tx_nr_rings +
 853                                               BNXT_NUM_ASYNC_CPR(bp));
 854         req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
 855         if (bp->vf_resv_strategy ==
 856             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
 857                 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
 858                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
 859                            HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
 860                 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
 861                 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
 862                 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
 863         }
 864
 865         if (test)
 866                 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
 867                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
 868                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
 869                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
 870                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
 871                         HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
 872
 873         if (test && BNXT_HAS_RING_GRPS(bp))
 874                 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
 875
 876         req.flags = rte_cpu_to_le_32(flags);
 877         req.enables |= rte_cpu_to_le_32(enables);
 878
 879         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 880
 881         if (test)
 882                 HWRM_CHECK_RESULT_SILENT();
 883         else
 884                 HWRM_CHECK_RESULT();
 885
 886         HWRM_UNLOCK();
 887         return rc;
 888 }
 889
 890 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
 891 {
 892         int rc;
 893         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 894         struct hwrm_func_resource_qcaps_input req = {0};
 895
 896         HWRM_PREP(req, FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
 897         req.fid = rte_cpu_to_le_16(0xffff);
 898
 899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 900
 901         HWRM_CHECK_RESULT();
 902
 903         if (BNXT_VF(bp)) {
 904                 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 905                 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 906                 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 907                 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 908                 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 909                 /* func_resource_qcaps does not return max_rx_em_flows.
 910                  * So use the value provided by func_qcaps.
 911                  */
 912                 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 913                 if (!BNXT_CHIP_THOR(bp))
 914                         bp->max_l2_ctx += bp->max_rx_em_flows;
 915                 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 916                 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 917         }
 918         bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
 919         bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
 920         if (bp->vf_resv_strategy >
 921             HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
 922                 bp->vf_resv_strategy =
 923                 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
 924
 925         HWRM_UNLOCK();
 926         return rc;
 927 }
 928
 929 int bnxt_hwrm_ver_get(struct bnxt *bp)
 930 {
 931         int rc = 0;
 932         struct hwrm_ver_get_input req = {.req_type = 0 };
 933         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 934         uint32_t fw_version;
 935         uint16_t max_resp_len;
 936         char type[RTE_MEMZONE_NAMESIZE];
 937         uint32_t dev_caps_cfg;
 938
 939         bp->max_req_len = HWRM_MAX_REQ_LEN;
 940         HWRM_PREP(req, VER_GET, BNXT_USE_CHIMP_MB);
 941
 942         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 943         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 944         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 945
 946         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 947
 948         if (bp->flags & BNXT_FLAG_FW_RESET)
 949                 HWRM_CHECK_RESULT_SILENT();
 950         else
 951                 HWRM_CHECK_RESULT();
 952
 953         PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
 954                 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
 955                 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
 956                 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
 957         bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
 958                      (resp->hwrm_fw_min_8b << 16) |
 959                      (resp->hwrm_fw_bld_8b << 8) |
 960                      resp->hwrm_fw_rsvd_8b;
 961         PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
 962                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 963
 964         fw_version = resp->hwrm_intf_maj_8b << 16;
 965         fw_version |= resp->hwrm_intf_min_8b << 8;
 966         fw_version |= resp->hwrm_intf_upd_8b;
 967         bp->hwrm_spec_code = fw_version;
 968
 969         /* def_req_timeout value is in milliseconds */
 970         bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
 971         /* convert timeout to usec */
 972         bp->hwrm_cmd_timeout *= 1000;
 973         if (!bp->hwrm_cmd_timeout)
 974                 bp->hwrm_cmd_timeout = HWRM_CMD_TIMEOUT;
 975
 976         if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
 977                 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
 978                 rc = -EINVAL;
 979                 goto error;
 980         }
 981
 982         if (bp->max_req_len > resp->max_req_win_len) {
 983                 PMD_DRV_LOG(ERR, "Unsupported request length\n");
 984                 rc = -EINVAL;
 985         }
 986         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 987         bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 988         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
 989                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
 990
 991         max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
 992         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 993
 994         if (bp->max_resp_len != max_resp_len) {
 995                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 996                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 997                         bp->pdev->addr.devid, bp->pdev->addr.function);
 998
 999                 rte_free(bp->hwrm_cmd_resp_addr);
1000
1001                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1002                 if (bp->hwrm_cmd_resp_addr == NULL) {
1003                         rc = -ENOMEM;
1004                         goto error;
1005                 }
1006                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1007                 bp->hwrm_cmd_resp_dma_addr =
1008                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1009                 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1010                         PMD_DRV_LOG(ERR,
1011                         "Unable to map response buffer to physical memory.\n");
1012                         rc = -ENOMEM;
1013                         goto error;
1014                 }
1015                 bp->max_resp_len = max_resp_len;
1016         }
1017
1018         if ((dev_caps_cfg &
1019                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1020             (dev_caps_cfg &
1021              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1022                 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1023                 bp->flags |= BNXT_FLAG_SHORT_CMD;
1024         }
1025
1026         if (((dev_caps_cfg &
1027               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1028              (dev_caps_cfg &
1029               HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1030             bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1031                 sprintf(type, "bnxt_hwrm_short_%04x:%02x:%02x:%02x",
1032                         bp->pdev->addr.domain, bp->pdev->addr.bus,
1033                         bp->pdev->addr.devid, bp->pdev->addr.function);
1034
1035                 rte_free(bp->hwrm_short_cmd_req_addr);
1036
1037                 bp->hwrm_short_cmd_req_addr =
1038                                 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1039                 if (bp->hwrm_short_cmd_req_addr == NULL) {
1040                         rc = -ENOMEM;
1041                         goto error;
1042                 }
1043                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
1044                 bp->hwrm_short_cmd_req_dma_addr =
1045                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
1046                 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1047                         rte_free(bp->hwrm_short_cmd_req_addr);
1048                         PMD_DRV_LOG(ERR,
1049                                 "Unable to map buffer to physical memory.\n");
1050                         rc = -ENOMEM;
1051                         goto error;
1052                 }
1053         }
1054         if (dev_caps_cfg &
1055             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1056                 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1057                 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1058         }
1059         if (dev_caps_cfg &
1060             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1061                 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1062         if (dev_caps_cfg &
1063             HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1064                 bp->flags |= BNXT_FLAG_ADV_FLOW_MGMT;
1065                 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1066         }
1067
1068 error:
1069         HWRM_UNLOCK();
1070         return rc;
1071 }
1072
1073 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1074 {
1075         int rc;
1076         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1077         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1078
1079         if (!(bp->flags & BNXT_FLAG_REGISTERED))
1080                 return 0;
1081
1082         HWRM_PREP(req, FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1083         req.flags = flags;
1084
1085         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1086
1087         HWRM_CHECK_RESULT();
1088         HWRM_UNLOCK();
1089
1090         return rc;
1091 }
1092
1093 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1094 {
1095         int rc = 0;
1096         struct hwrm_port_phy_cfg_input req = {0};
1097         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1098         uint32_t enables = 0;
1099
1100         HWRM_PREP(req, PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1101
1102         if (conf->link_up) {
1103                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1104                 if (bp->link_info.auto_mode && conf->link_speed) {
1105                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1106                         PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1107                 }
1108
1109                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1110                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1111                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1112                 /*
1113                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1114                  * any auto mode, even "none".
1115                  */
1116                 if (!conf->link_speed) {
1117                         /* No speeds specified. Enable AutoNeg - all speeds */
1118                         req.auto_mode =
1119                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1120                 }
1121                 /* AutoNeg - Advertise speeds specified. */
1122                 if (conf->auto_link_speed_mask &&
1123                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1124                         req.auto_mode =
1125                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1126                         req.auto_link_speed_mask =
1127                                 conf->auto_link_speed_mask;
1128                         enables |=
1129                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1130                 }
1131
1132                 req.auto_duplex = conf->duplex;
1133                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1134                 req.auto_pause = conf->auto_pause;
1135                 req.force_pause = conf->force_pause;
1136                 /* Set force_pause if there is no auto or if there is a force */
1137                 if (req.auto_pause && !req.force_pause)
1138                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1139                 else
1140                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1141
1142                 req.enables = rte_cpu_to_le_32(enables);
1143         } else {
1144                 req.flags =
1145                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1146                 PMD_DRV_LOG(INFO, "Force Link Down\n");
1147         }
1148
1149         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1150
1151         HWRM_CHECK_RESULT();
1152         HWRM_UNLOCK();
1153
1154         return rc;
1155 }
1156
1157 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1158                                    struct bnxt_link_info *link_info)
1159 {
1160         int rc = 0;
1161         struct hwrm_port_phy_qcfg_input req = {0};
1162         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1163
1164         HWRM_PREP(req, PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1165
1166         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1167
1168         HWRM_CHECK_RESULT();
1169
1170         link_info->phy_link_status = resp->link;
1171         link_info->link_up =
1172                 (link_info->phy_link_status ==
1173                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1174         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1175         link_info->duplex = resp->duplex_cfg;
1176         link_info->pause = resp->pause;
1177         link_info->auto_pause = resp->auto_pause;
1178         link_info->force_pause = resp->force_pause;
1179         link_info->auto_mode = resp->auto_mode;
1180         link_info->phy_type = resp->phy_type;
1181         link_info->media_type = resp->media_type;
1182
1183         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1184         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1185         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1186         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1187         link_info->phy_ver[0] = resp->phy_maj;
1188         link_info->phy_ver[1] = resp->phy_min;
1189         link_info->phy_ver[2] = resp->phy_bld;
1190
1191         HWRM_UNLOCK();
1192
1193         PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1194         PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1195         PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1196         PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1197         PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1198                     link_info->auto_link_speed_mask);
1199         PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1200                     link_info->force_link_speed);
1201
1202         return rc;
1203 }
1204
1205 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1206 {
1207         int rc = 0;
1208         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1209         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1210         uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1211         int i;
1212
1213 get_rx_info:
1214         HWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1215
1216         req.flags = rte_cpu_to_le_32(dir);
1217         /* HWRM Version >= 1.9.1 */
1218         if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
1219                 req.drv_qmap_cap =
1220                         HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1221         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1222
1223         HWRM_CHECK_RESULT();
1224
1225         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1226                 GET_TX_QUEUE_INFO(0);
1227                 GET_TX_QUEUE_INFO(1);
1228                 GET_TX_QUEUE_INFO(2);
1229                 GET_TX_QUEUE_INFO(3);
1230                 GET_TX_QUEUE_INFO(4);
1231                 GET_TX_QUEUE_INFO(5);
1232                 GET_TX_QUEUE_INFO(6);
1233                 GET_TX_QUEUE_INFO(7);
1234         } else  {
1235                 GET_RX_QUEUE_INFO(0);
1236                 GET_RX_QUEUE_INFO(1);
1237                 GET_RX_QUEUE_INFO(2);
1238                 GET_RX_QUEUE_INFO(3);
1239                 GET_RX_QUEUE_INFO(4);
1240                 GET_RX_QUEUE_INFO(5);
1241                 GET_RX_QUEUE_INFO(6);
1242                 GET_RX_QUEUE_INFO(7);
1243         }
1244
1245         HWRM_UNLOCK();
1246
1247         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1248                 goto done;
1249
1250         if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1251                 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1252         } else {
1253                 int j;
1254
1255                 /* iterate and find the COSq profile to use for Tx */
1256                 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1257                         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1258                                 if (bp->tx_cos_queue[i].id != 0xff)
1259                                         bp->tx_cosq_id[j++] =
1260                                                 bp->tx_cos_queue[i].id;
1261                         }
1262                 } else {
1263                         for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1264                                 if (bp->tx_cos_queue[i].profile ==
1265                                         HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1266                                         bp->tx_cosq_id[0] =
1267                                                 bp->tx_cos_queue[i].id;
1268                                         break;
1269                                 }
1270                         }
1271                 }
1272         }
1273
1274         bp->max_tc = resp->max_configurable_queues;
1275         bp->max_lltc = resp->max_configurable_lossless_queues;
1276         if (bp->max_tc > BNXT_MAX_QUEUE)
1277                 bp->max_tc = BNXT_MAX_QUEUE;
1278         bp->max_q = bp->max_tc;
1279
1280         if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1281                 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1282                 goto get_rx_info;
1283         }
1284
1285 done:
1286         return rc;
1287 }
1288
1289 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1290                          struct bnxt_ring *ring,
1291                          uint32_t ring_type, uint32_t map_index,
1292                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1293                          uint16_t tx_cosq_id)
1294 {
1295         int rc = 0;
1296         uint32_t enables = 0;
1297         struct hwrm_ring_alloc_input req = {.req_type = 0 };
1298         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1299         struct rte_mempool *mb_pool;
1300         uint16_t rx_buf_size;
1301
1302         HWRM_PREP(req, RING_ALLOC, BNXT_USE_CHIMP_MB);
1303
1304         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1305         req.fbo = rte_cpu_to_le_32(0);
1306         /* Association of ring index with doorbell index */
1307         req.logical_id = rte_cpu_to_le_16(map_index);
1308         req.length = rte_cpu_to_le_32(ring->ring_size);
1309
1310         switch (ring_type) {
1311         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1312                 req.ring_type = ring_type;
1313                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1314                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1315                 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1316                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1317                         enables |=
1318                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1319                 break;
1320         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1321                 req.ring_type = ring_type;
1322                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1323                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1324                 if (BNXT_CHIP_THOR(bp)) {
1325                         mb_pool = bp->rx_queues[0]->mb_pool;
1326                         rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1327                                       RTE_PKTMBUF_HEADROOM;
1328                         rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1329                         req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1330                         enables |=
1331                                 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1332                 }
1333                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1334                         enables |=
1335                                 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1336                 break;
1337         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1338                 req.ring_type = ring_type;
1339                 if (BNXT_HAS_NQ(bp)) {
1340                         /* Association of cp ring with nq */
1341                         req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1342                         enables |=
1343                                 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1344                 }
1345                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1346                 break;
1347         case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1348                 req.ring_type = ring_type;
1349                 req.page_size = BNXT_PAGE_SHFT;
1350                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1351                 break;
1352         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1353                 req.ring_type = ring_type;
1354                 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1355
1356                 mb_pool = bp->rx_queues[0]->mb_pool;
1357                 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1358                               RTE_PKTMBUF_HEADROOM;
1359                 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1360                 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1361
1362                 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1363                 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1364                            HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1365                            HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1366                 break;
1367         default:
1368                 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1369                         ring_type);
1370                 HWRM_UNLOCK();
1371                 return -EINVAL;
1372         }
1373         req.enables = rte_cpu_to_le_32(enables);
1374
1375         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1376
1377         if (rc || resp->error_code) {
1378                 if (rc == 0 && resp->error_code)
1379                         rc = rte_le_to_cpu_16(resp->error_code);
1380                 switch (ring_type) {
1381                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1382                         PMD_DRV_LOG(ERR,
1383                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1384                         HWRM_UNLOCK();
1385                         return rc;
1386                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1387                         PMD_DRV_LOG(ERR,
1388                                     "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1389                         HWRM_UNLOCK();
1390                         return rc;
1391                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1392                         PMD_DRV_LOG(ERR,
1393                                     "hwrm_ring_alloc rx agg failed. rc:%d\n",
1394                                     rc);
1395                         HWRM_UNLOCK();
1396                         return rc;
1397                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1398                         PMD_DRV_LOG(ERR,
1399                                     "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1400                         HWRM_UNLOCK();
1401                         return rc;
1402                 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1403                         PMD_DRV_LOG(ERR,
1404                                     "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1405                         HWRM_UNLOCK();
1406                         return rc;
1407                 default:
1408                         PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1409                         HWRM_UNLOCK();
1410                         return rc;
1411                 }
1412         }
1413
1414         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1415         HWRM_UNLOCK();
1416         return rc;
1417 }
1418
1419 int bnxt_hwrm_ring_free(struct bnxt *bp,
1420                         struct bnxt_ring *ring, uint32_t ring_type)
1421 {
1422         int rc;
1423         struct hwrm_ring_free_input req = {.req_type = 0 };
1424         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1425
1426         HWRM_PREP(req, RING_FREE, BNXT_USE_CHIMP_MB);
1427
1428         req.ring_type = ring_type;
1429         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1430
1431         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1432
1433         if (rc || resp->error_code) {
1434                 if (rc == 0 && resp->error_code)
1435                         rc = rte_le_to_cpu_16(resp->error_code);
1436                 HWRM_UNLOCK();
1437
1438                 switch (ring_type) {
1439                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1440                         PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1441                                 rc);
1442                         return rc;
1443                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1444                         PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1445                                 rc);
1446                         return rc;
1447                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1448                         PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1449                                 rc);
1450                         return rc;
1451                 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1452                         PMD_DRV_LOG(ERR,
1453                                     "hwrm_ring_free nq failed. rc:%d\n", rc);
1454                         return rc;
1455                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1456                         PMD_DRV_LOG(ERR,
1457                                     "hwrm_ring_free agg failed. rc:%d\n", rc);
1458                         return rc;
1459                 default:
1460                         PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1461                         return rc;
1462                 }
1463         }
1464         HWRM_UNLOCK();
1465         return 0;
1466 }
1467
1468 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1469 {
1470         int rc = 0;
1471         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1472         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1473
1474         HWRM_PREP(req, RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1475
1476         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1477         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1478         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1479         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1480
1481         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1482
1483         HWRM_CHECK_RESULT();
1484
1485         bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1486
1487         HWRM_UNLOCK();
1488
1489         return rc;
1490 }
1491
1492 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1493 {
1494         int rc;
1495         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1496         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1497
1498         HWRM_PREP(req, RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1499
1500         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1501
1502         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1503
1504         HWRM_CHECK_RESULT();
1505         HWRM_UNLOCK();
1506
1507         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1508         return rc;
1509 }
1510
1511 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1512 {
1513         int rc = 0;
1514         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1515         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1516
1517         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1518                 return rc;
1519
1520         HWRM_PREP(req, STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1521
1522         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1523
1524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1525
1526         HWRM_CHECK_RESULT();
1527         HWRM_UNLOCK();
1528
1529         return rc;
1530 }
1531
1532 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1533                                 unsigned int idx __rte_unused)
1534 {
1535         int rc;
1536         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1537         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1538
1539         HWRM_PREP(req, STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1540
1541         req.update_period_ms = rte_cpu_to_le_32(0);
1542
1543         req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1544
1545         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1546
1547         HWRM_CHECK_RESULT();
1548
1549         cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1550
1551         HWRM_UNLOCK();
1552
1553         return rc;
1554 }
1555
1556 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1557                                 unsigned int idx __rte_unused)
1558 {
1559         int rc;
1560         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1561         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1562
1563         HWRM_PREP(req, STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1564
1565         req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1566
1567         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1568
1569         HWRM_CHECK_RESULT();
1570         HWRM_UNLOCK();
1571
1572         return rc;
1573 }
1574
1575 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1576 {
1577         int rc = 0, i, j;
1578         struct hwrm_vnic_alloc_input req = { 0 };
1579         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1580
1581         if (!BNXT_HAS_RING_GRPS(bp))
1582                 goto skip_ring_grps;
1583
1584         /* map ring groups to this vnic */
1585         PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1586                 vnic->start_grp_id, vnic->end_grp_id);
1587         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1588                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1589
1590         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1591         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1592         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1593         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1594
1595 skip_ring_grps:
1596         vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1597                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
1598         HWRM_PREP(req, VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1599
1600         if (vnic->func_default)
1601                 req.flags =
1602                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1603         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1604
1605         HWRM_CHECK_RESULT();
1606
1607         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1608         HWRM_UNLOCK();
1609         PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1610         return rc;
1611 }
1612
1613 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1614                                         struct bnxt_vnic_info *vnic,
1615                                         struct bnxt_plcmodes_cfg *pmode)
1616 {
1617         int rc = 0;
1618         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1619         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1620
1621         HWRM_PREP(req, VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1622
1623         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1624
1625         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1626
1627         HWRM_CHECK_RESULT();
1628
1629         pmode->flags = rte_le_to_cpu_32(resp->flags);
1630         /* dflt_vnic bit doesn't exist in the _cfg command */
1631         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1632         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1633         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1634         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1635
1636         HWRM_UNLOCK();
1637
1638         return rc;
1639 }
1640
1641 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1642                                        struct bnxt_vnic_info *vnic,
1643                                        struct bnxt_plcmodes_cfg *pmode)
1644 {
1645         int rc = 0;
1646         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1647         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1648
1649         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1650                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1651                 return rc;
1652         }
1653
1654         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1655
1656         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1657         req.flags = rte_cpu_to_le_32(pmode->flags);
1658         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1659         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1660         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1661         req.enables = rte_cpu_to_le_32(
1662             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1663             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1664             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1665         );
1666
1667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1668
1669         HWRM_CHECK_RESULT();
1670         HWRM_UNLOCK();
1671
1672         return rc;
1673 }
1674
1675 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1676 {
1677         int rc = 0;
1678         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1679         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1680         struct bnxt_plcmodes_cfg pmodes = { 0 };
1681         uint32_t ctx_enable_flag = 0;
1682         uint32_t enables = 0;
1683
1684         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1685                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1686                 return rc;
1687         }
1688
1689         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1690         if (rc)
1691                 return rc;
1692
1693         HWRM_PREP(req, VNIC_CFG, BNXT_USE_CHIMP_MB);
1694
1695         if (BNXT_CHIP_THOR(bp)) {
1696                 struct bnxt_rx_queue *rxq =
1697                         bp->eth_dev->data->rx_queues[vnic->start_grp_id];
1698                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1699                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1700
1701                 req.default_rx_ring_id =
1702                         rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1703                 req.default_cmpl_ring_id =
1704                         rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1705                 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1706                           HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1707                 goto config_mru;
1708         }
1709
1710         /* Only RSS support for now TBD: COS & LB */
1711         enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1712         if (vnic->lb_rule != 0xffff)
1713                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1714         if (vnic->cos_rule != 0xffff)
1715                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1716         if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1717                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1718                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1719         }
1720         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1721                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1722                 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1723         }
1724
1725         enables |= ctx_enable_flag;
1726         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1727         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1728         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1729         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1730
1731 config_mru:
1732         req.enables = rte_cpu_to_le_32(enables);
1733         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1734         req.mru = rte_cpu_to_le_16(vnic->mru);
1735         /* Configure default VNIC only once. */
1736         if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1737                 req.flags |=
1738                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1739                 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1740         }
1741         if (vnic->vlan_strip)
1742                 req.flags |=
1743                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1744         if (vnic->bd_stall)
1745                 req.flags |=
1746                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1747         if (vnic->roce_dual)
1748                 req.flags |= rte_cpu_to_le_32(
1749                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1750         if (vnic->roce_only)
1751                 req.flags |= rte_cpu_to_le_32(
1752                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1753         if (vnic->rss_dflt_cr)
1754                 req.flags |= rte_cpu_to_le_32(
1755                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1756
1757         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1758
1759         HWRM_CHECK_RESULT();
1760         HWRM_UNLOCK();
1761
1762         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1763
1764         return rc;
1765 }
1766
1767 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1768                 int16_t fw_vf_id)
1769 {
1770         int rc = 0;
1771         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1772         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1773
1774         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1775                 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1776                 return rc;
1777         }
1778         HWRM_PREP(req, VNIC_QCFG, BNXT_USE_CHIMP_MB);
1779
1780         req.enables =
1781                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1782         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1783         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1784
1785         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1786
1787         HWRM_CHECK_RESULT();
1788
1789         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1790         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1791         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1792         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1793         vnic->mru = rte_le_to_cpu_16(resp->mru);
1794         vnic->func_default = rte_le_to_cpu_32(
1795                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1796         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1797                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1798         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1799                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1800         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1801                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1802         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1803                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1804         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1805                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1806
1807         HWRM_UNLOCK();
1808
1809         return rc;
1810 }
1811
1812 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1813                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1814 {
1815         int rc = 0;
1816         uint16_t ctx_id;
1817         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1818         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1819                                                 bp->hwrm_cmd_resp_addr;
1820
1821         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1822
1823         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824         HWRM_CHECK_RESULT();
1825
1826         ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1827         if (!BNXT_HAS_RING_GRPS(bp))
1828                 vnic->fw_grp_ids[ctx_idx] = ctx_id;
1829         else if (ctx_idx == 0)
1830                 vnic->rss_rule = ctx_id;
1831
1832         HWRM_UNLOCK();
1833
1834         return rc;
1835 }
1836
1837 static
1838 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
1839                              struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1840 {
1841         int rc = 0;
1842         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1843         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1844                                                 bp->hwrm_cmd_resp_addr;
1845
1846         if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
1847                 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1848                 return rc;
1849         }
1850         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
1851
1852         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
1853
1854         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1855
1856         HWRM_CHECK_RESULT();
1857         HWRM_UNLOCK();
1858
1859         return rc;
1860 }
1861
1862 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1863 {
1864         int rc = 0;
1865
1866         if (BNXT_CHIP_THOR(bp)) {
1867                 int j;
1868
1869                 for (j = 0; j < vnic->num_lb_ctxts; j++) {
1870                         rc = _bnxt_hwrm_vnic_ctx_free(bp,
1871                                                       vnic,
1872                                                       vnic->fw_grp_ids[j]);
1873                         vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
1874                 }
1875                 vnic->num_lb_ctxts = 0;
1876         } else {
1877                 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
1878                 vnic->rss_rule = INVALID_HW_RING_ID;
1879         }
1880
1881         return rc;
1882 }
1883
1884 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1885 {
1886         int rc = 0;
1887         struct hwrm_vnic_free_input req = {.req_type = 0 };
1888         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1889
1890         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1891                 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1892                 return rc;
1893         }
1894
1895         HWRM_PREP(req, VNIC_FREE, BNXT_USE_CHIMP_MB);
1896
1897         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1898
1899         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1900
1901         HWRM_CHECK_RESULT();
1902         HWRM_UNLOCK();
1903
1904         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1905         /* Configure default VNIC again if necessary. */
1906         if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
1907                 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
1908
1909         return rc;
1910 }
1911
1912 static int
1913 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1914 {
1915         int i;
1916         int rc = 0;
1917         int nr_ctxs = vnic->num_lb_ctxts;
1918         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1919         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1920
1921         for (i = 0; i < nr_ctxs; i++) {
1922                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1923
1924                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1925                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1926                 req.hash_mode_flags = vnic->hash_mode;
1927
1928                 req.hash_key_tbl_addr =
1929                         rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1930
1931                 req.ring_grp_tbl_addr =
1932                         rte_cpu_to_le_64(vnic->rss_table_dma_addr +
1933                                          i * HW_HASH_INDEX_SIZE);
1934                 req.ring_table_pair_index = i;
1935                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
1936
1937                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
1938                                             BNXT_USE_CHIMP_MB);
1939
1940                 HWRM_CHECK_RESULT();
1941                 HWRM_UNLOCK();
1942         }
1943
1944         return rc;
1945 }
1946
1947 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1948                            struct bnxt_vnic_info *vnic)
1949 {
1950         int rc = 0;
1951         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1952         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1953
1954         if (!vnic->rss_table)
1955                 return 0;
1956
1957         if (BNXT_CHIP_THOR(bp))
1958                 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
1959
1960         HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
1961
1962         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1963         req.hash_mode_flags = vnic->hash_mode;
1964
1965         req.ring_grp_tbl_addr =
1966             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1967         req.hash_key_tbl_addr =
1968             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1969         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1970         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1971
1972         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1973
1974         HWRM_CHECK_RESULT();
1975         HWRM_UNLOCK();
1976
1977         return rc;
1978 }
1979
1980 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1981                         struct bnxt_vnic_info *vnic)
1982 {
1983         int rc = 0;
1984         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1985         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1986         uint16_t size;
1987
1988         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1989                 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1990                 return rc;
1991         }
1992
1993         HWRM_PREP(req, VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1994
1995         req.flags = rte_cpu_to_le_32(
1996                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1997
1998         req.enables = rte_cpu_to_le_32(
1999                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2000
2001         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2002         size -= RTE_PKTMBUF_HEADROOM;
2003         size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2004
2005         req.jumbo_thresh = rte_cpu_to_le_16(size);
2006         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2007
2008         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2009
2010         HWRM_CHECK_RESULT();
2011         HWRM_UNLOCK();
2012
2013         return rc;
2014 }
2015
2016 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2017                         struct bnxt_vnic_info *vnic, bool enable)
2018 {
2019         int rc = 0;
2020         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2021         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2022
2023         if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2024                 if (enable)
2025                         PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2026                 return -ENOTSUP;
2027         }
2028
2029         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2030                 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2031                 return 0;
2032         }
2033
2034         HWRM_PREP(req, VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2035
2036         if (enable) {
2037                 req.enables = rte_cpu_to_le_32(
2038                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2039                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2040                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2041                 req.flags = rte_cpu_to_le_32(
2042                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2043                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2044                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2045                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2046                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2047                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2048                 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2049                 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2050                 req.min_agg_len = rte_cpu_to_le_32(512);
2051         }
2052         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2053
2054         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2055
2056         HWRM_CHECK_RESULT();
2057         HWRM_UNLOCK();
2058
2059         return rc;
2060 }
2061
2062 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2063 {
2064         struct hwrm_func_cfg_input req = {0};
2065         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2066         int rc;
2067
2068         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2069         req.enables = rte_cpu_to_le_32(
2070                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2071         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2072         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2073
2074         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2075
2076         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2077         HWRM_CHECK_RESULT();
2078         HWRM_UNLOCK();
2079
2080         bp->pf.vf_info[vf].random_mac = false;
2081
2082         return rc;
2083 }
2084
2085 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2086                                   uint64_t *dropped)
2087 {
2088         int rc = 0;
2089         struct hwrm_func_qstats_input req = {.req_type = 0};
2090         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2091
2092         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2093
2094         req.fid = rte_cpu_to_le_16(fid);
2095
2096         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2097
2098         HWRM_CHECK_RESULT();
2099
2100         if (dropped)
2101                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2102
2103         HWRM_UNLOCK();
2104
2105         return rc;
2106 }
2107
2108 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2109                           struct rte_eth_stats *stats)
2110 {
2111         int rc = 0;
2112         struct hwrm_func_qstats_input req = {.req_type = 0};
2113         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2114
2115         HWRM_PREP(req, FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2116
2117         req.fid = rte_cpu_to_le_16(fid);
2118
2119         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2120
2121         HWRM_CHECK_RESULT();
2122
2123         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2124         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2125         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2126         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2127         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2128         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2129
2130         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2131         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2132         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2133         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2134         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2135         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2136
2137         stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2138         stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2139         stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2140
2141         HWRM_UNLOCK();
2142
2143         return rc;
2144 }
2145
2146 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2147 {
2148         int rc = 0;
2149         struct hwrm_func_clr_stats_input req = {.req_type = 0};
2150         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2151
2152         HWRM_PREP(req, FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2153
2154         req.fid = rte_cpu_to_le_16(fid);
2155
2156         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2157
2158         HWRM_CHECK_RESULT();
2159         HWRM_UNLOCK();
2160
2161         return rc;
2162 }
2163
2164 /*
2165  * HWRM utility functions
2166  */
2167
2168 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2169 {
2170         unsigned int i;
2171         int rc = 0;
2172
2173         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2174                 struct bnxt_tx_queue *txq;
2175                 struct bnxt_rx_queue *rxq;
2176                 struct bnxt_cp_ring_info *cpr;
2177
2178                 if (i >= bp->rx_cp_nr_rings) {
2179                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2180                         cpr = txq->cp_ring;
2181                 } else {
2182                         rxq = bp->rx_queues[i];
2183                         cpr = rxq->cp_ring;
2184                 }
2185
2186                 rc = bnxt_hwrm_stat_clear(bp, cpr);
2187                 if (rc)
2188                         return rc;
2189         }
2190         return 0;
2191 }
2192
2193 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2194 {
2195         int rc;
2196         unsigned int i;
2197         struct bnxt_cp_ring_info *cpr;
2198
2199         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2200
2201                 if (i >= bp->rx_cp_nr_rings) {
2202                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2203                 } else {
2204                         cpr = bp->rx_queues[i]->cp_ring;
2205                         if (BNXT_HAS_RING_GRPS(bp))
2206                                 bp->grp_info[i].fw_stats_ctx = -1;
2207                 }
2208                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2209                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2210                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2211                         if (rc)
2212                                 return rc;
2213                 }
2214         }
2215         return 0;
2216 }
2217
2218 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2219 {
2220         unsigned int i;
2221         int rc = 0;
2222
2223         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2224                 struct bnxt_tx_queue *txq;
2225                 struct bnxt_rx_queue *rxq;
2226                 struct bnxt_cp_ring_info *cpr;
2227
2228                 if (i >= bp->rx_cp_nr_rings) {
2229                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2230                         cpr = txq->cp_ring;
2231                 } else {
2232                         rxq = bp->rx_queues[i];
2233                         cpr = rxq->cp_ring;
2234                 }
2235
2236                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2237
2238                 if (rc)
2239                         return rc;
2240         }
2241         return rc;
2242 }
2243
2244 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2245 {
2246         uint16_t idx;
2247         uint32_t rc = 0;
2248
2249         if (!BNXT_HAS_RING_GRPS(bp))
2250                 return 0;
2251
2252         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2253
2254                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2255                         continue;
2256
2257                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2258
2259                 if (rc)
2260                         return rc;
2261         }
2262         return rc;
2263 }
2264
2265 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2266 {
2267         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2268
2269         bnxt_hwrm_ring_free(bp, cp_ring,
2270                             HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2271         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2272         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2273                                      sizeof(*cpr->cp_desc_ring));
2274         cpr->cp_raw_cons = 0;
2275         cpr->valid = 0;
2276 }
2277
2278 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2279 {
2280         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2281
2282         bnxt_hwrm_ring_free(bp, cp_ring,
2283                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2284         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2285         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2286                         sizeof(*cpr->cp_desc_ring));
2287         cpr->cp_raw_cons = 0;
2288         cpr->valid = 0;
2289 }
2290
2291 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2292 {
2293         struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2294         struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2295         struct bnxt_ring *ring = rxr->rx_ring_struct;
2296         struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2297
2298         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2299                 bnxt_hwrm_ring_free(bp, ring,
2300                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2301                 ring->fw_ring_id = INVALID_HW_RING_ID;
2302                 if (BNXT_HAS_RING_GRPS(bp))
2303                         bp->grp_info[queue_index].rx_fw_ring_id =
2304                                                         INVALID_HW_RING_ID;
2305                 memset(rxr->rx_desc_ring, 0,
2306                        rxr->rx_ring_struct->ring_size *
2307                        sizeof(*rxr->rx_desc_ring));
2308                 memset(rxr->rx_buf_ring, 0,
2309                        rxr->rx_ring_struct->ring_size *
2310                        sizeof(*rxr->rx_buf_ring));
2311                 rxr->rx_prod = 0;
2312         }
2313         ring = rxr->ag_ring_struct;
2314         if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2315                 bnxt_hwrm_ring_free(bp, ring,
2316                                     BNXT_CHIP_THOR(bp) ?
2317                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2318                                     HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2319                 ring->fw_ring_id = INVALID_HW_RING_ID;
2320                 memset(rxr->ag_buf_ring, 0,
2321                        rxr->ag_ring_struct->ring_size *
2322                        sizeof(*rxr->ag_buf_ring));
2323                 rxr->ag_prod = 0;
2324                 if (BNXT_HAS_RING_GRPS(bp))
2325                         bp->grp_info[queue_index].ag_fw_ring_id =
2326                                                         INVALID_HW_RING_ID;
2327         }
2328         if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2329                 bnxt_free_cp_ring(bp, cpr);
2330
2331         if (BNXT_HAS_RING_GRPS(bp))
2332                 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2333 }
2334
2335 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
2336 {
2337         unsigned int i;
2338
2339         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2340                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2341                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2342                 struct bnxt_ring *ring = txr->tx_ring_struct;
2343                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2344
2345                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2346                         bnxt_hwrm_ring_free(bp, ring,
2347                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2348                         ring->fw_ring_id = INVALID_HW_RING_ID;
2349                         memset(txr->tx_desc_ring, 0,
2350                                         txr->tx_ring_struct->ring_size *
2351                                         sizeof(*txr->tx_desc_ring));
2352                         memset(txr->tx_buf_ring, 0,
2353                                         txr->tx_ring_struct->ring_size *
2354                                         sizeof(*txr->tx_buf_ring));
2355                         txr->tx_prod = 0;
2356                         txr->tx_cons = 0;
2357                 }
2358                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2359                         bnxt_free_cp_ring(bp, cpr);
2360                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2361                 }
2362         }
2363
2364         for (i = 0; i < bp->rx_cp_nr_rings; i++)
2365                 bnxt_free_hwrm_rx_ring(bp, i);
2366
2367         return 0;
2368 }
2369
2370 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2371 {
2372         uint16_t i;
2373         uint32_t rc = 0;
2374
2375         if (!BNXT_HAS_RING_GRPS(bp))
2376                 return 0;
2377
2378         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2379                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2380                 if (rc)
2381                         return rc;
2382         }
2383         return rc;
2384 }
2385
2386 void bnxt_free_hwrm_resources(struct bnxt *bp)
2387 {
2388         /* Release memzone */
2389         rte_free(bp->hwrm_cmd_resp_addr);
2390         rte_free(bp->hwrm_short_cmd_req_addr);
2391         bp->hwrm_cmd_resp_addr = NULL;
2392         bp->hwrm_short_cmd_req_addr = NULL;
2393         bp->hwrm_cmd_resp_dma_addr = 0;
2394         bp->hwrm_short_cmd_req_dma_addr = 0;
2395 }
2396
2397 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2398 {
2399         struct rte_pci_device *pdev = bp->pdev;
2400         char type[RTE_MEMZONE_NAMESIZE];
2401
2402         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
2403                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2404         bp->max_resp_len = HWRM_MAX_RESP_LEN;
2405         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2406         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
2407         if (bp->hwrm_cmd_resp_addr == NULL)
2408                 return -ENOMEM;
2409         bp->hwrm_cmd_resp_dma_addr =
2410                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
2411         if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2412                 PMD_DRV_LOG(ERR,
2413                         "unable to map response address to physical memory\n");
2414                 return -ENOMEM;
2415         }
2416         rte_spinlock_init(&bp->hwrm_lock);
2417
2418         return 0;
2419 }
2420
2421 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2422 {
2423         struct bnxt_filter_info *filter;
2424         int rc = 0;
2425
2426         STAILQ_FOREACH(filter, &vnic->filter, next) {
2427                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2428                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2429                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2430                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2431                 else
2432                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2433                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2434                 bnxt_free_filter(bp, filter);
2435                 //if (rc)
2436                         //break;
2437         }
2438         return rc;
2439 }
2440
2441 static int
2442 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2443 {
2444         struct bnxt_filter_info *filter;
2445         struct rte_flow *flow;
2446         int rc = 0;
2447
2448         while (!STAILQ_EMPTY(&vnic->flow_list)) {
2449                 flow = STAILQ_FIRST(&vnic->flow_list);
2450                 filter = flow->filter;
2451                 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2452                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2453                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
2454                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2455                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2456                 else
2457                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2458
2459                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2460                 rte_free(flow);
2461                 //if (rc)
2462                         //break;
2463         }
2464         return rc;
2465 }
2466
2467 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2468 {
2469         struct bnxt_filter_info *filter;
2470         int rc = 0;
2471
2472         STAILQ_FOREACH(filter, &vnic->filter, next) {
2473                 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2474                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2475                                                      filter);
2476                 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2477                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2478                                                          filter);
2479                 } else {
2480                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2481                                                      filter);
2482                         if (!rc)
2483                                 filter->dflt = 1;
2484                 }
2485                 if (rc)
2486                         break;
2487         }
2488         return rc;
2489 }
2490
2491 void bnxt_free_tunnel_ports(struct bnxt *bp)
2492 {
2493         if (bp->vxlan_port_cnt)
2494                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2495                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2496         bp->vxlan_port = 0;
2497         if (bp->geneve_port_cnt)
2498                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2499                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2500         bp->geneve_port = 0;
2501 }
2502
2503 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2504 {
2505         int i;
2506
2507         if (bp->vnic_info == NULL)
2508                 return;
2509
2510         /*
2511          * Cleanup VNICs in reverse order, to make sure the L2 filter
2512          * from vnic0 is last to be cleaned up.
2513          */
2514         for (i = bp->max_vnics - 1; i >= 0; i--) {
2515                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2516
2517                 // If the VNIC ID is invalid we are not currently using the VNIC
2518                 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2519                         continue;
2520
2521                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2522
2523                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2524
2525                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2526
2527                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2528
2529                 bnxt_hwrm_vnic_free(bp, vnic);
2530
2531                 rte_free(vnic->fw_grp_ids);
2532         }
2533         /* Ring resources */
2534         bnxt_free_all_hwrm_rings(bp);
2535         bnxt_free_all_hwrm_ring_grps(bp);
2536         bnxt_free_all_hwrm_stat_ctxs(bp);
2537         bnxt_free_tunnel_ports(bp);
2538 }
2539
2540 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2541 {
2542         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2543
2544         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2545                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2546
2547         switch (conf_link_speed) {
2548         case ETH_LINK_SPEED_10M_HD:
2549         case ETH_LINK_SPEED_100M_HD:
2550                 /* FALLTHROUGH */
2551                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2552         }
2553         return hw_link_duplex;
2554 }
2555
2556 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2557 {
2558         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2559 }
2560
2561 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2562 {
2563         uint16_t eth_link_speed = 0;
2564
2565         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2566                 return ETH_LINK_SPEED_AUTONEG;
2567
2568         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2569         case ETH_LINK_SPEED_100M:
2570         case ETH_LINK_SPEED_100M_HD:
2571                 /* FALLTHROUGH */
2572                 eth_link_speed =
2573                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2574                 break;
2575         case ETH_LINK_SPEED_1G:
2576                 eth_link_speed =
2577                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2578                 break;
2579         case ETH_LINK_SPEED_2_5G:
2580                 eth_link_speed =
2581                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2582                 break;
2583         case ETH_LINK_SPEED_10G:
2584                 eth_link_speed =
2585                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2586                 break;
2587         case ETH_LINK_SPEED_20G:
2588                 eth_link_speed =
2589                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2590                 break;
2591         case ETH_LINK_SPEED_25G:
2592                 eth_link_speed =
2593                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2594                 break;
2595         case ETH_LINK_SPEED_40G:
2596                 eth_link_speed =
2597                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2598                 break;
2599         case ETH_LINK_SPEED_50G:
2600                 eth_link_speed =
2601                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2602                 break;
2603         case ETH_LINK_SPEED_100G:
2604                 eth_link_speed =
2605                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2606                 break;
2607         default:
2608                 PMD_DRV_LOG(ERR,
2609                         "Unsupported link speed %d; default to AUTO\n",
2610                         conf_link_speed);
2611                 break;
2612         }
2613         return eth_link_speed;
2614 }
2615
2616 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2617                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2618                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2619                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2620
2621 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2622 {
2623         uint32_t one_speed;
2624
2625         if (link_speed == ETH_LINK_SPEED_AUTONEG)
2626                 return 0;
2627
2628         if (link_speed & ETH_LINK_SPEED_FIXED) {
2629                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2630
2631                 if (one_speed & (one_speed - 1)) {
2632                         PMD_DRV_LOG(ERR,
2633                                 "Invalid advertised speeds (%u) for port %u\n",
2634                                 link_speed, port_id);
2635                         return -EINVAL;
2636                 }
2637                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2638                         PMD_DRV_LOG(ERR,
2639                                 "Unsupported advertised speed (%u) for port %u\n",
2640                                 link_speed, port_id);
2641                         return -EINVAL;
2642                 }
2643         } else {
2644                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2645                         PMD_DRV_LOG(ERR,
2646                                 "Unsupported advertised speeds (%u) for port %u\n",
2647                                 link_speed, port_id);
2648                         return -EINVAL;
2649                 }
2650         }
2651         return 0;
2652 }
2653
2654 static uint16_t
2655 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2656 {
2657         uint16_t ret = 0;
2658
2659         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2660                 if (bp->link_info.support_speeds)
2661                         return bp->link_info.support_speeds;
2662                 link_speed = BNXT_SUPPORTED_SPEEDS;
2663         }
2664
2665         if (link_speed & ETH_LINK_SPEED_100M)
2666                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2667         if (link_speed & ETH_LINK_SPEED_100M_HD)
2668                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2669         if (link_speed & ETH_LINK_SPEED_1G)
2670                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2671         if (link_speed & ETH_LINK_SPEED_2_5G)
2672                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2673         if (link_speed & ETH_LINK_SPEED_10G)
2674                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2675         if (link_speed & ETH_LINK_SPEED_20G)
2676                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2677         if (link_speed & ETH_LINK_SPEED_25G)
2678                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2679         if (link_speed & ETH_LINK_SPEED_40G)
2680                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2681         if (link_speed & ETH_LINK_SPEED_50G)
2682                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2683         if (link_speed & ETH_LINK_SPEED_100G)
2684                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2685         return ret;
2686 }
2687
2688 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2689 {
2690         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2691
2692         switch (hw_link_speed) {
2693         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2694                 eth_link_speed = ETH_SPEED_NUM_100M;
2695                 break;
2696         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2697                 eth_link_speed = ETH_SPEED_NUM_1G;
2698                 break;
2699         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2700                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2701                 break;
2702         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2703                 eth_link_speed = ETH_SPEED_NUM_10G;
2704                 break;
2705         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2706                 eth_link_speed = ETH_SPEED_NUM_20G;
2707                 break;
2708         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2709                 eth_link_speed = ETH_SPEED_NUM_25G;
2710                 break;
2711         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2712                 eth_link_speed = ETH_SPEED_NUM_40G;
2713                 break;
2714         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2715                 eth_link_speed = ETH_SPEED_NUM_50G;
2716                 break;
2717         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2718                 eth_link_speed = ETH_SPEED_NUM_100G;
2719                 break;
2720         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2721         default:
2722                 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2723                         hw_link_speed);
2724                 break;
2725         }
2726         return eth_link_speed;
2727 }
2728
2729 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2730 {
2731         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2732
2733         switch (hw_link_duplex) {
2734         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2735         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2736                 /* FALLTHROUGH */
2737                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2738                 break;
2739         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2740                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2741                 break;
2742         default:
2743                 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2744                         hw_link_duplex);
2745                 break;
2746         }
2747         return eth_link_duplex;
2748 }
2749
2750 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2751 {
2752         int rc = 0;
2753         struct bnxt_link_info *link_info = &bp->link_info;
2754
2755         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2756         if (rc) {
2757                 PMD_DRV_LOG(ERR,
2758                         "Get link config failed with rc %d\n", rc);
2759                 goto exit;
2760         }
2761         if (link_info->link_speed)
2762                 link->link_speed =
2763                         bnxt_parse_hw_link_speed(link_info->link_speed);
2764         else
2765                 link->link_speed = ETH_SPEED_NUM_NONE;
2766         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2767         link->link_status = link_info->link_up;
2768         link->link_autoneg = link_info->auto_mode ==
2769                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2770                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2771 exit:
2772         return rc;
2773 }
2774
2775 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2776 {
2777         int rc = 0;
2778         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2779         struct bnxt_link_info link_req;
2780         uint16_t speed, autoneg;
2781
2782         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2783                 return 0;
2784
2785         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2786                         bp->eth_dev->data->port_id);
2787         if (rc)
2788                 goto error;
2789
2790         memset(&link_req, 0, sizeof(link_req));
2791         link_req.link_up = link_up;
2792         if (!link_up)
2793                 goto port_phy_cfg;
2794
2795         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2796         if (BNXT_CHIP_THOR(bp) &&
2797             dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2798                 /* 40G is not supported as part of media auto detect.
2799                  * The speed should be forced and autoneg disabled
2800                  * to configure 40G speed.
2801                  */
2802                 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2803                 autoneg = 0;
2804         }
2805
2806         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2807         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2808         /* Autoneg can be done only when the FW allows.
2809          * When user configures fixed speed of 40G and later changes to
2810          * any other speed, auto_link_speed/force_link_speed is still set
2811          * to 40G until link comes up at new speed.
2812          */
2813         if (autoneg == 1 &&
2814             !(!BNXT_CHIP_THOR(bp) &&
2815               (bp->link_info.auto_link_speed ||
2816                bp->link_info.force_link_speed))) {
2817                 link_req.phy_flags |=
2818                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2819                 link_req.auto_link_speed_mask =
2820                         bnxt_parse_eth_link_speed_mask(bp,
2821                                                        dev_conf->link_speeds);
2822         } else {
2823                 if (bp->link_info.phy_type ==
2824                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2825                     bp->link_info.phy_type ==
2826                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2827                     bp->link_info.media_type ==
2828                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2829                         PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2830                         return -EINVAL;
2831                 }
2832
2833                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2834                 /* If user wants a particular speed try that first. */
2835                 if (speed)
2836                         link_req.link_speed = speed;
2837                 else if (bp->link_info.force_link_speed)
2838                         link_req.link_speed = bp->link_info.force_link_speed;
2839                 else
2840                         link_req.link_speed = bp->link_info.auto_link_speed;
2841         }
2842         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2843         link_req.auto_pause = bp->link_info.auto_pause;
2844         link_req.force_pause = bp->link_info.force_pause;
2845
2846 port_phy_cfg:
2847         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2848         if (rc) {
2849                 PMD_DRV_LOG(ERR,
2850                         "Set link config failed with rc %d\n", rc);
2851         }
2852
2853 error:
2854         return rc;
2855 }
2856
2857 /* JIRA 22088 */
2858 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
2859 {
2860         struct hwrm_func_qcfg_input req = {0};
2861         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2862         uint16_t flags;
2863         int rc = 0;
2864
2865         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
2866         req.fid = rte_cpu_to_le_16(0xffff);
2867
2868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2869
2870         HWRM_CHECK_RESULT();
2871
2872         /* Hard Coded.. 0xfff VLAN ID mask */
2873         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2874         flags = rte_le_to_cpu_16(resp->flags);
2875         if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2876                 bp->flags |= BNXT_FLAG_MULTI_HOST;
2877
2878         if (BNXT_VF(bp) &&
2879             !BNXT_VF_IS_TRUSTED(bp) &&
2880             (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2881                 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
2882                 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
2883         } else if (BNXT_VF(bp) &&
2884                    BNXT_VF_IS_TRUSTED(bp) &&
2885                    !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
2886                 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
2887                 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
2888         }
2889
2890         if (mtu)
2891                 *mtu = resp->mtu;
2892
2893         switch (resp->port_partition_type) {
2894         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2895         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2896         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2897                 /* FALLTHROUGH */
2898                 bp->port_partition_type = resp->port_partition_type;
2899                 break;
2900         default:
2901                 bp->port_partition_type = 0;
2902                 break;
2903         }
2904
2905         HWRM_UNLOCK();
2906
2907         return rc;
2908 }
2909
2910 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2911                                    struct hwrm_func_qcaps_output *qcaps)
2912 {
2913         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2914         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2915                sizeof(qcaps->mac_address));
2916         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2917         qcaps->max_rx_rings = fcfg->num_rx_rings;
2918         qcaps->max_tx_rings = fcfg->num_tx_rings;
2919         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2920         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2921         qcaps->max_vfs = 0;
2922         qcaps->first_vf_id = 0;
2923         qcaps->max_vnics = fcfg->num_vnics;
2924         qcaps->max_decap_records = 0;
2925         qcaps->max_encap_records = 0;
2926         qcaps->max_tx_wm_flows = 0;
2927         qcaps->max_tx_em_flows = 0;
2928         qcaps->max_rx_wm_flows = 0;
2929         qcaps->max_rx_em_flows = 0;
2930         qcaps->max_flow_id = 0;
2931         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2932         qcaps->max_sp_tx_rings = 0;
2933         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2934 }
2935
2936 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2937 {
2938         struct hwrm_func_cfg_input req = {0};
2939         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2940         uint32_t enables;
2941         int rc;
2942
2943         enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2944                   HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2945                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2946                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2947                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2948                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2949                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2950                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2951                   HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
2952
2953         if (BNXT_HAS_RING_GRPS(bp)) {
2954                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
2955                 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2956         } else if (BNXT_HAS_NQ(bp)) {
2957                 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
2958                 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
2959         }
2960
2961         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2962         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2963         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2964                                    RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
2965                                    BNXT_NUM_VLANS);
2966         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2967         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2968         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2969         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2970         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2971         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2972         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2973         req.fid = rte_cpu_to_le_16(0xffff);
2974         req.enables = rte_cpu_to_le_32(enables);
2975
2976         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
2977
2978         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2979
2980         HWRM_CHECK_RESULT();
2981         HWRM_UNLOCK();
2982
2983         return rc;
2984 }
2985
2986 static void populate_vf_func_cfg_req(struct bnxt *bp,
2987                                      struct hwrm_func_cfg_input *req,
2988                                      int num_vfs)
2989 {
2990         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2991                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2992                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2993                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2994                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2995                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2996                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2997                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2998                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2999                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3000
3001         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3002                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3003                                     BNXT_NUM_VLANS);
3004         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3005                                     RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3006                                     BNXT_NUM_VLANS);
3007         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3008                                                 (num_vfs + 1));
3009         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3010         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3011                                                (num_vfs + 1));
3012         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3013         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3014         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3015         /* TODO: For now, do not support VMDq/RFS on VFs. */
3016         req->num_vnics = rte_cpu_to_le_16(1);
3017         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3018                                                  (num_vfs + 1));
3019 }
3020
3021 static void add_random_mac_if_needed(struct bnxt *bp,
3022                                      struct hwrm_func_cfg_input *cfg_req,
3023                                      int vf)
3024 {
3025         struct rte_ether_addr mac;
3026
3027         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3028                 return;
3029
3030         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3031                 cfg_req->enables |=
3032                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3033                 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3034                 bp->pf.vf_info[vf].random_mac = true;
3035         } else {
3036                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3037                         RTE_ETHER_ADDR_LEN);
3038         }
3039 }
3040
3041 static void reserve_resources_from_vf(struct bnxt *bp,
3042                                       struct hwrm_func_cfg_input *cfg_req,
3043                                       int vf)
3044 {
3045         struct hwrm_func_qcaps_input req = {0};
3046         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3047         int rc;
3048
3049         /* Get the actual allocated values now */
3050         HWRM_PREP(req, FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3051         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3052         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3053
3054         if (rc) {
3055                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3056                 copy_func_cfg_to_qcaps(cfg_req, resp);
3057         } else if (resp->error_code) {
3058                 rc = rte_le_to_cpu_16(resp->error_code);
3059                 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3060                 copy_func_cfg_to_qcaps(cfg_req, resp);
3061         }
3062
3063         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3064         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3065         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3066         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3067         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3068         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3069         /*
3070          * TODO: While not supporting VMDq with VFs, max_vnics is always
3071          * forced to 1 in this case
3072          */
3073         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3074         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3075
3076         HWRM_UNLOCK();
3077 }
3078
3079 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3080 {
3081         struct hwrm_func_qcfg_input req = {0};
3082         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3083         int rc;
3084
3085         /* Check for zero MAC address */
3086         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3087         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3089         HWRM_CHECK_RESULT();
3090         rc = rte_le_to_cpu_16(resp->vlan);
3091
3092         HWRM_UNLOCK();
3093
3094         return rc;
3095 }
3096
3097 static int update_pf_resource_max(struct bnxt *bp)
3098 {
3099         struct hwrm_func_qcfg_input req = {0};
3100         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3101         int rc;
3102
3103         /* And copy the allocated numbers into the pf struct */
3104         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3105         req.fid = rte_cpu_to_le_16(0xffff);
3106         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3107         HWRM_CHECK_RESULT();
3108
3109         /* Only TX ring value reflects actual allocation? TODO */
3110         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3111         bp->pf.evb_mode = resp->evb_mode;
3112
3113         HWRM_UNLOCK();
3114
3115         return rc;
3116 }
3117
3118 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3119 {
3120         int rc;
3121
3122         if (!BNXT_PF(bp)) {
3123                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3124                 return -EINVAL;
3125         }
3126
3127         rc = bnxt_hwrm_func_qcaps(bp);
3128         if (rc)
3129                 return rc;
3130
3131         bp->pf.func_cfg_flags &=
3132                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3133                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3134         bp->pf.func_cfg_flags |=
3135                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3136         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3137         rc = __bnxt_hwrm_func_qcaps(bp);
3138         return rc;
3139 }
3140
3141 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3142 {
3143         struct hwrm_func_cfg_input req = {0};
3144         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3145         int i;
3146         size_t sz;
3147         int rc = 0;
3148         size_t req_buf_sz;
3149
3150         if (!BNXT_PF(bp)) {
3151                 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3152                 return -EINVAL;
3153         }
3154
3155         rc = bnxt_hwrm_func_qcaps(bp);
3156
3157         if (rc)
3158                 return rc;
3159
3160         bp->pf.active_vfs = num_vfs;
3161
3162         /*
3163          * First, configure the PF to only use one TX ring.  This ensures that
3164          * there are enough rings for all VFs.
3165          *
3166          * If we don't do this, when we call func_alloc() later, we will lock
3167          * extra rings to the PF that won't be available during func_cfg() of
3168          * the VFs.
3169          *
3170          * This has been fixed with firmware versions above 20.6.54
3171          */
3172         bp->pf.func_cfg_flags &=
3173                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3174                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3175         bp->pf.func_cfg_flags |=
3176                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3177         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3178         if (rc)
3179                 return rc;
3180
3181         /*
3182          * Now, create and register a buffer to hold forwarded VF requests
3183          */
3184         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3185         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3186                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3187         if (bp->pf.vf_req_buf == NULL) {
3188                 rc = -ENOMEM;
3189                 goto error_free;
3190         }
3191         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3192                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
3193         for (i = 0; i < num_vfs; i++)
3194                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
3195                                         (i * HWRM_MAX_REQ_LEN);
3196
3197         rc = bnxt_hwrm_func_buf_rgtr(bp);
3198         if (rc)
3199                 goto error_free;
3200
3201         populate_vf_func_cfg_req(bp, &req, num_vfs);
3202
3203         bp->pf.active_vfs = 0;
3204         for (i = 0; i < num_vfs; i++) {
3205                 add_random_mac_if_needed(bp, &req, i);
3206
3207                 HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3208                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
3209                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
3210                 rc = bnxt_hwrm_send_message(bp,
3211                                             &req,
3212                                             sizeof(req),
3213                                             BNXT_USE_CHIMP_MB);
3214
3215                 /* Clear enable flag for next pass */
3216                 req.enables &= ~rte_cpu_to_le_32(
3217                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3218
3219                 if (rc || resp->error_code) {
3220                         PMD_DRV_LOG(ERR,
3221                                 "Failed to initizlie VF %d\n", i);
3222                         PMD_DRV_LOG(ERR,
3223                                 "Not all VFs available. (%d, %d)\n",
3224                                 rc, resp->error_code);
3225                         HWRM_UNLOCK();
3226                         break;
3227                 }
3228
3229                 HWRM_UNLOCK();
3230
3231                 reserve_resources_from_vf(bp, &req, i);
3232                 bp->pf.active_vfs++;
3233                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
3234         }
3235
3236         /*
3237          * Now configure the PF to use "the rest" of the resources
3238          * We're using STD_TX_RING_MODE here though which will limit the TX
3239          * rings.  This will allow QoS to function properly.  Not setting this
3240          * will cause PF rings to break bandwidth settings.
3241          */
3242         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3243         if (rc)
3244                 goto error_free;
3245
3246         rc = update_pf_resource_max(bp);
3247         if (rc)
3248                 goto error_free;
3249
3250         return rc;
3251
3252 error_free:
3253         bnxt_hwrm_func_buf_unrgtr(bp);
3254         return rc;
3255 }
3256
3257 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3258 {
3259         struct hwrm_func_cfg_input req = {0};
3260         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3261         int rc;
3262
3263         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3264
3265         req.fid = rte_cpu_to_le_16(0xffff);
3266         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3267         req.evb_mode = bp->pf.evb_mode;
3268
3269         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3270         HWRM_CHECK_RESULT();
3271         HWRM_UNLOCK();
3272
3273         return rc;
3274 }
3275
3276 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3277                                 uint8_t tunnel_type)
3278 {
3279         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3280         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3281         int rc = 0;
3282
3283         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3284         req.tunnel_type = tunnel_type;
3285         req.tunnel_dst_port_val = port;
3286         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3287         HWRM_CHECK_RESULT();
3288
3289         switch (tunnel_type) {
3290         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3291                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3292                 bp->vxlan_port = port;
3293                 break;
3294         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3295                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3296                 bp->geneve_port = port;
3297                 break;
3298         default:
3299                 break;
3300         }
3301
3302         HWRM_UNLOCK();
3303
3304         return rc;
3305 }
3306
3307 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3308                                 uint8_t tunnel_type)
3309 {
3310         struct hwrm_tunnel_dst_port_free_input req = {0};
3311         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3312         int rc = 0;
3313
3314         HWRM_PREP(req, TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3315
3316         req.tunnel_type = tunnel_type;
3317         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3318         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3319
3320         HWRM_CHECK_RESULT();
3321         HWRM_UNLOCK();
3322
3323         return rc;
3324 }
3325
3326 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3327                                         uint32_t flags)
3328 {
3329         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3330         struct hwrm_func_cfg_input req = {0};
3331         int rc;
3332
3333         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3334
3335         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3336         req.flags = rte_cpu_to_le_32(flags);
3337         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3338
3339         HWRM_CHECK_RESULT();
3340         HWRM_UNLOCK();
3341
3342         return rc;
3343 }
3344
3345 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3346 {
3347         uint32_t *flag = flagp;
3348
3349         vnic->flags = *flag;
3350 }
3351
3352 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3353 {
3354         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3355 }
3356
3357 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3358 {
3359         int rc = 0;
3360         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3361         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3362
3363         HWRM_PREP(req, FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3364
3365         req.req_buf_num_pages = rte_cpu_to_le_16(1);
3366         req.req_buf_page_size = rte_cpu_to_le_16(
3367                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
3368         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3369         req.req_buf_page_addr0 =
3370                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
3371         if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3372                 PMD_DRV_LOG(ERR,
3373                         "unable to map buffer address to physical memory\n");
3374                 return -ENOMEM;
3375         }
3376
3377         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3378
3379         HWRM_CHECK_RESULT();
3380         HWRM_UNLOCK();
3381
3382         return rc;
3383 }
3384
3385 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3386 {
3387         int rc = 0;
3388         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3389         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3390
3391         if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3392                 return 0;
3393
3394         HWRM_PREP(req, FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3395
3396         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3397
3398         HWRM_CHECK_RESULT();
3399         HWRM_UNLOCK();
3400
3401         return rc;
3402 }
3403
3404 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3405 {
3406         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3407         struct hwrm_func_cfg_input req = {0};
3408         int rc;
3409
3410         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3411
3412         req.fid = rte_cpu_to_le_16(0xffff);
3413         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
3414         req.enables = rte_cpu_to_le_32(
3415                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3416         req.async_event_cr = rte_cpu_to_le_16(
3417                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3419
3420         HWRM_CHECK_RESULT();
3421         HWRM_UNLOCK();
3422
3423         return rc;
3424 }
3425
3426 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3427 {
3428         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3429         struct hwrm_func_vf_cfg_input req = {0};
3430         int rc;
3431
3432         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3433
3434         req.enables = rte_cpu_to_le_32(
3435                         HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3436         req.async_event_cr = rte_cpu_to_le_16(
3437                         bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3438         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3439
3440         HWRM_CHECK_RESULT();
3441         HWRM_UNLOCK();
3442
3443         return rc;
3444 }
3445
3446 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3447 {
3448         struct hwrm_func_cfg_input req = {0};
3449         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3450         uint16_t dflt_vlan, fid;
3451         uint32_t func_cfg_flags;
3452         int rc = 0;
3453
3454         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3455
3456         if (is_vf) {
3457                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
3458                 fid = bp->pf.vf_info[vf].fid;
3459                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
3460         } else {
3461                 fid = rte_cpu_to_le_16(0xffff);
3462                 func_cfg_flags = bp->pf.func_cfg_flags;
3463                 dflt_vlan = bp->vlan;
3464         }
3465
3466         req.flags = rte_cpu_to_le_32(func_cfg_flags);
3467         req.fid = rte_cpu_to_le_16(fid);
3468         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3469         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3470
3471         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3472
3473         HWRM_CHECK_RESULT();
3474         HWRM_UNLOCK();
3475
3476         return rc;
3477 }
3478
3479 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3480                         uint16_t max_bw, uint16_t enables)
3481 {
3482         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3483         struct hwrm_func_cfg_input req = {0};
3484         int rc;
3485
3486         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3487
3488         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3489         req.enables |= rte_cpu_to_le_32(enables);
3490         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3491         req.max_bw = rte_cpu_to_le_32(max_bw);
3492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3493
3494         HWRM_CHECK_RESULT();
3495         HWRM_UNLOCK();
3496
3497         return rc;
3498 }
3499
3500 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3501 {
3502         struct hwrm_func_cfg_input req = {0};
3503         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3504         int rc = 0;
3505
3506         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
3507
3508         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
3509         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3510         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3511         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
3512
3513         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3514
3515         HWRM_CHECK_RESULT();
3516         HWRM_UNLOCK();
3517
3518         return rc;
3519 }
3520
3521 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3522 {
3523         int rc;
3524
3525         if (BNXT_PF(bp))
3526                 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3527         else
3528                 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3529
3530         return rc;
3531 }
3532
3533 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3534                               void *encaped, size_t ec_size)
3535 {
3536         int rc = 0;
3537         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3538         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3539
3540         if (ec_size > sizeof(req.encap_request))
3541                 return -1;
3542
3543         HWRM_PREP(req, REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3544
3545         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3546         memcpy(req.encap_request, encaped, ec_size);
3547
3548         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3549
3550         HWRM_CHECK_RESULT();
3551         HWRM_UNLOCK();
3552
3553         return rc;
3554 }
3555
3556 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3557                                        struct rte_ether_addr *mac)
3558 {
3559         struct hwrm_func_qcfg_input req = {0};
3560         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3561         int rc;
3562
3563         HWRM_PREP(req, FUNC_QCFG, BNXT_USE_CHIMP_MB);
3564
3565         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3567
3568         HWRM_CHECK_RESULT();
3569
3570         memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3571
3572         HWRM_UNLOCK();
3573
3574         return rc;
3575 }
3576
3577 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3578                             void *encaped, size_t ec_size)
3579 {
3580         int rc = 0;
3581         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3582         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3583
3584         if (ec_size > sizeof(req.encap_request))
3585                 return -1;
3586
3587         HWRM_PREP(req, EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3588
3589         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3590         memcpy(req.encap_request, encaped, ec_size);
3591
3592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3593
3594         HWRM_CHECK_RESULT();
3595         HWRM_UNLOCK();
3596
3597         return rc;
3598 }
3599
3600 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3601                          struct rte_eth_stats *stats, uint8_t rx)
3602 {
3603         int rc = 0;
3604         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3605         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3606
3607         HWRM_PREP(req, STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3608
3609         req.stat_ctx_id = rte_cpu_to_le_32(cid);
3610
3611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3612
3613         HWRM_CHECK_RESULT();
3614
3615         if (rx) {
3616                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3617                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3618                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3619                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3620                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3621                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3622                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3623                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3624         } else {
3625                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3626                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3627                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3628                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3629                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3630                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3631         }
3632
3633         HWRM_UNLOCK();
3634
3635         return rc;
3636 }
3637
3638 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3639 {
3640         struct hwrm_port_qstats_input req = {0};
3641         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3642         struct bnxt_pf_info *pf = &bp->pf;
3643         int rc;
3644
3645         HWRM_PREP(req, PORT_QSTATS, BNXT_USE_CHIMP_MB);
3646
3647         req.port_id = rte_cpu_to_le_16(pf->port_id);
3648         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3649         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3650         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3651
3652         HWRM_CHECK_RESULT();
3653         HWRM_UNLOCK();
3654
3655         return rc;
3656 }
3657
3658 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3659 {
3660         struct hwrm_port_clr_stats_input req = {0};
3661         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3662         struct bnxt_pf_info *pf = &bp->pf;
3663         int rc;
3664
3665         /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3666         if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3667             BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3668                 return 0;
3669
3670         HWRM_PREP(req, PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3671
3672         req.port_id = rte_cpu_to_le_16(pf->port_id);
3673         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3674
3675         HWRM_CHECK_RESULT();
3676         HWRM_UNLOCK();
3677
3678         return rc;
3679 }
3680
3681 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3682 {
3683         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3684         struct hwrm_port_led_qcaps_input req = {0};
3685         int rc;
3686
3687         if (BNXT_VF(bp))
3688                 return 0;
3689
3690         HWRM_PREP(req, PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3691         req.port_id = bp->pf.port_id;
3692         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3693
3694         HWRM_CHECK_RESULT();
3695
3696         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3697                 unsigned int i;
3698
3699                 bp->num_leds = resp->num_leds;
3700                 memcpy(bp->leds, &resp->led0_id,
3701                         sizeof(bp->leds[0]) * bp->num_leds);
3702                 for (i = 0; i < bp->num_leds; i++) {
3703                         struct bnxt_led_info *led = &bp->leds[i];
3704
3705                         uint16_t caps = led->led_state_caps;
3706
3707                         if (!led->led_group_id ||
3708                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3709                                 bp->num_leds = 0;
3710                                 break;
3711                         }
3712                 }
3713         }
3714
3715         HWRM_UNLOCK();
3716
3717         return rc;
3718 }
3719
3720 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3721 {
3722         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3723         struct hwrm_port_led_cfg_input req = {0};
3724         struct bnxt_led_cfg *led_cfg;
3725         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3726         uint16_t duration = 0;
3727         int rc, i;
3728
3729         if (!bp->num_leds || BNXT_VF(bp))
3730                 return -EOPNOTSUPP;
3731
3732         HWRM_PREP(req, PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3733
3734         if (led_on) {
3735                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3736                 duration = rte_cpu_to_le_16(500);
3737         }
3738         req.port_id = bp->pf.port_id;
3739         req.num_leds = bp->num_leds;
3740         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3741         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3742                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3743                 led_cfg->led_id = bp->leds[i].led_id;
3744                 led_cfg->led_state = led_state;
3745                 led_cfg->led_blink_on = duration;
3746                 led_cfg->led_blink_off = duration;
3747                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3748         }
3749
3750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3751
3752         HWRM_CHECK_RESULT();
3753         HWRM_UNLOCK();
3754
3755         return rc;
3756 }
3757
3758 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3759                                uint32_t *length)
3760 {
3761         int rc;
3762         struct hwrm_nvm_get_dir_info_input req = {0};
3763         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3764
3765         HWRM_PREP(req, NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3766
3767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3768
3769         HWRM_CHECK_RESULT();
3770
3771         *entries = rte_le_to_cpu_32(resp->entries);
3772         *length = rte_le_to_cpu_32(resp->entry_length);
3773
3774         HWRM_UNLOCK();
3775         return rc;
3776 }
3777
3778 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3779 {
3780         int rc;
3781         uint32_t dir_entries;
3782         uint32_t entry_length;
3783         uint8_t *buf;
3784         size_t buflen;
3785         rte_iova_t dma_handle;
3786         struct hwrm_nvm_get_dir_entries_input req = {0};
3787         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3788
3789         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3790         if (rc != 0)
3791                 return rc;
3792
3793         *data++ = dir_entries;
3794         *data++ = entry_length;
3795         len -= 2;
3796         memset(data, 0xff, len);
3797
3798         buflen = dir_entries * entry_length;
3799         buf = rte_malloc("nvm_dir", buflen, 0);
3800         rte_mem_lock_page(buf);
3801         if (buf == NULL)
3802                 return -ENOMEM;
3803         dma_handle = rte_mem_virt2iova(buf);
3804         if (dma_handle == RTE_BAD_IOVA) {
3805                 PMD_DRV_LOG(ERR,
3806                         "unable to map response address to physical memory\n");
3807                 return -ENOMEM;
3808         }
3809         HWRM_PREP(req, NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
3810         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3811         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3812
3813         if (rc == 0)
3814                 memcpy(data, buf, len > buflen ? buflen : len);
3815
3816         rte_free(buf);
3817         HWRM_CHECK_RESULT();
3818         HWRM_UNLOCK();
3819
3820         return rc;
3821 }
3822
3823 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3824                              uint32_t offset, uint32_t length,
3825                              uint8_t *data)
3826 {
3827         int rc;
3828         uint8_t *buf;
3829         rte_iova_t dma_handle;
3830         struct hwrm_nvm_read_input req = {0};
3831         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3832
3833         buf = rte_malloc("nvm_item", length, 0);
3834         rte_mem_lock_page(buf);
3835         if (!buf)
3836                 return -ENOMEM;
3837
3838         dma_handle = rte_mem_virt2iova(buf);
3839         if (dma_handle == RTE_BAD_IOVA) {
3840                 PMD_DRV_LOG(ERR,
3841                         "unable to map response address to physical memory\n");
3842                 return -ENOMEM;
3843         }
3844         HWRM_PREP(req, NVM_READ, BNXT_USE_CHIMP_MB);
3845         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3846         req.dir_idx = rte_cpu_to_le_16(index);
3847         req.offset = rte_cpu_to_le_32(offset);
3848         req.len = rte_cpu_to_le_32(length);
3849         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3850         if (rc == 0)
3851                 memcpy(data, buf, length);
3852
3853         rte_free(buf);
3854         HWRM_CHECK_RESULT();
3855         HWRM_UNLOCK();
3856
3857         return rc;
3858 }
3859
3860 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3861 {
3862         int rc;
3863         struct hwrm_nvm_erase_dir_entry_input req = {0};
3864         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3865
3866         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
3867         req.dir_idx = rte_cpu_to_le_16(index);
3868         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3869         HWRM_CHECK_RESULT();
3870         HWRM_UNLOCK();
3871
3872         return rc;
3873 }
3874
3875
3876 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3877                           uint16_t dir_ordinal, uint16_t dir_ext,
3878                           uint16_t dir_attr, const uint8_t *data,
3879                           size_t data_len)
3880 {
3881         int rc;
3882         struct hwrm_nvm_write_input req = {0};
3883         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3884         rte_iova_t dma_handle;
3885         uint8_t *buf;
3886
3887         buf = rte_malloc("nvm_write", data_len, 0);
3888         rte_mem_lock_page(buf);
3889         if (!buf)
3890                 return -ENOMEM;
3891
3892         dma_handle = rte_mem_virt2iova(buf);
3893         if (dma_handle == RTE_BAD_IOVA) {
3894                 PMD_DRV_LOG(ERR,
3895                         "unable to map response address to physical memory\n");
3896                 return -ENOMEM;
3897         }
3898         memcpy(buf, data, data_len);
3899
3900         HWRM_PREP(req, NVM_WRITE, BNXT_USE_CHIMP_MB);
3901
3902         req.dir_type = rte_cpu_to_le_16(dir_type);
3903         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3904         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3905         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3906         req.dir_data_length = rte_cpu_to_le_32(data_len);
3907         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3908
3909         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3910
3911         rte_free(buf);
3912         HWRM_CHECK_RESULT();
3913         HWRM_UNLOCK();
3914
3915         return rc;
3916 }
3917
3918 static void
3919 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3920 {
3921         uint32_t *count = cbdata;
3922
3923         *count = *count + 1;
3924 }
3925
3926 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3927                                      struct bnxt_vnic_info *vnic __rte_unused)
3928 {
3929         return 0;
3930 }
3931
3932 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3933 {
3934         uint32_t count = 0;
3935
3936         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3937             &count, bnxt_vnic_count_hwrm_stub);
3938
3939         return count;
3940 }
3941
3942 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3943                                         uint16_t *vnic_ids)
3944 {
3945         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3946         struct hwrm_func_vf_vnic_ids_query_output *resp =
3947                                                 bp->hwrm_cmd_resp_addr;
3948         int rc;
3949
3950         /* First query all VNIC ids */
3951         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
3952
3953         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3954         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3955         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3956
3957         if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
3958                 HWRM_UNLOCK();
3959                 PMD_DRV_LOG(ERR,
3960                 "unable to map VNIC ID table address to physical memory\n");
3961                 return -ENOMEM;
3962         }
3963         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3964         HWRM_CHECK_RESULT();
3965         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3966
3967         HWRM_UNLOCK();
3968
3969         return rc;
3970 }
3971
3972 /*
3973  * This function queries the VNIC IDs  for a specified VF. It then calls
3974  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3975  * Then it calls the hwrm_cb function to program this new vnic configuration.
3976  */
3977 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3978         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3979         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3980 {
3981         struct bnxt_vnic_info vnic;
3982         int rc = 0;
3983         int i, num_vnic_ids;
3984         uint16_t *vnic_ids;
3985         size_t vnic_id_sz;
3986         size_t sz;
3987
3988         /* First query all VNIC ids */
3989         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3990         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3991                         RTE_CACHE_LINE_SIZE);
3992         if (vnic_ids == NULL)
3993                 return -ENOMEM;
3994
3995         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3996                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3997
3998         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3999
4000         if (num_vnic_ids < 0)
4001                 return num_vnic_ids;
4002
4003         /* Retrieve VNIC, update bd_stall then update */
4004
4005         for (i = 0; i < num_vnic_ids; i++) {
4006                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4007                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4008                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
4009                 if (rc)
4010                         break;
4011                 if (vnic.mru <= 4)      /* Indicates unallocated */
4012                         continue;
4013
4014                 vnic_cb(&vnic, cbdata);
4015
4016                 rc = hwrm_cb(bp, &vnic);
4017                 if (rc)
4018                         break;
4019         }
4020
4021         rte_free(vnic_ids);
4022
4023         return rc;
4024 }
4025
4026 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4027                                               bool on)
4028 {
4029         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4030         struct hwrm_func_cfg_input req = {0};
4031         int rc;
4032
4033         HWRM_PREP(req, FUNC_CFG, BNXT_USE_CHIMP_MB);
4034
4035         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
4036         req.enables |= rte_cpu_to_le_32(
4037                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4038         req.vlan_antispoof_mode = on ?
4039                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4040                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4041         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4042
4043         HWRM_CHECK_RESULT();
4044         HWRM_UNLOCK();
4045
4046         return rc;
4047 }
4048
4049 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4050 {
4051         struct bnxt_vnic_info vnic;
4052         uint16_t *vnic_ids;
4053         size_t vnic_id_sz;
4054         int num_vnic_ids, i;
4055         size_t sz;
4056         int rc;
4057
4058         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
4059         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4060                         RTE_CACHE_LINE_SIZE);
4061         if (vnic_ids == NULL)
4062                 return -ENOMEM;
4063
4064         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4065                 rte_mem_lock_page(((char *)vnic_ids) + sz);
4066
4067         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4068         if (rc <= 0)
4069                 goto exit;
4070         num_vnic_ids = rc;
4071
4072         /*
4073          * Loop through to find the default VNIC ID.
4074          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4075          * by sending the hwrm_func_qcfg command to the firmware.
4076          */
4077         for (i = 0; i < num_vnic_ids; i++) {
4078                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4079                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4080                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4081                                         bp->pf.first_vf_id + vf);
4082                 if (rc)
4083                         goto exit;
4084                 if (vnic.func_default) {
4085                         rte_free(vnic_ids);
4086                         return vnic.fw_vnic_id;
4087                 }
4088         }
4089         /* Could not find a default VNIC. */
4090         PMD_DRV_LOG(ERR, "No default VNIC\n");
4091 exit:
4092         rte_free(vnic_ids);
4093         return rc;
4094 }
4095
4096 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4097                          uint16_t dst_id,
4098                          struct bnxt_filter_info *filter)
4099 {
4100         int rc = 0;
4101         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4102         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4103         uint32_t enables = 0;
4104
4105         if (filter->fw_em_filter_id != UINT64_MAX)
4106                 bnxt_hwrm_clear_em_filter(bp, filter);
4107
4108         HWRM_PREP(req, CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4109
4110         req.flags = rte_cpu_to_le_32(filter->flags);
4111
4112         enables = filter->enables |
4113               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4114         req.dst_id = rte_cpu_to_le_16(dst_id);
4115
4116         if (filter->ip_addr_type) {
4117                 req.ip_addr_type = filter->ip_addr_type;
4118                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4119         }
4120         if (enables &
4121             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4122                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4123         if (enables &
4124             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4125                 memcpy(req.src_macaddr, filter->src_macaddr,
4126                        RTE_ETHER_ADDR_LEN);
4127         if (enables &
4128             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4129                 memcpy(req.dst_macaddr, filter->dst_macaddr,
4130                        RTE_ETHER_ADDR_LEN);
4131         if (enables &
4132             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4133                 req.ovlan_vid = filter->l2_ovlan;
4134         if (enables &
4135             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4136                 req.ivlan_vid = filter->l2_ivlan;
4137         if (enables &
4138             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4139                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4140         if (enables &
4141             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4142                 req.ip_protocol = filter->ip_protocol;
4143         if (enables &
4144             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4145                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4146         if (enables &
4147             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4148                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4149         if (enables &
4150             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4151                 req.src_port = rte_cpu_to_be_16(filter->src_port);
4152         if (enables &
4153             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4154                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4155         if (enables &
4156             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4157                 req.mirror_vnic_id = filter->mirror_vnic_id;
4158
4159         req.enables = rte_cpu_to_le_32(enables);
4160
4161         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4162
4163         HWRM_CHECK_RESULT();
4164
4165         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4166         HWRM_UNLOCK();
4167
4168         return rc;
4169 }
4170
4171 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4172 {
4173         int rc = 0;
4174         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4175         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4176
4177         if (filter->fw_em_filter_id == UINT64_MAX)
4178                 return 0;
4179
4180         PMD_DRV_LOG(ERR, "Clear EM filter\n");
4181         HWRM_PREP(req, CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4182
4183         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4184
4185         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4186
4187         HWRM_CHECK_RESULT();
4188         HWRM_UNLOCK();
4189
4190         filter->fw_em_filter_id = UINT64_MAX;
4191         filter->fw_l2_filter_id = UINT64_MAX;
4192
4193         return 0;
4194 }
4195
4196 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4197                          uint16_t dst_id,
4198                          struct bnxt_filter_info *filter)
4199 {
4200         int rc = 0;
4201         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4202         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4203                                                 bp->hwrm_cmd_resp_addr;
4204         uint32_t enables = 0;
4205
4206         if (filter->fw_ntuple_filter_id != UINT64_MAX)
4207                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4208
4209         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4210
4211         req.flags = rte_cpu_to_le_32(filter->flags);
4212
4213         enables = filter->enables |
4214               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4215         req.dst_id = rte_cpu_to_le_16(dst_id);
4216
4217         if (filter->ip_addr_type) {
4218                 req.ip_addr_type = filter->ip_addr_type;
4219                 enables |=
4220                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4221         }
4222         if (enables &
4223             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4224                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4225         if (enables &
4226             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4227                 memcpy(req.src_macaddr, filter->src_macaddr,
4228                        RTE_ETHER_ADDR_LEN);
4229         //if (enables &
4230             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
4231                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
4232                        //RTE_ETHER_ADDR_LEN);
4233         if (enables &
4234             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4235                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4236         if (enables &
4237             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4238                 req.ip_protocol = filter->ip_protocol;
4239         if (enables &
4240             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4241                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4242         if (enables &
4243             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4244                 req.src_ipaddr_mask[0] =
4245                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4246         if (enables &
4247             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4248                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4249         if (enables &
4250             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4251                 req.dst_ipaddr_mask[0] =
4252                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4253         if (enables &
4254             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4255                 req.src_port = rte_cpu_to_le_16(filter->src_port);
4256         if (enables &
4257             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4258                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4259         if (enables &
4260             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4261                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4262         if (enables &
4263             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4264                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4265         if (enables &
4266             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4267                 req.mirror_vnic_id = filter->mirror_vnic_id;
4268
4269         req.enables = rte_cpu_to_le_32(enables);
4270
4271         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4272
4273         HWRM_CHECK_RESULT();
4274
4275         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4276         HWRM_UNLOCK();
4277
4278         return rc;
4279 }
4280
4281 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4282                                 struct bnxt_filter_info *filter)
4283 {
4284         int rc = 0;
4285         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4286         struct hwrm_cfa_ntuple_filter_free_output *resp =
4287                                                 bp->hwrm_cmd_resp_addr;
4288
4289         if (filter->fw_ntuple_filter_id == UINT64_MAX)
4290                 return 0;
4291
4292         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4293
4294         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4295
4296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4297
4298         HWRM_CHECK_RESULT();
4299         HWRM_UNLOCK();
4300
4301         filter->fw_ntuple_filter_id = UINT64_MAX;
4302
4303         return 0;
4304 }
4305
4306 static int
4307 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4308 {
4309         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4310         uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4311         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4312         struct bnxt_rx_queue **rxqs = bp->rx_queues;
4313         uint16_t *ring_tbl = vnic->rss_table;
4314         int nr_ctxs = vnic->num_lb_ctxts;
4315         int max_rings = bp->rx_nr_rings;
4316         int i, j, k, cnt;
4317         int rc = 0;
4318
4319         for (i = 0, k = 0; i < nr_ctxs; i++) {
4320                 struct bnxt_rx_ring_info *rxr;
4321                 struct bnxt_cp_ring_info *cpr;
4322
4323                 HWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4324
4325                 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4326                 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4327                 req.hash_mode_flags = vnic->hash_mode;
4328
4329                 req.ring_grp_tbl_addr =
4330                     rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4331                                      i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4332                                      2 * sizeof(*ring_tbl));
4333                 req.hash_key_tbl_addr =
4334                     rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4335
4336                 req.ring_table_pair_index = i;
4337                 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4338
4339                 for (j = 0; j < 64; j++) {
4340                         uint16_t ring_id;
4341
4342                         /* Find next active ring. */
4343                         for (cnt = 0; cnt < max_rings; cnt++) {
4344                                 if (rx_queue_state[k] !=
4345                                                 RTE_ETH_QUEUE_STATE_STOPPED)
4346                                         break;
4347                                 if (++k == max_rings)
4348                                         k = 0;
4349                         }
4350
4351                         /* Return if no rings are active. */
4352                         if (cnt == max_rings)
4353                                 return 0;
4354
4355                         /* Add rx/cp ring pair to RSS table. */
4356                         rxr = rxqs[k]->rx_ring;
4357                         cpr = rxqs[k]->cp_ring;
4358
4359                         ring_id = rxr->rx_ring_struct->fw_ring_id;
4360                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4361                         ring_id = cpr->cp_ring_struct->fw_ring_id;
4362                         *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4363
4364                         if (++k == max_rings)
4365                                 k = 0;
4366                 }
4367                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4368                                             BNXT_USE_CHIMP_MB);
4369
4370                 HWRM_CHECK_RESULT();
4371                 HWRM_UNLOCK();
4372         }
4373
4374         return rc;
4375 }
4376
4377 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4378 {
4379         unsigned int rss_idx, fw_idx, i;
4380
4381         if (!(vnic->rss_table && vnic->hash_type))
4382                 return 0;
4383
4384         if (BNXT_CHIP_THOR(bp))
4385                 return bnxt_vnic_rss_configure_thor(bp, vnic);
4386
4387         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4388                 return 0;
4389
4390         if (vnic->rss_table && vnic->hash_type) {
4391                 /*
4392                  * Fill the RSS hash & redirection table with
4393                  * ring group ids for all VNICs
4394                  */
4395                 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4396                         rss_idx++, fw_idx++) {
4397                         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4398                                 fw_idx %= bp->rx_cp_nr_rings;
4399                                 if (vnic->fw_grp_ids[fw_idx] !=
4400                                     INVALID_HW_RING_ID)
4401                                         break;
4402                                 fw_idx++;
4403                         }
4404                         if (i == bp->rx_cp_nr_rings)
4405                                 return 0;
4406                         vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4407                 }
4408                 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4409         }
4410
4411         return 0;
4412 }
4413
4414 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4415         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4416 {
4417         uint16_t flags;
4418
4419         req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4420
4421         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4422         req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4423
4424         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4425         req->num_cmpl_dma_aggr_during_int =
4426                 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4427
4428         req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4429
4430         /* min timer set to 1/2 of interrupt timer */
4431         req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4432
4433         /* buf timer set to 1/4 of interrupt timer */
4434         req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4435
4436         req->cmpl_aggr_dma_tmr_during_int =
4437                 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4438
4439         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4440                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4441         req->flags = rte_cpu_to_le_16(flags);
4442 }
4443
4444 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4445                 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4446 {
4447         struct hwrm_ring_aggint_qcaps_input req = {0};
4448         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4449         uint32_t enables;
4450         uint16_t flags;
4451         int rc;
4452
4453         HWRM_PREP(req, RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4454         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4455         HWRM_CHECK_RESULT();
4456
4457         agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4458         agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4459
4460         flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4461                 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4462         agg_req->flags = rte_cpu_to_le_16(flags);
4463         enables =
4464          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4465          HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4466         agg_req->enables = rte_cpu_to_le_32(enables);
4467
4468         HWRM_UNLOCK();
4469         return rc;
4470 }
4471
4472 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4473                         struct bnxt_coal *coal, uint16_t ring_id)
4474 {
4475         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4476         struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4477                                                 bp->hwrm_cmd_resp_addr;
4478         int rc;
4479
4480         /* Set ring coalesce parameters only for 100G NICs */
4481         if (BNXT_CHIP_THOR(bp)) {
4482                 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4483                         return -1;
4484         } else if (bnxt_stratus_device(bp)) {
4485                 bnxt_hwrm_set_coal_params(coal, &req);
4486         } else {
4487                 return 0;
4488         }
4489
4490         HWRM_PREP(req, RING_CMPL_RING_CFG_AGGINT_PARAMS, BNXT_USE_CHIMP_MB);
4491         req.ring_id = rte_cpu_to_le_16(ring_id);
4492         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4493         HWRM_CHECK_RESULT();
4494         HWRM_UNLOCK();
4495         return 0;
4496 }
4497
4498 #define BNXT_RTE_MEMZONE_FLAG  (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4499 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4500 {
4501         struct hwrm_func_backing_store_qcaps_input req = {0};
4502         struct hwrm_func_backing_store_qcaps_output *resp =
4503                 bp->hwrm_cmd_resp_addr;
4504         struct bnxt_ctx_pg_info *ctx_pg;
4505         struct bnxt_ctx_mem_info *ctx;
4506         int total_alloc_len;
4507         int rc, i;
4508
4509         if (!BNXT_CHIP_THOR(bp) ||
4510             bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4511             BNXT_VF(bp) ||
4512             bp->ctx)
4513                 return 0;
4514
4515         HWRM_PREP(req, FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4516         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4517         HWRM_CHECK_RESULT_SILENT();
4518
4519         total_alloc_len = sizeof(*ctx);
4520         ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4521                           RTE_CACHE_LINE_SIZE);
4522         if (!ctx) {
4523                 rc = -ENOMEM;
4524                 goto ctx_err;
4525         }
4526
4527         ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4528                             sizeof(*ctx_pg) * BNXT_MAX_Q,
4529                             RTE_CACHE_LINE_SIZE);
4530         if (!ctx_pg) {
4531                 rc = -ENOMEM;
4532                 goto ctx_err;
4533         }
4534         for (i = 0; i < BNXT_MAX_Q; i++, ctx_pg++)
4535                 ctx->tqm_mem[i] = ctx_pg;
4536
4537         bp->ctx = ctx;
4538         ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4539         ctx->qp_min_qp1_entries =
4540                 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4541         ctx->qp_max_l2_entries =
4542                 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4543         ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4544         ctx->srq_max_l2_entries =
4545                 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4546         ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4547         ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4548         ctx->cq_max_l2_entries =
4549                 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4550         ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4551         ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4552         ctx->vnic_max_vnic_entries =
4553                 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4554         ctx->vnic_max_ring_table_entries =
4555                 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4556         ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4557         ctx->stat_max_entries =
4558                 rte_le_to_cpu_32(resp->stat_max_entries);
4559         ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4560         ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4561         ctx->tqm_min_entries_per_ring =
4562                 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4563         ctx->tqm_max_entries_per_ring =
4564                 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4565         ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4566         if (!ctx->tqm_entries_multiple)
4567                 ctx->tqm_entries_multiple = 1;
4568         ctx->mrav_max_entries =
4569                 rte_le_to_cpu_32(resp->mrav_max_entries);
4570         ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4571         ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4572         ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4573 ctx_err:
4574         HWRM_UNLOCK();
4575         return rc;
4576 }
4577
4578 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4579 {
4580         struct hwrm_func_backing_store_cfg_input req = {0};
4581         struct hwrm_func_backing_store_cfg_output *resp =
4582                 bp->hwrm_cmd_resp_addr;
4583         struct bnxt_ctx_mem_info *ctx = bp->ctx;
4584         struct bnxt_ctx_pg_info *ctx_pg;
4585         uint32_t *num_entries;
4586         uint64_t *pg_dir;
4587         uint8_t *pg_attr;
4588         uint32_t ena;
4589         int i, rc;
4590
4591         if (!ctx)
4592                 return 0;
4593
4594         HWRM_PREP(req, FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4595         req.enables = rte_cpu_to_le_32(enables);
4596
4597         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4598                 ctx_pg = &ctx->qp_mem;
4599                 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4600                 req.qp_num_qp1_entries =
4601                         rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4602                 req.qp_num_l2_entries =
4603                         rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4604                 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4605                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4606                                       &req.qpc_pg_size_qpc_lvl,
4607                                       &req.qpc_page_dir);
4608         }
4609
4610         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4611                 ctx_pg = &ctx->srq_mem;
4612                 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4613                 req.srq_num_l2_entries =
4614                                  rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4615                 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4616                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4617                                       &req.srq_pg_size_srq_lvl,
4618                                       &req.srq_page_dir);
4619         }
4620
4621         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4622                 ctx_pg = &ctx->cq_mem;
4623                 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4624                 req.cq_num_l2_entries =
4625                                 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4626                 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4627                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4628                                       &req.cq_pg_size_cq_lvl,
4629                                       &req.cq_page_dir);
4630         }
4631
4632         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4633                 ctx_pg = &ctx->vnic_mem;
4634                 req.vnic_num_vnic_entries =
4635                         rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4636                 req.vnic_num_ring_table_entries =
4637                         rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4638                 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4639                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4640                                       &req.vnic_pg_size_vnic_lvl,
4641                                       &req.vnic_page_dir);
4642         }
4643
4644         if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4645                 ctx_pg = &ctx->stat_mem;
4646                 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4647                 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4648                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4649                                       &req.stat_pg_size_stat_lvl,
4650                                       &req.stat_page_dir);
4651         }
4652
4653         req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4654         num_entries = &req.tqm_sp_num_entries;
4655         pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4656         pg_dir = &req.tqm_sp_page_dir;
4657         ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4658         for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4659                 if (!(enables & ena))
4660                         continue;
4661
4662                 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4663
4664                 ctx_pg = ctx->tqm_mem[i];
4665                 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4666                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4667         }
4668
4669         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4670         HWRM_CHECK_RESULT();
4671         HWRM_UNLOCK();
4672
4673         return rc;
4674 }
4675
4676 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4677 {
4678         struct hwrm_port_qstats_ext_input req = {0};
4679         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4680         struct bnxt_pf_info *pf = &bp->pf;
4681         int rc;
4682
4683         if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4684               bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4685                 return 0;
4686
4687         HWRM_PREP(req, PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4688
4689         req.port_id = rte_cpu_to_le_16(pf->port_id);
4690         if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4691                 req.tx_stat_host_addr =
4692                         rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4693                 req.tx_stat_size =
4694                         rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4695         }
4696         if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4697                 req.rx_stat_host_addr =
4698                         rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4699                 req.rx_stat_size =
4700                         rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4701         }
4702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4703
4704         if (rc) {
4705                 bp->fw_rx_port_stats_ext_size = 0;
4706                 bp->fw_tx_port_stats_ext_size = 0;
4707         } else {
4708                 bp->fw_rx_port_stats_ext_size =
4709                         rte_le_to_cpu_16(resp->rx_stat_size);
4710                 bp->fw_tx_port_stats_ext_size =
4711                         rte_le_to_cpu_16(resp->tx_stat_size);
4712         }
4713
4714         HWRM_CHECK_RESULT();
4715         HWRM_UNLOCK();
4716
4717         return rc;
4718 }
4719
4720 int
4721 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4722 {
4723         struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4724         struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4725                 bp->hwrm_cmd_resp_addr;
4726         int rc = 0;
4727
4728         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4729         req.tunnel_type = type;
4730         req.dest_fid = bp->fw_fid;
4731         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4732         HWRM_CHECK_RESULT();
4733
4734         HWRM_UNLOCK();
4735
4736         return rc;
4737 }
4738
4739 int
4740 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4741 {
4742         struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4743         struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4744                 bp->hwrm_cmd_resp_addr;
4745         int rc = 0;
4746
4747         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4748         req.tunnel_type = type;
4749         req.dest_fid = bp->fw_fid;
4750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4751         HWRM_CHECK_RESULT();
4752
4753         HWRM_UNLOCK();
4754
4755         return rc;
4756 }
4757
4758 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4759 {
4760         struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4761         struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4762                 bp->hwrm_cmd_resp_addr;
4763         int rc = 0;
4764
4765         HWRM_PREP(req, CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4766         req.src_fid = bp->fw_fid;
4767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4768         HWRM_CHECK_RESULT();
4769
4770         if (type)
4771                 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4772
4773         HWRM_UNLOCK();
4774
4775         return rc;
4776 }
4777
4778 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4779                                    uint16_t *dst_fid)
4780 {
4781         struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4782         struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4783                 bp->hwrm_cmd_resp_addr;
4784         int rc = 0;
4785
4786         HWRM_PREP(req, CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
4787         req.src_fid = bp->fw_fid;
4788         req.tunnel_type = tun_type;
4789         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4790         HWRM_CHECK_RESULT();
4791
4792         if (dst_fid)
4793                 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
4794
4795         PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
4796
4797         HWRM_UNLOCK();
4798
4799         return rc;
4800 }
4801
4802 int bnxt_hwrm_set_mac(struct bnxt *bp)
4803 {
4804         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4805         struct hwrm_func_vf_cfg_input req = {0};
4806         int rc = 0;
4807
4808         if (!BNXT_VF(bp))
4809                 return 0;
4810
4811         HWRM_PREP(req, FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4812
4813         req.enables =
4814                 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
4815         memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4816
4817         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4818
4819         HWRM_CHECK_RESULT();
4820
4821         memcpy(bp->dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
4822         HWRM_UNLOCK();
4823
4824         return rc;
4825 }
4826
4827 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
4828 {
4829         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
4830         struct hwrm_func_drv_if_change_input req = {0};
4831         uint32_t flags;
4832         int rc;
4833
4834         if (!(bp->flags & BNXT_FLAG_FW_CAP_IF_CHANGE))
4835                 return 0;
4836
4837         /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
4838          * If we issue FUNC_DRV_IF_CHANGE with flags down before
4839          * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
4840          */
4841         if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
4842                 return 0;
4843
4844         HWRM_PREP(req, FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
4845
4846         if (up)
4847                 req.flags =
4848                 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
4849
4850         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4851
4852         HWRM_CHECK_RESULT();
4853         flags = rte_le_to_cpu_32(resp->flags);
4854         HWRM_UNLOCK();
4855
4856         if (!up)
4857                 return 0;
4858
4859         if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
4860                 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
4861                 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
4862         }
4863
4864         return 0;
4865 }
4866
4867 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
4868 {
4869         struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4870         struct bnxt_error_recovery_info *info = bp->recovery_info;
4871         struct hwrm_error_recovery_qcfg_input req = {0};
4872         uint32_t flags = 0;
4873         unsigned int i;
4874         int rc;
4875
4876         /* Older FW does not have error recovery support */
4877         if (!(bp->flags & BNXT_FLAG_FW_CAP_ERROR_RECOVERY))
4878                 return 0;
4879
4880         if (!info) {
4881                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4882                                    sizeof(*info), 0);
4883                 bp->recovery_info = info;
4884                 if (info == NULL)
4885                         return -ENOMEM;
4886         } else {
4887                 memset(info, 0, sizeof(*info));
4888         }
4889
4890         HWRM_PREP(req, ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
4891
4892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4893
4894         HWRM_CHECK_RESULT();
4895
4896         flags = rte_le_to_cpu_32(resp->flags);
4897         if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
4898                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
4899         else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
4900                 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
4901
4902         if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
4903             !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
4904                 rc = -EINVAL;
4905                 goto err;
4906         }
4907
4908         /* FW returned values are in units of 100msec */
4909         info->driver_polling_freq =
4910                 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
4911         info->master_func_wait_period =
4912                 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
4913         info->normal_func_wait_period =
4914                 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
4915         info->master_func_wait_period_after_reset =
4916                 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
4917         info->max_bailout_time_after_reset =
4918                 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
4919         info->status_regs[BNXT_FW_STATUS_REG] =
4920                 rte_le_to_cpu_32(resp->fw_health_status_reg);
4921         info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
4922                 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
4923         info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
4924                 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
4925         info->status_regs[BNXT_FW_RESET_INPROG_REG] =
4926                 rte_le_to_cpu_32(resp->reset_inprogress_reg);
4927         info->reg_array_cnt =
4928                 rte_le_to_cpu_32(resp->reg_array_cnt);
4929
4930         if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
4931                 rc = -EINVAL;
4932                 goto err;
4933         }
4934
4935         for (i = 0; i < info->reg_array_cnt; i++) {
4936                 info->reset_reg[i] =
4937                         rte_le_to_cpu_32(resp->reset_reg[i]);
4938                 info->reset_reg_val[i] =
4939                         rte_le_to_cpu_32(resp->reset_reg_val[i]);
4940                 info->delay_after_reset[i] =
4941                         resp->delay_after_reset[i];
4942         }
4943 err:
4944         HWRM_UNLOCK();
4945
4946         /* Map the FW status registers */
4947         if (!rc)
4948                 rc = bnxt_map_fw_health_status_regs(bp);
4949
4950         if (rc) {
4951                 rte_free(bp->recovery_info);
4952                 bp->recovery_info = NULL;
4953         }
4954         return rc;
4955 }
4956
4957 int bnxt_hwrm_fw_reset(struct bnxt *bp)
4958 {
4959         struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
4960         struct hwrm_fw_reset_input req = {0};
4961         int rc;
4962
4963         if (!BNXT_PF(bp))
4964                 return -EOPNOTSUPP;
4965
4966         HWRM_PREP(req, FW_RESET, BNXT_USE_KONG(bp));
4967
4968         req.embedded_proc_type =
4969                 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
4970         req.selfrst_status =
4971                 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
4972         req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
4973
4974         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4975                                     BNXT_USE_KONG(bp));
4976
4977         HWRM_CHECK_RESULT();
4978         HWRM_UNLOCK();
4979
4980         return rc;
4981 }
4982
4983 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
4984 {
4985         struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
4986         struct hwrm_port_ts_query_input req = {0};
4987         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4988         uint32_t flags = 0;
4989         int rc;
4990
4991         if (!ptp)
4992                 return 0;
4993
4994         HWRM_PREP(req, PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
4995
4996         switch (path) {
4997         case BNXT_PTP_FLAGS_PATH_TX:
4998                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
4999                 break;
5000         case BNXT_PTP_FLAGS_PATH_RX:
5001                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5002                 break;
5003         case BNXT_PTP_FLAGS_CURRENT_TIME:
5004                 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5005                 break;
5006         }
5007
5008         req.flags = rte_cpu_to_le_32(flags);
5009         req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
5010
5011         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5012
5013         HWRM_CHECK_RESULT();
5014
5015         if (timestamp) {
5016                 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5017                 *timestamp |=
5018                         (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5019         }
5020         HWRM_UNLOCK();
5021
5022         return rc;
5023 }
5024
5025 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5026 {
5027         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5028                                         bp->hwrm_cmd_resp_addr;
5029         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5030         uint32_t flags = 0;
5031         int rc = 0;
5032
5033         if (!(bp->flags & BNXT_FLAG_ADV_FLOW_MGMT))
5034                 return rc;
5035
5036         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5037                 PMD_DRV_LOG(DEBUG,
5038                             "Not a PF or trusted VF. Command not supported\n");
5039                 return 0;
5040         }
5041
5042         HWRM_PREP(req, CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5043         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5044
5045         HWRM_CHECK_RESULT();
5046         flags = rte_le_to_cpu_32(resp->flags);
5047         HWRM_UNLOCK();
5048
5049         if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5050                 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5051                 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5052         }
5053
5054         return rc;
5055 }